Markus Fröschle 7e2181fbc9 improved timing, added timing constraints, got rid of CLK_33M ...

Design compiles and runs, but still has issues with different screen resolutions and video clocks

2015-09-23 09:49:05 +00:00

FPGA_Quartus_13.1

improved timing, added timing constraints, got rid of CLK_33M

2015-09-23 09:49:05 +00:00

Description

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10 MiB

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VHDL 83.4%

Verilog 13.1%

PHP 2.1%

Tcl 0.6%

Assembly 0.4%

Other 0.4%