forked from Firebee/FPGA_Config
7e2181fbc9
Design compiles and runs, but still has issues with different screen resolutions and video clocks
8 lines
526 B
Plaintext
8 lines
526 B
Plaintext
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
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set_global_assignment -name IP_TOOL_VERSION "13.1"
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.cmp"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"]
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