forked from Firebee/FPGA_Config
7e2181fbc9
Design compiles and runs, but still has issues with different screen resolutions and video clocks
27 lines
849 B
PHP
27 lines
849 B
PHP
--Copyright (C) 1991-2014 Altera Corporation
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--Your use of Altera Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files from any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Altera Program License
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--Subscription Agreement, Altera MegaCore Function License
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--Agreement, or other applicable license agreement, including,
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--without limitation, that your use is for the sole purpose of
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--programming logic devices manufactured by Altera and sold by
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--Altera or its authorized distributors. Please refer to the
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--applicable agreement for further details.
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FUNCTION altpll1
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(
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inclk0
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)
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RETURNS (
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c0,
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c1,
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c2,
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locked
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);
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