FPGA_Config

Author	SHA1	Message	Date
Markus Fröschle	e2ab4af020	get rid of BUFFER parameters	2016-01-18 18:32:50 +00:00
Markus Fröschle	652dd1c124	hold time fix test	2016-01-18 18:15:02 +00:00
Markus Fröschle	e623e668c2	more flexbus_register work	2016-01-18 07:40:08 +00:00
Markus Fröschle	47f6884bbe	add more functionality	2016-01-17 21:45:53 +00:00
Markus Fröschle	b9c3ec9366	modify indent	2016-01-17 20:39:25 +00:00
Markus Fröschle	21a4a80fb7	start of flexbus_register implementation to simplify that	2016-01-17 20:28:18 +00:00
Markus Fröschle	ddad975d6f	fix 13MHz clock sdc	2016-01-17 08:43:20 +00:00
Markus Fröschle	91791dfb5d	do not automatically insert delay chains	2016-01-16 22:11:51 +00:00
Markus Fröschle	58a69ffc5f	reformat	2016-01-16 22:04:05 +00:00
Markus Fröschle	7bf4d912a0	fix timing	2016-01-16 21:38:17 +00:00
Markus Fröschle	0fe61bedef	fix output delay	2016-01-15 17:38:29 +00:00
Markus Fröschle	11bd410c15	simplify processes	2016-01-15 08:37:40 +00:00
Markus Fröschle	f11629ac29	fix video base address and video counter register	2016-01-14 22:02:44 +00:00
Markus Fröschle	c4d56bb652	reformat	2016-01-14 16:49:11 +00:00
Markus Fröschle	b7a34c8abf	reformat	2016-01-14 07:17:08 +00:00
Markus Fröschle	69c107ef32	remove unused connections	2016-01-14 06:45:15 +00:00
Markus Fröschle	52e1b53192	formatting	2016-01-14 06:44:52 +00:00
Markus Fröschle	4ed4616156	remove unused generated signals	2016-01-13 16:43:54 +00:00
Markus Fröschle	97a48bf636	reactivated delay chain	2016-01-13 15:04:24 +00:00
Markus Fröschle	fd5abf8b4a	reformat	2016-01-13 13:23:46 +00:00
Markus Fröschle	90c0f7758d	remove AHDL files	2016-01-13 12:54:00 +00:00
Markus Fröschle	5183d08d60	finish conversion to vhdl	2016-01-13 12:53:03 +00:00
Markus Fröschle	79a14e2a70	reformat internal signals	2016-01-13 07:27:57 +00:00
Markus Fröschle	621e2267a7	renamed pixel_clk_i	2016-01-13 07:16:24 +00:00
Markus Fröschle	c8b693d755	add file	2016-01-12 17:11:58 +00:00
Markus Fröschle	29df555945	reformat	2016-01-12 17:11:07 +00:00
Markus Fröschle	f1f893bc44	fix ports	2016-01-12 17:10:19 +00:00
Markus Fröschle	87100a7d62	fix formatting	2016-01-12 08:00:20 +00:00
Markus Fröschle	703d95ee75	fix wire loop still works (kind of) - pixel errors in MiNT, does not boot (no picture) with "pure" EmuTOS?	2016-01-12 07:58:07 +00:00
Markus Fröschle	7d2430a62c	reformat converted VHDL	2016-01-12 07:14:33 +00:00
Markus Fröschle	3ec978dff5	translate DDR_CTR to vhd	2016-01-11 17:55:18 +00:00
Markus Fröschle	35d70dc637	fix min instead of max	2016-01-11 17:07:35 +00:00
Markus Fröschle	b35e12b329	add more DDR clk signals to sdc	2016-01-11 17:05:39 +00:00
Markus Fröschle	476825a3ba	translate interrupt_controller to vhd	2016-01-11 16:11:04 +00:00
Markus Fröschle	98a362dc90	replace video.bdf with video.vhd	2016-01-11 08:43:42 +00:00
Markus Fröschle	f6aa56ac7a	convert firebee1.bdf to vhdl	2016-01-11 08:18:06 +00:00
Markus Fröschle	b3edfcd457	reformat	2016-01-11 07:13:36 +00:00
Markus Fröschle	9cfde26eef	modify settings	2016-01-10 19:05:15 +00:00
Markus Fröschle	7296970eb6	rename Video.bdf to lower case	2016-01-10 10:24:30 +00:00
Markus Fröschle	f887503255	rename to make it usable as alternative in Quartus	2016-01-10 07:44:20 +00:00
Markus Fröschle	f94b5f265e	remove delay chains	2016-01-09 21:36:02 +00:00
Markus Fröschle	7bdeac0860	rename video registers to their Falcon names	2016-01-09 18:49:18 +00:00
Markus Fröschle	5c933580a2	fix ACP web address	2015-11-18 06:41:49 +00:00
Markus Fröschle	fc8034d93b	patch with Fredi's lp fix (and others)	2015-10-26 06:48:18 +00:00
Markus Fröschle	1c661c8052	formatting	2015-10-18 19:33:25 +00:00
Markus Fröschle	13032a8635	reformat	2015-10-18 19:27:57 +00:00
Markus Fröschle	56adcdd218	added another false path to fix timing	2015-10-18 01:02:05 +00:00
Markus Fröschle	8b7fe5f731	fix timing (set_false_path was missing)	2015-10-18 00:57:04 +00:00
Markus Fröschle	7f4b30f483	changed component name to lower case	2015-10-17 16:10:06 +00:00
Markus Fröschle	602c20bb30	add missing project file	2015-10-17 10:58:27 +00:00

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127 Commits