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patch with Fredi's lp fix (and others)

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This commit is contained in:
Markus Fröschle
2015-10-26 06:48:18 +00:00
parent 1c661c8052
commit fc8034d93b
43 changed files with 5765 additions and 5956 deletions
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411
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
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@@ -115,7 +115,7 @@ ENTITY falconio_sdcard_ide_cf IS
nCF_CS0 : OUT std_logic;
nIDE_RD : INOUT std_logic;
nIDE_WR : INOUT std_logic;
AMKB_TX : OUT std_logic;
AMKB_TX : buffer std_logic;
IDE_RES : OUT std_logic;
DTR : OUT std_logic;
RTS : OUT std_logic;
@@ -132,6 +132,7 @@ ENTITY falconio_sdcard_ide_cf IS
DMA_DRQ : OUT std_logic;
FB_AD : INOUT std_logic_vector(31 DOWNTO 0);
LP_D : INOUT std_logic_vector(7 DOWNTO 0);
SND_A : INOUT std_logic_vector(7 downto 0);
ACSI_D : INOUT std_logic_vector(7 DOWNTO 0);
SCSI_D : INOUT std_logic_vector(7 DOWNTO 0);
SCSI_PAR : INOUT std_logic;
@@ -142,13 +143,12 @@ ENTITY falconio_sdcard_ide_cf IS
SD_CDM_D1 : INOUT std_logic
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END falconio_sdcard_ide_cf;
-- Architecture Body
ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS
ARCHITECTURE rtl OF FalconIO_SDCard_IDE_CF IS
-- system
SIGNAL SYS_CLK : std_logic;
SIGNAL RESETn : std_logic;
@@ -156,12 +156,15 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS
SIGNAL FB_B1 : std_logic; -- LOWER BYT BEI 16BIT BUS
SIGNAL BYT : std_logic; -- WENN BYT -> 1
SIGNAL LONG : std_logic; -- WENN -> 1
signal FB_ADI : STD_LOGIC_VECTOR(15 downto 0); -- gespeicherte writedaten
signal nResetatio : STD_LOGIC; -- reset atari bausteine
-- KEYBOARD MIDI
SIGNAL ACIA_CS_I : std_logic;
SIGNAL IRQ_KEYBDn : std_logic;
SIGNAL IRQ_MIDIn : std_logic;
SIGNAL KEYB_RxD : std_logic;
SIGNAL AMKB_REG : std_logic_vector(4 DOWNTO 0);
signal AMKB_REG : STD_LOGIC_VECTOR(3 downto 0);
signal AMKB_TX_sync : std_logic;
SIGNAL MIDI_OUT : std_logic;
SIGNAL DATA_OUT_ACIA_I : std_logic_vector(7 DOWNTO 0);
SIGNAL DATA_OUT_ACIA_II : std_logic_vector(7 DOWNTO 0);
@@ -169,8 +172,8 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS
SIGNAL MFP_CS : std_logic;
SIGNAL MFP_INTACK : std_logic;
SIGNAL LDS : std_logic;
signal acia_irq : STD_LOGIC;
SIGNAL DTACK_OUT_MFPn : std_logic;
SIGNAL IRQ_ACIAn : std_logic;
SIGNAL DINTn : std_logic;
SIGNAL DATA_OUT_MFP : std_logic_vector(7 DOWNTO 0);
SIGNAL TDO : std_logic;
@@ -180,7 +183,22 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS
SIGNAL SNDIR_I : std_logic;
SIGNAL LP_DIR_X : std_logic;
SIGNAL DA_OUT_X : std_logic_vector(7 DOWNTO 0);
signal SND_A_X : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL LP_D_X : std_logic_vector(7 DOWNTO 0);
signal nLP_STR : STD_LOGIC;
-- DMA SOUND
signal dma_snd_cs : STD_LOGIC;
signal sndmactl : STD_LOGIC_VECTOR(7 downto 0);
signal sndbashi : STD_LOGIC_VECTOR(7 downto 0);
signal sndbasmi : STD_LOGIC_VECTOR(7 downto 0);
signal sndbaslo : STD_LOGIC_VECTOR(7 downto 0);
signal sndadrhi : STD_LOGIC_VECTOR(7 downto 0);
signal sndadrmi : STD_LOGIC_VECTOR(7 downto 0);
signal sndadrlo : STD_LOGIC_VECTOR(7 downto 0);
signal sndendhi : STD_LOGIC_VECTOR(7 downto 0);
signal sndendmi : STD_LOGIC_VECTOR(7 downto 0);
signal sndendlo : STD_LOGIC_VECTOR(7 downto 0);
signal sndmode : STD_LOGIC_VECTOR(7 downto 0);
-- DIV
SIGNAL SUB_BUS : std_logic; -- SUB BUS MIT ROM-PORT, CF UND IDE
SIGNAL ROM_CS : std_logic;
@@ -228,9 +246,7 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS
SIGNAL WRF_RDE : std_logic;
SIGNAL WRF_WRE : std_logic;
SIGNAL nFDC_WR : std_logic;
TYPE FCF_STATES IS (FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7);
SIGNAL FCF_STATE : FCF_STATES;
SIGNAL NEXT_FCF_STATE : FCF_STATES;
SIGNAL DMA_REQ : std_logic;
@@ -241,7 +257,6 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS
SIGNAL DMA_ACTIV : std_logic;
SIGNAL DMA_ACTIV_NEW : std_logic;
SIGNAL FDC_OUT : std_logic_vector(7 DOWNTO 0);
-- SCSI
SIGNAL SCSI_CS : std_logic;
SIGNAL SCSI_CSn : std_logic;
@@ -259,7 +274,6 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS
SIGNAL BSY_EN : std_logic;
SIGNAL SEL_OUTn : std_logic;
SIGNAL SEL_EN : std_logic;
-- IDE
SIGNAL nnIDE_RES : std_logic;
SIGNAL IDE_CF_CS : std_logic;
@@ -269,7 +283,8 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS
type CMD_STATES is( IDLE, T1, T6, T7);
SIGNAL CMD_STATE : CMD_STATES;
SIGNAL NEXT_CMD_STATE : CMD_STATES;
-- Paddle
SIGNAL paddle_cs : std_logic;
BEGIN
LONG <= '1' WHEN FB_SIZE1 = '0' AND FB_SIZE0 = '0' ELSE '0';
@@ -277,23 +292,34 @@ BEGIN
FB_B0 <= '1' WHEN FB_ADR(0) = '0' OR BYT = '0' ELSE '0';
FB_B1 <= '1' WHEN FB_ADR(0) = '1' OR BYT = '0' ELSE '0';
FALCON_IO_TA <= '1' WHEN SNDCS = '1' OR DTACK_OUT_MFPn = '0' OR ACIA_CS_I = '1' OR DMA_MODUS_CS ='1'
OR DMA_ADR_CS = '1' OR DMA_DIRM_CS = '1' OR DMA_BYT_CNT_CS = '1' OR FCF_CS = '1' OR IDE_CF_TA = '1' ELSE '0';
FALCON_IO_TA <= '1' when ACIA_CS_I = '1' or DTACK_OUT_MFPn = '0' or DMA_MODUS_CS ='1' or dma_snd_cs = '1' or paddle_cs = '1'
or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';--SNDCS = '1' or
SUB_BUS <= '1' WHEN nFB_WR = '1' AND ROM_CS = '1' ELSE
'1' WHEN nFB_WR = '1' AND IDE_CF_CS = '1' ELSE
'1' WHEN nFB_WR = '0' AND nIDE_WR = '0' ELSE '0';
nRP_UDS <= '0' WHEN SUB_BUS = '1' AND FB_B0 = '1' ELSE '1';
nRP_LDS <= '0' WHEN SUB_BUS = '1' AND FB_B1 = '1' ELSE '1';
nRP_UDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B0 = '1' else '1';
nRP_LDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B1 = '1' else '1';
nDREQ0 <= '0';
-- input daten halten
p_hold_input_data : PROCESS(MAIN_CLK, nFB_WR, FB_AD(31 DOWNTO 16), FB_ADI(15 DOWNTO 0))
BEGIN
IF rising_edge(MAIN_CLK) THEN
IF nFB_WR = '0' THEN
FB_ADI <= FB_AD(31 downto 16);
ELSE
FB_ADI <= FB_ADI;
END IF;
ELSE
FB_ADI <= FB_ADI;
END IF;
END PROCESS;
----------------------------------------------------------------------------
-- SD
----------------------------------------------------------------------------
SD_CLK <= 'Z';
SD_CD_DATA3 <= 'Z';
SD_CDM_D1 <= 'Z';
----------------------------------------------------------------------------
-- IDE
----------------------------------------------------------------------------
@@ -353,24 +379,19 @@ BEGIN
IDE_RES <= NOT nnIDE_RES AND nRSTO;
IDE_CF_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 7) = x"0" ELSE '0'; -- FFF0'0000/80
nCF_CS0 <= '0' WHEN ACP_CONF(31) = '0' AND FB_ADR(19 DOWNTO 5) = x"0" ELSE -- FFFO'0000-FFF0'001F
'0' WHEN ACP_CONF(31) = '1' AND FB_ADR(19 DOWNTO 5) = x"2" ELSE '1'; -- FFFO'0040-FFF0'005F
nCF_CS1 <= '0' WHEN ACP_CONF(31) = '0' AND FB_ADR(19 DOWNTO 5) = x"1" ELSE -- FFF0'0020-FFF0'003F
'0' WHEN ACP_CONF(31) = '1' AND FB_ADR(19 DOWNTO 5) = x"3" ELSE '1'; -- FFFO'0060-FFF0'007F
nIDE_CS0 <= '0' WHEN ACP_CONF(30) = '0' AND FB_ADR(19 DOWNTO 5) = x"2" ELSE -- FFF0'0040-FFF0'005F
'0' WHEN ACP_CONF(30) = '1' AND FB_ADR(19 DOWNTO 5) = x"0" ELSE '1'; -- FFFO'0000-FFF0'001F
nIDE_CS1 <= '0' WHEN ACP_CONF(30) = '0' AND FB_ADR(19 DOWNTO 5) = x"3" ELSE -- FFF0'0060-FFF0'007F
'0' WHEN ACP_CONF(30) = '1' AND FB_ADR(19 DOWNTO 5) = x"1" ELSE '1'; -- FFFO'0020-FFF0'003F
-----------------------------------------------------------------------------------------------------------------------------------------
-- ACSI, SCSI UND FLOPPY WD1772
-------------------------------------------------------------------------------------------------------------------------------------------
-- daten read fifo
i_data_read_fifo: dcfifo0
RDF: dcfifo0
PORT MAP(
aclr => CLR_FIFO,
data => RDF_DIN,
@@ -381,16 +402,15 @@ BEGIN
q => RDF_DOUT,
wrusedw => RDF_AZ
);
FCF_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"0020110" AND LONG = '1' ELSE '0'; -- F002'0110 LONG ONLY
FCF_APH <= '1' WHEN FB_ALE = '1' AND FB_AD(31 DOWNTO 0) = x"F0020110" AND LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY
RDF_RDE <= '1' WHEN FCF_APH = '1' AND nFB_WR = '1' ELSE '0'; -- AKTIVIEREN IN ADRESSPHASE
FB_AD <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' and nFB_OE = '0'
ELSE (OTHERS => 'Z');
FB_AD <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
RDF_DIN <= CD_OUT_FDC WHEN DMA_MODUS(7) = '1' ELSE SCSI_DOUT;
-- daten write fifo
i_data_write_fifo: dcfifo1
WRF: dcfifo1
PORT MAP(
aclr => CLR_FIFO,
data => FB_AD(7 DOWNTO 0) & FB_AD(15 DOWNTO 8) & FB_AD(23 DOWNTO 16) & FB_AD(31 DOWNTO 24),
@@ -401,14 +421,14 @@ BEGIN
q => WRF_DOUT,
rdusedw => WRF_AZ
);
CD_IN_FDC <= WRF_DOUT WHEN DMA_ACTIV = '1' AND DMA_MODUS(8) = '1' ELSE FB_AD(23 DOWNTO 16); -- BEI DMA WRITE <-FIFO SONST <-FB
CD_IN_FDC <= WRF_DOUT WHEN DMA_ACTIV = '1' and DMA_MODUS(8) = '1' ELSE FB_ADI(7 DOWNTO 0); -- BEI DMA WRITE <-FIFO SONST <-FB
DMA_AZ_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"002010C" ELSE '0'; -- F002'010C LONG
FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' and nFB_OE = '0'
ELSE (OTHERS => 'Z');
DMA_DRQ_Q <= '1' WHEN DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' ELSE '0';
-- FIFO WRITE: GENAU 1 MAIN_CLK -------------------------------------------------------------------------
PROCESS(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH)
p_fifo_write : PROCESS(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH)
BEGIN
IF nRSTO = '0' THEN
WRF_WRE <= '0';
@@ -530,7 +550,7 @@ BEGIN
i_fdc : WF1772IP_TOP_SOC
PORT MAP(
CLK => FDC_CLK,
RESETn => nRSTO,
RESETn => nResetatio,
CSn => FDCS_In,
RWn => nFDC_WR,
A1 => CA2,
@@ -552,25 +572,20 @@ BEGIN
DRQ => DMA_DRQ_I,
INTRQ => FDINT
);
DMA_DATEN_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C302" ELSE '0'; -- F8604/2
DMA_MODUS_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C303" ELSE '0'; -- F8606/2
WDC_BSL_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C307" ELSE '0'; -- F860E/2
HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0);
nFDC_WR <= NOT DMA_MODUS(8) WHEN DMA_ACTIV = '1' ELSE nFB_WR;
nFDC_WR <= (not DMA_MODUS(8)) WHEN DMA_ACTIV = '1' ELSE nFB_WR;
CA0 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(0);
CA1 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(1);
CA2 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(2);
FB_AD(23 DOWNTO 16) <= "0000" & (NOT DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD WHEN WDC_BSL_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(31 DOWNTO 24) <= "00000000" WHEN DMA_DATEN_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else (OTHERS => 'Z');
FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(23 DOWNTO 16) <= FDC_OUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "00" AND nFB_OE = '0' ELSE
SCSI_DOUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "01" AND nFB_OE = '0' ELSE
DMA_BYT_CNT(16 DOWNTO 9) WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4) = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
--- WDC BSL REGISTER -------------------------------------------------------
PROCESS(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1)
BEGIN
@@ -584,7 +599,6 @@ BEGIN
END IF;
END IF;
END PROCESS;
--- DMA MODUS REGISTER -------------------------------------------------------
PROCESS(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1)
BEGIN
@@ -605,16 +619,15 @@ BEGIN
DMA_MODUS <= DMA_MODUS;
END IF;
END PROCESS;
-- BYT COUNTER, SECTOR COUNTER ----------------------------------------------------
PROCESS(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO)
BEGIN
IF nRSTO = '0' OR CLR_FIFO = '1' THEN
DMA_BYT_CNT <= x"00000000";
ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_DATEN_CS = '1' AND nFB_WR = '0' AND DMA_MODUS(4) = '1' AND FB_B1 = '1' THEN
DMA_BYT_CNT(31 DOWNTO 17) <= (OTHERS => 'Z');
DMA_BYT_CNT(31 downto 17) <= "000000000000000";
DMA_BYT_CNT(16 DOWNTO 9) <= FB_AD(23 DOWNTO 16);
DMA_BYT_CNT(8 DOWNTO 0) <= (OTHERS => 'Z');
DMA_BYT_CNT(8 downto 0) <= "000000000";
ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_BYT_CNT_CS = '1' THEN
DMA_BYT_CNT <= FB_AD;
ELSE
@@ -622,15 +635,13 @@ BEGIN
END IF;
END PROCESS;
--------------------------------------------------------------------
FB_AD(31 DOWNTO 16) <= "0000000000000" & DMA_STATUS WHEN DMA_MODUS_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
DMA_STATUS(0) <= '1'; -- DMA OK
DMA_STATUS(1) <= '1' WHEN DMA_BYT_CNT /= 0 AND DMA_BYT_CNT(31) = '0' ELSE '0'; -- WENN byts UND NICHT MINUS
DMA_STATUS(2) <= '0' WHEN DMA_DRQ_I = '1' OR SCSI_DRQ = '1' ELSE '0';
DMA_DRQQ <= '1' WHEN DMA_STATUS(1) = '1' AND DMA_MODUS(8) = '0' AND RDF_AZ > 15 AND DMA_MODUS(6) = '0' ELSE
'1' WHEN DMA_STATUS(1) = '1' AND DMA_MODUS(8) = '1' AND WRF_AZ < 512 AND DMA_MODUS(6) = '0' ELSE '0';
DMA_DRQ <= '1' WHEN DMA_DRQ_REG = "11" AND DMA_MODUS(6) = '0' ELSE '0';
-- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------
PROCESS(FDC_CLK, nRSTO, DMA_DRQ_REG)
BEGIN
@@ -643,7 +654,6 @@ BEGIN
DMA_DRQ_REG <= DMA_DRQ_REG;
END IF;
END PROCESS;
-- DMA ADRESSE ------------------------------------------------------
PROCESS(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS)
BEGIN
@@ -655,7 +665,6 @@ BEGIN
DMA_TOP <= DMA_TOP;
END IF;
END PROCESS;
PROCESS(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS)
BEGIN
IF nRSTO = '0' THEN
@@ -666,7 +675,6 @@ BEGIN
DMA_HIGH <= DMA_HIGH;
END IF;
END PROCESS;
PROCESS(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR)
BEGIN
DMA_MID <= DMA_MID;
@@ -680,7 +688,6 @@ BEGIN
END IF;
END IF;
END PROCESS;
PROCESS(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR)
BEGIN
DMA_LOW <= DMA_LOW;
@@ -694,29 +701,26 @@ BEGIN
END IF;
END IF;
END PROCESS;
--------------------------------------------------------------------------------------------
DMA_TOP_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C304" AND FB_B0 = '1' ELSE '0'; -- F8608/2
DMA_HIGH_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C304" AND FB_B1 = '1' ELSE '0'; -- F8609/2
DMA_MID_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C305" AND FB_B1 = '1' ELSE '0'; -- F860B/2
DMA_LOW_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C306" AND FB_B1 = '1' ELSE '0'; -- F860D/2
FB_AD(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
-- DIRECTZUGRIFF
DMA_DIRM_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20100" ELSE '0'; -- F002'0100 WORD
DMA_ADR_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20104" ELSE '0'; -- F002'0104 LONG
DMA_BYT_CNT_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20108" ELSE '0'; -- F002'0108 LONG
FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW WHEN DMA_ADR_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
-- DMA RW TOGGLE ------------------------------------------
PROCESS(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD)
BEGIN
IF nRSTO = '0' THEN
@@ -727,20 +731,18 @@ BEGIN
DMA_DIR_OLD <= DMA_DIR_OLD;
END IF;
END PROCESS;
CLR_FIFO <= DMA_MODUS(8) XOR DMA_DIR_OLD;
-- SCSI ----------------------------------------------------------------------------------
i_scsi : WF5380_TOP_SOC
PORT MAP(
CLK => FDC_CLK,
RESETn => nRSTO,
RESETn => nResetatio,
ADR => CA2 & CA1 & CA0,
DATA_IN => CD_IN_FDC,
DATA_OUT => SCSI_DOUT,
--DATA_EN : out bit;
-- Bus and DMA controls:
CSn => '1', --SCSI_CSn, ABGESCHALTET
CSn => SCSI_CSn,
RDn => (not nFDC_WR) or (not SCSI_CS),
WRn => nFDC_WR or (not SCSI_CS),
EOPn => '1',
@@ -783,21 +785,21 @@ BEGIN
-- MSG_OUTn => MSG_OUTn,
-- MSG_EN => MSG_EN
);
-- SCSI ACSI ---------------------------------------------------------------
SCSI_D <= DB_OUTn WHEN DB_EN = '1' ELSE (OTHERS => 'Z');
SCSI_DIR <= '1'; --'0' WHEN DB_EN = '1' ELSE '1'; --ABGESCHALTET
SCSI_D <= "ZZZZZZZZ"; --DB_OUTn when DB_EN = '1' else "ZZZZZZZZ";
SCSI_DIR <= '1';-- when DB_EN = '1' else '1';
SCSI_PAR <= DBP_OUTn WHEN DBP_EN = '1' ELSE 'Z';
nSCSI_RST <= RST_OUTn WHEN RST_EN = '1' ELSE 'Z';
nSCSI_BUSY <= BSY_OUTn WHEN BSY_EN = '1' ELSE 'Z';
nSCSI_SEL <= SEL_OUTn WHEN SEL_EN = '1' ELSE 'Z';
nSCSI_RST <= 'Z';--RST_OUTn when RST_EN = '1' else 'Z';
nSCSI_BUSY <= 'Z';--BSY_OUTn when BSY_EN = '1' else 'Z';
nSCSI_SEL <= 'Z';--SEL_OUTn when SEL_EN = '1' else 'Z';
ACSI_DIR <= '0';
ACSI_D <= (OTHERS => 'Z');
ACSI_D <= "ZZZZZZZZ";
nACSI_CS <= '1';
ACSI_A1 <= CA1;
nACSI_RESET <= nRSTO;
nACSI_ACK <= '1';
nResetatio <= '0' when nRSTO = '0' or ACP_CONF(24) = '1' else '1';
----------------------------------------------------------------------------
-- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns
@@ -806,14 +808,13 @@ BEGIN
nROM4 <= '0' WHEN ROM_CS = '1' AND FB_ADR(16) = '0' ELSE '1';
nROM3 <= '0' WHEN ROM_CS = '1' AND FB_ADR(16) = '1' ELSE '1';
----------------------------------------------------------------------------
-- ACIA KEYBOARD
----------------------------------------------------------------------------
i_acia_keyboard : WF6850IP_TOP_SOC
PORT MAP(
CLK => MAIN_CLK,
RESETn => nRSTO,
RESETn => nResetatio,
CS2n => FB_ADR(2),
CS1 => '1',
@@ -822,7 +823,7 @@ BEGIN
RWn => nFB_WR,
RS => FB_ADR(1),
DATA_IN => FB_AD(31 DOWNTO 24),
DATA_IN => FB_ADI(15 downto 8),
DATA_OUT => DATA_OUT_ACIA_I,
-- DATA_EN => DATA_EN_ACIA_I,
@@ -834,43 +835,48 @@ BEGIN
DCDn => '0',
IRQn => IRQ_KEYBDn,
TXDATA => AMKB_TX
TXDATA => AMKB_TX_sync
--RTSn => -- Not used.
);
ACIA_CS_I <= '1' WHEN nFB_CS1 = '0'AND FB_ADR(19 DOWNTO 3) = x"1FF80" ELSE '0'; -- FFC00-FFC07 FFC00/8
KEYB_RxD <= '1' WHEN AMKB_REG(3) = '1' OR PIC_AMKB_RX = '0' ELSE '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL
FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_I WHEN ACIA_CS_I = '1' AND FB_ADR(2) = '0' AND nFB_OE = '0' ELSE "ZZZZZZZZ";
KEYB_RxD <= '0' WHEN AMKB_REG(3) = '0' or PIC_AMKB_RX = '0' ELSE '1'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL //
FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_I WHEN ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' ELSE
DATA_OUT_ACIA_II WHEN ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
-- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------
-- AMKB_TX: SPIKES AUSFILTERN und sychronisieren ------------------------------------------
PROCESS(CLK2M, AMKB_RX, AMKB_REG)
BEGIN
IF rising_edge(CLK2M) THEN
if rising_edge(CLK500k) then
AMKB_TX <= AMKB_TX_sync;
IF AMKB_RX = '0' THEN
IF AMKB_REG < 16 THEN
AMKB_REG <= "00000";
IF AMKB_REG < 8 THEN
AMKB_REG <= "0000";
ELSE
AMKB_REG <= AMKB_REG - 1;
END IF;
ELSE
IF AMKB_REG > 15 THEN
AMKB_REG <= "11111";
IF AMKB_REG > 7 THEN
AMKB_REG <= "1111";
ELSE
AMKB_REG <= AMKB_REG + 1;
END IF;
END IF;
ELSE
AMKB_TX <= AMKB_TX;
AMKB_REG <= AMKB_REG;
END IF;
END PROCESS;
-- acia interrupt ------------------------------------------
acia_irq <= '0' WHEN IRQ_KEYBDn = '0' or IRQ_MIDIn = '0' ELSE '1';
----------------------------------------------------------------------------
-- ACIA MIDI
----------------------------------------------------------------------------
i_acia_midi : WF6850IP_TOP_SOC
PORT MAP(
CLK => MAIN_CLK,
RESETn => nRSTO,
RESETn => nResetatio,
CS2n => '0',
CS1 => FB_ADR(2),
@@ -879,7 +885,7 @@ BEGIN
RWn => nFB_WR,
RS => FB_ADR(1),
DATA_IN => FB_AD(31 DOWNTO 24),
DATA_IN => FB_ADI(15 downto 8),
DATA_OUT => DATA_OUT_ACIA_II,
-- DATA_EN => DATA_EN_ACIA_II,
@@ -893,19 +899,16 @@ BEGIN
TXDATA => MIDI_OUT
--RTSn => -- Not used.
);
MIDI_TLR <= MIDI_OUT;
MIDI_TLR <= MIDI_IN;
MIDI_OLR <= MIDI_OUT;
FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_II WHEN ACIA_CS_I = '1' AND FB_ADR(2) = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
----------------------------------------------------------------------------
-- MFP
----------------------------------------------------------------------------
i_mfp : WF68901IP_TOP_SOC
PORT MAP(
-- System control:
CLK => MAIN_CLK,
RESETn => nRSTO,
CLK => not MAIN_CLK,
RESETn => nResetatio,
-- Asynchronous bus control:
DSn => NOT LDS,
CSn => NOT MFP_CS,
@@ -919,7 +922,7 @@ BEGIN
GPIP_IN(7) => NOT DMA_DRQ_Q,
GPIP_IN(6) => NOT RI,
GPIP_IN(5) => DINTn,
GPIP_IN(4) => IRQ_ACIAn,
GPIP_IN(4) => acia_irq,
GPIP_IN(3) => DSP_INT,
GPIP_IN(2) => NOT CTS,
GPIP_IN(1) => NOT DCD,
@@ -954,34 +957,20 @@ BEGIN
MFP_INTACK <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20000" ELSE '0'; --F002'0000
LDS <= '1' WHEN MFP_CS = '1' OR MFP_INTACK = '1' ELSE '0';
FB_AD(23 DOWNTO 16) <= DATA_OUT_MFP WHEN MFP_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(31 DOWNTO 10) <= (OTHERS => '0') WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(9 DOWNTO 2) <= DATA_OUT_MFP WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z') ;
FB_AD(23 DOWNTO 16) <= DATA_OUT_MFP WHEN MFP_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(31 DOWNTO 10) <= "0000000000000000000000" WHEN MFP_INTACK = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZ";
FB_AD(9 DOWNTO 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(1 DOWNTO 0) <= "00" WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE "ZZ";
DINTn <= '0' WHEN IDE_INT = '1' AND ACP_CONF(28) = '1' ELSE
'0' WHEN FDINT = '1' ELSE
'0' WHEN SCSI_INT = '1' AND ACP_CONF(28) = '1' ELSE '1';
-- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------
PROCESS(MAIN_CLK, nRSTO, IRQ_ACIAn, IRQ_KEYBDn, IRQ_MIDIn)
BEGIN
IF nRSTO = '0' THEN
IRQ_ACIAn <= '1';
ELSIF rising_edge(MAIN_CLK) THEN
IRQ_ACIAn <= IRQ_KEYBDn AND IRQ_MIDIn;
ELSE
IRQ_ACIAn <= IRQ_ACIAn;
END IF;
END PROCESS;
----------------------------------------------------------------------------
-- Sound
----------------------------------------------------------------------------
i_sound : WF2149IP_TOP_SOC
PORT MAP(
SYS_CLK => MAIN_CLK,
RESETn => nRSTO,
SYS_CLK => not MAIN_CLK,
RESETn => nResetatio,
WAV_CLK => CLK2M,
SELn => '1',
@@ -992,18 +981,11 @@ BEGIN
A9n => '0',
A8 => '1',
DA_IN => FB_AD(31 DOWNTO 24),
DA_IN => FB_ADI(15 downto 8),
DA_OUT => DA_OUT_X,
IO_A_IN => x"00", -- All port pins are dedicated outputs.
IO_A_OUT(7) => nnIDE_RES,
IO_A_OUT(6) => LP_DIR_X,
IO_A_OUT(5) => LP_STR,
IO_A_OUT(4) => DTR,
IO_A_OUT(3) => RTS,
-- IO_A_OUT(2) => FDD_D1SEL,
IO_A_OUT(1) => DSA_D,
IO_A_OUT(0) => nSDSEL,
IO_A_IN => SND_A,
IO_A_OUT => SND_A_X,
-- IO_A_EN =>, -- Not required.
IO_B_IN => LP_D,
IO_B_OUT => LP_D_X,
@@ -1017,8 +999,185 @@ BEGIN
SNDCS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 2) = x"3E200" ELSE '0'; -- 8800-8803 F8800/4
SNDCS_I <= '1' WHEN SNDCS = '1' AND FB_ADR (1 DOWNTO 1) = "0" ELSE '0';
SNDIR_I <= '1' WHEN SNDCS = '1' AND nFB_WR = '0' ELSE '0';
FB_AD(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
LP_D <= LP_D_X WHEN LP_DIR_X = '0' ELSE (OTHERS => 'Z');
FB_AD(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
nnIDE_RES <= SND_A_X(7);
LP_DIR_X <= SND_A_X(6);
LP_STR <= SND_A_X(5);
DTR <= SND_A_X(4);
RTS <= SND_A_X(3);
-- FDD_D1SEL <= SND_A_X(2)
DSA_D <= SND_A_X(1);
nSDSEL <= SND_A_X(0);
SND_A <= SND_A_X;
LP_D <= LP_D_X WHEN LP_DIR_X = '0' ELSE "ZZZZZZZZ";
LP_DIR <= LP_DIR_X;
----------------------------------------------------------------------------
-- DMA Sound register
----------------------------------------------------------------------------
dma_snd_cs <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 6) = x"3E24" ELSE '0'; -- F8900-F893F
PROCESS(nRSTO,MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndmactl <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_WR = '0' and FB_B1 ='1' THEN
sndmactl <= FB_AD(23 DOWNTO 16);
ELSE
sndmactl <= sndmactl;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndmactl WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE "ZZZZZZZZ";
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
begin
IF nRSTO = '0' THEN
sndbashi <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_WR = '0' and FB_B1 ='1' THEN
sndbashi <= FB_AD(23 DOWNTO 16);
ELSE
sndbashi <= sndbashi;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndbashi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE "ZZZZZZZZ";
PROCESS(nRSTO,MAIN_CLK,FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndbasmi <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"2" and nFB_WR = '0' and FB_B1 ='1' THEN
sndbasmi <= FB_AD(23 DOWNTO 16);
ELSE
sndbasmi <= sndbasmi;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndbasmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"2" and nFB_OE = '0' ELSE "ZZZZZZZZ";
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndbaslo <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"3" and nFB_WR = '0' and FB_B1 ='1' THEN
sndbaslo <= FB_AD(23 DOWNTO 16);
ELSE
sndbaslo <= sndbaslo;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndbaslo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"3" and nFB_OE = '0' ELSE "ZZZZZZZZ";
PROCESS(nRSTO,MAIN_CLK,FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndadrhi <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"4" and nFB_WR = '0' and FB_B1 ='1' THEN
sndadrhi <= FB_AD(23 DOWNTO 16);
ELSE
sndadrhi <= sndadrhi;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndadrhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"4" and nFB_OE = '0' ELSE "ZZZZZZZZ";
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndadrmi <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"5" and nFB_WR = '0' and FB_B1 ='1' THEN
sndadrmi <= FB_AD(23 DOWNTO 16);
ELSE
sndadrmi <= sndadrmi;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndadrmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"5" and nFB_OE = '0' else "ZZZZZZZZ";
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndadrlo <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"6" and nFB_WR = '0' and FB_B1 ='1' THEN
sndadrlo <= FB_AD(23 DOWNTO 16);
ELSE
sndadrlo <= sndadrlo;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndadrlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"6" and nFB_OE = '0' ELSE "ZZZZZZZZ";
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndendhi <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"7" and nFB_WR = '0' and FB_B1 ='1' THEN
sndendhi <= FB_AD(23 DOWNTO 16);
ELSE
sndendhi <= sndendhi;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndendhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"7" and nFB_OE = '0' ELSE "ZZZZZZZZ";
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndendmi <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_WR = '0' and FB_B1 ='1' THEN
sndendmi <= FB_AD(23 DOWNTO 16);
ELSE
sndendmi <= sndendmi;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndendmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE "ZZZZZZZZ";
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndendlo <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_WR = '0' and FB_B1 ='1' THEN
sndendlo <= FB_AD(23 DOWNTO 16);
ELSE
sndendlo <= sndendlo;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndendlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE "ZZZZZZZZ";
PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs)
BEGIN
IF nRSTO = '0' THEN
sndmode <= x"00";
ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_WR = '0' and FB_B1 ='1' THEN
sndmode <= FB_AD(23 DOWNTO 16);
ELSE
sndmode <= sndmode;
END IF;
END PROCESS;
FB_AD(23 DOWNTO 16) <= sndmode WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE "ZZZZZZZZ";
----------------------------------------------------------------------------
-- Paddle
----------------------------------------------------------------------------
paddle_cs <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 6) = x"3E48" ELSE '0'; -- F9200-F923F
FB_AD(31 DOWNTO 16) <= x"bfff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"A" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"B" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
FB_AD(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"11" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ";
END rtl;

2
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
View File

@@ -64,7 +64,7 @@ type BUSCYCLES is (INACTIVE, R_READ, R_WRITE, ADDRESS);
component WF2149IP_WAVE
port(
RESETn : in bit;
SYS_CLK : in std_logic;
SYS_CLK : in bit;
WAV_STRB : in bit;

15
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
View File

@@ -83,7 +83,7 @@ LIBRARY ieee;
ENTITY WF2149IP_TOP_SOC IS
PORT(
SYS_CLK : IN std_logic; -- Read the inforation in the header!
SYS_CLK : in bit; -- Read the inforation in the header!
RESETn : IN bit;
WAV_CLK : IN bit; -- Read the inforation in the header!
@@ -110,7 +110,7 @@ ENTITY WF2149IP_TOP_SOC IS
);
END WF2149IP_TOP_SOC;
ARCHITECTURE rtl OF WF2149IP_TOP_SOC IS
architecture STRUCTURE of WF2149IP_TOP_SOC is
SIGNAL BUSCYCLE : BUSCYCLES;
SIGNAL DATA_OUT_I : std_logic_vector(7 DOWNTO 0);
SIGNAL DATA_EN_I : bit;
@@ -127,11 +127,10 @@ BEGIN
IF RESETn = '0' THEN
LOCK := false;
TMP := '0';
ELSIF rising_edge(SYS_CLK) THEN
elsif SYS_CLK = '1' and SYS_CLK' event then
IF WAV_CLK = '1' and LOCK = false THEN
LOCK := true;
TMP := not TMP; -- Divider by 2.
CASE SELn IS
WHEN '1' => WAV_STRB <= '1';
WHEN OTHERS => WAV_STRB <= TMP;
@@ -158,7 +157,7 @@ BEGIN
BEGIN
IF RESETn = '0' THEN
ADR_I <= (OTHERS => '0');
ELSIF rising_edge(SYS_CLK) THEN
elsif SYS_CLK = '1' and SYS_CLK' event then
IF BUSCYCLE = ADDRESS AND A9n = '0' AND A8 = '1' AND DA_IN(7 DOWNTO 4) = x"0" THEN
ADR_I <= To_BitVector(DA_IN(3 DOWNTO 0));
END IF;
@@ -170,7 +169,7 @@ BEGIN
BEGIN
IF RESETn = '0' THEN
CTRL_REG <= x"00";
ELSIF rising_edge(SYS_CLK) THEN
elsif SYS_CLK = '1' and SYS_CLK' event then
IF BUSCYCLE = R_WRITE AND ADR_I = x"7" THEN
CTRL_REG <= To_BitVector(DA_IN);
END IF;
@@ -182,7 +181,7 @@ BEGIN
IF RESETn = '0' THEN
PORT_A <= x"00";
PORT_B <= x"00";
ELSIF rising_edge(SYS_CLK) THEN
elsif SYS_CLK = '1' and SYS_CLK' event then
IF BUSCYCLE = R_WRITE AND ADR_I = x"E" THEN
PORT_A <= To_BitVector(DA_IN);
ELSIF BUSCYCLE = R_WRITE and ADR_I = x"F" THEN
@@ -227,4 +226,4 @@ BEGIN
To_StdLogicVector(IO_B_IN) WHEN BUSCYCLE = R_READ and ADR_I = x"F" ELSE
To_StdLogicVector(CTRL_REG) WHEN BUSCYCLE = R_READ and ADR_I = x"7" ELSE (OTHERS => '0');
END rtl;
end STRUCTURE;

2
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
View File

@@ -65,7 +65,7 @@ use work.wf2149ip_pkg.all;
entity WF2149IP_WAVE is
port(
RESETn : in bit;
SYS_CLK : in std_logic;
SYS_CLK : in bit;
WAV_STRB : in bit;

96
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
View File

@@ -67,7 +67,7 @@ use ieee.std_logic_unsigned.all;
entity WF6850IP_CTRL_STATUS is
port (
CLK : in bit;
CLK : in std_logic;
RESETn : in bit;
CS : in bit_vector(2 downto 0); -- Active if "011".
@@ -94,7 +94,7 @@ entity WF6850IP_CTRL_STATUS is
CDS : out bit_vector(1 downto 0); -- Clock control.
WS : out bit_vector(2 downto 0); -- Word select.
TC : out bit_vector(1 downto 0); -- Transmit control.
IRQn : out bit -- Interrupt request.
IRQn : buffer bit -- Interrupt request.
);
end entity WF6850IP_CTRL_STATUS;
@@ -102,19 +102,14 @@ architecture BEHAVIOR of WF6850IP_CTRL_STATUS is
signal CTRL_REG : bit_vector(7 downto 0);
signal STATUS_REG : bit_vector(7 downto 0);
signal RIE : bit;
signal IRQ_I : bit;
signal CTS_In : bit;
signal DCD_In : bit;
signal DCD_FLAGn : bit;
begin
P_SAMPLE: process
begin
wait until CLK = '0' and CLK' event;
CTS_In <= CTSn; -- Sample CTSn on the negative clock edge.
DCD_In <= DCDn; -- Sample DCDn on the negative clock edge.
end process P_SAMPLE;
CTS_In <= CTSn;
DCD_In <= DCDn; -- immer 0
STATUS_REG(7) <= IRQ_I;
STATUS_REG(7) <= not IRQn;
STATUS_REG(6) <= PE;
STATUS_REG(5) <= OVR;
STATUS_REG(4) <= FE;
@@ -123,8 +118,8 @@ begin
STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'.
STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty.
DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' and E = '1' else (others => '0');
DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' and E = '1' else '0';
DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' else (others => '0');
DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' else '0';
MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0';
RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1';
@@ -134,90 +129,52 @@ begin
TC <= CTRL_REG(6 downto 5);
RIE <= CTRL_REG(7);
P_IRQ: process
variable DCD_OVR_LOCK : boolean;
variable DCD_LOCK : boolean;
variable DCD_TRANS : boolean;
P_IRQ: process(CLK)
begin
wait until CLK = '1' and CLK' event;
if RESETn = '0' then
DCD_OVR_LOCK := false;
if rising_edge(CLK) then
if RESETn = '0' or MCLR = '1' then
IRQn <= '1';
IRQ_I <= '0';
elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
DCD_OVR_LOCK := false; -- Enable reset by reading the status.
end if;
-- Clear interrupts when disabled.
if CTRL_REG(7) = '0' then
IRQn <= '1';
IRQ_I <= '0';
elsif CTRL_REG(6 downto 5) /= "01" then
IRQn <= '1';
IRQ_I <= '0';
end if;
else
-- Transmitter interrupt:
if TDRE = '1' and CTRL_REG(6 downto 5) = "01" and CTS_In = '0' then
if TDRE = '1' and CTRL_REG(6 downto 5) = "01" then
IRQn <= '0';
IRQ_I <= '1';
elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' then
IRQn <= '1'; -- Clear by writing to the transmit data register.
end if;
-- Receiver interrupts:
if RDRF = '1' and RIE = '1' and DCD_In = '0' then
if RDRF = '1' and RIE = '1' then
IRQn <= '0';
IRQ_I <= '1';
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
IRQn <= '1'; -- Clear by reading the receive data register.
end if;
-- Overrun
if OVR = '1' and RIE = '1' then
IRQn <= '0';
IRQ_I <= '1';
DCD_OVR_LOCK := true;
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then
IRQn <= '1'; -- Clear by reading the receive data register after the status.
end if;
if DCD_In = '1' and RIE = '1' and DCD_TRANS = false then
IRQn <= '0';
IRQ_I <= '1';
-- DCD_TRANS is used to detect a low to high transition of DCDn.
DCD_TRANS := true;
DCD_OVR_LOCK := true;
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then
IRQn <= '1'; -- Clear by reading the receive data register after the status.
elsif DCD_In = '0' then
DCD_TRANS := false;
end if;
-- The reset of the IRQ status flag:
-- Clear by writing to the transmit data register.
-- Clear by reading the receive data register.
if CS = "011" and RS = '1' and E = '1' then
IRQ_I <= '0';
if CS = "011" and RS = '1' then
IRQn <= '1';
end if;
end if;
end if;
end process P_IRQ;
CONTROL: process
CONTROL: process(CLK)
begin
wait until CLK = '1' and CLK' event;
if rising_edge(CLK) then
if RESETn = '0' then
CTRL_REG <= "01000000";
elsif CS = "011" and RWn = '0' and RS = '0' and E = '1' then
elsif CS = "011" and RWn = '0' and RS = '0' then
CTRL_REG <= DATA_IN;
end if;
end if;
end process CONTROL;
P_DCD: process
P_DCD: process(CLK)
-- This process is some kind of tricky. Refer to the MC6850 data
-- sheet for more information.
variable READ_LOCK : boolean;
variable DCD_RELEASE : boolean;
begin
wait until CLK = '1' and CLK' event;
if rising_edge(CLK) then
if RESETn = '0' then
DCD_FLAGn <= '0'; -- This interrupt source must initialise low.
READ_LOCK := true;
@@ -227,9 +184,9 @@ begin
READ_LOCK := true;
elsif DCD_In = '1' then
DCD_FLAGn <= '1';
elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
elsif CS = "011" and RWn = '1' and RS = '0' then
READ_LOCK := false; -- Un-READ_LOCK if receiver data register is read.
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and READ_LOCK = false then
elsif CS = "011" and RWn = '1' and RS = '1' and READ_LOCK = false then
-- Clear if receiver status register read access.
-- After data register has ben read and READ_LOCK again.
DCD_RELEASE := true;
@@ -239,6 +196,7 @@ begin
DCD_FLAGn <= '0';
DCD_RELEASE := false;
end if;
end if;
end process P_DCD;
end architecture BEHAVIOR;

517
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
View File

@@ -54,362 +54,379 @@
-- Minor changes.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
entity WF6850IP_RECEIVE is
port (
CLK : in bit;
RESETn : in bit;
MCLR : in bit;
ENTITY WF6850IP_RECEIVE IS
PORT
(
CLK : IN std_logic;
RESETn : IN bit;
MCLR : IN bit;
CS : in bit_vector(2 downto 0);
E : in bit;
RWn : in bit;
RS : in bit;
CS : IN bit_vector(2 DOWNTO 0);
E : IN bit;
RWn : IN bit;
RS : IN bit;
DATA_OUT : out bit_vector(7 downto 0);
DATA_EN : out bit;
DATA_OUT : OUT bit_vector(7 DOWNTO 0);
DATA_EN : OUT bit;
WS : in bit_vector(2 downto 0);
CDS : in bit_vector(1 downto 0);
WS : IN bit_vector(2 DOWNTO 0);
CDS : IN bit_vector(1 DOWNTO 0);
RXCLK : in bit;
RXDATA : in bit;
RXCLK : IN bit;
RXDATA : IN bit;
RDRF : buffer bit;
OVR : out bit;
PE : out bit;
FE : out bit
RDRF : BUFFER bit;
OVR : OUT bit;
PE : OUT bit;
FE : OUT bit
);
end entity WF6850IP_RECEIVE;
END ENTITY WF6850IP_RECEIVE;
architecture BEHAVIOR of WF6850IP_RECEIVE is
type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC);
signal RCV_STATE, RCV_NEXT_STATE : RCV_STATES;
signal RXDATA_I : bit;
signal RXDATA_S : bit;
signal DATA_REG : bit_vector(7 downto 0);
signal SHIFT_REG : bit_vector(7 downto 0);
signal CLK_STRB : bit;
signal BITCNT : std_logic_vector(2 downto 0);
begin
P_SAMPLE: process
ARCHITECTURE rtl OF WF6850IP_RECEIVE IS
TYPE RCV_STATES IS (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC);
SIGNAL RCV_STATE, RCV_NEXT_STATE : RCV_STATES;
SIGNAL RXDATA_I : bit;
SIGNAL RXDATA_S : bit;
SIGNAL DATA_REG : bit_vector(7 DOWNTO 0);
SIGNAL SHIFT_REG : bit_vector(7 DOWNTO 0);
SIGNAL CLK_STRB : bit;
SIGNAL BITCNT : std_logic_vector(2 DOWNTO 0);
BEGIN
p_sample : PROCESS(CLK)
-- This filter provides a synchronisation to the system
-- clock, even for random baud rates of the received data
-- stream.
variable FLT_TMP : integer range 0 to 2;
begin
wait until CLK = '1' and CLK' event;
VARIABLE FLT_TMP : integer RANGE 0 TO 2;
BEGIN
IF rising_edge(CLK) THEN
--
RXDATA_I <= RXDATA;
--
if RXDATA_I = '1' and FLT_TMP < 2 then
IF RXDATA_I = '1' and FLT_TMP < 2 THEN
FLT_TMP := FLT_TMP + 1;
elsif RXDATA_I = '1' then
ELSIF RXDATA_I = '1' THEN
RXDATA_S <= '1';
elsif RXDATA_I = '0' and FLT_TMP > 0 then
ELSIF RXDATA_I = '0' and FLT_TMP > 0 THEN
FLT_TMP := FLT_TMP - 1;
elsif RXDATA_I = '0' then
ELSIF RXDATA_I = '0' THEN
RXDATA_S <= '0';
end if;
end process P_SAMPLE;
END IF;
END IF;
END PROCESS p_sample;
CLKDIV: process
variable CLK_LOCK : boolean;
variable STRB_LOCK : boolean;
variable CLK_DIVCNT : std_logic_vector(6 downto 0);
begin
wait until CLK = '1' and CLK' event;
if CDS = "00" then -- Divider off.
if RXCLK = '1' and STRB_LOCK = false then
clkdiv : PROCESS(CLK)
VARIABLE CLK_LOCK : boolean;
VARIABLE STRB_LOCK : boolean;
VARIABLE CLK_DIVCNT : std_logic_vector(6 DOWNTO 0);
BEGIN
IF rising_edge(CLK) THEN
IF CDS = "00" THEN -- Divider off.
IF RXCLK = '1' and STRB_LOCK = false THEN
CLK_STRB <= '1';
STRB_LOCK := true;
elsif RXCLK = '0' then
ELSIF RXCLK = '0' THEN
CLK_STRB <= '0';
STRB_LOCK := false;
else
ELSE
CLK_STRB <= '0';
end if;
elsif RCV_STATE = IDLE then
END IF;
ELSIF RCV_STATE = IDLE THEN
-- Preset the CLKDIV with the start delays.
if CDS = "01" then
IF CDS = "01" THEN
CLK_DIVCNT := "0001000"; -- Half of div by 16 mode.
elsif CDS = "10" then
ELSIF CDS = "10" THEN
CLK_DIVCNT := "0100000"; -- Half of div by 64 mode.
end if;
END IF;
CLK_STRB <= '0';
else
if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then
ELSE
IF CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false THEN
CLK_DIVCNT := CLK_DIVCNT - '1';
CLK_STRB <= '0';
CLK_LOCK := true;
elsif CDS = "01" and CLK_DIVCNT = "0000000" then
ELSIF CDS = "01" and CLK_DIVCNT = "0000000" THEN
CLK_DIVCNT := "0010000"; -- Div by 16 mode.
--
if STRB_LOCK = false then
IF STRB_LOCK = false THEN
STRB_LOCK := true;
CLK_STRB <= '1';
else
ELSE
CLK_STRB <= '0';
end if;
elsif CDS = "10" and CLK_DIVCNT = "0000000" then
END IF;
ELSIF CDS = "10" and CLK_DIVCNT = "0000000" THEN
CLK_DIVCNT := "1000000"; -- Div by 64 mode.
if STRB_LOCK = false then
IF STRB_LOCK = false THEN
STRB_LOCK := true;
CLK_STRB <= '1';
else
ELSE
CLK_STRB <= '0';
end if;
elsif RXCLK = '0' then
END IF;
ELSIF RXCLK = '0' THEN
CLK_LOCK := false;
STRB_LOCK := false;
CLK_STRB <= '0';
else
ELSE
CLK_STRB <= '0';
end if;
end if;
end process CLKDIV;
END IF;
END IF;
END IF;
END PROCESS clkdiv;
DATAREG: process(RESETn, CLK)
begin
if RESETn = '0' then
datareg : PROCESS(RESETn, CLK)
BEGIN
IF RESETn = '0' or MCLR = '1' THEN
DATA_REG <= x"00";
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
DATA_REG <= x"00";
elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data.
ELSE
IF rising_edge(CLK) THEN
IF RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' THEN -- 7 bit data.
-- Transfer from shift- to data register only if
-- data register is empty (RDRF = '0').
DATA_REG <= '0' & SHIFT_REG(7 downto 1);
elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data.
ELSIF RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' THEN -- 8 bit data.
-- Transfer from shift- to data register only if
-- data register is empty (RDRF = '0').
DATA_REG <= SHIFT_REG;
end if;
end if;
end process DATAREG;
DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0');
DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0';
END IF;
END IF;
END IF;
END PROCESS datareg;
SHIFTREG: process(RESETn, CLK)
begin
if RESETn = '0' then
SHIFT_REG <= x"00";
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
SHIFT_REG <= x"00";
elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then
SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right.
end if;
end if;
end process SHIFTREG;
DATA_OUT <= DATA_REG WHEN CS = "011" and RWn = '1' and RS = '1' ELSE (OTHERS => '0');
DATA_EN <= '1' WHEN CS = "011" and RWn = '1' and RS = '1' ELSE '0';
P_BITCNT: process
begin
wait until CLK = '1' and CLK' event;
if RCV_STATE = SAMPLE and CLK_STRB = '1' then
shiftreg : PROCESS(RESETn, CLK)
BEGIN
IF RESETn = '0' or MCLR = '1' THEN
SHIFT_REG <= x"00";
ELSE
IF rising_edge(CLK) THEN
IF RCV_STATE = SAMPLE and CLK_STRB = '1' THEN
SHIFT_REG <= RXDATA_S & SHIFT_REG(7 DOWNTO 1); -- Shift right.
END IF;
END IF;
END IF;
END PROCESS shiftreg;
p_bitcnt : PROCESS(CLK)
BEGIN
IF rising_edge(CLK) THEN
IF RCV_STATE = SAMPLE and CLK_STRB = '1' THEN
BITCNT <= BITCNT + '1';
elsif RCV_STATE /= SAMPLE then
BITCNT <= (others => '0');
end if;
end process P_BITCNT;
ELSIF RCV_STATE /= SAMPLE THEN
BITCNT <= (OTHERS => '0');
END IF;
END IF;
END PROCESS p_bitcnt;
FRAME_ERR: process(RESETn, CLK)
p_frame_err: PROCESS(RESETn, CLK)
-- This module detects a framing error
-- during stop bit 1 and stop bit 2.
variable FE_I: bit;
begin
if RESETn = '0' then
VARIABLE FE_I: bit;
BEGIN
IF RESETn = '0' THEN
FE_I := '0';
FE <= '0';
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
ELSE
IF rising_edge(CLK) THEN
IF MCLR = '1' THEN
FE_I := '0';
FE <= '0';
elsif CLK_STRB = '1' then
if RCV_STATE = STOP1 and RXDATA_S = '0' then
ELSIF CLK_STRB = '1' THEN
IF RCV_STATE = STOP1 and RXDATA_S = '0' THEN
FE_I := '1';
elsif RCV_STATE = STOP2 and RXDATA_S = '0' then
ELSIF RCV_STATE = STOP2 and RXDATA_S = '0' THEN
FE_I := '1';
elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
ELSIF RCV_STATE = STOP1 or RCV_STATE = STOP2 THEN
FE_I := '0'; -- Error resets when correct data appears.
end if;
end if;
if RCV_STATE = SYNC then
END IF;
END IF;
IF RCV_STATE = SYNC THEN
FE <= FE_I; -- Update the FE every SYNC time.
end if;
end if;
end process FRAME_ERR;
END IF;
END IF;
END IF;
END PROCESS p_frame_err;
OVERRUN: process(RESETn, CLK)
variable OVR_I : bit;
variable FIRST_READ : boolean;
begin
if RESETn = '0' then
p_overrun : PROCESS(RESETn, CLK)
VARIABLE OVR_I : bit;
VARIABLE FIRST_READ : boolean;
BEGIN
IF rising_edge(CLK) THEN
IF RESETn = '0' or MCLR = '1' THEN
OVR_I := '0';
OVR <= '0';
FIRST_READ := false;
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
OVR_I := '0';
OVR <= '0';
FIRST_READ := false;
elsif CLK_STRB = '1' and RCV_STATE = STOP1 then
ELSE
IF CLK_STRB = '1' and RCV_STATE = STOP1 THEN
-- Overrun appears if RDRF is '1' in this state.
OVR_I := RDRF;
end if;
if CS = "011" and RWn = '1' and RS = '1' and E = '1' and OVR_I = '1' then
END IF;
IF CS = "011" and RWn = '1' and RS = '1' THEN
-- If an overrun was detected, the concerning flag is
-- set when the valid data word in the receiver data
-- register is read. Thereafter the RDRF flag is reset
-- and the overrun disappears (OVR_I goes low) after
-- a second read (in time) of the receiver data register.
if FIRST_READ = false then
IF FIRST_READ = false THEN
IF OVR_I = '1' THEN
OVR <= '1';
OVR_I := '0';
FIRST_READ := true;
else
ELSE
OVR <= '0';
END IF;
END IF;
ELSE
FIRST_READ := false;
end if;
end if;
end if;
end process OVERRUN;
END IF;
END IF;
END IF;
END PROCESS p_overrun;
PARITY_TEST: process(RESETn, CLK)
variable PAR_TMP : bit;
variable PE_I : bit;
begin
if RESETn = '0' then
p_parity_test : PROCESS(RESETn,MCLR,CLK)
VARIABLE PAR_TMP : bit;
VARIABLE PE_I : bit;
BEGIN
IF RESETn = '0' or MCLR = '1' THEN
PE <= '0';
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
PE <= '0';
elsif CLK_STRB = '1' then -- Sample parity on clock strobe.
ELSE
IF rising_edge(CLK) THEN
IF CLK_STRB = '1' THEN -- Sample parity on clock strobe.
PE_I := '0'; -- Initialise.
if RCV_STATE = PARITY then
for i in 1 to 7 loop
if i = 1 then
IF RCV_STATE = PARITY THEN
FOR i in 1 TO 7 LOOP
IF i = 1 THEN
PAR_TMP := SHIFT_REG(i - 1) xor SHIFT_REG(i);
else
ELSE
PAR_TMP := PAR_TMP xor SHIFT_REG(i);
end if;
end loop;
if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
END IF;
END LOOP;
IF WS = "000" or WS = "010" or WS = "110" THEN -- Even parity.
PE_I := PAR_TMP xor RXDATA_S;
elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
ELSIF WS = "001" or WS = "011" or WS = "111" THEN -- Odd parity.
PE_I := not PAR_TMP xor RXDATA_S;
else -- No parity for WS = "100" and WS = "101".
ELSE -- No parity for WS = "100" and WS = "101".
PE_I := '0';
end if;
end if;
end if;
END IF;
END IF;
END IF;
END IF;
-- Transmit the parity flag together with the data
-- In other words: no parity to the status register
-- when RDRF inhibits the data transfer to the
-- receiver data register.
if RCV_STATE = SYNC and RDRF = '0' then
IF RCV_STATE = SYNC and RDRF = '0' THEN
PE <= PE_I;
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
ELSIF CS = "011" and RWn = '1' and RS = '1' THEN
PE <= '0'; -- Clear when reading the data register.
end if;
end if;
end process PARITY_TEST;
END IF;
END IF;
END PROCESS p_parity_test;
P_RDRF: process(RESETn, CLK)
p_rdrf : process(RESETn, CLK)
-- Receive data register full flag.
begin
if RESETn = '0' then
BEGIN
IF rising_edge(CLK) THEN
IF RESETn = '0' or MCLR = '1' THEN
RDRF <= '0';
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
RDRF <= '0';
elsif RCV_STATE = SYNC then
ELSE
IF RCV_STATE = SYNC THEN
RDRF <= '1'; -- Data register is full until now!
elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
RDRF <= '0'; -- After reading the data register ...
end if;
end if;
end process P_RDRF;
END IF;
IF CS = "011" and RWn = '1' and RS = '1' THEN
RDRF <= '0'; -- when reading the data register ...
END IF;
END IF;
END IF;
END PROCESS p_rdrf;
RCV_STATEREG: process(RESETn, CLK)
begin
if RESETn = '0' then
p_rcv_statereg : PROCESS(RESETn, CLK)
BEGIN
IF RESETn = '0' THEN
RCV_STATE <= IDLE;
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
ELSE
IF rising_edge(CLK) THEN
IF MCLR = '1' THEN
RCV_STATE <= IDLE;
else
ELSE
RCV_STATE <= RCV_NEXT_STATE;
end if;
end if;
end process RCV_STATEREG;
END IF;
END IF;
END IF;
END PROCESS p_rcv_statereg;
RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB)
begin
case RCV_STATE is
when IDLE =>
if RXDATA_S = '0' and CDS = "00" then
p_rcv_statedec : PROCESS(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB)
BEGIN
CASE RCV_STATE IS
WHEN IDLE =>
IF RXDATA_S = '0' and CDS = "00" THEN
RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode.
elsif RXDATA_S = '0' and CDS = "01" then
ELSIF RXDATA_S = '0' and CDS = "01" THEN
RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode.
elsif RXDATA_S = '0' and CDS = "10" then
ELSIF RXDATA_S = '0' and CDS = "10" THEN
RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode.
else
ELSE
RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-)
end if;
when WAIT_START =>
if CLK_STRB = '1' then
if RXDATA_S = '0' then
RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes.
else
RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back.
end if;
else
RCV_NEXT_STATE <= WAIT_START; -- Stay.
end if;
when SAMPLE =>
if CLK_STRB = '1' then
if BITCNT < "110" and WS(2) = '0' then
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits.
elsif BITCNT < "111" and WS(2) = '1' then
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits.
elsif WS = "100" or WS = "101" then
RCV_NEXT_STATE <= STOP1; -- No parity check enabled.
else
RCV_NEXT_STATE <= PARITY; -- Parity enabled.
end if;
else
RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode.
end if;
when PARITY =>
if CLK_STRB = '1' then
RCV_NEXT_STATE <= STOP1;
else
RCV_NEXT_STATE <= PARITY;
end if;
when STOP1 =>
if CLK_STRB = '1' then
if RXDATA_S = '0' then
RCV_NEXT_STATE <= SYNC; -- Framing error detected.
elsif WS = "000" or WS = "001" or WS = "100" then
RCV_NEXT_STATE <= STOP2; -- Two stop bits selected.
else
RCV_NEXT_STATE <= SYNC; -- One stop bit selected.
end if;
else
RCV_NEXT_STATE <= STOP1;
end if;
when STOP2 =>
if CLK_STRB = '1' then
RCV_NEXT_STATE <= SYNC;
else
RCV_NEXT_STATE <= STOP2;
end if;
when SYNC =>
RCV_NEXT_STATE <= IDLE;
end case;
end process RCV_STATEDEC;
end architecture BEHAVIOR;
END IF;
WHEN WAIT_START =>
IF CLK_STRB = '1' THEN
IF RXDATA_S = '0' THEN
RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes.
ELSE
RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back.
END IF;
ELSE
RCV_NEXT_STATE <= WAIT_START; -- Stay.
END IF;
WHEN SAMPLE =>
IF CLK_STRB = '1' THEN
IF BITCNT < "110" and WS(2) = '0' THEN
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits.
ELSIF BITCNT < "111" and WS(2) = '1' THEN
RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits.
ELSIF WS = "100" or WS = "101" THEN
RCV_NEXT_STATE <= STOP1; -- No parity check enabled.
ELSE
RCV_NEXT_STATE <= PARITY; -- Parity enabled.
END IF;
ELSE
RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode.
END IF;
WHEN PARITY =>
IF CLK_STRB = '1' THEN
RCV_NEXT_STATE <= STOP1;
ELSE
RCV_NEXT_STATE <= PARITY;
END IF;
WHEN STOP1 =>
IF CLK_STRB = '1' THEN
IF RXDATA_S = '0' THEN
RCV_NEXT_STATE <= SYNC; -- Framing error detected.
ELSIF WS = "000" or WS = "001" or WS = "100" THEN
RCV_NEXT_STATE <= STOP2; -- Two stop bits selected.
ELSE
RCV_NEXT_STATE <= SYNC; -- One stop bit selected.
END IF;
ELSE
RCV_NEXT_STATE <= STOP1;
END IF;
WHEN STOP2 =>
IF CLK_STRB = '1' THEN
RCV_NEXT_STATE <= SYNC;
ELSE
RCV_NEXT_STATE <= STOP2;
END IF;
WHEN SYNC =>
RCV_NEXT_STATE <= IDLE;
END CASE;
END PROCESS p_rcv_statedec;
END ARCHITECTURE rtl;

10
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
View File

@@ -158,7 +158,6 @@ ARCHITECTURE structure OF WF6850IP_TOP_SOC IS
TXDATA : OUT bit
);
END COMPONENT;
SIGNAL DATA_IN_I : bit_vector(7 DOWNTO 0);
SIGNAL DATA_RX : bit_vector(7 DOWNTO 0);
SIGNAL DATA_RX_EN : bit;
@@ -183,8 +182,7 @@ BEGIN
IRQn <= '0' when IRQ_In = '0' else '1';
I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS
PORT MAP
(
port map(
CLK => CLK,
RESETn => RESETn,
CS(2) => CS2n,
@@ -212,8 +210,7 @@ BEGIN
);
I_UART_RECEIVE: WF6850IP_RECEIVE
PORT MAP
(
port map (
CLK => CLK,
RESETn => RESETn,
MCLR => MCLR_I,
@@ -236,8 +233,7 @@ BEGIN
);
I_UART_TRANSMIT: WF6850IP_TRANSMIT
PORT MAP
(
port map (
CLK => CLK,
RESETn => RESETn,
MCLR => MCLR_I,

45
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
View File

@@ -63,7 +63,7 @@ use ieee.std_logic_unsigned.all;
entity WF6850IP_TRANSMIT is
port (
CLK : in bit;
CLK : in std_logic;
RESETn : in bit;
MCLR : in bit;
@@ -108,12 +108,12 @@ begin
'1' when TR_STATE = STOP1 else
'1' when TR_STATE = STOP2 else '1';
CLKDIV: process
CLKDIV: process(CLK)
variable CLK_LOCK : boolean;
variable STRB_LOCK : boolean;
variable CLK_DIVCNT : std_logic_vector(6 downto 0);
begin
wait until CLK = '1' and CLK' event;
if rising_edge(CLK) then
if CDS = "00" then -- divider off
if TXCLK = '0' and STRB_LOCK = false then -- Works on negative TXCLK edge.
CLK_STRB <= '1';
@@ -162,13 +162,14 @@ begin
CLK_STRB <= '0';
end if;
end if;
end if;
end process CLKDIV;
DATAREG: process(RESETn, CLK)
begin
if RESETn = '0' then
DATA_REG <= x"00";
elsif CLK = '1' and CLK' event then
elsif rising_edge(CLK) then
if MCLR = '1' then
DATA_REG <= x"00";
elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then
@@ -183,7 +184,7 @@ begin
begin
if RESETn = '0' then
SHIFT_REG <= x"00";
elsif CLK = '1' and CLK' event then
elsif rising_edge(CLK) then
if MCLR = '1' then
SHIFT_REG <= x"00";
elsif TR_STATE = LOAD_SHFT and TDRE = '0' then
@@ -198,47 +199,42 @@ begin
end if;
end process SHIFTREG;
P_BITCNT: process
P_BITCNT: process(CLK)
-- Counter for the data bits transmitted.
begin
wait until CLK = '1' and CLK' event;
if rising_edge(CLK) then
if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
BITCNT <= BITCNT + '1';
elsif TR_STATE /= SHIFTOUT then
BITCNT <= "000";
end if;
end if;
end process P_BITCNT;
P_TDRE: process(RESETn, CLK)
-- Transmit data register empty flag.
variable LOCK : boolean;
begin
if RESETn = '0' then
if rising_edge(CLK) then
if RESETn = '0' or MCLR = '1' then
TDRE <= '1';
LOCK := false;
elsif CLK = '1' and CLK' event then
if MCLR = '1' then
TDRE <= '1';
elsif TR_NEXT_STATE = START and TR_STATE /= START then
else
if TR_NEXT_STATE = START and TR_STATE /= START then
-- Data has been loaded to shift register, thus data register is free again.
-- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once
-- entering the state now.
TDRE <= '1';
elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' and LOCK = false then
LOCK := true;
elsif E = '0' and LOCK = true then
-- This construction clears TDRE after the falling edge of E
-- and after the transmit data register has been written to.
end if;
if CS = "011" and RWn = '0' and RS = '1' then
TDRE <= '0';
LOCK := false;
end if;
end if;
end if;
end process P_TDRE;
PARITY_GEN: process
PARITY_GEN: process(CLK)
variable PAR_TMP : bit;
begin
wait until CLK = '1' and CLK' event;
if rising_edge(CLK) then
if TR_STATE = START then -- Calculate the parity during the start phase.
for i in 1 to 7 loop
if i = 1 then
@@ -255,19 +251,22 @@ begin
PARITY_I <= '0';
end if;
end if;
end if;
end process PARITY_GEN;
TR_STATEREG: process(RESETn, CLK)
begin
if RESETn = '0' then
TR_STATE <= IDLE;
elsif CLK = '1' and CLK' event then
else
if rising_edge(CLK) then
if MCLR = '1' then
TR_STATE <= IDLE;
else
TR_STATE <= TR_NEXT_STATE;
end if;
end if;
end if;
end process TR_STATEREG;
TR_STATEDEC: process(TR_STATE, CLK_STRB, TC, BITCNT, WS, TDRE, CTSn)

216
FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf
View File

@@ -37,6 +37,7 @@ SUBDESIGN interrupt_handler
VSYNC : INPUT;
HSYNC : INPUT;
DMA_DRQ : INPUT;
nRSTO : INPUT;
nIRQ[7..2] : OUTPUT;
INT_HANDLER_TA : OUTPUT;
ACP_CONF[31..0] : OUTPUT;
@@ -56,6 +57,8 @@ VARIABLE
INT_IN[31..0] :NODE;
INT_ENA[31..0] :DFFE;
INT_ENA_CS :NODE;
INT_L[9..0] :DFF;
INT_LA[9..0][3..0] :DFF;
ACP_CONF[31..0] :DFFE;
ACP_CONF_CS :NODE;
PSEUDO_BUS_ERROR :NODE;
@@ -91,7 +94,7 @@ BEGIN
# !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & FB_ADR0 -- LLBYT
# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE
-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSL<53>SEN, 1=INT7 AUSL<53>SEN
-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSL<53>SEN, 1=INT7 AUSL<53>SEN
INT_CTR[].CLK = MAIN_CLK;
INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000"; -- $10000/4
INT_CTR[] = FB_AD[];
@@ -99,16 +102,15 @@ BEGIN
INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR;
INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR;
INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR;
-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
INT_ENA[].CLK = MAIN_CLK;
INT_ENA[].CLRN = nRSTO;
INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4
INT_ENA[] = FB_AD[];
INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR;
INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR;
INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR;
INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR;
-- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR
INT_CLEAR[].CLK = MAIN_CLK;
INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4
@@ -116,23 +118,21 @@ BEGIN
INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR;
INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR;
INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR;
-- INTERRUPT LATCH REGISTER READ ONLY
INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4
-- INTERRUPT
!nIRQ2 = HSYNC & INT_ENA[26];
!nIRQ3 = INT_CTR0 & INT_ENA[27];
!nIRQ4 = VSYNC & INT_ENA[28];
nIRQ5 = INT_LATCH[]==H"00000000" & INT_ENA[29];
!nIRQ5 = INT_LATCH[]!=H"00000000" & INT_ENA[29];
!nIRQ6 = !nMFP_INT & INT_ENA[30];
!nIRQ7 = PSEUDO_BUS_ERROR & INT_ENA[31];
PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC
# FB_ADR[19..4]==H"F8E0" -- VME
# FB_ADR[19..4]==H"F920" -- PADDLE
# FB_ADR[19..4]==H"F921" -- PADDLE
# FB_ADR[19..4]==H"F922" -- PADDLE
-- # FB_ADR[19..4]==H"F920" -- PADDLE
-- # FB_ADR[19..4]==H"F921" -- PADDLE
-- # FB_ADR[19..4]==H"F922" -- PADDLE
# FB_ADR[19..4]==H"FFA8" -- MFP2
# FB_ADR[19..4]==H"FFA9" -- MFP2
# FB_ADR[19..4]==H"FFAA" -- MFP2
@@ -140,28 +140,38 @@ PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC
# FB_ADR[19..8]==H"F87" -- TT SCSI
# FB_ADR[19..4]==H"FFC2" -- ST UHR
# FB_ADR[19..4]==H"FFC3" -- ST UHR
# FB_ADR[19..4]==H"F890" -- DMA SOUND
# FB_ADR[19..4]==H"F891" -- DMA SOUND
# FB_ADR[19..4]==H"F892"); -- DMA SOUND
-- # FB_ADR[19..4]==H"F890" -- DMA SOUND
-- # FB_ADR[19..4]==H"F891" -- DMA SOUND
-- # FB_ADR[19..4]==H"F892" -- DMA SOUND
);
-- IF VIDEO ADR CHANGE
TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
-- INTERRUPT LATCH
INT_LATCH[] = H"FFFFFFFF";
INT_LATCH0.CLK = PIC_INT & INT_ENA[0];
INT_LATCH1.CLK = E0_INT & INT_ENA[1];
INT_LATCH2.CLK = DVI_INT & INT_ENA[2];
INT_LATCH3.CLK = !nPCI_INTA & INT_ENA[3];
INT_LATCH4.CLK = !nPCI_INTB & INT_ENA[4];
INT_LATCH5.CLK = !nPCI_INTC & INT_ENA[5];
INT_LATCH6.CLK = !nPCI_INTD & INT_ENA[6];
INT_LATCH7.CLK = DSP_INT & INT_ENA[7];
INT_LATCH8.CLK = VSYNC & INT_ENA[8];
INT_LATCH9.CLK = HSYNC & INT_ENA[9];
INT_L[].CLK = MAIN_CLK;
INT_L[].CLRN = nRSTO;
INT_L0 = PIC_INT & INT_ENA[0];
INT_L1 = E0_INT & INT_ENA[1];
INT_L2 = DVI_INT & INT_ENA[2];
INT_L3 = !nPCI_INTA & INT_ENA[3];
INT_L4 = !nPCI_INTB & INT_ENA[4];
INT_L5 = !nPCI_INTC & INT_ENA[5];
INT_L6 = !nPCI_INTD & INT_ENA[6];
INT_L7 = DSP_INT & INT_ENA[7];
INT_L8 = VSYNC & INT_ENA[8];
INT_L9 = HSYNC & INT_ENA[9];
-- INTERRUPT CLEAR
INT_LATCH[].CLRN = !INT_CLEAR[];
INT_LA[][].CLK = MAIN_CLK;
INT_LATCH[] = H"FFFFFFFF";
INT_LATCH[].CLRN = !INT_CLEAR[] & nRSTO;
FOR I IN 0 TO 9 GENERATE
INT_LA[I][].CLRN = INT_ENA[I] & nRSTO;
INT_LA[I][] = INT_LA[I][]+1 & INT_L[I] & INT_LA[I][]<7
# INT_LA[I][]-1 & !INT_L[I] & INT_LA[I][]>8
# 15 & INT_L[I] & INT_LA[I][]>6
# 0 & !INT_L[I] & INT_LA[I][]<9;
INT_LATCH[I].CLK = INT_LA[I][3];
END GENERATE;
-- INT_IN
INT_IN0 = PIC_INT;
@@ -181,7 +191,6 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H
INT_IN29 = INT_LATCH[]!=H"00000000";
INT_IN30 = !nMFP_INT;
INT_IN31 = DMA_DRQ;
--***************************************************************************************
-- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE
ACP_CONF[].CLK = MAIN_CLK;
@@ -212,130 +221,16 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H
WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR;
WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR;
WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR;
WERTE[7..0][10] = FB_AD[23..16];
WERTE[7..0][11] = FB_AD[23..16];
WERTE[7..0][12] = FB_AD[23..16];
WERTE[7..0][13] = FB_AD[23..16];
WERTE[7..0][14] = FB_AD[23..16];
WERTE[7..0][15] = FB_AD[23..16];
WERTE[7..0][16] = FB_AD[23..16];
WERTE[7..0][17] = FB_AD[23..16];
WERTE[7..0][18] = FB_AD[23..16];
WERTE[7..0][19] = FB_AD[23..16];
WERTE[7..0][20] = FB_AD[23..16];
WERTE[7..0][21] = FB_AD[23..16];
WERTE[7..0][22] = FB_AD[23..16];
WERTE[7..0][23] = FB_AD[23..16];
WERTE[7..0][24] = FB_AD[23..16];
WERTE[7..0][25] = FB_AD[23..16];
WERTE[7..0][26] = FB_AD[23..16];
WERTE[7..0][27] = FB_AD[23..16];
WERTE[7..0][28] = FB_AD[23..16];
WERTE[7..0][29] = FB_AD[23..16];
WERTE[7..0][30] = FB_AD[23..16];
WERTE[7..0][31] = FB_AD[23..16];
WERTE[7..0][32] = FB_AD[23..16];
WERTE[7..0][33] = FB_AD[23..16];
WERTE[7..0][34] = FB_AD[23..16];
WERTE[7..0][35] = FB_AD[23..16];
WERTE[7..0][36] = FB_AD[23..16];
WERTE[7..0][37] = FB_AD[23..16];
WERTE[7..0][38] = FB_AD[23..16];
WERTE[7..0][39] = FB_AD[23..16];
WERTE[7..0][40] = FB_AD[23..16];
WERTE[7..0][41] = FB_AD[23..16];
WERTE[7..0][42] = FB_AD[23..16];
WERTE[7..0][43] = FB_AD[23..16];
WERTE[7..0][44] = FB_AD[23..16];
WERTE[7..0][45] = FB_AD[23..16];
WERTE[7..0][46] = FB_AD[23..16];
WERTE[7..0][47] = FB_AD[23..16];
WERTE[7..0][48] = FB_AD[23..16];
WERTE[7..0][49] = FB_AD[23..16];
WERTE[7..0][50] = FB_AD[23..16];
WERTE[7..0][51] = FB_AD[23..16];
WERTE[7..0][52] = FB_AD[23..16];
WERTE[7..0][53] = FB_AD[23..16];
WERTE[7..0][54] = FB_AD[23..16];
WERTE[7..0][55] = FB_AD[23..16];
WERTE[7..0][56] = FB_AD[23..16];
WERTE[7..0][57] = FB_AD[23..16];
WERTE[7..0][58] = FB_AD[23..16];
WERTE[7..0][59] = FB_AD[23..16];
WERTE[7..0][60] = FB_AD[23..16];
WERTE[7..0][61] = FB_AD[23..16];
WERTE[7..0][62] = FB_AD[23..16];
WERTE[7..0][63] = FB_AD[23..16];
WERTE[][0].ENA = RTC_ADR[]==0 & UHR_DS & !nFB_WR;
WERTE[][1].ENA = RTC_ADR[]==1 & UHR_DS & !nFB_WR;
WERTE[][2].ENA = RTC_ADR[]==2 & UHR_DS & !nFB_WR;
WERTE[][3].ENA = RTC_ADR[]==3 & UHR_DS & !nFB_WR;
WERTE[][4].ENA = RTC_ADR[]==4 & UHR_DS & !nFB_WR;
WERTE[][5].ENA = RTC_ADR[]==5 & UHR_DS & !nFB_WR;
WERTE[][6].ENA = RTC_ADR[]==6 & UHR_DS & !nFB_WR;
WERTE[][7].ENA = RTC_ADR[]==7 & UHR_DS & !nFB_WR;
WERTE[][8].ENA = RTC_ADR[]==8 & UHR_DS & !nFB_WR;
WERTE[][9].ENA = RTC_ADR[]==9 & UHR_DS & !nFB_WR;
WERTE[][10].ENA = RTC_ADR[]==10 & UHR_DS & !nFB_WR;
WERTE[][11].ENA = RTC_ADR[]==11 & UHR_DS & !nFB_WR;
WERTE[][12].ENA = RTC_ADR[]==12 & UHR_DS & !nFB_WR;
WERTE[][13].ENA = RTC_ADR[]==13 & UHR_DS & !nFB_WR;
WERTE[][14].ENA = RTC_ADR[]==14 & UHR_DS & !nFB_WR;
WERTE[][15].ENA = RTC_ADR[]==15 & UHR_DS & !nFB_WR;
WERTE[][16].ENA = RTC_ADR[]==16 & UHR_DS & !nFB_WR;
WERTE[][17].ENA = RTC_ADR[]==17 & UHR_DS & !nFB_WR;
WERTE[][18].ENA = RTC_ADR[]==18 & UHR_DS & !nFB_WR;
WERTE[][19].ENA = RTC_ADR[]==19 & UHR_DS & !nFB_WR;
WERTE[][20].ENA = RTC_ADR[]==20 & UHR_DS & !nFB_WR;
WERTE[][21].ENA = RTC_ADR[]==21 & UHR_DS & !nFB_WR;
WERTE[][22].ENA = RTC_ADR[]==22 & UHR_DS & !nFB_WR;
WERTE[][23].ENA = RTC_ADR[]==23 & UHR_DS & !nFB_WR;
WERTE[][24].ENA = RTC_ADR[]==24 & UHR_DS & !nFB_WR;
WERTE[][25].ENA = RTC_ADR[]==25 & UHR_DS & !nFB_WR;
WERTE[][26].ENA = RTC_ADR[]==26 & UHR_DS & !nFB_WR;
WERTE[][27].ENA = RTC_ADR[]==27 & UHR_DS & !nFB_WR;
WERTE[][28].ENA = RTC_ADR[]==28 & UHR_DS & !nFB_WR;
WERTE[][29].ENA = RTC_ADR[]==29 & UHR_DS & !nFB_WR;
WERTE[][30].ENA = RTC_ADR[]==30 & UHR_DS & !nFB_WR;
WERTE[][31].ENA = RTC_ADR[]==31 & UHR_DS & !nFB_WR;
WERTE[][32].ENA = RTC_ADR[]==32 & UHR_DS & !nFB_WR;
WERTE[][33].ENA = RTC_ADR[]==33 & UHR_DS & !nFB_WR;
WERTE[][34].ENA = RTC_ADR[]==34 & UHR_DS & !nFB_WR;
WERTE[][35].ENA = RTC_ADR[]==35 & UHR_DS & !nFB_WR;
WERTE[][36].ENA = RTC_ADR[]==36 & UHR_DS & !nFB_WR;
WERTE[][37].ENA = RTC_ADR[]==37 & UHR_DS & !nFB_WR;
WERTE[][38].ENA = RTC_ADR[]==38 & UHR_DS & !nFB_WR;
WERTE[][39].ENA = RTC_ADR[]==39 & UHR_DS & !nFB_WR;
WERTE[][40].ENA = RTC_ADR[]==40 & UHR_DS & !nFB_WR;
WERTE[][41].ENA = RTC_ADR[]==41 & UHR_DS & !nFB_WR;
WERTE[][42].ENA = RTC_ADR[]==42 & UHR_DS & !nFB_WR;
WERTE[][43].ENA = RTC_ADR[]==43 & UHR_DS & !nFB_WR;
WERTE[][44].ENA = RTC_ADR[]==44 & UHR_DS & !nFB_WR;
WERTE[][45].ENA = RTC_ADR[]==45 & UHR_DS & !nFB_WR;
WERTE[][46].ENA = RTC_ADR[]==46 & UHR_DS & !nFB_WR;
WERTE[][47].ENA = RTC_ADR[]==47 & UHR_DS & !nFB_WR;
WERTE[][48].ENA = RTC_ADR[]==48 & UHR_DS & !nFB_WR;
WERTE[][49].ENA = RTC_ADR[]==49 & UHR_DS & !nFB_WR;
WERTE[][50].ENA = RTC_ADR[]==50 & UHR_DS & !nFB_WR;
WERTE[][51].ENA = RTC_ADR[]==51 & UHR_DS & !nFB_WR;
WERTE[][52].ENA = RTC_ADR[]==52 & UHR_DS & !nFB_WR;
WERTE[][53].ENA = RTC_ADR[]==53 & UHR_DS & !nFB_WR;
WERTE[][54].ENA = RTC_ADR[]==54 & UHR_DS & !nFB_WR;
WERTE[][55].ENA = RTC_ADR[]==55 & UHR_DS & !nFB_WR;
WERTE[][56].ENA = RTC_ADR[]==56 & UHR_DS & !nFB_WR;
WERTE[][57].ENA = RTC_ADR[]==57 & UHR_DS & !nFB_WR;
WERTE[][58].ENA = RTC_ADR[]==58 & UHR_DS & !nFB_WR;
WERTE[][59].ENA = RTC_ADR[]==59 & UHR_DS & !nFB_WR;
WERTE[][60].ENA = RTC_ADR[]==60 & UHR_DS & !nFB_WR;
WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR;
WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR;
WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR;
FOR I IN 10 TO 63 GENERATE
WERTE[7..0][I] = FB_AD[23..16];
END GENERATE;
FOR I IN 0 TO 63 GENERATE
WERTE[][I].ENA = RTC_ADR[]==I & UHR_DS & !nFB_WR;
END GENERATE;
PIC_INT_SYNC[].CLK = MAIN_CLK;
PIC_INT_SYNC[0] = PIC_INT;
PIC_INT_SYNC[1] = PIC_INT_SYNC[0];
PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0];
UPDATE_ON = !WERTE[7][11];
WERTE[6][10].CLRN = GND; -- KEIN UIP
UPDATE_ON = !WERTE[7][11]; -- UPDATE ON OFF
@@ -343,57 +238,48 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H
WERTE[1][11] = VCC; -- IMMER 24H FORMAT
WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR
WERTE[7][13] = VCC; -- IMMER RICHTIG
-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F<>R R<>CKSCHALTUNG)
-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F<>R R<>CKSCHALTUNG)
SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL
WERTE[0][13] = SOMMERZEIT;
WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT);
WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13]; --LETZTER SONNTAG IM OKTOBER
-- ACHTELSEKUNDEN
ACHTELSEKUNDEN[].CLK = MAIN_CLK;
ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1;
ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON;
-- SEKUNDEN
INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON;
WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN Z<>HLEN BIS 59
WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN Z<>HLEN BIS 59
WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);
-- MINUTEN
INC_MIN = INC_SEC & WERTE[][0]==59; --
WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN Z<>HLEN BIS 59
WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN Z<>HLEN BIS 59
WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); --
-- STUNDEN
INC_STD = INC_MIN & WERTE[][2]==59;
WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN Z<>HLEN BIS 23
WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN Z<>HLEN BIS 23
WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT
-- WOCHENTAG UND TAG
INC_TAG = INC_STD & WERTE[][2]==23;
WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG Z<>HLEN BIS 7
WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG Z<>HLEN BIS 7
# 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER
WERTE[][6].ENA = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);
ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12)
# 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11)
# 29 & WERTE[][8]==2 & WERTE[1..0][9]==0
# 28 & WERTE[][8]==2 & WERTE[1..0][9]!=0;
WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG Z<>HLEN BIS MONATSENDE
WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG Z<>HLEN BIS MONATSENDE
# 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER
WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); --
-- MONATE
INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; --
WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE Z<>HLEN BIS 12
WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE Z<>HLEN BIS 12
# 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER
WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);
-- JAHR
INC_JAHR = INC_MONAT & WERTE[][8]==12; --
WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE Z<>HLEN BIS 99
WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE Z<>HLEN BIS 99
WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);
-- TRISTATE OUTPUT
FB_AD[31..24] = lpm_bustri_BYT(
@@ -475,7 +361,6 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H
# INT_CLEAR_CS & INT_IN[23..16]
# ACP_CONF_CS & ACP_CONF[23..16]
,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
FB_AD[15..8] = lpm_bustri_BYT(
INT_CTR_CS & INT_CTR[15..8]
# INT_ENA_CS & INT_ENA[15..8]
@@ -483,7 +368,6 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H
# INT_CLEAR_CS & INT_IN[15..8]
# ACP_CONF_CS & ACP_CONF[15..8]
,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
FB_AD[7..0] = lpm_bustri_BYT(
INT_CTR_CS & INT_CTR[7..0]
# INT_ENA_CS & INT_ENA[7..0]

47
FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd
View File

@@ -28,29 +28,30 @@ ENTITY blitter IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
nRSTO : IN STD_LOGIC;
MAIN_CLK : IN STD_LOGIC;
FB_ALE : IN STD_LOGIC;
nFB_WR : IN STD_LOGIC;
nFB_OE : IN STD_LOGIC;
FB_SIZE0 : IN STD_LOGIC;
FB_SIZE1 : IN STD_LOGIC;
VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0);
BLITTER_ON : IN STD_LOGIC;
FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
nFB_CS1 : IN STD_LOGIC;
nFB_CS2 : IN STD_LOGIC;
nFB_CS3 : IN STD_LOGIC;
DDRCLK0 : IN STD_LOGIC;
BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0);
BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0);
BLITTER_RUN : OUT STD_LOGIC;
BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0);
BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0);
BLITTER_SIG : OUT STD_LOGIC;
BLITTER_WR : OUT STD_LOGIC;
BLITTER_TA : OUT STD_LOGIC;
FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0)
nRSTO : IN std_logic;
MAIN_CLK : IN std_logic;
FB_ALE : IN std_logic;
nFB_WR : IN std_logic;
nFB_OE : IN std_logic;
FB_SIZE0 : IN std_logic;
FB_SIZE1 : IN std_logic;
VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0);
BLITTER_ON : IN std_logic;
FB_ADR : IN std_logic_vector(31 DOWNTO 0);
nFB_CS1 : IN std_logic;
nFB_CS2 : IN std_logic;
nFB_CS3 : IN std_logic;
DDRCLK0 : IN std_logic;
BLITTER_DIN : IN std_logic_vector(127 DOWNTO 0);
BLITTER_DACK : IN std_logic_vector(4 DOWNTO 0);
SR_BLITTER_DACK : IN std_logic;
BLITTER_RUN : OUT std_logic;
BLITTER_DOUT : OUT std_logic_vector(127 DOWNTO 0);
BLITTER_ADR : OUT std_logic_vector(31 DOWNTO 0);
BLITTER_SIG : OUT std_logic;
BLITTER_WR : OUT std_logic;
BLITTER_TA : OUT std_logic;
FB_AD : INOUT std_logic_vector(31 DOWNTO 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

6
FPGA_Quartus_13.1/Video/BLITTER/altsyncram0.qip Normal file
View File

@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "ALTSYNCRAM"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.cmp"]

6
FPGA_Quartus_13.1/Video/BLITTER/lpm_clshift0.qip Normal file
View File

@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "LPM_CLSHIFT"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.cmp"]

127
FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
View File

@@ -1,4 +1,4 @@
TITLE "VIDEO MODI AND CLUT CONTROL";
TITLE "VIDEO MODUSE UND CLUT CONTROL";
-- CREATED BY FREDI ASCHWANDEN
@@ -98,12 +98,12 @@ VARIABLE
VDL_LWD[15..0] :DFFE;
VDL_LWD_CS :NODE;
-- DIV. CONTROL REGISTER
CLUT_TA :DFF; -- needs one wait state
CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT
HSYNC :DFF;
HSYNC_I[7..0] :DFF;
HSY_LEN[7..0] :DFF; -- length of hsync pulse in pixel_clk
HSY_LEN[7..0] :DFF; -- L<EFBFBD>NGE HSYNC PULS IN PIXEL_CLK
HSYNC_START :DFF;
LAST :DFF; -- reached last pixel of a line
LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT
VSYNC :DFF;
VSYNC_START :DFFE;
VSYNC_I[2..0] :DFFE;
@@ -191,7 +191,6 @@ VARIABLE
VDL_VCT_CS :NODE;
VDL_VMD[3..0] :DFFE;
VDL_VMD_CS :NODE;
ACP_VCTR6_DUP : NODE;
BEGIN
-- BYT SELECT 32 BIT
@@ -204,75 +203,46 @@ BEGIN
FB_B3 = FB_ADR[1..0] == 3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- BYT SELECT 16 BIT
FB_16B0 = FB_ADR[0] == 0; -- ADR==0
FB_16B1 = FB_ADR[0] == 1 -- ADR==1
# !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT
-- ACP CLUT --
ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10] == H"0"; -- 0-3FF/1024
ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR;
CLUT_TA.CLK = MAIN_CLK;
CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA;
--FALCON CLUT --
FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10] == H"3E6"; -- $F9800/$400
FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD
FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD
FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
-- ST CLUT --
ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5] == H"7C12"; -- $F8240/$20
ST_CLUT_RD = ST_CLUT_CS & !nFB_OE;
ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR;
-- ST SHIFT MODE
ST_SHIFT_MODE[].CLK = MAIN_CLK;
ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C130"; -- $F8260/2
ST_SHIFT_MODE[] = FB_AD[25..24];
ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
COLOR1 = ST_SHIFT_MODE[] == B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO
COLOR2 = ST_SHIFT_MODE[] == B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN
COLOR4 = ST_SHIFT_MODE[] == B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN
-- FALCON SHIFT MODE
FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C133"; -- $F8266/2
FALCON_SHIFT_MODE[] = FB_AD[26..16];
FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
-- ACP VIDEO CONTROL
-- BIT 0=ACP VIDEO ON,
-- 1=POWER ON VIDEO DAC,
-- 2=ACP 24BIT,
-- 3=ACP 16BIT,
-- 4=ACP 8BIT,
-- 5=ACP 1BIT,
-- 6=FALCON SHIFT MODE,
-- 7=ST SHIFT MODE,
-- 9..8= VCLK FREQUENZ,
-- 15=-SYNC ALLOWED,
-- 31..16=VIDEO_RAM_CTR,
-- 25=RANDFARBE EINSCHALTEN,
-- 26=STANDARD ATARI SYNCS
-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
ACP_VCTR[].CLK = MAIN_CLK;
ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2] == H"100"; -- $400/4
ACP_VCTR[31..8] = FB_AD[31..8];
@@ -283,10 +253,8 @@ BEGIN
ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR;
ACP_VIDEO_ON = ACP_VCTR0;
nPD_VGA = ACP_VCTR1;
-- ATARI MODUS
ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFL<46>SUNG
ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFL<46>SUNG
-- HORIZONTAL TIMING 640x480
ATARI_HH[].CLK = MAIN_CLK;
ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4
@@ -295,7 +263,6 @@ BEGIN
ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR;
ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR;
-- VERTIKAL TIMING 640x480
ATARI_VH[].CLK = MAIN_CLK;
ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4
@@ -304,7 +271,6 @@ BEGIN
ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR;
ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR;
-- HORIZONTAL TIMING 320x240
ATARI_HL[].CLK = MAIN_CLK;
ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4
@@ -313,7 +279,6 @@ BEGIN
ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR;
ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR;
-- VERTIKAL TIMING 320x240
ATARI_VL[].CLK = MAIN_CLK;
ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4
@@ -322,8 +287,6 @@ BEGIN
ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR;
ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR;
-- VIDEO PLL CONFIG
VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
VR_WR.CLK = MAIN_CLK;
@@ -335,28 +298,21 @@ BEGIN
VR_FRQ[].CLK = MAIN_CLK;
VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
VR_FRQ[] = FB_AD[23..16];
-- VIDEO PLL RECONFIG
VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800
VIDEO_RECONFIG.CLK = MAIN_CLK;
VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
------------------------------------------------------------------------------------------------------------------------
VIDEO_RAM_CTR[] = ACP_VCTR[31..16];
-------------- COLOR MODE IM ACP SETZEN
COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON;
ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
-- duplicate ACP_VCTR6 according to TimeQuest recommendations
ACP_VCTR6_DUP = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
ACP_VCTR6 = ACP_VCTR6_DUP;
ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
FALCON_VIDEO = ACP_VCTR7;
FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
@@ -369,9 +325,7 @@ BEGIN
# B"101" & COLOR16
# B"110" & COLOR24
# B"111" & RAND_ON;
-- DIVERSE (VIDEO)-REGISTER ----------------------------
-- RANDFARBE
CCR[].CLK = MAIN_CLK;
CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4
@@ -379,129 +333,109 @@ BEGIN
CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR;
CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR;
--SYS CTR
SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2
SYS_CTR[].CLK = MAIN_CLK;
SYS_CTR[6..0] = FB_AD[22..16];
SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3;
BLITTER_ON = !SYS_CTR3;
--VDL_LOF
VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2
VDL_LOF[].CLK = MAIN_CLK;
VDL_LOF[] = FB_AD[31..16];
VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3;
--VDL_LWD
VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2
VDL_LWD[].CLK = MAIN_CLK;
VDL_LWD[] = FB_AD[31..16];
VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1;
-- HORIZONTAL
-- VDL_HHT
VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2
VDL_HHT[].CLK = MAIN_CLK;
VDL_HHT[] = FB_AD[27..16];
VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3;
-- VDL_HBE
VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2
VDL_HBE[].CLK = MAIN_CLK;
VDL_HBE[] = FB_AD[27..16];
VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3;
-- VDL_HDB
VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2
VDL_HDB[].CLK = MAIN_CLK;
VDL_HDB[] = FB_AD[27..16];
VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1;
-- VDL_HDE
VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2
VDL_HDE[].CLK = MAIN_CLK;
VDL_HDE[] = FB_AD[27..16];
VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3;
-- VDL_HBB
VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2
VDL_HBB[].CLK = MAIN_CLK;
VDL_HBB[] = FB_AD[27..16];
VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1;
-- VDL_HSS
VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2
VDL_HSS[].CLK = MAIN_CLK;
VDL_HSS[] = FB_AD[27..16];
VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1;
-- VERTIKAL
-- VDL_VBE
VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2
VDL_VBE[].CLK = MAIN_CLK;
VDL_VBE[] = FB_AD[26..16];
VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3;
-- VDL_VDB
VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2
VDL_VDB[].CLK = MAIN_CLK;
VDL_VDB[] = FB_AD[26..16];
VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1;
-- VDL_VDE
VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2
VDL_VDE[].CLK = MAIN_CLK;
VDL_VDE[] = FB_AD[26..16];
VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3;
-- VDL_VBB
VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2
VDL_VBB[].CLK = MAIN_CLK;
VDL_VBB[] = FB_AD[26..16];
VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1;
-- VDL_VSS
VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2
VDL_VSS[].CLK = MAIN_CLK;
VDL_VSS[] = FB_AD[26..16];
VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1;
-- VDL_VFT
VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2
VDL_VFT[].CLK = MAIN_CLK;
VDL_VFT[] = FB_AD[26..16];
VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3;
-- VDL_VCT
VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2
VDL_VCT[].CLK = MAIN_CLK;
VDL_VCT[] = FB_AD[24..16];
VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0;
VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1;
-- VDL_VMD
VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2
VDL_VMD[].CLK = MAIN_CLK;
VDL_VMD[] = FB_AD[19..16];
VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3;
--- REGISTER OUT
FB_AD[31..16] = lpm_bustri_WORD(
ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000")
@@ -550,9 +484,8 @@ BEGIN
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
# VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
-- VIDEO AUSGABE SETZEN
CLK17M.CLK = MAIN_CLK;
CLK17M.CLK = CLK33M;
CLK17M = !CLK17M;
CLK13M.CLK = CLK25M;
CLK13M = !CLK13M;
@@ -563,9 +496,8 @@ BEGIN
# CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
# CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
# CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9];
--------------------------------------------------------------
-- HORIZONTALE SYNC L<>NGE in PIXEL_CLK
-- HORIZONTALE SYNC L<>NGE in PIXEL_CLK
----------------------------------------------------------------
HSY_LEN[].CLK = MAIN_CLK;
HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0)
@@ -585,7 +517,6 @@ BEGIN
HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN
# 640 & !VDL_VMD2;
-- DOPPELZEILENMODUS
DOP_ZEI.CLK = MAIN_CLK;
DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS
@@ -593,7 +524,7 @@ BEGIN
INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
# DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
DOP_FIFO_CLR.CLK = PIXEL_CLK;
DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON
# 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
@@ -635,8 +566,7 @@ BEGIN
# ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
-- Z<>HLER
-- Z<>HLER
LAST.CLK = PIXEL_CLK;
LAST = VHCNT[]==(H_TOTAL[]-2);
VHCNT[].CLK = PIXEL_CLK;
@@ -644,11 +574,10 @@ BEGIN
VVCNT[].CLK = PIXEL_CLK;
VVCNT[].ENA = LAST;
VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
-- DISPLAY ON OFF
DPO_ZL.CLK = PIXEL_CLK;
DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1); -- 1 ZEILE DAVOR ON OFF
DPO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
DPO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
DPO_ON.CLK = PIXEL_CLK;
DPO_ON = VHCNT[]==RAND_LINKS[]; -- BESSER EINZELN WEGEN TIMING
DPO_OFF.CLK = PIXEL_CLK;
@@ -656,34 +585,30 @@ BEGIN
DISP_ON.CLK = PIXEL_CLK;
DISP_ON = DISP_ON & !DPO_OFF
# DPO_ON & DPO_ZL;
-- DATENTRANSFER ON OFF
VDO_ON.CLK = PIXEL_CLK;
VDO_ON = VHCNT[]==(HDIS_START[]-1); -- BESSER EINZELN WEGEN TIMING
VDO_OFF.CLK = PIXEL_CLK;
VDO_OFF = VHCNT[]==HDIS_END[];
VDO_ZL.CLK = PIXEL_CLK;
VDO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
VDO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]); -- 1 ZEILE DAVOR ON OFF
VDTRON.CLK = PIXEL_CLK;
VDTRON = VDTRON & !VDO_OFF
# VDO_ON & VDO_ZL;
-- VERZ<52>GERUNG UND SYNC
-- VERZ<52>GERUNG UND SYNC
HSYNC_START.CLK = PIXEL_CLK;
HSYNC_START = VHCNT[]==HS_START[]-3;
HSYNC_I[].CLK = PIXEL_CLK;
HSYNC_I[] = HSY_LEN[] & HSYNC_START
# (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
VSYNC_START.CLK = PIXEL_CLK;
VSYNC_START.ENA = LAST;
VSYNC_START = VVCNT[]==(VS_START[]-3); -- start am ende der Zeile vor dem vsync
VSYNC_I[].CLK = PIXEL_CLK;
VSYNC_I[].ENA = LAST; -- start am ende der Zeile vor dem vsync
VSYNC_I[] = 3 & VSYNC_START -- 3 zeilen vsync length
# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0; -- runterz<72>hlen bis 0
# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0; -- runterz<72>hlen bis 0
VERZ[][].CLK = PIXEL_CLK;
VERZ[][1] = VERZ[][0];
VERZ[][2] = VERZ[][1];
@@ -694,24 +619,19 @@ BEGIN
VERZ[][7] = VERZ[][6];
VERZ[][8] = VERZ[][7];
VERZ[][9] = VERZ[][8];
VERZ[0][0] = DISP_ON;
VERZ[1][0] = HSYNC_I[]!=0;
-- VERZ[1][0] = HSYNC_I[]!=0;
VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
# ACP_VCTR15 & VDL_VCT6 & HSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
# ACP_VCTR15 & VDL_VCT6 & HSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
# ACP_VCTR15 & VDL_VCT5 & VSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
# ACP_VCTR15 & VDL_VCT5 & VSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
nBLANK.CLK = PIXEL_CLK;
nBLANK = VERZ[0][8];
HSYNC.CLK = PIXEL_CLK;
HSYNC = VERZ[1][9];
VSYNC.CLK = PIXEL_CLK;
VSYNC = VERZ[2][9];
nSYNC = GND;
-- RANDFARBE MACHEN ------------------------------------
RAND[].CLK = PIXEL_CLK;
RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
@@ -722,20 +642,19 @@ BEGIN
RAND[5] = RAND[4];
RAND[6] = RAND[5];
RAND_ON = RAND[6];
----------------------------------------------------------
CLR_FIFO.CLK = PIXEL_CLK;
CLR_FIFO.ENA = LAST;
CLR_FIFO = VVCNT[]==V_TOTAL[]-2; -- IN LETZTER ZEILE L<>SCHEN
CLR_FIFO = VVCNT[]==V_TOTAL[]-2; -- IN LETZTER ZEILE L<>SCHEN
START_ZEILE.CLK = PIXEL_CLK;
START_ZEILE.ENA = LAST;
START_ZEILE = VVCNT[]==0; -- ZEILE 1
SYNC_PIX.CLK = PIXEL_CLK;
SYNC_PIX = VHCNT[]==3 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX = VHCNT[]==3 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX1.CLK = PIXEL_CLK;
SYNC_PIX1 = VHCNT[]==5 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX1 = VHCNT[]==5 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX2.CLK = PIXEL_CLK;
SYNC_PIX2 = VHCNT[]==7 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX2 = VHCNT[]==7 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX; --count up if display on sonst clear bei sync pix
@@ -746,7 +665,7 @@ BEGIN
# SUB_PIXEL_CNT[3..0]==1 & COLOR8
# SUB_PIXEL_CNT[2..0]==1 & COLOR16
# SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON
# SYNC_PIX # SYNC_PIX1 # SYNC_PIX2; -- 3 CLOCK ZUS<55>TZLICH F<>R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
# SYNC_PIX # SYNC_PIX1 # SYNC_PIX2; -- 3 CLOCK ZUS<55>TZLICH F<>R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
CLUT_MUX_ADR[].CLK = PIXEL_CLK;
CLUT_MUX_AV[][].CLK = PIXEL_CLK;

4080
FPGA_Quartus_13.1/Video/Video.bdf
View File

File diff suppressed because it is too large Load Diff

6
FPGA_Quartus_13.1/altiobuf_bidir0.qip Normal file
View File

@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "ALTIOBUF"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altiobuf_bidir0.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altiobuf_bidir0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altiobuf_bidir0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altiobuf_bidir0.cmp"]

114
FPGA_Quartus_13.1/altpll1.bsf
View File

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2014 Altera Corporation
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
@@ -18,83 +18,83 @@ programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 272 176)
(text "altpll1" (rect 119 0 160 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 161 26 172)(font "Arial" ))
(rect 0 0 272 184)
(text "altpll1" (rect 119 0 159 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 168 25 180)(font "Arial" ))
(port
(pt 0 64)
(input)
(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 40 64))
(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 40 64)(line_width 1))
)
(port
(pt 272 64)
(output)
(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c0" (rect 257 51 269 63)(font "Arial" (font_size 8)))
(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c0" (rect 257 51 268 64)(font "Arial" (font_size 8)))
(line (pt 272 64)(pt 224 64)(line_width 1))
)
(port
(pt 272 80)
(output)
(text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8)))
(text "c1" (rect 257 67 267 79)(font "Arial" (font_size 8)))
(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c1" (rect 257 67 268 80)(font "Arial" (font_size 8)))
(line (pt 272 80)(pt 224 80)(line_width 1))
)
(port
(pt 272 96)
(output)
(text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c2" (rect 257 83 269 95)(font "Arial" (font_size 8)))
(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c2" (rect 257 83 268 96)(font "Arial" (font_size 8)))
(line (pt 272 96)(pt 224 96)(line_width 1))
)
(port
(pt 272 112)
(output)
(text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8)))
(text "locked" (rect 237 99 268 111)(font "Arial" (font_size 8)))
(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "locked" (rect 238 99 268 112)(font "Arial" (font_size 8)))
(line (pt 272 112)(pt 224 112)(line_width 1))
)
(drawing
(text "Cyclone III" (rect 214 162 474 334)(font "Arial" ))
(text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" ))
(text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
(text "Clk " (rect 51 91 117 192)(font "Arial" ))
(text "Ratio" (rect 82 91 187 192)(font "Arial" ))
(text "Ph (dg)" (rect 119 91 269 192)(font "Arial" ))
(text "DC (%)" (rect 154 91 340 192)(font "Arial" ))
(text "c0" (rect 54 104 119 218)(font "Arial" ))
(text "1/66" (rect 84 104 186 218)(font "Arial" ))
(text "0.00" (rect 125 104 269 218)(font "Arial" ))
(text "50.00" (rect 158 104 340 218)(font "Arial" ))
(text "c1" (rect 54 117 118 244)(font "Arial" ))
(text "512/6875" (rect 74 117 187 244)(font "Arial" ))
(text "0.00" (rect 125 117 269 244)(font "Arial" ))
(text "50.00" (rect 158 117 340 244)(font "Arial" ))
(text "c2" (rect 54 130 119 270)(font "Arial" ))
(text "1024/1375" (rect 71 130 185 270)(font "Arial" ))
(text "0.00" (rect 125 130 269 270)(font "Arial" ))
(text "50.00" (rect 158 130 340 270)(font "Arial" ))
(line (pt 0 0)(pt 273 0))
(line (pt 273 0)(pt 273 177))
(line (pt 0 177)(pt 273 177))
(line (pt 0 0)(pt 0 177))
(line (pt 48 89)(pt 186 89))
(line (pt 48 101)(pt 186 101))
(line (pt 48 114)(pt 186 114))
(line (pt 48 127)(pt 186 127))
(line (pt 48 140)(pt 186 140))
(line (pt 48 89)(pt 48 140))
(line (pt 68 89)(pt 68 140)(line_width 3))
(line (pt 116 89)(pt 116 140)(line_width 3))
(line (pt 151 89)(pt 151 140)(line_width 3))
(line (pt 185 89)(pt 185 140))
(line (pt 40 48)(pt 223 48))
(line (pt 223 48)(pt 223 159))
(line (pt 40 159)(pt 223 159))
(line (pt 40 48)(pt 40 159))
(line (pt 271 64)(pt 223 64))
(line (pt 271 80)(pt 223 80))
(line (pt 271 96)(pt 223 96))
(line (pt 271 112)(pt 223 112))
(text "Cyclone III" (rect 211 169 258 181)(font "Arial" ))
(text "inclk0 frequency: 33.000 MHz" (rect 50 59 175 71)(font "Arial" ))
(text "Operation Mode: Src Sync Comp" (rect 50 73 188 85)(font "Arial" ))
(text "Clk " (rect 51 96 68 108)(font "Arial" ))
(text "Ratio" (rect 83 96 105 108)(font "Arial" ))
(text "Ph (dg)" (rect 121 96 151 108)(font "Arial" ))
(text "DC (%)" (rect 156 96 187 108)(font "Arial" ))
(text "c0" (rect 54 111 64 123)(font "Arial" ))
(text "16/11" (rect 83 111 106 123)(font "Arial" ))
(text "0.00" (rect 127 111 145 123)(font "Arial" ))
(text "50.00" (rect 160 111 183 123)(font "Arial" ))
(text "c1" (rect 54 126 64 138)(font "Arial" ))
(text "16/33" (rect 83 126 106 138)(font "Arial" ))
(text "0.00" (rect 127 126 145 138)(font "Arial" ))
(text "50.00" (rect 160 126 183 138)(font "Arial" ))
(text "c2" (rect 54 141 64 153)(font "Arial" ))
(text "1024/1375" (rect 73 141 116 153)(font "Arial" ))
(text "0.00" (rect 127 141 145 153)(font "Arial" ))
(text "50.00" (rect 160 141 183 153)(font "Arial" ))
(line (pt 0 0)(pt 273 0)(line_width 1))
(line (pt 273 0)(pt 273 185)(line_width 1))
(line (pt 0 185)(pt 273 185)(line_width 1))
(line (pt 0 0)(pt 0 185)(line_width 1))
(line (pt 48 94)(pt 189 94)(line_width 1))
(line (pt 48 108)(pt 189 108)(line_width 1))
(line (pt 48 123)(pt 189 123)(line_width 1))
(line (pt 48 138)(pt 189 138)(line_width 1))
(line (pt 48 153)(pt 189 153)(line_width 1))
(line (pt 48 94)(pt 48 153)(line_width 1))
(line (pt 70 94)(pt 70 153)(line_width 3))
(line (pt 118 94)(pt 118 153)(line_width 3))
(line (pt 153 94)(pt 153 153)(line_width 3))
(line (pt 188 94)(pt 188 153)(line_width 1))
(line (pt 40 48)(pt 224 48)(line_width 1))
(line (pt 224 48)(pt 224 168)(line_width 1))
(line (pt 40 168)(pt 224 168)(line_width 1))
(line (pt 40 48)(pt 40 168)(line_width 1))
)
)

2
FPGA_Quartus_13.1/altpll1.cmp
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2014 Altera Corporation
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing

2
FPGA_Quartus_13.1/altpll1.inc
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2014 Altera Corporation
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing

2
FPGA_Quartus_13.1/altpll1.qip
View File

@@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"]

64
FPGA_Quartus_13.1/altpll1.vhd
View File

@@ -14,11 +14,11 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
@@ -131,35 +131,35 @@ ARCHITECTURE SYN OF altpll1 IS
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
locked : OUT STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
locked <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 66,
clk0_divide_by => 11,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_multiply_by => 16,
clk0_phase_shift => "0",
clk1_divide_by => 6875,
clk1_divide_by => 33,
clk1_duty_cycle => 50,
clk1_multiply_by => 512,
clk1_multiply_by => 16,
clk1_phase_shift => "0",
clk2_divide_by => 1375,
clk2_duty_cycle => 50,
@@ -218,7 +218,7 @@ BEGIN
PORT MAP (
inclk => sub_wire6,
clk => sub_wire0,
locked => sub_wire2
locked => sub_wire4
);
@@ -244,14 +244,14 @@ END SYN;
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "90"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.457600"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.576000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
@@ -270,21 +270,21 @@ END SYN;
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "67"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.50000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
@@ -298,7 +298,7 @@ END SYN;
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
@@ -338,13 +338,13 @@ END SYN;
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "66"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "6875"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "512"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1375"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
@@ -406,17 +406,17 @@ END SYN;
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE

152
FPGA_Quartus_13.1/altpll2.bsf
View File

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2014 Altera Corporation
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
@@ -18,100 +18,100 @@ programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 256 200)
(text "altpll2" (rect 111 0 153 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 185 26 196)(font "Arial" ))
(rect 0 0 304 248)
(text "altpll2" (rect 132 1 179 20)(font "Arial" (font_size 10)))
(text "inst" (rect 8 229 31 244)(font "Arial" ))
(port
(pt 0 64)
(pt 0 72)
(input)
(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 40 64))
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 48 72)(line_width 1))
)
(port
(pt 256 64)
(pt 304 72)
(output)
(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c0" (rect 241 51 253 63)(font "Arial" (font_size 8)))
(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8)))
(line (pt 304 72)(pt 272 72)(line_width 1))
)
(port
(pt 256 80)
(pt 304 96)
(output)
(text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8)))
(text "c1" (rect 241 67 251 79)(font "Arial" (font_size 8)))
(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8)))
(line (pt 304 96)(pt 272 96)(line_width 1))
)
(port
(pt 256 96)
(pt 304 120)
(output)
(text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c2" (rect 241 83 253 95)(font "Arial" (font_size 8)))
(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8)))
(line (pt 304 120)(pt 272 120)(line_width 1))
)
(port
(pt 256 112)
(pt 304 144)
(output)
(text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c3" (rect 241 99 253 111)(font "Arial" (font_size 8)))
(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8)))
(line (pt 304 144)(pt 272 144)(line_width 1))
)
(port
(pt 256 128)
(pt 304 168)
(output)
(text "c4" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c4" (rect 241 115 253 127)(font "Arial" (font_size 8)))
(text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c4" (rect 287 152 301 168)(font "Arial" (font_size 8)))
(line (pt 304 168)(pt 272 168)(line_width 1))
)
(drawing
(text "Cyclone III" (rect 198 186 442 382)(font "Arial" ))
(text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" ))
(text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
(text "Clk " (rect 51 91 117 192)(font "Arial" ))
(text "Ratio" (rect 71 91 165 192)(font "Arial" ))
(text "Ph (dg)" (rect 97 91 225 192)(font "Arial" ))
(text "DC (%)" (rect 132 91 296 192)(font "Arial" ))
(text "c0" (rect 54 104 119 218)(font "Arial" ))
(text "4/1" (rect 76 104 165 218)(font "Arial" ))
(text "240.00" (rect 98 104 225 218)(font "Arial" ))
(text "50.00" (rect 136 104 296 218)(font "Arial" ))
(text "c1" (rect 54 117 118 244)(font "Arial" ))
(text "4/1" (rect 76 117 165 244)(font "Arial" ))
(text "0.00" (rect 103 117 225 244)(font "Arial" ))
(text "50.00" (rect 136 117 296 244)(font "Arial" ))
(text "c2" (rect 54 130 119 270)(font "Arial" ))
(text "4/1" (rect 76 130 165 270)(font "Arial" ))
(text "180.00" (rect 98 130 224 270)(font "Arial" ))
(text "50.00" (rect 136 130 296 270)(font "Arial" ))
(text "c3" (rect 54 143 119 296)(font "Arial" ))
(text "4/1" (rect 76 143 165 296)(font "Arial" ))
(text "105.00" (rect 98 143 224 296)(font "Arial" ))
(text "50.00" (rect 136 143 296 296)(font "Arial" ))
(text "c4" (rect 54 156 119 322)(font "Arial" ))
(text "2/1" (rect 76 156 165 322)(font "Arial" ))
(text "270.00" (rect 98 156 225 322)(font "Arial" ))
(text "50.00" (rect 136 156 296 322)(font "Arial" ))
(line (pt 0 0)(pt 257 0))
(line (pt 257 0)(pt 257 201))
(line (pt 0 201)(pt 257 201))
(line (pt 0 0)(pt 0 201))
(line (pt 48 89)(pt 164 89))
(line (pt 48 101)(pt 164 101))
(line (pt 48 114)(pt 164 114))
(line (pt 48 127)(pt 164 127))
(line (pt 48 140)(pt 164 140))
(line (pt 48 153)(pt 164 153))
(line (pt 48 166)(pt 164 166))
(line (pt 48 89)(pt 48 166))
(line (pt 68 89)(pt 68 166)(line_width 3))
(line (pt 94 89)(pt 94 166)(line_width 3))
(line (pt 129 89)(pt 129 166)(line_width 3))
(line (pt 163 89)(pt 163 166))
(line (pt 40 48)(pt 223 48))
(line (pt 223 48)(pt 223 183))
(line (pt 40 183)(pt 223 183))
(line (pt 40 48)(pt 40 183))
(line (pt 255 64)(pt 223 64))
(line (pt 255 80)(pt 223 80))
(line (pt 255 96)(pt 223 96))
(line (pt 255 112)(pt 223 112))
(line (pt 255 128)(pt 223 128))
(text "Cyclone III" (rect 229 230 277 244)(font "Arial" ))
(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
(text "Clk " (rect 59 111 76 125)(font "Arial" ))
(text "Ratio" (rect 85 111 109 125)(font "Arial" ))
(text "Ph (dg)" (rect 119 111 154 125)(font "Arial" ))
(text "DC (%)" (rect 164 111 199 125)(font "Arial" ))
(text "c0" (rect 63 129 75 143)(font "Arial" ))
(text "4/1" (rect 91 129 106 143)(font "Arial" ))
(text "240.00" (rect 120 129 153 143)(font "Arial" ))
(text "50.00" (rect 169 129 196 143)(font "Arial" ))
(text "c1" (rect 63 147 75 161)(font "Arial" ))
(text "4/1" (rect 91 147 106 161)(font "Arial" ))
(text "0.00" (rect 127 147 148 161)(font "Arial" ))
(text "50.00" (rect 169 147 196 161)(font "Arial" ))
(text "c2" (rect 63 165 75 179)(font "Arial" ))
(text "4/1" (rect 91 165 106 179)(font "Arial" ))
(text "180.00" (rect 120 165 153 179)(font "Arial" ))
(text "50.00" (rect 169 165 196 179)(font "Arial" ))
(text "c3" (rect 63 183 75 197)(font "Arial" ))
(text "4/1" (rect 91 183 106 197)(font "Arial" ))
(text "105.00" (rect 120 183 153 197)(font "Arial" ))
(text "50.00" (rect 169 183 196 197)(font "Arial" ))
(text "c4" (rect 63 201 75 215)(font "Arial" ))
(text "2/1" (rect 91 201 106 215)(font "Arial" ))
(text "270.00" (rect 120 201 153 215)(font "Arial" ))
(text "50.00" (rect 169 201 196 215)(font "Arial" ))
(line (pt 0 0)(pt 305 0)(line_width 1))
(line (pt 305 0)(pt 305 249)(line_width 1))
(line (pt 0 249)(pt 305 249)(line_width 1))
(line (pt 0 0)(pt 0 249)(line_width 1))
(line (pt 56 108)(pt 206 108)(line_width 1))
(line (pt 56 125)(pt 206 125)(line_width 1))
(line (pt 56 143)(pt 206 143)(line_width 1))
(line (pt 56 161)(pt 206 161)(line_width 1))
(line (pt 56 179)(pt 206 179)(line_width 1))
(line (pt 56 197)(pt 206 197)(line_width 1))
(line (pt 56 215)(pt 206 215)(line_width 1))
(line (pt 56 108)(pt 56 215)(line_width 1))
(line (pt 82 108)(pt 82 215)(line_width 3))
(line (pt 116 108)(pt 116 215)(line_width 3))
(line (pt 161 108)(pt 161 215)(line_width 3))
(line (pt 205 108)(pt 205 215)(line_width 1))
(line (pt 48 56)(pt 272 56)(line_width 1))
(line (pt 272 56)(pt 272 232)(line_width 1))
(line (pt 48 232)(pt 272 232)(line_width 1))
(line (pt 48 56)(pt 48 232)(line_width 1))
)
)

2
FPGA_Quartus_13.1/altpll2.cmp
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2014 Altera Corporation
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing

2
FPGA_Quartus_13.1/altpll2.inc
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2014 Altera Corporation
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing

2
FPGA_Quartus_13.1/altpll2.qip
View File

@@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"]

32
FPGA_Quartus_13.1/altpll2.vhd
View File

@@ -14,11 +14,11 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
@@ -140,8 +140,8 @@ ARCHITECTURE SYN OF altpll2 IS
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
@@ -149,14 +149,14 @@ BEGIN
sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire5 <= sub_wire0(4);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
c3 <= sub_wire4;
c4 <= sub_wire5;
sub_wire6 <= inclk0;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
@@ -293,7 +293,7 @@ END SYN;
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
@@ -459,18 +459,18 @@ END SYN;
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE

139
FPGA_Quartus_13.1/altpll3.bsf
View File

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2014 Altera Corporation
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
@@ -18,88 +18,95 @@ programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 256 184)
(text "altpll3" (rect 111 0 153 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 169 26 180)(font "Arial" ))
(rect 0 0 272 200)
(text "altpll3" (rect 119 0 159 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 184 25 196)(font "Arial" ))
(port
(pt 0 64)
(input)
(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 40 64))
(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 40 64)(line_width 1))
)
(port
(pt 256 64)
(pt 272 64)
(output)
(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c0" (rect 241 51 253 63)(font "Arial" (font_size 8)))
(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c0" (rect 257 51 268 64)(font "Arial" (font_size 8)))
(line (pt 272 64)(pt 224 64)(line_width 1))
)
(port
(pt 256 80)
(pt 272 80)
(output)
(text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8)))
(text "c1" (rect 241 67 251 79)(font "Arial" (font_size 8)))
(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c1" (rect 257 67 268 80)(font "Arial" (font_size 8)))
(line (pt 272 80)(pt 224 80)(line_width 1))
)
(port
(pt 256 96)
(pt 272 96)
(output)
(text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c2" (rect 241 83 253 95)(font "Arial" (font_size 8)))
(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c2" (rect 257 83 268 96)(font "Arial" (font_size 8)))
(line (pt 272 96)(pt 224 96)(line_width 1))
)
(port
(pt 256 112)
(pt 272 112)
(output)
(text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c3" (rect 241 99 253 111)(font "Arial" (font_size 8)))
(text "c3" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c3" (rect 257 99 268 112)(font "Arial" (font_size 8)))
(line (pt 272 112)(pt 224 112)(line_width 1))
)
(port
(pt 272 128)
(output)
(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "locked" (rect 238 115 268 128)(font "Arial" (font_size 8)))
(line (pt 272 128)(pt 224 128)(line_width 1))
)
(drawing
(text "Cyclone III" (rect 198 170 442 350)(font "Arial" ))
(text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" ))
(text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
(text "Clk " (rect 51 91 117 192)(font "Arial" ))
(text "Ratio" (rect 77 91 177 192)(font "Arial" ))
(text "Ph (dg)" (rect 109 91 249 192)(font "Arial" ))
(text "DC (%)" (rect 144 91 320 192)(font "Arial" ))
(text "c0" (rect 54 104 119 218)(font "Arial" ))
(text "2/33" (rect 79 104 177 218)(font "Arial" ))
(text "0.00" (rect 115 104 249 218)(font "Arial" ))
(text "50.00" (rect 148 104 320 218)(font "Arial" ))
(text "c1" (rect 54 117 118 244)(font "Arial" ))
(text "16/33" (rect 77 117 177 244)(font "Arial" ))
(text "0.00" (rect 115 117 249 244)(font "Arial" ))
(text "50.00" (rect 148 117 320 244)(font "Arial" ))
(text "c2" (rect 54 130 119 270)(font "Arial" ))
(text "227/300" (rect 71 130 176 270)(font "Arial" ))
(text "0.00" (rect 115 130 249 270)(font "Arial" ))
(text "50.00" (rect 148 130 320 270)(font "Arial" ))
(text "c3" (rect 54 143 119 296)(font "Arial" ))
(text "227/156" (rect 71 143 176 296)(font "Arial" ))
(text "0.00" (rect 115 143 249 296)(font "Arial" ))
(text "50.00" (rect 148 143 320 296)(font "Arial" ))
(line (pt 0 0)(pt 257 0))
(line (pt 257 0)(pt 257 185))
(line (pt 0 185)(pt 257 185))
(line (pt 0 0)(pt 0 185))
(line (pt 48 89)(pt 176 89))
(line (pt 48 101)(pt 176 101))
(line (pt 48 114)(pt 176 114))
(line (pt 48 127)(pt 176 127))
(line (pt 48 140)(pt 176 140))
(line (pt 48 153)(pt 176 153))
(line (pt 48 89)(pt 48 153))
(line (pt 68 89)(pt 68 153)(line_width 3))
(line (pt 106 89)(pt 106 153)(line_width 3))
(line (pt 141 89)(pt 141 153)(line_width 3))
(line (pt 175 89)(pt 175 153))
(line (pt 40 48)(pt 223 48))
(line (pt 223 48)(pt 223 167))
(line (pt 40 167)(pt 223 167))
(line (pt 40 48)(pt 40 167))
(line (pt 255 64)(pt 223 64))
(line (pt 255 80)(pt 223 80))
(line (pt 255 96)(pt 223 96))
(line (pt 255 112)(pt 223 112))
(text "Cyclone III" (rect 211 185 258 197)(font "Arial" ))
(text "inclk0 frequency: 33.000 MHz" (rect 50 59 175 71)(font "Arial" ))
(text "Operation Mode: Src Sync Comp" (rect 50 73 188 85)(font "Arial" ))
(text "Clk " (rect 51 96 68 108)(font "Arial" ))
(text "Ratio" (rect 81 96 103 108)(font "Arial" ))
(text "Ph (dg)" (rect 116 96 146 108)(font "Arial" ))
(text "DC (%)" (rect 151 96 182 108)(font "Arial" ))
(text "c0" (rect 54 111 64 123)(font "Arial" ))
(text "25/33" (rect 81 111 104 123)(font "Arial" ))
(text "0.00" (rect 122 111 140 123)(font "Arial" ))
(text "50.00" (rect 155 111 178 123)(font "Arial" ))
(text "c1" (rect 54 126 64 138)(font "Arial" ))
(text "2/33" (rect 83 126 101 138)(font "Arial" ))
(text "0.00" (rect 122 126 140 138)(font "Arial" ))
(text "50.00" (rect 155 126 178 138)(font "Arial" ))
(text "c2" (rect 54 141 64 153)(font "Arial" ))
(text "1/66" (rect 83 141 101 153)(font "Arial" ))
(text "0.00" (rect 122 141 140 153)(font "Arial" ))
(text "50.00" (rect 155 141 178 153)(font "Arial" ))
(text "c3" (rect 54 156 64 168)(font "Arial" ))
(text "512/6875" (rect 73 156 111 168)(font "Arial" ))
(text "0.00" (rect 122 156 140 168)(font "Arial" ))
(text "50.00" (rect 155 156 178 168)(font "Arial" ))
(line (pt 0 0)(pt 273 0)(line_width 1))
(line (pt 273 0)(pt 273 201)(line_width 1))
(line (pt 0 201)(pt 273 201)(line_width 1))
(line (pt 0 0)(pt 0 201)(line_width 1))
(line (pt 48 94)(pt 184 94)(line_width 1))
(line (pt 48 108)(pt 184 108)(line_width 1))
(line (pt 48 123)(pt 184 123)(line_width 1))
(line (pt 48 138)(pt 184 138)(line_width 1))
(line (pt 48 153)(pt 184 153)(line_width 1))
(line (pt 48 168)(pt 184 168)(line_width 1))
(line (pt 48 94)(pt 48 168)(line_width 1))
(line (pt 70 94)(pt 70 168)(line_width 3))
(line (pt 113 94)(pt 113 168)(line_width 3))
(line (pt 148 94)(pt 148 168)(line_width 3))
(line (pt 183 94)(pt 183 168)(line_width 1))
(line (pt 40 48)(pt 224 48)(line_width 1))
(line (pt 224 48)(pt 224 184)(line_width 1))
(line (pt 40 184)(pt 224 184)(line_width 1))
(line (pt 40 48)(pt 40 184)(line_width 1))
)
)

5
FPGA_Quartus_13.1/altpll3.cmp
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2014 Altera Corporation
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
@@ -20,6 +20,7 @@ component altpll3
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
end component;

5
FPGA_Quartus_13.1/altpll3.inc
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2014 Altera Corporation
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
@@ -22,5 +22,6 @@ RETURNS (
c0,
c1,
c2,
c3
c3,
locked
);

1
FPGA_Quartus_13.1/altpll3.ppf
View File

@@ -7,6 +7,7 @@
<pin name="c1" direction="output" scope="external" source="clock" />
<pin name="c2" direction="output" scope="external" source="clock" />
<pin name="c3" direction="output" scope="external" source="clock" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>

2
FPGA_Quartus_13.1/altpll3.qip
View File

@@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll3.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.inc"]

140
FPGA_Quartus_13.1/altpll3.vhd
View File

@@ -14,11 +14,11 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
@@ -46,7 +46,8 @@ ENTITY altpll3 IS
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END altpll3;
@@ -59,9 +60,10 @@ ARCHITECTURE SYN OF altpll3 IS
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
@@ -131,48 +133,51 @@ ARCHITECTURE SYN OF altpll3 IS
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
c3 <= sub_wire4;
locked <= sub_wire5;
sub_wire6 <= inclk0;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 33,
clk0_duty_cycle => 50,
clk0_multiply_by => 2,
clk0_multiply_by => 25,
clk0_phase_shift => "0",
clk1_divide_by => 33,
clk1_duty_cycle => 50,
clk1_multiply_by => 16,
clk1_multiply_by => 2,
clk1_phase_shift => "0",
clk2_divide_by => 300,
clk2_divide_by => 66,
clk2_duty_cycle => 50,
clk2_multiply_by => 227,
clk2_multiply_by => 1,
clk2_phase_shift => "0",
clk3_divide_by => 156,
clk3_divide_by => 6875,
clk3_duty_cycle => 50,
clk3_multiply_by => 227,
clk3_multiply_by => 512,
clk3_phase_shift => "0",
compensate_clock => "CLK1",
compensate_clock => "CLK0",
inclk0_input_frequency => 30303,
intended_device_family => "Cyclone III",
lpm_type => "altpll",
@@ -188,7 +193,7 @@ BEGIN
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
@@ -219,11 +224,13 @@ BEGIN
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire6,
clk => sub_wire0
inclk => sub_wire7,
clk => sub_wire0,
locked => sub_wire5
);
@@ -246,21 +253,21 @@ END SYN;
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3744"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "300"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "156"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "72"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "906"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "3072"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "738"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.969999"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.019230"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "0.500000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "2.457600"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -276,9 +283,9 @@ END SYN;
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
@@ -289,19 +296,19 @@ END SYN;
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "227"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "227"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "227"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "55"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "55"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "55"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "55"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "48.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "0.50000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "2.45760000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
@@ -316,7 +323,7 @@ END SYN;
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ns"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -359,21 +366,21 @@ END SYN;
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "300"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "66"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "227"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "156"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6875"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "227"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "512"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
@@ -389,7 +396,7 @@ END SYN;
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
@@ -420,6 +427,7 @@ END SYN;
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
@@ -428,18 +436,20 @@ END SYN;
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf

156
FPGA_Quartus_13.1/altpll4.bsf
View File

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2014 Altera Corporation
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
@@ -18,108 +18,108 @@ programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 312 184)
(text "altpll4" (rect 139 0 179 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 168 25 180)(font "Arial" ))
(rect 0 0 376 232)
(text "altpll4" (rect 168 1 215 20)(font "Arial" (font_size 10)))
(text "inst" (rect 8 213 31 228)(font "Arial" ))
(port
(pt 0 64)
(pt 0 72)
(input)
(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 72 64))
)
(port
(pt 0 80)
(input)
(text "areset" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "areset" (rect 4 66 33 79)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 72 80))
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 88 72)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "scanclk" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "scanclk" (rect 4 82 39 95)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 72 96))
(text "areset" (rect 0 0 42 16)(font "Arial" (font_size 8)))
(text "areset" (rect 4 80 40 96)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 88 96)(line_width 1))
)
(port
(pt 0 112)
(pt 0 120)
(input)
(text "scandata" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "scandata" (rect 4 98 47 111)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 72 112))
)
(port
(pt 0 128)
(input)
(text "scanclkena" (rect 0 0 64 14)(font "Arial" (font_size 8)))
(text "scanclkena" (rect 4 114 57 127)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 72 128))
(text "scanclk" (rect 0 0 53 16)(font "Arial" (font_size 8)))
(text "scanclk" (rect 4 104 49 120)(font "Arial" (font_size 8)))
(line (pt 0 120)(pt 88 120)(line_width 1))
)
(port
(pt 0 144)
(input)
(text "configupdate" (rect 0 0 74 14)(font "Arial" (font_size 8)))
(text "configupdate" (rect 4 130 65 143)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 72 144))
(text "scandata" (rect 0 0 62 16)(font "Arial" (font_size 8)))
(text "scandata" (rect 4 128 57 144)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 88 144)(line_width 1))
)
(port
(pt 312 64)
(output)
(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c0" (rect 296 50 306 63)(font "Arial" (font_size 8)))
(pt 0 168)
(input)
(text "scanclkena" (rect 0 0 77 16)(font "Arial" (font_size 8)))
(text "scanclkena" (rect 4 152 70 168)(font "Arial" (font_size 8)))
(line (pt 0 168)(pt 88 168)(line_width 1))
)
(port
(pt 312 80)
(output)
(text "scandataout" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "scandataout" (rect 248 66 306 79)(font "Arial" (font_size 8)))
(pt 0 192)
(input)
(text "configupdate" (rect 0 0 86 16)(font "Arial" (font_size 8)))
(text "configupdate" (rect 4 176 77 192)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 88 192)(line_width 1))
)
(port
(pt 312 96)
(pt 376 72)
(output)
(text "scandone" (rect 0 0 56 14)(font "Arial" (font_size 8)))
(text "scandone" (rect 260 82 306 95)(font "Arial" (font_size 8)))
(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c0" (rect 359 56 373 72)(font "Arial" (font_size 8)))
(line (pt 376 72)(pt 288 72)(line_width 1))
)
(port
(pt 312 112)
(pt 376 96)
(output)
(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "locked" (rect 277 98 306 111)(font "Arial" (font_size 8)))
(text "scandataout" (rect 0 0 83 16)(font "Arial" (font_size 8)))
(text "scandataout" (rect 302 80 373 96)(font "Arial" (font_size 8)))
(line (pt 376 96)(pt 288 96)(line_width 1))
)
(port
(pt 376 120)
(output)
(text "scandone" (rect 0 0 66 16)(font "Arial" (font_size 8)))
(text "scandone" (rect 317 104 373 120)(font "Arial" (font_size 8)))
(line (pt 376 120)(pt 288 120)(line_width 1))
)
(port
(pt 376 144)
(output)
(text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8)))
(text "locked" (rect 335 128 373 144)(font "Arial" (font_size 8)))
(line (pt 376 144)(pt 288 144)(line_width 1))
)
(drawing
(text "Cyclone III" (rect 250 169 545 349)(font "Arial" ))
(text "inclk0 frequency: 48.019 MHz" (rect 82 92 287 195)(font "Arial" ))
(text "Operation Mode: Normal" (rect 82 105 263 221)(font "Arial" ))
(text "Clk " (rect 83 126 180 263)(font "Arial" ))
(text "Ratio" (rect 104 126 228 263)(font "Arial" ))
(text "Ph (dg)" (rect 130 126 289 263)(font "Arial" ))
(text "DC (%)" (rect 164 126 358 263)(font "Arial" ))
(text "c0" (rect 86 140 180 291)(font "Arial" ))
(text "2/1" (rect 109 140 228 291)(font "Arial" ))
(text "0.00" (rect 136 140 288 291)(font "Arial" ))
(text "50.00" (rect 168 140 357 291)(font "Arial" ))
(line (pt 0 0)(pt 313 0))
(line (pt 313 0)(pt 313 186))
(line (pt 0 186)(pt 313 186))
(line (pt 0 0)(pt 0 186))
(line (pt 80 124)(pt 196 124))
(line (pt 80 137)(pt 196 137))
(line (pt 80 151)(pt 196 151))
(line (pt 80 124)(pt 80 151))
(line (pt 101 124)(pt 101 151)(line_width 3))
(line (pt 127 124)(pt 127 151)(line_width 3))
(line (pt 161 124)(pt 161 151)(line_width 3))
(line (pt 195 124)(pt 195 151))
(line (pt 72 48)(pt 239 48))
(line (pt 239 48)(pt 239 168))
(line (pt 72 168)(pt 239 168))
(line (pt 72 48)(pt 72 168))
(line (pt 311 64)(pt 239 64))
(line (pt 311 80)(pt 239 80))
(line (pt 311 96)(pt 239 96))
(line (pt 311 112)(pt 239 112))
(text "Cyclone III" (rect 301 214 349 228)(font "Arial" ))
(text "inclk0 frequency: 48.000 MHz" (rect 98 123 241 137)(font "Arial" ))
(text "Operation Mode: Normal" (rect 98 140 213 154)(font "Arial" ))
(text "Clk " (rect 99 167 116 181)(font "Arial" ))
(text "Ratio" (rect 125 167 149 181)(font "Arial" ))
(text "Ph (dg)" (rect 159 167 194 181)(font "Arial" ))
(text "DC (%)" (rect 204 167 239 181)(font "Arial" ))
(text "c0" (rect 103 185 115 199)(font "Arial" ))
(text "2/1" (rect 131 185 146 199)(font "Arial" ))
(text "0.00" (rect 167 185 188 199)(font "Arial" ))
(text "50.00" (rect 209 185 236 199)(font "Arial" ))
(line (pt 0 0)(pt 377 0)(line_width 1))
(line (pt 377 0)(pt 377 233)(line_width 1))
(line (pt 0 233)(pt 377 233)(line_width 1))
(line (pt 0 0)(pt 0 233)(line_width 1))
(line (pt 96 164)(pt 246 164)(line_width 1))
(line (pt 96 181)(pt 246 181)(line_width 1))
(line (pt 96 199)(pt 246 199)(line_width 1))
(line (pt 96 164)(pt 96 199)(line_width 1))
(line (pt 122 164)(pt 122 199)(line_width 3))
(line (pt 156 164)(pt 156 199)(line_width 3))
(line (pt 201 164)(pt 201 199)(line_width 3))
(line (pt 245 164)(pt 245 199)(line_width 1))
(line (pt 88 56)(pt 288 56)(line_width 1))
(line (pt 288 56)(pt 288 216)(line_width 1))
(line (pt 88 216)(pt 288 216)(line_width 1))
(line (pt 88 56)(pt 88 216)(line_width 1))
)
)

2
FPGA_Quartus_13.1/altpll4.cmp
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2014 Altera Corporation
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing

2
FPGA_Quartus_13.1/altpll4.inc
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2014 Altera Corporation
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing

6
FPGA_Quartus_13.1/altpll4.mif
View File

@@ -1,4 +1,4 @@
-- Copyright (C) 1991-2014 Altera Corporation
-- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
@@ -17,8 +17,8 @@
-- Device Part: -
-- Device Speed Grade: 8
-- PLL Scan Chain: Fast PLL (144 bits)
-- File Name: C:/Users/froesm1/Documents/Development/FPGA_quartus//altpll4.mif
-- Generated: Mon Sep 21 17:50:54 2015
-- File Name: C:\FireBee\FPGA\altpll4.mif
-- Generated: Mon Dec 06 01:47:24 2010
WIDTH=1;
DEPTH=144;

2
FPGA_Quartus_13.1/altpll4.qip
View File

@@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"]

44
FPGA_Quartus_13.1/altpll4.tdf
View File

@@ -14,11 +14,11 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
@@ -59,7 +59,7 @@ VARIABLE
CLK0_MULTIPLY_BY = 2,
CLK0_PHASE_SHIFT = "0",
COMPENSATE_CLOCK = "CLK0",
INCLK0_INPUT_FREQUENCY = 20824,
INCLK0_INPUT_FREQUENCY = 20833,
INTENDED_DEVICE_FAMILY = "Cyclone III",
LPM_TYPE = "altpll",
OPERATION_MODE = "NORMAL",
@@ -113,16 +113,16 @@ VARIABLE
BEGIN
c0 = altpll_component.clk[0..0];
scandataout = altpll_component.scandataout;
scandone = altpll_component.scandone;
scandataout = altpll_component.scandataout;
locked = altpll_component.locked;
altpll_component.areset = areset;
altpll_component.configupdate = configupdate;
altpll_component.scanclkena = scanclkena;
altpll_component.inclk[0..0] = inclk0;
altpll_component.inclk[1..1] = GND;
altpll_component.scanclk = scanclk;
altpll_component.scanclkena = scanclkena;
altpll_component.scandata = scandata;
altpll_component.areset = areset;
altpll_component.scanclk = scanclk;
altpll_component.configupdate = configupdate;
END;
@@ -148,7 +148,7 @@ END;
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.038460"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -156,7 +156,7 @@ END;
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.019"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
@@ -166,7 +166,7 @@ END;
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "336.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
@@ -217,7 +217,7 @@ END;
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20824"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
@@ -277,22 +277,22 @@ END;
-- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
-- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
-- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
-- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE
-- Retrieval info: LIB_FILE: altera_mf

4805
FPGA_Quartus_13.1/firebee1.bdf
View File

File diff suppressed because it is too large Load Diff

289
FPGA_Quartus_13.1/firebee1.qsf
View File

@@ -42,10 +42,10 @@
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf"
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_AB12 -to CLK33M
set_location_assignment PIN_G2 -to MAIN_CLK
set_location_assignment PIN_Y3 -to FB_AD[0]
set_location_assignment PIN_Y6 -to FB_AD[1]
@@ -319,7 +319,6 @@ set_location_assignment PIN_A20 -to nRD_DATA
set_location_assignment PIN_C17 -to nDCHG
set_location_assignment PIN_J4 -to nACSI_INT
set_location_assignment PIN_K7 -to nACSI_DRQ
set_location_assignment PIN_E12 -to MIDI_IN
set_location_assignment PIN_G7 -to LP_BUSY
set_location_assignment PIN_Y1 -to IDE_RDY
set_location_assignment PIN_G22 -to IDE_INT
@@ -368,14 +367,14 @@ set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK
set_instance_assignment -name IO_STANDARD "2.5 V" -to VA
set_instance_assignment -name IO_STANDARD "2.5 V" -to VD
@@ -495,7 +494,7 @@ set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to FB_AD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA
@@ -513,15 +512,14 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nPD_VGA
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SRD
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to IO
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRWE
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSROE
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRCS
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBLE
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBHE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M
@@ -546,8 +544,6 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3
# LogicLock Region Assignments
# ============================
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
# end LOGICLOCK_REGION(Root Region)
# ---------------------------------
@@ -557,76 +553,135 @@ set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(firebee1)
# --------------------
set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf"
set_location_assignment PIN_E5 -to LPDIR
set_location_assignment PIN_B11 -to nRSTO_MCF
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name DISABLE_OCP_HW_EVAL ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE PESSIMISTIC
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 3
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.5
set_global_assignment -name ECO_OPTIMIZE_TIMING ON
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD
set_location_assignment PIN_AB12 -to CLK33MDIR
set_location_assignment PIN_E12 -to MIDI_IN_PIN
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN
set_instance_assignment -name PCI_IO ON -to nPCI_INTA
set_instance_assignment -name PCI_IO ON -to nPCI_INTB
set_instance_assignment -name PCI_IO ON -to nPCI_INTC
set_instance_assignment -name PCI_IO ON -to nPCI_INTD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3]
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2]
set_global_assignment -name POWER_USE_TA_VALUE 35
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1]
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS
set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name BDF_FILE firebee1.bdf
set_global_assignment -name SDC_FILE firebee1.sdc
set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf
set_global_assignment -name VHDL_FILE DSP/DSP.vhd
set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd
set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp
set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp
set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd
set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf
set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp
set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp
set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp
set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp
set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp
set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp
set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp
set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp
set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp
set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp
set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp
set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp
set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp
@@ -637,12 +692,21 @@ set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd
set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf
set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp
set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd
set_global_assignment -name BDF_FILE Video/Video.bdf
set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp
set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp
set_global_assignment -name VHDL_FILE Video/altdpram0.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp
set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp
set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp
set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp
set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip
set_global_assignment -name QIP_FILE Video/altdpram0.qip
set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip
@@ -656,22 +720,6 @@ set_global_assignment -name QIP_FILE Video/lpm_mux1.qip
set_global_assignment -name QIP_FILE Video/lpm_mux2.qip
set_global_assignment -name QIP_FILE Video/lpm_constant2.qip
set_global_assignment -name QIP_FILE Video/altdpram2.qip
set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip
set_global_assignment -name QIP_FILE Video/lpm_mux3.qip
set_global_assignment -name QIP_FILE Video/lpm_mux4.qip
set_global_assignment -name QIP_FILE Video/lpm_constant3.qip
set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip
set_global_assignment -name QIP_FILE Video/lpm_latch1.qip
set_global_assignment -name QIP_FILE Video/lpm_constant4.qip
set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip
set_global_assignment -name QIP_FILE Video/lpm_compare1.qip
set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp
set_global_assignment -name VHDL_FILE Video/altdpram0.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp
set_global_assignment -name QIP_FILE Video/lpm_ff4.qip
set_global_assignment -name QIP_FILE Video/lpm_ff5.qip
set_global_assignment -name QIP_FILE Video/lpm_ff6.qip
set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp
set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip
set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip
set_global_assignment -name QIP_FILE Video/altddio_out0.qip
@@ -681,23 +729,46 @@ set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip
set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip
set_global_assignment -name QIP_FILE Video/altddio_out1.qip
set_global_assignment -name QIP_FILE Video/altddio_out2.qip
set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp
set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip
set_global_assignment -name QIP_FILE Video/lpm_mux6.qip
set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd
set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp
set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd
set_global_assignment -name QIP_FILE Video/lpm_mux3.qip
set_global_assignment -name QIP_FILE Video/lpm_mux4.qip
set_global_assignment -name QIP_FILE Video/lpm_constant3.qip
set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip
set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip
set_global_assignment -name QIP_FILE Video/lpm_latch1.qip
set_global_assignment -name QIP_FILE Video/lpm_constant4.qip
set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip
set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip
set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT
set_global_assignment -name QIP_FILE Video/lpm_compare1.qip
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp
set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp
set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd
set_global_assignment -name BDF_FILE Video/Video.bdf
set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp
set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd
set_global_assignment -name QIP_FILE Video/lpm_ff4.qip
set_global_assignment -name QIP_FILE Video/lpm_ff5.qip
set_global_assignment -name QIP_FILE Video/lpm_ff6.qip
set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp
set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip
set_global_assignment -name VHDL_FILE DSP/DSP.vhd
set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd
set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip
set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
@@ -725,37 +796,35 @@ set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf214
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip
set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip
set_global_assignment -name VHDL_FILE lpm_latch0.vhd
set_global_assignment -name SOURCE_FILE lpm_latch0.cmp
set_global_assignment -name QIP_FILE altpll0.qip
set_global_assignment -name SOURCE_FILE altpll0.cmp
set_global_assignment -name VHDL_FILE altpll1.vhd
set_global_assignment -name QIP_FILE altpll1.qip
set_global_assignment -name SOURCE_FILE altpll1.cmp
set_global_assignment -name VHDL_FILE altpll2.vhd
set_global_assignment -name QIP_FILE altpll2.qip
set_global_assignment -name SOURCE_FILE altpll2.cmp
set_global_assignment -name VHDL_FILE altpll3.vhd
set_global_assignment -name QIP_FILE altpll3.qip
set_global_assignment -name SOURCE_FILE altpll0.cmp
set_global_assignment -name SOURCE_FILE altpll2.cmp
set_global_assignment -name VHDL_FILE altpll2.vhd
set_global_assignment -name SOURCE_FILE altpll3.cmp
set_global_assignment -name QIP_FILE altpll4.qip
set_global_assignment -name AHDL_FILE altpll4.tdf
set_global_assignment -name QIP_FILE altpll_reconfig1.qip
set_global_assignment -name VHDL_FILE altpll3.vhd
set_global_assignment -name SOURCE_FILE lpm_counter0.cmp
set_global_assignment -name BDF_FILE firebee1.bdf
set_global_assignment -name VHDL_FILE altpll1.vhd
set_global_assignment -name SOURCE_FILE altpll1.cmp
set_global_assignment -name QIP_FILE altpll0.qip
set_global_assignment -name QIP_FILE lpm_counter0.qip
set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
set_global_assignment -name QIP_FILE altddio_out3.qip
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
set_global_assignment -name QIP_FILE altpll_reconfig1.qip
set_global_assignment -name QIP_FILE altpll4.qip
set_global_assignment -name QIP_FILE lpm_mux0.qip
set_global_assignment -name QIP_FILE lpm_shiftreg0.qip
set_global_assignment -name QIP_FILE lpm_counter1.qip
set_global_assignment -name QIP_FILE altiobuf_bidir0.qip
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

17
FPGA_Quartus_13.1/firebee1.sdc
View File

@@ -118,14 +118,14 @@ derive_clock_uncertainty
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.000 [all_inputs]
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [all_inputs]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.000 [all_outputs]
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [all_outputs]
#**************************************************************
@@ -149,17 +149,22 @@ set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pl
# MAIN_CLK to DDR clk and v.v.
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
# 2 MHz to 33 MHz
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {MAIN_CLK}]
# 16 MHz to 33 MHz
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}]
@@ -168,6 +173,9 @@ set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|al
# 25 MHz to 33 MHz
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
@@ -178,6 +186,7 @@ set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_genera
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}]

6
FPGA_Quartus_13.1/lpm_counter1.qip Normal file
View File

@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.cmp"]

6
FPGA_Quartus_13.1/lpm_mux0.qip Normal file
View File

@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.cmp"]

6
FPGA_Quartus_13.1/lpm_shiftreg0.qip Normal file
View File

@@ -0,0 +1,6 @@
set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.tdf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.cmp"]