From fc8034d93b16d353f6ba7379142d0afe8d038cb8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 26 Oct 2015 06:48:18 +0000 Subject: [PATCH] patch with Fredi's lp fix (and others) --- .../FalconIO_SDCard_IDE_CF.vhd | 435 +- .../WF_SND2149_IP/wf2149ip_pkg.vhd | 2 +- .../WF_SND2149_IP/wf2149ip_top_soc.vhd | 15 +- .../WF_SND2149_IP/wf2149ip_wave.vhd | 2 +- .../WF_UART6850_IP/wf6850ip_ctrl_status.vhd | 96 +- .../WF_UART6850_IP/wf6850ip_receive.vhd | 619 +-- .../WF_UART6850_IP/wf6850ip_top_soc.vhd | 10 +- .../WF_UART6850_IP/wf6850ip_transmit.vhd | 45 +- .../Interrupt_Handler/interrupt_handler.tdf | 216 +- FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd | 47 +- .../Video/BLITTER/altsyncram0.qip | 6 + .../Video/BLITTER/lpm_clshift0.qip | 6 + .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf | 127 +- FPGA_Quartus_13.1/Video/Video.bdf | 4080 +++++++------- FPGA_Quartus_13.1/altiobuf_bidir0.qip | 6 + FPGA_Quartus_13.1/altpll1.bsf | 114 +- FPGA_Quartus_13.1/altpll1.cmp | 2 +- FPGA_Quartus_13.1/altpll1.inc | 2 +- FPGA_Quartus_13.1/altpll1.qip | 2 +- FPGA_Quartus_13.1/altpll1.vhd | 64 +- FPGA_Quartus_13.1/altpll2.bsf | 152 +- FPGA_Quartus_13.1/altpll2.cmp | 2 +- FPGA_Quartus_13.1/altpll2.inc | 2 +- FPGA_Quartus_13.1/altpll2.qip | 2 +- FPGA_Quartus_13.1/altpll2.vhd | 32 +- FPGA_Quartus_13.1/altpll3.bsf | 139 +- FPGA_Quartus_13.1/altpll3.cmp | 5 +- FPGA_Quartus_13.1/altpll3.inc | 5 +- FPGA_Quartus_13.1/altpll3.ppf | 1 + FPGA_Quartus_13.1/altpll3.qip | 2 +- FPGA_Quartus_13.1/altpll3.vhd | 140 +- FPGA_Quartus_13.1/altpll4.bsf | 156 +- FPGA_Quartus_13.1/altpll4.cmp | 2 +- FPGA_Quartus_13.1/altpll4.inc | 2 +- FPGA_Quartus_13.1/altpll4.mif | 6 +- FPGA_Quartus_13.1/altpll4.qip | 2 +- FPGA_Quartus_13.1/altpll4.tdf | 44 +- FPGA_Quartus_13.1/firebee1.bdf | 4805 ++++++++--------- FPGA_Quartus_13.1/firebee1.qsf | 291 +- FPGA_Quartus_13.1/firebee1.sdc | 17 +- FPGA_Quartus_13.1/lpm_counter1.qip | 6 + FPGA_Quartus_13.1/lpm_mux0.qip | 6 + FPGA_Quartus_13.1/lpm_shiftreg0.qip | 6 + 43 files changed, 5765 insertions(+), 5956 deletions(-) create mode 100644 FPGA_Quartus_13.1/Video/BLITTER/altsyncram0.qip create mode 100644 FPGA_Quartus_13.1/Video/BLITTER/lpm_clshift0.qip create mode 100644 FPGA_Quartus_13.1/altiobuf_bidir0.qip create mode 100644 FPGA_Quartus_13.1/lpm_counter1.qip create mode 100644 FPGA_Quartus_13.1/lpm_mux0.qip create mode 100644 FPGA_Quartus_13.1/lpm_shiftreg0.qip diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd index b994a78..a5dbf21 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd @@ -115,7 +115,7 @@ ENTITY falconio_sdcard_ide_cf IS nCF_CS0 : OUT std_logic; nIDE_RD : INOUT std_logic; nIDE_WR : INOUT std_logic; - AMKB_TX : OUT std_logic; + AMKB_TX : buffer std_logic; IDE_RES : OUT std_logic; DTR : OUT std_logic; RTS : OUT std_logic; @@ -132,6 +132,7 @@ ENTITY falconio_sdcard_ide_cf IS DMA_DRQ : OUT std_logic; FB_AD : INOUT std_logic_vector(31 DOWNTO 0); LP_D : INOUT std_logic_vector(7 DOWNTO 0); + SND_A : INOUT std_logic_vector(7 downto 0); ACSI_D : INOUT std_logic_vector(7 DOWNTO 0); SCSI_D : INOUT std_logic_vector(7 DOWNTO 0); SCSI_PAR : INOUT std_logic; @@ -141,14 +142,13 @@ ENTITY falconio_sdcard_ide_cf IS SD_CD_DATA3 : INOUT std_logic; SD_CDM_D1 : INOUT std_logic ); - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! - + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! END falconio_sdcard_ide_cf; -- Architecture Body -ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS +ARCHITECTURE rtl OF FalconIO_SDCard_IDE_CF IS -- system SIGNAL SYS_CLK : std_logic; SIGNAL RESETn : std_logic; @@ -156,12 +156,15 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS SIGNAL FB_B1 : std_logic; -- LOWER BYT BEI 16BIT BUS SIGNAL BYT : std_logic; -- WENN BYT -> 1 SIGNAL LONG : std_logic; -- WENN -> 1 +signal FB_ADI : STD_LOGIC_VECTOR(15 downto 0); -- gespeicherte writedaten +signal nResetatio : STD_LOGIC; -- reset atari bausteine -- KEYBOARD MIDI SIGNAL ACIA_CS_I : std_logic; SIGNAL IRQ_KEYBDn : std_logic; SIGNAL IRQ_MIDIn : std_logic; SIGNAL KEYB_RxD : std_logic; - SIGNAL AMKB_REG : std_logic_vector(4 DOWNTO 0); +signal AMKB_REG : STD_LOGIC_VECTOR(3 downto 0); +signal AMKB_TX_sync : std_logic; SIGNAL MIDI_OUT : std_logic; SIGNAL DATA_OUT_ACIA_I : std_logic_vector(7 DOWNTO 0); SIGNAL DATA_OUT_ACIA_II : std_logic_vector(7 DOWNTO 0); @@ -169,8 +172,8 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS SIGNAL MFP_CS : std_logic; SIGNAL MFP_INTACK : std_logic; SIGNAL LDS : std_logic; +signal acia_irq : STD_LOGIC; SIGNAL DTACK_OUT_MFPn : std_logic; - SIGNAL IRQ_ACIAn : std_logic; SIGNAL DINTn : std_logic; SIGNAL DATA_OUT_MFP : std_logic_vector(7 DOWNTO 0); SIGNAL TDO : std_logic; @@ -180,7 +183,22 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS SIGNAL SNDIR_I : std_logic; SIGNAL LP_DIR_X : std_logic; SIGNAL DA_OUT_X : std_logic_vector(7 DOWNTO 0); +signal SND_A_X : STD_LOGIC_VECTOR(7 downto 0); SIGNAL LP_D_X : std_logic_vector(7 DOWNTO 0); +signal nLP_STR : STD_LOGIC; +-- DMA SOUND +signal dma_snd_cs : STD_LOGIC; +signal sndmactl : STD_LOGIC_VECTOR(7 downto 0); +signal sndbashi : STD_LOGIC_VECTOR(7 downto 0); +signal sndbasmi : STD_LOGIC_VECTOR(7 downto 0); +signal sndbaslo : STD_LOGIC_VECTOR(7 downto 0); +signal sndadrhi : STD_LOGIC_VECTOR(7 downto 0); +signal sndadrmi : STD_LOGIC_VECTOR(7 downto 0); +signal sndadrlo : STD_LOGIC_VECTOR(7 downto 0); +signal sndendhi : STD_LOGIC_VECTOR(7 downto 0); +signal sndendmi : STD_LOGIC_VECTOR(7 downto 0); +signal sndendlo : STD_LOGIC_VECTOR(7 downto 0); +signal sndmode : STD_LOGIC_VECTOR(7 downto 0); -- DIV SIGNAL SUB_BUS : std_logic; -- SUB BUS MIT ROM-PORT, CF UND IDE SIGNAL ROM_CS : std_logic; @@ -228,9 +246,7 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS SIGNAL WRF_RDE : std_logic; SIGNAL WRF_WRE : std_logic; SIGNAL nFDC_WR : std_logic; - TYPE FCF_STATES IS (FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7); - SIGNAL FCF_STATE : FCF_STATES; SIGNAL NEXT_FCF_STATE : FCF_STATES; SIGNAL DMA_REQ : std_logic; @@ -241,7 +257,6 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS SIGNAL DMA_ACTIV : std_logic; SIGNAL DMA_ACTIV_NEW : std_logic; SIGNAL FDC_OUT : std_logic_vector(7 DOWNTO 0); - -- SCSI SIGNAL SCSI_CS : std_logic; SIGNAL SCSI_CSn : std_logic; @@ -259,7 +274,6 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS SIGNAL BSY_EN : std_logic; SIGNAL SEL_OUTn : std_logic; SIGNAL SEL_EN : std_logic; - -- IDE SIGNAL nnIDE_RES : std_logic; SIGNAL IDE_CF_CS : std_logic; @@ -269,7 +283,8 @@ ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS type CMD_STATES is( IDLE, T1, T6, T7); SIGNAL CMD_STATE : CMD_STATES; SIGNAL NEXT_CMD_STATE : CMD_STATES; - +-- Paddle + SIGNAL paddle_cs : std_logic; BEGIN LONG <= '1' WHEN FB_SIZE1 = '0' AND FB_SIZE0 = '0' ELSE '0'; @@ -277,23 +292,34 @@ BEGIN FB_B0 <= '1' WHEN FB_ADR(0) = '0' OR BYT = '0' ELSE '0'; FB_B1 <= '1' WHEN FB_ADR(0) = '1' OR BYT = '0' ELSE '0'; - FALCON_IO_TA <= '1' WHEN SNDCS = '1' OR DTACK_OUT_MFPn = '0' OR ACIA_CS_I = '1' OR DMA_MODUS_CS ='1' - OR DMA_ADR_CS = '1' OR DMA_DIRM_CS = '1' OR DMA_BYT_CNT_CS = '1' OR FCF_CS = '1' OR IDE_CF_TA = '1' ELSE '0'; - + FALCON_IO_TA <= '1' when ACIA_CS_I = '1' or DTACK_OUT_MFPn = '0' or DMA_MODUS_CS ='1' or dma_snd_cs = '1' or paddle_cs = '1' + or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';--SNDCS = '1' or SUB_BUS <= '1' WHEN nFB_WR = '1' AND ROM_CS = '1' ELSE '1' WHEN nFB_WR = '1' AND IDE_CF_CS = '1' ELSE '1' WHEN nFB_WR = '0' AND nIDE_WR = '0' ELSE '0'; - nRP_UDS <= '0' WHEN SUB_BUS = '1' AND FB_B0 = '1' ELSE '1'; - nRP_LDS <= '0' WHEN SUB_BUS = '1' AND FB_B1 = '1' ELSE '1'; + nRP_UDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B0 = '1' else '1'; + nRP_LDS <= '0' when nFB_CS1 = '0' and SUB_BUS = '1' and FB_B1 = '1' else '1'; nDREQ0 <= '0'; - + + -- input daten halten + p_hold_input_data : PROCESS(MAIN_CLK, nFB_WR, FB_AD(31 DOWNTO 16), FB_ADI(15 DOWNTO 0)) + BEGIN + IF rising_edge(MAIN_CLK) THEN + IF nFB_WR = '0' THEN + FB_ADI <= FB_AD(31 downto 16); + ELSE + FB_ADI <= FB_ADI; + END IF; + ELSE + FB_ADI <= FB_ADI; + END IF; + END PROCESS; ---------------------------------------------------------------------------- -- SD ---------------------------------------------------------------------------- SD_CLK <= 'Z'; SD_CD_DATA3 <= 'Z'; SD_CDM_D1 <= 'Z'; - ---------------------------------------------------------------------------- -- IDE ---------------------------------------------------------------------------- @@ -353,24 +379,19 @@ BEGIN IDE_RES <= NOT nnIDE_RES AND nRSTO; IDE_CF_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 7) = x"0" ELSE '0'; -- FFF0'0000/80 - nCF_CS0 <= '0' WHEN ACP_CONF(31) = '0' AND FB_ADR(19 DOWNTO 5) = x"0" ELSE -- FFFO'0000-FFF0'001F '0' WHEN ACP_CONF(31) = '1' AND FB_ADR(19 DOWNTO 5) = x"2" ELSE '1'; -- FFFO'0040-FFF0'005F - nCF_CS1 <= '0' WHEN ACP_CONF(31) = '0' AND FB_ADR(19 DOWNTO 5) = x"1" ELSE -- FFF0'0020-FFF0'003F '0' WHEN ACP_CONF(31) = '1' AND FB_ADR(19 DOWNTO 5) = x"3" ELSE '1'; -- FFFO'0060-FFF0'007F - nIDE_CS0 <= '0' WHEN ACP_CONF(30) = '0' AND FB_ADR(19 DOWNTO 5) = x"2" ELSE -- FFF0'0040-FFF0'005F '0' WHEN ACP_CONF(30) = '1' AND FB_ADR(19 DOWNTO 5) = x"0" ELSE '1'; -- FFFO'0000-FFF0'001F - nIDE_CS1 <= '0' WHEN ACP_CONF(30) = '0' AND FB_ADR(19 DOWNTO 5) = x"3" ELSE -- FFF0'0060-FFF0'007F '0' WHEN ACP_CONF(30) = '1' AND FB_ADR(19 DOWNTO 5) = x"1" ELSE '1'; -- FFFO'0020-FFF0'003F - ----------------------------------------------------------------------------------------------------------------------------------------- -- ACSI, SCSI UND FLOPPY WD1772 ------------------------------------------------------------------------------------------------------------------------------------------- -- daten read fifo - i_data_read_fifo: dcfifo0 + RDF: dcfifo0 PORT MAP( aclr => CLR_FIFO, data => RDF_DIN, @@ -381,16 +402,15 @@ BEGIN q => RDF_DOUT, wrusedw => RDF_AZ ); - FCF_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"0020110" AND LONG = '1' ELSE '0'; -- F002'0110 LONG ONLY FCF_APH <= '1' WHEN FB_ALE = '1' AND FB_AD(31 DOWNTO 0) = x"F0020110" AND LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY RDF_RDE <= '1' WHEN FCF_APH = '1' AND nFB_WR = '1' ELSE '0'; -- AKTIVIEREN IN ADRESSPHASE - - FB_AD <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' and nFB_OE = '0' + ELSE (OTHERS => 'Z'); + RDF_DIN <= CD_OUT_FDC WHEN DMA_MODUS(7) = '1' ELSE SCSI_DOUT; - -- daten write fifo - i_data_write_fifo: dcfifo1 + WRF: dcfifo1 PORT MAP( aclr => CLR_FIFO, data => FB_AD(7 DOWNTO 0) & FB_AD(15 DOWNTO 8) & FB_AD(23 DOWNTO 16) & FB_AD(31 DOWNTO 24), @@ -401,14 +421,14 @@ BEGIN q => WRF_DOUT, rdusedw => WRF_AZ ); - - CD_IN_FDC <= WRF_DOUT WHEN DMA_ACTIV = '1' AND DMA_MODUS(8) = '1' ELSE FB_AD(23 DOWNTO 16); -- BEI DMA WRITE <-FIFO SONST <-FB + CD_IN_FDC <= WRF_DOUT WHEN DMA_ACTIV = '1' and DMA_MODUS(8) = '1' ELSE FB_ADI(7 DOWNTO 0); -- BEI DMA WRITE <-FIFO SONST <-FB DMA_AZ_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"002010C" ELSE '0'; -- F002'010C LONG - FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' and nFB_OE = '0' + ELSE (OTHERS => 'Z'); DMA_DRQ_Q <= '1' WHEN DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' ELSE '0'; - + -- FIFO WRITE: GENAU 1 MAIN_CLK ------------------------------------------------------------------------- - PROCESS(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH) + p_fifo_write : PROCESS(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH) BEGIN IF nRSTO = '0' THEN WRF_WRE <= '0'; @@ -530,7 +550,7 @@ BEGIN i_fdc : WF1772IP_TOP_SOC PORT MAP( CLK => FDC_CLK, - RESETn => nRSTO, + RESETn => nResetatio, CSn => FDCS_In, RWn => nFDC_WR, A1 => CA2, @@ -552,25 +572,20 @@ BEGIN DRQ => DMA_DRQ_I, INTRQ => FDINT ); - DMA_DATEN_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C302" ELSE '0'; -- F8604/2 DMA_MODUS_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C303" ELSE '0'; -- F8606/2 WDC_BSL_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C307" ELSE '0'; -- F860E/2 - HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0); - nFDC_WR <= NOT DMA_MODUS(8) WHEN DMA_ACTIV = '1' ELSE nFB_WR; - + nFDC_WR <= (not DMA_MODUS(8)) WHEN DMA_ACTIV = '1' ELSE nFB_WR; CA0 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(0); CA1 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(1); CA2 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(2); - FB_AD(23 DOWNTO 16) <= "0000" & (NOT DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD WHEN WDC_BSL_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD(31 DOWNTO 24) <= "00000000" WHEN DMA_DATEN_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else (OTHERS => 'Z'); + FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; FB_AD(23 DOWNTO 16) <= FDC_OUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "00" AND nFB_OE = '0' ELSE SCSI_DOUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "01" AND nFB_OE = '0' ELSE - DMA_BYT_CNT(16 DOWNTO 9) WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4) = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - - + DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; --- WDC BSL REGISTER ------------------------------------------------------- PROCESS(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1) BEGIN @@ -584,7 +599,6 @@ BEGIN END IF; END IF; END PROCESS; - --- DMA MODUS REGISTER ------------------------------------------------------- PROCESS(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1) BEGIN @@ -605,16 +619,15 @@ BEGIN DMA_MODUS <= DMA_MODUS; END IF; END PROCESS; - -- BYT COUNTER, SECTOR COUNTER ---------------------------------------------------- PROCESS(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO) BEGIN IF nRSTO = '0' OR CLR_FIFO = '1' THEN DMA_BYT_CNT <= x"00000000"; ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_DATEN_CS = '1' AND nFB_WR = '0' AND DMA_MODUS(4) = '1' AND FB_B1 = '1' THEN - DMA_BYT_CNT(31 DOWNTO 17) <= (OTHERS => 'Z'); + DMA_BYT_CNT(31 downto 17) <= "000000000000000"; DMA_BYT_CNT(16 DOWNTO 9) <= FB_AD(23 DOWNTO 16); - DMA_BYT_CNT(8 DOWNTO 0) <= (OTHERS => 'Z'); + DMA_BYT_CNT(8 downto 0) <= "000000000"; ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_BYT_CNT_CS = '1' THEN DMA_BYT_CNT <= FB_AD; ELSE @@ -622,15 +635,13 @@ BEGIN END IF; END PROCESS; -------------------------------------------------------------------- - FB_AD(31 DOWNTO 16) <= "0000000000000" & DMA_STATUS WHEN DMA_MODUS_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); - + FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; DMA_STATUS(0) <= '1'; -- DMA OK DMA_STATUS(1) <= '1' WHEN DMA_BYT_CNT /= 0 AND DMA_BYT_CNT(31) = '0' ELSE '0'; -- WENN byts UND NICHT MINUS DMA_STATUS(2) <= '0' WHEN DMA_DRQ_I = '1' OR SCSI_DRQ = '1' ELSE '0'; DMA_DRQQ <= '1' WHEN DMA_STATUS(1) = '1' AND DMA_MODUS(8) = '0' AND RDF_AZ > 15 AND DMA_MODUS(6) = '0' ELSE '1' WHEN DMA_STATUS(1) = '1' AND DMA_MODUS(8) = '1' AND WRF_AZ < 512 AND DMA_MODUS(6) = '0' ELSE '0'; DMA_DRQ <= '1' WHEN DMA_DRQ_REG = "11" AND DMA_MODUS(6) = '0' ELSE '0'; - -- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------ PROCESS(FDC_CLK, nRSTO, DMA_DRQ_REG) BEGIN @@ -643,7 +654,6 @@ BEGIN DMA_DRQ_REG <= DMA_DRQ_REG; END IF; END PROCESS; - -- DMA ADRESSE ------------------------------------------------------ PROCESS(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS) BEGIN @@ -655,7 +665,6 @@ BEGIN DMA_TOP <= DMA_TOP; END IF; END PROCESS; - PROCESS(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS) BEGIN IF nRSTO = '0' THEN @@ -666,7 +675,6 @@ BEGIN DMA_HIGH <= DMA_HIGH; END IF; END PROCESS; - PROCESS(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR) BEGIN DMA_MID <= DMA_MID; @@ -680,7 +688,6 @@ BEGIN END IF; END IF; END PROCESS; - PROCESS(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR) BEGIN DMA_LOW <= DMA_LOW; @@ -694,29 +701,26 @@ BEGIN END IF; END IF; END PROCESS; - -------------------------------------------------------------------------------------------- DMA_TOP_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C304" AND FB_B0 = '1' ELSE '0'; -- F8608/2 DMA_HIGH_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C304" AND FB_B1 = '1' ELSE '0'; -- F8609/2 DMA_MID_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C305" AND FB_B1 = '1' ELSE '0'; -- F860B/2 DMA_LOW_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C306" AND FB_B1 = '1' ELSE '0'; -- F860D/2 - - FB_AD(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); + + FB_AD(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + FB_AD(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + FB_AD(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + FB_AD(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; -- DIRECTZUGRIFF DMA_DIRM_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20100" ELSE '0'; -- F002'0100 WORD DMA_ADR_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20104" ELSE '0'; -- F002'0104 LONG DMA_BYT_CNT_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20108" ELSE '0'; -- F002'0108 LONG - - FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW WHEN DMA_ADR_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - - + + FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; + FB_AD(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + FB_AD <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; + -- DMA RW TOGGLE ------------------------------------------ - PROCESS(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD) BEGIN IF nRSTO = '0' THEN @@ -727,20 +731,18 @@ BEGIN DMA_DIR_OLD <= DMA_DIR_OLD; END IF; END PROCESS; - CLR_FIFO <= DMA_MODUS(8) XOR DMA_DIR_OLD; - -- SCSI ---------------------------------------------------------------------------------- i_scsi : WF5380_TOP_SOC PORT MAP( CLK => FDC_CLK, - RESETn => nRSTO, + RESETn => nResetatio, ADR => CA2 & CA1 & CA0, DATA_IN => CD_IN_FDC, DATA_OUT => SCSI_DOUT, --DATA_EN : out bit; -- Bus and DMA controls: - CSn => '1', --SCSI_CSn, ABGESCHALTET + CSn => SCSI_CSn, RDn => (not nFDC_WR) or (not SCSI_CS), WRn => nFDC_WR or (not SCSI_CS), EOPn => '1', @@ -783,37 +785,36 @@ BEGIN -- MSG_OUTn => MSG_OUTn, -- MSG_EN => MSG_EN ); - -- SCSI ACSI --------------------------------------------------------------- - SCSI_D <= DB_OUTn WHEN DB_EN = '1' ELSE (OTHERS => 'Z'); - SCSI_DIR <= '1'; --'0' WHEN DB_EN = '1' ELSE '1'; --ABGESCHALTET + SCSI_D <= "ZZZZZZZZ"; --DB_OUTn when DB_EN = '1' else "ZZZZZZZZ"; + SCSI_DIR <= '1';-- when DB_EN = '1' else '1'; SCSI_PAR <= DBP_OUTn WHEN DBP_EN = '1' ELSE 'Z'; - nSCSI_RST <= RST_OUTn WHEN RST_EN = '1' ELSE 'Z'; - nSCSI_BUSY <= BSY_OUTn WHEN BSY_EN = '1' ELSE 'Z'; - nSCSI_SEL <= SEL_OUTn WHEN SEL_EN = '1' ELSE 'Z'; + nSCSI_RST <= 'Z';--RST_OUTn when RST_EN = '1' else 'Z'; + nSCSI_BUSY <= 'Z';--BSY_OUTn when BSY_EN = '1' else 'Z'; + nSCSI_SEL <= 'Z';--SEL_OUTn when SEL_EN = '1' else 'Z'; + ACSI_DIR <= '0'; - ACSI_D <= (OTHERS => 'Z'); + ACSI_D <= "ZZZZZZZZ"; nACSI_CS <= '1'; ACSI_A1 <= CA1; nACSI_RESET <= nRSTO; nACSI_ACK <= '1'; - - + nResetatio <= '0' when nRSTO = '0' or ACP_CONF(24) = '1' else '1'; + ---------------------------------------------------------------------------- -- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns ---------------------------------------------------------------------------- ROM_CS <= '1' WHEN nFB_CS1 = '0' AND nFB_WR = '1' AND FB_ADR(19 DOWNTO 17) = x"5" ELSE '0'; -- FFF A'0000/2'0000 nROM4 <= '0' WHEN ROM_CS = '1' AND FB_ADR(16) = '0' ELSE '1'; nROM3 <= '0' WHEN ROM_CS = '1' AND FB_ADR(16) = '1' ELSE '1'; - - + ---------------------------------------------------------------------------- -- ACIA KEYBOARD ---------------------------------------------------------------------------- i_acia_keyboard : WF6850IP_TOP_SOC PORT MAP( CLK => MAIN_CLK, - RESETn => nRSTO, + RESETn => nResetatio, CS2n => FB_ADR(2), CS1 => '1', @@ -822,7 +823,7 @@ BEGIN RWn => nFB_WR, RS => FB_ADR(1), - DATA_IN => FB_AD(31 DOWNTO 24), + DATA_IN => FB_ADI(15 downto 8), DATA_OUT => DATA_OUT_ACIA_I, -- DATA_EN => DATA_EN_ACIA_I, @@ -834,43 +835,48 @@ BEGIN DCDn => '0', IRQn => IRQ_KEYBDn, - TXDATA => AMKB_TX + TXDATA => AMKB_TX_sync --RTSn => -- Not used. ); - ACIA_CS_I <= '1' WHEN nFB_CS1 = '0'AND FB_ADR(19 DOWNTO 3) = x"1FF80" ELSE '0'; -- FFC00-FFC07 FFC00/8 - KEYB_RxD <= '1' WHEN AMKB_REG(3) = '1' OR PIC_AMKB_RX = '0' ELSE '0'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL - FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_I WHEN ACIA_CS_I = '1' AND FB_ADR(2) = '0' AND nFB_OE = '0' ELSE "ZZZZZZZZ"; - - -- AMKB_TX: SPIKES AUSFILTERN ------------------------------------------ + KEYB_RxD <= '0' WHEN AMKB_REG(3) = '0' or PIC_AMKB_RX = '0' ELSE '1'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL // + FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_I WHEN ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' ELSE + DATA_OUT_ACIA_II WHEN ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + -- AMKB_TX: SPIKES AUSFILTERN und sychronisieren ------------------------------------------ PROCESS(CLK2M, AMKB_RX, AMKB_REG) BEGIN - IF rising_edge(CLK2M) THEN + if rising_edge(CLK500k) then + AMKB_TX <= AMKB_TX_sync; IF AMKB_RX = '0' THEN - IF AMKB_REG < 16 THEN - AMKB_REG <= "00000"; + IF AMKB_REG < 8 THEN + AMKB_REG <= "0000"; ELSE AMKB_REG <= AMKB_REG - 1; END IF; ELSE - IF AMKB_REG > 15 THEN - AMKB_REG <= "11111"; + IF AMKB_REG > 7 THEN + AMKB_REG <= "1111"; ELSE AMKB_REG <= AMKB_REG + 1; END IF; END IF; ELSE + AMKB_TX <= AMKB_TX; AMKB_REG <= AMKB_REG; END IF; END PROCESS; + -- acia interrupt ------------------------------------------ + acia_irq <= '0' WHEN IRQ_KEYBDn = '0' or IRQ_MIDIn = '0' ELSE '1'; + ---------------------------------------------------------------------------- -- ACIA MIDI ---------------------------------------------------------------------------- i_acia_midi : WF6850IP_TOP_SOC PORT MAP( CLK => MAIN_CLK, - RESETn => nRSTO, + RESETn => nResetatio, CS2n => '0', CS1 => FB_ADR(2), @@ -879,7 +885,7 @@ BEGIN RWn => nFB_WR, RS => FB_ADR(1), - DATA_IN => FB_AD(31 DOWNTO 24), + DATA_IN => FB_ADI(15 downto 8), DATA_OUT => DATA_OUT_ACIA_II, -- DATA_EN => DATA_EN_ACIA_II, @@ -893,19 +899,16 @@ BEGIN TXDATA => MIDI_OUT --RTSn => -- Not used. ); - - MIDI_TLR <= MIDI_OUT; + MIDI_TLR <= MIDI_IN; MIDI_OLR <= MIDI_OUT; - FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_II WHEN ACIA_CS_I = '1' AND FB_ADR(2) = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - ---------------------------------------------------------------------------- -- MFP ---------------------------------------------------------------------------- i_mfp : WF68901IP_TOP_SOC PORT MAP( -- System control: - CLK => MAIN_CLK, - RESETn => nRSTO, + CLK => not MAIN_CLK, + RESETn => nResetatio, -- Asynchronous bus control: DSn => NOT LDS, CSn => NOT MFP_CS, @@ -919,7 +922,7 @@ BEGIN GPIP_IN(7) => NOT DMA_DRQ_Q, GPIP_IN(6) => NOT RI, GPIP_IN(5) => DINTn, - GPIP_IN(4) => IRQ_ACIAn, + GPIP_IN(4) => acia_irq, GPIP_IN(3) => DSP_INT, GPIP_IN(2) => NOT CTS, GPIP_IN(1) => NOT DCD, @@ -953,35 +956,21 @@ BEGIN MFP_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 6) = x"3FE8" ELSE '0'; -- FFA00/40 MFP_INTACK <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20000" ELSE '0'; --F002'0000 LDS <= '1' WHEN MFP_CS = '1' OR MFP_INTACK = '1' ELSE '0'; - - FB_AD(23 DOWNTO 16) <= DATA_OUT_MFP WHEN MFP_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD(31 DOWNTO 10) <= (OTHERS => '0') WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - FB_AD(9 DOWNTO 2) <= DATA_OUT_MFP WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z') ; + + FB_AD(23 DOWNTO 16) <= DATA_OUT_MFP WHEN MFP_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + FB_AD(31 DOWNTO 10) <= "0000000000000000000000" WHEN MFP_INTACK = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZ"; + FB_AD(9 DOWNTO 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; FB_AD(1 DOWNTO 0) <= "00" WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE "ZZ"; - DINTn <= '0' WHEN IDE_INT = '1' AND ACP_CONF(28) = '1' ELSE '0' WHEN FDINT = '1' ELSE '0' WHEN SCSI_INT = '1' AND ACP_CONF(28) = '1' ELSE '1'; - - -- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN ------------------------------------------ - PROCESS(MAIN_CLK, nRSTO, IRQ_ACIAn, IRQ_KEYBDn, IRQ_MIDIn) - BEGIN - IF nRSTO = '0' THEN - IRQ_ACIAn <= '1'; - ELSIF rising_edge(MAIN_CLK) THEN - IRQ_ACIAn <= IRQ_KEYBDn AND IRQ_MIDIn; - ELSE - IRQ_ACIAn <= IRQ_ACIAn; - END IF; - END PROCESS; - ---------------------------------------------------------------------------- -- Sound ---------------------------------------------------------------------------- i_sound : WF2149IP_TOP_SOC PORT MAP( - SYS_CLK => MAIN_CLK, - RESETn => nRSTO, + SYS_CLK => not MAIN_CLK, + RESETn => nResetatio, WAV_CLK => CLK2M, SELn => '1', @@ -992,18 +981,11 @@ BEGIN A9n => '0', A8 => '1', - DA_IN => FB_AD(31 DOWNTO 24), + DA_IN => FB_ADI(15 downto 8), DA_OUT => DA_OUT_X, - IO_A_IN => x"00", -- All port pins are dedicated outputs. - IO_A_OUT(7) => nnIDE_RES, - IO_A_OUT(6) => LP_DIR_X, - IO_A_OUT(5) => LP_STR, - IO_A_OUT(4) => DTR, - IO_A_OUT(3) => RTS, --- IO_A_OUT(2) => FDD_D1SEL, - IO_A_OUT(1) => DSA_D, - IO_A_OUT(0) => nSDSEL, + IO_A_IN => SND_A, + IO_A_OUT => SND_A_X, -- IO_A_EN =>, -- Not required. IO_B_IN => LP_D, IO_B_OUT => LP_D_X, @@ -1017,8 +999,185 @@ BEGIN SNDCS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 2) = x"3E200" ELSE '0'; -- 8800-8803 F8800/4 SNDCS_I <= '1' WHEN SNDCS = '1' AND FB_ADR (1 DOWNTO 1) = "0" ELSE '0'; SNDIR_I <= '1' WHEN SNDCS = '1' AND nFB_WR = '0' ELSE '0'; - FB_AD(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z'); - - LP_D <= LP_D_X WHEN LP_DIR_X = '0' ELSE (OTHERS => 'Z'); + + FB_AD(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + nnIDE_RES <= SND_A_X(7); + LP_DIR_X <= SND_A_X(6); + LP_STR <= SND_A_X(5); + DTR <= SND_A_X(4); + RTS <= SND_A_X(3); + + -- FDD_D1SEL <= SND_A_X(2) + DSA_D <= SND_A_X(1); + nSDSEL <= SND_A_X(0); + SND_A <= SND_A_X; + LP_D <= LP_D_X WHEN LP_DIR_X = '0' ELSE "ZZZZZZZZ"; LP_DIR <= LP_DIR_X; + + + ---------------------------------------------------------------------------- + -- DMA Sound register + ---------------------------------------------------------------------------- + + dma_snd_cs <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 6) = x"3E24" ELSE '0'; -- F8900-F893F + + PROCESS(nRSTO,MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndmactl <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_WR = '0' and FB_B1 ='1' THEN + sndmactl <= FB_AD(23 DOWNTO 16); + ELSE + sndmactl <= sndmactl; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndmactl WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) + begin + IF nRSTO = '0' THEN + sndbashi <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_WR = '0' and FB_B1 ='1' THEN + sndbashi <= FB_AD(23 DOWNTO 16); + ELSE + sndbashi <= sndbashi; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndbashi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + PROCESS(nRSTO,MAIN_CLK,FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndbasmi <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"2" and nFB_WR = '0' and FB_B1 ='1' THEN + sndbasmi <= FB_AD(23 DOWNTO 16); + ELSE + sndbasmi <= sndbasmi; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndbasmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"2" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndbaslo <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"3" and nFB_WR = '0' and FB_B1 ='1' THEN + sndbaslo <= FB_AD(23 DOWNTO 16); + ELSE + sndbaslo <= sndbaslo; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndbaslo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"3" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + PROCESS(nRSTO,MAIN_CLK,FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndadrhi <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"4" and nFB_WR = '0' and FB_B1 ='1' THEN + sndadrhi <= FB_AD(23 DOWNTO 16); + ELSE + sndadrhi <= sndadrhi; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndadrhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"4" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndadrmi <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"5" and nFB_WR = '0' and FB_B1 ='1' THEN + sndadrmi <= FB_AD(23 DOWNTO 16); + ELSE + sndadrmi <= sndadrmi; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndadrmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"5" and nFB_OE = '0' else "ZZZZZZZZ"; + + PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndadrlo <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"6" and nFB_WR = '0' and FB_B1 ='1' THEN + sndadrlo <= FB_AD(23 DOWNTO 16); + ELSE + sndadrlo <= sndadrlo; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndadrlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"6" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndendhi <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"7" and nFB_WR = '0' and FB_B1 ='1' THEN + sndendhi <= FB_AD(23 DOWNTO 16); + ELSE + sndendhi <= sndendhi; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndendhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"7" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndendmi <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_WR = '0' and FB_B1 ='1' THEN + sndendmi <= FB_AD(23 DOWNTO 16); + ELSE + sndendmi <= sndendmi; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndendmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndendlo <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_WR = '0' and FB_B1 ='1' THEN + sndendlo <= FB_AD(23 DOWNTO 16); + ELSE + sndendlo <= sndendlo; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndendlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) + BEGIN + IF nRSTO = '0' THEN + sndmode <= x"00"; + ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_WR = '0' and FB_B1 ='1' THEN + sndmode <= FB_AD(23 DOWNTO 16); + ELSE + sndmode <= sndmode; + END IF; + END PROCESS; + + FB_AD(23 DOWNTO 16) <= sndmode WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + + ---------------------------------------------------------------------------- + -- Paddle + ---------------------------------------------------------------------------- + + paddle_cs <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 6) = x"3E48" ELSE '0'; -- F9200-F923F + + FB_AD(31 DOWNTO 16) <= x"bfff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"A" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"B" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + FB_AD(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"11" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + END rtl; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd index a140e29..9d048de 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd @@ -64,7 +64,7 @@ type BUSCYCLES is (INACTIVE, R_READ, R_WRITE, ADDRESS); component WF2149IP_WAVE port( RESETn : in bit; - SYS_CLK : in std_logic; + SYS_CLK : in bit; WAV_STRB : in bit; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd index 060058c..c2705dc 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd @@ -83,7 +83,7 @@ LIBRARY ieee; ENTITY WF2149IP_TOP_SOC IS PORT( - SYS_CLK : IN std_logic; -- Read the inforation in the header! + SYS_CLK : in bit; -- Read the inforation in the header! RESETn : IN bit; WAV_CLK : IN bit; -- Read the inforation in the header! @@ -110,7 +110,7 @@ ENTITY WF2149IP_TOP_SOC IS ); END WF2149IP_TOP_SOC; -ARCHITECTURE rtl OF WF2149IP_TOP_SOC IS +architecture STRUCTURE of WF2149IP_TOP_SOC is SIGNAL BUSCYCLE : BUSCYCLES; SIGNAL DATA_OUT_I : std_logic_vector(7 DOWNTO 0); SIGNAL DATA_EN_I : bit; @@ -127,11 +127,10 @@ BEGIN IF RESETn = '0' THEN LOCK := false; TMP := '0'; - ELSIF rising_edge(SYS_CLK) THEN + elsif SYS_CLK = '1' and SYS_CLK' event then IF WAV_CLK = '1' and LOCK = false THEN LOCK := true; TMP := not TMP; -- Divider by 2. - CASE SELn IS WHEN '1' => WAV_STRB <= '1'; WHEN OTHERS => WAV_STRB <= TMP; @@ -158,7 +157,7 @@ BEGIN BEGIN IF RESETn = '0' THEN ADR_I <= (OTHERS => '0'); - ELSIF rising_edge(SYS_CLK) THEN + elsif SYS_CLK = '1' and SYS_CLK' event then IF BUSCYCLE = ADDRESS AND A9n = '0' AND A8 = '1' AND DA_IN(7 DOWNTO 4) = x"0" THEN ADR_I <= To_BitVector(DA_IN(3 DOWNTO 0)); END IF; @@ -170,7 +169,7 @@ BEGIN BEGIN IF RESETn = '0' THEN CTRL_REG <= x"00"; - ELSIF rising_edge(SYS_CLK) THEN + elsif SYS_CLK = '1' and SYS_CLK' event then IF BUSCYCLE = R_WRITE AND ADR_I = x"7" THEN CTRL_REG <= To_BitVector(DA_IN); END IF; @@ -182,7 +181,7 @@ BEGIN IF RESETn = '0' THEN PORT_A <= x"00"; PORT_B <= x"00"; - ELSIF rising_edge(SYS_CLK) THEN + elsif SYS_CLK = '1' and SYS_CLK' event then IF BUSCYCLE = R_WRITE AND ADR_I = x"E" THEN PORT_A <= To_BitVector(DA_IN); ELSIF BUSCYCLE = R_WRITE and ADR_I = x"F" THEN @@ -227,4 +226,4 @@ BEGIN To_StdLogicVector(IO_B_IN) WHEN BUSCYCLE = R_READ and ADR_I = x"F" ELSE To_StdLogicVector(CTRL_REG) WHEN BUSCYCLE = R_READ and ADR_I = x"7" ELSE (OTHERS => '0'); -END rtl; +end STRUCTURE; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd index 8744213..d829f9b 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd @@ -65,7 +65,7 @@ use work.wf2149ip_pkg.all; entity WF2149IP_WAVE is port( RESETn : in bit; - SYS_CLK : in std_logic; + SYS_CLK : in bit; WAV_STRB : in bit; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd index e60cc43..3d5e2cf 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd @@ -67,7 +67,7 @@ use ieee.std_logic_unsigned.all; entity WF6850IP_CTRL_STATUS is port ( - CLK : in bit; + CLK : in std_logic; RESETn : in bit; CS : in bit_vector(2 downto 0); -- Active if "011". @@ -94,7 +94,7 @@ entity WF6850IP_CTRL_STATUS is CDS : out bit_vector(1 downto 0); -- Clock control. WS : out bit_vector(2 downto 0); -- Word select. TC : out bit_vector(1 downto 0); -- Transmit control. - IRQn : out bit -- Interrupt request. + IRQn : buffer bit -- Interrupt request. ); end entity WF6850IP_CTRL_STATUS; @@ -102,19 +102,14 @@ architecture BEHAVIOR of WF6850IP_CTRL_STATUS is signal CTRL_REG : bit_vector(7 downto 0); signal STATUS_REG : bit_vector(7 downto 0); signal RIE : bit; -signal IRQ_I : bit; signal CTS_In : bit; signal DCD_In : bit; signal DCD_FLAGn : bit; begin - P_SAMPLE: process - begin - wait until CLK = '0' and CLK' event; - CTS_In <= CTSn; -- Sample CTSn on the negative clock edge. - DCD_In <= DCDn; -- Sample DCDn on the negative clock edge. - end process P_SAMPLE; + CTS_In <= CTSn; + DCD_In <= DCDn; -- immer 0 - STATUS_REG(7) <= IRQ_I; + STATUS_REG(7) <= not IRQn; STATUS_REG(6) <= PE; STATUS_REG(5) <= OVR; STATUS_REG(4) <= FE; @@ -123,8 +118,8 @@ begin STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'. STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty. - DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' and E = '1' else (others => '0'); - DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' and E = '1' else '0'; + DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' else (others => '0'); + DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' else '0'; MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0'; RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1'; @@ -134,90 +129,52 @@ begin TC <= CTRL_REG(6 downto 5); RIE <= CTRL_REG(7); - P_IRQ: process - variable DCD_OVR_LOCK : boolean; - variable DCD_LOCK : boolean; - variable DCD_TRANS : boolean; + P_IRQ: process(CLK) begin - wait until CLK = '1' and CLK' event; - if RESETn = '0' then - DCD_OVR_LOCK := false; - IRQn <= '1'; - IRQ_I <= '0'; - elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then - DCD_OVR_LOCK := false; -- Enable reset by reading the status. - end if; - - -- Clear interrupts when disabled. - if CTRL_REG(7) = '0' then + if rising_edge(CLK) then + if RESETn = '0' or MCLR = '1' then IRQn <= '1'; - IRQ_I <= '0'; - elsif CTRL_REG(6 downto 5) /= "01" then - IRQn <= '1'; - IRQ_I <= '0'; - end if; - + else -- Transmitter interrupt: - if TDRE = '1' and CTRL_REG(6 downto 5) = "01" and CTS_In = '0' then + if TDRE = '1' and CTRL_REG(6 downto 5) = "01" then IRQn <= '0'; - IRQ_I <= '1'; - elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' then - IRQn <= '1'; -- Clear by writing to the transmit data register. end if; - -- Receiver interrupts: - if RDRF = '1' and RIE = '1' and DCD_In = '0' then + if RDRF = '1' and RIE = '1' then IRQn <= '0'; - IRQ_I <= '1'; - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then - IRQn <= '1'; -- Clear by reading the receive data register. end if; - + -- Overrun if OVR = '1' and RIE = '1' then IRQn <= '0'; - IRQ_I <= '1'; - DCD_OVR_LOCK := true; - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then - IRQn <= '1'; -- Clear by reading the receive data register after the status. end if; - - if DCD_In = '1' and RIE = '1' and DCD_TRANS = false then - IRQn <= '0'; - IRQ_I <= '1'; - -- DCD_TRANS is used to detect a low to high transition of DCDn. - DCD_TRANS := true; - DCD_OVR_LOCK := true; - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and DCD_OVR_LOCK = false then - IRQn <= '1'; -- Clear by reading the receive data register after the status. - elsif DCD_In = '0' then - DCD_TRANS := false; - end if; - -- The reset of the IRQ status flag: -- Clear by writing to the transmit data register. -- Clear by reading the receive data register. - if CS = "011" and RS = '1' and E = '1' then - IRQ_I <= '0'; + if CS = "011" and RS = '1' then + IRQn <= '1'; + end if; + end if; end if; end process P_IRQ; - CONTROL: process + CONTROL: process(CLK) begin - wait until CLK = '1' and CLK' event; + if rising_edge(CLK) then if RESETn = '0' then CTRL_REG <= "01000000"; - elsif CS = "011" and RWn = '0' and RS = '0' and E = '1' then + elsif CS = "011" and RWn = '0' and RS = '0' then CTRL_REG <= DATA_IN; end if; + end if; end process CONTROL; - P_DCD: process + P_DCD: process(CLK) -- This process is some kind of tricky. Refer to the MC6850 data -- sheet for more information. variable READ_LOCK : boolean; variable DCD_RELEASE : boolean; begin - wait until CLK = '1' and CLK' event; + if rising_edge(CLK) then if RESETn = '0' then DCD_FLAGn <= '0'; -- This interrupt source must initialise low. READ_LOCK := true; @@ -227,9 +184,9 @@ begin READ_LOCK := true; elsif DCD_In = '1' then DCD_FLAGn <= '1'; - elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then + elsif CS = "011" and RWn = '1' and RS = '0' then READ_LOCK := false; -- Un-READ_LOCK if receiver data register is read. - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and READ_LOCK = false then + elsif CS = "011" and RWn = '1' and RS = '1' and READ_LOCK = false then -- Clear if receiver status register read access. -- After data register has ben read and READ_LOCK again. DCD_RELEASE := true; @@ -239,6 +196,7 @@ begin DCD_FLAGn <= '0'; DCD_RELEASE := false; end if; + end if; end process P_DCD; end architecture BEHAVIOR; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd index 755e018..989447c 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd @@ -54,362 +54,379 @@ -- Minor changes. -- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; +LIBRARY ieee; + USE ieee.std_logic_1164.ALL; + USE ieee.std_logic_unsigned.ALL; -entity WF6850IP_RECEIVE is - port ( - CLK : in bit; - RESETn : in bit; - MCLR : in bit; +ENTITY WF6850IP_RECEIVE IS + PORT + ( + CLK : IN std_logic; + RESETn : IN bit; + MCLR : IN bit; - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; + CS : IN bit_vector(2 DOWNTO 0); + E : IN bit; + RWn : IN bit; + RS : IN bit; - DATA_OUT : out bit_vector(7 downto 0); - DATA_EN : out bit; + DATA_OUT : OUT bit_vector(7 DOWNTO 0); + DATA_EN : OUT bit; - WS : in bit_vector(2 downto 0); - CDS : in bit_vector(1 downto 0); + WS : IN bit_vector(2 DOWNTO 0); + CDS : IN bit_vector(1 DOWNTO 0); - RXCLK : in bit; - RXDATA : in bit; + RXCLK : IN bit; + RXDATA : IN bit; - RDRF : buffer bit; - OVR : out bit; - PE : out bit; - FE : out bit + RDRF : BUFFER bit; + OVR : OUT bit; + PE : OUT bit; + FE : OUT bit ); -end entity WF6850IP_RECEIVE; +END ENTITY WF6850IP_RECEIVE; -architecture BEHAVIOR of WF6850IP_RECEIVE is -type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC); -signal RCV_STATE, RCV_NEXT_STATE : RCV_STATES; -signal RXDATA_I : bit; -signal RXDATA_S : bit; -signal DATA_REG : bit_vector(7 downto 0); -signal SHIFT_REG : bit_vector(7 downto 0); -signal CLK_STRB : bit; -signal BITCNT : std_logic_vector(2 downto 0); -begin - P_SAMPLE: process - -- This filter provides a synchronisation to the system - -- clock, even for random baud rates of the received data - -- stream. - variable FLT_TMP : integer range 0 to 2; - begin - wait until CLK = '1' and CLK' event; - -- - RXDATA_I <= RXDATA; - -- - if RXDATA_I = '1' and FLT_TMP < 2 then - FLT_TMP := FLT_TMP + 1; - elsif RXDATA_I = '1' then - RXDATA_S <= '1'; - elsif RXDATA_I = '0' and FLT_TMP > 0 then - FLT_TMP := FLT_TMP - 1; - elsif RXDATA_I = '0' then - RXDATA_S <= '0'; - end if; - end process P_SAMPLE; - - CLKDIV: process - variable CLK_LOCK : boolean; - variable STRB_LOCK : boolean; - variable CLK_DIVCNT : std_logic_vector(6 downto 0); - begin - wait until CLK = '1' and CLK' event; - if CDS = "00" then -- Divider off. - if RXCLK = '1' and STRB_LOCK = false then - CLK_STRB <= '1'; - STRB_LOCK := true; - elsif RXCLK = '0' then - CLK_STRB <= '0'; - STRB_LOCK := false; - else - CLK_STRB <= '0'; - end if; - elsif RCV_STATE = IDLE then - -- Preset the CLKDIV with the start delays. - if CDS = "01" then - CLK_DIVCNT := "0001000"; -- Half of div by 16 mode. - elsif CDS = "10" then - CLK_DIVCNT := "0100000"; -- Half of div by 64 mode. - end if; - CLK_STRB <= '0'; - else - if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then - CLK_DIVCNT := CLK_DIVCNT - '1'; - CLK_STRB <= '0'; - CLK_LOCK := true; - elsif CDS = "01" and CLK_DIVCNT = "0000000" then - CLK_DIVCNT := "0010000"; -- Div by 16 mode. - -- - if STRB_LOCK = false then - STRB_LOCK := true; - CLK_STRB <= '1'; - else - CLK_STRB <= '0'; - end if; - elsif CDS = "10" and CLK_DIVCNT = "0000000" then - CLK_DIVCNT := "1000000"; -- Div by 64 mode. - if STRB_LOCK = false then - STRB_LOCK := true; - CLK_STRB <= '1'; - else - CLK_STRB <= '0'; - end if; - elsif RXCLK = '0' then - CLK_LOCK := false; - STRB_LOCK := false; - CLK_STRB <= '0'; - else - CLK_STRB <= '0'; - end if; - end if; - end process CLKDIV; +ARCHITECTURE rtl OF WF6850IP_RECEIVE IS + TYPE RCV_STATES IS (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC); + SIGNAL RCV_STATE, RCV_NEXT_STATE : RCV_STATES; + SIGNAL RXDATA_I : bit; + SIGNAL RXDATA_S : bit; + SIGNAL DATA_REG : bit_vector(7 DOWNTO 0); + SIGNAL SHIFT_REG : bit_vector(7 DOWNTO 0); + SIGNAL CLK_STRB : bit; + SIGNAL BITCNT : std_logic_vector(2 DOWNTO 0); +BEGIN + p_sample : PROCESS(CLK) + -- This filter provides a synchronisation to the system + -- clock, even for random baud rates of the received data + -- stream. + VARIABLE FLT_TMP : integer RANGE 0 TO 2; + BEGIN + IF rising_edge(CLK) THEN + -- + RXDATA_I <= RXDATA; + -- + IF RXDATA_I = '1' and FLT_TMP < 2 THEN + FLT_TMP := FLT_TMP + 1; + ELSIF RXDATA_I = '1' THEN + RXDATA_S <= '1'; + ELSIF RXDATA_I = '0' and FLT_TMP > 0 THEN + FLT_TMP := FLT_TMP - 1; + ELSIF RXDATA_I = '0' THEN + RXDATA_S <= '0'; + END IF; + END IF; + END PROCESS p_sample; + + clkdiv : PROCESS(CLK) + VARIABLE CLK_LOCK : boolean; + VARIABLE STRB_LOCK : boolean; + VARIABLE CLK_DIVCNT : std_logic_vector(6 DOWNTO 0); + BEGIN + IF rising_edge(CLK) THEN + IF CDS = "00" THEN -- Divider off. + IF RXCLK = '1' and STRB_LOCK = false THEN + CLK_STRB <= '1'; + STRB_LOCK := true; + ELSIF RXCLK = '0' THEN + CLK_STRB <= '0'; + STRB_LOCK := false; + ELSE + CLK_STRB <= '0'; + END IF; + ELSIF RCV_STATE = IDLE THEN + -- Preset the CLKDIV with the start delays. + IF CDS = "01" THEN + CLK_DIVCNT := "0001000"; -- Half of div by 16 mode. + ELSIF CDS = "10" THEN + CLK_DIVCNT := "0100000"; -- Half of div by 64 mode. + END IF; + CLK_STRB <= '0'; + ELSE + IF CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false THEN + CLK_DIVCNT := CLK_DIVCNT - '1'; + CLK_STRB <= '0'; + CLK_LOCK := true; + ELSIF CDS = "01" and CLK_DIVCNT = "0000000" THEN + CLK_DIVCNT := "0010000"; -- Div by 16 mode. + -- + IF STRB_LOCK = false THEN + STRB_LOCK := true; + CLK_STRB <= '1'; + ELSE + CLK_STRB <= '0'; + END IF; + ELSIF CDS = "10" and CLK_DIVCNT = "0000000" THEN + CLK_DIVCNT := "1000000"; -- Div by 64 mode. + IF STRB_LOCK = false THEN + STRB_LOCK := true; + CLK_STRB <= '1'; + ELSE + CLK_STRB <= '0'; + END IF; + ELSIF RXCLK = '0' THEN + CLK_LOCK := false; + STRB_LOCK := false; + CLK_STRB <= '0'; + ELSE + CLK_STRB <= '0'; + END IF; + END IF; + END IF; + END PROCESS clkdiv; - DATAREG: process(RESETn, CLK) - begin - if RESETn = '0' then - DATA_REG <= x"00"; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then + datareg : PROCESS(RESETn, CLK) + BEGIN + IF RESETn = '0' or MCLR = '1' THEN DATA_REG <= x"00"; - elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data. - -- Transfer from shift- to data register only if - -- data register is empty (RDRF = '0'). - DATA_REG <= '0' & SHIFT_REG(7 downto 1); - elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data. - -- Transfer from shift- to data register only if - -- data register is empty (RDRF = '0'). - DATA_REG <= SHIFT_REG; - end if; - end if; - end process DATAREG; - DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0'); - DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0'; + ELSE + IF rising_edge(CLK) THEN + IF RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' THEN -- 7 bit data. + -- Transfer from shift- to data register only if + -- data register is empty (RDRF = '0'). + DATA_REG <= '0' & SHIFT_REG(7 downto 1); + ELSIF RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' THEN -- 8 bit data. + -- Transfer from shift- to data register only if + -- data register is empty (RDRF = '0'). + DATA_REG <= SHIFT_REG; + END IF; + END IF; + END IF; + END PROCESS datareg; + + DATA_OUT <= DATA_REG WHEN CS = "011" and RWn = '1' and RS = '1' ELSE (OTHERS => '0'); + DATA_EN <= '1' WHEN CS = "011" and RWn = '1' and RS = '1' ELSE '0'; - SHIFTREG: process(RESETn, CLK) - begin - if RESETn = '0' then - SHIFT_REG <= x"00"; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then + shiftreg : PROCESS(RESETn, CLK) + BEGIN + IF RESETn = '0' or MCLR = '1' THEN SHIFT_REG <= x"00"; - elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then - SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right. - end if; - end if; - end process SHIFTREG; + ELSE + IF rising_edge(CLK) THEN + IF RCV_STATE = SAMPLE and CLK_STRB = '1' THEN + SHIFT_REG <= RXDATA_S & SHIFT_REG(7 DOWNTO 1); -- Shift right. + END IF; + END IF; + END IF; + END PROCESS shiftreg; - P_BITCNT: process - begin - wait until CLK = '1' and CLK' event; - if RCV_STATE = SAMPLE and CLK_STRB = '1' then - BITCNT <= BITCNT + '1'; - elsif RCV_STATE /= SAMPLE then - BITCNT <= (others => '0'); - end if; - end process P_BITCNT; + p_bitcnt : PROCESS(CLK) + BEGIN + IF rising_edge(CLK) THEN + IF RCV_STATE = SAMPLE and CLK_STRB = '1' THEN + BITCNT <= BITCNT + '1'; + ELSIF RCV_STATE /= SAMPLE THEN + BITCNT <= (OTHERS => '0'); + END IF; + END IF; + END PROCESS p_bitcnt; - FRAME_ERR: process(RESETn, CLK) + p_frame_err: PROCESS(RESETn, CLK) -- This module detects a framing error -- during stop bit 1 and stop bit 2. - variable FE_I: bit; - begin - if RESETn = '0' then + VARIABLE FE_I: bit; + BEGIN + IF RESETn = '0' THEN FE_I := '0'; FE <= '0'; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - FE_I := '0'; - FE <= '0'; - elsif CLK_STRB = '1' then - if RCV_STATE = STOP1 and RXDATA_S = '0' then - FE_I := '1'; - elsif RCV_STATE = STOP2 and RXDATA_S = '0' then - FE_I := '1'; - elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then - FE_I := '0'; -- Error resets when correct data appears. - end if; - end if; - if RCV_STATE = SYNC then - FE <= FE_I; -- Update the FE every SYNC time. - end if; - end if; - end process FRAME_ERR; + ELSE + IF rising_edge(CLK) THEN + IF MCLR = '1' THEN + FE_I := '0'; + FE <= '0'; + ELSIF CLK_STRB = '1' THEN + IF RCV_STATE = STOP1 and RXDATA_S = '0' THEN + FE_I := '1'; + ELSIF RCV_STATE = STOP2 and RXDATA_S = '0' THEN + FE_I := '1'; + ELSIF RCV_STATE = STOP1 or RCV_STATE = STOP2 THEN + FE_I := '0'; -- Error resets when correct data appears. + END IF; + END IF; + IF RCV_STATE = SYNC THEN + FE <= FE_I; -- Update the FE every SYNC time. + END IF; + END IF; + END IF; + END PROCESS p_frame_err; - OVERRUN: process(RESETn, CLK) - variable OVR_I : bit; - variable FIRST_READ : boolean; - begin - if RESETn = '0' then - OVR_I := '0'; - OVR <= '0'; - FIRST_READ := false; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then + p_overrun : PROCESS(RESETn, CLK) + VARIABLE OVR_I : bit; + VARIABLE FIRST_READ : boolean; + BEGIN + IF rising_edge(CLK) THEN + IF RESETn = '0' or MCLR = '1' THEN OVR_I := '0'; OVR <= '0'; FIRST_READ := false; - elsif CLK_STRB = '1' and RCV_STATE = STOP1 then - -- Overrun appears if RDRF is '1' in this state. - OVR_I := RDRF; - end if; - if CS = "011" and RWn = '1' and RS = '1' and E = '1' and OVR_I = '1' then - -- If an overrun was detected, the concerning flag is - -- set when the valid data word in the receiver data - -- register is read. Thereafter the RDRF flag is reset - -- and the overrun disappears (OVR_I goes low) after - -- a second read (in time) of the receiver data register. - if FIRST_READ = false then - OVR <= '1'; - FIRST_READ := true; - else - OVR <= '0'; + ELSE + IF CLK_STRB = '1' and RCV_STATE = STOP1 THEN + -- Overrun appears if RDRF is '1' in this state. + OVR_I := RDRF; + END IF; + IF CS = "011" and RWn = '1' and RS = '1' THEN + -- If an overrun was detected, the concerning flag is + -- set when the valid data word in the receiver data + -- register is read. Thereafter the RDRF flag is reset + -- and the overrun disappears (OVR_I goes low) after + -- a second read (in time) of the receiver data register. + IF FIRST_READ = false THEN + IF OVR_I = '1' THEN + OVR <= '1'; + OVR_I := '0'; + FIRST_READ := true; + ELSE + OVR <= '0'; + END IF; + END IF; + ELSE FIRST_READ := false; - end if; - end if; - end if; - end process OVERRUN; + END IF; + END IF; + END IF; + END PROCESS p_overrun; - PARITY_TEST: process(RESETn, CLK) - variable PAR_TMP : bit; - variable PE_I : bit; - begin - if RESETn = '0' then + p_parity_test : PROCESS(RESETn,MCLR,CLK) + VARIABLE PAR_TMP : bit; + VARIABLE PE_I : bit; + BEGIN + IF RESETn = '0' or MCLR = '1' THEN PE <= '0'; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - PE <= '0'; - elsif CLK_STRB = '1' then -- Sample parity on clock strobe. - PE_I := '0'; -- Initialise. - if RCV_STATE = PARITY then - for i in 1 to 7 loop - if i = 1 then - PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); - else - PAR_TMP := PAR_TMP xor SHIFT_REG(i); - end if; - end loop; - if WS = "000" or WS = "010" or WS = "110" then -- Even parity. - PE_I := PAR_TMP xor RXDATA_S; - elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity. - PE_I := not PAR_TMP xor RXDATA_S; - else -- No parity for WS = "100" and WS = "101". - PE_I := '0'; - end if; - end if; - end if; + ELSE + IF rising_edge(CLK) THEN + IF CLK_STRB = '1' THEN -- Sample parity on clock strobe. + PE_I := '0'; -- Initialise. + IF RCV_STATE = PARITY THEN + FOR i in 1 TO 7 LOOP + IF i = 1 THEN + PAR_TMP := SHIFT_REG(i - 1) xor SHIFT_REG(i); + ELSE + PAR_TMP := PAR_TMP xor SHIFT_REG(i); + END IF; + END LOOP; + IF WS = "000" or WS = "010" or WS = "110" THEN -- Even parity. + PE_I := PAR_TMP xor RXDATA_S; + ELSIF WS = "001" or WS = "011" or WS = "111" THEN -- Odd parity. + PE_I := not PAR_TMP xor RXDATA_S; + ELSE -- No parity for WS = "100" and WS = "101". + PE_I := '0'; + END IF; + END IF; + END IF; + END IF; -- Transmit the parity flag together with the data -- In other words: no parity to the status register -- when RDRF inhibits the data transfer to the -- receiver data register. - if RCV_STATE = SYNC and RDRF = '0' then + IF RCV_STATE = SYNC and RDRF = '0' THEN PE <= PE_I; - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then + ELSIF CS = "011" and RWn = '1' and RS = '1' THEN PE <= '0'; -- Clear when reading the data register. - end if; - end if; - end process PARITY_TEST; + END IF; + END IF; + END PROCESS p_parity_test; - P_RDRF: process(RESETn, CLK) + p_rdrf : process(RESETn, CLK) -- Receive data register full flag. - begin - if RESETn = '0' then - RDRF <= '0'; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - RDRF <= '0'; - elsif RCV_STATE = SYNC then - RDRF <= '1'; -- Data register is full until now! - elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then - RDRF <= '0'; -- After reading the data register ... - end if; - end if; - end process P_RDRF; + BEGIN + IF rising_edge(CLK) THEN + IF RESETn = '0' or MCLR = '1' THEN + RDRF <= '0'; + ELSE + IF RCV_STATE = SYNC THEN + RDRF <= '1'; -- Data register is full until now! + END IF; + IF CS = "011" and RWn = '1' and RS = '1' THEN + RDRF <= '0'; -- when reading the data register ... + END IF; + END IF; + END IF; + END PROCESS p_rdrf; - RCV_STATEREG: process(RESETn, CLK) - begin - if RESETn = '0' then + p_rcv_statereg : PROCESS(RESETn, CLK) + BEGIN + IF RESETn = '0' THEN RCV_STATE <= IDLE; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - RCV_STATE <= IDLE; - else - RCV_STATE <= RCV_NEXT_STATE; - end if; - end if; - end process RCV_STATEREG; + ELSE + IF rising_edge(CLK) THEN + IF MCLR = '1' THEN + RCV_STATE <= IDLE; + ELSE + RCV_STATE <= RCV_NEXT_STATE; + END IF; + END IF; + END IF; + END PROCESS p_rcv_statereg; - RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB) - begin - case RCV_STATE is - when IDLE => - if RXDATA_S = '0' and CDS = "00" then + p_rcv_statedec : PROCESS(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB) + BEGIN + CASE RCV_STATE IS + WHEN IDLE => + IF RXDATA_S = '0' and CDS = "00" THEN RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode. - elsif RXDATA_S = '0' and CDS = "01" then + ELSIF RXDATA_S = '0' and CDS = "01" THEN RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode. - elsif RXDATA_S = '0' and CDS = "10" then + ELSIF RXDATA_S = '0' and CDS = "10" THEN RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode. - else + ELSE RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-) - end if; - when WAIT_START => - if CLK_STRB = '1' then - if RXDATA_S = '0' then + END IF; + + WHEN WAIT_START => + IF CLK_STRB = '1' THEN + IF RXDATA_S = '0' THEN RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes. - else + ELSE RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back. - end if; - else + END IF; + ELSE RCV_NEXT_STATE <= WAIT_START; -- Stay. - end if; - when SAMPLE => - if CLK_STRB = '1' then - if BITCNT < "110" and WS(2) = '0' then + END IF; + + WHEN SAMPLE => + IF CLK_STRB = '1' THEN + IF BITCNT < "110" and WS(2) = '0' THEN RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits. - elsif BITCNT < "111" and WS(2) = '1' then + ELSIF BITCNT < "111" and WS(2) = '1' THEN RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits. - elsif WS = "100" or WS = "101" then + ELSIF WS = "100" or WS = "101" THEN RCV_NEXT_STATE <= STOP1; -- No parity check enabled. - else + ELSE RCV_NEXT_STATE <= PARITY; -- Parity enabled. - end if; - else + END IF; + ELSE RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode. - end if; - when PARITY => - if CLK_STRB = '1' then + END IF; + + WHEN PARITY => + IF CLK_STRB = '1' THEN RCV_NEXT_STATE <= STOP1; - else + ELSE RCV_NEXT_STATE <= PARITY; - end if; - when STOP1 => - if CLK_STRB = '1' then - if RXDATA_S = '0' then + END IF; + + WHEN STOP1 => + IF CLK_STRB = '1' THEN + IF RXDATA_S = '0' THEN RCV_NEXT_STATE <= SYNC; -- Framing error detected. - elsif WS = "000" or WS = "001" or WS = "100" then + ELSIF WS = "000" or WS = "001" or WS = "100" THEN RCV_NEXT_STATE <= STOP2; -- Two stop bits selected. - else + ELSE RCV_NEXT_STATE <= SYNC; -- One stop bit selected. - end if; - else + END IF; + ELSE RCV_NEXT_STATE <= STOP1; - end if; - when STOP2 => - if CLK_STRB = '1' then + END IF; + + WHEN STOP2 => + IF CLK_STRB = '1' THEN RCV_NEXT_STATE <= SYNC; - else + ELSE RCV_NEXT_STATE <= STOP2; - end if; - when SYNC => + END IF; + WHEN SYNC => RCV_NEXT_STATE <= IDLE; - end case; - end process RCV_STATEDEC; -end architecture BEHAVIOR; + END CASE; + END PROCESS p_rcv_statedec; +END ARCHITECTURE rtl; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd index be34852..ed96d8f 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd @@ -158,7 +158,6 @@ ARCHITECTURE structure OF WF6850IP_TOP_SOC IS TXDATA : OUT bit ); END COMPONENT; - SIGNAL DATA_IN_I : bit_vector(7 DOWNTO 0); SIGNAL DATA_RX : bit_vector(7 DOWNTO 0); SIGNAL DATA_RX_EN : bit; @@ -183,8 +182,7 @@ BEGIN IRQn <= '0' when IRQ_In = '0' else '1'; I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS - PORT MAP - ( + port map( CLK => CLK, RESETn => RESETn, CS(2) => CS2n, @@ -212,8 +210,7 @@ BEGIN ); I_UART_RECEIVE: WF6850IP_RECEIVE - PORT MAP - ( + port map ( CLK => CLK, RESETn => RESETn, MCLR => MCLR_I, @@ -236,8 +233,7 @@ BEGIN ); I_UART_TRANSMIT: WF6850IP_TRANSMIT - PORT MAP - ( + port map ( CLK => CLK, RESETn => RESETn, MCLR => MCLR_I, diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd index c8ae6fc..3de110a 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd @@ -63,7 +63,7 @@ use ieee.std_logic_unsigned.all; entity WF6850IP_TRANSMIT is port ( - CLK : in bit; + CLK : in std_logic; RESETn : in bit; MCLR : in bit; @@ -108,12 +108,12 @@ begin '1' when TR_STATE = STOP1 else '1' when TR_STATE = STOP2 else '1'; - CLKDIV: process + CLKDIV: process(CLK) variable CLK_LOCK : boolean; variable STRB_LOCK : boolean; variable CLK_DIVCNT : std_logic_vector(6 downto 0); begin - wait until CLK = '1' and CLK' event; + if rising_edge(CLK) then if CDS = "00" then -- divider off if TXCLK = '0' and STRB_LOCK = false then -- Works on negative TXCLK edge. CLK_STRB <= '1'; @@ -162,13 +162,14 @@ begin CLK_STRB <= '0'; end if; end if; + end if; end process CLKDIV; DATAREG: process(RESETn, CLK) begin if RESETn = '0' then DATA_REG <= x"00"; - elsif CLK = '1' and CLK' event then + elsif rising_edge(CLK) then if MCLR = '1' then DATA_REG <= x"00"; elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then @@ -183,7 +184,7 @@ begin begin if RESETn = '0' then SHIFT_REG <= x"00"; - elsif CLK = '1' and CLK' event then + elsif rising_edge(CLK) then if MCLR = '1' then SHIFT_REG <= x"00"; elsif TR_STATE = LOAD_SHFT and TDRE = '0' then @@ -198,47 +199,42 @@ begin end if; end process SHIFTREG; - P_BITCNT: process + P_BITCNT: process(CLK) -- Counter for the data bits transmitted. begin - wait until CLK = '1' and CLK' event; + if rising_edge(CLK) then if TR_STATE = SHIFTOUT and CLK_STRB = '1' then BITCNT <= BITCNT + '1'; elsif TR_STATE /= SHIFTOUT then BITCNT <= "000"; end if; + end if; end process P_BITCNT; P_TDRE: process(RESETn, CLK) -- Transmit data register empty flag. - variable LOCK : boolean; begin - if RESETn = '0' then + if rising_edge(CLK) then + if RESETn = '0' or MCLR = '1' then TDRE <= '1'; - LOCK := false; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - TDRE <= '1'; - elsif TR_NEXT_STATE = START and TR_STATE /= START then + else + if TR_NEXT_STATE = START and TR_STATE /= START then -- Data has been loaded to shift register, thus data register is free again. -- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once -- entering the state now. TDRE <= '1'; - elsif CS = "011" and RWn = '0' and RS = '1' and E = '1' and LOCK = false then - LOCK := true; - elsif E = '0' and LOCK = true then - -- This construction clears TDRE after the falling edge of E - -- and after the transmit data register has been written to. + end if; + if CS = "011" and RWn = '0' and RS = '1' then TDRE <= '0'; - LOCK := false; + end if; end if; end if; end process P_TDRE; - PARITY_GEN: process + PARITY_GEN: process(CLK) variable PAR_TMP : bit; begin - wait until CLK = '1' and CLK' event; + if rising_edge(CLK) then if TR_STATE = START then -- Calculate the parity during the start phase. for i in 1 to 7 loop if i = 1 then @@ -255,19 +251,22 @@ begin PARITY_I <= '0'; end if; end if; + end if; end process PARITY_GEN; TR_STATEREG: process(RESETn, CLK) begin if RESETn = '0' then TR_STATE <= IDLE; - elsif CLK = '1' and CLK' event then + else + if rising_edge(CLK) then if MCLR = '1' then TR_STATE <= IDLE; else TR_STATE <= TR_NEXT_STATE; end if; end if; + end if; end process TR_STATEREG; TR_STATEDEC: process(TR_STATE, CLK_STRB, TC, BITCNT, WS, TDRE, CTSn) diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf index b569002..fd3cd47 100644 --- a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf +++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf @@ -37,6 +37,7 @@ SUBDESIGN interrupt_handler VSYNC : INPUT; HSYNC : INPUT; DMA_DRQ : INPUT; + nRSTO : INPUT; nIRQ[7..2] : OUTPUT; INT_HANDLER_TA : OUTPUT; ACP_CONF[31..0] : OUTPUT; @@ -56,6 +57,8 @@ VARIABLE INT_IN[31..0] :NODE; INT_ENA[31..0] :DFFE; INT_ENA_CS :NODE; + INT_L[9..0] :DFF; + INT_LA[9..0][3..0] :DFF; ACP_CONF[31..0] :DFFE; ACP_CONF_CS :NODE; PSEUDO_BUS_ERROR :NODE; @@ -91,7 +94,7 @@ BEGIN # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & FB_ADR0 -- LLBYT # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE --- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSL�SEN, 1=INT7 AUSL�SEN +-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN INT_CTR[].CLK = MAIN_CLK; INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000"; -- $10000/4 INT_CTR[] = FB_AD[]; @@ -99,16 +102,15 @@ BEGIN INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR; INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR; INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR; - -- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2 INT_ENA[].CLK = MAIN_CLK; + INT_ENA[].CLRN = nRSTO; INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4 INT_ENA[] = FB_AD[]; INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR; INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR; INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR; INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR; - -- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR INT_CLEAR[].CLK = MAIN_CLK; INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4 @@ -116,23 +118,21 @@ BEGIN INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR; INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR; INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR; - -- INTERRUPT LATCH REGISTER READ ONLY INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4 - -- INTERRUPT !nIRQ2 = HSYNC & INT_ENA[26]; !nIRQ3 = INT_CTR0 & INT_ENA[27]; !nIRQ4 = VSYNC & INT_ENA[28]; - nIRQ5 = INT_LATCH[]==H"00000000" & INT_ENA[29]; + !nIRQ5 = INT_LATCH[]!=H"00000000" & INT_ENA[29]; !nIRQ6 = !nMFP_INT & INT_ENA[30]; !nIRQ7 = PSEUDO_BUS_ERROR & INT_ENA[31]; PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC # FB_ADR[19..4]==H"F8E0" -- VME - # FB_ADR[19..4]==H"F920" -- PADDLE - # FB_ADR[19..4]==H"F921" -- PADDLE - # FB_ADR[19..4]==H"F922" -- PADDLE +-- # FB_ADR[19..4]==H"F920" -- PADDLE +-- # FB_ADR[19..4]==H"F921" -- PADDLE +-- # FB_ADR[19..4]==H"F922" -- PADDLE # FB_ADR[19..4]==H"FFA8" -- MFP2 # FB_ADR[19..4]==H"FFA9" -- MFP2 # FB_ADR[19..4]==H"FFAA" -- MFP2 @@ -140,28 +140,38 @@ PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC # FB_ADR[19..8]==H"F87" -- TT SCSI # FB_ADR[19..4]==H"FFC2" -- ST UHR # FB_ADR[19..4]==H"FFC3" -- ST UHR - # FB_ADR[19..4]==H"F890" -- DMA SOUND - # FB_ADR[19..4]==H"F891" -- DMA SOUND - # FB_ADR[19..4]==H"F892"); -- DMA SOUND - +-- # FB_ADR[19..4]==H"F890" -- DMA SOUND +-- # FB_ADR[19..4]==H"F891" -- DMA SOUND +-- # FB_ADR[19..4]==H"F892" -- DMA SOUND + ); -- IF VIDEO ADR CHANGE TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2 -- INTERRUPT LATCH - INT_LATCH[] = H"FFFFFFFF"; - INT_LATCH0.CLK = PIC_INT & INT_ENA[0]; - INT_LATCH1.CLK = E0_INT & INT_ENA[1]; - INT_LATCH2.CLK = DVI_INT & INT_ENA[2]; - INT_LATCH3.CLK = !nPCI_INTA & INT_ENA[3]; - INT_LATCH4.CLK = !nPCI_INTB & INT_ENA[4]; - INT_LATCH5.CLK = !nPCI_INTC & INT_ENA[5]; - INT_LATCH6.CLK = !nPCI_INTD & INT_ENA[6]; - INT_LATCH7.CLK = DSP_INT & INT_ENA[7]; - INT_LATCH8.CLK = VSYNC & INT_ENA[8]; - INT_LATCH9.CLK = HSYNC & INT_ENA[9]; + INT_L[].CLK = MAIN_CLK; + INT_L[].CLRN = nRSTO; + INT_L0 = PIC_INT & INT_ENA[0]; + INT_L1 = E0_INT & INT_ENA[1]; + INT_L2 = DVI_INT & INT_ENA[2]; + INT_L3 = !nPCI_INTA & INT_ENA[3]; + INT_L4 = !nPCI_INTB & INT_ENA[4]; + INT_L5 = !nPCI_INTC & INT_ENA[5]; + INT_L6 = !nPCI_INTD & INT_ENA[6]; + INT_L7 = DSP_INT & INT_ENA[7]; + INT_L8 = VSYNC & INT_ENA[8]; + INT_L9 = HSYNC & INT_ENA[9]; --- INTERRUPT CLEAR - INT_LATCH[].CLRN = !INT_CLEAR[]; + INT_LA[][].CLK = MAIN_CLK; + INT_LATCH[] = H"FFFFFFFF"; + INT_LATCH[].CLRN = !INT_CLEAR[] & nRSTO; + FOR I IN 0 TO 9 GENERATE + INT_LA[I][].CLRN = INT_ENA[I] & nRSTO; + INT_LA[I][] = INT_LA[I][]+1 & INT_L[I] & INT_LA[I][]<7 + # INT_LA[I][]-1 & !INT_L[I] & INT_LA[I][]>8 + # 15 & INT_L[I] & INT_LA[I][]>6 + # 0 & !INT_L[I] & INT_LA[I][]<9; + INT_LATCH[I].CLK = INT_LA[I][3]; + END GENERATE; -- INT_IN INT_IN0 = PIC_INT; @@ -181,7 +191,6 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H INT_IN29 = INT_LATCH[]!=H"00000000"; INT_IN30 = !nMFP_INT; INT_IN31 = DMA_DRQ; - --*************************************************************************************** -- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE ACP_CONF[].CLK = MAIN_CLK; @@ -212,130 +221,16 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR; WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR; WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR; - WERTE[7..0][10] = FB_AD[23..16]; - WERTE[7..0][11] = FB_AD[23..16]; - WERTE[7..0][12] = FB_AD[23..16]; - WERTE[7..0][13] = FB_AD[23..16]; - WERTE[7..0][14] = FB_AD[23..16]; - WERTE[7..0][15] = FB_AD[23..16]; - WERTE[7..0][16] = FB_AD[23..16]; - WERTE[7..0][17] = FB_AD[23..16]; - WERTE[7..0][18] = FB_AD[23..16]; - WERTE[7..0][19] = FB_AD[23..16]; - WERTE[7..0][20] = FB_AD[23..16]; - WERTE[7..0][21] = FB_AD[23..16]; - WERTE[7..0][22] = FB_AD[23..16]; - WERTE[7..0][23] = FB_AD[23..16]; - WERTE[7..0][24] = FB_AD[23..16]; - WERTE[7..0][25] = FB_AD[23..16]; - WERTE[7..0][26] = FB_AD[23..16]; - WERTE[7..0][27] = FB_AD[23..16]; - WERTE[7..0][28] = FB_AD[23..16]; - WERTE[7..0][29] = FB_AD[23..16]; - WERTE[7..0][30] = FB_AD[23..16]; - WERTE[7..0][31] = FB_AD[23..16]; - WERTE[7..0][32] = FB_AD[23..16]; - WERTE[7..0][33] = FB_AD[23..16]; - WERTE[7..0][34] = FB_AD[23..16]; - WERTE[7..0][35] = FB_AD[23..16]; - WERTE[7..0][36] = FB_AD[23..16]; - WERTE[7..0][37] = FB_AD[23..16]; - WERTE[7..0][38] = FB_AD[23..16]; - WERTE[7..0][39] = FB_AD[23..16]; - WERTE[7..0][40] = FB_AD[23..16]; - WERTE[7..0][41] = FB_AD[23..16]; - WERTE[7..0][42] = FB_AD[23..16]; - WERTE[7..0][43] = FB_AD[23..16]; - WERTE[7..0][44] = FB_AD[23..16]; - WERTE[7..0][45] = FB_AD[23..16]; - WERTE[7..0][46] = FB_AD[23..16]; - WERTE[7..0][47] = FB_AD[23..16]; - WERTE[7..0][48] = FB_AD[23..16]; - WERTE[7..0][49] = FB_AD[23..16]; - WERTE[7..0][50] = FB_AD[23..16]; - WERTE[7..0][51] = FB_AD[23..16]; - WERTE[7..0][52] = FB_AD[23..16]; - WERTE[7..0][53] = FB_AD[23..16]; - WERTE[7..0][54] = FB_AD[23..16]; - WERTE[7..0][55] = FB_AD[23..16]; - WERTE[7..0][56] = FB_AD[23..16]; - WERTE[7..0][57] = FB_AD[23..16]; - WERTE[7..0][58] = FB_AD[23..16]; - WERTE[7..0][59] = FB_AD[23..16]; - WERTE[7..0][60] = FB_AD[23..16]; - WERTE[7..0][61] = FB_AD[23..16]; - WERTE[7..0][62] = FB_AD[23..16]; - WERTE[7..0][63] = FB_AD[23..16]; - WERTE[][0].ENA = RTC_ADR[]==0 & UHR_DS & !nFB_WR; - WERTE[][1].ENA = RTC_ADR[]==1 & UHR_DS & !nFB_WR; - WERTE[][2].ENA = RTC_ADR[]==2 & UHR_DS & !nFB_WR; - WERTE[][3].ENA = RTC_ADR[]==3 & UHR_DS & !nFB_WR; - WERTE[][4].ENA = RTC_ADR[]==4 & UHR_DS & !nFB_WR; - WERTE[][5].ENA = RTC_ADR[]==5 & UHR_DS & !nFB_WR; - WERTE[][6].ENA = RTC_ADR[]==6 & UHR_DS & !nFB_WR; - WERTE[][7].ENA = RTC_ADR[]==7 & UHR_DS & !nFB_WR; - WERTE[][8].ENA = RTC_ADR[]==8 & UHR_DS & !nFB_WR; - WERTE[][9].ENA = RTC_ADR[]==9 & UHR_DS & !nFB_WR; - WERTE[][10].ENA = RTC_ADR[]==10 & UHR_DS & !nFB_WR; - WERTE[][11].ENA = RTC_ADR[]==11 & UHR_DS & !nFB_WR; - WERTE[][12].ENA = RTC_ADR[]==12 & UHR_DS & !nFB_WR; - WERTE[][13].ENA = RTC_ADR[]==13 & UHR_DS & !nFB_WR; - WERTE[][14].ENA = RTC_ADR[]==14 & UHR_DS & !nFB_WR; - WERTE[][15].ENA = RTC_ADR[]==15 & UHR_DS & !nFB_WR; - WERTE[][16].ENA = RTC_ADR[]==16 & UHR_DS & !nFB_WR; - WERTE[][17].ENA = RTC_ADR[]==17 & UHR_DS & !nFB_WR; - WERTE[][18].ENA = RTC_ADR[]==18 & UHR_DS & !nFB_WR; - WERTE[][19].ENA = RTC_ADR[]==19 & UHR_DS & !nFB_WR; - WERTE[][20].ENA = RTC_ADR[]==20 & UHR_DS & !nFB_WR; - WERTE[][21].ENA = RTC_ADR[]==21 & UHR_DS & !nFB_WR; - WERTE[][22].ENA = RTC_ADR[]==22 & UHR_DS & !nFB_WR; - WERTE[][23].ENA = RTC_ADR[]==23 & UHR_DS & !nFB_WR; - WERTE[][24].ENA = RTC_ADR[]==24 & UHR_DS & !nFB_WR; - WERTE[][25].ENA = RTC_ADR[]==25 & UHR_DS & !nFB_WR; - WERTE[][26].ENA = RTC_ADR[]==26 & UHR_DS & !nFB_WR; - WERTE[][27].ENA = RTC_ADR[]==27 & UHR_DS & !nFB_WR; - WERTE[][28].ENA = RTC_ADR[]==28 & UHR_DS & !nFB_WR; - WERTE[][29].ENA = RTC_ADR[]==29 & UHR_DS & !nFB_WR; - WERTE[][30].ENA = RTC_ADR[]==30 & UHR_DS & !nFB_WR; - WERTE[][31].ENA = RTC_ADR[]==31 & UHR_DS & !nFB_WR; - WERTE[][32].ENA = RTC_ADR[]==32 & UHR_DS & !nFB_WR; - WERTE[][33].ENA = RTC_ADR[]==33 & UHR_DS & !nFB_WR; - WERTE[][34].ENA = RTC_ADR[]==34 & UHR_DS & !nFB_WR; - WERTE[][35].ENA = RTC_ADR[]==35 & UHR_DS & !nFB_WR; - WERTE[][36].ENA = RTC_ADR[]==36 & UHR_DS & !nFB_WR; - WERTE[][37].ENA = RTC_ADR[]==37 & UHR_DS & !nFB_WR; - WERTE[][38].ENA = RTC_ADR[]==38 & UHR_DS & !nFB_WR; - WERTE[][39].ENA = RTC_ADR[]==39 & UHR_DS & !nFB_WR; - WERTE[][40].ENA = RTC_ADR[]==40 & UHR_DS & !nFB_WR; - WERTE[][41].ENA = RTC_ADR[]==41 & UHR_DS & !nFB_WR; - WERTE[][42].ENA = RTC_ADR[]==42 & UHR_DS & !nFB_WR; - WERTE[][43].ENA = RTC_ADR[]==43 & UHR_DS & !nFB_WR; - WERTE[][44].ENA = RTC_ADR[]==44 & UHR_DS & !nFB_WR; - WERTE[][45].ENA = RTC_ADR[]==45 & UHR_DS & !nFB_WR; - WERTE[][46].ENA = RTC_ADR[]==46 & UHR_DS & !nFB_WR; - WERTE[][47].ENA = RTC_ADR[]==47 & UHR_DS & !nFB_WR; - WERTE[][48].ENA = RTC_ADR[]==48 & UHR_DS & !nFB_WR; - WERTE[][49].ENA = RTC_ADR[]==49 & UHR_DS & !nFB_WR; - WERTE[][50].ENA = RTC_ADR[]==50 & UHR_DS & !nFB_WR; - WERTE[][51].ENA = RTC_ADR[]==51 & UHR_DS & !nFB_WR; - WERTE[][52].ENA = RTC_ADR[]==52 & UHR_DS & !nFB_WR; - WERTE[][53].ENA = RTC_ADR[]==53 & UHR_DS & !nFB_WR; - WERTE[][54].ENA = RTC_ADR[]==54 & UHR_DS & !nFB_WR; - WERTE[][55].ENA = RTC_ADR[]==55 & UHR_DS & !nFB_WR; - WERTE[][56].ENA = RTC_ADR[]==56 & UHR_DS & !nFB_WR; - WERTE[][57].ENA = RTC_ADR[]==57 & UHR_DS & !nFB_WR; - WERTE[][58].ENA = RTC_ADR[]==58 & UHR_DS & !nFB_WR; - WERTE[][59].ENA = RTC_ADR[]==59 & UHR_DS & !nFB_WR; - WERTE[][60].ENA = RTC_ADR[]==60 & UHR_DS & !nFB_WR; - WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR; - WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR; - WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR; - + FOR I IN 10 TO 63 GENERATE + WERTE[7..0][I] = FB_AD[23..16]; + END GENERATE; + FOR I IN 0 TO 63 GENERATE + WERTE[][I].ENA = RTC_ADR[]==I & UHR_DS & !nFB_WR; + END GENERATE; PIC_INT_SYNC[].CLK = MAIN_CLK; PIC_INT_SYNC[0] = PIC_INT; PIC_INT_SYNC[1] = PIC_INT_SYNC[0]; PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0]; - UPDATE_ON = !WERTE[7][11]; WERTE[6][10].CLRN = GND; -- KEIN UIP UPDATE_ON = !WERTE[7][11]; -- UPDATE ON OFF @@ -343,57 +238,48 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H WERTE[1][11] = VCC; -- IMMER 24H FORMAT WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR WERTE[7][13] = VCC; -- IMMER RICHTIG - --- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F�R R�CKSCHALTUNG) +-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG) SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL WERTE[0][13] = SOMMERZEIT; WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT); WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13]; --LETZTER SONNTAG IM OKTOBER - -- ACHTELSEKUNDEN ACHTELSEKUNDEN[].CLK = MAIN_CLK; ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1; ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON; - -- SEKUNDEN INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON; - WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN Z�HLEN BIS 59 + WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN ZÄHLEN BIS 59 WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); - -- MINUTEN INC_MIN = INC_SEC & WERTE[][0]==59; -- - WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN Z�HLEN BIS 59 + WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN ZÄHLEN BIS 59 WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- - -- STUNDEN INC_STD = INC_MIN & WERTE[][2]==59; - WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN Z�HLEN BIS 23 + WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN ZÄHLEN BIS 23 WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT -- WOCHENTAG UND TAG - INC_TAG = INC_STD & WERTE[][2]==23; - WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG Z�HLEN BIS 7 + WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG ZÄHLEN BIS 7 # 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER WERTE[][6].ENA = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12) # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11) # 29 & WERTE[][8]==2 & WERTE[1..0][9]==0 # 28 & WERTE[][8]==2 & WERTE[1..0][9]!=0; - WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG Z�HLEN BIS MONATSENDE + WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG ZÄHLEN BIS MONATSENDE # 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- - -- MONATE INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; -- - WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE Z�HLEN BIS 12 + WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE ZÄHLEN BIS 12 # 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); - -- JAHR INC_JAHR = INC_MONAT & WERTE[][8]==12; -- - WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE Z�HLEN BIS 99 + WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE ZÄHLEN BIS 99 WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); - -- TRISTATE OUTPUT FB_AD[31..24] = lpm_bustri_BYT( @@ -475,7 +361,6 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H # INT_CLEAR_CS & INT_IN[23..16] # ACP_CONF_CS & ACP_CONF[23..16] ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); - FB_AD[15..8] = lpm_bustri_BYT( INT_CTR_CS & INT_CTR[15..8] # INT_ENA_CS & INT_ENA[15..8] @@ -483,7 +368,6 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H # INT_CLEAR_CS & INT_IN[15..8] # ACP_CONF_CS & ACP_CONF[15..8] ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); - FB_AD[7..0] = lpm_bustri_BYT( INT_CTR_CS & INT_CTR[7..0] # INT_ENA_CS & INT_ENA[7..0] diff --git a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd index 04aeb66..b083539 100644 --- a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd +++ b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd @@ -28,29 +28,30 @@ ENTITY blitter IS -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! PORT ( - nRSTO : IN STD_LOGIC; - MAIN_CLK : IN STD_LOGIC; - FB_ALE : IN STD_LOGIC; - nFB_WR : IN STD_LOGIC; - nFB_OE : IN STD_LOGIC; - FB_SIZE0 : IN STD_LOGIC; - FB_SIZE1 : IN STD_LOGIC; - VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0); - BLITTER_ON : IN STD_LOGIC; - FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0); - nFB_CS1 : IN STD_LOGIC; - nFB_CS2 : IN STD_LOGIC; - nFB_CS3 : IN STD_LOGIC; - DDRCLK0 : IN STD_LOGIC; - BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0); - BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0); - BLITTER_RUN : OUT STD_LOGIC; - BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0); - BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0); - BLITTER_SIG : OUT STD_LOGIC; - BLITTER_WR : OUT STD_LOGIC; - BLITTER_TA : OUT STD_LOGIC; - FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0) + nRSTO : IN std_logic; + MAIN_CLK : IN std_logic; + FB_ALE : IN std_logic; + nFB_WR : IN std_logic; + nFB_OE : IN std_logic; + FB_SIZE0 : IN std_logic; + FB_SIZE1 : IN std_logic; + VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0); + BLITTER_ON : IN std_logic; + FB_ADR : IN std_logic_vector(31 DOWNTO 0); + nFB_CS1 : IN std_logic; + nFB_CS2 : IN std_logic; + nFB_CS3 : IN std_logic; + DDRCLK0 : IN std_logic; + BLITTER_DIN : IN std_logic_vector(127 DOWNTO 0); + BLITTER_DACK : IN std_logic_vector(4 DOWNTO 0); + SR_BLITTER_DACK : IN std_logic; + BLITTER_RUN : OUT std_logic; + BLITTER_DOUT : OUT std_logic_vector(127 DOWNTO 0); + BLITTER_ADR : OUT std_logic_vector(31 DOWNTO 0); + BLITTER_SIG : OUT std_logic; + BLITTER_WR : OUT std_logic; + BLITTER_TA : OUT std_logic; + FB_AD : INOUT std_logic_vector(31 DOWNTO 0) ); -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! diff --git a/FPGA_Quartus_13.1/Video/BLITTER/altsyncram0.qip b/FPGA_Quartus_13.1/Video/BLITTER/altsyncram0.qip new file mode 100644 index 0000000..c42bd21 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/BLITTER/altsyncram0.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTSYNCRAM" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.tdf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.cmp"] diff --git a/FPGA_Quartus_13.1/Video/BLITTER/lpm_clshift0.qip b/FPGA_Quartus_13.1/Video/BLITTER/lpm_clshift0.qip new file mode 100644 index 0000000..737f0c0 --- /dev/null +++ b/FPGA_Quartus_13.1/Video/BLITTER/lpm_clshift0.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_CLSHIFT" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.tdf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.cmp"] diff --git a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf index f74f1dd..28c1ef3 100644 --- a/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf +++ b/FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf @@ -1,4 +1,4 @@ -TITLE "VIDEO MODI AND CLUT CONTROL"; +TITLE "VIDEO MODUSE UND CLUT CONTROL"; -- CREATED BY FREDI ASCHWANDEN @@ -98,12 +98,12 @@ VARIABLE VDL_LWD[15..0] :DFFE; VDL_LWD_CS :NODE; -- DIV. CONTROL REGISTER - CLUT_TA :DFF; -- needs one wait state + CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT HSYNC :DFF; HSYNC_I[7..0] :DFF; - HSY_LEN[7..0] :DFF; -- length of hsync pulse in pixel_clk + HSY_LEN[7..0] :DFF; -- LÄNGE HSYNC PULS IN PIXEL_CLK HSYNC_START :DFF; - LAST :DFF; -- reached last pixel of a line + LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT VSYNC :DFF; VSYNC_START :DFFE; VSYNC_I[2..0] :DFFE; @@ -191,7 +191,6 @@ VARIABLE VDL_VCT_CS :NODE; VDL_VMD[3..0] :DFFE; VDL_VMD_CS :NODE; - ACP_VCTR6_DUP : NODE; BEGIN -- BYT SELECT 32 BIT @@ -204,75 +203,46 @@ BEGIN FB_B3 = FB_ADR[1..0] == 3 -- ADR==3 # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - -- BYT SELECT 16 BIT FB_16B0 = FB_ADR[0] == 0; -- ADR==0 FB_16B1 = FB_ADR[0] == 1 -- ADR==1 # !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT - -- ACP CLUT -- ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10] == H"0"; -- 0-3FF/1024 ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE; ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR; - CLUT_TA.CLK = MAIN_CLK; CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA; - - --FALCON CLUT -- FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10] == H"3E6"; -- $F9800/$400 FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; - - -- ST CLUT -- ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5] == H"7C12"; -- $F8240/$20 ST_CLUT_RD = ST_CLUT_CS & !nFB_OE; ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR; - - -- ST SHIFT MODE ST_SHIFT_MODE[].CLK = MAIN_CLK; ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C130"; -- $F8260/2 ST_SHIFT_MODE[] = FB_AD[25..24]; ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0; - COLOR1 = ST_SHIFT_MODE[] == B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO COLOR2 = ST_SHIFT_MODE[] == B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN COLOR4 = ST_SHIFT_MODE[] == B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN - - -- FALCON SHIFT MODE FALCON_SHIFT_MODE[].CLK = MAIN_CLK; FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C133"; -- $F8266/2 FALCON_SHIFT_MODE[] = FB_AD[26..16]; FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2; FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3; - CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4; - COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON; COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; - - - -- ACP VIDEO CONTROL - -- BIT 0=ACP VIDEO ON, - -- 1=POWER ON VIDEO DAC, - -- 2=ACP 24BIT, - -- 3=ACP 16BIT, - -- 4=ACP 8BIT, - -- 5=ACP 1BIT, - -- 6=FALCON SHIFT MODE, - -- 7=ST SHIFT MODE, - -- 9..8= VCLK FREQUENZ, - -- 15=-SYNC ALLOWED, - -- 31..16=VIDEO_RAM_CTR, - -- 25=RANDFARBE EINSCHALTEN, - -- 26=STANDARD ATARI SYNCS +-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS ACP_VCTR[].CLK = MAIN_CLK; ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2] == H"100"; -- $400/4 ACP_VCTR[31..8] = FB_AD[31..8]; @@ -283,10 +253,8 @@ BEGIN ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR; ACP_VIDEO_ON = ACP_VCTR0; nPD_VGA = ACP_VCTR1; - -- ATARI MODUS - ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFL�SUNG - + ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFLÖSUNG -- HORIZONTAL TIMING 640x480 ATARI_HH[].CLK = MAIN_CLK; ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4 @@ -295,7 +263,6 @@ BEGIN ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR; ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR; ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR; - -- VERTIKAL TIMING 640x480 ATARI_VH[].CLK = MAIN_CLK; ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4 @@ -304,7 +271,6 @@ BEGIN ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR; ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR; ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR; - -- HORIZONTAL TIMING 320x240 ATARI_HL[].CLK = MAIN_CLK; ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4 @@ -313,7 +279,6 @@ BEGIN ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR; ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR; ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR; - -- VERTIKAL TIMING 320x240 ATARI_VL[].CLK = MAIN_CLK; ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4 @@ -322,8 +287,6 @@ BEGIN ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR; ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR; ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR; - - -- VIDEO PLL CONFIG VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY VR_WR.CLK = MAIN_CLK; @@ -335,28 +298,21 @@ BEGIN VR_FRQ[].CLK = MAIN_CLK; VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04"; VR_FRQ[] = FB_AD[23..16]; - -- VIDEO PLL RECONFIG VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800 VIDEO_RECONFIG.CLK = MAIN_CLK; VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG; - ------------------------------------------------------------------------------------------------------------------------ VIDEO_RAM_CTR[] = ACP_VCTR[31..16]; - -------------- COLOR MODE IM ACP SETZEN COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON; ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1; - -- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; - - -- duplicate ACP_VCTR6 according to TimeQuest recommendations - ACP_VCTR6_DUP = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; - ACP_VCTR6 = ACP_VCTR6_DUP; + ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0; FALCON_VIDEO = ACP_VCTR7; FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16; @@ -369,9 +325,7 @@ BEGIN # B"101" & COLOR16 # B"110" & COLOR24 # B"111" & RAND_ON; - -- DIVERSE (VIDEO)-REGISTER ---------------------------- - -- RANDFARBE CCR[].CLK = MAIN_CLK; CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4 @@ -379,129 +333,109 @@ BEGIN CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR; CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR; CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR; - --SYS CTR SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2 SYS_CTR[].CLK = MAIN_CLK; SYS_CTR[6..0] = FB_AD[22..16]; SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3; BLITTER_ON = !SYS_CTR3; - --VDL_LOF VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2 VDL_LOF[].CLK = MAIN_CLK; VDL_LOF[] = FB_AD[31..16]; VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2; VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3; - --VDL_LWD VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2 VDL_LWD[].CLK = MAIN_CLK; VDL_LWD[] = FB_AD[31..16]; VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0; VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1; - -- HORIZONTAL - -- VDL_HHT VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2 VDL_HHT[].CLK = MAIN_CLK; VDL_HHT[] = FB_AD[27..16]; VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2; VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3; - -- VDL_HBE VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2 VDL_HBE[].CLK = MAIN_CLK; VDL_HBE[] = FB_AD[27..16]; VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2; VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3; - -- VDL_HDB VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2 VDL_HDB[].CLK = MAIN_CLK; VDL_HDB[] = FB_AD[27..16]; VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0; VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1; - -- VDL_HDE VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2 VDL_HDE[].CLK = MAIN_CLK; VDL_HDE[] = FB_AD[27..16]; VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2; VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3; - -- VDL_HBB VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2 VDL_HBB[].CLK = MAIN_CLK; VDL_HBB[] = FB_AD[27..16]; VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0; VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1; - -- VDL_HSS VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2 VDL_HSS[].CLK = MAIN_CLK; VDL_HSS[] = FB_AD[27..16]; VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0; VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1; - -- VERTIKAL - -- VDL_VBE VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2 VDL_VBE[].CLK = MAIN_CLK; VDL_VBE[] = FB_AD[26..16]; VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2; VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3; - -- VDL_VDB VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2 VDL_VDB[].CLK = MAIN_CLK; VDL_VDB[] = FB_AD[26..16]; VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0; VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1; - -- VDL_VDE VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2 VDL_VDE[].CLK = MAIN_CLK; VDL_VDE[] = FB_AD[26..16]; VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2; VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3; - -- VDL_VBB VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2 VDL_VBB[].CLK = MAIN_CLK; VDL_VBB[] = FB_AD[26..16]; VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0; VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1; - -- VDL_VSS VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2 VDL_VSS[].CLK = MAIN_CLK; VDL_VSS[] = FB_AD[26..16]; VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0; VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1; - -- VDL_VFT VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2 VDL_VFT[].CLK = MAIN_CLK; VDL_VFT[] = FB_AD[26..16]; VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2; VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3; - -- VDL_VCT VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2 VDL_VCT[].CLK = MAIN_CLK; VDL_VCT[] = FB_AD[24..16]; VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0; VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1; - -- VDL_VMD VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2 VDL_VMD[].CLK = MAIN_CLK; VDL_VMD[] = FB_AD[19..16]; VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3; - --- REGISTER OUT FB_AD[31..16] = lpm_bustri_WORD( ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000") @@ -550,9 +484,8 @@ BEGIN # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS; - -- VIDEO AUSGABE SETZEN - CLK17M.CLK = MAIN_CLK; + CLK17M.CLK = CLK33M; CLK17M = !CLK17M; CLK13M.CLK = CLK25M; CLK13M = !CLK13M; @@ -563,9 +496,8 @@ BEGIN # CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" # CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" # CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9]; - -------------------------------------------------------------- - -- HORIZONTALE SYNC L�NGE in PIXEL_CLK +-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK ---------------------------------------------------------------- HSY_LEN[].CLK = MAIN_CLK; HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) @@ -585,7 +517,6 @@ BEGIN HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN # 640 & !VDL_VMD2; - -- DOPPELZEILENMODUS DOP_ZEI.CLK = MAIN_CLK; DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS @@ -593,7 +524,7 @@ BEGIN INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC # DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC DOP_FIFO_CLR.CLK = PIXEL_CLK; - DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO L�SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START + DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 @@ -635,8 +566,7 @@ BEGIN # ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 # ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 # (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; - - -- Z�HLER +-- ZÄHLER LAST.CLK = PIXEL_CLK; LAST = VHCNT[]==(H_TOTAL[]-2); VHCNT[].CLK = PIXEL_CLK; @@ -644,11 +574,10 @@ BEGIN VVCNT[].CLK = PIXEL_CLK; VVCNT[].ENA = LAST; VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1); - -- DISPLAY ON OFF DPO_ZL.CLK = PIXEL_CLK; DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]=(VDIS_START[]-1)) & (VVCNT[] "AUTO", - clk0_divide_by => 66, + clk0_divide_by => 11, clk0_duty_cycle => 50, - clk0_multiply_by => 1, + clk0_multiply_by => 16, clk0_phase_shift => "0", - clk1_divide_by => 6875, + clk1_divide_by => 33, clk1_duty_cycle => 50, - clk1_multiply_by => 512, + clk1_multiply_by => 16, clk1_phase_shift => "0", clk2_divide_by => 1375, clk2_duty_cycle => 50, @@ -218,7 +218,7 @@ BEGIN PORT MAP ( inclk => sub_wire6, clk => sub_wire0, - locked => sub_wire2 + locked => sub_wire4 ); @@ -244,14 +244,14 @@ END SYN; -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "90" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900" -- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.457600" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000" -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.576000" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" @@ -270,21 +270,21 @@ END SYN; -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "67" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67" -- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.50000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" @@ -298,7 +298,7 @@ END SYN; -- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" @@ -338,13 +338,13 @@ END SYN; -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "66" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11" -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "6875" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33" -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "512" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1375" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" @@ -406,17 +406,17 @@ END SYN; -- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE diff --git a/FPGA_Quartus_13.1/altpll2.bsf b/FPGA_Quartus_13.1/altpll2.bsf index 4bad59d..ac3d77f 100644 --- a/FPGA_Quartus_13.1/altpll2.bsf +++ b/FPGA_Quartus_13.1/altpll2.bsf @@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 1991-2014 Altera Corporation +Copyright (C) 1991-2010 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing @@ -18,100 +18,100 @@ programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ -(header "symbol" (version "1.2")) +(header "symbol" (version "1.1")) (symbol - (rect 0 0 256 200) - (text "altpll2" (rect 111 0 153 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 185 26 196)(font "Arial" )) + (rect 0 0 304 248) + (text "altpll2" (rect 132 1 179 20)(font "Arial" (font_size 10))) + (text "inst" (rect 8 229 31 244)(font "Arial" )) (port - (pt 0 64) + (pt 0 72) (input) - (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8))) - (line (pt 0 64)(pt 40 64)) + (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 48 72)(line_width 1)) ) (port - (pt 256 64) + (pt 304 72) (output) - (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c0" (rect 241 51 253 63)(font "Arial" (font_size 8))) + (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8))) + (line (pt 304 72)(pt 272 72)(line_width 1)) ) (port - (pt 256 80) + (pt 304 96) (output) - (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) - (text "c1" (rect 241 67 251 79)(font "Arial" (font_size 8))) + (text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8))) + (line (pt 304 96)(pt 272 96)(line_width 1)) ) (port - (pt 256 96) + (pt 304 120) (output) - (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c2" (rect 241 83 253 95)(font "Arial" (font_size 8))) + (text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8))) + (line (pt 304 120)(pt 272 120)(line_width 1)) ) (port - (pt 256 112) + (pt 304 144) (output) - (text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c3" (rect 241 99 253 111)(font "Arial" (font_size 8))) + (text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8))) + (line (pt 304 144)(pt 272 144)(line_width 1)) ) (port - (pt 256 128) + (pt 304 168) (output) - (text "c4" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c4" (rect 241 115 253 127)(font "Arial" (font_size 8))) + (text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c4" (rect 287 152 301 168)(font "Arial" (font_size 8))) + (line (pt 304 168)(pt 272 168)(line_width 1)) ) (drawing - (text "Cyclone III" (rect 198 186 442 382)(font "Arial" )) - (text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" )) - (text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" )) - (text "Clk " (rect 51 91 117 192)(font "Arial" )) - (text "Ratio" (rect 71 91 165 192)(font "Arial" )) - (text "Ph (dg)" (rect 97 91 225 192)(font "Arial" )) - (text "DC (%)" (rect 132 91 296 192)(font "Arial" )) - (text "c0" (rect 54 104 119 218)(font "Arial" )) - (text "4/1" (rect 76 104 165 218)(font "Arial" )) - (text "240.00" (rect 98 104 225 218)(font "Arial" )) - (text "50.00" (rect 136 104 296 218)(font "Arial" )) - (text "c1" (rect 54 117 118 244)(font "Arial" )) - (text "4/1" (rect 76 117 165 244)(font "Arial" )) - (text "0.00" (rect 103 117 225 244)(font "Arial" )) - (text "50.00" (rect 136 117 296 244)(font "Arial" )) - (text "c2" (rect 54 130 119 270)(font "Arial" )) - (text "4/1" (rect 76 130 165 270)(font "Arial" )) - (text "180.00" (rect 98 130 224 270)(font "Arial" )) - (text "50.00" (rect 136 130 296 270)(font "Arial" )) - (text "c3" (rect 54 143 119 296)(font "Arial" )) - (text "4/1" (rect 76 143 165 296)(font "Arial" )) - (text "105.00" (rect 98 143 224 296)(font "Arial" )) - (text "50.00" (rect 136 143 296 296)(font "Arial" )) - (text "c4" (rect 54 156 119 322)(font "Arial" )) - (text "2/1" (rect 76 156 165 322)(font "Arial" )) - (text "270.00" (rect 98 156 225 322)(font "Arial" )) - (text "50.00" (rect 136 156 296 322)(font "Arial" )) - (line (pt 0 0)(pt 257 0)) - (line (pt 257 0)(pt 257 201)) - (line (pt 0 201)(pt 257 201)) - (line (pt 0 0)(pt 0 201)) - (line (pt 48 89)(pt 164 89)) - (line (pt 48 101)(pt 164 101)) - (line (pt 48 114)(pt 164 114)) - (line (pt 48 127)(pt 164 127)) - (line (pt 48 140)(pt 164 140)) - (line (pt 48 153)(pt 164 153)) - (line (pt 48 166)(pt 164 166)) - (line (pt 48 89)(pt 48 166)) - (line (pt 68 89)(pt 68 166)(line_width 3)) - (line (pt 94 89)(pt 94 166)(line_width 3)) - (line (pt 129 89)(pt 129 166)(line_width 3)) - (line (pt 163 89)(pt 163 166)) - (line (pt 40 48)(pt 223 48)) - (line (pt 223 48)(pt 223 183)) - (line (pt 40 183)(pt 223 183)) - (line (pt 40 48)(pt 40 183)) - (line (pt 255 64)(pt 223 64)) - (line (pt 255 80)(pt 223 80)) - (line (pt 255 96)(pt 223 96)) - (line (pt 255 112)(pt 223 112)) - (line (pt 255 128)(pt 223 128)) + (text "Cyclone III" (rect 229 230 277 244)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" )) + (text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" )) + (text "Clk " (rect 59 111 76 125)(font "Arial" )) + (text "Ratio" (rect 85 111 109 125)(font "Arial" )) + (text "Ph (dg)" (rect 119 111 154 125)(font "Arial" )) + (text "DC (%)" (rect 164 111 199 125)(font "Arial" )) + (text "c0" (rect 63 129 75 143)(font "Arial" )) + (text "4/1" (rect 91 129 106 143)(font "Arial" )) + (text "240.00" (rect 120 129 153 143)(font "Arial" )) + (text "50.00" (rect 169 129 196 143)(font "Arial" )) + (text "c1" (rect 63 147 75 161)(font "Arial" )) + (text "4/1" (rect 91 147 106 161)(font "Arial" )) + (text "0.00" (rect 127 147 148 161)(font "Arial" )) + (text "50.00" (rect 169 147 196 161)(font "Arial" )) + (text "c2" (rect 63 165 75 179)(font "Arial" )) + (text "4/1" (rect 91 165 106 179)(font "Arial" )) + (text "180.00" (rect 120 165 153 179)(font "Arial" )) + (text "50.00" (rect 169 165 196 179)(font "Arial" )) + (text "c3" (rect 63 183 75 197)(font "Arial" )) + (text "4/1" (rect 91 183 106 197)(font "Arial" )) + (text "105.00" (rect 120 183 153 197)(font "Arial" )) + (text "50.00" (rect 169 183 196 197)(font "Arial" )) + (text "c4" (rect 63 201 75 215)(font "Arial" )) + (text "2/1" (rect 91 201 106 215)(font "Arial" )) + (text "270.00" (rect 120 201 153 215)(font "Arial" )) + (text "50.00" (rect 169 201 196 215)(font "Arial" )) + (line (pt 0 0)(pt 305 0)(line_width 1)) + (line (pt 305 0)(pt 305 249)(line_width 1)) + (line (pt 0 249)(pt 305 249)(line_width 1)) + (line (pt 0 0)(pt 0 249)(line_width 1)) + (line (pt 56 108)(pt 206 108)(line_width 1)) + (line (pt 56 125)(pt 206 125)(line_width 1)) + (line (pt 56 143)(pt 206 143)(line_width 1)) + (line (pt 56 161)(pt 206 161)(line_width 1)) + (line (pt 56 179)(pt 206 179)(line_width 1)) + (line (pt 56 197)(pt 206 197)(line_width 1)) + (line (pt 56 215)(pt 206 215)(line_width 1)) + (line (pt 56 108)(pt 56 215)(line_width 1)) + (line (pt 82 108)(pt 82 215)(line_width 3)) + (line (pt 116 108)(pt 116 215)(line_width 3)) + (line (pt 161 108)(pt 161 215)(line_width 3)) + (line (pt 205 108)(pt 205 215)(line_width 1)) + (line (pt 48 56)(pt 272 56)(line_width 1)) + (line (pt 272 56)(pt 272 232)(line_width 1)) + (line (pt 48 232)(pt 272 232)(line_width 1)) + (line (pt 48 56)(pt 48 232)(line_width 1)) ) ) diff --git a/FPGA_Quartus_13.1/altpll2.cmp b/FPGA_Quartus_13.1/altpll2.cmp index 2a70d95..6915d3c 100644 --- a/FPGA_Quartus_13.1/altpll2.cmp +++ b/FPGA_Quartus_13.1/altpll2.cmp @@ -1,4 +1,4 @@ ---Copyright (C) 1991-2014 Altera Corporation +--Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/FPGA_Quartus_13.1/altpll2.inc b/FPGA_Quartus_13.1/altpll2.inc index db081f6..91f248d 100644 --- a/FPGA_Quartus_13.1/altpll2.inc +++ b/FPGA_Quartus_13.1/altpll2.inc @@ -1,4 +1,4 @@ ---Copyright (C) 1991-2014 Altera Corporation +--Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/FPGA_Quartus_13.1/altpll2.qip b/FPGA_Quartus_13.1/altpll2.qip index 294e5db..e31d829 100644 --- a/FPGA_Quartus_13.1/altpll2.qip +++ b/FPGA_Quartus_13.1/altpll2.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name IP_TOOL_VERSION "9.1" set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"] diff --git a/FPGA_Quartus_13.1/altpll2.vhd b/FPGA_Quartus_13.1/altpll2.vhd index c79f465..2ee39a9 100644 --- a/FPGA_Quartus_13.1/altpll2.vhd +++ b/FPGA_Quartus_13.1/altpll2.vhd @@ -14,11 +14,11 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ ---Copyright (C) 1991-2014 Altera Corporation +--Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing @@ -140,8 +140,8 @@ ARCHITECTURE SYN OF altpll2 IS width_clock : NATURAL ); PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) ); END COMPONENT; @@ -149,14 +149,14 @@ BEGIN sub_wire8_bv(0 DOWNTO 0) <= "0"; sub_wire8 <= To_stdlogicvector(sub_wire8_bv); sub_wire5 <= sub_wire0(4); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; + sub_wire4 <= sub_wire0(3); + sub_wire3 <= sub_wire0(2); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + c2 <= sub_wire3; + c3 <= sub_wire4; c4 <= sub_wire5; sub_wire6 <= inclk0; sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; @@ -293,7 +293,7 @@ END SYN; -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" @@ -459,18 +459,18 @@ END SYN; -- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" -- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 -- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 -- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE diff --git a/FPGA_Quartus_13.1/altpll3.bsf b/FPGA_Quartus_13.1/altpll3.bsf index 98eb9cf..1665956 100644 --- a/FPGA_Quartus_13.1/altpll3.bsf +++ b/FPGA_Quartus_13.1/altpll3.bsf @@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 1991-2014 Altera Corporation +Copyright (C) 1991-2010 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing @@ -18,88 +18,95 @@ programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ -(header "symbol" (version "1.2")) +(header "symbol" (version "1.1")) (symbol - (rect 0 0 256 184) - (text "altpll3" (rect 111 0 153 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 169 26 180)(font "Arial" )) + (rect 0 0 272 200) + (text "altpll3" (rect 119 0 159 16)(font "Arial" (font_size 10))) + (text "inst" (rect 8 184 25 196)(font "Arial" )) (port (pt 0 64) (input) - (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8))) - (line (pt 0 64)(pt 40 64)) + (text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 40 64)(line_width 1)) ) (port - (pt 256 64) + (pt 272 64) (output) - (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c0" (rect 241 51 253 63)(font "Arial" (font_size 8))) + (text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8))) + (text "c0" (rect 257 51 268 64)(font "Arial" (font_size 8))) + (line (pt 272 64)(pt 224 64)(line_width 1)) ) (port - (pt 256 80) + (pt 272 80) (output) - (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) - (text "c1" (rect 241 67 251 79)(font "Arial" (font_size 8))) + (text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8))) + (text "c1" (rect 257 67 268 80)(font "Arial" (font_size 8))) + (line (pt 272 80)(pt 224 80)(line_width 1)) ) (port - (pt 256 96) + (pt 272 96) (output) - (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c2" (rect 241 83 253 95)(font "Arial" (font_size 8))) + (text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8))) + (text "c2" (rect 257 83 268 96)(font "Arial" (font_size 8))) + (line (pt 272 96)(pt 224 96)(line_width 1)) ) (port - (pt 256 112) + (pt 272 112) (output) - (text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c3" (rect 241 99 253 111)(font "Arial" (font_size 8))) + (text "c3" (rect 0 0 14 14)(font "Arial" (font_size 8))) + (text "c3" (rect 257 99 268 112)(font "Arial" (font_size 8))) + (line (pt 272 112)(pt 224 112)(line_width 1)) + ) + (port + (pt 272 128) + (output) + (text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8))) + (text "locked" (rect 238 115 268 128)(font "Arial" (font_size 8))) + (line (pt 272 128)(pt 224 128)(line_width 1)) ) (drawing - (text "Cyclone III" (rect 198 170 442 350)(font "Arial" )) - (text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" )) - (text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" )) - (text "Clk " (rect 51 91 117 192)(font "Arial" )) - (text "Ratio" (rect 77 91 177 192)(font "Arial" )) - (text "Ph (dg)" (rect 109 91 249 192)(font "Arial" )) - (text "DC (%)" (rect 144 91 320 192)(font "Arial" )) - (text "c0" (rect 54 104 119 218)(font "Arial" )) - (text "2/33" (rect 79 104 177 218)(font "Arial" )) - (text "0.00" (rect 115 104 249 218)(font "Arial" )) - (text "50.00" (rect 148 104 320 218)(font "Arial" )) - (text "c1" (rect 54 117 118 244)(font "Arial" )) - (text "16/33" (rect 77 117 177 244)(font "Arial" )) - (text "0.00" (rect 115 117 249 244)(font "Arial" )) - (text "50.00" (rect 148 117 320 244)(font "Arial" )) - (text "c2" (rect 54 130 119 270)(font "Arial" )) - (text "227/300" (rect 71 130 176 270)(font "Arial" )) - (text "0.00" (rect 115 130 249 270)(font "Arial" )) - (text "50.00" (rect 148 130 320 270)(font "Arial" )) - (text "c3" (rect 54 143 119 296)(font "Arial" )) - (text "227/156" (rect 71 143 176 296)(font "Arial" )) - (text "0.00" (rect 115 143 249 296)(font "Arial" )) - (text "50.00" (rect 148 143 320 296)(font "Arial" )) - (line (pt 0 0)(pt 257 0)) - (line (pt 257 0)(pt 257 185)) - (line (pt 0 185)(pt 257 185)) - (line (pt 0 0)(pt 0 185)) - (line (pt 48 89)(pt 176 89)) - (line (pt 48 101)(pt 176 101)) - (line (pt 48 114)(pt 176 114)) - (line (pt 48 127)(pt 176 127)) - (line (pt 48 140)(pt 176 140)) - (line (pt 48 153)(pt 176 153)) - (line (pt 48 89)(pt 48 153)) - (line (pt 68 89)(pt 68 153)(line_width 3)) - (line (pt 106 89)(pt 106 153)(line_width 3)) - (line (pt 141 89)(pt 141 153)(line_width 3)) - (line (pt 175 89)(pt 175 153)) - (line (pt 40 48)(pt 223 48)) - (line (pt 223 48)(pt 223 167)) - (line (pt 40 167)(pt 223 167)) - (line (pt 40 48)(pt 40 167)) - (line (pt 255 64)(pt 223 64)) - (line (pt 255 80)(pt 223 80)) - (line (pt 255 96)(pt 223 96)) - (line (pt 255 112)(pt 223 112)) + (text "Cyclone III" (rect 211 185 258 197)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 50 59 175 71)(font "Arial" )) + (text "Operation Mode: Src Sync Comp" (rect 50 73 188 85)(font "Arial" )) + (text "Clk " (rect 51 96 68 108)(font "Arial" )) + (text "Ratio" (rect 81 96 103 108)(font "Arial" )) + (text "Ph (dg)" (rect 116 96 146 108)(font "Arial" )) + (text "DC (%)" (rect 151 96 182 108)(font "Arial" )) + (text "c0" (rect 54 111 64 123)(font "Arial" )) + (text "25/33" (rect 81 111 104 123)(font "Arial" )) + (text "0.00" (rect 122 111 140 123)(font "Arial" )) + (text "50.00" (rect 155 111 178 123)(font "Arial" )) + (text "c1" (rect 54 126 64 138)(font "Arial" )) + (text "2/33" (rect 83 126 101 138)(font "Arial" )) + (text "0.00" (rect 122 126 140 138)(font "Arial" )) + (text "50.00" (rect 155 126 178 138)(font "Arial" )) + (text "c2" (rect 54 141 64 153)(font "Arial" )) + (text "1/66" (rect 83 141 101 153)(font "Arial" )) + (text "0.00" (rect 122 141 140 153)(font "Arial" )) + (text "50.00" (rect 155 141 178 153)(font "Arial" )) + (text "c3" (rect 54 156 64 168)(font "Arial" )) + (text "512/6875" (rect 73 156 111 168)(font "Arial" )) + (text "0.00" (rect 122 156 140 168)(font "Arial" )) + (text "50.00" (rect 155 156 178 168)(font "Arial" )) + (line (pt 0 0)(pt 273 0)(line_width 1)) + (line (pt 273 0)(pt 273 201)(line_width 1)) + (line (pt 0 201)(pt 273 201)(line_width 1)) + (line (pt 0 0)(pt 0 201)(line_width 1)) + (line (pt 48 94)(pt 184 94)(line_width 1)) + (line (pt 48 108)(pt 184 108)(line_width 1)) + (line (pt 48 123)(pt 184 123)(line_width 1)) + (line (pt 48 138)(pt 184 138)(line_width 1)) + (line (pt 48 153)(pt 184 153)(line_width 1)) + (line (pt 48 168)(pt 184 168)(line_width 1)) + (line (pt 48 94)(pt 48 168)(line_width 1)) + (line (pt 70 94)(pt 70 168)(line_width 3)) + (line (pt 113 94)(pt 113 168)(line_width 3)) + (line (pt 148 94)(pt 148 168)(line_width 3)) + (line (pt 183 94)(pt 183 168)(line_width 1)) + (line (pt 40 48)(pt 224 48)(line_width 1)) + (line (pt 224 48)(pt 224 184)(line_width 1)) + (line (pt 40 184)(pt 224 184)(line_width 1)) + (line (pt 40 48)(pt 40 184)(line_width 1)) ) ) diff --git a/FPGA_Quartus_13.1/altpll3.cmp b/FPGA_Quartus_13.1/altpll3.cmp index 233616a..2007307 100644 --- a/FPGA_Quartus_13.1/altpll3.cmp +++ b/FPGA_Quartus_13.1/altpll3.cmp @@ -1,4 +1,4 @@ ---Copyright (C) 1991-2014 Altera Corporation +--Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing @@ -20,6 +20,7 @@ component altpll3 c0 : OUT STD_LOGIC ; c1 : OUT STD_LOGIC ; c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC + c3 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC ); end component; diff --git a/FPGA_Quartus_13.1/altpll3.inc b/FPGA_Quartus_13.1/altpll3.inc index 66f8ef8..9b8ca64 100644 --- a/FPGA_Quartus_13.1/altpll3.inc +++ b/FPGA_Quartus_13.1/altpll3.inc @@ -1,4 +1,4 @@ ---Copyright (C) 1991-2014 Altera Corporation +--Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing @@ -22,5 +22,6 @@ RETURNS ( c0, c1, c2, - c3 + c3, + locked ); diff --git a/FPGA_Quartus_13.1/altpll3.ppf b/FPGA_Quartus_13.1/altpll3.ppf index c840c97..a771350 100644 --- a/FPGA_Quartus_13.1/altpll3.ppf +++ b/FPGA_Quartus_13.1/altpll3.ppf @@ -7,6 +7,7 @@ + diff --git a/FPGA_Quartus_13.1/altpll3.qip b/FPGA_Quartus_13.1/altpll3.qip index 0b0f8f4..adefea9 100644 --- a/FPGA_Quartus_13.1/altpll3.qip +++ b/FPGA_Quartus_13.1/altpll3.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name IP_TOOL_VERSION "9.1" set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll3.vhd"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.bsf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.inc"] diff --git a/FPGA_Quartus_13.1/altpll3.vhd b/FPGA_Quartus_13.1/altpll3.vhd index be0649b..9176b7a 100644 --- a/FPGA_Quartus_13.1/altpll3.vhd +++ b/FPGA_Quartus_13.1/altpll3.vhd @@ -14,11 +14,11 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ ---Copyright (C) 1991-2014 Altera Corporation +--Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing @@ -46,7 +46,8 @@ ENTITY altpll3 IS c0 : OUT STD_LOGIC ; c1 : OUT STD_LOGIC ; c2 : OUT STD_LOGIC ; - c3 : OUT STD_LOGIC + c3 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC ); END altpll3; @@ -59,9 +60,10 @@ ARCHITECTURE SYN OF altpll3 IS SIGNAL sub_wire3 : STD_LOGIC ; SIGNAL sub_wire4 : STD_LOGIC ; SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC ; + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0); @@ -131,48 +133,51 @@ ARCHITECTURE SYN OF altpll3 IS port_extclk1 : STRING; port_extclk2 : STRING; port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; width_clock : NATURAL ); PORT ( - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0) + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) ); END COMPONENT; BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire4 <= sub_wire0(2); - sub_wire3 <= sub_wire0(0); - sub_wire2 <= sub_wire0(3); - sub_wire1 <= sub_wire0(1); - c1 <= sub_wire1; - c3 <= sub_wire2; - c0 <= sub_wire3; - c2 <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; + sub_wire8_bv(0 DOWNTO 0) <= "0"; + sub_wire8 <= To_stdlogicvector(sub_wire8_bv); + sub_wire4 <= sub_wire0(3); + sub_wire3 <= sub_wire0(2); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + c2 <= sub_wire3; + c3 <= sub_wire4; + locked <= sub_wire5; + sub_wire6 <= inclk0; + sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; altpll_component : altpll GENERIC MAP ( bandwidth_type => "AUTO", clk0_divide_by => 33, clk0_duty_cycle => 50, - clk0_multiply_by => 2, + clk0_multiply_by => 25, clk0_phase_shift => "0", clk1_divide_by => 33, clk1_duty_cycle => 50, - clk1_multiply_by => 16, + clk1_multiply_by => 2, clk1_phase_shift => "0", - clk2_divide_by => 300, + clk2_divide_by => 66, clk2_duty_cycle => 50, - clk2_multiply_by => 227, + clk2_multiply_by => 1, clk2_phase_shift => "0", - clk3_divide_by => 156, + clk3_divide_by => 6875, clk3_duty_cycle => 50, - clk3_multiply_by => 227, + clk3_multiply_by => 512, clk3_phase_shift => "0", - compensate_clock => "CLK1", + compensate_clock => "CLK0", inclk0_input_frequency => 30303, intended_device_family => "Cyclone III", lpm_type => "altpll", @@ -188,7 +193,7 @@ BEGIN port_fbin => "PORT_UNUSED", port_inclk0 => "PORT_USED", port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_UNUSED", + port_locked => "PORT_USED", port_pfdena => "PORT_UNUSED", port_phasecounterselect => "PORT_UNUSED", port_phasedone => "PORT_UNUSED", @@ -219,11 +224,13 @@ BEGIN port_extclk1 => "PORT_UNUSED", port_extclk2 => "PORT_UNUSED", port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", width_clock => 5 ) PORT MAP ( - inclk => sub_wire6, - clk => sub_wire0 + inclk => sub_wire7, + clk => sub_wire0, + locked => sub_wire5 ); @@ -246,21 +253,21 @@ END SYN; -- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" -- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" -- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "3744" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "300" --- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "156" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "72" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "906" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "3072" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "738" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.969999" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.019230" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "0.500000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "2.457600" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -276,9 +283,9 @@ END SYN; -- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" @@ -289,19 +296,19 @@ END SYN; -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" -- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "227" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "227" --- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "227" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "55" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "55" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "55" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "55" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "48.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "0.50000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "2.45760000" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" @@ -316,7 +323,7 @@ END SYN; -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ns" -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -359,21 +366,21 @@ END SYN; -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33" -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33" -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2" -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "300" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "66" -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "227" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1" -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "156" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "6875" -- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "227" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "512" -- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" @@ -389,7 +396,7 @@ END SYN; -- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" -- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" @@ -420,6 +427,7 @@ END SYN; -- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" -- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" -- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" @@ -428,18 +436,20 @@ END SYN; -- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" -- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 -- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.vhd FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_wave*.jpg FALSE -- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/altpll4.bsf b/FPGA_Quartus_13.1/altpll4.bsf index f74527e..e071d43 100644 --- a/FPGA_Quartus_13.1/altpll4.bsf +++ b/FPGA_Quartus_13.1/altpll4.bsf @@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in the Block Editor! File corruption is VERY likely to occur. */ /* -Copyright (C) 1991-2014 Altera Corporation +Copyright (C) 1991-2010 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing @@ -18,108 +18,108 @@ programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. */ -(header "symbol" (version "1.2")) +(header "symbol" (version "1.1")) (symbol - (rect 0 0 312 184) - (text "altpll4" (rect 139 0 179 16)(font "Arial" (font_size 10))) - (text "inst" (rect 8 168 25 180)(font "Arial" )) + (rect 0 0 376 232) + (text "altpll4" (rect 168 1 215 20)(font "Arial" (font_size 10))) + (text "inst" (rect 8 213 31 228)(font "Arial" )) (port - (pt 0 64) + (pt 0 72) (input) - (text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8))) - (line (pt 0 64)(pt 72 64)) - ) - (port - (pt 0 80) - (input) - (text "areset" (rect 0 0 36 14)(font "Arial" (font_size 8))) - (text "areset" (rect 4 66 33 79)(font "Arial" (font_size 8))) - (line (pt 0 80)(pt 72 80)) + (text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 88 72)(line_width 1)) ) (port (pt 0 96) (input) - (text "scanclk" (rect 0 0 43 14)(font "Arial" (font_size 8))) - (text "scanclk" (rect 4 82 39 95)(font "Arial" (font_size 8))) - (line (pt 0 96)(pt 72 96)) + (text "areset" (rect 0 0 42 16)(font "Arial" (font_size 8))) + (text "areset" (rect 4 80 40 96)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 88 96)(line_width 1)) ) (port - (pt 0 112) + (pt 0 120) (input) - (text "scandata" (rect 0 0 53 14)(font "Arial" (font_size 8))) - (text "scandata" (rect 4 98 47 111)(font "Arial" (font_size 8))) - (line (pt 0 112)(pt 72 112)) - ) - (port - (pt 0 128) - (input) - (text "scanclkena" (rect 0 0 64 14)(font "Arial" (font_size 8))) - (text "scanclkena" (rect 4 114 57 127)(font "Arial" (font_size 8))) - (line (pt 0 128)(pt 72 128)) + (text "scanclk" (rect 0 0 53 16)(font "Arial" (font_size 8))) + (text "scanclk" (rect 4 104 49 120)(font "Arial" (font_size 8))) + (line (pt 0 120)(pt 88 120)(line_width 1)) ) (port (pt 0 144) (input) - (text "configupdate" (rect 0 0 74 14)(font "Arial" (font_size 8))) - (text "configupdate" (rect 4 130 65 143)(font "Arial" (font_size 8))) - (line (pt 0 144)(pt 72 144)) + (text "scandata" (rect 0 0 62 16)(font "Arial" (font_size 8))) + (text "scandata" (rect 4 128 57 144)(font "Arial" (font_size 8))) + (line (pt 0 144)(pt 88 144)(line_width 1)) ) (port - (pt 312 64) - (output) - (text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8))) - (text "c0" (rect 296 50 306 63)(font "Arial" (font_size 8))) + (pt 0 168) + (input) + (text "scanclkena" (rect 0 0 77 16)(font "Arial" (font_size 8))) + (text "scanclkena" (rect 4 152 70 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 88 168)(line_width 1)) ) (port - (pt 312 80) - (output) - (text "scandataout" (rect 0 0 70 14)(font "Arial" (font_size 8))) - (text "scandataout" (rect 248 66 306 79)(font "Arial" (font_size 8))) + (pt 0 192) + (input) + (text "configupdate" (rect 0 0 86 16)(font "Arial" (font_size 8))) + (text "configupdate" (rect 4 176 77 192)(font "Arial" (font_size 8))) + (line (pt 0 192)(pt 88 192)(line_width 1)) ) (port - (pt 312 96) + (pt 376 72) (output) - (text "scandone" (rect 0 0 56 14)(font "Arial" (font_size 8))) - (text "scandone" (rect 260 82 306 95)(font "Arial" (font_size 8))) + (text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8))) + (text "c0" (rect 359 56 373 72)(font "Arial" (font_size 8))) + (line (pt 376 72)(pt 288 72)(line_width 1)) ) (port - (pt 312 112) + (pt 376 96) (output) - (text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8))) - (text "locked" (rect 277 98 306 111)(font "Arial" (font_size 8))) + (text "scandataout" (rect 0 0 83 16)(font "Arial" (font_size 8))) + (text "scandataout" (rect 302 80 373 96)(font "Arial" (font_size 8))) + (line (pt 376 96)(pt 288 96)(line_width 1)) + ) + (port + (pt 376 120) + (output) + (text "scandone" (rect 0 0 66 16)(font "Arial" (font_size 8))) + (text "scandone" (rect 317 104 373 120)(font "Arial" (font_size 8))) + (line (pt 376 120)(pt 288 120)(line_width 1)) + ) + (port + (pt 376 144) + (output) + (text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8))) + (text "locked" (rect 335 128 373 144)(font "Arial" (font_size 8))) + (line (pt 376 144)(pt 288 144)(line_width 1)) ) (drawing - (text "Cyclone III" (rect 250 169 545 349)(font "Arial" )) - (text "inclk0 frequency: 48.019 MHz" (rect 82 92 287 195)(font "Arial" )) - (text "Operation Mode: Normal" (rect 82 105 263 221)(font "Arial" )) - (text "Clk " (rect 83 126 180 263)(font "Arial" )) - (text "Ratio" (rect 104 126 228 263)(font "Arial" )) - (text "Ph (dg)" (rect 130 126 289 263)(font "Arial" )) - (text "DC (%)" (rect 164 126 358 263)(font "Arial" )) - (text "c0" (rect 86 140 180 291)(font "Arial" )) - (text "2/1" (rect 109 140 228 291)(font "Arial" )) - (text "0.00" (rect 136 140 288 291)(font "Arial" )) - (text "50.00" (rect 168 140 357 291)(font "Arial" )) - (line (pt 0 0)(pt 313 0)) - (line (pt 313 0)(pt 313 186)) - (line (pt 0 186)(pt 313 186)) - (line (pt 0 0)(pt 0 186)) - (line (pt 80 124)(pt 196 124)) - (line (pt 80 137)(pt 196 137)) - (line (pt 80 151)(pt 196 151)) - (line (pt 80 124)(pt 80 151)) - (line (pt 101 124)(pt 101 151)(line_width 3)) - (line (pt 127 124)(pt 127 151)(line_width 3)) - (line (pt 161 124)(pt 161 151)(line_width 3)) - (line (pt 195 124)(pt 195 151)) - (line (pt 72 48)(pt 239 48)) - (line (pt 239 48)(pt 239 168)) - (line (pt 72 168)(pt 239 168)) - (line (pt 72 48)(pt 72 168)) - (line (pt 311 64)(pt 239 64)) - (line (pt 311 80)(pt 239 80)) - (line (pt 311 96)(pt 239 96)) - (line (pt 311 112)(pt 239 112)) + (text "Cyclone III" (rect 301 214 349 228)(font "Arial" )) + (text "inclk0 frequency: 48.000 MHz" (rect 98 123 241 137)(font "Arial" )) + (text "Operation Mode: Normal" (rect 98 140 213 154)(font "Arial" )) + (text "Clk " (rect 99 167 116 181)(font "Arial" )) + (text "Ratio" (rect 125 167 149 181)(font "Arial" )) + (text "Ph (dg)" (rect 159 167 194 181)(font "Arial" )) + (text "DC (%)" (rect 204 167 239 181)(font "Arial" )) + (text "c0" (rect 103 185 115 199)(font "Arial" )) + (text "2/1" (rect 131 185 146 199)(font "Arial" )) + (text "0.00" (rect 167 185 188 199)(font "Arial" )) + (text "50.00" (rect 209 185 236 199)(font "Arial" )) + (line (pt 0 0)(pt 377 0)(line_width 1)) + (line (pt 377 0)(pt 377 233)(line_width 1)) + (line (pt 0 233)(pt 377 233)(line_width 1)) + (line (pt 0 0)(pt 0 233)(line_width 1)) + (line (pt 96 164)(pt 246 164)(line_width 1)) + (line (pt 96 181)(pt 246 181)(line_width 1)) + (line (pt 96 199)(pt 246 199)(line_width 1)) + (line (pt 96 164)(pt 96 199)(line_width 1)) + (line (pt 122 164)(pt 122 199)(line_width 3)) + (line (pt 156 164)(pt 156 199)(line_width 3)) + (line (pt 201 164)(pt 201 199)(line_width 3)) + (line (pt 245 164)(pt 245 199)(line_width 1)) + (line (pt 88 56)(pt 288 56)(line_width 1)) + (line (pt 288 56)(pt 288 216)(line_width 1)) + (line (pt 88 216)(pt 288 216)(line_width 1)) + (line (pt 88 56)(pt 88 216)(line_width 1)) ) ) diff --git a/FPGA_Quartus_13.1/altpll4.cmp b/FPGA_Quartus_13.1/altpll4.cmp index ac5def2..83b3c1e 100644 --- a/FPGA_Quartus_13.1/altpll4.cmp +++ b/FPGA_Quartus_13.1/altpll4.cmp @@ -1,4 +1,4 @@ ---Copyright (C) 1991-2014 Altera Corporation +--Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/FPGA_Quartus_13.1/altpll4.inc b/FPGA_Quartus_13.1/altpll4.inc index c622d5e..39f54c9 100644 --- a/FPGA_Quartus_13.1/altpll4.inc +++ b/FPGA_Quartus_13.1/altpll4.inc @@ -1,4 +1,4 @@ ---Copyright (C) 1991-2014 Altera Corporation +--Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing diff --git a/FPGA_Quartus_13.1/altpll4.mif b/FPGA_Quartus_13.1/altpll4.mif index b526227..e50eda2 100644 --- a/FPGA_Quartus_13.1/altpll4.mif +++ b/FPGA_Quartus_13.1/altpll4.mif @@ -1,4 +1,4 @@ --- Copyright (C) 1991-2014 Altera Corporation +-- Copyright (C) 1991-2010 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing @@ -17,8 +17,8 @@ -- Device Part: - -- Device Speed Grade: 8 -- PLL Scan Chain: Fast PLL (144 bits) --- File Name: C:/Users/froesm1/Documents/Development/FPGA_quartus//altpll4.mif --- Generated: Mon Sep 21 17:50:54 2015 +-- File Name: C:\FireBee\FPGA\altpll4.mif +-- Generated: Mon Dec 06 01:47:24 2010 WIDTH=1; DEPTH=144; diff --git a/FPGA_Quartus_13.1/altpll4.qip b/FPGA_Quartus_13.1/altpll4.qip index ded02bb..f44acdc 100644 --- a/FPGA_Quartus_13.1/altpll4.qip +++ b/FPGA_Quartus_13.1/altpll4.qip @@ -1,5 +1,5 @@ set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name IP_TOOL_VERSION "9.1" set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"] diff --git a/FPGA_Quartus_13.1/altpll4.tdf b/FPGA_Quartus_13.1/altpll4.tdf index 8e72bcc..3ec77d4 100644 --- a/FPGA_Quartus_13.1/altpll4.tdf +++ b/FPGA_Quartus_13.1/altpll4.tdf @@ -14,11 +14,11 @@ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- --- 13.1.4 Build 182 03/12/2014 SJ Web Edition +-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ ---Copyright (C) 1991-2014 Altera Corporation +--Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing @@ -59,7 +59,7 @@ VARIABLE CLK0_MULTIPLY_BY = 2, CLK0_PHASE_SHIFT = "0", COMPENSATE_CLOCK = "CLK0", - INCLK0_INPUT_FREQUENCY = 20824, + INCLK0_INPUT_FREQUENCY = 20833, INTENDED_DEVICE_FAMILY = "Cyclone III", LPM_TYPE = "altpll", OPERATION_MODE = "NORMAL", @@ -113,16 +113,16 @@ VARIABLE BEGIN c0 = altpll_component.clk[0..0]; - scandataout = altpll_component.scandataout; scandone = altpll_component.scandone; + scandataout = altpll_component.scandataout; locked = altpll_component.locked; - altpll_component.areset = areset; - altpll_component.configupdate = configupdate; + altpll_component.scanclkena = scanclkena; altpll_component.inclk[0..0] = inclk0; altpll_component.inclk[1..1] = GND; - altpll_component.scanclk = scanclk; - altpll_component.scanclkena = scanclkena; altpll_component.scandata = scandata; + altpll_component.areset = areset; + altpll_component.scanclk = scanclk; + altpll_component.configupdate = configupdate; END; @@ -148,7 +148,7 @@ END; -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.038460" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -156,7 +156,7 @@ END; -- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" -- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.019" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000" -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" @@ -166,7 +166,7 @@ END; -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "336.000" -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" @@ -217,7 +217,7 @@ END; -- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20824" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" @@ -277,22 +277,22 @@ END; -- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata" -- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout" -- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0 --- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0 --- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 --- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0 -- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0 +-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0 +-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0 +-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0 +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE -- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_Quartus_13.1/firebee1.bdf b/FPGA_Quartus_13.1/firebee1.bdf index abc22f8..4f32a08 100644 --- a/FPGA_Quartus_13.1/firebee1.bdf +++ b/FPGA_Quartus_13.1/firebee1.bdf @@ -25,660 +25,643 @@ applicable agreement for further details. ) (pin (input) - (rect 208 1392 384 1408) + (rect 208 1392 376 1408) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "FB_ALE" (rect 9 0 51 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 152 1408 208 1424)) + (annotation_block (location)(rect 160 1408 208 1424)) ) (pin (input) - (rect 992 936 1168 952) + (rect 992 936 1160 952) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nFB_WR" (rect 9 0 55 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 936 952 992 968)) + (annotation_block (location)(rect 944 952 992 968)) ) (pin (input) - (rect 992 960 1168 976) + (rect 992 960 1160 976) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nFB_CS1" (rect 9 0 57 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 936 976 992 992)) + (annotation_block (location)(rect 944 976 992 992)) ) (pin (input) - (rect 992 984 1168 1000) + (rect 992 984 1160 1000) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nFB_CS2" (rect 9 0 58 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 936 1000 992 1016)) + (annotation_block (location)(rect 944 1000 992 1016)) ) (pin (input) - (rect 1008 360 1184 376) + (rect 1008 360 1176 376) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nFB_CS3" (rect 9 0 58 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 952 376 1008 392)) + (annotation_block (location)(rect 960 376 1008 392)) ) (pin (input) - (rect 992 1008 1168 1024) + (rect 992 1008 1160 1024) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "FB_SIZE0" (rect 9 0 60 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 936 1024 992 1040)) + (annotation_block (location)(rect 944 1024 992 1040)) ) (pin (input) - (rect 992 1032 1168 1048) + (rect 992 1032 1160 1048) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "FB_SIZE1" (rect 9 0 59 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 936 1048 992 1064)) + (annotation_block (location)(rect 944 1048 992 1064)) ) (pin (input) - (rect 992 1056 1168 1072) + (rect 992 1056 1160 1072) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nFB_BURST" (rect 9 0 73 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 936 1072 992 1088)) + (annotation_block (location)(rect 944 1072 992 1088)) ) (pin (input) - (rect 936 1168 1112 1184) + (rect 936 1168 1104 1184) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "LP_BUSY" (rect 9 0 60 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 880 1184 936 1200)) + (annotation_block (location)(rect 888 1184 936 1200)) ) (pin (input) - (rect 856 1200 1032 1216) + (rect 856 1200 1024 1216) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nACSI_DRQ" (rect 9 0 72 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 800 1216 856 1232)) + (annotation_block (location)(rect 808 1216 856 1232)) ) (pin (input) - (rect 856 1224 1032 1240) + (rect 856 1224 1024 1240) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nACSI_INT" (rect 9 0 66 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 800 1240 856 1256)) + (annotation_block (location)(rect 808 1240 856 1256)) ) (pin (input) - (rect 936 1392 1112 1408) + (rect 936 1392 1104 1408) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "RxD" (rect 9 0 32 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 872 1408 936 1424)) + (annotation_block (location)(rect 880 1408 936 1424)) ) (pin (input) - (rect 936 1416 1112 1432) + (rect 936 1416 1104 1432) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "CTS" (rect 9 0 32 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 872 1432 936 1448)) + (annotation_block (location)(rect 880 1432 936 1448)) ) (pin (input) - (rect 936 1440 1112 1456) + (rect 936 1440 1104 1456) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "RI" (rect 9 0 20 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 872 1456 936 1472)) + (annotation_block (location)(rect 880 1456 936 1472)) ) (pin (input) - (rect 936 1464 1112 1480) + (rect 936 1464 1104 1480) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "DCD" (rect 9 0 34 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 872 1480 936 1496)) + (annotation_block (location)(rect 880 1480 936 1496)) ) (pin (input) - (rect 608 1488 784 1504) + (rect 608 1488 776 1504) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "AMKB_RX" (rect 9 0 64 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 552 1504 608 1520)) + (annotation_block (location)(rect 560 1504 648 1536)) ) (pin (input) - (rect 608 1512 784 1528) + (rect 608 1512 776 1528) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "PIC_AMKB_RX" (rect 9 0 89 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 552 1528 608 1544)) + (annotation_block (location)(rect 560 1528 608 1544)) ) (pin (input) - (rect 936 1544 1112 1560) + (rect 936 1544 1104 1560) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "IDE_RDY" (rect 9 0 59 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 880 1560 936 1576)) + (annotation_block (location)(rect 888 1560 936 1576)) ) (pin (input) - (rect 936 1568 1112 1584) + (rect 936 1568 1104 1584) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "IDE_INT" (rect 9 0 52 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 872 1584 936 1600)) + (annotation_block (location)(rect 880 1584 936 1600)) ) (pin (input) - (rect 936 1592 1112 1608) + (rect 936 1592 1104 1608) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "WP_CF_CARD" (rect 9 0 86 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 880 1608 936 1624)) + (annotation_block (location)(rect 888 1608 936 1624)) ) (pin (input) - (rect 872 1672 1048 1688) + (rect 872 1672 1040 1688) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "TRACK00" (rect 9 0 59 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 808 1688 872 1704)) + (annotation_block (location)(rect 816 1688 872 1704)) ) (pin (input) - (rect 872 1696 1048 1712) + (rect 872 1696 1040 1712) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nWP" (rect 9 0 34 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 808 1712 872 1728)) + (annotation_block (location)(rect 816 1712 872 1728)) ) (pin (input) - (rect 872 1744 1048 1760) + (rect 872 1744 1040 1760) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nDCHG" (rect 9 0 49 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 808 1760 872 1776)) + (annotation_block (location)(rect 816 1760 872 1776)) ) (pin (input) - (rect 936 1776 1112 1792) + (rect 936 1776 1104 1792) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "SD_DATA0" (rect 9 0 68 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 872 1792 936 1808)) + (annotation_block (location)(rect 880 1792 936 1808)) ) (pin (input) - (rect 936 1800 1112 1816) + (rect 936 1800 1104 1816) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "SD_DATA1" (rect 9 0 66 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 872 1816 936 1832)) + (annotation_block (location)(rect 880 1816 936 1832)) ) (pin (input) - (rect 936 1824 1112 1840) + (rect 936 1824 1104 1840) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "SD_DATA2" (rect 9 0 68 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 872 1840 936 1856)) + (annotation_block (location)(rect 880 1840 936 1856)) ) (pin (input) - (rect 936 1848 1112 1864) + (rect 936 1848 1104 1864) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "SD_CARD_DEDECT" (rect 9 0 115 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 872 1864 936 1880)) + (annotation_block (location)(rect 880 1864 936 1880)) ) (pin (input) - (rect 872 1360 1048 1376) - (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) - (text "MIDI_IN" (rect 9 0 50 11)(font "Arial" )) - (pt 176 8) - (drawing - (line (pt 92 12)(pt 117 12)) - (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) - (line (pt 92 12)(pt 92 4)) - (line (pt 117 4)(pt 121 8)) - (line (pt 117 12)(pt 121 8)) - ) - (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 808 1376 872 1392)) -) -(pin - (input) - (rect 936 1256 1112 1272) + (rect 936 1256 1104 1272) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nSCSI_DRQ" (rect 9 0 72 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 880 1272 936 1288)) + (annotation_block (location)(rect 888 1272 936 1288)) ) (pin (input) - (rect 936 1872 1112 1888) + (rect 936 1872 1104 1888) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "SD_WP" (rect 9 0 50 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 872 1888 936 1904)) + (annotation_block (location)(rect 880 1888 936 1904)) ) (pin (input) - (rect 872 1720 1048 1736) + (rect 872 1720 1040 1736) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nRD_DATA" (rect 9 0 69 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 808 1736 872 1752)) + (annotation_block (location)(rect 816 1736 872 1752)) ) (pin (input) - (rect 936 1280 1112 1296) + (rect 936 1280 1104 1296) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nSCSI_C_D" (rect 9 0 70 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 880 1296 936 1312)) + (annotation_block (location)(rect 888 1296 936 1312)) ) (pin (input) - (rect 936 1304 1112 1320) + (rect 936 1304 1104 1320) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nSCSI_I_O" (rect 9 0 66 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 880 1320 936 1336)) + (annotation_block (location)(rect 888 1320 936 1336)) ) (pin (input) - (rect 936 1328 1112 1344) + (rect 936 1328 1104 1344) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nSCSI_MSG" (rect 9 0 73 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 880 1344 936 1360)) + (annotation_block (location)(rect 888 1344 936 1360)) ) (pin (input) - (rect 992 1104 1168 1120) + (rect 992 1104 1160 1120) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nDACK0" (rect 9 0 53 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 928 1120 992 1136)) + (annotation_block (location)(rect 936 1120 992 1136)) ) (pin (input) - (rect 984 2592 1160 2608) + (rect 984 2592 1152 2608) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "PIC_INT" (rect 9 0 52 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 920 2608 984 2624)) + (annotation_block (location)(rect 928 2608 984 2624)) ) (pin (input) - (rect 992 912 1168 928) + (rect 992 912 1160 928) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nFB_OE" (rect 9 0 52 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 936 928 992 944)) + (annotation_block (location)(rect 944 928 992 944)) ) (pin (input) - (rect 360 2616 536 2632) + (rect 360 2616 528 2632) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "TOUT0" (rect 9 0 46 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 296 2632 360 2648)) + (annotation_block (location)(rect 304 2632 360 2648)) ) (pin (input) - (rect 360 2504 536 2520) + (rect 360 2504 528 2520) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nMASTER" (rect 9 0 63 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) @@ -688,207 +671,207 @@ applicable agreement for further details. ) (pin (input) - (rect 984 2640 1160 2656) + (rect 680 2640 848 2656) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "DVI_INT" (rect 9 0 52 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 920 2656 984 2672)) + (annotation_block (location)(rect 624 2656 680 2672)) ) (pin (input) - (rect 360 2408 536 2424) + (rect 360 2408 528 2424) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nDACK1" (rect 9 0 52 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 296 2424 360 2440)) + (annotation_block (location)(rect 304 2424 360 2440)) ) (pin (input) - (rect 984 2664 1160 2680) + (rect 984 2664 1152 2680) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nPCI_INTD" (rect 9 0 66 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 928 2680 984 2696)) + (annotation_block (location)(rect 936 2680 984 2696)) ) (pin (input) - (rect 984 2688 1160 2704) + (rect 984 2688 1152 2704) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nPCI_INTC" (rect 9 0 66 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 928 2704 984 2720)) + (annotation_block (location)(rect 936 2704 984 2720)) ) (pin (input) - (rect 984 2712 1160 2728) + (rect 984 2712 1152 2728) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nPCI_INTB" (rect 9 0 66 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 928 2728 984 2744)) + (annotation_block (location)(rect 936 2728 984 2744)) ) (pin (input) - (rect 984 2736 1160 2752) + (rect 984 2736 1152 2752) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nPCI_INTA" (rect 9 0 68 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 920 2752 984 2768)) + (annotation_block (location)(rect 928 2752 984 2768)) ) (pin (input) - (rect 984 2616 1160 2632) + (rect 984 2616 1152 2632) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "E0_INT" (rect 9 0 47 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 920 2632 984 2648)) + (annotation_block (location)(rect 928 2632 984 2648)) ) (pin (input) - (rect 872 1648 1048 1664) + (rect 872 1648 1040 1664) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "nINDEX" (rect 9 0 51 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 808 1664 872 1680)) + (annotation_block (location)(rect 816 1664 872 1680)) ) (pin (input) - (rect 872 1624 1048 1640) + (rect 872 1624 1040 1640) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "HD_DD" (rect 9 0 49 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 808 1640 872 1656)) + (annotation_block (location)(rect 816 1640 872 1656)) ) (pin (input) - (rect 664 440 840 456) - (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) - (text "nRSTO_MCF" (rect 9 0 77 11)(font "Arial" )) - (pt 176 8) - (drawing - (line (pt 92 12)(pt 117 12)) - (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) - (line (pt 92 12)(pt 92 4)) - (line (pt 117 4)(pt 121 8)) - (line (pt 117 12)(pt 121 8)) - ) - (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 600 456 664 472)) -) -(pin - (input) - (rect 168 296 344 312) + (rect 96 -288 264 -272) (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) (text "MAIN_CLK" (rect 9 0 66 11)(font "Arial" )) - (pt 176 8) + (pt 168 8) (drawing (line (pt 92 12)(pt 117 12)) (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) + (line (pt 121 8)(pt 168 8)) (line (pt 92 12)(pt 92 4)) (line (pt 117 4)(pt 121 8)) (line (pt 117 12)(pt 121 8)) ) (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 112 312 168 328)) + (annotation_block (location)(rect 48 -272 96 -256)) ) (pin - (output) - (rect 864 288 1040 304) - (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) - (text "CLK24M576" (rect 90 0 152 11)(font "Arial" )) - (pt 0 8) + (input) + (rect 592 440 760 456) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "nRSTO_MCF" (rect 9 0 77 11)(font "Arial" )) + (pt 168 8) (drawing - (line (pt 0 8)(pt 52 8)) - (line (pt 52 4)(pt 78 4)) - (line (pt 52 12)(pt 78 12)) - (line (pt 52 12)(pt 52 4)) - (line (pt 78 4)(pt 82 8)) - (line (pt 82 8)(pt 78 12)) - (line (pt 78 12)(pt 82 8)) + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 168 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) ) - (annotation_block (location)(rect 1040 304 1112 320)) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 536 456 592 472)) +) +(pin + (input) + (rect 56 304 224 320) + (text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6))) + (text "CLK33MDIR" (rect 9 0 72 11)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 92 12)(pt 117 12)) + (line (pt 92 4)(pt 117 4)) + (line (pt 121 8)(pt 168 8)) + (line (pt 92 12)(pt 92 4)) + (line (pt 117 4)(pt 121 8)) + (line (pt 117 12)(pt 121 8)) + ) + (text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect -8 320 56 336)) ) (pin (output) @@ -905,7 +888,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 848 2064 864)) + (annotation_block (location)(rect 2008 848 2096 880)) ) (pin (output) @@ -922,7 +905,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 952 2064 968)) + (annotation_block (location)(rect 2008 952 2056 968)) ) (pin (output) @@ -939,7 +922,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 976 2064 992)) + (annotation_block (location)(rect 2008 976 2056 992)) ) (pin (output) @@ -956,7 +939,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 1000 2064 1016)) + (annotation_block (location)(rect 2008 1000 2056 1016)) ) (pin (output) @@ -973,7 +956,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 1024 2064 1040)) + (annotation_block (location)(rect 2008 1024 2056 1040)) ) (pin (output) @@ -990,7 +973,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 1048 2064 1064)) + (annotation_block (location)(rect 2008 1048 2056 1064)) ) (pin (output) @@ -1007,7 +990,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2016 1128 2072 1144)) + (annotation_block (location)(rect 2016 1128 2064 1144)) ) (pin (output) @@ -1024,7 +1007,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2016 1152 2072 1168)) + (annotation_block (location)(rect 2016 1152 2064 1168)) ) (pin (output) @@ -1041,28 +1024,11 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2016 1176 2072 1192)) + (annotation_block (location)(rect 2016 1176 2064 1192)) ) (pin (output) - (rect 1920 1264 2096 1280) - (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) - (text "MIDI_OLR" (rect 90 0 144 11)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)) - (line (pt 52 4)(pt 78 4)) - (line (pt 52 12)(pt 78 12)) - (line (pt 52 12)(pt 52 4)) - (line (pt 78 4)(pt 82 8)) - (line (pt 82 8)(pt 78 12)) - (line (pt 78 12)(pt 82 8)) - ) - (annotation_block (location)(rect 2096 1280 2152 1296)) -) -(pin - (output) - (rect 1920 1288 2096 1304) + (rect 1832 2240 2008 2256) (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) (text "MIDI_TLR" (rect 90 0 141 11)(font "Arial" )) (pt 0 8) @@ -1075,7 +1041,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2096 1304 2152 1320)) + (annotation_block (location)(rect 2008 2256 2056 2272)) ) (pin (output) @@ -1092,7 +1058,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2016 1336 2080 1352)) + (annotation_block (location)(rect 2016 1336 2072 1352)) ) (pin (output) @@ -1109,7 +1075,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2016 1360 2080 1376)) + (annotation_block (location)(rect 2016 1360 2072 1376)) ) (pin (output) @@ -1126,7 +1092,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2024 1384 2088 1400)) + (annotation_block (location)(rect 2024 1384 2080 1400)) ) (pin (output) @@ -1143,7 +1109,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2288 1416 2344 1432)) + (annotation_block (location)(rect 2288 1416 2376 1448)) ) (pin (output) @@ -1160,7 +1126,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2024 1448 2080 1464)) + (annotation_block (location)(rect 2024 1448 2072 1464)) ) (pin (output) @@ -1177,7 +1143,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2024 1472 2080 1488)) + (annotation_block (location)(rect 2024 1472 2072 1488)) ) (pin (output) @@ -1194,7 +1160,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2032 1496 2088 1512)) + (annotation_block (location)(rect 2032 1496 2080 1512)) ) (pin (output) @@ -1211,7 +1177,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2024 1520 2080 1536)) + (annotation_block (location)(rect 2024 1520 2072 1536)) ) (pin (output) @@ -1228,7 +1194,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2024 1544 2080 1560)) + (annotation_block (location)(rect 2024 1544 2072 1560)) ) (pin (output) @@ -1279,7 +1245,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2096 1624 2152 1640)) + (annotation_block (location)(rect 2096 1624 2144 1640)) ) (pin (output) @@ -1296,7 +1262,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2096 1648 2152 1664)) + (annotation_block (location)(rect 2096 1648 2144 1664)) ) (pin (output) @@ -1313,7 +1279,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2096 1672 2152 1688)) + (annotation_block (location)(rect 2096 1672 2144 1688)) ) (pin (output) @@ -1330,7 +1296,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2096 1696 2152 1712)) + (annotation_block (location)(rect 2096 1696 2144 1712)) ) (pin (output) @@ -1347,7 +1313,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2032 1872 2096 1888)) + (annotation_block (location)(rect 2032 1872 2088 1888)) ) (pin (output) @@ -1364,7 +1330,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2312 1848 2376 1864)) + (annotation_block (location)(rect 2312 1848 2368 1864)) ) (pin (output) @@ -1381,7 +1347,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2312 1824 2376 1840)) + (annotation_block (location)(rect 2312 1824 2368 1840)) ) (pin (output) @@ -1398,7 +1364,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2104 1928 2168 1944)) + (annotation_block (location)(rect 2104 1928 2160 1944)) ) (pin (output) @@ -1415,7 +1381,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2104 1952 2168 1968)) + (annotation_block (location)(rect 2104 1952 2160 1968)) ) (pin (output) @@ -1432,7 +1398,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2104 1976 2168 1992)) + (annotation_block (location)(rect 2104 1976 2160 1992)) ) (pin (output) @@ -1449,7 +1415,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2032 2056 2096 2072)) + (annotation_block (location)(rect 2032 2056 2088 2072)) ) (pin (output) @@ -1466,7 +1432,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2032 1728 2096 1744)) + (annotation_block (location)(rect 2032 1728 2088 1744)) ) (pin (output) @@ -1483,7 +1449,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2256 88 2312 104)) + (annotation_block (location)(rect 2280 24 2360 152)) ) (pin (output) @@ -1500,7 +1466,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2176 112 2240 128)) + (annotation_block (location)(rect 2192 112 2272 240)) ) (pin (output) @@ -1517,7 +1483,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2088 136 2152 152)) + (annotation_block (location)(rect 2104 144 2184 272)) ) (pin (output) @@ -1534,7 +1500,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2704 336 2768 352)) + (annotation_block (location)(rect 2736 344 2800 544)) ) (pin (output) @@ -1551,7 +1517,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2576 360 2640 376)) + (annotation_block (location)(rect 2576 360 2632 392)) ) (pin (output) @@ -1568,7 +1534,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2480 384 2552 400)) + (annotation_block (location)(rect 2480 384 2544 416)) ) (pin (output) @@ -1585,7 +1551,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2384 408 2448 424)) + (annotation_block (location)(rect 2384 408 2440 440)) ) (pin (output) @@ -1602,7 +1568,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2216 432 2280 448)) + (annotation_block (location)(rect 2216 432 2272 464)) ) (pin (output) @@ -1619,7 +1585,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2120 576 2192 592)) + (annotation_block (location)(rect 2144 592 2208 664)) ) (pin (output) @@ -1636,7 +1602,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 280 2064 296)) + (annotation_block (location)(rect 2008 280 2056 296)) ) (pin (output) @@ -1653,24 +1619,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 2432 2064 2448)) -) -(pin - (output) - (rect 776 0 952 16) - (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) - (text "CLK25M" (rect 90 0 134 11)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)) - (line (pt 52 4)(pt 78 4)) - (line (pt 52 12)(pt 78 12)) - (line (pt 52 12)(pt 52 4)) - (line (pt 78 4)(pt 82 8)) - (line (pt 82 8)(pt 78 12)) - (line (pt 78 12)(pt 82 8)) - ) - (annotation_block (location)(rect 952 16 1008 32)) + (annotation_block (location)(rect 2008 2432 2096 2560)) ) (pin (output) @@ -1687,7 +1636,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 2648 2064 2664)) + (annotation_block (location)(rect 2008 2648 2056 2664)) ) (pin (output) @@ -1704,7 +1653,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2000 3296 2056 3312)) + (annotation_block (location)(rect 2000 3296 2088 3328)) ) (pin (output) @@ -1721,7 +1670,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2000 3320 2056 3336)) + (annotation_block (location)(rect 2000 3320 2088 3352)) ) (pin (output) @@ -1738,7 +1687,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2000 3344 2056 3360)) + (annotation_block (location)(rect 2000 3344 2088 3376)) ) (pin (output) @@ -1755,7 +1704,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2000 3368 2056 3384)) + (annotation_block (location)(rect 2000 3368 2088 3400)) ) (pin (output) @@ -1789,7 +1738,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 784 2144 848 2160)) + (annotation_block (location)(rect 784 2144 840 2176)) ) (pin (output) @@ -1823,7 +1772,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2120 456 2184 472)) + (annotation_block (location)(rect 2120 456 2176 488)) ) (pin (output) @@ -1840,7 +1789,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2232 744 2288 760)) + (annotation_block (location)(rect 2232 744 2280 760)) ) (pin (output) @@ -1857,7 +1806,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2888 896 2960 912)) + (annotation_block (location)(rect 2888 896 2952 928)) ) (pin (output) @@ -1874,7 +1823,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2712 768 2784 784)) + (annotation_block (location)(rect 2712 768 2776 800)) ) (pin (output) @@ -1891,7 +1840,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 480 2072 496)) + (annotation_block (location)(rect 2008 480 2072 528)) ) (pin (output) @@ -1908,7 +1857,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2312 -56 2376 -40)) + (annotation_block (location)(rect 2232 -32 2312 0)) ) (pin (output) @@ -1925,7 +1874,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2888 -72 2952 -56)) + (annotation_block (location)(rect 2888 -72 2968 -40)) ) (pin (output) @@ -1942,7 +1891,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2888 48 2952 64)) + (annotation_block (location)(rect 2888 48 2968 80)) ) (pin (output) @@ -1959,7 +1908,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2888 176 2952 192)) + (annotation_block (location)(rect 2888 176 2968 208)) ) (pin (output) @@ -1976,7 +1925,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 232 2072 248)) + (annotation_block (location)(rect 2008 232 2096 264)) ) (pin (output) @@ -1993,7 +1942,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2312 1752 2376 1768)) + (annotation_block (location)(rect 2312 1752 2368 1768)) ) (pin (output) @@ -2010,7 +1959,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2312 1776 2376 1792)) + (annotation_block (location)(rect 2312 1776 2368 1792)) ) (pin (output) @@ -2027,24 +1976,7 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2312 1800 2376 1816)) -) -(pin - (output) - (rect 840 48 1016 64) - (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) - (text "CLKUSB" (rect 90 0 136 11)(font "Arial" )) - (pt 0 8) - (drawing - (line (pt 0 8)(pt 52 8)) - (line (pt 52 4)(pt 78 4)) - (line (pt 52 12)(pt 78 12)) - (line (pt 52 12)(pt 52 4)) - (line (pt 78 4)(pt 82 8)) - (line (pt 82 8)(pt 78 12)) - (line (pt 78 12)(pt 82 8)) - ) - (annotation_block (location)(rect 1016 64 1072 80)) + (annotation_block (location)(rect 2312 1800 2368 1816)) ) (pin (output) @@ -2061,7 +1993,75 @@ applicable agreement for further details. (line (pt 82 8)(pt 78 12)) (line (pt 78 12)(pt 82 8)) ) - (annotation_block (location)(rect 2008 872 2064 888)) + (annotation_block (location)(rect 2008 872 2096 904)) +) +(pin + (output) + (rect 1920 2280 2096 2296) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "MIDI_OLR" (rect 90 0 144 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 2096 2296 2144 2312)) +) +(pin + (output) + (rect 920 -24 1096 -8) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "CLK25M" (rect 90 0 134 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 1096 -24 1144 -8)) +) +(pin + (output) + (rect 808 240 984 256) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "CLKUSB" (rect 90 0 136 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 984 240 1032 256)) +) +(pin + (output) + (rect 816 272 992 288) + (text "OUTPUT" (rect 1 0 41 10)(font "Arial" (font_size 6))) + (text "CLK24M576" (rect 90 0 152 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) + (annotation_block (location)(rect 992 272 1056 288)) ) (pin (bidir) @@ -2079,7 +2079,7 @@ applicable agreement for further details. (line (pt 52 8)(pt 56 12)) ) (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2016 1104 2072 1120)) + (annotation_block (location)(rect 2016 1104 2064 1120)) ) (pin (bidir) @@ -2097,7 +2097,7 @@ applicable agreement for further details. (line (pt 52 8)(pt 56 12)) ) (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2016 1200 2072 1216)) + (annotation_block (location)(rect 2016 1200 2064 1216)) ) (pin (bidir) @@ -2115,7 +2115,7 @@ applicable agreement for further details. (line (pt 52 8)(pt 56 12)) ) (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2016 1224 2072 1240)) + (annotation_block (location)(rect 2016 1224 2064 1240)) ) (pin (bidir) @@ -2133,7 +2133,7 @@ applicable agreement for further details. (line (pt 52 8)(pt 56 12)) ) (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2016 1248 2072 1264)) + (annotation_block (location)(rect 2016 1248 2064 1264)) ) (pin (bidir) @@ -2151,7 +2151,7 @@ applicable agreement for further details. (line (pt 52 8)(pt 56 12)) ) (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2032 2008 2096 2024)) + (annotation_block (location)(rect 2032 2008 2088 2024)) ) (pin (bidir) @@ -2169,7 +2169,7 @@ applicable agreement for further details. (line (pt 52 8)(pt 56 12)) ) (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2032 2032 2096 2048)) + (annotation_block (location)(rect 2032 2032 2088 2048)) ) (pin (bidir) @@ -2187,7 +2187,7 @@ applicable agreement for further details. (line (pt 52 8)(pt 56 12)) ) (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2112 1080 2168 1096)) + (annotation_block (location)(rect 2112 1080 2160 1192)) ) (pin (bidir) @@ -2205,7 +2205,7 @@ applicable agreement for further details. (line (pt 52 8)(pt 56 12)) ) (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2080 904 2136 920)) + (annotation_block (location)(rect 2080 904 2128 1016)) ) (pin (bidir) @@ -2223,13 +2223,13 @@ applicable agreement for further details. (line (pt 52 8)(pt 56 12)) ) (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2136 824 2192 840)) + (annotation_block (location)(rect 2136 824 2224 952)) ) (pin (bidir) (rect 176 1360 352 1376) - (text "BIDIR" (rect 148 0 175 10)(font "Arial" (font_size 6))) - (text "FB_AD[31..0]" (rect 20 0 86 11)(font "Arial" )) + (text "BIDIR" (rect 151 0 178 10)(font "Arial" (font_size 6))) + (text "FB_AD[31..0]" (rect 19 0 85 11)(font "Arial" )) (pt 176 8) (drawing (line (pt 120 4)(pt 98 4)) @@ -2241,8 +2241,8 @@ applicable agreement for further details. (line (pt 124 8)(pt 120 12)) ) (flipy) - (text "VCC" (rect 151 7 172 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 352 1376 408 1392)) + (text "VCC" (rect 152 7 173 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 24 1288 88 1736)) ) (pin (bidir) @@ -2260,7 +2260,7 @@ applicable agreement for further details. (line (pt 52 8)(pt 56 12)) ) (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2280 3248 2336 3264)) + (annotation_block (location)(rect 2280 3248 2368 3632)) ) (pin (bidir) @@ -2278,7 +2278,7 @@ applicable agreement for further details. (line (pt 52 8)(pt 56 12)) ) (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2120 3272 2176 3288)) + (annotation_block (location)(rect 2120 3272 2208 3512)) ) (pin (bidir) @@ -2296,7 +2296,7 @@ applicable agreement for further details. (line (pt 52 8)(pt 56 12)) ) (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2216 552 2288 568)) + (annotation_block (location)(rect 2248 552 2312 624)) ) (pin (bidir) @@ -2314,7 +2314,25 @@ applicable agreement for further details. (line (pt 52 8)(pt 56 12)) ) (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) - (annotation_block (location)(rect 2824 312 2888 328)) + (annotation_block (location)(rect 2856 304 2920 768)) +) +(pin + (bidir) + (rect 1960 2200 2136 2216) + (text "BIDIR" (rect 1 0 28 10)(font "Arial" (font_size 6))) + (text "MIDI_IN_PIN" (rect 90 0 154 11)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 56 4)(pt 78 4)) + (line (pt 0 8)(pt 52 8)) + (line (pt 56 12)(pt 78 12)) + (line (pt 78 4)(pt 82 8)) + (line (pt 78 12)(pt 82 8)) + (line (pt 56 4)(pt 52 8)) + (line (pt 52 8)(pt 56 12)) + ) + (text "VCC" (rect 4 7 25 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 2136 2216 2192 2232)) ) (symbol (rect 464 1336 608 1432) @@ -2359,7 +2377,7 @@ applicable agreement for further details. ) ) (symbol - (rect 544 2024 688 2088) + (rect 544 2032 688 2096) (text "lpm_counter0" (rect 33 1 129 17)(font "Arial" (font_size 10))) (text "inst18" (rect 8 48 38 59)(font "Arial" )) (port @@ -2373,7 +2391,7 @@ applicable agreement for further details. (pt 144 40) (output) (text "q[17..0]" (rect 0 0 43 13)(font "Arial" (font_size 8))) - (text "q[17..0]" (rect 87 34 130 47)(font "Arial" (font_size 8))) + (text "q[17..0]" (rect 89 34 132 47)(font "Arial" (font_size 8))) (line (pt 144 40)(pt 128 40)(line_width 3)) ) (drawing @@ -2660,12 +2678,12 @@ applicable agreement for further details. (symbol (rect 2368 120 2400 152) (text "GND" (rect 6 8 16 30)(font "Arial" (font_size 6))(vertical)) - (text "inst10" (rect 0 3 11 33)(font "Arial" )(vertical)(invisible)) + (text "inst10" (rect -1 3 10 33)(font "Arial" )(vertical)(invisible)) (port (pt 32 16) (output) (text "1" (rect 18 0 25 11)(font "Courier New" (bold))(invisible)) - (text "1" (rect 21 18 32 25)(font "Courier New" (bold))(vertical)(invisible)) + (text "1" (rect 20 18 31 25)(font "Courier New" (bold))(vertical)(invisible)) (line (pt 24 16)(pt 32 16)) ) (drawing @@ -2817,64 +2835,7 @@ applicable agreement for further details. ) ) (symbol - (rect -16 680 32 712) - (text "NOT" (rect 1 0 22 10)(font "Arial" (font_size 6))) - (text "inst23" (rect 3 21 33 32)(font "Arial" )) - (port - (pt 0 16) - (input) - (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) - (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) - (line (pt 0 16)(pt 13 16)) - ) - (port - (pt 48 16) - (output) - (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) - (line (pt 39 16)(pt 48 16)) - ) - (drawing - (line (pt 13 25)(pt 13 7)) - (line (pt 13 7)(pt 31 16)) - (line (pt 13 25)(pt 31 16)) - (circle (rect 31 12 39 20)) - ) -) -(symbol - (rect 944 416 1008 464) - (text "AND2" (rect 1 0 29 10)(font "Arial" (font_size 6))) - (text "inst25" (rect 3 37 33 48)(font "Arial" )) - (port - (pt 0 16) - (input) - (text "IN1" (rect 2 7 22 18)(font "Courier New" (bold))(invisible)) - (text "IN1" (rect 2 7 22 18)(font "Courier New" (bold))(invisible)) - (line (pt 0 16)(pt 14 16)) - ) - (port - (pt 0 32) - (input) - (text "IN2" (rect 2 23 22 34)(font "Courier New" (bold))(invisible)) - (text "IN2" (rect 2 23 22 34)(font "Courier New" (bold))(invisible)) - (line (pt 0 32)(pt 14 32)) - ) - (port - (pt 64 24) - (output) - (text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible)) - (text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible)) - (line (pt 42 24)(pt 64 24)) - ) - (drawing - (line (pt 14 12)(pt 30 12)) - (line (pt 14 37)(pt 31 37)) - (line (pt 14 12)(pt 14 37)) - (arc (pt 31 37)(pt 30 12)(rect 18 12 43 37)) - ) -) -(symbol - (rect 456 -352 760 -104) + (rect 448 -352 752 -104) (text "altpll2" (rect 132 1 174 17)(font "Arial" (font_size 10))) (text "i_ddr_clk_pll" (rect 8 229 70 240)(font "Arial" )) (port @@ -2970,172 +2931,34 @@ applicable agreement for further details. ) ) (symbol - (rect 448 -88 704 96) - (text "altpll3" (rect 111 0 153 16)(font "Arial" (font_size 10))) - (text "i_atari_clk_pll" (rect 8 169 76 180)(font "Arial" )) + (rect -16 680 32 712) + (text "NOT" (rect 1 0 22 10)(font "Arial" (font_size 6))) + (text "inst23" (rect 3 21 33 32)(font "Arial" )) (port - (pt 0 64) + (pt 0 16) (input) - (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 51 38 64)(font "Arial" (font_size 8))) - (line (pt 0 64)(pt 40 64)) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 13 16)) ) (port - (pt 256 64) + (pt 48 16) (output) - (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c0" (rect 241 51 256 64)(font "Arial" (font_size 8))) - ) - (port - (pt 256 80) - (output) - (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) - (text "c1" (rect 241 67 255 80)(font "Arial" (font_size 8))) - ) - (port - (pt 256 96) - (output) - (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c2" (rect 241 83 256 96)(font "Arial" (font_size 8))) - ) - (port - (pt 256 112) - (output) - (text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c3" (rect 241 99 256 112)(font "Arial" (font_size 8))) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (line (pt 39 16)(pt 48 16)) ) (drawing - (text "Cyclone III" (rect 198 170 249 181)(font "Arial" )) - (text "inclk0 frequency: 33.000 MHz" (rect 50 60 196 71)(font "Arial" )) - (text "Operation Mode: Src Sync Comp" (rect 50 72 212 83)(font "Arial" )) - (text "Clk " (rect 51 91 71 102)(font "Arial" )) - (text "Ratio" (rect 77 91 104 102)(font "Arial" )) - (text "Ph (dg)" (rect 109 91 146 102)(font "Arial" )) - (text "DC (%)" (rect 144 91 181 102)(font "Arial" )) - (text "c0" (rect 54 104 66 115)(font "Arial" )) - (text "2/33" (rect 79 104 102 115)(font "Arial" )) - (text "0.00" (rect 115 104 138 115)(font "Arial" )) - (text "50.00" (rect 148 104 177 115)(font "Arial" )) - (text "c1" (rect 54 117 65 128)(font "Arial" )) - (text "16/33" (rect 77 117 106 128)(font "Arial" )) - (text "0.00" (rect 115 117 138 128)(font "Arial" )) - (text "50.00" (rect 148 117 177 128)(font "Arial" )) - (text "c2" (rect 54 130 66 141)(font "Arial" )) - (text "109/144" (rect 71 130 112 141)(font "Arial" )) - (text "0.00" (rect 115 130 138 141)(font "Arial" )) - (text "50.00" (rect 148 130 177 141)(font "Arial" )) - (text "c3" (rect 54 143 66 154)(font "Arial" )) - (text "16/11" (rect 77 143 105 154)(font "Arial" )) - (text "0.00" (rect 115 143 138 154)(font "Arial" )) - (text "50.00" (rect 148 143 177 154)(font "Arial" )) - (line (pt 0 0)(pt 257 0)) - (line (pt 257 0)(pt 257 185)) - (line (pt 0 185)(pt 257 185)) - (line (pt 0 0)(pt 0 185)) - (line (pt 48 89)(pt 176 89)) - (line (pt 48 101)(pt 176 101)) - (line (pt 48 114)(pt 176 114)) - (line (pt 48 127)(pt 176 127)) - (line (pt 48 140)(pt 176 140)) - (line (pt 48 153)(pt 176 153)) - (line (pt 48 89)(pt 48 153)) - (line (pt 68 89)(pt 68 153)(line_width 3)) - (line (pt 106 89)(pt 106 153)(line_width 3)) - (line (pt 141 89)(pt 141 153)(line_width 3)) - (line (pt 175 89)(pt 175 153)) - (line (pt 40 48)(pt 223 48)) - (line (pt 223 48)(pt 223 167)) - (line (pt 40 167)(pt 223 167)) - (line (pt 40 48)(pt 40 167)) - (line (pt 255 64)(pt 223 64)) - (line (pt 255 80)(pt 223 80)) - (line (pt 255 96)(pt 223 96)) - (line (pt 255 112)(pt 223 112)) - ) -) -(symbol - (rect 440 176 768 392) - (text "altpll1" (rect 144 1 185 17)(font "Arial" (font_size 10))) - (text "i_mfp_acia_clk_pll" (rect 8 197 100 208)(font "Arial" )) - (port - (pt 0 72) - (input) - (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) - (text "inclk0" (rect 4 56 38 69)(font "Arial" (font_size 8))) - (line (pt 0 72)(pt 48 72)) - ) - (port - (pt 328 72) - (output) - (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c0" (rect 311 56 326 69)(font "Arial" (font_size 8))) - (line (pt 328 72)(pt 272 72)) - ) - (port - (pt 328 96) - (output) - (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) - (text "c1" (rect 311 80 325 93)(font "Arial" (font_size 8))) - (line (pt 328 96)(pt 272 96)) - ) - (port - (pt 328 120) - (output) - (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) - (text "c2" (rect 311 104 326 117)(font "Arial" (font_size 8))) - (line (pt 328 120)(pt 272 120)) - ) - (port - (pt 328 144) - (output) - (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8))) - (text "locked" (rect 287 128 324 141)(font "Arial" (font_size 8))) - (line (pt 328 144)(pt 272 144)) - ) - (drawing - (text "Cyclone III" (rect 253 198 304 209)(font "Arial" )) - (text "inclk0 frequency: 33.000 MHz" (rect 58 67 204 78)(font "Arial" )) - (text "Operation Mode: Src Sync Comp" (rect 58 84 220 95)(font "Arial" )) - (text "Clk " (rect 59 111 79 122)(font "Arial" )) - (text "Ratio" (rect 90 111 117 122)(font "Arial" )) - (text "Ph (dg)" (rect 128 111 165 122)(font "Arial" )) - (text "DC (%)" (rect 173 111 210 122)(font "Arial" )) - (text "c0" (rect 63 129 75 140)(font "Arial" )) - (text "1/66" (rect 92 129 115 140)(font "Arial" )) - (text "0.00" (rect 136 129 159 140)(font "Arial" )) - (text "50.00" (rect 178 129 207 140)(font "Arial" )) - (text "c1" (rect 63 147 74 158)(font "Arial" )) - (text "67/900" (rect 85 147 120 158)(font "Arial" )) - (text "0.00" (rect 136 147 159 158)(font "Arial" )) - (text "50.00" (rect 178 147 207 158)(font "Arial" )) - (text "c2" (rect 63 165 75 176)(font "Arial" )) - (text "67/90" (rect 89 165 118 176)(font "Arial" )) - (text "0.00" (rect 136 165 159 176)(font "Arial" )) - (text "50.00" (rect 178 165 207 176)(font "Arial" )) - (line (pt 0 0)(pt 329 0)) - (line (pt 329 0)(pt 329 217)) - (line (pt 0 217)(pt 329 217)) - (line (pt 0 0)(pt 0 217)) - (line (pt 56 108)(pt 215 108)) - (line (pt 56 125)(pt 215 125)) - (line (pt 56 143)(pt 215 143)) - (line (pt 56 161)(pt 215 161)) - (line (pt 56 179)(pt 215 179)) - (line (pt 56 108)(pt 56 179)) - (line (pt 82 108)(pt 82 179)(line_width 3)) - (line (pt 125 108)(pt 125 179)(line_width 3)) - (line (pt 170 108)(pt 170 179)(line_width 3)) - (line (pt 214 108)(pt 214 179)) - (line (pt 48 56)(pt 272 56)) - (line (pt 272 56)(pt 272 200)) - (line (pt 48 200)(pt 272 200)) - (line (pt 48 56)(pt 48 200)) + (line (pt 13 25)(pt 13 7)) + (line (pt 13 7)(pt 31 16)) + (line (pt 13 25)(pt 31 16)) + (circle (rect 31 12 39 20)) ) ) (symbol (rect 192 472 408 768) (text "altpll_reconfig1" (rect 54 1 160 17)(font "Arial" (font_size 10))) - (text "i_programmable_clk" (rect 8 277 108 288)(font "Arial" )) + (text "i_pll_reconfig" (rect 8 277 74 288)(font "Arial" )) (port (pt 0 40) (input) @@ -3217,49 +3040,49 @@ applicable agreement for further details. (pt 216 40) (output) (text "busy" (rect 0 0 29 13)(font "Arial" (font_size 8))) - (text "busy" (rect 171 32 200 45)(font "Arial" (font_size 8))) + (text "busy" (rect 169 32 198 45)(font "Arial" (font_size 8))) (line (pt 216 40)(pt 200 40)) ) (port (pt 216 96) (output) (text "data_out[8..0]" (rect 0 0 79 13)(font "Arial" (font_size 8))) - (text "data_out[8..0]" (rect 129 88 208 101)(font "Arial" (font_size 8))) + (text "data_out[8..0]" (rect 117 88 196 101)(font "Arial" (font_size 8))) (line (pt 216 96)(pt 200 96)(line_width 3)) ) (port (pt 216 152) (output) (text "pll_scandata" (rect 0 0 71 13)(font "Arial" (font_size 8))) - (text "pll_scandata" (rect 135 144 206 157)(font "Arial" (font_size 8))) + (text "pll_scandata" (rect 124 144 195 157)(font "Arial" (font_size 8))) (line (pt 216 152)(pt 200 152)) ) (port (pt 216 168) (output) (text "pll_scanclk" (rect 0 0 64 13)(font "Arial" (font_size 8))) - (text "pll_scanclk" (rect 141 160 205 173)(font "Arial" (font_size 8))) + (text "pll_scanclk" (rect 132 160 196 173)(font "Arial" (font_size 8))) (line (pt 216 168)(pt 200 168)) ) (port (pt 216 200) (output) (text "pll_scanclkena" (rect 0 0 83 13)(font "Arial" (font_size 8))) - (text "pll_scanclkena" (rect 125 192 208 205)(font "Arial" (font_size 8))) + (text "pll_scanclkena" (rect 111 192 194 205)(font "Arial" (font_size 8))) (line (pt 216 200)(pt 200 200)) ) (port (pt 216 216) (output) (text "pll_configupdate" (rect 0 0 93 13)(font "Arial" (font_size 8))) - (text "pll_configupdate" (rect 117 208 210 221)(font "Arial" (font_size 8))) + (text "pll_configupdate" (rect 104 208 197 221)(font "Arial" (font_size 8))) (line (pt 216 216)(pt 200 216)) ) (port (pt 216 248) (output) (text "pll_areset" (rect 0 0 56 13)(font "Arial" (font_size 8))) - (text "pll_areset" (rect 148 240 204 253)(font "Arial" (font_size 8))) + (text "pll_areset" (rect 141 240 197 253)(font "Arial" (font_size 8))) (line (pt 216 248)(pt 200 248)) ) (drawing @@ -3377,6 +3200,396 @@ applicable agreement for further details. (line (pt 88 56)(pt 88 216)) ) ) +(symbol + (rect 800 144 848 176) + (text "WIRE" (rect 1 0 26 10)(font "Arial" (font_size 6))) + (text "inst20" (rect 3 21 33 32)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (text "IN" (rect 2 7 17 18)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 14 16)) + ) + (port + (pt 48 16) + (output) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 53 18)(font "Courier New" (bold))(invisible)) + (line (pt 32 16)(pt 48 16)) + ) + (drawing + (line (pt 14 7)(pt 32 16)) + (line (pt 14 25)(pt 14 7)) + (line (pt 14 25)(pt 32 16)) + ) +) +(symbol + (rect 952 416 1016 464) + (text "AND3" (rect 1 0 29 10)(font "Arial" (font_size 6))) + (text "inst25" (rect 3 37 33 48)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN1" (rect 2 7 22 18)(font "Courier New" (bold))(invisible)) + (text "IN1" (rect 2 7 22 18)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 16 16)) + ) + (port + (pt 0 24) + (input) + (text "IN2" (rect 2 15 22 26)(font "Courier New" (bold))(invisible)) + (text "IN2" (rect 2 15 22 26)(font "Courier New" (bold))(invisible)) + (line (pt 0 24)(pt 16 24)) + ) + (port + (pt 0 32) + (input) + (text "IN3" (rect 2 23 22 34)(font "Courier New" (bold))(invisible)) + (text "IN3" (rect 2 23 22 34)(font "Courier New" (bold))(invisible)) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 64 24) + (output) + (text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 48 15 69 26)(font "Courier New" (bold))(invisible)) + (line (pt 43 24)(pt 64 24)) + ) + (drawing + (line (pt 16 12)(pt 31 12)) + (line (pt 16 37)(pt 31 37)) + (line (pt 16 12)(pt 16 37)) + (arc (pt 31 36)(pt 31 12)(rect 19 12 44 37)) + ) +) +(symbol + (rect 1864 2192 1912 2240) + (text "ALT_IOBUF" (rect 1 0 54 10)(font "Arial" (font_size 6))) + (text "inst29" (rect 3 36 31 46)(font "Arial" (font_size 6))) + (port + (pt 0 16) + (input) + (text "i" (rect 6 7 13 18)(font "Courier New" (bold))(invisible)) + (text "i" (rect 6 7 13 18)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 14 16)) + ) + (port + (pt 24 0) + (input) + (text "oe" (rect 29 1 44 12)(font "Courier New" (bold))(invisible)) + (text "oe" (rect 29 1 44 12)(font "Courier New" (bold))(invisible)) + (line (pt 24 12)(pt 24 0)) + ) + (port + (pt 0 32) + (output) + (text "o" (rect 20 23 28 37)(font "Courier New" (font_size 8))(invisible)) + (text "o" (rect 20 23 28 37)(font "Courier New" (font_size 8))(invisible)) + (line (pt 0 32)(pt 14 32)) + ) + (port + (pt 48 16) + (bidir) + (text "io" (rect 38 7 53 18)(font "Courier New" (bold))(invisible)) + (text "io" (rect 38 7 53 18)(font "Courier New" (bold))(invisible)) + (line (pt 40 16)(pt 48 16)) + ) + (drawing + (line (pt 32 32)(pt 40 32)) + (line (pt 14 25)(pt 14 7)) + (line (pt 32 41)(pt 32 23)) + (line (pt 40 32)(pt 40 17)) + (line (pt 14 7)(pt 32 16)) + (line (pt 14 25)(pt 32 16)) + (line (pt 14 32)(pt 32 23)) + (line (pt 14 32)(pt 32 41)) + (line (pt 32 16)(pt 40 16)) + ) +) +(symbol + (rect 464 -80 736 120) + (text "altpll3" (rect 119 0 161 16)(font "Arial" (font_size 10))) + (text "i_atari_clk_pll" (rect 8 184 76 195)(font "Arial" )) + (port + (pt 0 64) + (input) + (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 51 38 64)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 40 64)) + ) + (port + (pt 272 64) + (output) + (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c0" (rect 257 51 272 64)(font "Arial" (font_size 8))) + (line (pt 272 64)(pt 224 64)) + ) + (port + (pt 272 80) + (output) + (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) + (text "c1" (rect 257 67 271 80)(font "Arial" (font_size 8))) + (line (pt 272 80)(pt 224 80)) + ) + (port + (pt 272 96) + (output) + (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c2" (rect 257 83 272 96)(font "Arial" (font_size 8))) + (line (pt 272 96)(pt 224 96)) + ) + (port + (pt 272 112) + (output) + (text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c3" (rect 257 99 272 112)(font "Arial" (font_size 8))) + (line (pt 272 112)(pt 224 112)) + ) + (port + (pt 272 128) + (output) + (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8))) + (text "locked" (rect 238 115 275 128)(font "Arial" (font_size 8))) + (line (pt 272 128)(pt 224 128)) + ) + (drawing + (text "Cyclone III" (rect 211 185 262 196)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 50 59 196 70)(font "Arial" )) + (text "Operation Mode: Src Sync Comp" (rect 50 73 212 84)(font "Arial" )) + (text "Clk " (rect 51 96 71 107)(font "Arial" )) + (text "Ratio" (rect 81 96 108 107)(font "Arial" )) + (text "Ph (dg)" (rect 116 96 153 107)(font "Arial" )) + (text "DC (%)" (rect 151 96 188 107)(font "Arial" )) + (text "c0" (rect 54 111 66 122)(font "Arial" )) + (text "25/33" (rect 81 111 110 122)(font "Arial" )) + (text "0.00" (rect 122 111 145 122)(font "Arial" )) + (text "50.00" (rect 155 111 184 122)(font "Arial" )) + (text "c1" (rect 54 126 65 137)(font "Arial" )) + (text "2/33" (rect 83 126 106 137)(font "Arial" )) + (text "0.00" (rect 122 126 145 137)(font "Arial" )) + (text "50.00" (rect 155 126 184 137)(font "Arial" )) + (text "c2" (rect 54 141 66 152)(font "Arial" )) + (text "1/66" (rect 83 141 106 152)(font "Arial" )) + (text "0.00" (rect 122 141 145 152)(font "Arial" )) + (text "50.00" (rect 155 141 184 152)(font "Arial" )) + (text "c3" (rect 54 156 66 167)(font "Arial" )) + (text "512/6875" (rect 73 156 120 167)(font "Arial" )) + (text "0.00" (rect 122 156 145 167)(font "Arial" )) + (text "50.00" (rect 155 156 184 167)(font "Arial" )) + (line (pt 0 0)(pt 273 0)) + (line (pt 273 0)(pt 273 201)) + (line (pt 0 201)(pt 273 201)) + (line (pt 0 0)(pt 0 201)) + (line (pt 48 94)(pt 184 94)) + (line (pt 48 108)(pt 184 108)) + (line (pt 48 123)(pt 184 123)) + (line (pt 48 138)(pt 184 138)) + (line (pt 48 153)(pt 184 153)) + (line (pt 48 168)(pt 184 168)) + (line (pt 48 94)(pt 48 168)) + (line (pt 70 94)(pt 70 168)(line_width 3)) + (line (pt 113 94)(pt 113 168)(line_width 3)) + (line (pt 148 94)(pt 148 168)(line_width 3)) + (line (pt 183 94)(pt 183 168)) + (line (pt 40 48)(pt 224 48)) + (line (pt 224 48)(pt 224 184)) + (line (pt 40 184)(pt 224 184)) + (line (pt 40 48)(pt 40 184)) + ) +) +(symbol + (rect 440 184 712 368) + (text "altpll1" (rect 119 0 160 16)(font "Arial" (font_size 10))) + (text "i_mfp_acia_clk_pll" (rect 8 168 100 179)(font "Arial" )) + (port + (pt 0 64) + (input) + (text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8))) + (text "inclk0" (rect 4 51 38 64)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 40 64)) + ) + (port + (pt 272 64) + (output) + (text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c0" (rect 257 51 272 64)(font "Arial" (font_size 8))) + (line (pt 272 64)(pt 224 64)) + ) + (port + (pt 272 80) + (output) + (text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8))) + (text "c1" (rect 257 67 271 80)(font "Arial" (font_size 8))) + (line (pt 272 80)(pt 224 80)) + ) + (port + (pt 272 96) + (output) + (text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8))) + (text "c2" (rect 257 83 272 96)(font "Arial" (font_size 8))) + (line (pt 272 96)(pt 224 96)) + ) + (port + (pt 272 112) + (output) + (text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8))) + (text "locked" (rect 238 99 275 112)(font "Arial" (font_size 8))) + (line (pt 272 112)(pt 224 112)) + ) + (drawing + (text "Cyclone III" (rect 211 169 262 180)(font "Arial" )) + (text "inclk0 frequency: 33.000 MHz" (rect 50 59 196 70)(font "Arial" )) + (text "Operation Mode: Src Sync Comp" (rect 50 73 212 84)(font "Arial" )) + (text "Clk " (rect 51 96 71 107)(font "Arial" )) + (text "Ratio" (rect 83 96 110 107)(font "Arial" )) + (text "Ph (dg)" (rect 121 96 158 107)(font "Arial" )) + (text "DC (%)" (rect 156 96 193 107)(font "Arial" )) + (text "c0" (rect 54 111 66 122)(font "Arial" )) + (text "16/11" (rect 83 111 111 122)(font "Arial" )) + (text "0.00" (rect 127 111 150 122)(font "Arial" )) + (text "50.00" (rect 160 111 189 122)(font "Arial" )) + (text "c1" (rect 54 126 65 137)(font "Arial" )) + (text "16/33" (rect 83 126 112 137)(font "Arial" )) + (text "0.00" (rect 127 126 150 137)(font "Arial" )) + (text "50.00" (rect 160 126 189 137)(font "Arial" )) + (text "c2" (rect 54 141 66 152)(font "Arial" )) + (text "1024/1375" (rect 73 141 127 152)(font "Arial" )) + (text "0.00" (rect 127 141 150 152)(font "Arial" )) + (text "50.00" (rect 160 141 189 152)(font "Arial" )) + (line (pt 0 0)(pt 273 0)) + (line (pt 273 0)(pt 273 185)) + (line (pt 0 185)(pt 273 185)) + (line (pt 0 0)(pt 0 185)) + (line (pt 48 94)(pt 189 94)) + (line (pt 48 108)(pt 189 108)) + (line (pt 48 123)(pt 189 123)) + (line (pt 48 138)(pt 189 138)) + (line (pt 48 153)(pt 189 153)) + (line (pt 48 94)(pt 48 153)) + (line (pt 70 94)(pt 70 153)(line_width 3)) + (line (pt 118 94)(pt 118 153)(line_width 3)) + (line (pt 153 94)(pt 153 153)(line_width 3)) + (line (pt 188 94)(pt 188 153)) + (line (pt 40 48)(pt 224 48)) + (line (pt 224 48)(pt 224 168)) + (line (pt 40 168)(pt 224 168)) + (line (pt 40 48)(pt 40 168)) + ) +) +(block + (rect 1264 2944 1672 3560) + (text "dsp" (rect 5 5 27 18)(font "Arial" (font_size 8))) (text "i_dsp" (rect 5 602 33 613)(font "Arial" )) (block_io "CLK33M" (input)) + (block_io "MAIN_CLK" (input)) + (block_io "nFB_OE" (input)) + (block_io "nFB_WR" (input)) + (block_io "nFB_CS1" (input)) + (block_io "nFB_CS2" (input)) + (block_io "FB_SIZE0" (input)) + (block_io "FB_SIZE1" (input)) + (block_io "nFB_BURST" (input)) + (block_io "FB_ADR[31..0]" (input)) + (block_io "nRSTO" (input)) + (block_io "nFB_CS3" (input)) + (block_io "nSRCS" (output)) + (block_io "nSRBLE" (output)) + (block_io "nSRBHE" (output)) + (block_io "nSRWE" (output)) + (block_io "nSROE" (output)) + (block_io "DSP_INT" (output)) + (block_io "DSP_TA" (output)) + (block_io "FB_AD[31..0]" (bidir)) + (block_io "IO[17..0]" (bidir)) + (block_io "SRD[15..0]" (bidir)) + (mapper + (pt 408 416) + (bidir) + ) + (mapper + (pt 408 392) + (bidir) + ) + (mapper + (pt 408 368) + (bidir) + ) + (mapper + (pt 408 320) + (bidir) + ) + (mapper + (pt 408 440) + (bidir) + ) + (mapper + (pt 408 344) + (bidir) + ) + (mapper + (pt 408 296) + (bidir) + ) + (mapper + (pt 408 40) + (bidir) + ) + (mapper + (pt 0 56) + (bidir) + ) + (mapper + (pt 0 80) + (bidir) + ) + (mapper + (pt 0 104) + (bidir) + ) + (mapper + (pt 0 128) + (bidir) + ) + (mapper + (pt 0 152) + (bidir) + ) + (mapper + (pt 0 176) + (bidir) + ) + (mapper + (pt 0 248) + (bidir) + ) + (mapper + (pt 0 224) + (bidir) + ) + (mapper + (pt 0 272) + (bidir) + ) + (mapper + (pt 0 296) + (bidir) + ) + (mapper + (pt 408 72) + (bidir) + ) + (mapper + (pt 408 576) + (bidir) + ) + (mapper + (pt 0 320) + (bidir) + ) + (mapper + (pt 0 200) + (bidir) + ) +) (block (rect 1264 2344 1672 2904) (text "interrupt_handler" (rect 5 5 101 18)(font "Arial" (font_size 8))) (text "i_interrupt_handler" (rect 5 546 99 557)(font "Arial" )) (block_io "MAIN_CLK" (input)) @@ -3399,35 +3612,12 @@ applicable agreement for further details. (block_io "VSYNC" (input)) (block_io "HSYNC" (input)) (block_io "DMA_DRQ" (input)) + (block_io "nRSTO" (input)) (block_io "nIRQ[7..2]" (output)) (block_io "INT_HANDLER_TA" (output)) (block_io "ACP_CONF[31..0]" (output)) (block_io "TIN0" (output)) (block_io "FB_AD[31..0]" (bidir)) - (mapper - (pt 0 136) - (bidir) - ) - (mapper - (pt 0 160) - (bidir) - ) - (mapper - (pt 0 184) - (bidir) - ) - (mapper - (pt 0 88) - (bidir) - ) - (mapper - (pt 0 112) - (bidir) - ) - (mapper - (pt 0 40) - (bidir) - ) (mapper (pt 408 56) (bidir) @@ -3448,14 +3638,6 @@ applicable agreement for further details. (pt 0 304) (bidir) ) - (mapper - (pt 0 208) - (bidir) - ) - (mapper - (pt 0 64) - (bidir) - ) (mapper (pt 0 376) (bidir) @@ -3504,9 +3686,559 @@ applicable agreement for further details. (pt 408 296) (bidir) ) + (mapper + (pt 0 224) + (bidir) + ) + (mapper + (pt 0 104) + (bidir) + ) + (mapper + (pt 0 128) + (bidir) + ) + (mapper + (pt 0 176) + (bidir) + ) + (mapper + (pt 0 200) + (bidir) + ) + (mapper + (pt 0 56) + (bidir) + ) + (mapper + (pt 0 152) + (bidir) + ) + (mapper + (pt 0 80) + (bidir) + ) + (mapper + (pt 0 32) + (bidir) + ) ) (block - (rect 1264 -40 1672 736) + (rect 1264 744 1672 2312) + (text "falconio_sdcard_ide_cf" (rect 5 5 135 18)(font "Arial" (font_size 8))) (text "i_falcioio_sdcard_ide_cf" (rect 5 1554 124 1565)(font "Arial" )) (block_io "CLK33M" (input)) + (block_io "MAIN_CLK" (input)) + (block_io "CLK2M" (input)) + (block_io "CLK500k" (input)) + (block_io "nFB_CS1" (input)) + (block_io "FB_SIZE0" (input)) + (block_io "FB_SIZE1" (input)) + (block_io "nFB_BURST" (input)) + (block_io "FB_ADR[31..0]" (input)) + (block_io "LP_BUSY" (input)) + (block_io "nACSI_DRQ" (input)) + (block_io "nACSI_INT" (input)) + (block_io "nSCSI_DRQ" (input)) + (block_io "nSCSI_MSG" (input)) + (block_io "MIDI_IN" (input)) + (block_io "RxD" (input)) + (block_io "CTS" (input)) + (block_io "RI" (input)) + (block_io "DCD" (input)) + (block_io "AMKB_RX" (input)) + (block_io "PIC_AMKB_RX" (input)) + (block_io "IDE_RDY" (input)) + (block_io "IDE_INT" (input)) + (block_io "WP_CS_CARD" (input)) + (block_io "nINDEX" (input)) + (block_io "TRACK00" (input)) + (block_io "nRD_DATA" (input)) + (block_io "nDCHG" (input)) + (block_io "SD_DATA0" (input)) + (block_io "SD_DATA1" (input)) + (block_io "SD_DATA2" (input)) + (block_io "SD_CARD_DEDECT" (input)) + (block_io "SD_WP" (input)) + (block_io "nDACK0" (input)) + (block_io "nFB_WR" (input)) + (block_io "WP_CF_CARD" (input)) + (block_io "nWP" (input)) + (block_io "nFB_CS2" (input)) + (block_io "nRSTO" (input)) + (block_io "nSCSI_C_D" (input)) + (block_io "nSCSI_I_O" (input)) + (block_io "CLK2M4576" (input)) + (block_io "nFB_OE" (input)) + (block_io "VSYNC" (input)) + (block_io "HSYNC" (input)) + (block_io "DSP_INT" (input)) + (block_io "nBLANK" (input)) + (block_io "FDC_CLK" (input)) + (block_io "FB_ALE" (input)) + (block_io "ACP_CONF[31..24]" (input)) + (block_io "HD_DD" (input)) + (block_io "nIDE_CS1" (output)) + (block_io "nIDE_CS0" (output)) + (block_io "LP_STR" (output)) + (block_io "LP_DIR" (output)) + (block_io "nACSI_ACK" (output)) + (block_io "nACSI_RESET" (output)) + (block_io "nACSI_CS" (output)) + (block_io "ACSI_DIR" (output)) + (block_io "ACSI_A1" (output)) + (block_io "nSCSI_ACK" (output)) + (block_io "nSCSI_ATN" (output)) + (block_io "SCSI_DIR" (output)) + (block_io "SD_CLK" (output)) + (block_io "YM_QA" (output)) + (block_io "YM_QC" (output)) + (block_io "YM_QB" (output)) + (block_io "nSDSEL" (output)) + (block_io "STEP" (output)) + (block_io "MOT_ON" (output)) + (block_io "nRP_LDS" (output)) + (block_io "nRP_UDS" (output)) + (block_io "nROM4" (output)) + (block_io "nROM3" (output)) + (block_io "nCF_CS1" (output)) + (block_io "nCF_CS0" (output)) + (block_io "nIDE_RD" (output)) + (block_io "nIDE_WR" (output)) + (block_io "AMKB_TX" (output)) + (block_io "IDE_RES" (output)) + (block_io "DTR" (output)) + (block_io "RTS" (output)) + (block_io "TxD" (output)) + (block_io "MIDI_OLR" (output)) + (block_io "nDREQ0" (output)) + (block_io "DSA_D" (output)) + (block_io "nMFP_INT" (output)) + (block_io "FALCON_IO_TA" (output)) + (block_io "STEP_DIR" (output)) + (block_io "WR_DATA" (output)) + (block_io "WR_GATE" (output)) + (block_io "DMA_DRQ" (output)) + (block_io "MIDI_TLR" (output)) + (block_io "FB_AD[31..0]" (bidir)) + (block_io "LP_D[7..0]" (bidir)) + (block_io "ACSI_D[7..0]" (bidir)) + (block_io "SCSI_D[7..0]" (bidir)) + (block_io "SCSI_PAR" (bidir)) + (block_io "nSCSI_SEL" (bidir)) + (block_io "nSCSI_BUSY" (bidir)) + (block_io "nSCSI_RST" (bidir)) + (block_io "SD_CD_DATA3" (bidir)) + (block_io "SD_CDM_D1" (bidir)) + (mapper + (pt 0 128) + (bidir) + ) + (mapper + (pt 0 104) + (bidir) + ) + (mapper + (pt 0 56) + (bidir) + ) + (mapper + (pt 0 80) + (bidir) + ) + (mapper + (pt 0 224) + (bidir) + ) + (mapper + (pt 0 248) + (bidir) + ) + (mapper + (pt 0 272) + (bidir) + ) + (mapper + (pt 408 96) + (bidir) + ) + (mapper + (pt 408 120) + (bidir) + ) + (mapper + (pt 408 72) + (bidir) + ) + (mapper + (pt 408 152) + (bidir) + ) + (mapper + (pt 408 200) + (bidir) + ) + (mapper + (pt 408 224) + (bidir) + ) + (mapper + (pt 408 248) + (bidir) + ) + (mapper + (pt 408 272) + (bidir) + ) + (mapper + (pt 408 296) + (bidir) + ) + (mapper + (pt 408 424) + (bidir) + ) + (mapper + (pt 408 352) + (bidir) + ) + (mapper + (pt 408 328) + (bidir) + ) + (mapper + (pt 408 448) + (bidir) + ) + (mapper + (pt 408 400) + (bidir) + ) + (mapper + (pt 408 376) + (bidir) + ) + (mapper + (pt 408 472) + (bidir) + ) + (mapper + (pt 408 496) + (bidir) + ) + (mapper + (pt 408 608) + (bidir) + ) + (mapper + (pt 408 632) + (bidir) + ) + (mapper + (pt 408 584) + (bidir) + ) + (mapper + (pt 0 656) + (bidir) + ) + (mapper + (pt 0 680) + (bidir) + ) + (mapper + (pt 0 704) + (bidir) + ) + (mapper + (pt 0 728) + (bidir) + ) + (mapper + (pt 0 752) + (bidir) + ) + (mapper + (pt 0 776) + (bidir) + ) + (mapper + (pt 408 664) + (bidir) + ) + (mapper + (pt 0 808) + (bidir) + ) + (mapper + (pt 0 832) + (bidir) + ) + (mapper + (pt 408 696) + (bidir) + ) + (mapper + (pt 408 720) + (bidir) + ) + (mapper + (pt 408 744) + (bidir) + ) + (mapper + (pt 408 768) + (bidir) + ) + (mapper + (pt 408 792) + (bidir) + ) + (mapper + (pt 408 816) + (bidir) + ) + (mapper + (pt 408 840) + (bidir) + ) + (mapper + (pt 0 856) + (bidir) + ) + (mapper + (pt 408 872) + (bidir) + ) + (mapper + (pt 408 896) + (bidir) + ) + (mapper + (pt 408 920) + (bidir) + ) + (mapper + (pt 408 944) + (bidir) + ) + (mapper + (pt 0 912) + (bidir) + ) + (mapper + (pt 0 936) + (bidir) + ) + (mapper + (pt 0 960) + (bidir) + ) + (mapper + (pt 0 984) + (bidir) + ) + (mapper + (pt 0 1008) + (bidir) + ) + (mapper + (pt 408 976) + (bidir) + ) + (mapper + (pt 408 1000) + (bidir) + ) + (mapper + (pt 408 1072) + (bidir) + ) + (mapper + (pt 408 1096) + (bidir) + ) + (mapper + (pt 408 1176) + (bidir) + ) + (mapper + (pt 0 296) + (bidir) + ) + (mapper + (pt 408 1256) + (bidir) + ) + (mapper + (pt 0 1040) + (bidir) + ) + (mapper + (pt 0 1064) + (bidir) + ) + (mapper + (pt 0 1088) + (bidir) + ) + (mapper + (pt 0 1112) + (bidir) + ) + (mapper + (pt 0 1136) + (bidir) + ) + (mapper + (pt 0 432) + (bidir) + ) + (mapper + (pt 0 464) + (bidir) + ) + (mapper + (pt 0 488) + (bidir) + ) + (mapper + (pt 0 520) + (bidir) + ) + (mapper + (pt 0 544) + (bidir) + ) + (mapper + (pt 0 568) + (bidir) + ) + (mapper + (pt 0 592) + (bidir) + ) + (mapper + (pt 0 320) + (bidir) + ) + (mapper + (pt 0 200) + (bidir) + ) + (mapper + (pt 0 344) + (bidir) + ) + (mapper + (pt 0 1168) + (bidir) + ) + (mapper + (pt 0 1192) + (bidir) + ) + (mapper + (pt 0 368) + (bidir) + ) + (mapper + (pt 0 392) + (bidir) + ) + (mapper + (pt 0 176) + (bidir) + ) + (mapper + (pt 0 1216) + (bidir) + ) + (mapper + (pt 408 48) + (bidir) + ) + (mapper + (pt 408 16) + (bidir) + ) + (mapper + (pt 0 1240) + (bidir) + ) + (mapper + (pt 408 1304) + (bidir) + ) + (mapper + (pt 408 1200) + (bidir) + ) + (mapper + (pt 408 1344) + (bidir) + ) + (mapper + (pt 408 1280) + (bidir) + ) + (mapper + (pt 408 1224) + (bidir) + ) + (mapper + (pt 408 1120) + (bidir) + ) + (mapper + (pt 408 1048) + (bidir) + ) + (mapper + (pt 408 1024) + (bidir) + ) + (mapper + (pt 0 32) + (bidir) + ) + (mapper + (pt 0 152) + (bidir) + ) + (mapper + (pt 408 1368) + (bidir) + ) + (mapper + (pt 0 1264) + (bidir) + ) + (mapper + (pt 0 1336) + (bidir) + ) + (mapper + (pt 0 888) + (bidir) + ) + (mapper + (pt 408 1480) + (bidir) + ) + (mapper + (pt 408 1504) + (bidir) + ) + (mapper + (pt 408 1392) + (bidir) + ) + (mapper + (pt 408 1544) + (bidir) + ) +) +(block + (rect 1264 -48 1672 728) (text "video" (rect 5 5 36 18)(font "Arial" (font_size 8))) (text "i_video" (rect 5 762 41 773)(font "Arial" )) (block_io "FB_ADR[31..0]" (input)) (block_io "MAIN_CLK" (input)) (block_io "nFB_CS1" (input)) @@ -3718,821 +4450,6 @@ applicable agreement for further details. (bidir) ) ) -(block - (rect 1264 744 1672 2264) - (text "falconio_sdcard_ide_cf" (rect 5 5 135 18)(font "Arial" (font_size 8))) (text "i_falcon_io_sdcard_ide_cf" (rect 5 1506 133 1517)(font "Arial" )) (block_io "CLK33M" (input)) - (block_io "MAIN_CLK" (input)) - (block_io "CLK2M" (input)) - (block_io "CLK500k" (input)) - (block_io "nFB_CS1" (input)) - (block_io "FB_SIZE0" (input)) - (block_io "FB_SIZE1" (input)) - (block_io "nFB_BURST" (input)) - (block_io "FB_ADR[31..0]" (input)) - (block_io "LP_BUSY" (input)) - (block_io "nACSI_DRQ" (input)) - (block_io "nACSI_INT" (input)) - (block_io "nSCSI_DRQ" (input)) - (block_io "nSCSI_MSG" (input)) - (block_io "MIDI_IN" (input)) - (block_io "RxD" (input)) - (block_io "CTS" (input)) - (block_io "RI" (input)) - (block_io "DCD" (input)) - (block_io "AMKB_RX" (input)) - (block_io "PIC_AMKB_RX" (input)) - (block_io "IDE_RDY" (input)) - (block_io "IDE_INT" (input)) - (block_io "WP_CS_CARD" (input)) - (block_io "nINDEX" (input)) - (block_io "TRACK00" (input)) - (block_io "nRD_DATA" (input)) - (block_io "nDCHG" (input)) - (block_io "SD_DATA0" (input)) - (block_io "SD_DATA1" (input)) - (block_io "SD_DATA2" (input)) - (block_io "SD_CARD_DEDECT" (input)) - (block_io "SD_WP" (input)) - (block_io "nDACK0" (input)) - (block_io "nFB_WR" (input)) - (block_io "WP_CF_CARD" (input)) - (block_io "nWP" (input)) - (block_io "nFB_CS2" (input)) - (block_io "nRSTO" (input)) - (block_io "nSCSI_C_D" (input)) - (block_io "nSCSI_I_O" (input)) - (block_io "CLK2M4576" (input)) - (block_io "nFB_OE" (input)) - (block_io "VSYNC" (input)) - (block_io "HSYNC" (input)) - (block_io "DSP_INT" (input)) - (block_io "nBLANK" (input)) - (block_io "FDC_CLK" (input)) - (block_io "FB_ALE" (input)) - (block_io "ACP_CONF[31..24]" (input)) - (block_io "HD_DD" (input)) - (block_io "nIDE_CS1" (output)) - (block_io "nIDE_CS0" (output)) - (block_io "LP_STR" (output)) - (block_io "LP_DIR" (output)) - (block_io "nACSI_ACK" (output)) - (block_io "nACSI_RESET" (output)) - (block_io "nACSI_CS" (output)) - (block_io "ACSI_DIR" (output)) - (block_io "ACSI_A1" (output)) - (block_io "nSCSI_ACK" (output)) - (block_io "nSCSI_ATN" (output)) - (block_io "SCSI_DIR" (output)) - (block_io "SD_CLK" (output)) - (block_io "YM_QA" (output)) - (block_io "YM_QC" (output)) - (block_io "YM_QB" (output)) - (block_io "nSDSEL" (output)) - (block_io "STEP" (output)) - (block_io "MOT_ON" (output)) - (block_io "nRP_LDS" (output)) - (block_io "nRP_UDS" (output)) - (block_io "nROM4" (output)) - (block_io "nROM3" (output)) - (block_io "nCF_CS1" (output)) - (block_io "nCF_CS0" (output)) - (block_io "nIDE_RD" (output)) - (block_io "nIDE_WR" (output)) - (block_io "AMKB_TX" (output)) - (block_io "IDE_RES" (output)) - (block_io "DTR" (output)) - (block_io "RTS" (output)) - (block_io "TxD" (output)) - (block_io "MIDI_OLR" (output)) - (block_io "MIDI_TLR" (output)) - (block_io "nDREQ0" (output)) - (block_io "DSA_D" (output)) - (block_io "nMFP_INT" (output)) - (block_io "FALCON_IO_TA" (output)) - (block_io "STEP_DIR" (output)) - (block_io "WR_DATA" (output)) - (block_io "WR_GATE" (output)) - (block_io "DMA_DRQ" (output)) - (block_io "FB_AD[31..0]" (bidir)) - (block_io "LP_D[7..0]" (bidir)) - (block_io "ACSI_D[7..0]" (bidir)) - (block_io "SCSI_D[7..0]" (bidir)) - (block_io "SCSI_PAR" (bidir)) - (block_io "nSCSI_SEL" (bidir)) - (block_io "nSCSI_BUSY" (bidir)) - (block_io "nSCSI_RST" (bidir)) - (block_io "SD_CD_DATA3" (bidir)) - (block_io "SD_CDM_D1" (bidir)) - (mapper - (pt 0 128) - (bidir) - ) - (mapper - (pt 0 104) - (bidir) - ) - (mapper - (pt 0 56) - (bidir) - ) - (mapper - (pt 0 80) - (bidir) - ) - (mapper - (pt 0 224) - (bidir) - ) - (mapper - (pt 0 248) - (bidir) - ) - (mapper - (pt 0 272) - (bidir) - ) - (mapper - (pt 408 96) - (bidir) - ) - (mapper - (pt 408 120) - (bidir) - ) - (mapper - (pt 408 72) - (bidir) - ) - (mapper - (pt 408 152) - (bidir) - ) - (mapper - (pt 408 200) - (bidir) - ) - (mapper - (pt 408 224) - (bidir) - ) - (mapper - (pt 408 248) - (bidir) - ) - (mapper - (pt 408 272) - (bidir) - ) - (mapper - (pt 408 296) - (bidir) - ) - (mapper - (pt 408 424) - (bidir) - ) - (mapper - (pt 408 352) - (bidir) - ) - (mapper - (pt 408 328) - (bidir) - ) - (mapper - (pt 408 448) - (bidir) - ) - (mapper - (pt 408 400) - (bidir) - ) - (mapper - (pt 408 376) - (bidir) - ) - (mapper - (pt 408 472) - (bidir) - ) - (mapper - (pt 408 496) - (bidir) - ) - (mapper - (pt 408 608) - (bidir) - ) - (mapper - (pt 408 632) - (bidir) - ) - (mapper - (pt 408 528) - (bidir) - ) - (mapper - (pt 408 552) - (bidir) - ) - (mapper - (pt 408 584) - (bidir) - ) - (mapper - (pt 0 624) - (bidir) - ) - (mapper - (pt 0 656) - (bidir) - ) - (mapper - (pt 0 680) - (bidir) - ) - (mapper - (pt 0 704) - (bidir) - ) - (mapper - (pt 0 728) - (bidir) - ) - (mapper - (pt 0 752) - (bidir) - ) - (mapper - (pt 0 776) - (bidir) - ) - (mapper - (pt 408 664) - (bidir) - ) - (mapper - (pt 0 808) - (bidir) - ) - (mapper - (pt 0 832) - (bidir) - ) - (mapper - (pt 408 696) - (bidir) - ) - (mapper - (pt 408 720) - (bidir) - ) - (mapper - (pt 408 744) - (bidir) - ) - (mapper - (pt 408 768) - (bidir) - ) - (mapper - (pt 408 792) - (bidir) - ) - (mapper - (pt 408 816) - (bidir) - ) - (mapper - (pt 408 840) - (bidir) - ) - (mapper - (pt 0 856) - (bidir) - ) - (mapper - (pt 408 872) - (bidir) - ) - (mapper - (pt 408 896) - (bidir) - ) - (mapper - (pt 408 920) - (bidir) - ) - (mapper - (pt 408 944) - (bidir) - ) - (mapper - (pt 0 912) - (bidir) - ) - (mapper - (pt 0 936) - (bidir) - ) - (mapper - (pt 0 960) - (bidir) - ) - (mapper - (pt 0 984) - (bidir) - ) - (mapper - (pt 0 1008) - (bidir) - ) - (mapper - (pt 408 976) - (bidir) - ) - (mapper - (pt 408 1000) - (bidir) - ) - (mapper - (pt 408 1072) - (bidir) - ) - (mapper - (pt 408 1096) - (bidir) - ) - (mapper - (pt 408 1176) - (bidir) - ) - (mapper - (pt 0 296) - (bidir) - ) - (mapper - (pt 408 1256) - (bidir) - ) - (mapper - (pt 0 1040) - (bidir) - ) - (mapper - (pt 0 1064) - (bidir) - ) - (mapper - (pt 0 1088) - (bidir) - ) - (mapper - (pt 0 1112) - (bidir) - ) - (mapper - (pt 0 1136) - (bidir) - ) - (mapper - (pt 0 432) - (bidir) - ) - (mapper - (pt 0 464) - (bidir) - ) - (mapper - (pt 0 488) - (bidir) - ) - (mapper - (pt 0 520) - (bidir) - ) - (mapper - (pt 0 544) - (bidir) - ) - (mapper - (pt 0 568) - (bidir) - ) - (mapper - (pt 0 592) - (bidir) - ) - (mapper - (pt 408 1424) - (bidir) - ) - (mapper - (pt 0 320) - (bidir) - ) - (mapper - (pt 0 200) - (bidir) - ) - (mapper - (pt 0 344) - (bidir) - ) - (mapper - (pt 0 1168) - (bidir) - ) - (mapper - (pt 0 1192) - (bidir) - ) - (mapper - (pt 0 368) - (bidir) - ) - (mapper - (pt 0 392) - (bidir) - ) - (mapper - (pt 0 176) - (bidir) - ) - (mapper - (pt 0 1216) - (bidir) - ) - (mapper - (pt 408 48) - (bidir) - ) - (mapper - (pt 408 16) - (bidir) - ) - (mapper - (pt 0 1240) - (bidir) - ) - (mapper - (pt 408 1304) - (bidir) - ) - (mapper - (pt 408 1200) - (bidir) - ) - (mapper - (pt 408 1344) - (bidir) - ) - (mapper - (pt 408 1280) - (bidir) - ) - (mapper - (pt 408 1224) - (bidir) - ) - (mapper - (pt 408 1120) - (bidir) - ) - (mapper - (pt 408 1048) - (bidir) - ) - (mapper - (pt 408 1024) - (bidir) - ) - (mapper - (pt 0 32) - (bidir) - ) - (mapper - (pt 0 152) - (bidir) - ) - (mapper - (pt 408 1368) - (bidir) - ) - (mapper - (pt 0 1264) - (bidir) - ) - (mapper - (pt 0 1336) - (bidir) - ) - (mapper - (pt 0 888) - (bidir) - ) -) -(block - (rect 1264 2944 1672 3560) - (text "dsp" (rect 5 5 27 18)(font "Arial" (font_size 8))) (text "i_dsp" (rect 5 602 33 613)(font "Arial" )) (block_io "CLK33M" (input)) - (block_io "MAIN_CLK" (input)) - (block_io "nFB_OE" (input)) - (block_io "nFB_WR" (input)) - (block_io "nFB_CS1" (input)) - (block_io "nFB_CS2" (input)) - (block_io "FB_SIZE0" (input)) - (block_io "FB_SIZE1" (input)) - (block_io "nFB_BURST" (input)) - (block_io "FB_ADR[31..0]" (input)) - (block_io "nRSTO" (input)) - (block_io "nFB_CS3" (input)) - (block_io "nSRCS" (output)) - (block_io "nSRBLE" (output)) - (block_io "nSRBHE" (output)) - (block_io "nSRWE" (output)) - (block_io "nSROE" (output)) - (block_io "DSP_INT" (output)) - (block_io "DSP_TA" (output)) - (block_io "FB_AD[31..0]" (bidir)) - (block_io "IO[17..0]" (bidir)) - (block_io "SRD[15..0]" (bidir)) - (mapper - (pt 408 416) - (bidir) - ) - (mapper - (pt 408 392) - (bidir) - ) - (mapper - (pt 408 368) - (bidir) - ) - (mapper - (pt 408 320) - (bidir) - ) - (mapper - (pt 408 440) - (bidir) - ) - (mapper - (pt 408 344) - (bidir) - ) - (mapper - (pt 408 296) - (bidir) - ) - (mapper - (pt 408 40) - (bidir) - ) - (mapper - (pt 0 56) - (bidir) - ) - (mapper - (pt 0 80) - (bidir) - ) - (mapper - (pt 0 104) - (bidir) - ) - (mapper - (pt 0 128) - (bidir) - ) - (mapper - (pt 0 152) - (bidir) - ) - (mapper - (pt 0 176) - (bidir) - ) - (mapper - (pt 0 248) - (bidir) - ) - (mapper - (pt 0 224) - (bidir) - ) - (mapper - (pt 0 272) - (bidir) - ) - (mapper - (pt 0 296) - (bidir) - ) - (mapper - (pt 408 72) - (bidir) - ) - (mapper - (pt 408 576) - (bidir) - ) - (mapper - (pt 0 320) - (bidir) - ) - (mapper - (pt 0 200) - (bidir) - ) -) -(connector - (text "FB_AD[31..0]" (rect 1682 776 1748 787)(font "Arial" )) - (pt 1832 792) - (pt 1672 792) - (bus) -) -(connector - (text "FB_ADR[31..0]" (rect 1146 1072 1220 1083)(font "Arial" )) - (pt 1112 1088) - (pt 1264 1088) - (bus) -) -(connector - (text "MAIN_CLK" (rect 1162 784 1219 795)(font "Arial" )) - (pt 1152 800) - (pt 1264 800) -) -(connector - (text "CLK2M" (rect 1202 808 1240 819)(font "Arial" )) - (pt 1192 824) - (pt 1264 824) -) -(connector - (text "CLK500k" (rect 1202 832 1249 843)(font "Arial" )) - (pt 1192 848) - (pt 1264 848) -) -(connector - (text "LP_DIR" (rect 1682 848 1722 859)(font "Arial" )) - (pt 1672 864) - (pt 1832 864) -) -(connector - (text "LP_STR" (rect 1682 824 1725 835)(font "Arial" )) - (pt 1672 840) - (pt 1832 840) -) -(connector - (text "nACSI_ACK" (rect 1682 928 1745 939)(font "Arial" )) - (pt 1672 944) - (pt 1832 944) -) -(connector - (text "nACSI_RESET" (rect 1682 952 1758 963)(font "Arial" )) - (pt 1672 968) - (pt 1832 968) -) -(connector - (text "nACSI_CS" (rect 1682 976 1737 987)(font "Arial" )) - (pt 1672 992) - (pt 1832 992) -) -(connector - (text "ACSI_DIR" (rect 1682 1000 1733 1011)(font "Arial" )) - (pt 1672 1016) - (pt 1832 1016) -) -(connector - (text "ACSI_A1" (rect 1682 1024 1728 1035)(font "Arial" )) - (pt 1672 1040) - (pt 1832 1040) -) -(connector - (text "nSCSI_ATN" (rect 1682 1128 1742 1139)(font "Arial" )) - (pt 1672 1144) - (pt 1840 1144) -) -(connector - (text "SCSI_DIR" (rect 1682 1152 1733 1163)(font "Arial" )) - (pt 1672 1168) - (pt 1840 1168) -) -(connector - (text "nSCSI_RST" (rect 1682 1176 1743 1187)(font "Arial" )) - (pt 1672 1192) - (pt 1840 1192) -) -(connector - (text "nSCSI_SEL" (rect 1680 1200 1740 1211)(font "Arial" )) - (pt 1672 1216) - (pt 1840 1216) -) -(connector - (text "nSCSI_BUSY" (rect 1682 1224 1752 1235)(font "Arial" )) - (pt 1672 1240) - (pt 1840 1240) -) -(connector - (text "TxD" (rect 1682 1312 1704 1323)(font "Arial" )) - (pt 1672 1328) - (pt 1840 1328) -) -(connector - (text "RTS" (rect 1682 1336 1705 1347)(font "Arial" )) - (pt 1672 1352) - (pt 1840 1352) -) -(connector - (text "DTR" (rect 1680 1360 1704 1371)(font "Arial" )) - (pt 1672 1376) - (pt 1848 1376) -) -(connector - (text "IDE_RES" (rect 1682 1424 1730 1435)(font "Arial" )) - (pt 1672 1440) - (pt 1848 1440) -) -(connector - (text "nIDE_CS0" (rect 1682 1448 1736 1459)(font "Arial" )) - (pt 1672 1464) - (pt 1848 1464) -) -(connector - (text "nIDE_CS1" (rect 1682 1472 1735 1483)(font "Arial" )) - (pt 1672 1488) - (pt 1856 1488) -) -(connector - (text "nIDE_WR" (rect 1682 1496 1732 1507)(font "Arial" )) - (pt 1672 1512) - (pt 1848 1512) -) -(connector - (text "nIDE_RD" (rect 1682 1520 1730 1531)(font "Arial" )) - (pt 1672 1536) - (pt 1848 1536) -) -(connector - (text "nCF_CS0" (rect 1682 1544 1731 1555)(font "Arial" )) - (pt 1672 1560) - (pt 1848 1560) -) -(connector - (text "nCF_CS1" (rect 1682 1568 1730 1579)(font "Arial" )) - (pt 1672 1584) - (pt 1848 1584) -) -(connector - (text "nSDSEL" (rect 1682 1848 1725 1859)(font "Arial" )) - (pt 1672 1864) - (pt 1856 1864) -) -(connector - (text "nDREQ0" (rect 1682 2152 1728 2163)(font "Arial" )) - (pt 1672 2168) - (pt 1856 2168) -) -(connector - (text "SD_CLK" (rect 1682 2032 1728 2043)(font "Arial" )) - (pt 1856 2048) - (pt 1672 2048) -) -(connector - (text "FB_ADR[31..0]" (rect 1146 2536 1220 2547)(font "Arial" )) - (pt 1112 2552) - (pt 1264 2552) - (bus) -) -(connector - (text "nFB_WR" (rect 1162 2416 1208 2427)(font "Arial" )) - (pt 1152 2432) - (pt 1264 2432) -) -(connector - (text "nFB_CS1" (rect 1154 2440 1202 2451)(font "Arial" )) - (pt 1152 2456) - (pt 1264 2456) -) -(connector - (text "FB_SIZE0" (rect 1154 2488 1205 2499)(font "Arial" )) - (pt 1152 2504) - (pt 1264 2504) -) -(connector - (text "FB_SIZE1" (rect 1154 2512 1204 2523)(font "Arial" )) - (pt 1152 2528) - (pt 1264 2528) -) -(connector - (text "MAIN_CLK" (rect 1162 2368 1219 2379)(font "Arial" )) - (pt 1152 2384) - (pt 1264 2384) -) -(connector - (text "nFB_CS2" (rect 1162 2464 1211 2475)(font "Arial" )) - (pt 1152 2480) - (pt 1264 2480) -) (connector (text "FB_AD[31..0]" (rect 1682 2384 1748 2395)(font "Arial" )) (pt 1832 2400) @@ -4540,84 +4457,66 @@ applicable agreement for further details. (bus) ) (connector - (text "nSCSI_ACK" (rect 1682 1104 1745 1115)(font "Arial" )) - (pt 1672 1120) - (pt 1840 1120) + (text "FB_AD[31..0]" (rect 1682 8 1748 19)(font "Arial" )) + (pt 1832 24) + (pt 1672 24) + (bus) ) (connector - (text "SCSI_PAR" (rect 1682 1080 1738 1091)(font "Arial" )) - (pt 1672 1096) - (pt 1840 1096) + (text "FB_ADR[31..0]" (rect 1146 328 1220 339)(font "Arial" )) + (pt 1112 344) + (pt 1264 344) + (bus) ) (connector - (text "MIDI_OLR" (rect 1762 1256 1816 1267)(font "Arial" )) - (pt 1672 1272) - (pt 1920 1272) + (text "nFB_WR" (rect 1162 184 1208 195)(font "Arial" )) + (pt 1152 200) + (pt 1264 200) ) (connector - (text "MIDI_TLR" (rect 1770 1280 1821 1291)(font "Arial" )) - (pt 1672 1296) - (pt 1920 1296) + (text "nFB_CS1" (rect 1154 208 1202 219)(font "Arial" )) + (pt 1152 224) + (pt 1264 224) ) (connector - (text "nROM3" (rect 1754 1600 1794 1611)(font "Arial" )) - (pt 1672 1616) - (pt 1920 1616) + (text "FB_SIZE0" (rect 1154 256 1205 267)(font "Arial" )) + (pt 1152 272) + (pt 1264 272) ) (connector - (text "nROM4" (rect 1754 1624 1794 1635)(font "Arial" )) - (pt 1672 1640) - (pt 1920 1640) + (text "FB_SIZE1" (rect 1154 280 1204 291)(font "Arial" )) + (pt 1152 296) + (pt 1264 296) ) (connector - (text "nRP_UDS" (rect 1744 1648 1797 1659)(font "Arial" )) - (pt 1672 1664) - (pt 1920 1664) + (text "nFB_CS2" (rect 1162 232 1211 243)(font "Arial" )) + (pt 1152 248) + (pt 1264 248) ) (connector - (text "nRP_LDS" (rect 1746 1672 1796 1683)(font "Arial" )) - (pt 1672 1688) - (pt 1920 1688) + (text "nBLANK" (rect 1682 184 1726 195)(font "Arial" )) + (pt 1672 200) + (pt 1832 200) ) (connector - (text "YM_QA" (rect 1762 1904 1803 1915)(font "Arial" )) - (pt 1672 1920) - (pt 1928 1920) + (text "nSYNC" (rect 1682 208 1720 219)(font "Arial" )) + (pt 1672 224) + (pt 1832 224) ) (connector - (text "YM_QB" (rect 1762 1928 1802 1939)(font "Arial" )) - (pt 1672 1944) - (pt 1928 1944) + (text "nFB_CS3" (rect 1186 352 1235 363)(font "Arial" )) + (pt 1264 368) + (pt 1176 368) ) (connector - (text "YM_QC" (rect 1762 1952 1803 1963)(font "Arial" )) - (pt 1672 1968) - (pt 1928 1968) + (text "nPD_VGA" (rect 1682 256 1736 267)(font "Arial" )) + (pt 1672 272) + (pt 1832 272) ) (connector - (text "SD_CARD_DEDECT" (rect 1138 1840 1244 1851)(font "Arial" )) - (pt 1264 1856) - (pt 1128 1856) -) -(connector - (text "SD_CD_DATA3" (rect 1682 1984 1762 1995)(font "Arial" )) - (pt 1672 2000) - (pt 1856 2000) -) -(connector - (text "SD_CDM_D1" (rect 1682 2008 1749 2019)(font "Arial" )) - (pt 1672 2024) - (pt 1856 2024) -) -(connector - (text "DSA_D" (rect 1682 1704 1720 1715)(font "Arial" )) - (pt 1672 1720) - (pt 1856 1720) -) -(connector - (text "nRSTO" (rect 1170 1120 1208 1131)(font "Arial" )) - (pt 1264 1136) - (pt 1160 1136) + (text "PIC_INT" (rect 1162 2584 1205 2595)(font "Arial" )) + (pt 1152 2600) + (pt 1264 2600) ) (connector (text "nIRQ[7..2]" (rect 1682 2408 1732 2419)(font "Arial" )) @@ -4626,14 +4525,29 @@ applicable agreement for further details. (bus) ) (connector - (text "CLK2M4576" (rect 1202 856 1264 867)(font "Arial" )) - (pt 1192 872) - (pt 1264 872) + (text "nFB_OE" (rect 1170 160 1213 171)(font "Arial" )) + (pt 1264 176) + (pt 1160 176) ) (connector - (text "nFB_OE" (rect 1170 2392 1213 2403)(font "Arial" )) - (pt 1264 2408) - (pt 1160 2408) + (text "nPCI_INTA" (rect 1162 2728 1221 2739)(font "Arial" )) + (pt 1152 2744) + (pt 1264 2744) +) +(connector + (text "nPCI_INTB" (rect 1162 2704 1219 2715)(font "Arial" )) + (pt 1152 2720) + (pt 1264 2720) +) +(connector + (text "nPCI_INTC" (rect 1162 2680 1219 2691)(font "Arial" )) + (pt 1152 2696) + (pt 1264 2696) +) +(connector + (text "nPCI_INTD" (rect 1162 2656 1219 2667)(font "Arial" )) + (pt 1152 2672) + (pt 1264 2672) ) (connector (text "nMFP_INT" (rect 1162 2760 1217 2771)(font "Arial" )) @@ -4641,9 +4555,96 @@ applicable agreement for further details. (pt 1264 2776) ) (connector - (text "nMFP_INT" (rect 1682 2072 1737 2083)(font "Arial" )) - (pt 1672 2088) - (pt 1784 2088) + (text "E0_INT" (rect 1162 2608 1200 2619)(font "Arial" )) + (pt 1152 2624) + (pt 1264 2624) +) +(connector + (text "FB_AD[31..0]" (rect 1682 2968 1748 2979)(font "Arial" )) + (pt 1832 2984) + (pt 1672 2984) + (bus) +) +(connector + (text "FB_ADR[31..0]" (rect 1146 3224 1220 3235)(font "Arial" )) + (pt 1112 3240) + (pt 1264 3240) + (bus) +) +(connector + (text "MAIN_CLK" (rect 1162 3008 1219 3019)(font "Arial" )) + (pt 1152 3024) + (pt 1264 3024) +) +(connector + (text "CLK33M" (rect 1210 2984 1254 2995)(font "Arial" )) + (pt 1200 3000) + (pt 1264 3000) +) +(connector + (text "nFB_WR" (rect 1170 3056 1216 3067)(font "Arial" )) + (pt 1264 3072) + (pt 1160 3072) +) +(connector + (text "nFB_CS1" (rect 1162 3080 1210 3091)(font "Arial" )) + (pt 1264 3096) + (pt 1160 3096) +) +(connector + (text "nFB_CS2" (rect 1170 3104 1219 3115)(font "Arial" )) + (pt 1264 3120) + (pt 1160 3120) +) +(connector + (text "FB_SIZE0" (rect 1162 3152 1213 3163)(font "Arial" )) + (pt 1264 3168) + (pt 1160 3168) +) +(connector + (text "FB_SIZE1" (rect 1162 3176 1212 3187)(font "Arial" )) + (pt 1264 3192) + (pt 1160 3192) +) +(connector + (text "nFB_BURST" (rect 1162 3200 1226 3211)(font "Arial" )) + (pt 1264 3216) + (pt 1160 3216) +) +(connector + (text "nRSTO" (rect 1170 3248 1208 3259)(font "Arial" )) + (pt 1264 3264) + (pt 1160 3264) +) +(connector + (text "nFB_OE" (rect 1170 3032 1213 3043)(font "Arial" )) + (pt 1264 3048) + (pt 1160 3048) +) +(connector + (text "nSRCS" (rect 1682 3272 1720 3283)(font "Arial" )) + (pt 1824 3288) + (pt 1672 3288) +) +(connector + (text "nSRBLE" (rect 1682 3296 1725 3307)(font "Arial" )) + (pt 1824 3312) + (pt 1672 3312) +) +(connector + (text "nSRBHE" (rect 1682 3320 1728 3331)(font "Arial" )) + (pt 1824 3336) + (pt 1672 3336) +) +(connector + (text "nSRWE" (rect 1682 3344 1723 3355)(font "Arial" )) + (pt 1824 3360) + (pt 1672 3360) +) +(connector + (text "nSROE" (rect 1682 3368 1720 3379)(font "Arial" )) + (pt 1824 3384) + (pt 1672 3384) ) (connector (text "DSP_INT" (rect 1130 2832 1178 2843)(font "Arial" )) @@ -4651,39 +4652,117 @@ applicable agreement for further details. (pt 1120 2848) ) (connector - (text "CLK500k" (rect 482 2040 529 2051)(font "Arial" )) - (pt 472 2056) - (pt 544 2056) + (text "DSP_INT" (rect 1682 3000 1730 3011)(font "Arial" )) + (pt 1816 3016) + (pt 1672 3016) ) (connector - (text "SCSI_D[7..0]" (rect 1786 1056 1850 1067)(font "Arial" )) - (pt 1672 1072) - (pt 1936 1072) + (pt 528 2416) + (pt 616 2416) +) +(connector + (text "FB_ALE" (rect 1194 304 1236 315)(font "Arial" )) + (pt 1264 320) + (pt 1184 320) +) +(connector + (text "DDRCLK[3..0]" (rect 1162 136 1232 147)(font "Arial" )) + (pt 1152 152) + (pt 1264 152) (bus) ) (connector - (text "ACSI_D[7..0]" (rect 1754 880 1818 891)(font "Arial" )) - (pt 1672 896) - (pt 1904 896) + (text "DDR_SYNC_66M" (rect 1178 112 1267 123)(font "Arial" )) + (pt 1168 128) + (pt 1264 128) +) +(connector + (text "VD[31..0]" (rect 1682 288 1728 299)(font "Arial" )) + (pt 1672 304) + (pt 2648 304) (bus) ) (connector - (text "LP_D[7..0]" (rect 1810 800 1863 811)(font "Arial" )) - (pt 1672 816) - (pt 1960 816) + (text "VA[12..0]" (rect 1682 312 1728 323)(font "Arial" )) + (pt 1672 328) + (pt 2528 328) (bus) ) +(connector + (text "nVWE" (rect 1682 336 1715 347)(font "Arial" )) + (pt 1672 352) + (pt 2400 352) +) +(connector + (text "nVCAS" (rect 1690 360 1727 371)(font "Arial" )) + (pt 1672 376) + (pt 2304 376) +) +(connector + (text "nVRAS" (rect 1690 384 1727 395)(font "Arial" )) + (pt 1672 400) + (pt 2208 400) +) +(connector + (text "nVCS" (rect 1690 408 1720 419)(font "Arial" )) + (pt 1672 424) + (pt 2040 424) +) +(connector + (text "VCKE" (rect 1690 432 1721 443)(font "Arial" )) + (pt 1672 448) + (pt 1944 448) +) +(connector + (text "VSYNC" (rect 1682 136 1722 147)(font "Arial" )) + (pt 1672 152) + (pt 1832 152) +) +(connector + (text "HSYNC" (rect 1682 160 1722 171)(font "Arial" )) + (pt 1672 176) + (pt 1832 176) +) +(connector + (text "VB[7..0]" (rect 1754 112 1794 123)(font "Arial" )) + (pt 1672 128) + (pt 1912 128) + (bus) +) +(connector + (text "VG[7..0]" (rect 1842 88 1883 99)(font "Arial" )) + (pt 1672 104) + (pt 2000 104) + (bus) +) +(connector + (text "VR[7..0]" (rect 1922 64 1962 75)(font "Arial" )) + (pt 1672 80) + (pt 2080 80) + (bus) +) +(connector + (text "IO[17..0]" (rect 1962 3224 2004 3235)(font "Arial" )) + (pt 1672 3240) + (pt 2104 3240) + (bus) +) +(connector + (text "SRD[15..0]" (rect 1802 3248 1856 3259)(font "Arial" )) + (pt 1672 3264) + (pt 1944 3264) + (bus) +) +(connector + (text "CLK25M" (rect 1202 608 1246 619)(font "Arial" )) + (pt 1192 624) + (pt 1264 624) +) (connector (text "TIMEBASE[17]" (rect 354 2120 428 2131)(font "Arial" )) (pt 440 2136) (pt 344 2136) ) -(connector - (text "TIMEBASE[17..0]" (rect 706 2048 792 2059)(font "Arial" )) - (pt 688 2064) - (pt 808 2064) - (bus) -) (connector (text "HSYNC" (rect 1130 2784 1170 2795)(font "Arial" )) (pt 1264 2800) @@ -4694,16 +4773,6 @@ applicable agreement for further details. (pt 1264 2824) (pt 1120 2824) ) -(connector - (text "VSYNC" (rect 1130 1920 1170 1931)(font "Arial" )) - (pt 1264 1936) - (pt 1120 1936) -) -(connector - (text "HSYNC" (rect 1130 1896 1170 1907)(font "Arial" )) - (pt 1264 1912) - (pt 1120 1912) -) (connector (pt 488 2136) (pt 608 2136) @@ -4719,9 +4788,14 @@ applicable agreement for further details. (pt 1808 2848) ) (connector - (text "FALCON_IO_TA" (rect 1682 744 1766 755)(font "Arial" )) - (pt 1672 760) - (pt 1880 760) + (text "DSP_TA" (rect 1682 3504 1728 3515)(font "Arial" )) + (pt 1672 3520) + (pt 1792 3520) +) +(connector + (text "Video_TA" (rect 1682 696 1732 707)(font "Arial" )) + (pt 1672 712) + (pt 1880 712) ) (connector (text "INT_HANDLER_TA" (rect 1810 728 1909 739)(font "Arial" )) @@ -4754,6 +4828,22 @@ applicable agreement for further details. (pt 2504 760) (pt 2536 760) ) +(connector + (text "MAIN_CLK" (rect 1186 88 1243 99)(font "Arial" )) + (pt 1184 104) + (pt 1264 104) +) +(connector + (text "nRSTO" (rect 1194 40 1232 51)(font "Arial" )) + (pt 1184 56) + (pt 1264 56) +) +(connector + (text "BA[1..0]" (rect 1682 456 1722 467)(font "Arial" )) + (pt 1672 472) + (pt 1832 472) + (bus) +) (connector (text "PIXEL_CLK" (rect 2394 -64 2455 -53)(font "Arial" )) (pt 2384 -48) @@ -4791,6 +4881,11 @@ applicable agreement for further details. (pt 2128 -64) (pt 2136 -64) ) +(connector + (text "PIXEL_CLK" (rect 1682 232 1743 243)(font "Arial" )) + (pt 1744 248) + (pt 1672 248) +) (connector (text "PIXEL_CLK" (rect 2394 184 2455 195)(font "Arial" )) (pt 2384 200) @@ -4825,19 +4920,9 @@ applicable agreement for further details. (pt 2440 160) ) (connector - (text "nBLANK" (rect 1154 1968 1198 1979)(font "Arial" )) - (pt 1264 1984) - (pt 1144 1984) -) -(connector - (text "DSP_INT" (rect 1154 1944 1202 1955)(font "Arial" )) - (pt 1264 1960) - (pt 1144 1960) -) -(connector - (text "STEP_DIR" (rect 1682 1752 1737 1763)(font "Arial" )) - (pt 1672 1768) - (pt 1856 1768) + (text "nFB_CS3" (rect 1170 3128 1219 3139)(font "Arial" )) + (pt 1264 3144) + (pt 1160 3144) ) (connector (pt 1904 1768) @@ -4847,67 +4932,23 @@ applicable agreement for further details. (pt 1904 1816) (pt 2136 1816) ) -(connector - (text "WR_DATA" (rect 1682 1800 1738 1811)(font "Arial" )) - (pt 1672 1816) - (pt 1856 1816) -) (connector (text "DMA_DRQ" (rect 1130 2856 1186 2867)(font "Arial" )) (pt 1264 2872) (pt 1120 2872) ) -(connector - (text "DMA_DRQ" (rect 1682 2096 1738 2107)(font "Arial" )) - (pt 1784 2112) - (pt 1672 2112) -) -(connector - (text "FDC_CLK" (rect 1202 880 1255 891)(font "Arial" )) - (pt 1192 896) - (pt 1264 896) -) -(connector - (text "MOT_ON" (rect 1626 1728 1673 1739)(font "Arial" )) - (pt 1672 1744) - (pt 1800 1744) -) (connector (pt 1848 1744) (pt 2136 1744) ) -(connector - (text "STEP" (rect 1626 1776 1656 1787)(font "Arial" )) - (pt 1672 1792) - (pt 1800 1792) -) (connector (pt 1848 1792) (pt 2136 1792) ) -(connector - (text "WR_GATE" (rect 1690 1824 1746 1835)(font "Arial" )) - (pt 1672 1840) - (pt 1800 1840) -) (connector (pt 1848 1840) (pt 2136 1840) ) -(connector - (text "FB_ALE" (rect 1186 1992 1228 2003)(font "Arial" )) - (pt 1144 2008) - (pt 1264 2008) -) -(connector - (text "AMKB_TX" (rect 1946 1392 2000 1403)(font "Arial" )) - (pt 1672 1408) - (pt 2112 1408) -) -(connector - (pt 440 248) - (pt 400 248) -) (connector (text "FB_AD[31..0]" (rect 370 1352 436 1363)(font "Arial" )) (pt 352 1368) @@ -4925,18 +4966,17 @@ applicable agreement for further details. (pt 368 1384) (pt 464 1384) ) +(connector + (text "FB_ALE" (rect 386 1384 428 1395)(font "Arial" )) + (pt 376 1400) + (pt 464 1400) +) (connector (text "ACP_CONF[31..0]" (rect 1682 2568 1772 2579)(font "Arial" )) (pt 1672 2584) (pt 1832 2584) (bus) ) -(connector - (text "ACP_CONF[31..24]" (rect 1146 2064 1242 2075)(font "Arial" )) - (pt 1136 2080) - (pt 1264 2080) - (bus) -) (connector (text "TIN0" (rect 1682 2624 1707 2635)(font "Arial" )) (pt 1832 2640) @@ -4962,6 +5002,31 @@ applicable agreement for further details. (pt 2424 -80) (pt 2424 -64) ) +(connector + (text "DDRCLK[0]" (rect 762 -296 819 -285)(font "Arial" )) + (pt 752 -280) + (pt 848 -280) +) +(connector + (text "DDRCLK[1]" (rect 762 -272 819 -261)(font "Arial" )) + (pt 752 -256) + (pt 848 -256) +) +(connector + (text "DDRCLK[2]" (rect 762 -248 819 -237)(font "Arial" )) + (pt 752 -232) + (pt 848 -232) +) +(connector + (text "DDRCLK[3]" (rect 762 -224 819 -213)(font "Arial" )) + (pt 752 -208) + (pt 848 -208) +) +(connector + (text "DDR_SYNC_66M" (rect 762 -200 851 -189)(font "Arial" )) + (pt 752 -184) + (pt 848 -184) +) (connector (pt 408 672) (pt 472 672) @@ -5092,23 +5157,69 @@ applicable agreement for further details. (pt 64 544) (pt 192 544) ) +(connector + (text "VR_D[8..0]" (rect 1170 464 1224 475)(font "Arial" )) + (pt 1144 480) + (pt 1264 480) + (bus) +) (connector (text "VDQS[3..0]" (rect 1674 504 1730 515)(font "Arial" )) (pt 2040 544) (pt 1960 544) (bus) ) +(connector + (pt 1672 544) + (pt 1888 544) + (bus) +) +(connector + (pt 1888 544) + (pt 1888 568) + (bus) +) (connector (text "VDM[3..0]" (rect 1682 528 1731 539)(font "Arial" )) (pt 1944 568) (pt 1888 568) (bus) ) +(connector + (pt 1672 520) + (pt 1960 520) + (bus) +) +(connector + (pt 1960 544) + (pt 1960 520) + (bus) +) +(connector + (text "VIDEO_RECONFIG" (rect 1674 560 1774 571)(font "Arial" )) + (pt 1672 576) + (pt 1792 576) +) +(connector + (text "VR_WR" (rect 1698 592 1739 603)(font "Arial" )) + (pt 1672 608) + (pt 1792 608) +) (connector (text "VR_BUSY" (rect 418 496 472 507)(font "Arial" )) (pt 408 512) (pt 480 512) ) +(connector + (text "VR_BUSY" (rect 1170 448 1224 459)(font "Arial" )) + (pt 1144 464) + (pt 1264 464) +) +(connector + (text "VR_RD" (rect 1698 576 1736 587)(font "Arial" )) + (pt 1792 592) + (pt 1672 592) +) (connector (text "nRSTO" (rect -86 680 -48 691)(font "Arial" )) (pt -96 696) @@ -5125,40 +5236,19 @@ applicable agreement for further details. (bus) ) (connector - (text "CLK500k" (rect 802 232 849 243)(font "Arial" )) - (pt 768 248) - (pt 864 248) + (text "CLK48M" (rect 538 552 582 563)(font "Arial" )) + (pt 528 568) + (pt 608 568) ) (connector - (text "CLK2M4576" (rect 802 256 864 267)(font "Arial" )) - (pt 768 272) - (pt 864 272) + (text "CLK_VIDEO" (rect 1162 552 1225 563)(font "Arial" )) + (pt 984 568) + (pt 1264 568) ) (connector - (text "CLK24M576" (rect 802 280 864 291)(font "Arial" )) - (pt 768 296) - (pt 864 296) -) -(connector - (text "nRSTO" (rect 1018 424 1056 435)(font "Arial" )) - (pt 1008 440) - (pt 1096 440) -) -(connector - (pt 768 320) - (pt 872 320) -) -(connector - (pt 872 432) - (pt 944 432) -) -(connector - (pt 840 448) - (pt 944 448) -) -(connector - (pt 872 320) - (pt 872 432) + (text "CLK33M" (rect 1202 584 1246 595)(font "Arial" )) + (pt 1264 600) + (pt 1192 600) ) (connector (text "HSYNC" (rect 2314 -96 2354 -85)(font "Arial" )) @@ -5175,1022 +5265,731 @@ applicable agreement for further details. (pt 1856 -64) ) (connector - (text "FB_AD[31..0]" (rect 1682 2968 1748 2979)(font "Arial" )) - (pt 1832 2984) - (pt 1672 2984) + (text "DVI_INT" (rect 858 2632 901 2643)(font "Arial" )) + (pt 848 2648) + (pt 1264 2648) +) +(connector + (text "MAIN_CLK" (rect 330 -296 387 -285)(font "Arial" )) + (pt 264 -280) + (pt 400 -280) +) +(connector + (pt 400 -280) + (pt 448 -280) +) +(connector + (text "CLK33MDIR" (rect 234 296 297 307)(font "Arial" )) + (pt 224 312) + (pt 288 312) +) +(connector + (pt 800 160) + (pt 400 160) +) +(connector + (text "CLK33M" (rect 858 144 902 155)(font "Arial" )) + (pt 848 160) + (pt 952 160) +) +(connector + (text "FB_AD[31..0]" (rect 1682 776 1748 787)(font "Arial" )) + (pt 1832 792) + (pt 1672 792) (bus) ) (connector - (text "FB_ADR[31..0]" (rect 1146 3224 1220 3235)(font "Arial" )) - (pt 1112 3240) - (pt 1264 3240) + (text "FB_ADR[31..0]" (rect 1146 1072 1220 1083)(font "Arial" )) + (pt 1112 1088) + (pt 1264 1088) (bus) ) (connector - (text "MAIN_CLK" (rect 1162 3008 1219 3019)(font "Arial" )) - (pt 1152 3024) - (pt 1264 3024) + (text "MAIN_CLK" (rect 1162 784 1219 795)(font "Arial" )) + (pt 1152 800) + (pt 1264 800) ) (connector - (text "nFB_WR" (rect 1170 3056 1216 3067)(font "Arial" )) - (pt 1264 3072) - (pt 1160 3072) -) -(connector - (text "nFB_CS1" (rect 1162 3080 1210 3091)(font "Arial" )) - (pt 1264 3096) - (pt 1160 3096) -) -(connector - (text "nFB_CS2" (rect 1170 3104 1219 3115)(font "Arial" )) - (pt 1264 3120) - (pt 1160 3120) -) -(connector - (text "FB_SIZE0" (rect 1162 3152 1213 3163)(font "Arial" )) - (pt 1264 3168) - (pt 1160 3168) -) -(connector - (text "FB_SIZE1" (rect 1162 3176 1212 3187)(font "Arial" )) - (pt 1264 3192) - (pt 1160 3192) -) -(connector - (text "nFB_BURST" (rect 1162 3200 1226 3211)(font "Arial" )) - (pt 1264 3216) - (pt 1160 3216) -) -(connector - (text "nRSTO" (rect 1170 3248 1208 3259)(font "Arial" )) - (pt 1264 3264) - (pt 1160 3264) -) -(connector - (text "nFB_OE" (rect 1170 3032 1213 3043)(font "Arial" )) - (pt 1264 3048) - (pt 1160 3048) -) -(connector - (text "IO[17..0]" (rect 1962 3224 2004 3235)(font "Arial" )) - (pt 2104 3240) - (pt 1672 3240) - (bus) -) -(connector - (text "SRD[15..0]" (rect 1802 3248 1856 3259)(font "Arial" )) - (pt 1944 3264) - (pt 1672 3264) - (bus) -) -(connector - (text "nSRCS" (rect 1682 3272 1720 3283)(font "Arial" )) - (pt 1824 3288) - (pt 1672 3288) -) -(connector - (text "nSRBLE" (rect 1682 3296 1725 3307)(font "Arial" )) - (pt 1824 3312) - (pt 1672 3312) -) -(connector - (text "nSRBHE" (rect 1682 3320 1728 3331)(font "Arial" )) - (pt 1824 3336) - (pt 1672 3336) -) -(connector - (text "nSRWE" (rect 1682 3344 1723 3355)(font "Arial" )) - (pt 1824 3360) - (pt 1672 3360) -) -(connector - (text "nSROE" (rect 1682 3368 1720 3379)(font "Arial" )) - (pt 1824 3384) - (pt 1672 3384) -) -(connector - (text "DSP_INT" (rect 1682 3000 1730 3011)(font "Arial" )) - (pt 1816 3016) - (pt 1672 3016) -) -(connector - (text "DSP_TA" (rect 1682 3504 1728 3515)(font "Arial" )) - (pt 1672 3520) - (pt 1792 3520) -) -(connector - (text "nFB_CS3" (rect 1170 3128 1219 3139)(font "Arial" )) - (pt 1264 3144) - (pt 1160 3144) -) -(connector - (text "MAIN_CLK" (rect 1210 760 1267 771)(font "Arial" )) + (text "CLK33M" (rect 1210 760 1254 771)(font "Arial" )) (pt 1200 776) (pt 1264 776) ) (connector - (text "MAIN_CLK" (rect 1210 2984 1267 2995)(font "Arial" )) - (pt 1200 3000) - (pt 1264 3000) + (text "CLK2M" (rect 1202 808 1240 819)(font "Arial" )) + (pt 1192 824) + (pt 1264 824) ) (connector - (text "DDRCLK[0]" (rect 770 -296 827 -285)(font "Arial" )) - (pt 760 -280) - (pt 856 -280) + (text "CLK500k" (rect 1202 832 1249 843)(font "Arial" )) + (pt 1192 848) + (pt 1264 848) ) (connector - (text "DDRCLK[1]" (rect 770 -272 827 -261)(font "Arial" )) - (pt 760 -256) - (pt 856 -256) + (text "nRSTO" (rect 1170 1120 1208 1131)(font "Arial" )) + (pt 1264 1136) + (pt 1160 1136) ) (connector - (text "DDRCLK[2]" (rect 770 -248 827 -237)(font "Arial" )) - (pt 760 -232) - (pt 856 -232) + (text "CLK2M4576" (rect 1202 856 1264 867)(font "Arial" )) + (pt 1192 872) + (pt 1264 872) ) (connector - (text "DDRCLK[3]" (rect 770 -224 827 -213)(font "Arial" )) - (pt 760 -208) - (pt 856 -208) + (text "nMFP_INT" (rect 1682 2072 1737 2083)(font "Arial" )) + (pt 1672 2088) + (pt 1784 2088) ) (connector - (text "DDR_SYNC_66M" (rect 770 -200 859 -189)(font "Arial" )) - (pt 760 -184) - (pt 856 -184) + (text "VSYNC" (rect 1130 1920 1170 1931)(font "Arial" )) + (pt 1264 1936) + (pt 1120 1936) ) (connector - (text "MAIN_CLK" (rect 338 -296 395 -285)(font "Arial" )) - (pt 272 -280) - (pt 456 -280) + (text "HSYNC" (rect 1130 1896 1170 1907)(font "Arial" )) + (pt 1264 1912) + (pt 1120 1912) ) (connector - (text "FB_AD[31..0]" (rect 1682 16 1748 27)(font "Arial" )) - (pt 1832 32) - (pt 1672 32) + (text "nBLANK" (rect 1154 1968 1198 1979)(font "Arial" )) + (pt 1264 1984) + (pt 1144 1984) +) +(connector + (text "DSP_INT" (rect 1154 1944 1202 1955)(font "Arial" )) + (pt 1264 1960) + (pt 1144 1960) +) +(connector + (text "DMA_DRQ" (rect 1682 2096 1738 2107)(font "Arial" )) + (pt 1784 2112) + (pt 1672 2112) +) +(connector + (text "FDC_CLK" (rect 1202 880 1255 891)(font "Arial" )) + (pt 1192 896) + (pt 1264 896) +) +(connector + (text "FB_ALE" (rect 1186 1992 1228 2003)(font "Arial" )) + (pt 1144 2008) + (pt 1264 2008) +) +(connector + (text "ACP_CONF[31..24]" (rect 1146 2064 1242 2075)(font "Arial" )) + (pt 1136 2080) + (pt 1264 2080) (bus) ) (connector - (text "FB_ADR[31..0]" (rect 1146 336 1220 347)(font "Arial" )) - (pt 1112 352) - (pt 1264 352) - (bus) + (text "LP_STR" (rect 1682 824 1725 835)(font "Arial" )) + (pt 1672 840) + (pt 1832 840) ) (connector - (text "nFB_WR" (rect 1162 192 1208 203)(font "Arial" )) - (pt 1152 208) - (pt 1264 208) + (text "LP_DIR" (rect 1682 848 1722 859)(font "Arial" )) + (pt 1672 864) + (pt 1832 864) ) (connector - (text "nFB_CS1" (rect 1154 216 1202 227)(font "Arial" )) - (pt 1152 232) - (pt 1264 232) -) -(connector - (text "FB_SIZE0" (rect 1154 264 1205 275)(font "Arial" )) - (pt 1152 280) - (pt 1264 280) -) -(connector - (text "FB_SIZE1" (rect 1154 288 1204 299)(font "Arial" )) - (pt 1152 304) - (pt 1264 304) -) -(connector - (text "nFB_CS2" (rect 1162 240 1211 251)(font "Arial" )) - (pt 1152 256) - (pt 1264 256) -) -(connector - (text "nBLANK" (rect 1682 192 1726 203)(font "Arial" )) - (pt 1672 208) - (pt 1832 208) -) -(connector - (pt 1680 80) - (pt 1680 88) - (bus) -) -(connector - (pt 2080 80) - (pt 1680 80) - (bus) -) -(connector - (text "VR[7..0]" (rect 1922 72 1962 83)(font "Arial" )) - (pt 1680 88) - (pt 1672 88) - (bus) -) -(connector - (pt 1688 104) - (pt 1688 112) - (bus) -) -(connector - (pt 2000 104) - (pt 1688 104) - (bus) -) -(connector - (text "VG[7..0]" (rect 1842 96 1883 107)(font "Arial" )) - (pt 1688 112) - (pt 1672 112) - (bus) -) -(connector - (pt 1696 128) - (pt 1696 136) - (bus) -) -(connector - (pt 1912 128) - (pt 1696 128) - (bus) -) -(connector - (text "VB[7..0]" (rect 1754 120 1794 131)(font "Arial" )) - (pt 1696 136) - (pt 1672 136) - (bus) -) -(connector - (pt 1704 224) - (pt 1704 232) -) -(connector - (pt 1832 224) - (pt 1704 224) -) -(connector - (text "nSYNC" (rect 1682 216 1720 227)(font "Arial" )) - (pt 1704 232) - (pt 1672 232) -) -(connector - (pt 1712 272) - (pt 1712 280) -) -(connector - (pt 1832 272) - (pt 1712 272) -) -(connector - (text "nPD_VGA" (rect 1682 264 1736 275)(font "Arial" )) - (pt 1712 280) - (pt 1672 280) -) -(connector - (pt 1720 328) - (pt 1720 336) - (bus) -) -(connector - (pt 2528 328) - (pt 1720 328) - (bus) -) -(connector - (text "VA[12..0]" (rect 1682 320 1728 331)(font "Arial" )) - (pt 1720 336) - (pt 1672 336) - (bus) -) -(connector - (pt 1728 352) - (pt 1728 360) -) -(connector - (pt 2400 352) - (pt 1728 352) -) -(connector - (text "nVWE" (rect 1682 344 1715 355)(font "Arial" )) - (pt 1728 360) - (pt 1672 360) -) -(connector - (pt 1256 368) - (pt 1256 376) -) -(connector - (text "nFB_CS3" (rect 1186 360 1235 371)(font "Arial" )) - (pt 1256 376) - (pt 1264 376) -) -(connector - (text "nFB_OE" (rect 1170 168 1213 179)(font "Arial" )) - (pt 1264 184) - (pt 1160 184) -) -(connector - (text "FB_ALE" (rect 1194 312 1236 323)(font "Arial" )) - (pt 1264 328) - (pt 1184 328) -) -(connector - (text "DDRCLK[3..0]" (rect 1162 144 1232 155)(font "Arial" )) - (pt 1152 160) - (pt 1264 160) - (bus) -) -(connector - (text "DDR_SYNC_66M" (rect 1178 120 1267 131)(font "Arial" )) - (pt 1168 136) - (pt 1264 136) -) -(connector - (pt 1736 304) - (pt 1736 312) - (bus) -) -(connector - (pt 2648 304) - (pt 1736 304) - (bus) -) -(connector - (text "VD[31..0]" (rect 1682 296 1728 307)(font "Arial" )) - (pt 1736 312) - (pt 1672 312) - (bus) -) -(connector - (pt 1744 376) - (pt 1744 384) -) -(connector - (pt 2304 376) - (pt 1744 376) -) -(connector - (text "nVCAS" (rect 1690 368 1727 379)(font "Arial" )) - (pt 1744 384) - (pt 1672 384) -) -(connector - (pt 1752 400) - (pt 1752 408) -) -(connector - (pt 2208 400) - (pt 1752 400) -) -(connector - (text "nVRAS" (rect 1690 392 1727 403)(font "Arial" )) - (pt 1752 408) - (pt 1672 408) -) -(connector - (pt 1760 424) - (pt 1760 432) -) -(connector - (pt 2040 424) - (pt 1760 424) -) -(connector - (text "nVCS" (rect 1690 416 1720 427)(font "Arial" )) - (pt 1760 432) - (pt 1672 432) -) -(connector - (pt 1768 448) - (pt 1768 456) -) -(connector - (pt 1944 448) - (pt 1768 448) -) -(connector - (text "VCKE" (rect 1690 440 1721 451)(font "Arial" )) - (pt 1768 456) - (pt 1672 456) -) -(connector - (text "VSYNC" (rect 1682 144 1722 155)(font "Arial" )) - (pt 1672 160) - (pt 1832 160) -) -(connector - (text "HSYNC" (rect 1682 168 1722 179)(font "Arial" )) - (pt 1672 184) - (pt 1832 184) -) -(connector - (pt 1776 712) - (pt 1776 720) -) -(connector - (pt 1880 712) - (pt 1776 712) -) -(connector - (text "Video_TA" (rect 1682 704 1732 715)(font "Arial" )) - (pt 1776 720) - (pt 1672 720) -) -(connector - (text "MAIN_CLK" (rect 1186 96 1243 107)(font "Arial" )) - (pt 1184 112) - (pt 1264 112) -) -(connector - (text "nRSTO" (rect 1194 48 1232 59)(font "Arial" )) - (pt 1184 64) - (pt 1264 64) -) -(connector - (pt 1784 472) - (pt 1784 480) - (bus) -) -(connector - (pt 1832 472) - (pt 1784 472) - (bus) -) -(connector - (text "BA[1..0]" (rect 1682 464 1722 475)(font "Arial" )) - (pt 1784 480) - (pt 1672 480) - (bus) -) -(connector - (text "PIXEL_CLK" (rect 1682 240 1743 251)(font "Arial" )) - (pt 1744 256) - (pt 1672 256) -) -(connector - (text "VR_D[8..0]" (rect 1170 472 1224 483)(font "Arial" )) - (pt 1144 488) - (pt 1264 488) - (bus) -) -(connector - (pt 1888 552) - (pt 1672 552) - (bus) -) -(connector - (pt 1888 568) - (pt 1888 552) - (bus) -) -(connector - (pt 1960 528) - (pt 1672 528) - (bus) -) -(connector - (pt 1960 544) - (pt 1960 528) - (bus) -) -(connector - (text "VIDEO_RECONFIG" (rect 1674 568 1774 579)(font "Arial" )) - (pt 1672 584) - (pt 1792 584) -) -(connector - (text "VR_WR" (rect 1698 600 1739 611)(font "Arial" )) - (pt 1672 616) - (pt 1792 616) -) -(connector - (text "VR_BUSY" (rect 1170 456 1224 467)(font "Arial" )) - (pt 1144 472) - (pt 1264 472) -) -(connector - (text "VR_RD" (rect 1698 584 1736 595)(font "Arial" )) - (pt 1792 600) - (pt 1672 600) -) -(connector - (pt 1248 568) - (pt 1248 576) -) -(connector - (pt 984 568) - (pt 1248 568) -) -(connector - (text "CLK_VIDEO" (rect 1162 560 1225 571)(font "Arial" )) - (pt 1248 576) - (pt 1264 576) -) -(connector - (text "MAIN_CLK" (rect 1202 592 1259 603)(font "Arial" )) - (pt 1264 608) - (pt 1192 608) -) -(connector - (pt 1264 1264) - (pt 1112 1264) -) -(connector - (text "nSCSI_DRQ" (rect 1114 1248 1177 1259)(font "Arial" )) - (pt 1112 1264) - (pt 1104 1264) -) -(connector - (pt 1104 1336) - (pt 1112 1336) -) -(connector - (text "nSCSI_MSG" (rect 1114 1320 1178 1331)(font "Arial" )) - (pt 1112 1336) - (pt 1264 1336) -) -(connector - (pt 1104 1424) - (pt 1112 1424) -) -(connector - (text "CTS" (rect 1114 1408 1137 1419)(font "Arial" )) - (pt 1112 1424) - (pt 1264 1424) -) -(connector - (pt 1104 1448) - (pt 1112 1448) -) -(connector - (text "RI" (rect 1114 1432 1125 1443)(font "Arial" )) - (pt 1112 1448) - (pt 1264 1448) -) -(connector - (pt 1104 1472) - (pt 1112 1472) -) -(connector - (text "DCD" (rect 1114 1456 1139 1467)(font "Arial" )) - (pt 1112 1472) - (pt 1264 1472) -) -(connector - (pt 1264 1552) - (pt 1112 1552) -) -(connector - (text "IDE_RDY" (rect 1114 1536 1164 1547)(font "Arial" )) - (pt 1112 1552) - (pt 1104 1552) -) -(connector - (pt 1104 1576) - (pt 1112 1576) -) -(connector - (text "IDE_INT" (rect 1114 1560 1157 1571)(font "Arial" )) - (pt 1112 1576) - (pt 1264 1576) -) -(connector - (pt 1104 1600) - (pt 1112 1600) -) -(connector - (text "WP_CF_CARD" (rect 1112 1584 1189 1595)(font "Arial" )) - (pt 1112 1600) - (pt 1264 1600) -) -(connector - (pt 1104 1784) - (pt 1112 1784) -) -(connector - (text "SD_DATA0" (rect 1114 1768 1173 1779)(font "Arial" )) - (pt 1112 1784) - (pt 1264 1784) -) -(connector - (pt 1104 1808) - (pt 1112 1808) -) -(connector - (text "SD_DATA1" (rect 1114 1792 1171 1803)(font "Arial" )) - (pt 1112 1808) - (pt 1264 1808) -) -(connector - (pt 1104 1832) - (pt 1112 1832) -) -(connector - (text "SD_DATA2" (rect 1114 1816 1173 1827)(font "Arial" )) - (pt 1112 1832) - (pt 1264 1832) -) -(connector - (pt 1104 1880) - (pt 1112 1880) -) -(connector - (text "SD_WP" (rect 1114 1864 1155 1875)(font "Arial" )) - (pt 1112 1880) - (pt 1264 1880) -) -(connector - (pt 1264 1176) - (pt 1112 1176) -) -(connector - (text "LP_BUSY" (rect 1114 1160 1165 1171)(font "Arial" )) - (pt 1112 1176) - (pt 1104 1176) -) -(connector - (pt 1024 1208) - (pt 1032 1208) -) -(connector - (text "nACSI_DRQ" (rect 1034 1192 1097 1203)(font "Arial" )) - (pt 1032 1208) - (pt 1264 1208) -) -(connector - (pt 1024 1232) - (pt 1032 1232) -) -(connector - (text "nACSI_INT" (rect 1034 1216 1091 1227)(font "Arial" )) - (pt 1032 1232) - (pt 1264 1232) -) -(connector - (pt 1040 1368) - (pt 1048 1368) -) -(connector - (text "MIDI_IN" (rect 1050 1352 1091 1363)(font "Arial" )) - (pt 1048 1368) - (pt 1264 1368) -) -(connector - (pt 1264 1400) - (pt 1112 1400) -) -(connector - (text "RxD" (rect 1114 1384 1137 1395)(font "Arial" )) - (pt 1112 1400) - (pt 1104 1400) -) -(connector - (pt 1040 1656) - (pt 1048 1656) -) -(connector - (text "nINDEX" (rect 1050 1640 1092 1651)(font "Arial" )) - (pt 1048 1656) - (pt 1264 1656) -) -(connector - (pt 1040 1680) - (pt 1048 1680) -) -(connector - (text "TRACK00" (rect 1050 1664 1100 1675)(font "Arial" )) - (pt 1048 1680) - (pt 1264 1680) -) -(connector - (pt 1040 1704) - (pt 1048 1704) -) -(connector - (text "nWP" (rect 1050 1688 1075 1699)(font "Arial" )) - (pt 1048 1704) - (pt 1264 1704) -) -(connector - (pt 1040 1728) - (pt 1048 1728) -) -(connector - (text "nRD_DATA" (rect 1050 1712 1110 1723)(font "Arial" )) - (pt 1048 1728) - (pt 1264 1728) -) -(connector - (pt 1040 1752) - (pt 1048 1752) -) -(connector - (text "nDCHG" (rect 1050 1736 1090 1747)(font "Arial" )) - (pt 1048 1752) - (pt 1264 1752) -) -(connector - (pt 1104 1288) - (pt 1112 1288) -) -(connector - (text "nSCSI_C_D" (rect 1114 1272 1175 1283)(font "Arial" )) - (pt 1112 1288) - (pt 1264 1288) -) -(connector - (pt 1104 1312) - (pt 1112 1312) -) -(connector - (text "nSCSI_I_O" (rect 1114 1296 1171 1307)(font "Arial" )) - (pt 1112 1312) - (pt 1264 1312) -) -(connector - (pt 1264 944) - (pt 1168 944) + (text "nACSI_ACK" (rect 1682 928 1745 939)(font "Arial" )) + (pt 1672 944) + (pt 1832 944) ) (connector (text "nFB_WR" (rect 1170 928 1216 939)(font "Arial" )) - (pt 1168 944) (pt 1160 944) + (pt 1264 944) ) (connector - (pt 1264 968) - (pt 1168 968) + (text "nACSI_RESET" (rect 1682 952 1758 963)(font "Arial" )) + (pt 1672 968) + (pt 1832 968) ) (connector (text "nFB_CS1" (rect 1162 952 1210 963)(font "Arial" )) - (pt 1168 968) (pt 1160 968) + (pt 1264 968) ) (connector - (pt 1264 992) - (pt 1168 992) + (text "nACSI_CS" (rect 1682 976 1737 987)(font "Arial" )) + (pt 1672 992) + (pt 1832 992) ) (connector (text "nFB_CS2" (rect 1170 976 1219 987)(font "Arial" )) - (pt 1168 992) (pt 1160 992) + (pt 1264 992) ) (connector - (pt 1264 1016) - (pt 1168 1016) + (text "ACSI_DIR" (rect 1682 1000 1733 1011)(font "Arial" )) + (pt 1672 1016) + (pt 1832 1016) ) (connector (text "FB_SIZE0" (rect 1162 1000 1213 1011)(font "Arial" )) - (pt 1168 1016) (pt 1160 1016) + (pt 1264 1016) ) (connector - (pt 1264 1040) - (pt 1168 1040) + (text "ACSI_A1" (rect 1682 1024 1728 1035)(font "Arial" )) + (pt 1672 1040) + (pt 1832 1040) ) (connector (text "FB_SIZE1" (rect 1162 1024 1212 1035)(font "Arial" )) - (pt 1168 1040) (pt 1160 1040) -) -(connector - (pt 1264 1064) - (pt 1168 1064) + (pt 1264 1040) ) (connector (text "nFB_BURST" (rect 1162 1048 1226 1059)(font "Arial" )) - (pt 1168 1064) (pt 1160 1064) + (pt 1264 1064) ) (connector - (pt 1264 1112) - (pt 1168 1112) + (text "SCSI_PAR" (rect 1682 1080 1738 1091)(font "Arial" )) + (pt 1672 1096) + (pt 1840 1096) ) (connector - (text "nDACK0" (rect 1250 1096 1294 1107)(font "Arial" )) - (pt 1168 1112) + (text "nDACK0" (rect 1202 1096 1246 1107)(font "Arial" )) (pt 1160 1112) + (pt 1264 1112) ) (connector - (pt 1152 2600) - (pt 1160 2600) + (text "nSCSI_ACK" (rect 1682 1104 1745 1115)(font "Arial" )) + (pt 1672 1120) + (pt 1840 1120) ) (connector - (text "PIC_INT" (rect 1162 2584 1205 2595)(font "Arial" )) - (pt 1160 2600) - (pt 1264 2600) + (text "nSCSI_ATN" (rect 1682 1128 1742 1139)(font "Arial" )) + (pt 1672 1144) + (pt 1840 1144) ) (connector - (pt 1264 920) - (pt 1168 920) + (text "SCSI_DIR" (rect 1682 1152 1733 1163)(font "Arial" )) + (pt 1672 1168) + (pt 1840 1168) ) (connector - (text "nFB_OE" (rect 1170 904 1213 915)(font "Arial" )) - (pt 1168 920) - (pt 1160 920) + (text "LP_BUSY" (rect 1114 1160 1165 1171)(font "Arial" )) + (pt 1104 1176) + (pt 1264 1176) ) (connector - (pt 1152 2648) - (pt 1160 2648) + (text "nSCSI_RST" (rect 1682 1176 1743 1187)(font "Arial" )) + (pt 1672 1192) + (pt 1840 1192) ) (connector - (text "DVI_INT" (rect 1162 2632 1205 2643)(font "Arial" )) - (pt 1160 2648) - (pt 1264 2648) + (text "nACSI_DRQ" (rect 1034 1192 1097 1203)(font "Arial" )) + (pt 1024 1208) + (pt 1264 1208) ) (connector - (pt 1152 2744) - (pt 1160 2744) + (text "nSCSI_SEL" (rect 1680 1200 1740 1211)(font "Arial" )) + (pt 1672 1216) + (pt 1840 1216) ) (connector - (text "nPCI_INTA" (rect 1162 2728 1221 2739)(font "Arial" )) - (pt 1160 2744) - (pt 1264 2744) + (text "nACSI_INT" (rect 1034 1216 1091 1227)(font "Arial" )) + (pt 1024 1232) + (pt 1264 1232) ) (connector - (pt 1152 2720) - (pt 1160 2720) + (text "nSCSI_BUSY" (rect 1682 1224 1752 1235)(font "Arial" )) + (pt 1672 1240) + (pt 1840 1240) ) (connector - (text "nPCI_INTB" (rect 1162 2704 1219 2715)(font "Arial" )) - (pt 1160 2720) - (pt 1264 2720) + (text "nSCSI_DRQ" (rect 1114 1248 1177 1259)(font "Arial" )) + (pt 1104 1264) + (pt 1264 1264) ) (connector - (pt 1152 2696) - (pt 1160 2696) + (text "nSCSI_C_D" (rect 1114 1272 1175 1283)(font "Arial" )) + (pt 1104 1288) + (pt 1264 1288) ) (connector - (text "nPCI_INTC" (rect 1162 2680 1219 2691)(font "Arial" )) - (pt 1160 2696) - (pt 1264 2696) + (text "nSCSI_I_O" (rect 1114 1296 1171 1307)(font "Arial" )) + (pt 1104 1312) + (pt 1264 1312) ) (connector - (pt 1152 2672) - (pt 1160 2672) + (text "TxD" (rect 1682 1312 1704 1323)(font "Arial" )) + (pt 1672 1328) + (pt 1840 1328) ) (connector - (text "nPCI_INTD" (rect 1162 2656 1219 2667)(font "Arial" )) - (pt 1160 2672) - (pt 1264 2672) + (text "nSCSI_MSG" (rect 1114 1320 1178 1331)(font "Arial" )) + (pt 1104 1336) + (pt 1264 1336) ) (connector - (pt 1152 2624) - (pt 1160 2624) + (text "RTS" (rect 1682 1336 1705 1347)(font "Arial" )) + (pt 1672 1352) + (pt 1840 1352) ) (connector - (text "E0_INT" (rect 1162 2608 1200 2619)(font "Arial" )) - (pt 1160 2624) - (pt 1264 2624) + (text "DTR" (rect 1680 1360 1704 1371)(font "Arial" )) + (pt 1672 1376) + (pt 1848 1376) ) (connector - (pt 528 2416) - (pt 536 2416) + (text "RxD" (rect 1114 1384 1137 1395)(font "Arial" )) + (pt 1104 1400) + (pt 1264 1400) ) (connector - (pt 536 2416) - (pt 616 2416) + (text "AMKB_TX" (rect 1946 1392 2000 1403)(font "Arial" )) + (pt 1672 1408) + (pt 2112 1408) ) (connector - (pt 776 1496) - (pt 784 1496) + (text "CTS" (rect 1114 1408 1137 1419)(font "Arial" )) + (pt 1104 1424) + (pt 1264 1424) ) (connector - (text "AMKB_RX" (rect 786 1480 841 1491)(font "Arial" )) - (pt 784 1496) - (pt 1264 1496) + (text "IDE_RES" (rect 1682 1424 1730 1435)(font "Arial" )) + (pt 1672 1440) + (pt 1848 1440) ) (connector - (pt 776 1520) - (pt 784 1520) + (text "RI" (rect 1114 1432 1125 1443)(font "Arial" )) + (pt 1104 1448) + (pt 1264 1448) +) +(connector + (text "nIDE_CS0" (rect 1682 1448 1736 1459)(font "Arial" )) + (pt 1672 1464) + (pt 1848 1464) +) +(connector + (text "DCD" (rect 1114 1456 1139 1467)(font "Arial" )) + (pt 1104 1472) + (pt 1264 1472) +) +(connector + (text "nIDE_CS1" (rect 1682 1472 1735 1483)(font "Arial" )) + (pt 1672 1488) + (pt 1856 1488) +) +(connector + (text "nIDE_WR" (rect 1682 1496 1732 1507)(font "Arial" )) + (pt 1672 1512) + (pt 1848 1512) ) (connector (text "PIC_AMKB_RX" (rect 786 1504 866 1515)(font "Arial" )) - (pt 784 1520) + (pt 776 1520) (pt 1264 1520) ) (connector - (pt 376 1400) - (pt 384 1400) + (text "nIDE_RD" (rect 1682 1520 1730 1531)(font "Arial" )) + (pt 1672 1536) + (pt 1848 1536) ) (connector - (text "FB_ALE" (rect 386 1384 428 1395)(font "Arial" )) - (pt 384 1400) - (pt 464 1400) + (text "IDE_RDY" (rect 1114 1536 1164 1547)(font "Arial" )) + (pt 1104 1552) + (pt 1264 1552) ) (connector - (pt 1040 1632) - (pt 1048 1632) + (text "nCF_CS0" (rect 1682 1544 1731 1555)(font "Arial" )) + (pt 1672 1560) + (pt 1848 1560) +) +(connector + (text "IDE_INT" (rect 1114 1560 1157 1571)(font "Arial" )) + (pt 1104 1576) + (pt 1264 1576) +) +(connector + (text "nCF_CS1" (rect 1682 1568 1730 1579)(font "Arial" )) + (pt 1672 1584) + (pt 1848 1584) +) +(connector + (text "WP_CF_CARD" (rect 1112 1584 1189 1595)(font "Arial" )) + (pt 1104 1600) + (pt 1264 1600) +) +(connector + (text "nROM3" (rect 1754 1600 1794 1611)(font "Arial" )) + (pt 1672 1616) + (pt 1920 1616) +) +(connector + (text "nROM4" (rect 1754 1624 1794 1635)(font "Arial" )) + (pt 1672 1640) + (pt 1920 1640) +) +(connector + (text "nINDEX" (rect 1050 1640 1092 1651)(font "Arial" )) + (pt 1040 1656) + (pt 1264 1656) +) +(connector + (text "nRP_UDS" (rect 1744 1648 1797 1659)(font "Arial" )) + (pt 1672 1664) + (pt 1920 1664) +) +(connector + (text "TRACK00" (rect 1050 1664 1100 1675)(font "Arial" )) + (pt 1040 1680) + (pt 1264 1680) +) +(connector + (text "nRP_LDS" (rect 1746 1672 1796 1683)(font "Arial" )) + (pt 1672 1688) + (pt 1920 1688) +) +(connector + (text "nWP" (rect 1050 1688 1075 1699)(font "Arial" )) + (pt 1040 1704) + (pt 1264 1704) +) +(connector + (text "DSA_D" (rect 1682 1704 1720 1715)(font "Arial" )) + (pt 1672 1720) + (pt 1856 1720) +) +(connector + (text "nRD_DATA" (rect 1050 1712 1110 1723)(font "Arial" )) + (pt 1040 1728) + (pt 1264 1728) +) +(connector + (text "nDCHG" (rect 1050 1736 1090 1747)(font "Arial" )) + (pt 1040 1752) + (pt 1264 1752) +) +(connector + (text "SD_DATA0" (rect 1114 1768 1173 1779)(font "Arial" )) + (pt 1104 1784) + (pt 1264 1784) +) +(connector + (text "SD_DATA1" (rect 1114 1792 1171 1803)(font "Arial" )) + (pt 1104 1808) + (pt 1264 1808) +) +(connector + (text "SD_DATA2" (rect 1114 1816 1173 1827)(font "Arial" )) + (pt 1104 1832) + (pt 1264 1832) +) +(connector + (text "WR_GATE" (rect 1690 1824 1746 1835)(font "Arial" )) + (pt 1672 1840) + (pt 1800 1840) +) +(connector + (text "SD_CARD_DEDECT" (rect 1138 1840 1244 1851)(font "Arial" )) + (pt 1128 1856) + (pt 1264 1856) +) +(connector + (text "nSDSEL" (rect 1682 1848 1725 1859)(font "Arial" )) + (pt 1672 1864) + (pt 1856 1864) +) +(connector + (text "SD_WP" (rect 1114 1864 1155 1875)(font "Arial" )) + (pt 1104 1880) + (pt 1264 1880) +) +(connector + (text "YM_QA" (rect 1762 1904 1803 1915)(font "Arial" )) + (pt 1672 1920) + (pt 1928 1920) +) +(connector + (text "YM_QB" (rect 1762 1928 1802 1939)(font "Arial" )) + (pt 1672 1944) + (pt 1928 1944) +) +(connector + (text "YM_QC" (rect 1762 1952 1803 1963)(font "Arial" )) + (pt 1672 1968) + (pt 1928 1968) +) +(connector + (text "SD_CD_DATA3" (rect 1682 1984 1762 1995)(font "Arial" )) + (pt 1672 2000) + (pt 1856 2000) +) +(connector + (text "SD_CDM_D1" (rect 1682 2008 1749 2019)(font "Arial" )) + (pt 1672 2024) + (pt 1856 2024) +) +(connector + (text "SD_CLK" (rect 1682 2032 1728 2043)(font "Arial" )) + (pt 1672 2048) + (pt 1856 2048) +) +(connector + (text "nFB_OE" (rect 1170 904 1213 915)(font "Arial" )) + (pt 1160 920) + (pt 1264 920) +) +(connector + (text "LP_D[7..0]" (rect 1810 800 1863 811)(font "Arial" )) + (pt 1672 816) + (pt 1960 816) + (bus) +) +(connector + (text "ACSI_D[7..0]" (rect 1754 880 1818 891)(font "Arial" )) + (pt 1672 896) + (pt 1904 896) + (bus) +) +(connector + (text "SCSI_D[7..0]" (rect 1786 1056 1850 1067)(font "Arial" )) + (pt 1672 1072) + (pt 1936 1072) + (bus) +) +(connector + (text "AMKB_RX" (rect 786 1480 841 1491)(font "Arial" )) + (pt 776 1496) + (pt 1264 1496) +) +(connector + (text "FALCON_IO_TA" (rect 1682 744 1766 755)(font "Arial" )) + (pt 1672 760) + (pt 1880 760) +) +(connector + (text "STEP_DIR" (rect 1682 1752 1737 1763)(font "Arial" )) + (pt 1672 1768) + (pt 1856 1768) +) +(connector + (text "WR_DATA" (rect 1682 1800 1738 1811)(font "Arial" )) + (pt 1672 1816) + (pt 1856 1816) +) +(connector + (text "MOT_ON" (rect 1626 1728 1673 1739)(font "Arial" )) + (pt 1672 1744) + (pt 1800 1744) +) +(connector + (text "STEP" (rect 1626 1776 1656 1787)(font "Arial" )) + (pt 1672 1792) + (pt 1800 1792) ) (connector (text "HD_DD" (rect 1050 1616 1090 1627)(font "Arial" )) - (pt 1048 1632) + (pt 1040 1632) (pt 1264 1632) ) (connector - (pt 336 304) - (pt 344 304) + (pt 400 248) + (pt 440 248) ) (connector - (text "MAIN_CLK" (rect 346 288 403 299)(font "Arial" )) - (pt 344 304) - (pt 400 304) -) -(connector - (pt 1176 368) - (pt 1184 368) -) -(connector - (pt 1184 368) - (pt 1256 368) -) -(connector - (text "CLK2M" (rect 906 -40 944 -29)(font "Arial" )) - (pt 704 -24) - (pt 944 -24) -) -(connector - (text "FDC_CLK" (rect 954 -24 1007 -13)(font "Arial" )) - (pt 704 -8) - (pt 944 -8) -) -(connector - (pt 832 56) - (pt 832 24) -) -(connector - (pt 840 56) - (pt 832 56) -) -(connector - (pt 832 24) - (pt 704 24) -) -(connector - (pt 400 -24) + (pt 400 160) (pt 400 248) ) (connector - (pt 400 248) - (pt 400 304) + (text "nRSTO" (rect 1026 424 1064 435)(font "Arial" )) + (pt 1016 440) + (pt 1104 440) ) (connector - (pt 448 -24) - (pt 400 -24) + (pt 920 432) + (pt 952 432) ) (connector - (text "CLK25M" (rect 1210 616 1254 627)(font "Arial" )) - (pt 1264 632) - (pt 1200 632) + (pt 760 448) + (pt 952 448) ) (connector - (pt 776 8) - (pt 704 8) + (pt 824 440) + (pt 952 440) ) (connector - (text "CLKUSB" (rect 538 552 584 563)(font "Arial" )) - (pt 528 568) - (pt 608 568) + (pt 1120 328) + (pt 920 328) +) +(connector + (pt 920 328) + (pt 920 432) +) +(connector + (pt 1888 2192) + (pt 1888 2176) +) +(connector + (pt 1848 2176) + (pt 1888 2176) +) +(connector + (pt 1848 2176) + (pt 1848 2208) +) +(connector + (pt 1848 2208) + (pt 1864 2208) +) +(connector + (text "CLK2M" (rect 1778 2192 1816 2203)(font "Arial" )) + (pt 1768 2208) + (pt 1848 2208) +) +(connector + (text "FB_ADR[31..0]" (rect 1146 2552 1220 2563)(font "Arial" )) + (pt 1112 2568) + (pt 1264 2568) + (bus) +) +(connector + (text "nFB_WR" (rect 1162 2432 1208 2443)(font "Arial" )) + (pt 1152 2448) + (pt 1264 2448) +) +(connector + (text "nFB_CS1" (rect 1154 2456 1202 2467)(font "Arial" )) + (pt 1152 2472) + (pt 1264 2472) +) +(connector + (text "FB_SIZE0" (rect 1154 2504 1205 2515)(font "Arial" )) + (pt 1152 2520) + (pt 1264 2520) +) +(connector + (text "FB_SIZE1" (rect 1154 2528 1204 2539)(font "Arial" )) + (pt 1152 2544) + (pt 1264 2544) +) +(connector + (text "MAIN_CLK" (rect 1162 2384 1219 2395)(font "Arial" )) + (pt 1152 2400) + (pt 1264 2400) +) +(connector + (text "nFB_CS2" (rect 1162 2480 1211 2491)(font "Arial" )) + (pt 1152 2496) + (pt 1264 2496) +) +(connector + (text "nFB_OE" (rect 1170 2408 1213 2419)(font "Arial" )) + (pt 1264 2424) + (pt 1160 2424) +) +(connector + (text "nRSTO" (rect 1170 2360 1208 2371)(font "Arial" )) + (pt 1264 2376) + (pt 1160 2376) +) +(connector + (pt 1912 2208) + (pt 1960 2208) +) +(connector + (text "MIDI_IN" (rect 1682 2208 1723 2219)(font "Arial" )) + (pt 1672 2224) + (pt 1864 2224) +) +(connector + (text "nDREQ0" (rect 1674 2120 1720 2131)(font "Arial" )) + (pt 1672 2136) + (pt 1800 2136) +) +(connector + (text "MIDI_OLR" (rect 1682 2272 1736 2283)(font "Arial" )) + (pt 1672 2288) + (pt 1920 2288) +) +(connector + (text "MIDI_TLR" (rect 1682 2232 1733 2243)(font "Arial" )) + (pt 1672 2248) + (pt 1832 2248) +) +(connector + (pt 824 440) + (pt 824 296) +) +(connector + (pt 824 296) + (pt 712 296) +) +(connector + (pt 1120 328) + (pt 1120 48) +) +(connector + (pt 400 -16) + (pt 464 -16) +) +(connector + (pt 400 -280) + (pt 400 -16) +) +(connector + (pt 400 -16) + (pt 400 160) +) +(connector + (pt 736 48) + (pt 1120 48) +) +(connector + (text "CLK25M" (rect 802 -32 846 -21)(font "Arial" )) + (pt 736 -16) + (pt 920 -16) +) +(connector + (text "CLK2M" (rect 810 -8 848 3)(font "Arial" )) + (pt 736 0) + (pt 808 0) +) +(connector + (text "CLK500k" (rect 834 8 881 19)(font "Arial" )) + (pt 736 16) + (pt 832 16) +) +(connector + (text "CLK2M4576" (rect 810 24 872 35)(font "Arial" )) + (pt 736 32) + (pt 808 32) +) +(connector + (text "CLK48M" (rect 722 232 766 243)(font "Arial" )) + (pt 712 248) + (pt 808 248) +) +(connector + (text "FDC_CLK" (rect 786 256 839 267)(font "Arial" )) + (pt 712 264) + (pt 784 264) +) +(connector + (text "CLK24M576" (rect 722 272 784 283)(font "Arial" )) + (pt 816 280) + (pt 712 280) +) +(connector + (text "TIMEBASE[17..0]" (rect 706 2056 792 2067)(font "Arial" )) + (pt 688 2072) + (pt 808 2072) + (bus) +) +(connector + (text "CLK500k" (rect 482 2048 529 2059)(font "Arial" )) + (pt 472 2064) + (pt 544 2064) ) (junction (pt 2504 760)) -(junction (pt 400 248)) (junction (pt 1856 -64)) (junction (pt 2424 -80)) -(junction (pt 1112 1264)) -(junction (pt 1112 1336)) -(junction (pt 1112 1424)) -(junction (pt 1112 1448)) -(junction (pt 1112 1472)) -(junction (pt 1112 1552)) -(junction (pt 1112 1576)) -(junction (pt 1112 1600)) -(junction (pt 1112 1784)) -(junction (pt 1112 1808)) -(junction (pt 1112 1832)) -(junction (pt 1112 1880)) -(junction (pt 1112 1176)) -(junction (pt 1032 1208)) -(junction (pt 1032 1232)) -(junction (pt 1048 1368)) -(junction (pt 1112 1400)) -(junction (pt 1048 1656)) -(junction (pt 1048 1680)) -(junction (pt 1048 1704)) -(junction (pt 1048 1728)) -(junction (pt 1048 1752)) -(junction (pt 1112 1288)) -(junction (pt 1112 1312)) -(junction (pt 1168 944)) -(junction (pt 1168 968)) -(junction (pt 1168 992)) -(junction (pt 1168 1016)) -(junction (pt 1168 1040)) -(junction (pt 1168 1064)) -(junction (pt 1168 1112)) -(junction (pt 1160 2600)) -(junction (pt 1168 920)) -(junction (pt 1160 2648)) -(junction (pt 1160 2744)) -(junction (pt 1160 2720)) -(junction (pt 1160 2696)) -(junction (pt 1160 2672)) -(junction (pt 1160 2624)) -(junction (pt 536 2416)) -(junction (pt 784 1496)) -(junction (pt 784 1520)) -(junction (pt 384 1400)) -(junction (pt 1048 1632)) -(junction (pt 344 304)) -(junction (pt 1184 368)) +(junction (pt 400 -280)) +(junction (pt 400 160)) +(junction (pt 1848 2208)) +(junction (pt 400 -16)) diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index f167edb..6be8aa6 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -42,10 +42,10 @@ set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf" # Pin & Location Assignments # ========================== -set_location_assignment PIN_AB12 -to CLK33M set_location_assignment PIN_G2 -to MAIN_CLK set_location_assignment PIN_Y3 -to FB_AD[0] set_location_assignment PIN_Y6 -to FB_AD[1] @@ -319,7 +319,6 @@ set_location_assignment PIN_A20 -to nRD_DATA set_location_assignment PIN_C17 -to nDCHG set_location_assignment PIN_J4 -to nACSI_INT set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_E12 -to MIDI_IN set_location_assignment PIN_G7 -to LP_BUSY set_location_assignment PIN_Y1 -to IDE_RDY set_location_assignment PIN_G22 -to IDE_INT @@ -353,7 +352,7 @@ set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name TOP_LEVEL_ENTITY firebee1 +set_global_assignment -name TOP_LEVEL_ENTITY firebee1 set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED @@ -368,14 +367,14 @@ set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name FITTER_EFFORT "AUTO FIT" set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK set_instance_assignment -name IO_STANDARD "2.5 V" -to VA set_instance_assignment -name IO_STANDARD "2.5 V" -to VD @@ -495,7 +494,7 @@ set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA @@ -513,15 +512,14 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSROE -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M @@ -546,8 +544,6 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # LogicLock Region Assignments # ============================ -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" # end LOGICLOCK_REGION(Root Region) # --------------------------------- @@ -557,76 +553,135 @@ set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" # Incremental Compilation Assignments # =================================== -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top # end DESIGN_PARTITION(Top) # ------------------------- # end ENTITY(firebee1) # -------------------- +set_global_assignment -name MISC_FILE "C:/FireBee/FPGA/firebee1.dpf" set_location_assignment PIN_E5 -to LPDIR set_location_assignment PIN_B11 -to nRSTO_MCF -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name DISABLE_OCP_HW_EVAL ON -set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON - -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE PESSIMISTIC -set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM -set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON -set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 3 -set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.5 -set_global_assignment -name ECO_OPTIMIZE_TIMING ON -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON -set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD +set_location_assignment PIN_AB12 -to CLK33MDIR +set_location_assignment PIN_E12 -to MIDI_IN_PIN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN +set_instance_assignment -name PCI_IO ON -to nPCI_INTA +set_instance_assignment -name PCI_IO ON -to nPCI_INTB +set_instance_assignment -name PCI_IO ON -to nPCI_INTC +set_instance_assignment -name PCI_IO ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] +set_global_assignment -name POWER_USE_TA_VALUE 35 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name BDF_FILE firebee1.bdf set_global_assignment -name SDC_FILE firebee1.sdc -set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf -set_global_assignment -name VHDL_FILE DSP/DSP.vhd set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp @@ -637,12 +692,21 @@ set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd set_global_assignment -name AHDL_FILE Video/VIDEO_MOD_MUX_CLUTCTR.tdf set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name BDF_FILE Video/Video.bdf -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip set_global_assignment -name QIP_FILE Video/altdpram0.qip set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip @@ -656,22 +720,6 @@ set_global_assignment -name QIP_FILE Video/lpm_mux1.qip set_global_assignment -name QIP_FILE Video/lpm_mux2.qip set_global_assignment -name QIP_FILE Video/lpm_constant2.qip set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip set_global_assignment -name QIP_FILE Video/altddio_out0.qip @@ -681,23 +729,46 @@ set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip set_global_assignment -name QIP_FILE Video/altddio_out1.qip set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name BDF_FILE Video/Video.bdf +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd @@ -725,37 +796,35 @@ set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf214 set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip set_global_assignment -name VHDL_FILE lpm_latch0.vhd set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name AHDL_FILE altpll4.tdf -set_global_assignment -name QIP_FILE altpll_reconfig1.qip +set_global_assignment -name VHDL_FILE altpll3.vhd set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name BDF_FILE firebee1.bdf +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip set_global_assignment -name QIP_FILE lpm_counter0.qip set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation - -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll_reconfig1.qip +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index a28e73e..2260426 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -118,14 +118,14 @@ derive_clock_uncertainty # Set Input Delay #************************************************************** -set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.000 [all_inputs] +set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [all_inputs] #************************************************************** # Set Output Delay #************************************************************** -set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.000 [all_outputs] +set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [all_outputs] #************************************************************** @@ -149,17 +149,22 @@ set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pl # MAIN_CLK to DDR clk and v.v. set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] -set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] +set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] +set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] + set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}] - +set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] # 2 MHz to 33 MHz set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}] +set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] +set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {MAIN_CLK}] # 16 MHz to 33 MHz set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}] @@ -168,6 +173,9 @@ set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|al # 25 MHz to 33 MHz set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {MAIN_CLK}] set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] +set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] +set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {MAIN_CLK}] + set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] @@ -178,6 +186,7 @@ set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_genera set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] +set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}] set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}] diff --git a/FPGA_Quartus_13.1/lpm_counter1.qip b/FPGA_Quartus_13.1/lpm_counter1.qip new file mode 100644 index 0000000..2bcc1a0 --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_counter1.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.tdf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter1.cmp"] diff --git a/FPGA_Quartus_13.1/lpm_mux0.qip b/FPGA_Quartus_13.1/lpm_mux0.qip new file mode 100644 index 0000000..b46f6a0 --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_mux0.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.tdf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.cmp"] diff --git a/FPGA_Quartus_13.1/lpm_shiftreg0.qip b/FPGA_Quartus_13.1/lpm_shiftreg0.qip new file mode 100644 index 0000000..7fd6c84 --- /dev/null +++ b/FPGA_Quartus_13.1/lpm_shiftreg0.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG" +set_global_assignment -name IP_TOOL_VERSION "9.1" +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.tdf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.inc"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.cmp"]