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patch with Fredi's lp fix (and others)

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This commit is contained in:
Markus Fröschle
2015-10-26 06:48:18 +00:00
parent 1c661c8052
commit fc8034d93b
43 changed files with 5765 additions and 5956 deletions
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32
FPGA_Quartus_13.1/altpll2.vhd
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@@ -14,11 +14,11 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
@@ -140,8 +140,8 @@ ARCHITECTURE SYN OF altpll2 IS
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
@@ -149,14 +149,14 @@ BEGIN
sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire5 <= sub_wire0(4);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
c3 <= sub_wire4;
c4 <= sub_wire5;
sub_wire6 <= inclk0;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
@@ -293,7 +293,7 @@ END SYN;
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
@@ -459,18 +459,18 @@ END SYN;
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE