ragnar/FPGA_Config
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fix 13MHz clock sdc

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This commit is contained in:
Markus Fröschle
2016-01-17 08:43:20 +00:00
parent 91791dfb5d
commit ddad975d6f
2 changed files with 6 additions and 7 deletions
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FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
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@@ -1486,8 +1486,7 @@ BEGIN
BORDER_COLOR0_clk_ctrl <= MAIN_CLK;
-- $404/4
BORDER_COLOR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2)
= "00000000000000000100000001");
BORDER_COLOR_CS <= to_std_logic(((not nFB_CS2) = '1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000001");
BORDER_COLOR_d <= FB_AD(23 DOWNTO 0);
BORDER_COLOR16_ena_ctrl <= BORDER_COLOR_CS and FB_B(1) and (not nFB_WR);
BORDER_COLOR8_ena_ctrl <= BORDER_COLOR_CS and FB_B(2) and (not nFB_WR);