diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
index 0ea49e4..2cc1649 100755
--- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
+++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
@@ -1486,8 +1486,7 @@ BEGIN
    BORDER_COLOR0_clk_ctrl <= MAIN_CLK;
 
 --  $404/4
-   BORDER_COLOR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2)
-	 = "00000000000000000100000001");
+   BORDER_COLOR_CS <= to_std_logic(((not nFB_CS2) = '1') and FB_ADR(27 DOWNTO 2) = "00000000000000000100000001");
    BORDER_COLOR_d <= FB_AD(23 DOWNTO 0);
    BORDER_COLOR16_ena_ctrl <= BORDER_COLOR_CS and FB_B(1) and (not nFB_WR);
    BORDER_COLOR8_ena_ctrl <= BORDER_COLOR_CS and FB_B(2) and (not nFB_WR);
diff --git a/FPGA_Quartus_13.1/firebee_groups.sdc b/FPGA_Quartus_13.1/firebee_groups.sdc
index 3924ec3..5b43ebc 100644
--- a/FPGA_Quartus_13.1/firebee_groups.sdc
+++ b/FPGA_Quartus_13.1/firebee_groups.sdc
@@ -92,7 +92,7 @@ create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_por
 derive_pll_clocks
 
 create_generated_clock -divide_by 2 -source MAIN_CLK i_video|i_video_mod_mux_clutctr|CLK17M_q
-create_generated_clock -divide_by 2 -source i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[2] i_video|i_video_mod_mux_clutctr|CLK13M_q
+create_generated_clock -divide_by 2 -source i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0] i_video|i_video_mod_mux_clutctr|CLK13M_q
 
 # PIXEL_CLK is either
 # CLK13M, CLK17M, CLK25M, CLK33M or CLK_VIDEO
@@ -121,16 +121,16 @@ derive_clock_uncertainty
 # Set Input Delay
 #**************************************************************
 
-set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [all_inputs]
-set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 0.500 [all_inputs]
+#set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [all_inputs]
+#set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 0.500 [all_inputs]
 
 
 #**************************************************************
 # Set Output Delay
 #**************************************************************
 
-set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_outputs]
-set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 0.500 [all_outputs]
+#set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_outputs]
+#set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 0.500 [all_outputs]
 
 
 #**************************************************************