ragnar/FPGA_Config
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reformatted, forced tighter timing

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Config works, but screen is still scrambled
This commit is contained in:
Markus Fröschle
2015-09-20 17:13:10 +00:00
parent fb3fcdf996
commit bb0f702a45
5 changed files with 125 additions and 105 deletions
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12
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
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@@ -20,12 +20,12 @@
-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
-- Created on Tue Sep 08 16:24:20 2009
library work;
use work.FalconIO_SDCard_IDE_CF_pkg.all;
LIBRARY work;
USE work.FalconIO_SDCard_IDE_CF_pkg.ALL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
-- Entity Declaration
@@ -148,7 +148,7 @@ END falconio_sdcard_ide_cf;
-- Architecture Body
ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS
ARCHITECTURE rtl OF falconio_sdcard_ide_cf IS
-- system
SIGNAL SYS_CLK : std_logic;
SIGNAL RESETn : std_logic;