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multiple driver problem

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This commit is contained in:
Markus Fröschle
2016-04-28 04:34:30 +00:00
parent 761b807e92
commit ba5713a154
4 changed files with 1118 additions and 1136 deletions
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96
FPGA_Quartus_13.1/Video/DDR_CTR.vhd
View File

@@ -281,19 +281,12 @@ architecture rtl of ddr_ctr is
signal v_bash : std_logic_vector(7 downto 0); signal v_bash : std_logic_vector(7 downto 0);
signal v_bash_cs : std_logic; signal v_bash_cs : std_logic;
signal reg_ta : std_logic; signal reg_ta : std_logic := '0';
type flexbus_states is (FR_WAIT, FR_S0, FR_S1, FR_S2, FR_S3);
-- Sub Module Interface Section -- Sub Module Interface Section
-- component lpm_bustri_BYT
-- port
-- (
-- data : in std_logic_vector(7 downto 0);
-- enabledt : in std_logic;
-- tridata : buffer std_logic_vector(7 downto 0)
-- );
-- end component lpm_bustri_BYT;
function to_std_logic(X : in boolean) return std_logic is function to_std_logic(X : in boolean) return std_logic is
variable ret : std_logic; variable ret : std_logic;
begin begin
@@ -578,45 +571,45 @@ begin
end if; end if;
end process; end process;
i_vbasx : work.flexbus_register -- i_vbasx : work.flexbus_register
generic map -- generic map
( -- (
reg_width => 2, -- reg_width => 2,
match_address => x"ffff8603", -- match_address => x"ffff8603",
match_mask => x"0000ffff", -- byte register -- match_mask => x"0000ffff", -- byte register
match_fbcs => 1 -- match_fbcs => 1
) -- )
port map -- port map
( -- (
clk => clk33m, -- clk => clk33m,
fb_addr => fb_adr, -- fb_addr => fb_adr,
fb_data => fb_ad, -- fb_data => fb_ad,
fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1), -- fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1),
fb_ta_n => reg_ta, -- fb_ta_n => reg_ta,
fb_wr_n => nfb_wr, -- fb_wr_n => nfb_wr,
reg_value => v_basx, -- reg_value => v_basx,
cs => v_basx_cs -- cs => v_basx_cs
); -- );
--
i_vbash : work.flexbus_register -- i_vbash : work.flexbus_register
generic map -- generic map
( -- (
reg_width => 8, -- reg_width => 8,
match_address => x"ffff8604", -- match_address => x"ffff8604",
match_mask => x"0000fffe", -- byte register -- match_mask => x"0000fffe", -- byte register
match_fbcs => 1 -- match_fbcs => 1
) -- )
port map -- port map
( -- (
clk => clk33m, -- clk => clk33m,
fb_addr => fb_adr, -- fb_addr => fb_adr,
fb_data => fb_ad, -- fb_data => fb_ad,
fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1), -- fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1),
fb_ta_n => reg_ta, -- fb_ta_n => V,
fb_wr_n => nfb_wr, -- fb_wr_n => nfb_wr,
reg_value => v_bash, -- reg_value => v_bash,
cs => v_bash_cs -- cs => v_bash_cs
); -- );
-- Start of original equations -- Start of original equations
line <= fb_size0 and fb_size1; line <= fb_size0 and fb_size1;
@@ -654,6 +647,7 @@ begin
bus_cyc_end <= '0'; bus_cyc_end <= '0';
stdVec3 := FB_REGDDR_q; stdVec3 := FB_REGDDR_q;
case stdVec3 is case stdVec3 is
when "000" => when "000" =>
FB_LE(0) <= not nFB_WR; FB_LE(0) <= not nFB_WR;
@@ -718,7 +712,7 @@ begin
end if; end if;
when others => when others =>
video_ddr_ta <= '0';
end case; end case;
stdVec3 := (others => '0'); -- no storage needed stdVec3 := (others => '0'); -- no storage needed
end process; end process;

113
FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
View File

@@ -545,7 +545,7 @@ begin
HBE <= HBE_q; HBE <= HBE_q;
HSS <= HSS_q; HSS <= HSS_q;
VCO <= VCO_q; VCO <= VCO_q;
VCNTRL <= VCNTRL_q; VCNTRL <= VCNTRL_d;
VSYNC <= VSYNC_q; VSYNC <= VSYNC_q;
nBLANK <= nBLANK_q; nBLANK <= nBLANK_q;
@@ -1269,47 +1269,82 @@ begin
-- - REGISTER OUT -- - REGISTER OUT
-- low word register access -- low word register access
u0_data <= (sizeIt(ST_SHIFT_MODE_CS,16) and std_logic_vector'("000000" & ST_SHIFT_MODE_q & "00000000")) or -- u0_data <= (sizeIt(ST_SHIFT_MODE_CS,16) and std_logic_vector'("000000" & ST_SHIFT_MODE_q & "00000000")) or
(sizeIt(FALCON_SHIFT_MODE_CS,16) and std_logic_vector'("00000" & FALCON_SHIFT_MODE_q)) or -- (sizeIt(FALCON_SHIFT_MODE_CS,16) and std_logic_vector'("00000" & FALCON_SHIFT_MODE_q)) or
(sizeIt(SYS_CTR_CS,16) and std_logic_vector'("100000000" & SYS_CTR_q(6 downto 4) & (not BLITTER_RUN) & SYS_CTR_q(2 downto 0))) or -- (sizeIt(SYS_CTR_CS,16) and std_logic_vector'("100000000" & SYS_CTR_q(6 downto 4) & (not BLITTER_RUN) & SYS_CTR_q(2 downto 0))) or
(sizeIt(LOF_CS,16) and LOF_q) or (sizeIt(LWD_CS,16) and LWD_q) or -- (sizeIt(LOF_CS,16) and LOF_q) or (sizeIt(LWD_CS,16) and LWD_q) or
(sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or -- (sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or
(sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or -- (sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or
(sizeIt(HDE_CS,16) and std_logic_vector'("0000" & HDE_q)) or -- (sizeIt(HDE_CS,16) and std_logic_vector'("0000" & HDE_q)) or
(sizeIt(HBB_CS,16) and std_logic_vector'("0000" & HBB_q)) or -- (sizeIt(HBB_CS,16) and std_logic_vector'("0000" & HBB_q)) or
(sizeIt(HSS_CS,16) and std_logic_vector'("0000" & HSS_q)) or -- (sizeIt(HSS_CS,16) and std_logic_vector'("0000" & HSS_q)) or
(sizeIt(HHT_CS,16) and std_logic_vector'("0000" & HHT_q)) or -- (sizeIt(HHT_CS,16) and std_logic_vector'("0000" & HHT_q)) or
(sizeIt(VBE_CS,16) and std_logic_vector'("00000" & VBE_q)) or -- (sizeIt(VBE_CS,16) and std_logic_vector'("00000" & VBE_q)) or
(sizeIt(VDB_CS,16) and std_logic_vector'("00000" & VDB_q)) or -- (sizeIt(VDB_CS,16) and std_logic_vector'("00000" & VDB_q)) or
(sizeIt(VDE_CS,16) and std_logic_vector'("00000" & VDE_q)) or -- (sizeIt(VDE_CS,16) and std_logic_vector'("00000" & VDE_q)) or
(sizeIt(VBB_CS,16) and std_logic_vector'("00000" & VBB_q)) or -- (sizeIt(VBB_CS,16) and std_logic_vector'("00000" & VBB_q)) or
(sizeIt(VSS_CS,16) and std_logic_vector'("00000" & VSS_q)) or -- (sizeIt(VSS_CS,16) and std_logic_vector'("00000" & VSS_q)) or
(sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or -- (sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or
(sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or -- (sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or
(sizeIt(VCNTRL_CS,16) and std_logic_vector'("000000000000" & VCNTRL_q)) or -- (sizeIt(VCNTRL_CS,16) and std_logic_vector'("000000000000" & VCNTRL_q)) or
(sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(31 downto 16)) or -- (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(31 downto 16)) or
(sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 downto 16)) or -- (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 downto 16)) or
(sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 downto 16)) or -- (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 downto 16)) or
(sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(31 downto 16)) or -- (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(31 downto 16)) or
(sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 downto 16)) or -- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 downto 16)) or
(sizeIt(BORDER_COLOR_CS,16) and std_logic_vector'("00000000" & BORDER_COLOR_q(23 downto 16))) or -- (sizeIt(BORDER_COLOR_CS,16) and std_logic_vector'("00000000" & BORDER_COLOR_q(23 downto 16))) or
(sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & VR_DOUT_q)) or -- (sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & VR_DOUT_q)) or
(sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(VR_BUSY & "0000" & VR_WR_q & VR_RD & VIDEO_RECONFIG_q & "11111010")); -- (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(VR_BUSY & "0000" & VR_WR_q & VR_RD & VIDEO_RECONFIG_q & "11111010"));
u0_enabledt <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or BORDER_COLOR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or FB_AD(31 downto 16) <= "000000" & st_shift_mode_q & "00000000" when st_shift_mode_cs = '1' else
HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or "100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0) when sys_ctr_cs = '1' else
VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS) and (not nFB_OE); lwd_q when lof_cs = '1' and lwd_cs = '1' else
FB_AD(31 downto 16) <= u0_tridata; "0000" & hbe_q when hbe_cs = '1' else
"0000" & hdb_q when hdb_cs = '1' else
"0000" & hde_q when hde_cs = '1' else
"0000" & hbb_q when hbb_cs = '1' else
"0000" & hss_q when hss_cs = '1' else
"0000" & hht_q when hht_cs = '1' else
"00000" & vbe_q when vbe_cs = '1' else
"00000" & vdb_q when vdb_cs = '1' else
"00000" & vde_q when vde_cs = '1' else
"00000" & vbb_q when vbb_cs = '1' else
"00000" & vss_q when vss_cs = '1' else
"00000" & vft_q when vft_cs = '1' else
"0000000" & vco_q when vco_cs = '1' else
"000000000000" & vcntrl_q when vcntrl_cs = '1' else
acp_vctr_q(31 downto 16) when acp_vctr_cs = '1' else
atari_hh_q(31 downto 16) when atari_hh_cs = '1' else
atari_vh_q(31 downto 16) when atari_vh_cs = '1' else
atari_hl_q(31 downto 16) when atari_hl_cs = '1' else
atari_vl_q(31 downto 16) when atari_vl_cs = '1' else
"00000000" & border_color_q(23 downto 16) when border_color_cs = '1' else
"0000000" & vr_dout_q when video_pll_config_cs = '1' else
vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs else
(others => 'Z');
-- u0_enabledt <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or BORDER_COLOR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or
-- HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or
-- VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS) and (not nFB_OE);
-- FB_AD(31 downto 16) <= u0_tridata;
-- high word register access -- high word register access
u1_data <= (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(15 downto 0)) or -- u1_data <= (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(15 downto 0)) or
(sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(15 downto 0)) or -- (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(15 downto 0)) or
(sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(15 downto 0)) or -- (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(15 downto 0)) or
(sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(15 downto 0)) or -- (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(15 downto 0)) or
(sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 downto 0)) or -- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 downto 0)) or
(sizeIt(BORDER_COLOR_CS,16) and BORDER_COLOR_q(15 downto 0)); -- (sizeIt(BORDER_COLOR_CS,16) and BORDER_COLOR_q(15 downto 0));
u1_enabledt <= (ACP_VCTR_CS or BORDER_COLOR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); -- u1_enabledt <= (ACP_VCTR_CS or BORDER_COLOR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE);
FB_AD(15 downto 0) <= u1_tridata; -- FB_AD(15 downto 0) <= u1_tridata;
fb_ad(15 downto 0) <= acp_vctr_q(15 downto 0) when acp_vctr_cs = '1' else
atari_hh_q(15 downto 0) when atari_hh_cs = '1' else
atari_vh_q(15 downto 0) when atari_vh_cs = '1' else
atari_hl_q(15 downto 0) when atari_hl_cs = '1' else
atari_vl_q(15 downto 0) when atari_vl_cs = '1' else
border_color_q(15 downto 0) when border_color_cs = '1' else
(others => 'Z');
video_mod_ta <= clut_ta_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or video_mod_ta <= clut_ta_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or
HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or

555
FPGA_Quartus_13.1/firebee1.vhd
View File

@@ -7,293 +7,246 @@ LIBRARY altera;
LIBRARY work; LIBRARY work;
ENTITY firebee1 IS ENTITY firebee1 IS
PORT port
( (
FB_ALE : IN std_logic; FB_ALE : in std_logic;
nFB_WR : IN std_logic; nFB_WR : in std_logic;
nFB_CS1 : IN std_logic; nFB_CS1 : in std_logic;
nFB_CS2 : IN std_logic; nFB_CS2 : in std_logic;
nFB_CS3 : IN std_logic; nFB_CS3 : in std_logic;
FB_SIZE0 : IN std_logic; FB_SIZE0 : in std_logic;
FB_SIZE1 : IN std_logic; FB_SIZE1 : in std_logic;
nFB_BURST : IN std_logic; nFB_BURST : in std_logic;
LP_BUSY : IN std_logic; LP_BUSY : in std_logic;
nACSI_DRQ : IN std_logic; nACSI_DRQ : in std_logic;
nACSI_INT : IN std_logic; nACSI_INT : in std_logic;
RxD : IN std_logic; RxD : in std_logic;
CTS : IN std_logic; CTS : in std_logic;
RI : IN std_logic; RI : in std_logic;
DCD : IN std_logic; DCD : in std_logic;
AMKB_RX : IN std_logic; AMKB_RX : in std_logic;
PIC_AMKB_RX : IN std_logic; PIC_AMKB_RX : in std_logic;
IDE_RDY : IN std_logic; IDE_RDY : in std_logic;
IDE_INT : IN std_logic; IDE_INT : in std_logic;
WP_CF_CARD : IN std_logic; WP_CF_CARD : in std_logic;
TRACK00 : IN std_logic; TRACK00 : in std_logic;
nWP : IN std_logic; nWP : in std_logic;
nDCHG : IN std_logic; nDCHG : in std_logic;
SD_DATA0 : IN std_logic; SD_DATA0 : in std_logic;
SD_DATA1 : IN std_logic; SD_DATA1 : in std_logic;
SD_DATA2 : IN std_logic; SD_DATA2 : in std_logic;
SD_CARD_DEDECT : IN std_logic; SD_CARD_DEDECT : in std_logic;
nSCSI_DRQ : IN std_logic; nSCSI_DRQ : in std_logic;
SD_WP : IN std_logic; SD_WP : in std_logic;
nRD_DATA : IN std_logic; nRD_DATA : in std_logic;
nSCSI_C_D : IN std_logic; nSCSI_C_D : in std_logic;
nSCSI_I_O : IN std_logic; nSCSI_I_O : in std_logic;
nSCSI_MSG : IN std_logic; nSCSI_MSG : in std_logic;
nDACK0 : IN std_logic; nDACK0 : in std_logic;
PIC_INT : IN std_logic; PIC_INT : in std_logic;
nFB_OE : IN std_logic; nFB_OE : in std_logic;
TOUT0 : IN std_logic; TOUT0 : in std_logic;
nMASTER : IN std_logic; nMASTER : in std_logic;
DVI_INT : IN std_logic; DVI_INT : in std_logic;
nDACK1 : IN std_logic; nDACK1 : in std_logic;
nPCI_INTD : IN std_logic; nPCI_INTD : in std_logic;
nPCI_INTC : IN std_logic; nPCI_INTC : in std_logic;
nPCI_INTB : IN std_logic; nPCI_INTB : in std_logic;
nPCI_INTA : IN std_logic; nPCI_INTA : in std_logic;
E0_INT : IN std_logic; E0_INT : in std_logic;
nINDEX : IN std_logic; nINDEX : in std_logic;
HD_DD : IN std_logic; HD_DD : in std_logic;
MAIN_CLK : IN std_logic; MAIN_CLK : in std_logic;
nRSTO_MCF : IN std_logic; nRSTO_MCF : in std_logic;
CLK33MDIR : IN std_logic; CLK33MDIR : in std_logic;
SCSI_PAR : INOUT std_logic; SCSI_PAR : inout std_logic;
nSCSI_RST : INOUT std_logic; nSCSI_RST : inout std_logic;
nSCSI_SEL : INOUT std_logic; nSCSI_SEL : inout std_logic;
nSCSI_BUSY : INOUT std_logic; nSCSI_BUSY : inout std_logic;
SD_CD_DATA3 : INOUT std_logic; SD_CD_DATA3 : inout std_logic;
SD_CMD_D1 : INOUT std_logic; SD_CMD_D1 : inout std_logic;
MIDI_IN_PIN : INOUT std_logic; MIDI_IN_PIN : inout std_logic;
ACSI_D : INOUT std_logic_vector(7 DOWNTO 0); ACSI_D : inout std_logic_vector(7 downto 0);
FB_AD : INOUT std_logic_vector(31 DOWNTO 0); FB_AD : inout std_logic_vector(31 downto 0);
IO : INOUT std_logic_vector(17 DOWNTO 0); IO : inout std_logic_vector(17 downto 0);
LP_D : INOUT std_logic_vector(7 DOWNTO 0); LP_D : inout std_logic_vector(7 downto 0);
SCSI_D : INOUT std_logic_vector(7 DOWNTO 0); SCSI_D : inout std_logic_vector(7 downto 0);
SRD : INOUT std_logic_vector(15 DOWNTO 0); SRD : inout std_logic_vector(15 downto 0);
VD : INOUT std_logic_vector(31 DOWNTO 0); VD : inout std_logic_vector(31 downto 0);
VDQS : INOUT std_logic_vector(3 DOWNTO 0); VDQS : inout std_logic_vector(3 downto 0);
LP_STR : OUT std_logic; LP_STR : out std_logic;
nACSI_ACK : OUT std_logic; nACSI_ACK : out std_logic;
nACSI_RESET : OUT std_logic; nACSI_RESET : out std_logic;
nACSI_CS : OUT std_logic; nACSI_CS : out std_logic;
ACSI_DIR : OUT std_logic; ACSI_DIR : out std_logic;
ACSI_A1 : OUT std_logic; ACSI_A1 : out std_logic;
nSCSI_ACK : OUT std_logic; nSCSI_ACK : out std_logic;
nSCSI_ATN : OUT std_logic; nSCSI_ATN : out std_logic;
SCSI_DIR : OUT std_logic; SCSI_DIR : out std_logic;
MIDI_TLR : OUT std_logic; MIDI_TLR : out std_logic;
TxD : OUT std_logic; TxD : out std_logic;
RTS : OUT std_logic; RTS : out std_logic;
DTR : OUT std_logic; DTR : out std_logic;
AMKB_TX : OUT std_logic; AMKB_TX : out std_logic;
IDE_RES : OUT std_logic; IDE_RES : out std_logic;
nIDE_CS0 : OUT std_logic; nIDE_CS0 : out std_logic;
nIDE_CS1 : OUT std_logic; nIDE_CS1 : out std_logic;
nIDE_WR : OUT std_logic; nIDE_WR : out std_logic;
nIDE_RD : OUT std_logic; nIDE_RD : out std_logic;
nCF_CS0 : OUT std_logic; nCF_CS0 : out std_logic;
nCF_CS1 : OUT std_logic; nCF_CS1 : out std_logic;
nROM3 : OUT std_logic; nROM3 : out std_logic;
nROM4 : OUT std_logic; nROM4 : out std_logic;
nRP_UDS : OUT std_logic; nRP_UDS : out std_logic;
nRP_LDS : OUT std_logic; nRP_LDS : out std_logic;
nSDSEL : OUT std_logic; nSDSEL : out std_logic;
nWR_GATE : OUT std_logic; nWR_GATE : out std_logic;
nWR : OUT std_logic; nWR : out std_logic;
YM_QA : OUT std_logic; YM_QA : out std_logic;
YM_QB : OUT std_logic; YM_QB : out std_logic;
YM_QC : OUT std_logic; YM_QC : out std_logic;
SD_CLK : OUT std_logic; SD_CLK : out std_logic;
DSA_D : OUT std_logic; DSA_D : out std_logic;
nVWE : OUT std_logic; nVWE : out std_logic;
nVCAS : OUT std_logic; nVCAS : out std_logic;
nVRAS : OUT std_logic; nVRAS : out std_logic;
nVCS : OUT std_logic; nVCS : out std_logic;
nPD_VGA : OUT std_logic; nPD_VGA : out std_logic;
TIN0 : OUT std_logic; TIN0 : out std_logic;
nSRCS : OUT std_logic; nSRCS : out std_logic;
nSRBLE : OUT std_logic; nSRBLE : out std_logic;
nSRBHE : OUT std_logic; nSRBHE : out std_logic;
nSRWE : OUT std_logic; nSRWE : out std_logic;
nDREQ1 : OUT std_logic; nDREQ1 : out std_logic;
LED_FPGA_OK : OUT std_logic; LED_FPGA_OK : out std_logic;
nSROE : OUT std_logic; nSROE : out std_logic;
VCKE : OUT std_logic; VCKE : out std_logic;
nFB_TA : OUT std_logic; nFB_TA : out std_logic;
nDDR_CLK : OUT std_logic; nDDR_CLK : out std_logic;
DDR_CLK : OUT std_logic; DDR_CLK : out std_logic;
VSYNC_PAD : OUT std_logic; VSYNC_PAD : out std_logic;
HSYNC_PAD : OUT std_logic; HSYNC_PAD : out std_logic;
nBLANK_PAD : OUT std_logic; nBLANK_PAD : out std_logic;
PIXEL_CLK_PAD : OUT std_logic; PIXEL_CLK_PAD : out std_logic;
nSYNC : OUT std_logic; nSYNC : out std_logic;
nMOT_ON : OUT std_logic; nMOT_ON : out std_logic;
nSTEP_DIR : OUT std_logic; nSTEP_DIR : out std_logic;
nSTEP : OUT std_logic; nSTEP : out std_logic;
LPDIR : OUT std_logic; LPDIR : out std_logic;
MIDI_OLR : OUT std_logic; MIDI_OLR : out std_logic;
CLK25M : OUT std_logic; CLK25M : out std_logic;
CLKUSB : OUT std_logic; CLKUSB : out std_logic;
CLK24M576 : OUT std_logic; CLK24M576 : out std_logic;
BA : OUT std_logic_vector(1 DOWNTO 0); BA : out std_logic_vector(1 downto 0);
nIRQ : OUT std_logic_vector(7 DOWNTO 2); nIRQ : out std_logic_vector(7 downto 2);
VA : OUT std_logic_vector(12 DOWNTO 0); VA : out std_logic_vector(12 downto 0);
VB : OUT std_logic_vector(7 DOWNTO 0); VB : out std_logic_vector(7 downto 0);
VDM : OUT std_logic_vector(3 DOWNTO 0); VDM : out std_logic_vector(3 downto 0);
VG : OUT std_logic_vector(7 DOWNTO 0); VG : out std_logic_vector(7 downto 0);
VR : OUT std_logic_vector(7 DOWNTO 0) VR : out std_logic_vector(7 downto 0)
); );
END firebee1; end firebee1;
ARCHITECTURE rtl OF firebee1 IS architecture rtl OF firebee1 IS
SIGNAL ACP_CONF : std_logic_vector(31 DOWNTO 0); signal ACP_CONF : std_logic_vector(31 downto 0);
SIGNAL clk25m_i : std_logic; signal clk25m_i : std_logic;
SIGNAL CLK2M : std_logic; signal CLK2M : std_logic;
SIGNAL CLK2M4576 : std_logic; signal CLK2M4576 : std_logic;
SIGNAL CLK33M : std_logic; signal CLK33M : std_logic;
SIGNAL CLK48M : std_logic; signal CLK48M : std_logic;
SIGNAL CLK500k : std_logic; signal CLK500k : std_logic;
SIGNAL CLK_VIDEO : std_logic; signal CLK_VIDEO : std_logic;
SIGNAL DDR_SYNC_66M : std_logic; signal DDR_SYNC_66M : std_logic;
SIGNAL DDRCLK : std_logic_vector(3 DOWNTO 0); signal DDRCLK : std_logic_vector(3 downto 0);
SIGNAL DMA_DRQ : std_logic; signal DMA_DRQ : std_logic;
SIGNAL DSP_INT : std_logic; signal DSP_INT : std_logic;
SIGNAL DSP_TA : std_logic; signal DSP_TA : std_logic;
SIGNAL FALCON_IO_TA : std_logic; signal FALCON_IO_TA : std_logic;
SIGNAL FB_ADR : std_logic_vector(31 DOWNTO 0); signal FB_ADR : std_logic_vector(31 downto 0);
SIGNAL FDC_CLK : std_logic; signal FDC_CLK : std_logic;
SIGNAL HSYNC : std_logic; signal HSYNC : std_logic;
SIGNAL INT_HANDLER_TA : std_logic; signal INT_HANDLER_TA : std_logic;
SIGNAL LP_DIR : std_logic; signal LP_DIR : std_logic;
SIGNAL MIDI_IN : std_logic; signal MIDI_IN : std_logic;
SIGNAL MOT_ON : std_logic; signal MOT_ON : std_logic;
SIGNAL nBLANK : std_logic; signal nBLANK : std_logic;
SIGNAL nDREQ0 : std_logic; signal nDREQ0 : std_logic;
SIGNAL nMFP_INT : std_logic; signal nMFP_INT : std_logic;
SIGNAL nRSTO : std_logic; signal nRSTO : std_logic;
SIGNAL PIXEL_CLK : std_logic; signal PIXEL_CLK : std_logic;
SIGNAL SD_CDM_D1 : std_logic; signal SD_CDM_D1 : std_logic;
SIGNAL STEP : std_logic; signal STEP : std_logic;
SIGNAL STEP_DIR : std_logic; signal STEP_DIR : std_logic;
SIGNAL TIMEBASE : std_logic_vector(17 DOWNTO 0); signal TIMEBASE : std_logic_vector(17 downto 0);
SIGNAL VIDEO_RECONFIG : std_logic; signal VIDEO_RECONFIG : std_logic;
SIGNAL Video_TA : std_logic; signal Video_TA : std_logic;
SIGNAL VR_BUSY : std_logic; signal VR_BUSY : std_logic;
SIGNAL VR_D : std_logic_vector(8 DOWNTO 0); signal VR_D : std_logic_vector(8 downto 0);
SIGNAL VR_RD : std_logic; signal VR_RD : std_logic;
SIGNAL VR_WR : std_logic; signal VR_WR : std_logic;
SIGNAL VSYNC : std_logic; signal VSYNC : std_logic;
SIGNAL WR_DATA : std_logic; signal WR_DATA : std_logic;
SIGNAL WR_GATE : std_logic; signal WR_GATE : std_logic;
SIGNAL scandataout : std_logic; signal scandataout : std_logic;
SIGNAL scandone : std_logic; signal scandone : std_logic;
SIGNAL reset : std_logic; signal reset : std_logic;
SIGNAL pll_reset : std_logic; signal pll_reset : std_logic;
SIGNAL scanclk : std_logic; signal scanclk : std_logic;
SIGNAL scandata : std_logic; signal scandata : std_logic;
SIGNAL scan_clkena : std_logic; signal scan_clkena : std_logic;
SIGNAL config_update : std_logic; signal config_update : std_logic;
SIGNAL pll3_locked : std_logic; signal pll3_locked : std_logic;
SIGNAL pll1_locked : std_logic; signal pll1_locked : std_logic;
SIGNAL nSRCS_i : std_logic; signal nSRCS_i : std_logic;
SIGNAL nFB_WR_i : std_logic; signal nFB_WR_i : std_logic;
SIGNAL nIDE_RD_i : std_logic; signal nIDE_RD_i : std_logic;
SIGNAL nIDE_WR_i : std_logic; signal nIDE_WR_i : std_logic;
COMPONENT altpll_reconfig1 component altpll_reconfig1
PORT port
( (
clock : IN std_logic ; clock : in std_logic ;
counter_param : IN std_logic_vector (2 DOWNTO 0); counter_param : in std_logic_vector (2 downto 0);
counter_type : IN std_logic_vector (3 DOWNTO 0); counter_type : in std_logic_vector (3 downto 0);
data_in : IN std_logic_vector (8 DOWNTO 0); data_in : in std_logic_vector (8 downto 0);
pll_areset_in : IN std_logic := '0'; pll_areset_in : in std_logic := '0';
pll_scandataout : IN std_logic ; pll_scandataout : in std_logic ;
pll_scandone : IN std_logic ; pll_scandone : in std_logic ;
read_param : IN std_logic ; read_param : in std_logic ;
reconfig : IN std_logic ; reconfig : in std_logic ;
reset : IN std_logic ; reset : in std_logic ;
write_param : IN std_logic ; write_param : in std_logic ;
busy : OUT std_logic ; busy : out std_logic ;
data_out : OUT std_logic_vector (8 DOWNTO 0); data_out : out std_logic_vector (8 downto 0);
pll_areset : OUT std_logic ; pll_areset : out std_logic ;
pll_configupdate : OUT std_logic ; pll_configupdate : out std_logic ;
pll_scanclk : OUT std_logic ; pll_scanclk : out std_logic ;
pll_scanclkena : OUT std_logic ; pll_scanclkena : out std_logic ;
pll_scandata : OUT std_logic pll_scandata : out std_logic
); );
END COMPONENT altpll_reconfig1; end component altpll_reconfig1;
COMPONENT altpll4 component altpll4
PORT port
( (
areset : IN std_logic := '0'; areset : in std_logic := '0';
configupdate : IN std_logic := '0'; configupdate : in std_logic := '0';
inclk0 : IN std_logic := '0'; inclk0 : in std_logic := '0';
scanclk : IN std_logic := '1'; scanclk : in std_logic := '1';
scanclkena : IN std_logic := '0'; scanclkena : in std_logic := '0';
scandata : IN std_logic := '0'; scandata : in std_logic := '0';
c0 : OUT std_logic ; c0 : out std_logic;
locked : OUT std_logic ; locked : out std_logic;
scandataout : OUT std_logic ; scandataout : out std_logic;
scandone : OUT std_logic scandone : out std_logic
); );
END COMPONENT altpll4; end component altpll4;
-- COMPONENT video begin
-- PORT
-- (
-- FB_ADR : IN std_logic_vector(31 DOWNTO 0);
-- MAIN_CLK : IN std_logic;
-- nFB_CS1 : IN std_logic;
-- nFB_CS2 : IN std_logic;
-- nFB_CS3 : IN std_logic;
-- nFB_WR : IN std_logic;
-- FB_SIZE0 : IN std_logic;
-- FB_SIZE1 : IN std_logic;
-- nRSTO : IN std_logic;
-- nFB_OE : IN std_logic;
-- FB_ALE : IN std_logic;
-- DDRCLK : IN std_logic_vector(3 DOWNTO 0);
-- DDR_SYNC_66M : IN std_logic;
-- CLK33M : IN std_logic;
-- CLK25M : IN std_logic;
-- CLK_VIDEO : IN std_logic;
-- VR_D : IN std_logic_vector(8 DOWNTO 0);
-- VR_BUSY : IN std_logic;
-- VG : OUT std_logic_vector(7 DOWNTO 0);
-- VB : OUT std_logic_vector(7 DOWNTO 0);
-- VR : OUT std_logic_vector(7 DOWNTO 0);
-- nBLANK : OUT std_logic;
-- VA : OUT std_logic_vector(12 DOWNTO 0);
-- nVWE : OUT std_logic;
-- nVCAS : OUT std_logic;
-- nVRAS : OUT std_logic;
-- nVCS : OUT std_logic;
-- VDM : OUT std_logic_vector(3 DOWNTO 0);
-- nPD_VGA : OUT std_logic;
-- VCKE : OUT std_logic;
-- VSYNC : OUT std_logic;
-- HSYNC : OUT std_logic;
-- nSYNC : OUT std_logic;
-- VIDEO_TA : OUT std_logic;
-- PIXEL_CLK : OUT std_logic;
-- BA : OUT std_logic_vector(1 DOWNTO 0);
-- VIDEO_RECONFIG : OUT std_logic;
-- VR_WR : OUT std_logic;
-- VR_RD : OUT std_logic;
-- VDQS : INOUT std_logic_vector(3 DOWNTO 0);
-- FB_AD : INOUT std_logic_vector(31 DOWNTO 0);
-- VD : INOUT std_logic_vector(31 DOWNTO 0)
-- );
-- END COMPONENT video;
BEGIN
nDREQ1 <= nDACK1; nDREQ1 <= nDACK1;
i_atari_clk_pll : work.altpll3 i_atari_clk_pll : work.altpll3
PORT MAP port map
( (
inclk0 => MAIN_CLK, inclk0 => MAIN_CLK,
c0 => clk25m_i, c0 => clk25m_i,
@@ -305,7 +258,7 @@ BEGIN
i_ddr_clk_pll : work.altpll2 i_ddr_clk_pll : work.altpll2
PORT MAP port map
( (
inclk0 => MAIN_CLK, inclk0 => MAIN_CLK,
c0 => DDRCLK(0), c0 => DDRCLK(0),
@@ -317,7 +270,7 @@ BEGIN
i_dsp : work.dsp i_dsp : work.dsp
PORT MAP port map
( (
CLK33M => CLK33M, CLK33M => CLK33M,
MAIN_CLK => MAIN_CLK, MAIN_CLK => MAIN_CLK,
@@ -345,7 +298,7 @@ BEGIN
i_falcioio_sdcard_ide_cf : work.falconio_sdcard_ide_cf i_falcioio_sdcard_ide_cf : work.falconio_sdcard_ide_cf
PORT MAP port map
( (
CLK33M => CLK33M, CLK33M => CLK33M,
MAIN_CLK => MAIN_CLK, MAIN_CLK => MAIN_CLK,
@@ -402,7 +355,7 @@ BEGIN
nSCSI_RST => nSCSI_RST, nSCSI_RST => nSCSI_RST,
SD_CD_DATA3 => SD_CD_DATA3, SD_CD_DATA3 => SD_CD_DATA3,
SD_CDM_D1 => SD_CDM_D1, SD_CDM_D1 => SD_CDM_D1,
ACP_CONF => ACP_CONF(31 DOWNTO 24), ACP_CONF => ACP_CONF(31 downto 24),
ACSI_D => ACSI_D, ACSI_D => ACSI_D,
FB_AD => FB_AD, FB_AD => FB_AD,
FB_ADR => FB_ADR, FB_ADR => FB_ADR,
@@ -453,7 +406,7 @@ BEGIN
i_interrupt_handler : work.interrupt_handler i_interrupt_handler : work.interrupt_handler
PORT MAP port map
( (
MAIN_CLK => MAIN_CLK, MAIN_CLK => MAIN_CLK,
nFB_WR => nFB_WR, nFB_WR => nFB_WR,
@@ -485,7 +438,7 @@ BEGIN
i_mfp_acia_clk_pll : work.altpll1 i_mfp_acia_clk_pll : work.altpll1
PORT MAP port map
( (
inclk0 => MAIN_CLK, inclk0 => MAIN_CLK,
c0 => CLK48M, c0 => CLK48M,
@@ -496,7 +449,7 @@ BEGIN
i_pll_reconfig : altpll_reconfig1 i_pll_reconfig : altpll_reconfig1
PORT MAP port map
( (
reconfig => VIDEO_RECONFIG, reconfig => VIDEO_RECONFIG,
read_param => VR_RD, read_param => VR_RD,
@@ -506,9 +459,9 @@ BEGIN
pll_scandone => scandone, pll_scandone => scandone,
clock => MAIN_CLK, clock => MAIN_CLK,
reset => reset, reset => reset,
counter_param => FB_ADR(8 DOWNTO 6), counter_param => FB_ADR(8 downto 6),
counter_type => FB_ADR(5 DOWNTO 2), counter_type => FB_ADR(5 downto 2),
data_in => FB_AD(24 DOWNTO 16), data_in => FB_AD(24 downto 16),
busy => VR_BUSY, busy => VR_BUSY,
pll_scandata => scandata, pll_scandata => scandata,
pll_scanclk => scanclk, pll_scanclk => scanclk,
@@ -520,7 +473,7 @@ BEGIN
i_video : entity work.video i_video : entity work.video
PORT MAP port map
( (
MAIN_CLK => MAIN_CLK, MAIN_CLK => MAIN_CLK,
nFB_CS1 => nFB_CS1, nFB_CS1 => nFB_CS1,
@@ -568,7 +521,7 @@ BEGIN
i_video_clk_pll : altpll4 i_video_clk_pll : altpll4
PORT MAP port map
( (
inclk0 => CLK48M, inclk0 => CLK48M,
areset => pll_reset, areset => pll_reset,
@@ -583,7 +536,7 @@ BEGIN
inst1 : work.lpm_ff0 inst1 : work.lpm_ff0
PORT MAP port map
( (
clock => DDR_SYNC_66M, clock => DDR_SYNC_66M,
enable => FB_ALE, enable => FB_ALE,
@@ -591,13 +544,13 @@ BEGIN
q => FB_ADR q => FB_ADR
); );
nMOT_ON <= NOT(MOT_ON); nMOT_ON <= not(MOT_ON);
nSTEP_DIR <= NOT(STEP_DIR); nSTEP_DIR <= not(STEP_DIR);
nSTEP <= NOT(STEP); nSTEP <= not(STEP);
nWR <= NOT(WR_DATA); nWR <= not(WR_DATA);
inst18 : work.lpm_counter0 inst18 : work.lpm_counter0
PORT MAP port map
( (
clock => CLK500k, clock => CLK500k,
q => TIMEBASE q => TIMEBASE
@@ -610,11 +563,11 @@ BEGIN
CLK33M <= MAIN_CLK; CLK33M <= MAIN_CLK;
reset <= NOT(nRSTO); reset <= not(nRSTO);
nRSTO <= pll3_locked AND pll1_locked AND nRSTO_MCF; nRSTO <= pll3_locked and pll1_locked and nRSTO_MCF;
inst29 : alt_iobuf inst29 : alt_iobuf
PORT MAP port map
( (
i => CLK2M, i => CLK2M,
oe => CLK2M, oe => CLK2M,
@@ -624,10 +577,10 @@ BEGIN
LED_FPGA_OK <= TIMEBASE(17); LED_FPGA_OK <= TIMEBASE(17);
nDDR_CLK <= NOT(DDRCLK(0)); nDDR_CLK <= not(DDRCLK(0));
inst5 : work.altddio_out3 inst5 : work.altddio_out3
PORT MAP port map
( (
datain_h => VSYNC, datain_h => VSYNC,
datain_l => VSYNC, datain_l => VSYNC,
@@ -637,7 +590,7 @@ BEGIN
inst6 : work.altddio_out3 inst6 : work.altddio_out3
PORT MAP port map
( (
datain_h => HSYNC, datain_h => HSYNC,
datain_l => HSYNC, datain_l => HSYNC,
@@ -647,7 +600,7 @@ BEGIN
inst8 : work.altddio_out3 inst8 : work.altddio_out3
PORT MAP port map
( (
datain_h => nBLANK, datain_h => nBLANK,
datain_l => nBLANK, datain_l => nBLANK,
@@ -656,7 +609,7 @@ BEGIN
); );
inst9 : work.altddio_out3 inst9 : work.altddio_out3
PORT MAP port map
( (
datain_h => '0', datain_h => '0',
datain_l => '1', datain_l => '1',
@@ -673,4 +626,4 @@ BEGIN
nIDE_RD <= nIDE_RD_i; nIDE_RD <= nIDE_RD_i;
nIDE_WR <= nIDE_WR_i; nIDE_WR <= nIDE_WR_i;
END rtl; end rtl;