diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index c005a60..742660f 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -281,19 +281,12 @@ architecture rtl of ddr_ctr is signal v_bash : std_logic_vector(7 downto 0); signal v_bash_cs : std_logic; - signal reg_ta : std_logic; + signal reg_ta : std_logic := '0'; + + type flexbus_states is (FR_WAIT, FR_S0, FR_S1, FR_S2, FR_S3); + -- Sub Module Interface Section - --- component lpm_bustri_BYT --- port --- ( --- data : in std_logic_vector(7 downto 0); --- enabledt : in std_logic; --- tridata : buffer std_logic_vector(7 downto 0) --- ); --- end component lpm_bustri_BYT; - function to_std_logic(X : in boolean) return std_logic is variable ret : std_logic; begin @@ -578,45 +571,45 @@ begin end if; end process; - i_vbasx : work.flexbus_register - generic map - ( - reg_width => 2, - match_address => x"ffff8603", - match_mask => x"0000ffff", -- byte register - match_fbcs => 1 - ) - port map - ( - clk => clk33m, - fb_addr => fb_adr, - fb_data => fb_ad, - fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1), - fb_ta_n => reg_ta, - fb_wr_n => nfb_wr, - reg_value => v_basx, - cs => v_basx_cs - ); - - i_vbash : work.flexbus_register - generic map - ( - reg_width => 8, - match_address => x"ffff8604", - match_mask => x"0000fffe", -- byte register - match_fbcs => 1 - ) - port map - ( - clk => clk33m, - fb_addr => fb_adr, - fb_data => fb_ad, - fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1), - fb_ta_n => reg_ta, - fb_wr_n => nfb_wr, - reg_value => v_bash, - cs => v_bash_cs - ); +-- i_vbasx : work.flexbus_register +-- generic map +-- ( +-- reg_width => 2, +-- match_address => x"ffff8603", +-- match_mask => x"0000ffff", -- byte register +-- match_fbcs => 1 +-- ) +-- port map +-- ( +-- clk => clk33m, +-- fb_addr => fb_adr, +-- fb_data => fb_ad, +-- fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1), +-- fb_ta_n => reg_ta, +-- fb_wr_n => nfb_wr, +-- reg_value => v_basx, +-- cs => v_basx_cs +-- ); +-- +-- i_vbash : work.flexbus_register +-- generic map +-- ( +-- reg_width => 8, +-- match_address => x"ffff8604", +-- match_mask => x"0000fffe", -- byte register +-- match_fbcs => 1 +-- ) +-- port map +-- ( +-- clk => clk33m, +-- fb_addr => fb_adr, +-- fb_data => fb_ad, +-- fb_cs => ('0', '0', nfb_cs3, nfb_cs2, nfb_cs1), +-- fb_ta_n => V, +-- fb_wr_n => nfb_wr, +-- reg_value => v_bash, +-- cs => v_bash_cs +-- ); -- Start of original equations line <= fb_size0 and fb_size1; @@ -654,6 +647,7 @@ begin bus_cyc_end <= '0'; stdVec3 := FB_REGDDR_q; + case stdVec3 is when "000" => FB_LE(0) <= not nFB_WR; @@ -718,7 +712,7 @@ begin end if; when others => - video_ddr_ta <= '0'; + end case; stdVec3 := (others => '0'); -- no storage needed end process; diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index ade9e44..7afd582 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -545,7 +545,7 @@ begin HBE <= HBE_q; HSS <= HSS_q; VCO <= VCO_q; - VCNTRL <= VCNTRL_q; + VCNTRL <= VCNTRL_d; VSYNC <= VSYNC_q; nBLANK <= nBLANK_q; @@ -1269,47 +1269,82 @@ begin -- - REGISTER OUT -- low word register access - u0_data <= (sizeIt(ST_SHIFT_MODE_CS,16) and std_logic_vector'("000000" & ST_SHIFT_MODE_q & "00000000")) or - (sizeIt(FALCON_SHIFT_MODE_CS,16) and std_logic_vector'("00000" & FALCON_SHIFT_MODE_q)) or - (sizeIt(SYS_CTR_CS,16) and std_logic_vector'("100000000" & SYS_CTR_q(6 downto 4) & (not BLITTER_RUN) & SYS_CTR_q(2 downto 0))) or - (sizeIt(LOF_CS,16) and LOF_q) or (sizeIt(LWD_CS,16) and LWD_q) or - (sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or - (sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or - (sizeIt(HDE_CS,16) and std_logic_vector'("0000" & HDE_q)) or - (sizeIt(HBB_CS,16) and std_logic_vector'("0000" & HBB_q)) or - (sizeIt(HSS_CS,16) and std_logic_vector'("0000" & HSS_q)) or - (sizeIt(HHT_CS,16) and std_logic_vector'("0000" & HHT_q)) or - (sizeIt(VBE_CS,16) and std_logic_vector'("00000" & VBE_q)) or - (sizeIt(VDB_CS,16) and std_logic_vector'("00000" & VDB_q)) or - (sizeIt(VDE_CS,16) and std_logic_vector'("00000" & VDE_q)) or - (sizeIt(VBB_CS,16) and std_logic_vector'("00000" & VBB_q)) or - (sizeIt(VSS_CS,16) and std_logic_vector'("00000" & VSS_q)) or - (sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or - (sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or - (sizeIt(VCNTRL_CS,16) and std_logic_vector'("000000000000" & VCNTRL_q)) or - (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(31 downto 16)) or - (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 downto 16)) or - (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 downto 16)) or - (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(31 downto 16)) or - (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 downto 16)) or - (sizeIt(BORDER_COLOR_CS,16) and std_logic_vector'("00000000" & BORDER_COLOR_q(23 downto 16))) or - (sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & VR_DOUT_q)) or - (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(VR_BUSY & "0000" & VR_WR_q & VR_RD & VIDEO_RECONFIG_q & "11111010")); +-- u0_data <= (sizeIt(ST_SHIFT_MODE_CS,16) and std_logic_vector'("000000" & ST_SHIFT_MODE_q & "00000000")) or +-- (sizeIt(FALCON_SHIFT_MODE_CS,16) and std_logic_vector'("00000" & FALCON_SHIFT_MODE_q)) or +-- (sizeIt(SYS_CTR_CS,16) and std_logic_vector'("100000000" & SYS_CTR_q(6 downto 4) & (not BLITTER_RUN) & SYS_CTR_q(2 downto 0))) or +-- (sizeIt(LOF_CS,16) and LOF_q) or (sizeIt(LWD_CS,16) and LWD_q) or +-- (sizeIt(HBE_CS,16) and std_logic_vector'("0000" & HBE_q)) or +-- (sizeIt(HDB_CS,16) and std_logic_vector'("0000" & HDB_q)) or +-- (sizeIt(HDE_CS,16) and std_logic_vector'("0000" & HDE_q)) or +-- (sizeIt(HBB_CS,16) and std_logic_vector'("0000" & HBB_q)) or +-- (sizeIt(HSS_CS,16) and std_logic_vector'("0000" & HSS_q)) or +-- (sizeIt(HHT_CS,16) and std_logic_vector'("0000" & HHT_q)) or +-- (sizeIt(VBE_CS,16) and std_logic_vector'("00000" & VBE_q)) or +-- (sizeIt(VDB_CS,16) and std_logic_vector'("00000" & VDB_q)) or +-- (sizeIt(VDE_CS,16) and std_logic_vector'("00000" & VDE_q)) or +-- (sizeIt(VBB_CS,16) and std_logic_vector'("00000" & VBB_q)) or +-- (sizeIt(VSS_CS,16) and std_logic_vector'("00000" & VSS_q)) or +-- (sizeIt(VFT_CS,16) and std_logic_vector'("00000" & VFT_q)) or +-- (sizeIt(VCO_CS,16) and std_logic_vector'("0000000" & VCO_q)) or +-- (sizeIt(VCNTRL_CS,16) and std_logic_vector'("000000000000" & VCNTRL_q)) or +-- (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(31 downto 16)) or +-- (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(31 downto 16)) or +-- (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(31 downto 16)) or +-- (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(31 downto 16)) or +-- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(31 downto 16)) or +-- (sizeIt(BORDER_COLOR_CS,16) and std_logic_vector'("00000000" & BORDER_COLOR_q(23 downto 16))) or +-- (sizeIt(VIDEO_PLL_CONFIG_CS,16) and std_logic_vector'("0000000" & VR_DOUT_q)) or +-- (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(VR_BUSY & "0000" & VR_WR_q & VR_RD & VIDEO_RECONFIG_q & "11111010")); - u0_enabledt <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or BORDER_COLOR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or - HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or - VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS) and (not nFB_OE); - FB_AD(31 downto 16) <= u0_tridata; + FB_AD(31 downto 16) <= "000000" & st_shift_mode_q & "00000000" when st_shift_mode_cs = '1' else + "100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0) when sys_ctr_cs = '1' else + lwd_q when lof_cs = '1' and lwd_cs = '1' else + "0000" & hbe_q when hbe_cs = '1' else + "0000" & hdb_q when hdb_cs = '1' else + "0000" & hde_q when hde_cs = '1' else + "0000" & hbb_q when hbb_cs = '1' else + "0000" & hss_q when hss_cs = '1' else + "0000" & hht_q when hht_cs = '1' else + "00000" & vbe_q when vbe_cs = '1' else + "00000" & vdb_q when vdb_cs = '1' else + "00000" & vde_q when vde_cs = '1' else + "00000" & vbb_q when vbb_cs = '1' else + "00000" & vss_q when vss_cs = '1' else + "00000" & vft_q when vft_cs = '1' else + "0000000" & vco_q when vco_cs = '1' else + "000000000000" & vcntrl_q when vcntrl_cs = '1' else + acp_vctr_q(31 downto 16) when acp_vctr_cs = '1' else + atari_hh_q(31 downto 16) when atari_hh_cs = '1' else + atari_vh_q(31 downto 16) when atari_vh_cs = '1' else + atari_hl_q(31 downto 16) when atari_hl_cs = '1' else + atari_vl_q(31 downto 16) when atari_vl_cs = '1' else + "00000000" & border_color_q(23 downto 16) when border_color_cs = '1' else + "0000000" & vr_dout_q when video_pll_config_cs = '1' else + vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs else + (others => 'Z'); + +-- u0_enabledt <= (ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or BORDER_COLOR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or +-- HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or +-- VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS) and (not nFB_OE); +-- FB_AD(31 downto 16) <= u0_tridata; -- high word register access - u1_data <= (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(15 downto 0)) or - (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(15 downto 0)) or - (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(15 downto 0)) or - (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(15 downto 0)) or - (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 downto 0)) or - (sizeIt(BORDER_COLOR_CS,16) and BORDER_COLOR_q(15 downto 0)); - u1_enabledt <= (ACP_VCTR_CS or BORDER_COLOR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); - FB_AD(15 downto 0) <= u1_tridata; +-- u1_data <= (sizeIt(ACP_VCTR_CS,16) and ACP_VCTR_q(15 downto 0)) or +-- (sizeIt(ATARI_HH_CS,16) and ATARI_HH_q(15 downto 0)) or +-- (sizeIt(ATARI_VH_CS,16) and ATARI_VH_q(15 downto 0)) or +-- (sizeIt(ATARI_HL_CS,16) and ATARI_HL_q(15 downto 0)) or +-- (sizeIt(ATARI_VL_CS,16) and ATARI_VL_q(15 downto 0)) or +-- (sizeIt(BORDER_COLOR_CS,16) and BORDER_COLOR_q(15 downto 0)); +-- u1_enabledt <= (ACP_VCTR_CS or BORDER_COLOR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE); +-- FB_AD(15 downto 0) <= u1_tridata; + + fb_ad(15 downto 0) <= acp_vctr_q(15 downto 0) when acp_vctr_cs = '1' else + atari_hh_q(15 downto 0) when atari_hh_cs = '1' else + atari_vh_q(15 downto 0) when atari_vh_cs = '1' else + atari_hl_q(15 downto 0) when atari_hl_cs = '1' else + atari_vl_q(15 downto 0) when atari_vl_cs = '1' else + border_color_q(15 downto 0) when border_color_cs = '1' else + (others => 'Z'); video_mod_ta <= clut_ta_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index 78a9acc..f42b241 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -39,389 +39,389 @@ # Project-Wide Assignments # ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29 SEPTEMBER 03, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 # Pin & Location Assignments # ========================== -set_location_assignment PIN_G2 -to MAIN_CLK -set_location_assignment PIN_Y3 -to FB_AD[0] -set_location_assignment PIN_Y6 -to FB_AD[1] -set_location_assignment PIN_AA3 -to FB_AD[2] -set_location_assignment PIN_AB3 -to FB_AD[3] -set_location_assignment PIN_W6 -to FB_AD[4] -set_location_assignment PIN_V7 -to FB_AD[5] -set_location_assignment PIN_AA4 -to FB_AD[6] -set_location_assignment PIN_AB4 -to FB_AD[7] -set_location_assignment PIN_AA5 -to FB_AD[8] -set_location_assignment PIN_AB5 -to FB_AD[9] -set_location_assignment PIN_W7 -to FB_AD[10] -set_location_assignment PIN_Y7 -to FB_AD[11] -set_location_assignment PIN_U9 -to FB_AD[12] -set_location_assignment PIN_V8 -to FB_AD[13] -set_location_assignment PIN_W8 -to FB_AD[14] -set_location_assignment PIN_AA7 -to FB_AD[15] -set_location_assignment PIN_AB7 -to FB_AD[16] -set_location_assignment PIN_Y8 -to FB_AD[17] -set_location_assignment PIN_V9 -to FB_AD[18] -set_location_assignment PIN_V10 -to FB_AD[19] -set_location_assignment PIN_T10 -to FB_AD[20] -set_location_assignment PIN_U10 -to FB_AD[21] -set_location_assignment PIN_AA8 -to FB_AD[22] -set_location_assignment PIN_AB8 -to FB_AD[23] -set_location_assignment PIN_T11 -to FB_AD[24] -set_location_assignment PIN_AA9 -to FB_AD[25] -set_location_assignment PIN_AB9 -to FB_AD[26] -set_location_assignment PIN_U11 -to FB_AD[27] -set_location_assignment PIN_V11 -to FB_AD[28] -set_location_assignment PIN_W10 -to FB_AD[29] -set_location_assignment PIN_Y10 -to FB_AD[30] -set_location_assignment PIN_AA10 -to FB_AD[31] -set_location_assignment PIN_R7 -to FB_ALE -set_location_assignment PIN_N19 -to LED_FPGA_OK -set_location_assignment PIN_AB10 -to CLK24M576 -set_location_assignment PIN_J1 -to CLKUSB -set_location_assignment PIN_T4 -to CLK25M -set_location_assignment PIN_U8 -to FB_SIZE0 -set_location_assignment PIN_Y4 -to FB_SIZE1 -set_location_assignment PIN_T3 -to nFB_BURST -set_location_assignment PIN_T8 -to nFB_CS1 -set_location_assignment PIN_T9 -to nFB_CS2 -set_location_assignment PIN_V6 -to nFB_CS3 -set_location_assignment PIN_R6 -to nFB_OE -set_location_assignment PIN_T5 -to nFB_WR -set_location_assignment PIN_R5 -to TIN0 -set_location_assignment PIN_T21 -to nMASTER -set_location_assignment PIN_E11 -to nDREQ1 -set_location_assignment PIN_A12 -to nDACK1 -set_location_assignment PIN_B12 -to nDACK0 -set_location_assignment PIN_T22 -to TOUT0 -set_location_assignment PIN_AB17 -to DDR_CLK -set_location_assignment PIN_AA17 -to nDDR_CLK -set_location_assignment PIN_AB18 -to nVCAS -set_location_assignment PIN_T18 -to nVCS -set_location_assignment PIN_W17 -to nVRAS -set_location_assignment PIN_Y17 -to nVWE -set_location_assignment PIN_W20 -to VA[0] -set_location_assignment PIN_W22 -to VA[1] -set_location_assignment PIN_W21 -to VA[2] -set_location_assignment PIN_Y22 -to VA[3] -set_location_assignment PIN_AA22 -to VA[4] -set_location_assignment PIN_Y21 -to VA[5] -set_location_assignment PIN_AA21 -to VA[6] -set_location_assignment PIN_AA20 -to VA[7] -set_location_assignment PIN_AB20 -to VA[8] -set_location_assignment PIN_AB19 -to VA[9] -set_location_assignment PIN_V21 -to VA[10] -set_location_assignment PIN_U19 -to VA[11] -set_location_assignment PIN_AA18 -to VA[12] -set_location_assignment PIN_U15 -to VCKE -set_location_assignment PIN_M22 -to VD[0] -set_location_assignment PIN_M21 -to VD[1] -set_location_assignment PIN_P22 -to VD[2] -set_location_assignment PIN_R20 -to VD[3] -set_location_assignment PIN_P21 -to VD[4] -set_location_assignment PIN_R17 -to VD[5] -set_location_assignment PIN_R19 -to VD[6] -set_location_assignment PIN_U21 -to VD[7] -set_location_assignment PIN_V22 -to VD[8] -set_location_assignment PIN_R18 -to VD[9] -set_location_assignment PIN_P17 -to VD[10] -set_location_assignment PIN_R21 -to VD[11] -set_location_assignment PIN_N17 -to VD[12] -set_location_assignment PIN_P20 -to VD[13] -set_location_assignment PIN_R22 -to VD[14] -set_location_assignment PIN_N20 -to VD[15] -set_location_assignment PIN_T12 -to VD[16] -set_location_assignment PIN_Y13 -to VD[17] -set_location_assignment PIN_AA13 -to VD[18] -set_location_assignment PIN_V14 -to VD[19] -set_location_assignment PIN_U13 -to VD[20] -set_location_assignment PIN_V15 -to VD[21] -set_location_assignment PIN_W14 -to VD[22] -set_location_assignment PIN_AB16 -to VD[23] -set_location_assignment PIN_AB15 -to VD[24] -set_location_assignment PIN_AA14 -to VD[25] -set_location_assignment PIN_AB14 -to VD[26] -set_location_assignment PIN_V13 -to VD[27] -set_location_assignment PIN_W13 -to VD[28] -set_location_assignment PIN_AB13 -to VD[29] -set_location_assignment PIN_V12 -to VD[30] -set_location_assignment PIN_U12 -to VD[31] -set_location_assignment PIN_AA16 -to VDM[0] -set_location_assignment PIN_V16 -to VDM[1] -set_location_assignment PIN_U20 -to VDM[2] -set_location_assignment PIN_T17 -to VDM[3] -set_location_assignment PIN_AA15 -to VDQS[0] -set_location_assignment PIN_W15 -to VDQS[1] -set_location_assignment PIN_U22 -to VDQS[2] -set_location_assignment PIN_T16 -to VDQS[3] -set_location_assignment PIN_V1 -to nPD_VGA -set_location_assignment PIN_G18 -to VB[0] -set_location_assignment PIN_H17 -to VB[1] -set_location_assignment PIN_C22 -to VB[2] -set_location_assignment PIN_C21 -to VB[3] -set_location_assignment PIN_B22 -to VB[4] -set_location_assignment PIN_B21 -to VB[5] -set_location_assignment PIN_C20 -to VB[6] -set_location_assignment PIN_D20 -to VB[7] -set_location_assignment PIN_H19 -to VG[0] -set_location_assignment PIN_E22 -to VG[1] -set_location_assignment PIN_E21 -to VG[2] -set_location_assignment PIN_H18 -to VG[3] -set_location_assignment PIN_J17 -to VG[4] -set_location_assignment PIN_H16 -to VG[5] -set_location_assignment PIN_D22 -to VG[6] -set_location_assignment PIN_D21 -to VG[7] -set_location_assignment PIN_J22 -to VR[0] -set_location_assignment PIN_J21 -to VR[1] -set_location_assignment PIN_H22 -to VR[2] -set_location_assignment PIN_H21 -to VR[3] -set_location_assignment PIN_K17 -to VR[4] -set_location_assignment PIN_K18 -to VR[5] -set_location_assignment PIN_J18 -to VR[6] -set_location_assignment PIN_F22 -to VR[7] -set_location_assignment PIN_M6 -to ACSI_A1 -set_location_assignment PIN_B1 -to ACSI_D[0] -set_location_assignment PIN_G5 -to ACSI_D[1] -set_location_assignment PIN_E3 -to ACSI_D[2] -set_location_assignment PIN_C2 -to ACSI_D[3] -set_location_assignment PIN_C1 -to ACSI_D[4] -set_location_assignment PIN_D2 -to ACSI_D[5] -set_location_assignment PIN_H7 -to ACSI_D[6] -set_location_assignment PIN_H6 -to ACSI_D[7] -set_location_assignment PIN_L6 -to ACSI_DIR -set_location_assignment PIN_N1 -to AMKB_TX -set_location_assignment PIN_F15 -to DSA_D -set_location_assignment PIN_D15 -to DTR -set_location_assignment PIN_A11 -to DVI_INT -set_location_assignment PIN_G21 -to E0_INT -set_location_assignment PIN_M5 -to IDE_RES -set_location_assignment PIN_A8 -to IO[0] -set_location_assignment PIN_A7 -to IO[1] -set_location_assignment PIN_B7 -to IO[2] -set_location_assignment PIN_A6 -to IO[3] -set_location_assignment PIN_B6 -to IO[4] -set_location_assignment PIN_E9 -to IO[5] -set_location_assignment PIN_C8 -to IO[6] -set_location_assignment PIN_C7 -to IO[7] -set_location_assignment PIN_G10 -to IO[8] -set_location_assignment PIN_A15 -to IO[9] -set_location_assignment PIN_B15 -to IO[10] -set_location_assignment PIN_C13 -to IO[11] -set_location_assignment PIN_D13 -to IO[12] -set_location_assignment PIN_E13 -to IO[13] -set_location_assignment PIN_A14 -to IO[14] -set_location_assignment PIN_B14 -to IO[15] -set_location_assignment PIN_A13 -to IO[16] -set_location_assignment PIN_B13 -to IO[17] -set_location_assignment PIN_F7 -to LP_D[0] -set_location_assignment PIN_C4 -to LP_D[1] -set_location_assignment PIN_C3 -to LP_D[2] -set_location_assignment PIN_E7 -to LP_D[3] -set_location_assignment PIN_D6 -to LP_D[4] -set_location_assignment PIN_B3 -to LP_D[5] -set_location_assignment PIN_A3 -to LP_D[6] -set_location_assignment PIN_G8 -to LP_D[7] -set_location_assignment PIN_E6 -to LP_STR -set_location_assignment PIN_H5 -to MIDI_OLR -set_location_assignment PIN_B2 -to MIDI_TLR -set_location_assignment PIN_M4 -to nACSI_ACK -set_location_assignment PIN_M2 -to nACSI_CS -set_location_assignment PIN_M1 -to nACSI_RESET -set_location_assignment PIN_W2 -to nCF_CS0 -set_location_assignment PIN_W1 -to nCF_CS1 -set_location_assignment PIN_T7 -to nFB_TA -set_location_assignment PIN_R2 -to nIDE_CS0 -set_location_assignment PIN_R1 -to nIDE_CS1 -set_location_assignment PIN_P1 -to nIDE_RD -set_location_assignment PIN_P2 -to nIDE_WR -set_location_assignment PIN_F21 -to nIRQ[2] -set_location_assignment PIN_H20 -to nIRQ[3] -set_location_assignment PIN_F20 -to nIRQ[4] -set_location_assignment PIN_P5 -to nIRQ[5] -set_location_assignment PIN_P7 -to nIRQ[6] -set_location_assignment PIN_N7 -to nIRQ[7] -set_location_assignment PIN_AA1 -to nPCI_INTA -set_location_assignment PIN_V4 -to nPCI_INTB -set_location_assignment PIN_V3 -to nPCI_INTC -set_location_assignment PIN_P6 -to nPCI_INTD -set_location_assignment PIN_P3 -to nROM3 -set_location_assignment PIN_U2 -to nROM4 -set_location_assignment PIN_N5 -to nRP_LDS -set_location_assignment PIN_P4 -to nRP_UDS -set_location_assignment PIN_N2 -to nSCSI_ACK -set_location_assignment PIN_M3 -to nSCSI_ATN -set_location_assignment PIN_N8 -to nSCSI_BUSY -set_location_assignment PIN_N6 -to nSCSI_RST -set_location_assignment PIN_M8 -to nSCSI_SEL -set_location_assignment PIN_B20 -to nSDSEL -set_location_assignment PIN_B4 -to nSRBHE -set_location_assignment PIN_A4 -to nSRBLE -set_location_assignment PIN_B8 -to nSRCS -set_location_assignment PIN_F11 -to nSROE -set_location_assignment PIN_F8 -to nSRWE -set_location_assignment PIN_G14 -to nWR -set_location_assignment PIN_D17 -to nWR_GATE -set_location_assignment PIN_AA2 -to PIC_INT -set_location_assignment PIN_B18 -to RTS -set_location_assignment PIN_J6 -to SCSI_D[0] -set_location_assignment PIN_E1 -to SCSI_D[1] -set_location_assignment PIN_F2 -to SCSI_D[2] -set_location_assignment PIN_F1 -to SCSI_D[3] -set_location_assignment PIN_G4 -to SCSI_D[4] -set_location_assignment PIN_G3 -to SCSI_D[5] -set_location_assignment PIN_L8 -to SCSI_D[6] -set_location_assignment PIN_K8 -to SCSI_D[7] -set_location_assignment PIN_J7 -to SCSI_DIR -set_location_assignment PIN_M7 -to SCSI_PAR -set_location_assignment PIN_F13 -to SD_CD_DATA3 -set_location_assignment PIN_C15 -to SD_CLK -set_location_assignment PIN_E14 -to SD_CMD_D1 -set_location_assignment PIN_B5 -to SRD[0] -set_location_assignment PIN_A5 -to SRD[1] -set_location_assignment PIN_C6 -to SRD[2] -set_location_assignment PIN_G11 -to SRD[3] -set_location_assignment PIN_C10 -to SRD[4] -set_location_assignment PIN_F9 -to SRD[5] -set_location_assignment PIN_E10 -to SRD[6] -set_location_assignment PIN_H11 -to SRD[7] -set_location_assignment PIN_B9 -to SRD[8] -set_location_assignment PIN_A10 -to SRD[9] -set_location_assignment PIN_A9 -to SRD[10] -set_location_assignment PIN_B10 -to SRD[11] -set_location_assignment PIN_D10 -to SRD[12] -set_location_assignment PIN_F10 -to SRD[13] -set_location_assignment PIN_G9 -to SRD[14] -set_location_assignment PIN_H10 -to SRD[15] -set_location_assignment PIN_A18 -to TxD -set_location_assignment PIN_A17 -to YM_QA -set_location_assignment PIN_G13 -to YM_QB -set_location_assignment PIN_E15 -to YM_QC -set_location_assignment PIN_T1 -to WP_CF_CARD -set_location_assignment PIN_C19 -to TRACK00 -set_location_assignment PIN_M19 -to SD_WP -set_location_assignment PIN_B17 -to SD_DATA2 -set_location_assignment PIN_A16 -to SD_DATA1 -set_location_assignment PIN_B16 -to SD_DATA0 -set_location_assignment PIN_M20 -to SD_CARD_DEDECT -set_location_assignment PIN_H15 -to RxD -set_location_assignment PIN_B19 -to RI -set_location_assignment PIN_L7 -to PIC_AMKB_RX -set_location_assignment PIN_D19 -to nWP -set_location_assignment PIN_H2 -to nSCSI_MSG -set_location_assignment PIN_J3 -to nSCSI_I_O -set_location_assignment PIN_U1 -to nSCSI_DRQ -set_location_assignment PIN_H1 -to nSCSI_C_D -set_location_assignment PIN_A20 -to nRD_DATA -set_location_assignment PIN_C17 -to nDCHG -set_location_assignment PIN_J4 -to nACSI_INT -set_location_assignment PIN_K7 -to nACSI_DRQ -set_location_assignment PIN_G7 -to LP_BUSY -set_location_assignment PIN_Y1 -to IDE_RDY -set_location_assignment PIN_G22 -to IDE_INT -set_location_assignment PIN_F16 -to HD_DD -set_location_assignment PIN_A19 -to DCD -set_location_assignment PIN_H14 -to CTS -set_location_assignment PIN_Y2 -to AMKB_RX -set_location_assignment PIN_E16 -to nINDEX -set_location_assignment PIN_W19 -to BA[0] -set_location_assignment PIN_AA19 -to BA[1] -set_location_assignment PIN_K21 -to HSYNC_PAD -set_location_assignment PIN_K19 -to VSYNC_PAD -set_location_assignment PIN_G17 -to nBLANK_PAD -set_location_assignment PIN_F19 -to PIXEL_CLK_PAD -set_location_assignment PIN_F17 -to nSYNC -set_location_assignment PIN_G15 -to nSTEP_DIR -set_location_assignment PIN_F14 -to nSTEP -set_location_assignment PIN_G16 -to nMOT_ON +set_location_assignment PIN_G2 -to MAIN_CLK +set_location_assignment PIN_Y3 -to FB_AD[0] +set_location_assignment PIN_Y6 -to FB_AD[1] +set_location_assignment PIN_AA3 -to FB_AD[2] +set_location_assignment PIN_AB3 -to FB_AD[3] +set_location_assignment PIN_W6 -to FB_AD[4] +set_location_assignment PIN_V7 -to FB_AD[5] +set_location_assignment PIN_AA4 -to FB_AD[6] +set_location_assignment PIN_AB4 -to FB_AD[7] +set_location_assignment PIN_AA5 -to FB_AD[8] +set_location_assignment PIN_AB5 -to FB_AD[9] +set_location_assignment PIN_W7 -to FB_AD[10] +set_location_assignment PIN_Y7 -to FB_AD[11] +set_location_assignment PIN_U9 -to FB_AD[12] +set_location_assignment PIN_V8 -to FB_AD[13] +set_location_assignment PIN_W8 -to FB_AD[14] +set_location_assignment PIN_AA7 -to FB_AD[15] +set_location_assignment PIN_AB7 -to FB_AD[16] +set_location_assignment PIN_Y8 -to FB_AD[17] +set_location_assignment PIN_V9 -to FB_AD[18] +set_location_assignment PIN_V10 -to FB_AD[19] +set_location_assignment PIN_T10 -to FB_AD[20] +set_location_assignment PIN_U10 -to FB_AD[21] +set_location_assignment PIN_AA8 -to FB_AD[22] +set_location_assignment PIN_AB8 -to FB_AD[23] +set_location_assignment PIN_T11 -to FB_AD[24] +set_location_assignment PIN_AA9 -to FB_AD[25] +set_location_assignment PIN_AB9 -to FB_AD[26] +set_location_assignment PIN_U11 -to FB_AD[27] +set_location_assignment PIN_V11 -to FB_AD[28] +set_location_assignment PIN_W10 -to FB_AD[29] +set_location_assignment PIN_Y10 -to FB_AD[30] +set_location_assignment PIN_AA10 -to FB_AD[31] +set_location_assignment PIN_R7 -to FB_ALE +set_location_assignment PIN_N19 -to LED_FPGA_OK +set_location_assignment PIN_AB10 -to CLK24M576 +set_location_assignment PIN_J1 -to CLKUSB +set_location_assignment PIN_T4 -to CLK25M +set_location_assignment PIN_U8 -to FB_SIZE0 +set_location_assignment PIN_Y4 -to FB_SIZE1 +set_location_assignment PIN_T3 -to nFB_BURST +set_location_assignment PIN_T8 -to nFB_CS1 +set_location_assignment PIN_T9 -to nFB_CS2 +set_location_assignment PIN_V6 -to nFB_CS3 +set_location_assignment PIN_R6 -to nFB_OE +set_location_assignment PIN_T5 -to nFB_WR +set_location_assignment PIN_R5 -to TIN0 +set_location_assignment PIN_T21 -to nMASTER +set_location_assignment PIN_E11 -to nDREQ1 +set_location_assignment PIN_A12 -to nDACK1 +set_location_assignment PIN_B12 -to nDACK0 +set_location_assignment PIN_T22 -to TOUT0 +set_location_assignment PIN_AB17 -to DDR_CLK +set_location_assignment PIN_AA17 -to nDDR_CLK +set_location_assignment PIN_AB18 -to nVCAS +set_location_assignment PIN_T18 -to nVCS +set_location_assignment PIN_W17 -to nVRAS +set_location_assignment PIN_Y17 -to nVWE +set_location_assignment PIN_W20 -to VA[0] +set_location_assignment PIN_W22 -to VA[1] +set_location_assignment PIN_W21 -to VA[2] +set_location_assignment PIN_Y22 -to VA[3] +set_location_assignment PIN_AA22 -to VA[4] +set_location_assignment PIN_Y21 -to VA[5] +set_location_assignment PIN_AA21 -to VA[6] +set_location_assignment PIN_AA20 -to VA[7] +set_location_assignment PIN_AB20 -to VA[8] +set_location_assignment PIN_AB19 -to VA[9] +set_location_assignment PIN_V21 -to VA[10] +set_location_assignment PIN_U19 -to VA[11] +set_location_assignment PIN_AA18 -to VA[12] +set_location_assignment PIN_U15 -to VCKE +set_location_assignment PIN_M22 -to VD[0] +set_location_assignment PIN_M21 -to VD[1] +set_location_assignment PIN_P22 -to VD[2] +set_location_assignment PIN_R20 -to VD[3] +set_location_assignment PIN_P21 -to VD[4] +set_location_assignment PIN_R17 -to VD[5] +set_location_assignment PIN_R19 -to VD[6] +set_location_assignment PIN_U21 -to VD[7] +set_location_assignment PIN_V22 -to VD[8] +set_location_assignment PIN_R18 -to VD[9] +set_location_assignment PIN_P17 -to VD[10] +set_location_assignment PIN_R21 -to VD[11] +set_location_assignment PIN_N17 -to VD[12] +set_location_assignment PIN_P20 -to VD[13] +set_location_assignment PIN_R22 -to VD[14] +set_location_assignment PIN_N20 -to VD[15] +set_location_assignment PIN_T12 -to VD[16] +set_location_assignment PIN_Y13 -to VD[17] +set_location_assignment PIN_AA13 -to VD[18] +set_location_assignment PIN_V14 -to VD[19] +set_location_assignment PIN_U13 -to VD[20] +set_location_assignment PIN_V15 -to VD[21] +set_location_assignment PIN_W14 -to VD[22] +set_location_assignment PIN_AB16 -to VD[23] +set_location_assignment PIN_AB15 -to VD[24] +set_location_assignment PIN_AA14 -to VD[25] +set_location_assignment PIN_AB14 -to VD[26] +set_location_assignment PIN_V13 -to VD[27] +set_location_assignment PIN_W13 -to VD[28] +set_location_assignment PIN_AB13 -to VD[29] +set_location_assignment PIN_V12 -to VD[30] +set_location_assignment PIN_U12 -to VD[31] +set_location_assignment PIN_AA16 -to VDM[0] +set_location_assignment PIN_V16 -to VDM[1] +set_location_assignment PIN_U20 -to VDM[2] +set_location_assignment PIN_T17 -to VDM[3] +set_location_assignment PIN_AA15 -to VDQS[0] +set_location_assignment PIN_W15 -to VDQS[1] +set_location_assignment PIN_U22 -to VDQS[2] +set_location_assignment PIN_T16 -to VDQS[3] +set_location_assignment PIN_V1 -to nPD_VGA +set_location_assignment PIN_G18 -to VB[0] +set_location_assignment PIN_H17 -to VB[1] +set_location_assignment PIN_C22 -to VB[2] +set_location_assignment PIN_C21 -to VB[3] +set_location_assignment PIN_B22 -to VB[4] +set_location_assignment PIN_B21 -to VB[5] +set_location_assignment PIN_C20 -to VB[6] +set_location_assignment PIN_D20 -to VB[7] +set_location_assignment PIN_H19 -to VG[0] +set_location_assignment PIN_E22 -to VG[1] +set_location_assignment PIN_E21 -to VG[2] +set_location_assignment PIN_H18 -to VG[3] +set_location_assignment PIN_J17 -to VG[4] +set_location_assignment PIN_H16 -to VG[5] +set_location_assignment PIN_D22 -to VG[6] +set_location_assignment PIN_D21 -to VG[7] +set_location_assignment PIN_J22 -to VR[0] +set_location_assignment PIN_J21 -to VR[1] +set_location_assignment PIN_H22 -to VR[2] +set_location_assignment PIN_H21 -to VR[3] +set_location_assignment PIN_K17 -to VR[4] +set_location_assignment PIN_K18 -to VR[5] +set_location_assignment PIN_J18 -to VR[6] +set_location_assignment PIN_F22 -to VR[7] +set_location_assignment PIN_M6 -to ACSI_A1 +set_location_assignment PIN_B1 -to ACSI_D[0] +set_location_assignment PIN_G5 -to ACSI_D[1] +set_location_assignment PIN_E3 -to ACSI_D[2] +set_location_assignment PIN_C2 -to ACSI_D[3] +set_location_assignment PIN_C1 -to ACSI_D[4] +set_location_assignment PIN_D2 -to ACSI_D[5] +set_location_assignment PIN_H7 -to ACSI_D[6] +set_location_assignment PIN_H6 -to ACSI_D[7] +set_location_assignment PIN_L6 -to ACSI_DIR +set_location_assignment PIN_N1 -to AMKB_TX +set_location_assignment PIN_F15 -to DSA_D +set_location_assignment PIN_D15 -to DTR +set_location_assignment PIN_A11 -to DVI_INT +set_location_assignment PIN_G21 -to E0_INT +set_location_assignment PIN_M5 -to IDE_RES +set_location_assignment PIN_A8 -to IO[0] +set_location_assignment PIN_A7 -to IO[1] +set_location_assignment PIN_B7 -to IO[2] +set_location_assignment PIN_A6 -to IO[3] +set_location_assignment PIN_B6 -to IO[4] +set_location_assignment PIN_E9 -to IO[5] +set_location_assignment PIN_C8 -to IO[6] +set_location_assignment PIN_C7 -to IO[7] +set_location_assignment PIN_G10 -to IO[8] +set_location_assignment PIN_A15 -to IO[9] +set_location_assignment PIN_B15 -to IO[10] +set_location_assignment PIN_C13 -to IO[11] +set_location_assignment PIN_D13 -to IO[12] +set_location_assignment PIN_E13 -to IO[13] +set_location_assignment PIN_A14 -to IO[14] +set_location_assignment PIN_B14 -to IO[15] +set_location_assignment PIN_A13 -to IO[16] +set_location_assignment PIN_B13 -to IO[17] +set_location_assignment PIN_F7 -to LP_D[0] +set_location_assignment PIN_C4 -to LP_D[1] +set_location_assignment PIN_C3 -to LP_D[2] +set_location_assignment PIN_E7 -to LP_D[3] +set_location_assignment PIN_D6 -to LP_D[4] +set_location_assignment PIN_B3 -to LP_D[5] +set_location_assignment PIN_A3 -to LP_D[6] +set_location_assignment PIN_G8 -to LP_D[7] +set_location_assignment PIN_E6 -to LP_STR +set_location_assignment PIN_H5 -to MIDI_OLR +set_location_assignment PIN_B2 -to MIDI_TLR +set_location_assignment PIN_M4 -to nACSI_ACK +set_location_assignment PIN_M2 -to nACSI_CS +set_location_assignment PIN_M1 -to nACSI_RESET +set_location_assignment PIN_W2 -to nCF_CS0 +set_location_assignment PIN_W1 -to nCF_CS1 +set_location_assignment PIN_T7 -to nFB_TA +set_location_assignment PIN_R2 -to nIDE_CS0 +set_location_assignment PIN_R1 -to nIDE_CS1 +set_location_assignment PIN_P1 -to nIDE_RD +set_location_assignment PIN_P2 -to nIDE_WR +set_location_assignment PIN_F21 -to nIRQ[2] +set_location_assignment PIN_H20 -to nIRQ[3] +set_location_assignment PIN_F20 -to nIRQ[4] +set_location_assignment PIN_P5 -to nIRQ[5] +set_location_assignment PIN_P7 -to nIRQ[6] +set_location_assignment PIN_N7 -to nIRQ[7] +set_location_assignment PIN_AA1 -to nPCI_INTA +set_location_assignment PIN_V4 -to nPCI_INTB +set_location_assignment PIN_V3 -to nPCI_INTC +set_location_assignment PIN_P6 -to nPCI_INTD +set_location_assignment PIN_P3 -to nROM3 +set_location_assignment PIN_U2 -to nROM4 +set_location_assignment PIN_N5 -to nRP_LDS +set_location_assignment PIN_P4 -to nRP_UDS +set_location_assignment PIN_N2 -to nSCSI_ACK +set_location_assignment PIN_M3 -to nSCSI_ATN +set_location_assignment PIN_N8 -to nSCSI_BUSY +set_location_assignment PIN_N6 -to nSCSI_RST +set_location_assignment PIN_M8 -to nSCSI_SEL +set_location_assignment PIN_B20 -to nSDSEL +set_location_assignment PIN_B4 -to nSRBHE +set_location_assignment PIN_A4 -to nSRBLE +set_location_assignment PIN_B8 -to nSRCS +set_location_assignment PIN_F11 -to nSROE +set_location_assignment PIN_F8 -to nSRWE +set_location_assignment PIN_G14 -to nWR +set_location_assignment PIN_D17 -to nWR_GATE +set_location_assignment PIN_AA2 -to PIC_INT +set_location_assignment PIN_B18 -to RTS +set_location_assignment PIN_J6 -to SCSI_D[0] +set_location_assignment PIN_E1 -to SCSI_D[1] +set_location_assignment PIN_F2 -to SCSI_D[2] +set_location_assignment PIN_F1 -to SCSI_D[3] +set_location_assignment PIN_G4 -to SCSI_D[4] +set_location_assignment PIN_G3 -to SCSI_D[5] +set_location_assignment PIN_L8 -to SCSI_D[6] +set_location_assignment PIN_K8 -to SCSI_D[7] +set_location_assignment PIN_J7 -to SCSI_DIR +set_location_assignment PIN_M7 -to SCSI_PAR +set_location_assignment PIN_F13 -to SD_CD_DATA3 +set_location_assignment PIN_C15 -to SD_CLK +set_location_assignment PIN_E14 -to SD_CMD_D1 +set_location_assignment PIN_B5 -to SRD[0] +set_location_assignment PIN_A5 -to SRD[1] +set_location_assignment PIN_C6 -to SRD[2] +set_location_assignment PIN_G11 -to SRD[3] +set_location_assignment PIN_C10 -to SRD[4] +set_location_assignment PIN_F9 -to SRD[5] +set_location_assignment PIN_E10 -to SRD[6] +set_location_assignment PIN_H11 -to SRD[7] +set_location_assignment PIN_B9 -to SRD[8] +set_location_assignment PIN_A10 -to SRD[9] +set_location_assignment PIN_A9 -to SRD[10] +set_location_assignment PIN_B10 -to SRD[11] +set_location_assignment PIN_D10 -to SRD[12] +set_location_assignment PIN_F10 -to SRD[13] +set_location_assignment PIN_G9 -to SRD[14] +set_location_assignment PIN_H10 -to SRD[15] +set_location_assignment PIN_A18 -to TxD +set_location_assignment PIN_A17 -to YM_QA +set_location_assignment PIN_G13 -to YM_QB +set_location_assignment PIN_E15 -to YM_QC +set_location_assignment PIN_T1 -to WP_CF_CARD +set_location_assignment PIN_C19 -to TRACK00 +set_location_assignment PIN_M19 -to SD_WP +set_location_assignment PIN_B17 -to SD_DATA2 +set_location_assignment PIN_A16 -to SD_DATA1 +set_location_assignment PIN_B16 -to SD_DATA0 +set_location_assignment PIN_M20 -to SD_CARD_DEDECT +set_location_assignment PIN_H15 -to RxD +set_location_assignment PIN_B19 -to RI +set_location_assignment PIN_L7 -to PIC_AMKB_RX +set_location_assignment PIN_D19 -to nWP +set_location_assignment PIN_H2 -to nSCSI_MSG +set_location_assignment PIN_J3 -to nSCSI_I_O +set_location_assignment PIN_U1 -to nSCSI_DRQ +set_location_assignment PIN_H1 -to nSCSI_C_D +set_location_assignment PIN_A20 -to nRD_DATA +set_location_assignment PIN_C17 -to nDCHG +set_location_assignment PIN_J4 -to nACSI_INT +set_location_assignment PIN_K7 -to nACSI_DRQ +set_location_assignment PIN_G7 -to LP_BUSY +set_location_assignment PIN_Y1 -to IDE_RDY +set_location_assignment PIN_G22 -to IDE_INT +set_location_assignment PIN_F16 -to HD_DD +set_location_assignment PIN_A19 -to DCD +set_location_assignment PIN_H14 -to CTS +set_location_assignment PIN_Y2 -to AMKB_RX +set_location_assignment PIN_E16 -to nINDEX +set_location_assignment PIN_W19 -to BA[0] +set_location_assignment PIN_AA19 -to BA[1] +set_location_assignment PIN_K21 -to HSYNC_PAD +set_location_assignment PIN_K19 -to VSYNC_PAD +set_location_assignment PIN_G17 -to nBLANK_PAD +set_location_assignment PIN_F19 -to PIXEL_CLK_PAD +set_location_assignment PIN_F17 -to nSYNC +set_location_assignment PIN_G15 -to nSTEP_DIR +set_location_assignment PIN_F14 -to nSTEP +set_location_assignment PIN_G16 -to nMOT_ON # Classic Timing Assignments # ========================== -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name TPD_REQUIREMENT "1 ns" -set_global_assignment -name TSU_REQUIREMENT "1 ns" -set_global_assignment -name TCO_REQUIREMENT "1 ns" -set_global_assignment -name TH_REQUIREMENT "1 ns" -set_global_assignment -name FMAX_REQUIREMENT "30 ns" +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name TPD_REQUIREMENT "1 ns" +set_global_assignment -name TSU_REQUIREMENT "1 ns" +set_global_assignment -name TCO_REQUIREMENT "1 ns" +set_global_assignment -name TH_REQUIREMENT "1 ns" +set_global_assignment -name FMAX_REQUIREMENT "30 ns" # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name FAMILY CycloneIII -set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name SAFE_STATE_MACHINE OFF -set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" +set_global_assignment -name FAMILY CycloneIII +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484 +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name SAFE_STATE_MACHINE OFF +set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT" # Fitter Assignments # ================== -set_global_assignment -name DEVICE EP3C40F484C6 -set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON -set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON -set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VA -set_instance_assignment -name IO_STANDARD "2.5 V" -to VD -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM -set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS -set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK -set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE -set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK -set_instance_assignment -name IO_STANDARD "2.5 V" -to BA -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX +set_global_assignment -name DEVICE EP3C40F484C6 +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON +set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON +set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VA +set_instance_assignment -name IO_STANDARD "2.5 V" -to VD +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM +set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS +set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE +set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK +set_instance_assignment -name IO_STANDARD "2.5 V" -to BA +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX # Assembler Assignments # ===================== -set_global_assignment -name GENERATE_TTF_FILE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name GENERATE_HEX_FILE OFF -set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 +set_global_assignment -name GENERATE_TTF_FILE OFF +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name GENERATE_HEX_FILE OFF +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000 # Simulator Assignments # ===================== -set_global_assignment -name END_TIME "2 us" -set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF -set_global_assignment -name SETUP_HOLD_DETECTION OFF -set_global_assignment -name GLITCH_DETECTION OFF -set_global_assignment -name CHECK_OUTPUTS OFF -set_global_assignment -name SIMULATION_MODE TIMING -set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf +set_global_assignment -name END_TIME "2 us" +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF +set_global_assignment -name SETUP_HOLD_DETECTION OFF +set_global_assignment -name GLITCH_DETECTION OFF +set_global_assignment -name CHECK_OUTPUTS OFF +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf # start EDA_TOOL_SETTINGS(eda_blast_fpga) # --------------------------------------- # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga # end EDA_TOOL_SETTINGS(eda_blast_fpga) # ------------------------------------- @@ -431,7 +431,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e # Classic Timing Assignments # ========================== -set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast +set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # end CLOCK(fast) # --------------- @@ -441,21 +441,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast # Assignment Group Assignments # ============================ -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast -set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast +set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast # end ASSIGNMENT_GROUP(fast) # -------------------------- @@ -465,76 +465,76 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_ # Classic Timing Assignments # ========================== -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] -set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE -set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS -set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2] +set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3] +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" +set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" +set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE +set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS +set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA # Fitter Assignments # ================== -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA -set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA +set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX # Simulator Assignments # ===================== -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # start LOGICLOCK_REGION(Root Region) # ----------------------------------- @@ -556,311 +556,311 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3 # end ENTITY(firebee1) # -------------------- -set_location_assignment PIN_E5 -to LPDIR -set_location_assignment PIN_B11 -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD -set_location_assignment PIN_AB12 -to CLK33MDIR -set_location_assignment PIN_E12 -to MIDI_IN_PIN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN -set_instance_assignment -name PCI_IO ON -to nPCI_INTA -set_instance_assignment -name PCI_IO ON -to nPCI_INTB -set_instance_assignment -name PCI_IO ON -to nPCI_INTC -set_instance_assignment -name PCI_IO ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] -set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] -set_global_assignment -name POWER_USE_TA_VALUE 35 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS -set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name SMART_RECOMPILE ON +set_location_assignment PIN_E5 -to LPDIR +set_location_assignment PIN_B11 -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD +set_location_assignment PIN_AB12 -to CLK33MDIR +set_location_assignment PIN_E12 -to MIDI_IN_PIN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN +set_instance_assignment -name PCI_IO ON -to nPCI_INTA +set_instance_assignment -name PCI_IO ON -to nPCI_INTB +set_instance_assignment -name PCI_IO ON -to nPCI_INTC +set_instance_assignment -name PCI_IO ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0 +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6] +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3] +set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2] +set_global_assignment -name POWER_USE_TA_VALUE 35 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1] +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS +set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name TOP_LEVEL_ENTITY firebee1 -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 -set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" -set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis -set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" -set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF -set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q -set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf -set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf -set_global_assignment -name AHDL_FILE altpll4.tdf -set_global_assignment -name SDC_FILE firebee_groups.sdc -set_global_assignment -name VHDL_FILE Video/video.vhd -set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd -set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd -set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp -set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd -set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE Video/mux41.vhd -set_global_assignment -name VHDL_FILE Video/mux41_5.vhd -set_global_assignment -name VHDL_FILE Video/mux41_4.vhd -set_global_assignment -name VHDL_FILE Video/mux41_3.vhd -set_global_assignment -name VHDL_FILE Video/mux41_2.vhd -set_global_assignment -name VHDL_FILE Video/mux41_1.vhd -set_global_assignment -name VHDL_FILE Video/mux41_0.vhd -set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp -set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd -set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp -set_global_assignment -name VHDL_FILE Video/altdpram0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp -set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp -set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp -set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE Video/altdpram0.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip -set_global_assignment -name QIP_FILE Video/altdpram1.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant0.qip -set_global_assignment -name QIP_FILE Video/lpm_constant1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux1.qip -set_global_assignment -name QIP_FILE Video/lpm_mux2.qip -set_global_assignment -name QIP_FILE Video/lpm_constant2.qip -set_global_assignment -name QIP_FILE Video/altdpram2.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip -set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip -set_global_assignment -name QIP_FILE Video/altddio_out0.qip -set_global_assignment -name QIP_FILE Video/lpm_mux5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip -set_global_assignment -name QIP_FILE Video/altddio_out1.qip -set_global_assignment -name QIP_FILE Video/altddio_out2.qip -set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux6.qip -set_global_assignment -name QIP_FILE Video/lpm_mux3.qip -set_global_assignment -name QIP_FILE Video/lpm_mux4.qip -set_global_assignment -name QIP_FILE Video/lpm_constant3.qip -set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip -set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip -set_global_assignment -name QIP_FILE Video/lpm_latch1.qip -set_global_assignment -name QIP_FILE Video/lpm_constant4.qip -set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip -set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip -set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT -set_global_assignment -name QIP_FILE Video/lpm_compare1.qip -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp -set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp -set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd -set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp -set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd -set_global_assignment -name QIP_FILE Video/lpm_ff4.qip -set_global_assignment -name QIP_FILE Video/lpm_ff5.qip -set_global_assignment -name QIP_FILE Video/lpm_ff6.qip -set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp -set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip -set_global_assignment -name VHDL_FILE DSP/DSP.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd -set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip -set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd -set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd -set_global_assignment -name VHDL_FILE lpm_latch0.vhd -set_global_assignment -name SOURCE_FILE lpm_latch0.cmp -set_global_assignment -name QIP_FILE altpll1.qip -set_global_assignment -name QIP_FILE altpll2.qip -set_global_assignment -name QIP_FILE altpll3.qip -set_global_assignment -name SOURCE_FILE altpll0.cmp -set_global_assignment -name SOURCE_FILE altpll2.cmp -set_global_assignment -name VHDL_FILE altpll2.vhd -set_global_assignment -name SOURCE_FILE altpll3.cmp -set_global_assignment -name VHDL_FILE altpll3.vhd -set_global_assignment -name SOURCE_FILE lpm_counter0.cmp -set_global_assignment -name VHDL_FILE altpll1.vhd -set_global_assignment -name SOURCE_FILE altpll1.cmp -set_global_assignment -name QIP_FILE altpll0.qip -set_global_assignment -name QIP_FILE lpm_counter0.qip -set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip -set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip -set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip -set_global_assignment -name QIP_FILE altddio_out3.qip -set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt -set_global_assignment -name QIP_FILE altpll4.qip -set_global_assignment -name QIP_FILE lpm_mux0.qip -set_global_assignment -name QIP_FILE lpm_shiftreg0.qip -set_global_assignment -name QIP_FILE lpm_counter1.qip -set_global_assignment -name QIP_FILE altiobuf_bidir0.qip -set_global_assignment -name VHDL_FILE flexbus_register.vhd +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" +set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON +set_global_assignment -name SAVE_DISK_SPACE OFF +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK +set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q +set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf +set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf +set_global_assignment -name AHDL_FILE altpll4.tdf +set_global_assignment -name SDC_FILE firebee_groups.sdc +set_global_assignment -name VHDL_FILE Video/video.vhd +set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd +set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd +set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp +set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd +set_global_assignment -name SOURCE_FILE altpll4.cmp +set_global_assignment -name VHDL_FILE firebee1.vhd +set_global_assignment -name VHDL_FILE Video/mux41.vhd +set_global_assignment -name VHDL_FILE Video/mux41_5.vhd +set_global_assignment -name VHDL_FILE Video/mux41_4.vhd +set_global_assignment -name VHDL_FILE Video/mux41_3.vhd +set_global_assignment -name VHDL_FILE Video/mux41_2.vhd +set_global_assignment -name VHDL_FILE Video/mux41_1.vhd +set_global_assignment -name VHDL_FILE Video/mux41_0.vhd +set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp +set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd +set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp +set_global_assignment -name VHDL_FILE Video/altdpram0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp +set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp +set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp +set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE Video/altdpram0.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip +set_global_assignment -name QIP_FILE Video/altdpram1.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant0.qip +set_global_assignment -name QIP_FILE Video/lpm_constant1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux1.qip +set_global_assignment -name QIP_FILE Video/lpm_mux2.qip +set_global_assignment -name QIP_FILE Video/lpm_constant2.qip +set_global_assignment -name QIP_FILE Video/altdpram2.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip +set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip +set_global_assignment -name QIP_FILE Video/altddio_out0.qip +set_global_assignment -name QIP_FILE Video/lpm_mux5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip +set_global_assignment -name QIP_FILE Video/altddio_out1.qip +set_global_assignment -name QIP_FILE Video/altddio_out2.qip +set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux6.qip +set_global_assignment -name QIP_FILE Video/lpm_mux3.qip +set_global_assignment -name QIP_FILE Video/lpm_mux4.qip +set_global_assignment -name QIP_FILE Video/lpm_constant3.qip +set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip +set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip +set_global_assignment -name QIP_FILE Video/lpm_latch1.qip +set_global_assignment -name QIP_FILE Video/lpm_constant4.qip +set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip +set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip +set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT +set_global_assignment -name QIP_FILE Video/lpm_compare1.qip +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp +set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp +set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd +set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp +set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd +set_global_assignment -name QIP_FILE Video/lpm_ff4.qip +set_global_assignment -name QIP_FILE Video/lpm_ff5.qip +set_global_assignment -name QIP_FILE Video/lpm_ff6.qip +set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp +set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip +set_global_assignment -name VHDL_FILE DSP/DSP.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd +set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip +set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd +set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd +set_global_assignment -name VHDL_FILE lpm_latch0.vhd +set_global_assignment -name SOURCE_FILE lpm_latch0.cmp +set_global_assignment -name QIP_FILE altpll1.qip +set_global_assignment -name QIP_FILE altpll2.qip +set_global_assignment -name QIP_FILE altpll3.qip +set_global_assignment -name SOURCE_FILE altpll0.cmp +set_global_assignment -name SOURCE_FILE altpll2.cmp +set_global_assignment -name VHDL_FILE altpll2.vhd +set_global_assignment -name SOURCE_FILE altpll3.cmp +set_global_assignment -name VHDL_FILE altpll3.vhd +set_global_assignment -name SOURCE_FILE lpm_counter0.cmp +set_global_assignment -name VHDL_FILE altpll1.vhd +set_global_assignment -name SOURCE_FILE altpll1.cmp +set_global_assignment -name QIP_FILE altpll0.qip +set_global_assignment -name QIP_FILE lpm_counter0.qip +set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip +set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip +set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip +set_global_assignment -name QIP_FILE altddio_out3.qip +set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt +set_global_assignment -name QIP_FILE altpll4.qip +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE lpm_shiftreg0.qip +set_global_assignment -name QIP_FILE lpm_counter1.qip +set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_global_assignment -name VHDL_FILE flexbus_register.vhd set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index 3388ae3..49d04e6 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -7,293 +7,246 @@ LIBRARY altera; LIBRARY work; ENTITY firebee1 IS - PORT + port ( - FB_ALE : IN std_logic; - nFB_WR : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nFB_BURST : IN std_logic; - LP_BUSY : IN std_logic; - nACSI_DRQ : IN std_logic; - nACSI_INT : IN std_logic; - RxD : IN std_logic; - CTS : IN std_logic; - RI : IN std_logic; - DCD : IN std_logic; - AMKB_RX : IN std_logic; - PIC_AMKB_RX : IN std_logic; - IDE_RDY : IN std_logic; - IDE_INT : IN std_logic; - WP_CF_CARD : IN std_logic; - TRACK00 : IN std_logic; - nWP : IN std_logic; - nDCHG : IN std_logic; - SD_DATA0 : IN std_logic; - SD_DATA1 : IN std_logic; - SD_DATA2 : IN std_logic; - SD_CARD_DEDECT : IN std_logic; - nSCSI_DRQ : IN std_logic; - SD_WP : IN std_logic; - nRD_DATA : IN std_logic; - nSCSI_C_D : IN std_logic; - nSCSI_I_O : IN std_logic; - nSCSI_MSG : IN std_logic; - nDACK0 : IN std_logic; - PIC_INT : IN std_logic; - nFB_OE : IN std_logic; - TOUT0 : IN std_logic; - nMASTER : IN std_logic; - DVI_INT : IN std_logic; - nDACK1 : IN std_logic; - nPCI_INTD : IN std_logic; - nPCI_INTC : IN std_logic; - nPCI_INTB : IN std_logic; - nPCI_INTA : IN std_logic; - E0_INT : IN std_logic; - nINDEX : IN std_logic; - HD_DD : IN std_logic; - MAIN_CLK : IN std_logic; - nRSTO_MCF : IN std_logic; - CLK33MDIR : IN std_logic; - SCSI_PAR : INOUT std_logic; - nSCSI_RST : INOUT std_logic; - nSCSI_SEL : INOUT std_logic; - nSCSI_BUSY : INOUT std_logic; - SD_CD_DATA3 : INOUT std_logic; - SD_CMD_D1 : INOUT std_logic; - MIDI_IN_PIN : INOUT std_logic; - ACSI_D : INOUT std_logic_vector(7 DOWNTO 0); - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); - IO : INOUT std_logic_vector(17 DOWNTO 0); - LP_D : INOUT std_logic_vector(7 DOWNTO 0); - SCSI_D : INOUT std_logic_vector(7 DOWNTO 0); - SRD : INOUT std_logic_vector(15 DOWNTO 0); - VD : INOUT std_logic_vector(31 DOWNTO 0); - VDQS : INOUT std_logic_vector(3 DOWNTO 0); - LP_STR : OUT std_logic; - nACSI_ACK : OUT std_logic; - nACSI_RESET : OUT std_logic; - nACSI_CS : OUT std_logic; - ACSI_DIR : OUT std_logic; - ACSI_A1 : OUT std_logic; - nSCSI_ACK : OUT std_logic; - nSCSI_ATN : OUT std_logic; - SCSI_DIR : OUT std_logic; - MIDI_TLR : OUT std_logic; - TxD : OUT std_logic; - RTS : OUT std_logic; - DTR : OUT std_logic; - AMKB_TX : OUT std_logic; - IDE_RES : OUT std_logic; - nIDE_CS0 : OUT std_logic; - nIDE_CS1 : OUT std_logic; - nIDE_WR : OUT std_logic; - nIDE_RD : OUT std_logic; - nCF_CS0 : OUT std_logic; - nCF_CS1 : OUT std_logic; - nROM3 : OUT std_logic; - nROM4 : OUT std_logic; - nRP_UDS : OUT std_logic; - nRP_LDS : OUT std_logic; - nSDSEL : OUT std_logic; - nWR_GATE : OUT std_logic; - nWR : OUT std_logic; - YM_QA : OUT std_logic; - YM_QB : OUT std_logic; - YM_QC : OUT std_logic; - SD_CLK : OUT std_logic; - DSA_D : OUT std_logic; - nVWE : OUT std_logic; - nVCAS : OUT std_logic; - nVRAS : OUT std_logic; - nVCS : OUT std_logic; - nPD_VGA : OUT std_logic; - TIN0 : OUT std_logic; - nSRCS : OUT std_logic; - nSRBLE : OUT std_logic; - nSRBHE : OUT std_logic; - nSRWE : OUT std_logic; - nDREQ1 : OUT std_logic; - LED_FPGA_OK : OUT std_logic; - nSROE : OUT std_logic; - VCKE : OUT std_logic; - nFB_TA : OUT std_logic; - nDDR_CLK : OUT std_logic; - DDR_CLK : OUT std_logic; - VSYNC_PAD : OUT std_logic; - HSYNC_PAD : OUT std_logic; - nBLANK_PAD : OUT std_logic; - PIXEL_CLK_PAD : OUT std_logic; - nSYNC : OUT std_logic; - nMOT_ON : OUT std_logic; - nSTEP_DIR : OUT std_logic; - nSTEP : OUT std_logic; - LPDIR : OUT std_logic; - MIDI_OLR : OUT std_logic; - CLK25M : OUT std_logic; - CLKUSB : OUT std_logic; - CLK24M576 : OUT std_logic; - BA : OUT std_logic_vector(1 DOWNTO 0); - nIRQ : OUT std_logic_vector(7 DOWNTO 2); - VA : OUT std_logic_vector(12 DOWNTO 0); - VB : OUT std_logic_vector(7 DOWNTO 0); - VDM : OUT std_logic_vector(3 DOWNTO 0); - VG : OUT std_logic_vector(7 DOWNTO 0); - VR : OUT std_logic_vector(7 DOWNTO 0) + FB_ALE : in std_logic; + nFB_WR : in std_logic; + nFB_CS1 : in std_logic; + nFB_CS2 : in std_logic; + nFB_CS3 : in std_logic; + FB_SIZE0 : in std_logic; + FB_SIZE1 : in std_logic; + nFB_BURST : in std_logic; + LP_BUSY : in std_logic; + nACSI_DRQ : in std_logic; + nACSI_INT : in std_logic; + RxD : in std_logic; + CTS : in std_logic; + RI : in std_logic; + DCD : in std_logic; + AMKB_RX : in std_logic; + PIC_AMKB_RX : in std_logic; + IDE_RDY : in std_logic; + IDE_INT : in std_logic; + WP_CF_CARD : in std_logic; + TRACK00 : in std_logic; + nWP : in std_logic; + nDCHG : in std_logic; + SD_DATA0 : in std_logic; + SD_DATA1 : in std_logic; + SD_DATA2 : in std_logic; + SD_CARD_DEDECT : in std_logic; + nSCSI_DRQ : in std_logic; + SD_WP : in std_logic; + nRD_DATA : in std_logic; + nSCSI_C_D : in std_logic; + nSCSI_I_O : in std_logic; + nSCSI_MSG : in std_logic; + nDACK0 : in std_logic; + PIC_INT : in std_logic; + nFB_OE : in std_logic; + TOUT0 : in std_logic; + nMASTER : in std_logic; + DVI_INT : in std_logic; + nDACK1 : in std_logic; + nPCI_INTD : in std_logic; + nPCI_INTC : in std_logic; + nPCI_INTB : in std_logic; + nPCI_INTA : in std_logic; + E0_INT : in std_logic; + nINDEX : in std_logic; + HD_DD : in std_logic; + MAIN_CLK : in std_logic; + nRSTO_MCF : in std_logic; + CLK33MDIR : in std_logic; + SCSI_PAR : inout std_logic; + nSCSI_RST : inout std_logic; + nSCSI_SEL : inout std_logic; + nSCSI_BUSY : inout std_logic; + SD_CD_DATA3 : inout std_logic; + SD_CMD_D1 : inout std_logic; + MIDI_IN_PIN : inout std_logic; + ACSI_D : inout std_logic_vector(7 downto 0); + FB_AD : inout std_logic_vector(31 downto 0); + IO : inout std_logic_vector(17 downto 0); + LP_D : inout std_logic_vector(7 downto 0); + SCSI_D : inout std_logic_vector(7 downto 0); + SRD : inout std_logic_vector(15 downto 0); + VD : inout std_logic_vector(31 downto 0); + VDQS : inout std_logic_vector(3 downto 0); + LP_STR : out std_logic; + nACSI_ACK : out std_logic; + nACSI_RESET : out std_logic; + nACSI_CS : out std_logic; + ACSI_DIR : out std_logic; + ACSI_A1 : out std_logic; + nSCSI_ACK : out std_logic; + nSCSI_ATN : out std_logic; + SCSI_DIR : out std_logic; + MIDI_TLR : out std_logic; + TxD : out std_logic; + RTS : out std_logic; + DTR : out std_logic; + AMKB_TX : out std_logic; + IDE_RES : out std_logic; + nIDE_CS0 : out std_logic; + nIDE_CS1 : out std_logic; + nIDE_WR : out std_logic; + nIDE_RD : out std_logic; + nCF_CS0 : out std_logic; + nCF_CS1 : out std_logic; + nROM3 : out std_logic; + nROM4 : out std_logic; + nRP_UDS : out std_logic; + nRP_LDS : out std_logic; + nSDSEL : out std_logic; + nWR_GATE : out std_logic; + nWR : out std_logic; + YM_QA : out std_logic; + YM_QB : out std_logic; + YM_QC : out std_logic; + SD_CLK : out std_logic; + DSA_D : out std_logic; + nVWE : out std_logic; + nVCAS : out std_logic; + nVRAS : out std_logic; + nVCS : out std_logic; + nPD_VGA : out std_logic; + TIN0 : out std_logic; + nSRCS : out std_logic; + nSRBLE : out std_logic; + nSRBHE : out std_logic; + nSRWE : out std_logic; + nDREQ1 : out std_logic; + LED_FPGA_OK : out std_logic; + nSROE : out std_logic; + VCKE : out std_logic; + nFB_TA : out std_logic; + nDDR_CLK : out std_logic; + DDR_CLK : out std_logic; + VSYNC_PAD : out std_logic; + HSYNC_PAD : out std_logic; + nBLANK_PAD : out std_logic; + PIXEL_CLK_PAD : out std_logic; + nSYNC : out std_logic; + nMOT_ON : out std_logic; + nSTEP_DIR : out std_logic; + nSTEP : out std_logic; + LPDIR : out std_logic; + MIDI_OLR : out std_logic; + CLK25M : out std_logic; + CLKUSB : out std_logic; + CLK24M576 : out std_logic; + BA : out std_logic_vector(1 downto 0); + nIRQ : out std_logic_vector(7 downto 2); + VA : out std_logic_vector(12 downto 0); + VB : out std_logic_vector(7 downto 0); + VDM : out std_logic_vector(3 downto 0); + VG : out std_logic_vector(7 downto 0); + VR : out std_logic_vector(7 downto 0) ); -END firebee1; +end firebee1; -ARCHITECTURE rtl OF firebee1 IS - SIGNAL ACP_CONF : std_logic_vector(31 DOWNTO 0); - SIGNAL clk25m_i : std_logic; - SIGNAL CLK2M : std_logic; - SIGNAL CLK2M4576 : std_logic; - SIGNAL CLK33M : std_logic; - SIGNAL CLK48M : std_logic; - SIGNAL CLK500k : std_logic; - SIGNAL CLK_VIDEO : std_logic; - SIGNAL DDR_SYNC_66M : std_logic; - SIGNAL DDRCLK : std_logic_vector(3 DOWNTO 0); - SIGNAL DMA_DRQ : std_logic; - SIGNAL DSP_INT : std_logic; - SIGNAL DSP_TA : std_logic; - SIGNAL FALCON_IO_TA : std_logic; - SIGNAL FB_ADR : std_logic_vector(31 DOWNTO 0); - SIGNAL FDC_CLK : std_logic; - SIGNAL HSYNC : std_logic; - SIGNAL INT_HANDLER_TA : std_logic; - SIGNAL LP_DIR : std_logic; - SIGNAL MIDI_IN : std_logic; - SIGNAL MOT_ON : std_logic; - SIGNAL nBLANK : std_logic; - SIGNAL nDREQ0 : std_logic; - SIGNAL nMFP_INT : std_logic; - SIGNAL nRSTO : std_logic; - SIGNAL PIXEL_CLK : std_logic; - SIGNAL SD_CDM_D1 : std_logic; - SIGNAL STEP : std_logic; - SIGNAL STEP_DIR : std_logic; - SIGNAL TIMEBASE : std_logic_vector(17 DOWNTO 0); - SIGNAL VIDEO_RECONFIG : std_logic; - SIGNAL Video_TA : std_logic; - SIGNAL VR_BUSY : std_logic; - SIGNAL VR_D : std_logic_vector(8 DOWNTO 0); - SIGNAL VR_RD : std_logic; - SIGNAL VR_WR : std_logic; - SIGNAL VSYNC : std_logic; - SIGNAL WR_DATA : std_logic; - SIGNAL WR_GATE : std_logic; - SIGNAL scandataout : std_logic; - SIGNAL scandone : std_logic; - SIGNAL reset : std_logic; - SIGNAL pll_reset : std_logic; - SIGNAL scanclk : std_logic; - SIGNAL scandata : std_logic; - SIGNAL scan_clkena : std_logic; - SIGNAL config_update : std_logic; - SIGNAL pll3_locked : std_logic; - SIGNAL pll1_locked : std_logic; - SIGNAL nSRCS_i : std_logic; - SIGNAL nFB_WR_i : std_logic; - SIGNAL nIDE_RD_i : std_logic; - SIGNAL nIDE_WR_i : std_logic; +architecture rtl OF firebee1 IS + signal ACP_CONF : std_logic_vector(31 downto 0); + signal clk25m_i : std_logic; + signal CLK2M : std_logic; + signal CLK2M4576 : std_logic; + signal CLK33M : std_logic; + signal CLK48M : std_logic; + signal CLK500k : std_logic; + signal CLK_VIDEO : std_logic; + signal DDR_SYNC_66M : std_logic; + signal DDRCLK : std_logic_vector(3 downto 0); + signal DMA_DRQ : std_logic; + signal DSP_INT : std_logic; + signal DSP_TA : std_logic; + signal FALCON_IO_TA : std_logic; + signal FB_ADR : std_logic_vector(31 downto 0); + signal FDC_CLK : std_logic; + signal HSYNC : std_logic; + signal INT_HANDLER_TA : std_logic; + signal LP_DIR : std_logic; + signal MIDI_IN : std_logic; + signal MOT_ON : std_logic; + signal nBLANK : std_logic; + signal nDREQ0 : std_logic; + signal nMFP_INT : std_logic; + signal nRSTO : std_logic; + signal PIXEL_CLK : std_logic; + signal SD_CDM_D1 : std_logic; + signal STEP : std_logic; + signal STEP_DIR : std_logic; + signal TIMEBASE : std_logic_vector(17 downto 0); + signal VIDEO_RECONFIG : std_logic; + signal Video_TA : std_logic; + signal VR_BUSY : std_logic; + signal VR_D : std_logic_vector(8 downto 0); + signal VR_RD : std_logic; + signal VR_WR : std_logic; + signal VSYNC : std_logic; + signal WR_DATA : std_logic; + signal WR_GATE : std_logic; + signal scandataout : std_logic; + signal scandone : std_logic; + signal reset : std_logic; + signal pll_reset : std_logic; + signal scanclk : std_logic; + signal scandata : std_logic; + signal scan_clkena : std_logic; + signal config_update : std_logic; + signal pll3_locked : std_logic; + signal pll1_locked : std_logic; + signal nSRCS_i : std_logic; + signal nFB_WR_i : std_logic; + signal nIDE_RD_i : std_logic; + signal nIDE_WR_i : std_logic; - COMPONENT altpll_reconfig1 - PORT + component altpll_reconfig1 + port ( - clock : IN std_logic ; - counter_param : IN std_logic_vector (2 DOWNTO 0); - counter_type : IN std_logic_vector (3 DOWNTO 0); - data_in : IN std_logic_vector (8 DOWNTO 0); - pll_areset_in : IN std_logic := '0'; - pll_scandataout : IN std_logic ; - pll_scandone : IN std_logic ; - read_param : IN std_logic ; - reconfig : IN std_logic ; - reset : IN std_logic ; - write_param : IN std_logic ; - busy : OUT std_logic ; - data_out : OUT std_logic_vector (8 DOWNTO 0); - pll_areset : OUT std_logic ; - pll_configupdate : OUT std_logic ; - pll_scanclk : OUT std_logic ; - pll_scanclkena : OUT std_logic ; - pll_scandata : OUT std_logic + clock : in std_logic ; + counter_param : in std_logic_vector (2 downto 0); + counter_type : in std_logic_vector (3 downto 0); + data_in : in std_logic_vector (8 downto 0); + pll_areset_in : in std_logic := '0'; + pll_scandataout : in std_logic ; + pll_scandone : in std_logic ; + read_param : in std_logic ; + reconfig : in std_logic ; + reset : in std_logic ; + write_param : in std_logic ; + busy : out std_logic ; + data_out : out std_logic_vector (8 downto 0); + pll_areset : out std_logic ; + pll_configupdate : out std_logic ; + pll_scanclk : out std_logic ; + pll_scanclkena : out std_logic ; + pll_scandata : out std_logic ); - END COMPONENT altpll_reconfig1; + end component altpll_reconfig1; - COMPONENT altpll4 - PORT + component altpll4 + port ( - areset : IN std_logic := '0'; - configupdate : IN std_logic := '0'; - inclk0 : IN std_logic := '0'; - scanclk : IN std_logic := '1'; - scanclkena : IN std_logic := '0'; - scandata : IN std_logic := '0'; - c0 : OUT std_logic ; - locked : OUT std_logic ; - scandataout : OUT std_logic ; - scandone : OUT std_logic + areset : in std_logic := '0'; + configupdate : in std_logic := '0'; + inclk0 : in std_logic := '0'; + scanclk : in std_logic := '1'; + scanclkena : in std_logic := '0'; + scandata : in std_logic := '0'; + c0 : out std_logic; + locked : out std_logic; + scandataout : out std_logic; + scandone : out std_logic ); - END COMPONENT altpll4; + end component altpll4; --- COMPONENT video --- PORT --- ( --- FB_ADR : IN std_logic_vector(31 DOWNTO 0); --- MAIN_CLK : IN std_logic; --- nFB_CS1 : IN std_logic; --- nFB_CS2 : IN std_logic; --- nFB_CS3 : IN std_logic; --- nFB_WR : IN std_logic; --- FB_SIZE0 : IN std_logic; --- FB_SIZE1 : IN std_logic; --- nRSTO : IN std_logic; --- nFB_OE : IN std_logic; --- FB_ALE : IN std_logic; --- DDRCLK : IN std_logic_vector(3 DOWNTO 0); --- DDR_SYNC_66M : IN std_logic; --- CLK33M : IN std_logic; --- CLK25M : IN std_logic; --- CLK_VIDEO : IN std_logic; --- VR_D : IN std_logic_vector(8 DOWNTO 0); --- VR_BUSY : IN std_logic; --- VG : OUT std_logic_vector(7 DOWNTO 0); --- VB : OUT std_logic_vector(7 DOWNTO 0); --- VR : OUT std_logic_vector(7 DOWNTO 0); --- nBLANK : OUT std_logic; --- VA : OUT std_logic_vector(12 DOWNTO 0); --- nVWE : OUT std_logic; --- nVCAS : OUT std_logic; --- nVRAS : OUT std_logic; --- nVCS : OUT std_logic; --- VDM : OUT std_logic_vector(3 DOWNTO 0); --- nPD_VGA : OUT std_logic; --- VCKE : OUT std_logic; --- VSYNC : OUT std_logic; --- HSYNC : OUT std_logic; --- nSYNC : OUT std_logic; --- VIDEO_TA : OUT std_logic; --- PIXEL_CLK : OUT std_logic; --- BA : OUT std_logic_vector(1 DOWNTO 0); --- VIDEO_RECONFIG : OUT std_logic; --- VR_WR : OUT std_logic; --- VR_RD : OUT std_logic; --- VDQS : INOUT std_logic_vector(3 DOWNTO 0); --- FB_AD : INOUT std_logic_vector(31 DOWNTO 0); --- VD : INOUT std_logic_vector(31 DOWNTO 0) --- ); --- END COMPONENT video; -BEGIN +begin nDREQ1 <= nDACK1; i_atari_clk_pll : work.altpll3 - PORT MAP + port map ( inclk0 => MAIN_CLK, c0 => clk25m_i, @@ -305,7 +258,7 @@ BEGIN i_ddr_clk_pll : work.altpll2 - PORT MAP + port map ( inclk0 => MAIN_CLK, c0 => DDRCLK(0), @@ -317,7 +270,7 @@ BEGIN i_dsp : work.dsp - PORT MAP + port map ( CLK33M => CLK33M, MAIN_CLK => MAIN_CLK, @@ -345,7 +298,7 @@ BEGIN i_falcioio_sdcard_ide_cf : work.falconio_sdcard_ide_cf - PORT MAP + port map ( CLK33M => CLK33M, MAIN_CLK => MAIN_CLK, @@ -402,7 +355,7 @@ BEGIN nSCSI_RST => nSCSI_RST, SD_CD_DATA3 => SD_CD_DATA3, SD_CDM_D1 => SD_CDM_D1, - ACP_CONF => ACP_CONF(31 DOWNTO 24), + ACP_CONF => ACP_CONF(31 downto 24), ACSI_D => ACSI_D, FB_AD => FB_AD, FB_ADR => FB_ADR, @@ -453,7 +406,7 @@ BEGIN i_interrupt_handler : work.interrupt_handler - PORT MAP + port map ( MAIN_CLK => MAIN_CLK, nFB_WR => nFB_WR, @@ -485,7 +438,7 @@ BEGIN i_mfp_acia_clk_pll : work.altpll1 - PORT MAP + port map ( inclk0 => MAIN_CLK, c0 => CLK48M, @@ -496,7 +449,7 @@ BEGIN i_pll_reconfig : altpll_reconfig1 - PORT MAP + port map ( reconfig => VIDEO_RECONFIG, read_param => VR_RD, @@ -506,9 +459,9 @@ BEGIN pll_scandone => scandone, clock => MAIN_CLK, reset => reset, - counter_param => FB_ADR(8 DOWNTO 6), - counter_type => FB_ADR(5 DOWNTO 2), - data_in => FB_AD(24 DOWNTO 16), + counter_param => FB_ADR(8 downto 6), + counter_type => FB_ADR(5 downto 2), + data_in => FB_AD(24 downto 16), busy => VR_BUSY, pll_scandata => scandata, pll_scanclk => scanclk, @@ -520,7 +473,7 @@ BEGIN i_video : entity work.video - PORT MAP + port map ( MAIN_CLK => MAIN_CLK, nFB_CS1 => nFB_CS1, @@ -568,7 +521,7 @@ BEGIN i_video_clk_pll : altpll4 - PORT MAP + port map ( inclk0 => CLK48M, areset => pll_reset, @@ -583,7 +536,7 @@ BEGIN inst1 : work.lpm_ff0 - PORT MAP + port map ( clock => DDR_SYNC_66M, enable => FB_ALE, @@ -591,13 +544,13 @@ BEGIN q => FB_ADR ); - nMOT_ON <= NOT(MOT_ON); - nSTEP_DIR <= NOT(STEP_DIR); - nSTEP <= NOT(STEP); - nWR <= NOT(WR_DATA); + nMOT_ON <= not(MOT_ON); + nSTEP_DIR <= not(STEP_DIR); + nSTEP <= not(STEP); + nWR <= not(WR_DATA); inst18 : work.lpm_counter0 - PORT MAP + port map ( clock => CLK500k, q => TIMEBASE @@ -610,11 +563,11 @@ BEGIN CLK33M <= MAIN_CLK; - reset <= NOT(nRSTO); - nRSTO <= pll3_locked AND pll1_locked AND nRSTO_MCF; + reset <= not(nRSTO); + nRSTO <= pll3_locked and pll1_locked and nRSTO_MCF; inst29 : alt_iobuf - PORT MAP + port map ( i => CLK2M, oe => CLK2M, @@ -624,10 +577,10 @@ BEGIN LED_FPGA_OK <= TIMEBASE(17); - nDDR_CLK <= NOT(DDRCLK(0)); + nDDR_CLK <= not(DDRCLK(0)); inst5 : work.altddio_out3 - PORT MAP + port map ( datain_h => VSYNC, datain_l => VSYNC, @@ -637,7 +590,7 @@ BEGIN inst6 : work.altddio_out3 - PORT MAP + port map ( datain_h => HSYNC, datain_l => HSYNC, @@ -647,7 +600,7 @@ BEGIN inst8 : work.altddio_out3 - PORT MAP + port map ( datain_h => nBLANK, datain_l => nBLANK, @@ -656,7 +609,7 @@ BEGIN ); inst9 : work.altddio_out3 - PORT MAP + port map ( datain_h => '0', datain_l => '1', @@ -673,4 +626,4 @@ BEGIN nIDE_RD <= nIDE_RD_i; nIDE_WR <= nIDE_WR_i; -END rtl; \ No newline at end of file +end rtl; \ No newline at end of file