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replace video.bdf with video.vhd

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Markus Fröschle
2016-01-11 08:43:42 +00:00
parent f6aa56ac7a
commit 98a362dc90
10 changed files with 2195 additions and 10680 deletions
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90
FPGA_Quartus_13.1/Video/mux41.vhd Normal file
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-- Copyright (C) 1991-2014 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
-- CREATED "Mon Jan 11 09:37:12 2016"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY mux41 IS
PORT
(
S0 : IN STD_LOGIC;
D2 : IN STD_LOGIC;
INH : IN STD_LOGIC;
D0 : IN STD_LOGIC;
D1 : IN STD_LOGIC;
D3 : IN STD_LOGIC;
S1 : IN STD_LOGIC;
Q : OUT STD_LOGIC
);
END mux41;
ARCHITECTURE bdf_type OF mux41 IS
SIGNAL SYNTHESIZED_WIRE_18 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_19 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_20 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_21 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_22 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_14 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_15 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_16 : STD_LOGIC;
BEGIN
SYNTHESIZED_WIRE_18 <= NOT(S0);
SYNTHESIZED_WIRE_21 <= NOT(SYNTHESIZED_WIRE_18);
SYNTHESIZED_WIRE_13 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_20 AND SYNTHESIZED_WIRE_18 AND D0;
SYNTHESIZED_WIRE_14 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_20 AND SYNTHESIZED_WIRE_21 AND D1;
SYNTHESIZED_WIRE_15 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_22 AND SYNTHESIZED_WIRE_18 AND D2;
SYNTHESIZED_WIRE_16 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_22 AND SYNTHESIZED_WIRE_21 AND D3;
Q <= SYNTHESIZED_WIRE_13 OR SYNTHESIZED_WIRE_14 OR SYNTHESIZED_WIRE_15 OR SYNTHESIZED_WIRE_16;
SYNTHESIZED_WIRE_19 <= NOT(INH);
SYNTHESIZED_WIRE_20 <= NOT(S1);
SYNTHESIZED_WIRE_22 <= NOT(SYNTHESIZED_WIRE_20);
END bdf_type;

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FPGA_Quartus_13.1/Video/mux41_0.vhd Normal file
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-- Copyright (C) 1991-2014 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
-- CREATED "Mon Jan 11 09:20:56 2016"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera;
USE altera.maxplus2.all;
LIBRARY work;
ENTITY mux41_0 IS
PORT
(
S0 : IN STD_LOGIC;
S1 : IN STD_LOGIC;
D0 : IN STD_LOGIC;
INH : IN STD_LOGIC;
D1 : IN STD_LOGIC;
Q : OUT STD_LOGIC
);
END mux41_0;
ARCHITECTURE bdf_type OF mux41_0 IS
BEGIN
-- instantiate macrofunction
b2v_inst40 : work.mux41
PORT MAP(S0 => S0,
S1 => S1,
D0 => D0,
INH => INH,
D1 => D1,
D2 => '0',
D3 => '0',
Q => Q);
END bdf_type;

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FPGA_Quartus_13.1/Video/mux41_1.vhd Normal file
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@@ -0,0 +1,54 @@
-- Copyright (C) 1991-2014 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
-- CREATED "Mon Jan 11 09:20:56 2016"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera;
USE altera.maxplus2.all;
LIBRARY work;
ENTITY mux41_1 IS
PORT
(
S0 : IN STD_LOGIC;
S1 : IN STD_LOGIC;
D0 : IN STD_LOGIC;
INH : IN STD_LOGIC;
D1 : IN STD_LOGIC;
Q : OUT STD_LOGIC
);
END mux41_1;
ARCHITECTURE bdf_type OF mux41_1 IS
BEGIN
-- instantiate macrofunction
b2v_inst41 : work.mux41
PORT MAP(S0 => S0,
S1 => S1,
D0 => D0,
INH => INH,
D1 => D1,
D2 => '0',
D3 => '0',
Q => Q);
END bdf_type;

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FPGA_Quartus_13.1/Video/mux41_2.vhd Normal file
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-- Copyright (C) 1991-2014 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
-- CREATED "Mon Jan 11 09:20:56 2016"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera;
USE altera.maxplus2.all;
LIBRARY work;
ENTITY mux41_2 IS
PORT
(
S0 : IN STD_LOGIC;
D2 : IN STD_LOGIC;
S1 : IN STD_LOGIC;
D0 : IN STD_LOGIC;
INH : IN STD_LOGIC;
D1 : IN STD_LOGIC;
Q : OUT STD_LOGIC
);
END mux41_2;
ARCHITECTURE bdf_type OF mux41_2 IS
BEGIN
-- instantiate macrofunction
b2v_inst42 : work.mux41
PORT MAP(S0 => S0,
D2 => D2,
S1 => S1,
D0 => D0,
D3 => '0',
INH => INH,
D1 => D1,
Q => Q);
END bdf_type;

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FPGA_Quartus_13.1/Video/mux41_3.vhd Normal file
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@@ -0,0 +1,55 @@
-- Copyright (C) 1991-2014 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
-- CREATED "Mon Jan 11 09:20:56 2016"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera;
USE altera.maxplus2.all;
LIBRARY work;
ENTITY mux41_3 IS
PORT
(
S0 : IN STD_LOGIC;
D2 : IN STD_LOGIC;
S1 : IN STD_LOGIC;
D0 : IN STD_LOGIC;
INH : IN STD_LOGIC;
D1 : IN STD_LOGIC;
Q : OUT STD_LOGIC
);
END mux41_3;
ARCHITECTURE bdf_type OF mux41_3 IS
BEGIN
-- instantiate macrofunction
b2v_inst43 : work.mux41
PORT MAP(S0 => S0,
D2 => D2,
S1 => S1,
D0 => D0,
D3 => '0',
INH => INH,
D1 => D1,
Q => Q);
END bdf_type;

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FPGA_Quartus_13.1/Video/mux41_4.vhd Normal file
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@@ -0,0 +1,55 @@
-- Copyright (C) 1991-2014 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
-- CREATED "Mon Jan 11 09:20:56 2016"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera;
USE altera.maxplus2.all;
LIBRARY work;
ENTITY mux41_4 IS
PORT
(
S0 : IN STD_LOGIC;
D2 : IN STD_LOGIC;
S1 : IN STD_LOGIC;
D0 : IN STD_LOGIC;
INH : IN STD_LOGIC;
D1 : IN STD_LOGIC;
Q : OUT STD_LOGIC
);
END mux41_4;
ARCHITECTURE bdf_type OF mux41_4 IS
BEGIN
-- instantiate macrofunction
b2v_inst44 : work.mux41
PORT MAP(S0 => S0,
D2 => D2,
S1 => S1,
D0 => D0,
D3 => '0',
INH => INH,
D1 => D1,
Q => Q);
END bdf_type;

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FPGA_Quartus_13.1/Video/mux41_5.vhd Normal file
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@@ -0,0 +1,56 @@
-- Copyright (C) 1991-2014 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
-- CREATED "Mon Jan 11 09:20:56 2016"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera;
USE altera.maxplus2.all;
LIBRARY work;
ENTITY mux41_5 IS
PORT
(
S0 : IN STD_LOGIC;
D2 : IN STD_LOGIC;
S1 : IN STD_LOGIC;
D0 : IN STD_LOGIC;
INH : IN STD_LOGIC;
D1 : IN STD_LOGIC;
Q : OUT STD_LOGIC
);
END mux41_5;
ARCHITECTURE bdf_type OF mux41_5 IS
BEGIN
-- instantiate macrofunction
b2v_inst45 : work.mux41
PORT MAP(S0 => S0,
D2 => D2,
S1 => S1,
D0 => D0,
D3 => '0',
INH => INH,
D1 => D1,
Q => Q);
END bdf_type;

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FPGA_Quartus_13.1/Video/video.bdf
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9
FPGA_Quartus_13.1/firebee1.qsf
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@@ -670,11 +670,18 @@ set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name VHDL_FILE Video/mux41.vhd
set_global_assignment -name VHDL_FILE Video/mux41_5.vhd
set_global_assignment -name VHDL_FILE Video/mux41_4.vhd
set_global_assignment -name VHDL_FILE Video/mux41_3.vhd
set_global_assignment -name VHDL_FILE Video/mux41_2.vhd
set_global_assignment -name VHDL_FILE Video/mux41_1.vhd
set_global_assignment -name VHDL_FILE Video/mux41_0.vhd
set_global_assignment -name VHDL_FILE firebee1.vhd
set_global_assignment -name SDC_FILE firebee1.sdc
set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf
set_global_assignment -name AHDL_FILE altpll4.tdf
set_global_assignment -name BDF_FILE Video/video.bdf
set_global_assignment -name VHDL_FILE Video/video.vhd
set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd
set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf
set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp