diff --git a/FPGA_Quartus_13.1/Video/mux41.vhd b/FPGA_Quartus_13.1/Video/mux41.vhd
new file mode 100644
index 0000000..5a51a23
--- /dev/null
+++ b/FPGA_Quartus_13.1/Video/mux41.vhd
@@ -0,0 +1,90 @@
+-- Copyright (C) 1991-2014 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
+-- CREATED		"Mon Jan 11 09:37:12 2016"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY work;
+
+ENTITY mux41 IS 
+	PORT
+	(
+		S0 :  IN  STD_LOGIC;
+		D2 :  IN  STD_LOGIC;
+		INH :  IN  STD_LOGIC;
+		D0 :  IN  STD_LOGIC;
+		D1 :  IN  STD_LOGIC;
+		D3 :  IN  STD_LOGIC;
+		S1 :  IN  STD_LOGIC;
+		Q :  OUT  STD_LOGIC
+	);
+END mux41;
+
+ARCHITECTURE bdf_type OF mux41 IS 
+
+SIGNAL	SYNTHESIZED_WIRE_18 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_19 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_20 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_21 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_22 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_13 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_14 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_15 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_16 :  STD_LOGIC;
+
+
+BEGIN 
+
+
+
+SYNTHESIZED_WIRE_18 <= NOT(S0);
+
+
+
+SYNTHESIZED_WIRE_21 <= NOT(SYNTHESIZED_WIRE_18);
+
+
+
+SYNTHESIZED_WIRE_13 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_20 AND SYNTHESIZED_WIRE_18 AND D0;
+
+
+SYNTHESIZED_WIRE_14 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_20 AND SYNTHESIZED_WIRE_21 AND D1;
+
+
+SYNTHESIZED_WIRE_15 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_22 AND SYNTHESIZED_WIRE_18 AND D2;
+
+
+SYNTHESIZED_WIRE_16 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_22 AND SYNTHESIZED_WIRE_21 AND D3;
+
+
+Q <= SYNTHESIZED_WIRE_13 OR SYNTHESIZED_WIRE_14 OR SYNTHESIZED_WIRE_15 OR SYNTHESIZED_WIRE_16;
+
+
+SYNTHESIZED_WIRE_19 <= NOT(INH);
+
+
+
+SYNTHESIZED_WIRE_20 <= NOT(S1);
+
+
+
+SYNTHESIZED_WIRE_22 <= NOT(SYNTHESIZED_WIRE_20);
+
+
+
+END bdf_type;
\ No newline at end of file
diff --git a/FPGA_Quartus_13.1/Video/mux41_0.vhd b/FPGA_Quartus_13.1/Video/mux41_0.vhd
new file mode 100644
index 0000000..5fa086e
--- /dev/null
+++ b/FPGA_Quartus_13.1/Video/mux41_0.vhd
@@ -0,0 +1,54 @@
+-- Copyright (C) 1991-2014 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
+-- CREATED		"Mon Jan 11 09:20:56 2016"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY altera;
+USE altera.maxplus2.all; 
+
+LIBRARY work;
+
+ENTITY mux41_0 IS 
+PORT 
+( 
+	S0	:	IN	 STD_LOGIC;
+	S1	:	IN	 STD_LOGIC;
+	D0	:	IN	 STD_LOGIC;
+	INH	:	IN	 STD_LOGIC;
+	D1	:	IN	 STD_LOGIC;
+	Q	:	OUT	 STD_LOGIC
+); 
+END mux41_0;
+
+ARCHITECTURE bdf_type OF mux41_0 IS 
+BEGIN 
+
+-- instantiate macrofunction 
+
+b2v_inst40 : work.mux41
+PORT MAP(S0 => S0,
+		 S1 => S1,
+		 D0 => D0,
+		 INH => INH,
+		 D1 => D1,
+         D2 => '0',
+         D3 => '0',
+		 Q => Q);
+
+END bdf_type; 
\ No newline at end of file
diff --git a/FPGA_Quartus_13.1/Video/mux41_1.vhd b/FPGA_Quartus_13.1/Video/mux41_1.vhd
new file mode 100644
index 0000000..0feca80
--- /dev/null
+++ b/FPGA_Quartus_13.1/Video/mux41_1.vhd
@@ -0,0 +1,54 @@
+-- Copyright (C) 1991-2014 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
+-- CREATED		"Mon Jan 11 09:20:56 2016"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY altera;
+USE altera.maxplus2.all; 
+
+LIBRARY work;
+
+ENTITY mux41_1 IS 
+PORT 
+( 
+	S0	:	IN	 STD_LOGIC;
+	S1	:	IN	 STD_LOGIC;
+	D0	:	IN	 STD_LOGIC;
+	INH	:	IN	 STD_LOGIC;
+	D1	:	IN	 STD_LOGIC;
+	Q	:	OUT	 STD_LOGIC
+); 
+END mux41_1;
+
+ARCHITECTURE bdf_type OF mux41_1 IS 
+BEGIN 
+
+-- instantiate macrofunction 
+
+b2v_inst41 : work.mux41
+PORT MAP(S0 => S0,
+		 S1 => S1,
+		 D0 => D0,
+		 INH => INH,
+		 D1 => D1,
+         D2 => '0',
+         D3 => '0',
+		 Q => Q);
+
+END bdf_type; 
\ No newline at end of file
diff --git a/FPGA_Quartus_13.1/Video/mux41_2.vhd b/FPGA_Quartus_13.1/Video/mux41_2.vhd
new file mode 100644
index 0000000..6e8f4ae
--- /dev/null
+++ b/FPGA_Quartus_13.1/Video/mux41_2.vhd
@@ -0,0 +1,55 @@
+-- Copyright (C) 1991-2014 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
+-- CREATED		"Mon Jan 11 09:20:56 2016"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY altera;
+USE altera.maxplus2.all; 
+
+LIBRARY work;
+
+ENTITY mux41_2 IS 
+PORT 
+( 
+	S0	:	IN	 STD_LOGIC;
+	D2	:	IN	 STD_LOGIC;
+	S1	:	IN	 STD_LOGIC;
+	D0	:	IN	 STD_LOGIC;
+	INH	:	IN	 STD_LOGIC;
+	D1	:	IN	 STD_LOGIC;
+	Q	:	OUT	 STD_LOGIC
+); 
+END mux41_2;
+
+ARCHITECTURE bdf_type OF mux41_2 IS 
+BEGIN 
+
+-- instantiate macrofunction 
+
+b2v_inst42 : work.mux41
+PORT MAP(S0 => S0,
+		 D2 => D2,
+		 S1 => S1,
+		 D0 => D0,
+         D3 => '0',
+		 INH => INH,
+		 D1 => D1,
+		 Q => Q);
+
+END bdf_type; 
\ No newline at end of file
diff --git a/FPGA_Quartus_13.1/Video/mux41_3.vhd b/FPGA_Quartus_13.1/Video/mux41_3.vhd
new file mode 100644
index 0000000..a8c762c
--- /dev/null
+++ b/FPGA_Quartus_13.1/Video/mux41_3.vhd
@@ -0,0 +1,55 @@
+-- Copyright (C) 1991-2014 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
+-- CREATED		"Mon Jan 11 09:20:56 2016"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY altera;
+USE altera.maxplus2.all; 
+
+LIBRARY work;
+
+ENTITY mux41_3 IS 
+PORT 
+( 
+	S0	:	IN	 STD_LOGIC;
+	D2	:	IN	 STD_LOGIC;
+	S1	:	IN	 STD_LOGIC;
+	D0	:	IN	 STD_LOGIC;
+	INH	:	IN	 STD_LOGIC;
+	D1	:	IN	 STD_LOGIC;
+	Q	:	OUT	 STD_LOGIC
+); 
+END mux41_3;
+
+ARCHITECTURE bdf_type OF mux41_3 IS 
+BEGIN 
+
+-- instantiate macrofunction 
+
+b2v_inst43 : work.mux41
+PORT MAP(S0 => S0,
+		 D2 => D2,
+		 S1 => S1,
+		 D0 => D0,
+         D3 => '0',
+		 INH => INH,
+		 D1 => D1,
+		 Q => Q);
+
+END bdf_type; 
\ No newline at end of file
diff --git a/FPGA_Quartus_13.1/Video/mux41_4.vhd b/FPGA_Quartus_13.1/Video/mux41_4.vhd
new file mode 100644
index 0000000..f1c9027
--- /dev/null
+++ b/FPGA_Quartus_13.1/Video/mux41_4.vhd
@@ -0,0 +1,55 @@
+-- Copyright (C) 1991-2014 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
+-- CREATED		"Mon Jan 11 09:20:56 2016"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY altera;
+USE altera.maxplus2.all; 
+
+LIBRARY work;
+
+ENTITY mux41_4 IS 
+PORT 
+( 
+	S0	:	IN	 STD_LOGIC;
+	D2	:	IN	 STD_LOGIC;
+	S1	:	IN	 STD_LOGIC;
+	D0	:	IN	 STD_LOGIC;
+	INH	:	IN	 STD_LOGIC;
+	D1	:	IN	 STD_LOGIC;
+	Q	:	OUT	 STD_LOGIC
+); 
+END mux41_4;
+
+ARCHITECTURE bdf_type OF mux41_4 IS 
+BEGIN 
+
+-- instantiate macrofunction 
+
+b2v_inst44 : work.mux41
+PORT MAP(S0 => S0,
+		 D2 => D2,
+		 S1 => S1,
+		 D0 => D0,
+         D3 => '0',
+		 INH => INH,
+		 D1 => D1,
+		 Q => Q);
+
+END bdf_type; 
\ No newline at end of file
diff --git a/FPGA_Quartus_13.1/Video/mux41_5.vhd b/FPGA_Quartus_13.1/Video/mux41_5.vhd
new file mode 100644
index 0000000..0fc955e
--- /dev/null
+++ b/FPGA_Quartus_13.1/Video/mux41_5.vhd
@@ -0,0 +1,56 @@
+-- Copyright (C) 1991-2014 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
+-- CREATED		"Mon Jan 11 09:20:56 2016"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY altera;
+USE altera.maxplus2.all; 
+
+LIBRARY work;
+
+ENTITY mux41_5 IS 
+PORT 
+( 
+	S0	:	IN	 STD_LOGIC;
+	D2	:	IN	 STD_LOGIC;
+	S1	:	IN	 STD_LOGIC;
+	D0	:	IN	 STD_LOGIC;
+	INH	:	IN	 STD_LOGIC;
+	D1	:	IN	 STD_LOGIC;
+	Q	:	OUT	 STD_LOGIC
+); 
+END mux41_5;
+
+
+ARCHITECTURE bdf_type OF mux41_5 IS 
+BEGIN 
+
+-- instantiate macrofunction 
+
+b2v_inst45 : work.mux41
+PORT MAP(S0 => S0,
+		 D2 => D2,
+		 S1 => S1,
+		 D0 => D0,
+         D3 => '0',
+		 INH => INH,
+		 D1 => D1,
+		 Q => Q);
+
+END bdf_type; 
\ No newline at end of file
diff --git a/FPGA_Quartus_13.1/Video/video.bdf b/FPGA_Quartus_13.1/Video/video.bdf
deleted file mode 100644
index 83f2f08..0000000
--- a/FPGA_Quartus_13.1/Video/video.bdf
+++ /dev/null
@@ -1,10679 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 1991-2014 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Altera Program License 
-Subscription Agreement, Altera MegaCore Function License 
-Agreement, or other applicable license agreement, including, 
-without limitation, that your use is for the sole purpose of 
-programming logic devices manufactured by Altera and sold by 
-Altera or its authorized distributors.  Please refer to the 
-applicable agreement for further details.
-*/
-(header "graphic" (version "1.4"))
-(properties
-	(page_setup "header_footer\nDate: %D\n%f\nProject: %j\n\nPage %p of %P\nRevision: %a\nmargin\n1\n1\n1\n1\norientation\n2\npaper_size\n9\npaper_source\n15\nfit_page_wide\n1\nfit_page_tall\n1\n")
-)
-(pin
-	(input)
-	(rect 184 1192 352 1208)
-	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
-	(text "FB_ADR[31..0]" (rect 9 0 83 11)(font "Arial" ))
-	(pt 168 8)
-	(connected_pin (pt 0 0))
-	(drawing
-		(line (pt 92 12)(pt 117 12))
-		(line (pt 92 4)(pt 117 4))
-		(line (pt 121 8)(pt 168 8))
-		(line (pt 92 12)(pt 92 4))
-		(line (pt 117 4)(pt 121 8))
-		(line (pt 117 12)(pt 121 8))
-	)
-	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
-)
-(pin
-	(input)
-	(rect 184 1248 352 1264)
-	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
-	(text "MAIN_CLK" (rect 9 0 66 11)(font "Arial" ))
-	(pt 168 8)
-	(connected_pin (pt 0 0))
-	(drawing
-		(line (pt 92 12)(pt 117 12))
-		(line (pt 92 4)(pt 117 4))
-		(line (pt 121 8)(pt 168 8))
-		(line (pt 92 12)(pt 92 4))
-		(line (pt 117 4)(pt 121 8))
-		(line (pt 117 12)(pt 121 8))
-	)
-	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
-)
-(pin
-	(input)
-	(rect 184 1352 352 1368)
-	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
-	(text "nFB_CS1" (rect 9 0 57 11)(font "Arial" ))
-	(pt 168 8)
-	(connected_pin (pt 0 0))
-	(drawing
-		(line (pt 92 12)(pt 117 12))
-		(line (pt 92 4)(pt 117 4))
-		(line (pt 121 8)(pt 168 8))
-		(line (pt 92 12)(pt 92 4))
-		(line (pt 117 4)(pt 121 8))
-		(line (pt 117 12)(pt 121 8))
-	)
-	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
-)
-(pin
-	(input)
-	(rect 184 1384 352 1400)
-	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
-	(text "nFB_CS2" (rect 9 0 58 11)(font "Arial" ))
-	(pt 168 8)
-	(connected_pin (pt 0 0))
-	(drawing
-		(line (pt 92 12)(pt 117 12))
-		(line (pt 92 4)(pt 117 4))
-		(line (pt 121 8)(pt 168 8))
-		(line (pt 92 12)(pt 92 4))
-		(line (pt 117 4)(pt 121 8))
-		(line (pt 117 12)(pt 121 8))
-	)
-	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
-)
-(pin
-	(input)
-	(rect 184 1416 352 1432)
-	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
-	(text "nFB_CS3" (rect 9 0 58 11)(font "Arial" ))
-	(pt 168 8)
-	(connected_pin (pt 0 0))
-	(drawing
-		(line (pt 92 12)(pt 117 12))
-		(line (pt 92 4)(pt 117 4))
-		(line (pt 121 8)(pt 168 8))
-		(line (pt 92 12)(pt 92 4))
-		(line (pt 117 4)(pt 121 8))
-		(line (pt 117 12)(pt 121 8))
-	)
-	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
-)
-(pin
-	(input)
-	(rect 184 1448 352 1464)
-	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
-	(text "nFB_WR" (rect 9 0 55 11)(font "Arial" ))
-	(pt 168 8)
-	(connected_pin (pt 0 0))
-	(drawing
-		(line (pt 92 12)(pt 117 12))
-		(line (pt 92 4)(pt 117 4))
-		(line (pt 121 8)(pt 168 8))
-		(line (pt 92 12)(pt 92 4))
-		(line (pt 117 4)(pt 121 8))
-		(line (pt 117 12)(pt 121 8))
-	)
-	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
-)
-(pin
-	(input)
-	(rect 184 1480 352 1496)
-	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
-	(text "FB_SIZE0" (rect 9 0 60 11)(font "Arial" ))
-	(pt 168 8)
-	(connected_pin (pt 0 0))
-	(drawing
-		(line (pt 92 12)(pt 117 12))
-		(line (pt 92 4)(pt 117 4))
-		(line (pt 121 8)(pt 168 8))
-		(line (pt 92 12)(pt 92 4))
-		(line (pt 117 4)(pt 121 8))
-		(line (pt 117 12)(pt 121 8))
-	)
-	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
-)
-(pin
-	(input)
-	(rect 184 1512 352 1528)
-	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
-	(text "FB_SIZE1" (rect 9 0 59 11)(font "Arial" ))
-	(pt 168 8)
-	(connected_pin (pt 0 0))
-	(drawing
-		(line (pt 92 12)(pt 117 12))
-		(line (pt 92 4)(pt 117 4))
-		(line (pt 121 8)(pt 168 8))
-		(line (pt 92 12)(pt 92 4))
-		(line (pt 117 4)(pt 121 8))
-		(line (pt 117 12)(pt 121 8))
-	)
-	(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
-)
-(pin
-	(input)
-	(rect 184 1544 352 1560)
-	(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
-	(text "nRSTO" (rect 9 0 47 11)(font "Arial" ))
-	(pt 168 8)
-	(connected_pin (pt 0 0))
-	(drawing
-		(line (pt 92 12)(pt 117 12))
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-	(mapper
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-	(mapper
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-	(mapper
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-	(mapper
-		(pt 352 472)
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-	(mapper
-		(pt 352 448)
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-	(mapper
-		(pt 352 528)
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-	(mapper
-		(pt 352 320)
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-	(mapper
-		(pt 352 576)
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-	(mapper
-		(pt 352 400)
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-	(mapper
-		(pt 352 376)
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-	(mapper
-		(pt 352 352)
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-	(mapper
-		(pt 352 504)
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-	(mapper
-		(pt 352 296)
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-	(mapper
-		(pt 352 424)
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-	(mapper
-		(pt 352 552)
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-	(mapper
-		(pt 352 752)
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-	(mapper
-		(pt 352 776)
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-	(mapper
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-	(mapper
-		(pt 0 496)
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-	(mapper
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-	(mapper
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-	(mapper
-		(pt 352 216)
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-	(mapper
-		(pt 352 40)
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-(connector
-	(text "CLUT_MUX_ADR[3..0]" (rect 2722 2880 2835 2891)(font "Arial" ))
-	(pt 2712 2896)
-	(pt 2904 2896)
-	(bus)
-)
-(connector
-	(pt 792 1648)
-	(pt 920 1648)
-	(bus)
-)
-(connector
-	(pt 792 1792)
-	(pt 920 1792)
-	(bus)
-)
-(connector
-	(pt 792 1928)
-	(pt 920 1928)
-	(bus)
-)
-(connector
-	(pt 792 2064)
-	(pt 920 2064)
-	(bus)
-)
-(connector
-	(text "FB_LE0" (rect 826 1664 867 1675)(font "Arial" ))
-	(pt 920 1680)
-	(pt 816 1680)
-)
-(connector
-	(text "FB_LE1" (rect 834 1808 874 1819)(font "Arial" ))
-	(pt 920 1824)
-	(pt 824 1824)
-)
-(connector
-	(text "FB_LE2" (rect 834 1944 875 1955)(font "Arial" ))
-	(pt 920 1960)
-	(pt 824 1960)
-)
-(connector
-	(text "FB_LE3" (rect 834 2080 875 2091)(font "Arial" ))
-	(pt 920 2096)
-	(pt 824 2096)
-)
-(connector
-	(text "DDR_SYNC_66M" (rect 834 1648 923 1659)(font "Arial" ))
-	(pt 824 1664)
-	(pt 920 1664)
-)
-(connector
-	(text "DDR_SYNC_66M" (rect 834 1792 923 1803)(font "Arial" ))
-	(pt 824 1808)
-	(pt 920 1808)
-)
-(connector
-	(text "DDR_SYNC_66M" (rect 834 1928 923 1939)(font "Arial" ))
-	(pt 824 1944)
-	(pt 920 1944)
-)
-(connector
-	(text "DDR_SYNC_66M" (rect 834 2064 923 2075)(font "Arial" ))
-	(pt 824 2080)
-	(pt 920 2080)
-)
-(connector
-	(pt 792 1792)
-	(pt 792 1928)
-	(bus)
-)
-(connector
-	(pt 792 1928)
-	(pt 792 2064)
-	(bus)
-)
-(connector
-	(pt 792 1432)
-	(pt 792 1552)
-	(bus)
-)
-(connector
-	(pt 792 1552)
-	(pt 792 1648)
-	(bus)
-)
-(connector
-	(pt 792 1648)
-	(pt 792 1792)
-	(bus)
-)
-(connector
-	(text "FIFO_RDE" (rect 1450 1408 1506 1419)(font "Arial" ))
-	(pt 1440 1424)
-	(pt 1536 1424)
-)
-(connector
-	(text "VDP_IN[63..32]" (rect 1114 1392 1190 1403)(font "Arial" ))
-	(pt 1104 1408)
-	(pt 1192 1408)
-	(bus)
-)
-(connector
-	(pt 1328 2856)
-	(pt 1360 2856)
-)
-(connector
-	(pt 1360 2904)
-	(pt 1328 2904)
-)
-(connector
-	(pt 1384 2840)
-	(pt 1384 2824)
-)
-(connector
-	(pt 1384 2880)
-	(pt 1384 2888)
-)
-(connector
-	(pt 1344 2880)
-	(pt 1384 2880)
-)
-(connector
-	(pt 1344 2928)
-	(pt 1384 2928)
-)
-(connector
-	(pt 1384 2928)
-	(pt 1384 2936)
-)
-(connector
-	(pt 1328 3008)
-	(pt 1360 3008)
-)
-(connector
-	(pt 1384 2984)
-	(pt 1384 2992)
-)
-(connector
-	(text "VDQS0" (rect 1418 2840 1456 2851)(font "Arial" ))
-	(pt 1408 2856)
-	(pt 1520 2856)
-)
-(connector
-	(text "VDQS1" (rect 1418 2888 1455 2899)(font "Arial" ))
-	(pt 1408 2904)
-	(pt 1520 2904)
-)
-(connector
-	(text "VDQS2" (rect 1418 2936 1456 2947)(font "Arial" ))
-	(pt 1408 2952)
-	(pt 1520 2952)
-)
-(connector
-	(text "VDQS3" (rect 1418 2992 1456 3003)(font "Arial" ))
-	(pt 1408 3008)
-	(pt 1520 3008)
-)
-(connector
-	(pt 1344 2984)
-	(pt 1384 2984)
-)
-(connector
-	(text "FB_DDR[63..32]" (rect 1074 1936 1155 1947)(font "Arial" ))
-	(pt 1064 1952)
-	(pt 1160 1952)
-	(bus)
-)
-(connector
-	(text "FB_DDR[31..0]" (rect 1074 2072 1149 2083)(font "Arial" ))
-	(pt 1064 2088)
-	(pt 1160 2088)
-	(bus)
-)
-(connector
-	(text "FB_DDR[95..64]" (rect 1074 1800 1155 1811)(font "Arial" ))
-	(pt 1064 1816)
-	(pt 1160 1816)
-	(bus)
-)
-(connector
-	(text "FB_DDR[127..96]" (rect 1074 1656 1161 1667)(font "Arial" ))
-	(pt 1064 1672)
-	(pt 1160 1672)
-	(bus)
-)
-(connector
-	(text "SR_FIFO_WRE" (rect 842 2280 922 2291)(font "Arial" ))
-	(pt 920 2296)
-	(pt 832 2296)
-)
-(connector
-	(text "VDVZ[127..0]" (rect 810 2920 876 2931)(font "Arial" ))
-	(pt 800 2936)
-	(pt 888 2936)
-	(bus)
-)
-(connector
-	(text "DDRCLK0" (rect 842 2160 895 2171)(font "Arial" ))
-	(pt 832 2176)
-	(pt 920 2176)
-)
-(connector
-	(text "SR_DDR_FB" (rect 850 2176 917 2187)(font "Arial" ))
-	(pt 920 2192)
-	(pt 840 2192)
-)
-(connector
-	(pt 920 1312)
-	(pt 960 1312)
-	(bus)
-)
-(connector
-	(text "VDP_IN[31..0]" (rect 1114 1512 1184 1523)(font "Arial" ))
-	(pt 1104 1528)
-	(pt 1192 1528)
-	(bus)
-)
-(connector
-	(text "DDR_FB1" (rect 1106 1304 1156 1315)(font "Arial" ))
-	(pt 1104 1320)
-	(pt 1176 1320)
-)
-(connector
-	(text "DDR_FB0" (rect 1106 1544 1157 1555)(font "Arial" ))
-	(pt 1104 1560)
-	(pt 1176 1560)
-)
-(connector
-	(text "FIFO_WRE" (rect 1074 2280 1133 2291)(font "Arial" ))
-	(pt 1064 2296)
-	(pt 1144 2296)
-)
-(connector
-	(pt 432 1808)
-	(pt 472 1808)
-)
-(connector
-	(text "BLITTER_TA" (rect 274 1792 342 1803)(font "Arial" ))
-	(pt 264 1808)
-	(pt 368 1808)
-)
-(connector
-	(pt 360 1816)
-	(pt 360 1832)
-)
-(connector
-	(pt 368 1816)
-	(pt 360 1816)
-)
-(connector
-	(pt 360 1800)
-	(pt 360 1784)
-)
-(connector
-	(pt 368 1800)
-	(pt 360 1800)
-)
-(connector
-	(text "VIDEO_DDR_TA" (rect 258 1768 345 1779)(font "Arial" ))
-	(pt 360 1784)
-	(pt 264 1784)
-)
-(connector
-	(text "VDP_OUT[63..0]" (rect 1506 1328 1588 1339)(font "Arial" ))
-	(pt 1584 1344)
-	(pt 1496 1344)
-	(bus)
-)
-(connector
-	(text "FB_DDR[127..64]" (rect 1258 1352 1345 1363)(font "Arial" ))
-	(pt 1224 1368)
-	(pt 1344 1368)
-	(bus)
-)
-(connector
-	(text "BLITTER_DOUT[63..0]" (rect 1234 1304 1347 1315)(font "Arial" ))
-	(pt 1224 1320)
-	(pt 1344 1320)
-	(bus)
-)
-(connector
-	(text "BLITTER_DOUT[127..64]" (rect 1234 1320 1360 1331)(font "Arial" ))
-	(pt 1224 1336)
-	(pt 1344 1336)
-	(bus)
-)
-(connector
-	(text "FB_DDR[63..0]" (rect 1258 1336 1333 1347)(font "Arial" ))
-	(pt 1224 1352)
-	(pt 1344 1352)
-	(bus)
-)
-(connector
-	(text "VDR[31..0]" (rect 930 1176 984 1187)(font "Arial" ))
-	(pt 920 1192)
-	(pt 1008 1192)
-	(bus)
-)
-(connector
-	(text "DDRWR_D_SEL[1..0]" (rect 1298 1400 1406 1411)(font "Arial" ))
-	(pt 1424 1416)
-	(pt 1288 1416)
-	(bus)
-)
-(connector
-	(pt 1424 1392)
-	(pt 1424 1416)
-	(bus)
-)
-(connector
-	(text "DDR_FB0" (rect 1106 1424 1157 1435)(font "Arial" ))
-	(pt 1104 1440)
-	(pt 1176 1440)
-)
-(connector
-	(text "VDP_IN[31..0]" (rect 1114 1272 1184 1283)(font "Arial" ))
-	(pt 1104 1288)
-	(pt 1192 1288)
-	(bus)
-)
-(connector
-	(text "DDRCLK0" (rect 1114 1528 1167 1539)(font "Arial" ))
-	(pt 1104 1544)
-	(pt 1176 1544)
-)
-(connector
-	(text "DDRCLK0" (rect 1114 1408 1167 1419)(font "Arial" ))
-	(pt 1104 1424)
-	(pt 1176 1424)
-)
-(connector
-	(text "DDRCLK0" (rect 1114 1288 1167 1299)(font "Arial" ))
-	(pt 1104 1304)
-	(pt 1176 1304)
-)
-(connector
-	(text "DDRCLK0" (rect 1650 1384 1703 1395)(font "Arial" ))
-	(pt 1712 1400)
-	(pt 1640 1400)
-)
-(connector
-	(text "DDRCLK0" (rect 810 2936 863 2947)(font "Arial" ))
-	(pt 800 2952)
-	(pt 888 2952)
-)
-(connector
-	(text "DDRCLK0" (rect 842 2264 895 2275)(font "Arial" ))
-	(pt 832 2280)
-	(pt 920 2280)
-)
-(connector
-	(text "DDR_FB[4..0]" (rect 1074 2176 1142 2187)(font "Arial" ))
-	(pt 1064 2192)
-	(pt 1168 2192)
-	(bus)
-)
-(connector
-	(text "FIFO_D[127..0]" (rect 2170 1416 2246 1427)(font "Arial" ))
-	(pt 2168 1432)
-	(pt 2232 1432)
-	(bus)
-)
-(connector
-	(pt 2632 2208)
-	(pt 2512 2208)
-)
-(connector
-	(pt 2632 1728)
-	(pt 2512 1728)
-)
-(connector
-	(pt 2632 1888)
-	(pt 2512 1888)
-)
-(connector
-	(pt 2512 1728)
-	(pt 2512 1888)
-)
-(connector
-	(pt 2632 2048)
-	(pt 2512 2048)
-)
-(connector
-	(pt 2512 1888)
-	(pt 2512 2048)
-)
-(connector
-	(pt 2632 1248)
-	(pt 2512 1248)
-)
-(connector
-	(pt 2632 1408)
-	(pt 2512 1408)
-)
-(connector
-	(pt 2632 1568)
-	(pt 2512 1568)
-)
-(connector
-	(pt 2512 1568)
-	(pt 2512 1728)
-)
-(connector
-	(text "PIXEL_CLK" (rect 1634 1432 1695 1443)(font "Arial" ))
-	(pt 1640 1448)
-	(pt 1712 1448)
-)
-(connector
-	(text "PIXEL_CLK" (rect 1938 1424 1999 1435)(font "Arial" ))
-	(pt 1928 1440)
-	(pt 2000 1440)
-)
-(connector
-	(text "FIFO_RDE" (rect 1914 1440 1970 1451)(font "Arial" ))
-	(pt 1904 1456)
-	(pt 2000 1456)
-)
-(connector
-	(text "PIXEL_CLK" (rect 2018 1552 2079 1563)(font "Arial" ))
-	(pt 2008 1568)
-	(pt 2080 1568)
-)
-(connector
-	(text "FIFO_RDE" (rect 1994 1536 2050 1547)(font "Arial" ))
-	(pt 1984 1552)
-	(pt 2080 1552)
-)
-(connector
-	(pt 2512 1408)
-	(pt 2512 1552)
-)
-(connector
-	(pt 2512 1552)
-	(pt 2512 1568)
-)
-(connector
-	(pt 2144 1552)
-	(pt 2512 1552)
-)
-(connector
-	(pt 2512 2368)
-	(pt 2632 2368)
-)
-(connector
-	(pt 2512 2048)
-	(pt 2512 2208)
-)
-(connector
-	(pt 2512 2208)
-	(pt 2512 2368)
-)
-(connector
-	(text "DDR_WR" (rect 1290 2808 1339 2819)(font "Arial" ))
-	(pt 1280 2824)
-	(pt 1344 2824)
-)
-(connector
-	(pt 1344 2824)
-	(pt 1384 2824)
-)
-(connector
-	(pt 1344 2824)
-	(pt 1344 2880)
-)
-(connector
-	(pt 1344 2880)
-	(pt 1344 2928)
-)
-(connector
-	(pt 1344 2928)
-	(pt 1344 2984)
-)
-(connector
-	(pt 1328 2856)
-	(pt 1328 2904)
-)
-(connector
-	(pt 1328 2904)
-	(pt 1328 2952)
-)
-(connector
-	(pt 1328 2952)
-	(pt 1328 3008)
-)
-(connector
-	(text "DDRCLK0" (rect 1218 2936 1271 2947)(font "Arial" ))
-	(pt 1208 2952)
-	(pt 1328 2952)
-)
-(connector
-	(pt 1328 2952)
-	(pt 1360 2952)
-)
-(connector
-	(text "VDP_OUT[63..32]" (rect 1234 1520 1323 1531)(font "Arial" ))
-	(pt 1312 1536)
-	(pt 1224 1536)
-	(bus)
-)
-(connector
-	(text "VDP_OUT[31..0]" (rect 1234 1536 1316 1547)(font "Arial" ))
-	(pt 1312 1552)
-	(pt 1224 1552)
-	(bus)
-)
-(connector
-	(text "VDP_IN[63..32]" (rect 1562 1536 1638 1547)(font "Arial" ))
-	(pt 1552 1552)
-	(pt 1640 1552)
-	(bus)
-)
-(connector
-	(text "VD[31..0]" (rect 1578 1552 1624 1563)(font "Arial" ))
-	(pt 1640 1568)
-	(pt 1552 1568)
-	(bus)
-)
-(connector
-	(text "DDRCLK3" (rect 1250 1584 1303 1595)(font "Arial" ))
-	(pt 1312 1600)
-	(pt 1240 1600)
-)
-(connector
-	(text "VDP_IN[31..0]" (rect 1554 1520 1624 1531)(font "Arial" ))
-	(pt 1552 1536)
-	(pt 1632 1536)
-	(bus)
-)
-(connector
-	(text "DDRCLK1" (rect 1250 1568 1301 1579)(font "Arial" ))
-	(pt 1312 1584)
-	(pt 1240 1584)
-)
-(connector
-	(text "VDR[31..0]" (rect 1858 1568 1912 1579)(font "Arial" ))
-	(pt 1848 1584)
-	(pt 1936 1584)
-	(bus)
-)
-(connector
-	(text "DDR_SYNC_66M" (rect 1602 1584 1691 1595)(font "Arial" ))
-	(pt 1592 1600)
-	(pt 1688 1600)
-)
-(connector
-	(pt 1552 1584)
-	(pt 1688 1584)
-	(bus)
-)
-(connector
-	(text "VDOUT_OE" (rect 1242 1552 1304 1563)(font "Arial" ))
-	(pt 1232 1568)
-	(pt 1312 1568)
-)
-(connector
-	(text "DDRCLK3" (rect 1170 2472 1223 2483)(font "Arial" ))
-	(pt 1160 2488)
-	(pt 1240 2488)
-)
-(connector
-	(text "VDM[3..0]" (rect 1482 2440 1531 2451)(font "Arial" ))
-	(pt 1536 2456)
-	(pt 1472 2456)
-	(bus)
-)
-(connector
-	(text "VDMP[7..4]" (rect 1170 2440 1226 2451)(font "Arial" ))
-	(pt 1160 2456)
-	(pt 1240 2456)
-	(bus)
-)
-(connector
-	(text "VDMP[3..0]" (rect 1170 2456 1226 2467)(font "Arial" ))
-	(pt 1160 2472)
-	(pt 1240 2472)
-	(bus)
-)
-(connector
-	(text "VDMP[7..0]" (rect 1242 2672 1298 2683)(font "Arial" ))
-	(pt 1232 2688)
-	(pt 1304 2688)
-	(bus)
-)
-(connector
-	(text "DDRWR_D_SEL0" (rect 1066 2768 1156 2779)(font "Arial" ))
-	(pt 1056 2784)
-	(pt 1152 2784)
-)
-(connector
-	(text "DDRCLK3" (rect 930 2784 983 2795)(font "Arial" ))
-	(pt 928 2800)
-	(pt 992 2800)
-)
-(connector
-	(text "SR_VDMP[7..0]" (rect 1002 2656 1079 2667)(font "Arial" ))
-	(pt 992 2672)
-	(pt 1088 2672)
-	(bus)
-)
-(connector
-	(text "SR_DDRWR_D_SEL" (rect 890 2768 996 2779)(font "Arial" ))
-	(pt 888 2784)
-	(pt 992 2784)
-)
-(connector
-	(text "VDOUT_OE" (rect 1386 2328 1448 2339)(font "Arial" ))
-	(pt 1376 2344)
-	(pt 1456 2344)
-)
-(connector
-	(text "DDR_WR" (rect 1258 2336 1307 2347)(font "Arial" ))
-	(pt 1248 2352)
-	(pt 1312 2352)
-)
-(connector
-	(text "SR_DDR_WR" (rect 1242 2320 1313 2331)(font "Arial" ))
-	(pt 1248 2336)
-	(pt 1312 2336)
-)
-(connector
-	(text "DDRCLK3" (rect 906 2400 959 2411)(font "Arial" ))
-	(pt 904 2416)
-	(pt 968 2416)
-)
-(connector
-	(text "SR_DDR_WR" (rect 898 2384 969 2395)(font "Arial" ))
-	(pt 896 2400)
-	(pt 968 2400)
-)
-(connector
-	(text "DDR_WR" (rect 1042 2384 1091 2395)(font "Arial" ))
-	(pt 1032 2400)
-	(pt 1096 2400)
-)
-(connector
-	(text "DDRCLK2" (rect 1018 2672 1071 2683)(font "Arial" ))
-	(pt 1008 2688)
-	(pt 1088 2688)
-)
-(connector
-	(pt 1696 2840)
-	(pt 1696 2816)
-	(bus)
-)
-(connector
-	(pt 1832 2760)
-	(pt 1768 2760)
-	(bus)
-)
-(connector
-	(pt 1808 2776)
-	(pt 1832 2776)
-)
-(connector
-	(pt 1808 2840)
-	(pt 1808 2776)
-)
-(connector
-	(text "PIXEL_CLK" (rect 1546 2776 1607 2787)(font "Arial" ))
-	(pt 1536 2792)
-	(pt 1616 2792)
-)
-(connector
-	(text "CLUT_MUX_ADR[2..0]" (rect 2130 2744 2243 2755)(font "Arial" ))
-	(pt 2304 2760)
-	(pt 2120 2760)
-	(bus)
-)
-(connector
-	(text "PIXEL_CLK" (rect 2338 2744 2399 2755)(font "Arial" ))
-	(pt 2400 2760)
-	(pt 2328 2760)
-)
-(connector
-	(pt 2376 2648)
-	(pt 2416 2648)
-	(bus)
-)
-(connector
-	(pt 2400 2664)
-	(pt 2416 2664)
-)
-(connector
-	(pt 2400 2760)
-	(pt 2400 2664)
-)
-(connector
-	(pt 2304 2760)
-	(pt 2304 2736)
-	(bus)
-)
-(connector
-	(text "PIXEL_CLK" (rect 2162 2696 2223 2707)(font "Arial" ))
-	(pt 2224 2712)
-	(pt 2152 2712)
-)
-(connector
-	(text "FIFO_D[7..0]" (rect 2730 2568 2793 2579)(font "Arial" ))
-	(pt 2824 2584)
-	(pt 2720 2584)
-	(bus)
-)
-(connector
-	(text "FIFO_D[15..8]" (rect 2730 2584 2799 2595)(font "Arial" ))
-	(pt 2824 2600)
-	(pt 2720 2600)
-	(bus)
-)
-(connector
-	(text "FIFO_D[23..16]" (rect 2730 2600 2806 2611)(font "Arial" ))
-	(pt 2824 2616)
-	(pt 2720 2616)
-	(bus)
-)
-(connector
-	(text "FIFO_D[31..24]" (rect 2730 2616 2806 2627)(font "Arial" ))
-	(pt 2824 2632)
-	(pt 2720 2632)
-	(bus)
-)
-(connector
-	(text "FIFO_D[39..32]" (rect 2730 2632 2806 2643)(font "Arial" ))
-	(pt 2824 2648)
-	(pt 2720 2648)
-	(bus)
-)
-(connector
-	(text "FIFO_D[47..40]" (rect 2730 2648 2806 2659)(font "Arial" ))
-	(pt 2824 2664)
-	(pt 2720 2664)
-	(bus)
-)
-(connector
-	(text "FIFO_D[55..48]" (rect 2730 2664 2806 2675)(font "Arial" ))
-	(pt 2824 2680)
-	(pt 2720 2680)
-	(bus)
-)
-(connector
-	(text "FIFO_D[63..56]" (rect 2730 2680 2806 2691)(font "Arial" ))
-	(pt 2824 2696)
-	(pt 2720 2696)
-	(bus)
-)
-(connector
-	(text "FIFO_D[71..64]" (rect 2730 2696 2806 2707)(font "Arial" ))
-	(pt 2824 2712)
-	(pt 2720 2712)
-	(bus)
-)
-(connector
-	(text "FIFO_D[79..72]" (rect 2730 2712 2806 2723)(font "Arial" ))
-	(pt 2824 2728)
-	(pt 2720 2728)
-	(bus)
-)
-(connector
-	(text "FIFO_D[87..80]" (rect 2730 2728 2806 2739)(font "Arial" ))
-	(pt 2824 2744)
-	(pt 2720 2744)
-	(bus)
-)
-(connector
-	(text "FIFO_D[95..88]" (rect 2730 2744 2806 2755)(font "Arial" ))
-	(pt 2824 2760)
-	(pt 2720 2760)
-	(bus)
-)
-(connector
-	(text "FIFO_D[103..96]" (rect 2730 2760 2812 2771)(font "Arial" ))
-	(pt 2824 2776)
-	(pt 2720 2776)
-	(bus)
-)
-(connector
-	(text "FIFO_D[111..104]" (rect 2730 2776 2818 2787)(font "Arial" ))
-	(pt 2824 2792)
-	(pt 2720 2792)
-	(bus)
-)
-(connector
-	(text "FIFO_D[119..112]" (rect 2730 2792 2818 2803)(font "Arial" ))
-	(pt 2824 2808)
-	(pt 2720 2808)
-	(bus)
-)
-(connector
-	(text "FIFO_D[127..120]" (rect 2730 2808 2818 2819)(font "Arial" ))
-	(pt 2824 2824)
-	(pt 2720 2824)
-	(bus)
-)
-(connector
-	(text "CCF[23..0]" (rect 3362 2752 3416 2763)(font "Arial" ))
-	(pt 3432 2768)
-	(pt 3352 2768)
-	(bus)
-)
-(connector
-	(text "CCS[23..0]" (rect 3362 2840 3416 2851)(font "Arial" ))
-	(pt 3432 2856)
-	(pt 3352 2856)
-	(bus)
-)
-(connector
-	(pt 2904 2896)
-	(pt 2904 2864)
-	(bus)
-)
-(connector
-	(text "ZR_C8[7..0]" (rect 3232 2712 3292 2723)(font "Arial" ))
-	(pt 3232 2728)
-	(pt 3304 2728)
-	(bus)
-)
-(connector
-	(pt 3088 2712)
-	(pt 2968 2712)
-	(bus)
-)
-(connector
-	(text "PIXEL_CLK" (rect 2746 2824 2807 2835)(font "Arial" ))
-	(pt 2824 2840)
-	(pt 2736 2840)
-)
-(connector
-	(pt 3576 2784)
-	(pt 3672 2784)
-	(bus)
-)
-(connector
-	(pt 3576 2872)
-	(pt 3672 2872)
-	(bus)
-)
-(connector
-	(pt 3816 2800)
-	(pt 3888 2800)
-	(bus)
-)
-(connector
-	(pt 3888 2888)
-	(pt 3816 2888)
-	(bus)
-)
-(connector
-	(text "PIXEL_CLK" (rect 3034 2712 3095 2723)(font "Arial" ))
-	(pt 3032 2728)
-	(pt 3088 2728)
-)
-(connector
-	(text "PIXEL_CLK" (rect 3618 2784 3679 2795)(font "Arial" ))
-	(pt 3616 2800)
-	(pt 3672 2800)
-)
-(connector
-	(text "PIXEL_CLK" (rect 3618 2872 3679 2883)(font "Arial" ))
-	(pt 3616 2888)
-	(pt 3672 2888)
-)
-(connector
-	(text "PIXEL_CLK" (rect 3378 2856 3439 2867)(font "Arial" ))
-	(pt 3376 2872)
-	(pt 3432 2872)
-)
-(connector
-	(text "PIXEL_CLK" (rect 3378 2768 3439 2779)(font "Arial" ))
-	(pt 3376 2784)
-	(pt 3432 2784)
-)
-(connector
-	(text "CC16[18..16],CC16[9..8],CC16[2..0]" (rect 2530 2728 2707 2739)(font "Arial" ))
-	(pt 2696 2744)
-	(pt 2520 2744)
-	(bus)
-)
-(connector
-	(text "CC24[31..0]" (rect 1986 2760 2045 2771)(font "Arial" ))
-	(pt 1976 2776)
-	(pt 2072 2776)
-	(bus)
-)
-(connector
-	(text "ZR_C8B[0]" (rect 3282 2952 3337 2963)(font "Arial" ))
-	(pt 3272 2968)
-	(pt 3344 2968)
-)
-(connector
-	(text "COLOR1" (rect 3154 3008 3200 3019)(font "Arial" ))
-	(pt 3232 3024)
-	(pt 3144 3024)
-)
-(connector
-	(text "ZR_C8[7..1]" (rect 3090 3072 3150 3083)(font "Arial" ))
-	(pt 3080 3088)
-	(pt 3160 3088)
-	(bus)
-)
-(connector
-	(pt 3232 3000)
-	(pt 3232 3024)
-)
-(connector
-	(pt 3232 3024)
-	(pt 3232 3064)
-)
-(connector
-	(text "ZR_C8B[7..1]" (rect 3306 3080 3373 3091)(font "Arial" ))
-	(pt 3296 3096)
-	(pt 3392 3096)
-	(bus)
-)
-(connector
-	(pt 3072 3104)
-	(pt 3160 3104)
-	(bus)
-)
-(connector
-	(text "ZR_C8[0]" (rect 3146 2960 3193 2971)(font "Arial" ))
-	(pt 3136 2976)
-	(pt 3192 2976)
-)
-(connector
-	(text "CLUT_ADR0" (rect 2842 2944 2908 2955)(font "Arial" ))
-	(pt 2832 2960)
-	(pt 2912 2960)
-)
-(connector
-	(text "PIXEL_CLK" (rect 2858 2960 2919 2971)(font "Arial" ))
-	(pt 2856 2976)
-	(pt 2912 2976)
-)
-(connector
-	(text "PIXEL_CLK" (rect 2994 2960 3055 2971)(font "Arial" ))
-	(pt 2992 2976)
-	(pt 3048 2976)
-)
-(connector
-	(pt 2976 2960)
-	(pt 3048 2960)
-)
-(connector
-	(pt 3112 2960)
-	(pt 3192 2960)
-)
-(connector
-	(text "MAIN_CLK" (rect 3370 2208 3427 2219)(font "Arial" ))
-	(pt 3448 2224)
-	(pt 3360 2224)
-)
-(connector
-	(text "PIXEL_CLK" (rect 3370 2224 3431 2235)(font "Arial" ))
-	(pt 3448 2240)
-	(pt 3360 2240)
-)
-(connector
-	(pt 3808 2112)
-	(pt 3808 2128)
-)
-(connector
-	(text "ACP_CLUT_RD" (rect 3722 2112 3803 2123)(font "Arial" ))
-	(pt 3808 2128)
-	(pt 3712 2128)
-)
-(connector
-	(pt 3328 2192)
-	(pt 3448 2192)
-)
-(connector
-	(pt 3704 2096)
-	(pt 3768 2096)
-	(bus)
-)
-(connector
-	(text "MAIN_CLK" (rect 3370 2416 3427 2427)(font "Arial" ))
-	(pt 3448 2432)
-	(pt 3360 2432)
-)
-(connector
-	(text "PIXEL_CLK" (rect 3370 2432 3431 2443)(font "Arial" ))
-	(pt 3448 2448)
-	(pt 3360 2448)
-)
-(connector
-	(pt 3808 2320)
-	(pt 3808 2336)
-)
-(connector
-	(text "ACP_CLUT_RD" (rect 3722 2320 3803 2331)(font "Arial" ))
-	(pt 3808 2336)
-	(pt 3712 2336)
-)
-(connector
-	(pt 3328 2400)
-	(pt 3448 2400)
-)
-(connector
-	(pt 3704 2304)
-	(pt 3768 2304)
-	(bus)
-)
-(connector
-	(text "MAIN_CLK" (rect 3370 2624 3427 2635)(font "Arial" ))
-	(pt 3448 2640)
-	(pt 3360 2640)
-)
-(connector
-	(text "PIXEL_CLK" (rect 3370 2640 3431 2651)(font "Arial" ))
-	(pt 3448 2656)
-	(pt 3360 2656)
-)
-(connector
-	(pt 3808 2528)
-	(pt 3808 2544)
-)
-(connector
-	(text "ACP_CLUT_RD" (rect 3722 2528 3803 2539)(font "Arial" ))
-	(pt 3808 2544)
-	(pt 3712 2544)
-)
-(connector
-	(pt 3328 2608)
-	(pt 3448 2608)
-)
-(connector
-	(pt 3704 2512)
-	(pt 3768 2512)
-	(bus)
-)
-(connector
-	(text "MAIN_CLK" (rect 3370 1560 3427 1571)(font "Arial" ))
-	(pt 3448 1576)
-	(pt 3360 1576)
-)
-(connector
-	(text "PIXEL_CLK" (rect 3370 1576 3431 1587)(font "Arial" ))
-	(pt 3448 1592)
-	(pt 3360 1592)
-)
-(connector
-	(pt 3840 1448)
-	(pt 3704 1448)
-	(bus)
-)
-(connector
-	(text "FB_AD[31..26]" (rect 3930 1432 4003 1443)(font "Arial" ))
-	(pt 3920 1448)
-	(pt 4032 1448)
-	(bus)
-)
-(connector
-	(text "MAIN_CLK" (rect 3370 1768 3427 1779)(font "Arial" ))
-	(pt 3448 1784)
-	(pt 3360 1784)
-)
-(connector
-	(text "PIXEL_CLK" (rect 3370 1784 3431 1795)(font "Arial" ))
-	(pt 3448 1800)
-	(pt 3360 1800)
-)
-(connector
-	(pt 3840 1656)
-	(pt 3704 1656)
-	(bus)
-)
-(connector
-	(text "MAIN_CLK" (rect 3370 1976 3427 1987)(font "Arial" ))
-	(pt 3448 1992)
-	(pt 3360 1992)
-)
-(connector
-	(text "PIXEL_CLK" (rect 3370 1992 3431 2003)(font "Arial" ))
-	(pt 3448 2008)
-	(pt 3360 2008)
-)
-(connector
-	(pt 3328 1960)
-	(pt 3448 1960)
-)
-(connector
-	(pt 3840 1864)
-	(pt 3704 1864)
-	(bus)
-)
-(connector
-	(text "CLUT_ADR[7..0]" (rect 3338 1928 3420 1939)(font "Arial" ))
-	(pt 3336 1944)
-	(pt 3448 1944)
-	(bus)
-)
-(connector
-	(text "FB_AD[23..18]" (rect 3930 1640 4003 1651)(font "Arial" ))
-	(pt 3920 1656)
-	(pt 4032 1656)
-	(bus)
-)
-(connector
-	(text "FB_AD[23..18]" (rect 3930 1848 4003 1859)(font "Arial" ))
-	(pt 3920 1864)
-	(pt 4032 1864)
-	(bus)
-)
-(connector
-	(pt 3880 1464)
-	(pt 3880 1480)
-)
-(connector
-	(text "FALCON_CLUT_RDH" (rect 3762 1464 3871 1475)(font "Arial" ))
-	(pt 3880 1480)
-	(pt 3752 1480)
-)
-(connector
-	(pt 3880 1672)
-	(pt 3880 1688)
-)
-(connector
-	(text "FALCON_CLUT_RDH" (rect 3762 1672 3871 1683)(font "Arial" ))
-	(pt 3880 1688)
-	(pt 3752 1688)
-)
-(connector
-	(pt 3880 1880)
-	(pt 3880 1896)
-)
-(connector
-	(text "FALCON_CLUT_RDL" (rect 3762 1880 3871 1891)(font "Arial" ))
-	(pt 3880 1896)
-	(pt 3752 1896)
-)
-(connector
-	(text "FALCON_CLUT_WR3" (rect 3346 1880 3458 1891)(font "Arial" ))
-	(pt 3448 1896)
-	(pt 3336 1896)
-)
-(connector
-	(text "FALCON_CLUT_WR0" (rect 3346 1464 3458 1475)(font "Arial" ))
-	(pt 3448 1480)
-	(pt 3336 1480)
-)
-(connector
-	(text "FALCON_CLUT_WR1" (rect 3346 1672 3456 1683)(font "Arial" ))
-	(pt 3448 1688)
-	(pt 3336 1688)
-)
-(connector
-	(text "CCF[7..2]" (rect 3834 1912 3881 1923)(font "Arial" ))
-	(pt 3904 1928)
-	(pt 3704 1928)
-	(bus)
-)
-(connector
-	(text "CCF[1..0]" (rect 3842 1944 3889 1955)(font "Arial" ))
-	(pt 3904 1960)
-	(pt 3816 1960)
-	(bus)
-)
-(connector
-	(text "CCF[23..18]" (rect 3826 1496 3886 1507)(font "Arial" ))
-	(pt 3904 1512)
-	(pt 3704 1512)
-	(bus)
-)
-(connector
-	(text "CCF[15..10]" (rect 3826 1704 3886 1715)(font "Arial" ))
-	(pt 3904 1720)
-	(pt 3704 1720)
-	(bus)
-)
-(connector
-	(text "CCF[9..8]" (rect 3842 1744 3889 1755)(font "Arial" ))
-	(pt 3904 1760)
-	(pt 3816 1760)
-	(bus)
-)
-(connector
-	(text "CCF[17..16]" (rect 3842 1536 3902 1547)(font "Arial" ))
-	(pt 3904 1552)
-	(pt 3816 1552)
-	(bus)
-)
-(connector
-	(text "CLUT_ADR[7..0]" (rect 3338 1720 3420 1731)(font "Arial" ))
-	(pt 3336 1736)
-	(pt 3448 1736)
-	(bus)
-)
-(connector
-	(pt 3328 1752)
-	(pt 3448 1752)
-)
-(connector
-	(text "FB_AD[23..18]" (rect 3346 1848 3419 1859)(font "Arial" ))
-	(pt 3336 1864)
-	(pt 3448 1864)
-	(bus)
-)
-(connector
-	(text "FB_ADR[9..2]" (rect 3346 1864 3414 1875)(font "Arial" ))
-	(pt 3336 1880)
-	(pt 3448 1880)
-	(bus)
-)
-(connector
-	(text "CLUT_ADR[7..0]" (rect 3338 1512 3420 1523)(font "Arial" ))
-	(pt 3336 1528)
-	(pt 3448 1528)
-	(bus)
-)
-(connector
-	(pt 3328 1544)
-	(pt 3448 1544)
-)
-(connector
-	(text "FB_AD[23..18]" (rect 3346 1640 3419 1651)(font "Arial" ))
-	(pt 3336 1656)
-	(pt 3448 1656)
-	(bus)
-)
-(connector
-	(text "FB_ADR[9..2]" (rect 3346 1656 3414 1667)(font "Arial" ))
-	(pt 3336 1672)
-	(pt 3448 1672)
-	(bus)
-)
-(connector
-	(text "FB_AD[31..26]" (rect 3346 1432 3419 1443)(font "Arial" ))
-	(pt 3336 1448)
-	(pt 3448 1448)
-	(bus)
-)
-(connector
-	(text "FB_ADR[9..2]" (rect 3346 1448 3414 1459)(font "Arial" ))
-	(pt 3336 1464)
-	(pt 3448 1464)
-	(bus)
-)
-(connector
-	(text "MAIN_CLK" (rect 3370 920 3427 931)(font "Arial" ))
-	(pt 3448 936)
-	(pt 3360 936)
-)
-(connector
-	(text "PIXEL_CLK" (rect 3370 936 3431 947)(font "Arial" ))
-	(pt 3448 952)
-	(pt 3360 952)
-)
-(connector
-	(pt 3704 808)
-	(pt 3840 808)
-	(bus)
-)
-(connector
-	(text "MAIN_CLK" (rect 3370 1128 3427 1139)(font "Arial" ))
-	(pt 3448 1144)
-	(pt 3360 1144)
-)
-(connector
-	(text "PIXEL_CLK" (rect 3370 1144 3431 1155)(font "Arial" ))
-	(pt 3448 1160)
-	(pt 3360 1160)
-)
-(connector
-	(pt 3704 1016)
-	(pt 3840 1016)
-	(bus)
-)
-(connector
-	(pt 3704 1224)
-	(pt 3840 1224)
-	(bus)
-)
-(connector
-	(text "MAIN_CLK" (rect 3370 1336 3427 1347)(font "Arial" ))
-	(pt 3448 1352)
-	(pt 3360 1352)
-)
-(connector
-	(text "PIXEL_CLK" (rect 3370 1352 3431 1363)(font "Arial" ))
-	(pt 3448 1368)
-	(pt 3360 1368)
-)
-(connector
-	(text "CLUT_ADR[3..0]" (rect 3338 1288 3420 1299)(font "Arial" ))
-	(pt 3336 1304)
-	(pt 3448 1304)
-	(bus)
-)
-(connector
-	(pt 3328 1320)
-	(pt 3448 1320)
-)
-(connector
-	(text "FB_AD[26..24]" (rect 3930 792 4003 803)(font "Arial" ))
-	(pt 3920 808)
-	(pt 4032 808)
-	(bus)
-)
-(connector
-	(text "FB_AD[22..20]" (rect 3930 1000 4003 1011)(font "Arial" ))
-	(pt 3920 1016)
-	(pt 4032 1016)
-	(bus)
-)
-(connector
-	(text "FB_AD[18..16]" (rect 3930 1208 4003 1219)(font "Arial" ))
-	(pt 3920 1224)
-	(pt 4032 1224)
-	(bus)
-)
-(connector
-	(pt 3880 824)
-	(pt 3880 840)
-)
-(connector
-	(text "ST_CLUT_RD" (rect 3802 824 3875 835)(font "Arial" ))
-	(pt 3880 840)
-	(pt 3792 840)
-)
-(connector
-	(pt 3880 1032)
-	(pt 3880 1048)
-)
-(connector
-	(text "ST_CLUT_RD" (rect 3802 1032 3875 1043)(font "Arial" ))
-	(pt 3880 1048)
-	(pt 3792 1048)
-)
-(connector
-	(pt 3880 1240)
-	(pt 3880 1256)
-)
-(connector
-	(text "ST_CLUT_RD" (rect 3802 1240 3875 1251)(font "Arial" ))
-	(pt 3880 1256)
-	(pt 3792 1256)
-)
-(connector
-	(text "ST_CLUT_WR1" (rect 3346 1240 3426 1251)(font "Arial" ))
-	(pt 3448 1256)
-	(pt 3336 1256)
-)
-(connector
-	(text "ST_CLUT_WR0" (rect 3346 824 3427 835)(font "Arial" ))
-	(pt 3448 840)
-	(pt 3336 840)
-)
-(connector
-	(text "ST_CLUT_WR1" (rect 3346 1032 3426 1043)(font "Arial" ))
-	(pt 3448 1048)
-	(pt 3336 1048)
-)
-(connector
-	(text "CCS[15..13]" (rect 3826 1064 3886 1075)(font "Arial" ))
-	(pt 3920 1080)
-	(pt 3704 1080)
-	(bus)
-)
-(connector
-	(text "CCS[12..8]" (rect 3826 1096 3880 1107)(font "Arial" ))
-	(pt 3816 1112)
-	(pt 3920 1112)
-	(bus)
-)
-(connector
-	(text "CCS[23..21]" (rect 3810 856 3870 867)(font "Arial" ))
-	(pt 3904 872)
-	(pt 3704 872)
-	(bus)
-)
-(connector
-	(text "CCS[20..16]" (rect 3818 888 3878 899)(font "Arial" ))
-	(pt 3808 904)
-	(pt 3904 904)
-	(bus)
-)
-(connector
-	(text "CCS[7..5]" (rect 3714 1272 3762 1283)(font "Arial" ))
-	(pt 3920 1288)
-	(pt 3704 1288)
-	(bus)
-)
-(connector
-	(text "CCS[4..0]" (rect 3818 1304 3866 1315)(font "Arial" ))
-	(pt 3808 1320)
-	(pt 3920 1320)
-	(bus)
-)
-(connector
-	(text "FB_AD[26..24]" (rect 3346 792 3419 803)(font "Arial" ))
-	(pt 3336 808)
-	(pt 3448 808)
-	(bus)
-)
-(connector
-	(text "FB_ADR[4..1]" (rect 3346 808 3414 819)(font "Arial" ))
-	(pt 3336 824)
-	(pt 3448 824)
-	(bus)
-)
-(connector
-	(text "CLUT_ADR[3..0]" (rect 3338 872 3420 883)(font "Arial" ))
-	(pt 3336 888)
-	(pt 3448 888)
-	(bus)
-)
-(connector
-	(pt 3328 904)
-	(pt 3448 904)
-)
-(connector
-	(text "FB_AD[22..20]" (rect 3346 1000 3419 1011)(font "Arial" ))
-	(pt 3336 1016)
-	(pt 3448 1016)
-	(bus)
-)
-(connector
-	(text "FB_ADR[4..1]" (rect 3346 1016 3414 1027)(font "Arial" ))
-	(pt 3336 1032)
-	(pt 3448 1032)
-	(bus)
-)
-(connector
-	(text "CLUT_ADR[3..0]" (rect 3338 1080 3420 1091)(font "Arial" ))
-	(pt 3336 1096)
-	(pt 3448 1096)
-	(bus)
-)
-(connector
-	(pt 3328 1112)
-	(pt 3448 1112)
-)
-(connector
-	(text "FB_AD[18..16]" (rect 3346 1208 3419 1219)(font "Arial" ))
-	(pt 3336 1224)
-	(pt 3448 1224)
-	(bus)
-)
-(connector
-	(text "FB_ADR[4..1]" (rect 3346 1224 3414 1235)(font "Arial" ))
-	(pt 3336 1240)
-	(pt 3448 1240)
-	(bus)
-)
-(connector
-	(text "ACP_CLUT_WR1" (rect 3314 2112 3402 2123)(font "Arial" ))
-	(pt 3304 2128)
-	(pt 3448 2128)
-)
-(connector
-	(text "FB_AD[23..16]" (rect 3874 2080 3947 2091)(font "Arial" ))
-	(pt 3960 2096)
-	(pt 3864 2096)
-	(bus)
-)
-(connector
-	(text "FB_AD[15..8]" (rect 3874 2288 3940 2299)(font "Arial" ))
-	(pt 3864 2304)
-	(pt 3952 2304)
-	(bus)
-)
-(connector
-	(text "FB_AD[15..8]" (rect 3370 2288 3436 2299)(font "Arial" ))
-	(pt 3360 2304)
-	(pt 3448 2304)
-	(bus)
-)
-(connector
-	(text "FB_AD[7..0]" (rect 3874 2496 3934 2507)(font "Arial" ))
-	(pt 3864 2512)
-	(pt 3952 2512)
-	(bus)
-)
-(connector
-	(text "FB_AD[7..0]" (rect 3370 2496 3430 2507)(font "Arial" ))
-	(pt 3360 2512)
-	(pt 3448 2512)
-	(bus)
-)
-(connector
-	(text "CCA[23..16]" (rect 3730 2144 3790 2155)(font "Arial" ))
-	(pt 3808 2160)
-	(pt 3704 2160)
-	(bus)
-)
-(connector
-	(text "CCA[15..8]" (rect 3730 2352 3784 2363)(font "Arial" ))
-	(pt 3808 2368)
-	(pt 3704 2368)
-	(bus)
-)
-(connector
-	(text "CCA[7..0]" (rect 3730 2560 3778 2571)(font "Arial" ))
-	(pt 3808 2576)
-	(pt 3704 2576)
-	(bus)
-)
-(connector
-	(text "FB_AD[23..16]" (rect 3362 2080 3435 2091)(font "Arial" ))
-	(pt 3448 2096)
-	(pt 3352 2096)
-	(bus)
-)
-(connector
-	(text "ZR_C8B[7..0]" (rect 3354 2576 3421 2587)(font "Arial" ))
-	(pt 3448 2592)
-	(pt 3344 2592)
-	(bus)
-)
-(connector
-	(text "ZR_C8B[7..0]" (rect 3362 2368 3429 2379)(font "Arial" ))
-	(pt 3448 2384)
-	(pt 3352 2384)
-	(bus)
-)
-(connector
-	(text "ZR_C8B[7..0]" (rect 3362 2160 3429 2171)(font "Arial" ))
-	(pt 3448 2176)
-	(pt 3352 2176)
-	(bus)
-)
-(connector
-	(text "FB_ADR[9..2]" (rect 3266 2304 3334 2315)(font "Arial" ))
-	(pt 3448 2320)
-	(pt 3256 2320)
-	(bus)
-)
-(connector
-	(text "FB_ADR[9..2]" (rect 3266 2096 3334 2107)(font "Arial" ))
-	(pt 3448 2112)
-	(pt 3256 2112)
-	(bus)
-)
-(connector
-	(text "FB_ADR[9..2]" (rect 3266 2512 3334 2523)(font "Arial" ))
-	(pt 3448 2528)
-	(pt 3256 2528)
-	(bus)
-)
-(connector
-	(text "ACP_CLUT_WR3" (rect 3346 2528 3435 2539)(font "Arial" ))
-	(pt 3448 2544)
-	(pt 3336 2544)
-)
-(connector
-	(text "ACP_CLUT_WR2" (rect 3346 2320 3435 2331)(font "Arial" ))
-	(pt 3448 2336)
-	(pt 3336 2336)
-)
-(connector
-	(text "FIFO_MW[8..0]" (rect 1882 1384 1957 1395)(font "Arial" ))
-	(pt 1952 1400)
-	(pt 1872 1400)
-	(bus)
-)
-(connector
-	(pt 2000 1408)
-	(pt 1984 1408)
-	(bus)
-)
-(connector
-	(pt 1984 1344)
-	(pt 1984 1408)
-	(bus)
-)
-(connector
-	(pt 1984 1344)
-	(pt 2248 1344)
-	(bus)
-)
-(connector
-	(pt 2512 1248)
-	(pt 2512 1408)
-)
-(connector
-	(pt 2088 1480)
-	(pt 2088 1512)
-)
-(connector
-	(text "INTER_ZEI" (rect 1994 1496 2050 1507)(font "Arial" ))
-	(pt 1984 1512)
-	(pt 2088 1512)
-)
-(connector
-	(text "INTER_ZEI" (rect 1362 1424 1418 1435)(font "Arial" ))
-	(pt 1352 1440)
-	(pt 1456 1440)
-)
-(connector
-	(pt 1504 1440)
-	(pt 1536 1440)
-)
-(connector
-	(text "VDVZ[127..0]" (rect 1090 1120 1156 1131)(font "Arial" ))
-	(pt 1088 1136)
-	(pt 1160 1136)
-	(bus)
-)
-(connector
-	(text "VDVZ[127..96]" (rect 1450 936 1523 947)(font "Arial" ))
-	(pt 1440 952)
-	(pt 1520 952)
-	(bus)
-)
-(connector
-	(text "VDVZ[63..32]" (rect 1194 920 1260 931)(font "Arial" ))
-	(pt 1184 936)
-	(pt 1296 936)
-	(bus)
-)
-(connector
-	(text "VDP_IN[31..0]" (rect 962 992 1032 1003)(font "Arial" ))
-	(pt 952 1008)
-	(pt 1040 1008)
-	(bus)
-)
-(connector
-	(text "VDVZ[95..64]" (rect 1450 1024 1516 1035)(font "Arial" ))
-	(pt 1440 1040)
-	(pt 1520 1040)
-	(bus)
-)
-(connector
-	(text "VDVZ[31..0]" (rect 1194 1008 1254 1019)(font "Arial" ))
-	(pt 1184 1024)
-	(pt 1296 1024)
-	(bus)
-)
-(connector
-	(text "VDP_IN[63..32]" (rect 962 904 1038 915)(font "Arial" ))
-	(pt 952 920)
-	(pt 1040 920)
-	(bus)
-)
-(connector
-	(text "DDRCLK0" (rect 978 920 1031 931)(font "Arial" ))
-	(pt 1040 936)
-	(pt 968 936)
-)
-(connector
-	(text "DDRCLK0" (rect 978 1008 1031 1019)(font "Arial" ))
-	(pt 1040 1024)
-	(pt 968 1024)
-)
-(connector
-	(text "DDRCLK0" (rect 1234 936 1287 947)(font "Arial" ))
-	(pt 1296 952)
-	(pt 1224 952)
-)
-(connector
-	(text "DDRCLK0" (rect 1234 1024 1287 1035)(font "Arial" ))
-	(pt 1224 1040)
-	(pt 1296 1040)
-)
-(connector
-	(text "DDRCLK0" (rect 1098 1136 1151 1147)(font "Arial" ))
-	(pt 1160 1152)
-	(pt 1088 1152)
-)
-(connector
-	(text "DDRCLK0" (rect 1338 1160 1391 1171)(font "Arial" ))
-	(pt 1400 1176)
-	(pt 1328 1176)
-)
-(connector
-	(text "VDMB[127..0]" (rect 1554 1168 1622 1179)(font "Arial" ))
-	(pt 1544 1184)
-	(pt 1624 1184)
-	(bus)
-)
-(connector
-	(text "VDMA[127..0]" (rect 1314 1144 1382 1155)(font "Arial" ))
-	(pt 1304 1160)
-	(pt 1400 1160)
-	(bus)
-)
-(connector
-	(text "VDMC[127..0]" (rect 1642 1344 1711 1355)(font "Arial" ))
-	(pt 1640 1360)
-	(pt 1712 1360)
-	(bus)
-)
-(connector
-	(text "VDMC[127..0]" (rect 1970 960 2039 971)(font "Arial" ))
-	(pt 1968 976)
-	(pt 2040 976)
-	(bus)
-)
-(connector
-	(text "VDMB[127..0]" (rect 1586 1080 1654 1091)(font "Arial" ))
-	(pt 1576 1096)
-	(pt 1800 1096)
-	(bus)
-)
-(connector
-	(text "VDMB[119..0],VDMA[127..120]" (rect 1586 1064 1738 1075)(font "Arial" ))
-	(pt 1576 1080)
-	(pt 1800 1080)
-	(bus)
-)
-(connector
-	(text "VDMB[111..0],VDMA[127..112]" (rect 1586 1048 1738 1059)(font "Arial" ))
-	(pt 1576 1064)
-	(pt 1800 1064)
-	(bus)
-)
-(connector
-	(text "VDMB[103..0],VDMA[127..104]" (rect 1586 1032 1738 1043)(font "Arial" ))
-	(pt 1576 1048)
-	(pt 1800 1048)
-	(bus)
-)
-(connector
-	(text "VDMB[95..0],VDMA[127..96]" (rect 1586 1016 1726 1027)(font "Arial" ))
-	(pt 1576 1032)
-	(pt 1800 1032)
-	(bus)
-)
-(connector
-	(text "VDMB[87..0],VDMA[127..88]" (rect 1586 1000 1726 1011)(font "Arial" ))
-	(pt 1576 1016)
-	(pt 1800 1016)
-	(bus)
-)
-(connector
-	(text "VDMB[79..0],VDMA[127..80]" (rect 1586 984 1726 995)(font "Arial" ))
-	(pt 1576 1000)
-	(pt 1800 1000)
-	(bus)
-)
-(connector
-	(text "VDMB[71..0],VDMA[127..72]" (rect 1586 968 1726 979)(font "Arial" ))
-	(pt 1576 984)
-	(pt 1800 984)
-	(bus)
-)
-(connector
-	(text "VDMB[63..0],VDMA[127..64]" (rect 1586 952 1726 963)(font "Arial" ))
-	(pt 1576 968)
-	(pt 1800 968)
-	(bus)
-)
-(connector
-	(text "VDMB[55..0],VDMA[127..56]" (rect 1586 936 1726 947)(font "Arial" ))
-	(pt 1576 952)
-	(pt 1800 952)
-	(bus)
-)
-(connector
-	(text "VDMB[47..0],VDMA[127..48]" (rect 1586 920 1726 931)(font "Arial" ))
-	(pt 1576 936)
-	(pt 1800 936)
-	(bus)
-)
-(connector
-	(text "VDMB[39..0],VDMA[127..40]" (rect 1586 904 1726 915)(font "Arial" ))
-	(pt 1576 920)
-	(pt 1800 920)
-	(bus)
-)
-(connector
-	(text "VDMB[31..0],VDMA[127..32]" (rect 1586 888 1726 899)(font "Arial" ))
-	(pt 1576 904)
-	(pt 1800 904)
-	(bus)
-)
-(connector
-	(text "VDMB[23..0],VDMA[127..24]" (rect 1586 872 1726 883)(font "Arial" ))
-	(pt 1576 888)
-	(pt 1800 888)
-	(bus)
-)
-(connector
-	(text "VDMB[15..0],VDMA[127..16]" (rect 1586 856 1726 867)(font "Arial" ))
-	(pt 1576 872)
-	(pt 1800 872)
-	(bus)
-)
-(connector
-	(text "VDMB[7..0],VDMA[127..8]" (rect 1586 840 1714 851)(font "Arial" ))
-	(pt 1576 856)
-	(pt 1800 856)
-	(bus)
-)
-(connector
-	(text "FIFO_WRE" (rect 1098 1152 1157 1163)(font "Arial" ))
-	(pt 1088 1168)
-	(pt 1160 1168)
-)
-(connector
-	(text "FIFO_WRE" (rect 1338 1176 1397 1187)(font "Arial" ))
-	(pt 1328 1192)
-	(pt 1400 1192)
-)
-(connector
-	(text "FIFO_WRE" (rect 1650 1368 1709 1379)(font "Arial" ))
-	(pt 1640 1384)
-	(pt 1712 1384)
-)
-(connector
-	(pt 1888 1120)
-	(pt 1888 1160)
-	(bus)
-)
-(connector
-	(text "VDM_SEL[3..0]" (rect 1810 1144 1886 1155)(font "Arial" ))
-	(pt 1888 1160)
-	(pt 1800 1160)
-	(bus)
-)
-(connector
-	(pt 1944 1296)
-	(pt 1920 1296)
-)
-(connector
-	(text "FIFO_RDE" (rect 1770 1272 1826 1283)(font "Arial" ))
-	(pt 1760 1288)
-	(pt 1856 1288)
-)
-(connector
-	(text "INTER_ZEI" (rect 1762 1288 1818 1299)(font "Arial" ))
-	(pt 1752 1304)
-	(pt 1856 1304)
-)
-(connector
-	(text "VIDEO_MOD_TA" (rect 258 1816 347 1827)(font "Arial" ))
-	(pt 264 1832)
-	(pt 360 1832)
-)
-(connector
-	(text "CLR_FIFO" (rect 1634 1456 1689 1467)(font "Arial" ))
-	(pt 1712 1472)
-	(pt 1632 1472)
-)
-(connector
-	(text "SR_BLITTER_DACK" (rect 778 2560 884 2571)(font "Arial" ))
-	(pt 904 2576)
-	(pt 768 2576)
-)
-(connector
-	(text "DDRCLK0" (rect 794 2544 847 2555)(font "Arial" ))
-	(pt 904 2560)
-	(pt 784 2560)
-)
-(connector
-	(text "BLITTER_DACK[4..0]" (rect 1058 2560 1165 2571)(font "Arial" ))
-	(pt 1176 2576)
-	(pt 1048 2576)
-	(bus)
-)
-(connector
-	(text "BLITTER_DACK[0]" (rect 778 2952 872 2963)(font "Arial" ))
-	(pt 776 2968)
-	(pt 888 2968)
-)
-(connector
-	(text "BLITTER_DIN[127..0]" (rect 1042 2944 1149 2955)(font "Arial" ))
-	(pt 1160 2960)
-	(pt 1032 2960)
-	(bus)
-)
-(connector
-	(text "BLITTER_SIG" (rect 578 2808 649 2819)(font "Arial" ))
-	(pt 568 2824)
-	(pt 680 2824)
-)
-(connector
-	(text "BLITTER_WR" (rect 578 2832 649 2843)(font "Arial" ))
-	(pt 568 2848)
-	(pt 680 2848)
-)
-(connector
-	(text "nFB_CS1" (rect 202 2696 250 2707)(font "Arial" ))
-	(pt 192 2712)
-	(pt 296 2712)
-)
-(connector
-	(text "nFB_CS2" (rect 202 2720 251 2731)(font "Arial" ))
-	(pt 192 2736)
-	(pt 296 2736)
-)
-(connector
-	(text "nFB_CS3" (rect 202 2744 251 2755)(font "Arial" ))
-	(pt 192 2760)
-	(pt 296 2760)
-)
-(connector
-	(text "nFB_WR" (rect 202 2768 248 2779)(font "Arial" ))
-	(pt 192 2784)
-	(pt 296 2784)
-)
-(connector
-	(text "FB_SIZE0" (rect 202 2792 253 2803)(font "Arial" ))
-	(pt 192 2808)
-	(pt 296 2808)
-)
-(connector
-	(text "FB_SIZE1" (rect 202 2816 252 2827)(font "Arial" ))
-	(pt 192 2832)
-	(pt 296 2832)
-)
-(connector
-	(text "nFB_OE" (rect 202 2840 245 2851)(font "Arial" ))
-	(pt 192 2856)
-	(pt 296 2856)
-)
-(connector
-	(text "MAIN_CLK" (rect 202 2624 259 2635)(font "Arial" ))
-	(pt 296 2640)
-	(pt 192 2640)
-)
-(connector
-	(text "FB_ALE" (rect 202 2672 244 2683)(font "Arial" ))
-	(pt 296 2688)
-	(pt 192 2688)
-)
-(connector
-	(text "FB_ADR[31..0]" (rect 202 2648 276 2659)(font "Arial" ))
-	(pt 192 2664)
-	(pt 296 2664)
-	(bus)
-)
-(connector
-	(text "nRSTO" (rect 202 2576 240 2587)(font "Arial" ))
-	(pt 192 2592)
-	(pt 296 2592)
-)
-(connector
-	(text "FB_AD[31..0]" (rect 578 2616 644 2627)(font "Arial" ))
-	(pt 688 2632)
-	(pt 568 2632)
-	(bus)
-)
-(connector
-	(text "DDRCLK0" (rect 194 2600 247 2611)(font "Arial" ))
-	(pt 296 2616)
-	(pt 184 2616)
-)
-(connector
-	(text "BLITTER_TA" (rect 578 2968 646 2979)(font "Arial" ))
-	(pt 568 2984)
-	(pt 672 2984)
-)
-(connector
-	(text "BLITTER_DACK[4..0]" (rect 178 2872 285 2883)(font "Arial" ))
-	(pt 296 2888)
-	(pt 184 2888)
-	(bus)
-)
-(connector
-	(text "VIDEO_RAM_CTR[15..0]" (rect 154 2904 279 2915)(font "Arial" ))
-	(pt 296 2920)
-	(pt 144 2920)
-	(bus)
-)
-(connector
-	(text "BLITTER_ON" (rect 202 2928 270 2939)(font "Arial" ))
-	(pt 296 2944)
-	(pt 192 2944)
-)
-(connector
-	(text "BLITTER_DIN[127..0]" (rect 162 2952 269 2963)(font "Arial" ))
-	(pt 296 2968)
-	(pt 152 2968)
-	(bus)
-)
-(connector
-	(text "BLITTER_DOUT[127..0]" (rect 578 2752 697 2763)(font "Arial" ))
-	(pt 712 2768)
-	(pt 568 2768)
-	(bus)
-)
-(connector
-	(text "BLITTER_ADR[31..0]" (rect 578 2784 684 2795)(font "Arial" ))
-	(pt 704 2800)
-	(pt 568 2800)
-	(bus)
-)
-(connector
-	(text "BLITTER_RUN" (rect 578 2720 653 2731)(font "Arial" ))
-	(pt 672 2736)
-	(pt 568 2736)
-)
-(connector
-	(text "SR_BLITTER_DACK" (rect 170 2984 276 2995)(font "Arial" ))
-	(pt 296 3000)
-	(pt 160 3000)
-)
-(connector
-	(text "DOP_FIFO_CLR" (rect 1978 1296 2062 1307)(font "Arial" ))
-	(pt 2064 1312)
-	(pt 1992 1312)
-)
-(connector
-	(pt 1968 1424)
-	(pt 1968 1208)
-	(bus)
-)
-(connector
-	(pt 2248 1208)
-	(pt 2240 1208)
-	(bus)
-)
-(connector
-	(pt 2248 1344)
-	(pt 2248 1208)
-	(bus)
-)
-(connector
-	(pt 1608 1432)
-	(pt 1608 1232)
-)
-(connector
-	(pt 1944 1296)
-	(pt 1944 1248)
-)
-(connector
-	(pt 2064 1312)
-	(pt 2064 1296)
-)
-(connector
-	(pt 1872 1424)
-	(pt 1968 1424)
-	(bus)
-)
-(connector
-	(pt 1968 1424)
-	(pt 2000 1424)
-	(bus)
-)
-(connector
-	(pt 1600 1432)
-	(pt 1608 1432)
-)
-(connector
-	(pt 1608 1432)
-	(pt 1712 1432)
-)
-(connector
-	(pt 1968 1208)
-	(pt 2080 1208)
-	(bus)
-)
-(connector
-	(pt 1608 1232)
-	(pt 2080 1232)
-)
-(connector
-	(pt 1944 1248)
-	(pt 2080 1248)
-)
-(connector
-	(text "PIXEL_CLK" (rect 2010 1256 2071 1267)(font "Arial" ))
-	(pt 2000 1272)
-	(pt 2080 1272)
-)
-(connector
-	(pt 2064 1296)
-	(pt 2080 1296)
-)
-(connector
-	(text "nFB_BURST" (rect 1570 1896 1634 1907)(font "Arial" ))
-	(pt 1560 1912)
-	(pt 1664 1912)
-)
-(connector
-	(text "nFB_OE" (rect 1570 1920 1613 1931)(font "Arial" ))
-	(pt 1560 1936)
-	(pt 1664 1936)
-)
-(connector
-	(text "nRSTO" (rect 1570 1704 1608 1715)(font "Arial" ))
-	(pt 1560 1720)
-	(pt 1664 1720)
-)
-(connector
-	(text "MAIN_CLK" (rect 1570 1728 1627 1739)(font "Arial" ))
-	(pt 1664 1744)
-	(pt 1560 1744)
-)
-(connector
-	(text "nFB_CS1" (rect 1570 1752 1618 1763)(font "Arial" ))
-	(pt 1560 1768)
-	(pt 1664 1768)
-)
-(connector
-	(text "nFB_CS2" (rect 1570 1776 1619 1787)(font "Arial" ))
-	(pt 1560 1792)
-	(pt 1664 1792)
-)
-(connector
-	(text "nFB_CS3" (rect 1570 1800 1619 1811)(font "Arial" ))
-	(pt 1560 1816)
-	(pt 1664 1816)
-)
-(connector
-	(text "nFB_WR" (rect 1570 1824 1616 1835)(font "Arial" ))
-	(pt 1560 1840)
-	(pt 1664 1840)
-)
-(connector
-	(text "FB_SIZE0" (rect 1570 1848 1621 1859)(font "Arial" ))
-	(pt 1560 1864)
-	(pt 1664 1864)
-)
-(connector
-	(text "FB_SIZE1" (rect 1570 1872 1620 1883)(font "Arial" ))
-	(pt 1560 1888)
-	(pt 1664 1888)
-)
-(connector
-	(text "FB_AD[31..0]" (rect 2026 1720 2092 1731)(font "Arial" ))
-	(pt 2136 1736)
-	(pt 2016 1736)
-	(bus)
-)
-(connector
-	(text "FB_ADR[31..0]" (rect 1570 1944 1644 1955)(font "Arial" ))
-	(pt 1664 1960)
-	(pt 1560 1960)
-	(bus)
-)
-(connector
-	(text "ACP_CLUT_RD" (rect 2026 1968 2107 1979)(font "Arial" ))
-	(pt 2016 1984)
-	(pt 2112 1984)
-)
-(connector
-	(text "PIXEL_CLK" (rect 2026 2224 2087 2235)(font "Arial" ))
-	(pt 2104 2240)
-	(pt 2016 2240)
-)
-(connector
-	(text "ST_CLUT_RD" (rect 2026 2096 2099 2107)(font "Arial" ))
-	(pt 2016 2112)
-	(pt 2120 2112)
-)
-(connector
-	(text "FALCON_CLUT_RDH" (rect 2026 2024 2135 2035)(font "Arial" ))
-	(pt 2016 2040)
-	(pt 2120 2040)
-)
-(connector
-	(text "FALCON_CLUT_RDL" (rect 2026 2000 2135 2011)(font "Arial" ))
-	(pt 2016 2016)
-	(pt 2120 2016)
-)
-(connector
-	(text "ST_CLUT_WR[1..0]" (rect 2026 2120 2123 2131)(font "Arial" ))
-	(pt 2016 2136)
-	(pt 2112 2136)
-	(bus)
-)
-(connector
-	(text "CLUT_MUX_ADR[3..0]" (rect 2026 2152 2139 2163)(font "Arial" ))
-	(pt 2016 2168)
-	(pt 2120 2168)
-	(bus)
-)
-(connector
-	(text "HSYNC" (rect 2026 2248 2066 2259)(font "Arial" ))
-	(pt 2104 2264)
-	(pt 2016 2264)
-)
-(connector
-	(text "VSYNC" (rect 2026 2272 2066 2283)(font "Arial" ))
-	(pt 2104 2288)
-	(pt 2016 2288)
-)
-(connector
-	(text "nBLANK" (rect 2026 2296 2070 2307)(font "Arial" ))
-	(pt 2104 2312)
-	(pt 2016 2312)
-)
-(connector
-	(text "nSYNC" (rect 2026 2320 2064 2331)(font "Arial" ))
-	(pt 2104 2336)
-	(pt 2016 2336)
-)
-(connector
-	(text "nPD_VGA" (rect 2026 2344 2080 2355)(font "Arial" ))
-	(pt 2104 2360)
-	(pt 2016 2360)
-)
-(connector
-	(text "CLUT_OFF[3..0]" (rect 2026 2072 2107 2083)(font "Arial" ))
-	(pt 2016 2088)
-	(pt 2112 2088)
-	(bus)
-)
-(connector
-	(text "BLITTER_ON" (rect 2026 2488 2094 2499)(font "Arial" ))
-	(pt 2096 2504)
-	(pt 2016 2504)
-)
-(connector
-	(text "VIDEO_RAM_CTR[15..0]" (rect 2026 2368 2151 2379)(font "Arial" ))
-	(pt 2144 2384)
-	(pt 2016 2384)
-	(bus)
-)
-(connector
-	(text "CCSEL[2..0]" (rect 2026 2200 2087 2211)(font "Arial" ))
-	(pt 2016 2216)
-	(pt 2096 2216)
-	(bus)
-)
-(connector
-	(text "ACP_CLUT_WR[3..0]" (rect 2026 1944 2133 1955)(font "Arial" ))
-	(pt 2136 1960)
-	(pt 2016 1960)
-	(bus)
-)
-(connector
-	(text "FALCON_CLUT_WR[3..0]" (rect 2026 2048 2154 2059)(font "Arial" ))
-	(pt 2144 2064)
-	(pt 2016 2064)
-	(bus)
-)
-(connector
-	(text "INTER_ZEI" (rect 2026 2400 2082 2411)(font "Arial" ))
-	(pt 2016 2416)
-	(pt 2136 2416)
-)
-(connector
-	(text "DOP_FIFO_CLR" (rect 2026 2424 2110 2435)(font "Arial" ))
-	(pt 2016 2440)
-	(pt 2128 2440)
-)
-(connector
-	(text "VIDEO_MOD_TA" (rect 2026 2520 2115 2531)(font "Arial" ))
-	(pt 2088 2536)
-	(pt 2016 2536)
-)
-(connector
-	(text "BLITTER_RUN" (rect 1546 2528 1621 2539)(font "Arial" ))
-	(pt 1664 2544)
-	(pt 1536 2544)
-)
-(connector
-	(text "CLK_VIDEO" (rect 1570 2144 1633 2155)(font "Arial" ))
-	(pt 1512 2160)
-	(pt 1664 2160)
-)
-(connector
-	(text "CLK33M" (rect 1586 2168 1630 2179)(font "Arial" ))
-	(pt 1512 2184)
-	(pt 1664 2184)
-)
-(connector
-	(text "CLK25M" (rect 1586 2192 1630 2203)(font "Arial" ))
-	(pt 1512 2208)
-	(pt 1664 2208)
-)
-(connector
-	(text "COLOR8" (rect 2026 1912 2073 1923)(font "Arial" ))
-	(pt 2016 1928)
-	(pt 2120 1928)
-)
-(connector
-	(text "COLOR4" (rect 2026 1896 2073 1907)(font "Arial" ))
-	(pt 2016 1912)
-	(pt 2120 1912)
-)
-(connector
-	(text "COLOR2" (rect 2026 1880 2073 1891)(font "Arial" ))
-	(pt 2016 1896)
-	(pt 2120 1896)
-)
-(connector
-	(text "COLOR1" (rect 2026 1864 2072 1875)(font "Arial" ))
-	(pt 2016 1880)
-	(pt 2120 1880)
-)
-(connector
-	(text "FIFO_RDE" (rect 2026 1736 2082 1747)(font "Arial" ))
-	(pt 2104 1752)
-	(pt 2016 1752)
-)
-(connector
-	(text "VIDEO_RECONFIG" (rect 2026 1688 2126 1699)(font "Arial" ))
-	(pt 2144 1704)
-	(pt 2016 1704)
-)
-(connector
-	(text "VR_WR" (rect 2026 1784 2067 1795)(font "Arial" ))
-	(pt 2112 1800)
-	(pt 2016 1800)
-)
-(connector
-	(text "VR_RD" (rect 2026 1800 2064 1811)(font "Arial" ))
-	(pt 2112 1816)
-	(pt 2016 1816)
-)
-(connector
-	(text "VR_BUSY" (rect 1578 2104 1632 2115)(font "Arial" ))
-	(pt 1512 2120)
-	(pt 1664 2120)
-)
-(connector
-	(text "VR_D[8..0]" (rect 1570 2120 1624 2131)(font "Arial" ))
-	(pt 1512 2136)
-	(pt 1664 2136)
-	(bus)
-)
-(connector
-	(text "CLR_FIFO" (rect 2026 1752 2081 1763)(font "Arial" ))
-	(pt 2016 1768)
-	(pt 2112 1768)
-)
-(connector
-	(text "BORDER_COLOR[23..0]" (rect 2026 2176 2149 2187)(font "Arial" ))
-	(pt 2096 2192)
-	(pt 2016 2192)
-	(bus)
-)
-(connector
-	(text "VR[7..0],VG[7..0],VB[7..0]" (rect 4522 2776 4648 2787)(font "Arial" ))
-	(pt 4512 2792)
-	(pt 4664 2792)
-	(bus)
-)
-(connector
-	(pt 4240 2808)
-	(pt 4280 2808)
-	(bus)
-)
-(connector
-	(text "PIXEL_CLK" (rect 4202 2808 4263 2819)(font "Arial" ))
-	(pt 4192 2824)
-	(pt 4280 2824)
-)
-(connector
-	(pt 4240 2792)
-	(pt 4280 2792)
-	(bus)
-)
-(connector
-	(text "FB_AD[31..0]" (rect 570 1904 636 1915)(font "Arial" ))
-	(pt 680 1920)
-	(pt 560 1920)
-	(bus)
-)
-(connector
-	(text "nFB_CS1" (rect 202 2040 250 2051)(font "Arial" ))
-	(pt 192 2056)
-	(pt 296 2056)
-)
-(connector
-	(text "nFB_CS2" (rect 202 2064 251 2075)(font "Arial" ))
-	(pt 192 2080)
-	(pt 296 2080)
-)
-(connector
-	(text "nFB_CS3" (rect 202 2088 251 2099)(font "Arial" ))
-	(pt 192 2104)
-	(pt 296 2104)
-)
-(connector
-	(text "nFB_WR" (rect 202 2112 248 2123)(font "Arial" ))
-	(pt 192 2128)
-	(pt 296 2128)
-)
-(connector
-	(text "FB_SIZE0" (rect 202 2136 253 2147)(font "Arial" ))
-	(pt 192 2152)
-	(pt 296 2152)
-)
-(connector
-	(text "FB_SIZE1" (rect 202 2160 252 2171)(font "Arial" ))
-	(pt 192 2176)
-	(pt 296 2176)
-)
-(connector
-	(text "nFB_OE" (rect 202 2184 245 2195)(font "Arial" ))
-	(pt 192 2200)
-	(pt 296 2200)
-)
-(connector
-	(text "nVWE" (rect 570 2192 603 2203)(font "Arial" ))
-	(pt 632 2208)
-	(pt 560 2208)
-)
-(connector
-	(text "nVCAS" (rect 570 2216 607 2227)(font "Arial" ))
-	(pt 632 2232)
-	(pt 560 2232)
-)
-(connector
-	(text "nVRAS" (rect 570 2240 607 2251)(font "Arial" ))
-	(pt 632 2256)
-	(pt 560 2256)
-)
-(connector
-	(text "nVCS" (rect 570 2264 600 2275)(font "Arial" ))
-	(pt 632 2280)
-	(pt 560 2280)
-)
-(connector
-	(text "VCKE" (rect 570 2288 601 2299)(font "Arial" ))
-	(pt 632 2304)
-	(pt 560 2304)
-)
-(connector
-	(text "MAIN_CLK" (rect 202 1944 259 1955)(font "Arial" ))
-	(pt 296 1960)
-	(pt 192 1960)
-)
-(connector
-	(text "FB_ALE" (rect 202 2016 244 2027)(font "Arial" ))
-	(pt 296 2032)
-	(pt 192 2032)
-)
-(connector
-	(text "FB_LE[3..0]" (rect 570 1976 629 1987)(font "Arial" ))
-	(pt 560 1992)
-	(pt 680 1992)
-	(bus)
-)
-(connector
-	(text "FB_VDOE[3..0]" (rect 570 2000 646 2011)(font "Arial" ))
-	(pt 560 2016)
-	(pt 680 2016)
-	(bus)
-)
-(connector
-	(text "DDR_SYNC_66M" (rect 210 1968 299 1979)(font "Arial" ))
-	(pt 200 1984)
-	(pt 296 1984)
-)
-(connector
-	(text "FB_ADR[31..0]" (rect 202 1992 276 2003)(font "Arial" ))
-	(pt 192 2008)
-	(pt 296 2008)
-	(bus)
-)
-(connector
-	(text "nRSTO" (rect 202 1896 240 1907)(font "Arial" ))
-	(pt 192 1912)
-	(pt 296 1912)
-)
-(connector
-	(text "VIDEO_RAM_CTR[15..0]" (rect 178 2240 303 2251)(font "Arial" ))
-	(pt 296 2256)
-	(pt 168 2256)
-	(bus)
-)
-(connector
-	(text "BLITTER_ADR[31..0]" (rect 194 2288 300 2299)(font "Arial" ))
-	(pt 184 2304)
-	(pt 296 2304)
-	(bus)
-)
-(connector
-	(text "BLITTER_SIG" (rect 194 2312 265 2323)(font "Arial" ))
-	(pt 184 2328)
-	(pt 296 2328)
-)
-(connector
-	(text "BLITTER_WR" (rect 194 2336 265 2347)(font "Arial" ))
-	(pt 184 2352)
-	(pt 296 2352)
-)
-(connector
-	(text "SR_FIFO_WRE" (rect 570 2072 650 2083)(font "Arial" ))
-	(pt 648 2088)
-	(pt 560 2088)
-)
-(connector
-	(text "SR_DDR_FB" (rect 570 2312 637 2323)(font "Arial" ))
-	(pt 640 2328)
-	(pt 560 2328)
-)
-(connector
-	(text "SR_DDR_WR" (rect 570 2024 641 2035)(font "Arial" ))
-	(pt 664 2040)
-	(pt 560 2040)
-)
-(connector
-	(text "SR_VDMP[7..0]" (rect 570 2336 647 2347)(font "Arial" ))
-	(pt 560 2352)
-	(pt 664 2352)
-	(bus)
-)
-(connector
-	(text "SR_DDRWR_D_SEL" (rect 570 2360 676 2371)(font "Arial" ))
-	(pt 560 2376)
-	(pt 664 2376)
-)
-(connector
-	(text "DDRCLK0" (rect 194 1920 247 1931)(font "Arial" ))
-	(pt 296 1936)
-	(pt 184 1936)
-)
-(connector
-	(text "VIDEO_DDR_TA" (rect 570 2488 657 2499)(font "Arial" ))
-	(pt 560 2504)
-	(pt 664 2504)
-)
-(connector
-	(text "SR_BLITTER_DACK" (rect 570 2464 676 2475)(font "Arial" ))
-	(pt 664 2480)
-	(pt 560 2480)
-)
-(connector
-	(text "CLK33M" (rect 218 2432 262 2443)(font "Arial" ))
-	(pt 208 2448)
-	(pt 296 2448)
-)
-(connector
-	(text "BA[1..0]" (rect 570 2120 610 2131)(font "Arial" ))
-	(pt 632 2136)
-	(pt 560 2136)
-	(bus)
-)
-(connector
-	(text "DDRWR_D_SEL1" (rect 570 2392 659 2403)(font "Arial" ))
-	(pt 656 2408)
-	(pt 560 2408)
-)
-(connector
-	(text "FIFO_MW[8..0]" (rect 194 2376 269 2387)(font "Arial" ))
-	(pt 296 2392)
-	(pt 184 2392)
-	(bus)
-)
-(connector
-	(text "VDM_SEL[3..0]" (rect 570 2416 646 2427)(font "Arial" ))
-	(pt 560 2432)
-	(pt 656 2432)
-	(bus)
-)
-(connector
-	(text "CLR_FIFO" (rect 202 2216 257 2227)(font "Arial" ))
-	(pt 296 2232)
-	(pt 192 2232)
-)
-(connector
-	(text "VA[12..0]" (rect 570 2168 616 2179)(font "Arial" ))
-	(pt 560 2184)
-	(pt 632 2184)
-	(bus)
-)
-(connector
-	(text "CC16[23..0]" (rect 3954 2752 4013 2763)(font "Arial" ))
-	(pt 4024 2768)
-	(pt 3944 2768)
-	(bus)
-)
-(connector
-	(pt 4240 2800)
-	(pt 4176 2800)
-	(bus)
-)
-(connector
-	(text "PIXEL_CLK" (rect 3946 2848 4007 2859)(font "Arial" ))
-	(pt 3936 2864)
-	(pt 4024 2864)
-)
-(connector
-	(pt 4104 2920)
-	(pt 4104 2888)
-	(bus)
-)
-(connector
-	(text "CCSEL[2..0]" (rect 4010 2904 4071 2915)(font "Arial" ))
-	(pt 4000 2920)
-	(pt 4104 2920)
-	(bus)
-)
-(connector
-	(text "CCA[23..0]" (rect 3954 2768 4008 2779)(font "Arial" ))
-	(pt 4024 2784)
-	(pt 3944 2784)
-	(bus)
-)
-(connector
-	(text "CC24[23..0]" (rect 3954 2736 4013 2747)(font "Arial" ))
-	(pt 3944 2752)
-	(pt 4024 2752)
-	(bus)
-)
-(connector
-	(pt 3888 2800)
-	(pt 3888 2832)
-	(bus)
-)
-(connector
-	(pt 3888 2832)
-	(pt 4024 2832)
-	(bus)
-)
-(connector
-	(pt 3888 2848)
-	(pt 4024 2848)
-	(bus)
-)
-(connector
-	(pt 3888 2888)
-	(pt 3888 2848)
-	(bus)
-)
-(connector
-	(text "BORDER_COLOR[23..0]" (rect 3954 2720 4077 2731)(font "Arial" ))
-	(pt 4024 2736)
-	(pt 3944 2736)
-	(bus)
-)
-(connector
-	(pt 4240 2792)
-	(pt 4240 2800)
-	(bus)
-)
-(connector
-	(pt 4240 2800)
-	(pt 4240 2808)
-	(bus)
-)
-(connector
-	(pt 2568 2664)
-	(pt 2568 2568)
-	(bus)
-)
-(connector
-	(pt 2560 2664)
-	(pt 2568 2664)
-	(bus)
-)
-(connector
-	(text "CC16[23..19],CC16[15..10],CC16[7..3]" (rect 2530 2552 2718 2563)(font "Arial" ))
-	(pt 2568 2568)
-	(pt 2688 2568)
-	(bus)
-)
-(junction (pt 2984 1688))
-(junction (pt 792 1192))
-(junction (pt 792 1312))
-(junction (pt 792 1432))
-(junction (pt 792 1792))
-(junction (pt 792 1928))
-(junction (pt 792 1552))
-(junction (pt 792 1648))
-(junction (pt 2512 1728))
-(junction (pt 2512 1888))
-(junction (pt 2512 2048))
-(junction (pt 2512 1408))
-(junction (pt 2512 1568))
-(junction (pt 2512 1552))
-(junction (pt 2512 2208))
-(junction (pt 1344 2880))
-(junction (pt 1344 2824))
-(junction (pt 1344 2928))
-(junction (pt 1328 2904))
-(junction (pt 1328 2952))
-(junction (pt 4240 2800))
-(junction (pt 3232 3024))
-(junction (pt 1968 1424))
-(junction (pt 1608 1432))
diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd
new file mode 100644
index 0000000..3fbd54a
--- /dev/null
+++ b/FPGA_Quartus_13.1/Video/video.vhd
@@ -0,0 +1,1768 @@
+-- Copyright (C) 1991-2014 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
+-- CREATED		"Mon Jan 11 09:20:56 2016"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY work;
+
+ENTITY video IS 
+	PORT
+	(
+		MAIN_CLK :  IN  STD_LOGIC;
+		nFB_CS1 :  IN  STD_LOGIC;
+		nFB_CS2 :  IN  STD_LOGIC;
+		nFB_CS3 :  IN  STD_LOGIC;
+		nFB_WR :  IN  STD_LOGIC;
+		FB_SIZE0 :  IN  STD_LOGIC;
+		FB_SIZE1 :  IN  STD_LOGIC;
+		nRSTO :  IN  STD_LOGIC;
+		nFB_OE :  IN  STD_LOGIC;
+		FB_ALE :  IN  STD_LOGIC;
+		DDR_SYNC_66M :  IN  STD_LOGIC;
+		CLK33M :  IN  STD_LOGIC;
+		CLK25M :  IN  STD_LOGIC;
+		CLK_VIDEO :  IN  STD_LOGIC;
+		VR_BUSY :  IN  STD_LOGIC;
+		DDRCLK :  IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		FB_AD :  INOUT  STD_LOGIC_VECTOR(31 DOWNTO 0);
+		FB_ADR :  IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+		VD :  INOUT  STD_LOGIC_VECTOR(31 DOWNTO 0);
+		VDQS :  INOUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VR_D :  IN  STD_LOGIC_VECTOR(8 DOWNTO 0);
+		nBLANK :  OUT  STD_LOGIC;
+		nVWE :  OUT  STD_LOGIC;
+		nVCAS :  OUT  STD_LOGIC;
+		nVRAS :  OUT  STD_LOGIC;
+		nVCS :  OUT  STD_LOGIC;
+		nPD_VGA :  OUT  STD_LOGIC;
+		VCKE :  OUT  STD_LOGIC;
+		VSYNC :  OUT  STD_LOGIC;
+		HSYNC :  OUT  STD_LOGIC;
+		nSYNC :  OUT  STD_LOGIC;
+		VIDEO_TA :  OUT  STD_LOGIC;
+		PIXEL_CLK :  OUT  STD_LOGIC;
+		VIDEO_RECONFIG :  OUT  STD_LOGIC;
+		VR_WR :  OUT  STD_LOGIC;
+		VR_RD :  OUT  STD_LOGIC;
+		BA :  OUT  STD_LOGIC_VECTOR(1 DOWNTO 0);
+		VA :  OUT  STD_LOGIC_VECTOR(12 DOWNTO 0);
+		VB :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		VDM :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VG :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		VR :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END video;
+
+ARCHITECTURE bdf_type OF video IS 
+
+ATTRIBUTE black_box : BOOLEAN;
+ATTRIBUTE noopt : BOOLEAN;
+
+COMPONENT mux41_0
+	PORT(S0 : IN STD_LOGIC;
+		 S1 : IN STD_LOGIC;
+		 D0 : IN STD_LOGIC;
+		 INH : IN STD_LOGIC;
+		 D1 : IN STD_LOGIC;
+		 Q : OUT STD_LOGIC);
+END COMPONENT;
+ATTRIBUTE black_box OF mux41_0: COMPONENT IS true;
+ATTRIBUTE noopt OF mux41_0: COMPONENT IS true;
+
+COMPONENT mux41_1
+	PORT(S0 : IN STD_LOGIC;
+		 S1 : IN STD_LOGIC;
+		 D0 : IN STD_LOGIC;
+		 INH : IN STD_LOGIC;
+		 D1 : IN STD_LOGIC;
+		 Q : OUT STD_LOGIC);
+END COMPONENT;
+ATTRIBUTE black_box OF mux41_1: COMPONENT IS true;
+ATTRIBUTE noopt OF mux41_1: COMPONENT IS true;
+
+COMPONENT mux41_2
+	PORT(S0 : IN STD_LOGIC;
+		 D2 : IN STD_LOGIC;
+		 S1 : IN STD_LOGIC;
+		 D0 : IN STD_LOGIC;
+		 INH : IN STD_LOGIC;
+		 D1 : IN STD_LOGIC;
+		 Q : OUT STD_LOGIC);
+END COMPONENT;
+ATTRIBUTE black_box OF mux41_2: COMPONENT IS true;
+ATTRIBUTE noopt OF mux41_2: COMPONENT IS true;
+
+COMPONENT mux41_3
+	PORT(S0 : IN STD_LOGIC;
+		 D2 : IN STD_LOGIC;
+		 S1 : IN STD_LOGIC;
+		 D0 : IN STD_LOGIC;
+		 INH : IN STD_LOGIC;
+		 D1 : IN STD_LOGIC;
+		 Q : OUT STD_LOGIC);
+END COMPONENT;
+ATTRIBUTE black_box OF mux41_3: COMPONENT IS true;
+ATTRIBUTE noopt OF mux41_3: COMPONENT IS true;
+
+COMPONENT mux41_4
+	PORT(S0 : IN STD_LOGIC;
+		 D2 : IN STD_LOGIC;
+		 S1 : IN STD_LOGIC;
+		 D0 : IN STD_LOGIC;
+		 INH : IN STD_LOGIC;
+		 D1 : IN STD_LOGIC;
+		 Q : OUT STD_LOGIC);
+END COMPONENT;
+ATTRIBUTE black_box OF mux41_4: COMPONENT IS true;
+ATTRIBUTE noopt OF mux41_4: COMPONENT IS true;
+
+COMPONENT mux41_5
+	PORT(S0 : IN STD_LOGIC;
+		 D2 : IN STD_LOGIC;
+		 S1 : IN STD_LOGIC;
+		 D0 : IN STD_LOGIC;
+		 INH : IN STD_LOGIC;
+		 D1 : IN STD_LOGIC;
+		 Q : OUT STD_LOGIC);
+END COMPONENT;
+ATTRIBUTE black_box OF mux41_5: COMPONENT IS true;
+ATTRIBUTE noopt OF mux41_5: COMPONENT IS true;
+
+COMPONENT altdpram2
+	PORT(wren_a : IN STD_LOGIC;
+		 wren_b : IN STD_LOGIC;
+		 clock_a : IN STD_LOGIC;
+		 clock_b : IN STD_LOGIC;
+		 address_a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 address_b : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data_a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data_b : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 q_a : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 q_b : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT blitter
+	PORT(nRSTO : IN STD_LOGIC;
+		 MAIN_CLK : IN STD_LOGIC;
+		 FB_ALE : IN STD_LOGIC;
+		 nFB_WR : IN STD_LOGIC;
+		 nFB_OE : IN STD_LOGIC;
+		 FB_SIZE0 : IN STD_LOGIC;
+		 FB_SIZE1 : IN STD_LOGIC;
+		 BLITTER_ON : IN STD_LOGIC;
+		 nFB_CS1 : IN STD_LOGIC;
+		 nFB_CS2 : IN STD_LOGIC;
+		 nFB_CS3 : IN STD_LOGIC;
+		 DDRCLK0 : IN STD_LOGIC;
+		 SR_BLITTER_DACK : IN STD_LOGIC;
+		 BLITTER_DACK : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 BLITTER_DIN : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 BLITTER_RUN : OUT STD_LOGIC;
+		 BLITTER_SIG : OUT STD_LOGIC;
+		 BLITTER_WR : OUT STD_LOGIC;
+		 BLITTER_TA : OUT STD_LOGIC;
+		 BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT ddr_ctr
+	PORT(nFB_CS1 : IN STD_LOGIC;
+		 nFB_CS2 : IN STD_LOGIC;
+		 nFB_CS3 : IN STD_LOGIC;
+		 nFB_OE : IN STD_LOGIC;
+		 FB_SIZE0 : IN STD_LOGIC;
+		 FB_SIZE1 : IN STD_LOGIC;
+		 nRSTO : IN STD_LOGIC;
+		 MAIN_CLK : IN STD_LOGIC;
+		 FB_ALE : IN STD_LOGIC;
+		 nFB_WR : IN STD_LOGIC;
+		 DDR_SYNC_66M : IN STD_LOGIC;
+		 BLITTER_SIG : IN STD_LOGIC;
+		 BLITTER_WR : IN STD_LOGIC;
+		 DDRCLK0 : IN STD_LOGIC;
+		 CLK33M : IN STD_LOGIC;
+		 CLR_FIFO : IN STD_LOGIC;
+		 BLITTER_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 FIFO_MW : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+		 VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 nVWE : OUT STD_LOGIC;
+		 nVRAS : OUT STD_LOGIC;
+		 nVCS : OUT STD_LOGIC;
+		 VCKE : OUT STD_LOGIC;
+		 nVCAS : OUT STD_LOGIC;
+		 SR_FIFO_WRE : OUT STD_LOGIC;
+		 SR_DDR_FB : OUT STD_LOGIC;
+		 SR_DDR_WR : OUT STD_LOGIC;
+		 SR_DDRWR_D_SEL : OUT STD_LOGIC;
+		 VIDEO_DDR_TA : OUT STD_LOGIC;
+		 SR_BLITTER_DACK : OUT STD_LOGIC;
+		 DDRWR_D_SEL1 : OUT STD_LOGIC;
+		 BA : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 FB_LE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 FB_VDOE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SR_VDMP : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
+		 VDM_SEL : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT altdpram1
+	PORT(wren_a : IN STD_LOGIC;
+		 wren_b : IN STD_LOGIC;
+		 clock_a : IN STD_LOGIC;
+		 clock_b : IN STD_LOGIC;
+		 address_a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 address_b : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data_a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 data_b : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 q_a : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 q_b : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_fifo_dc0
+	PORT(wrreq : IN STD_LOGIC;
+		 wrclk : IN STD_LOGIC;
+		 rdreq : IN STD_LOGIC;
+		 rdclk : IN STD_LOGIC;
+		 aclr : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 rdempty : OUT STD_LOGIC;
+		 q : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 wrusedw : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT altddio_bidir0
+	PORT(oe : IN STD_LOGIC;
+		 inclock : IN STD_LOGIC;
+		 outclock : IN STD_LOGIC;
+		 datain_h : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 datain_l : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 padio : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 combout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 dataout_h : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 dataout_l : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_ff4
+	PORT(clock : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_muxvdm
+	PORT(data0x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data10x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data11x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data12x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data13x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data14x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data15x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data1x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data2x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data3x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data4x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data5x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data6x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data7x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data8x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data9x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 result : OUT STD_LOGIC_VECTOR(127 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_mux3
+	PORT(data1 : IN STD_LOGIC;
+		 data0 : IN STD_LOGIC;
+		 sel : IN STD_LOGIC;
+		 result : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT lpm_bustri_long
+	PORT(enabledt : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 tridata : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_ff5
+	PORT(clock : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_ff1
+	PORT(clock : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_ff0
+	PORT(clock : IN STD_LOGIC;
+		 enable : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT altddio_out0
+	PORT(outclock : IN STD_LOGIC;
+		 datain_h : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 datain_l : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 dataout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_mux0
+	PORT(clock : IN STD_LOGIC;
+		 data0x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 data1x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 data2x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 data3x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_mux5
+	PORT(data0x : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+		 data1x : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+		 data2x : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+		 data3x : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+		 sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 result : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_constant2
+	PORT(		 result : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_mux1
+	PORT(clock : IN STD_LOGIC;
+		 data0x : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 data1x : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 data2x : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 data3x : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 data4x : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 data5x : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 data6x : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 data7x : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 result : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_mux2
+	PORT(clock : IN STD_LOGIC;
+		 data0x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data10x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data11x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data12x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data13x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data14x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data15x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data1x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data2x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data3x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data4x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data5x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data6x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data7x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data8x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data9x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 result : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_shiftreg4
+	PORT(clock : IN STD_LOGIC;
+		 shiftin : IN STD_LOGIC;
+		 shiftout : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT lpm_latch0
+	PORT(gate : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_ff6
+	PORT(clock : IN STD_LOGIC;
+		 enable : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(127 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_ff3
+	PORT(clock : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT altddio_out2
+	PORT(outclock : IN STD_LOGIC;
+		 datain_h : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 datain_l : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 dataout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_bustri1
+	PORT(enabledt : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 tridata : INOUT STD_LOGIC_VECTOR(2 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_bustri_byt
+	PORT(enabledt : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 tridata : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_constant0
+	PORT(		 result : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_muxdz
+	PORT(clock : IN STD_LOGIC;
+		 clken : IN STD_LOGIC;
+		 sel : IN STD_LOGIC;
+		 data0x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data1x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 result : OUT STD_LOGIC_VECTOR(127 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_fifodz
+	PORT(wrreq : IN STD_LOGIC;
+		 rdreq : IN STD_LOGIC;
+		 clock : IN STD_LOGIC;
+		 aclr : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(127 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_bustri3
+	PORT(enabledt : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 tridata : INOUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_mux6
+	PORT(clock : IN STD_LOGIC;
+		 data0x : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 data1x : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 data2x : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 data3x : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 data4x : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 data5x : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 data6x : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 data7x : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 result : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_constant1
+	PORT(		 result : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_mux4
+	PORT(sel : IN STD_LOGIC;
+		 data0x : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+		 data1x : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+		 result : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_constant3
+	PORT(		 result : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_shiftreg6
+	PORT(clock : IN STD_LOGIC;
+		 shiftin : IN STD_LOGIC;
+		 q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_shiftreg0
+	PORT(load : IN STD_LOGIC;
+		 clock : IN STD_LOGIC;
+		 shiftin : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 shiftout : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT altdpram0
+	PORT(wren_a : IN STD_LOGIC;
+		 wren_b : IN STD_LOGIC;
+		 clock_a : IN STD_LOGIC;
+		 clock_b : IN STD_LOGIC;
+		 address_a : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 address_b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 data_a : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 data_b : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 q_a : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 q_b : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT video_mod_mux_clutctr
+	PORT(nRSTO : IN STD_LOGIC;
+		 MAIN_CLK : IN STD_LOGIC;
+		 nFB_CS1 : IN STD_LOGIC;
+		 nFB_CS2 : IN STD_LOGIC;
+		 nFB_CS3 : IN STD_LOGIC;
+		 nFB_WR : IN STD_LOGIC;
+		 nFB_OE : IN STD_LOGIC;
+		 FB_SIZE0 : IN STD_LOGIC;
+		 FB_SIZE1 : IN STD_LOGIC;
+		 nFB_BURST : IN STD_LOGIC;
+		 CLK33M : IN STD_LOGIC;
+		 CLK25M : IN STD_LOGIC;
+		 BLITTER_RUN : IN STD_LOGIC;
+		 CLK_VIDEO : IN STD_LOGIC;
+		 VR_BUSY : IN STD_LOGIC;
+		 FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 VR_D : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+		 COLOR8 : OUT STD_LOGIC;
+		 ACP_CLUT_RD : OUT STD_LOGIC;
+		 COLOR1 : OUT STD_LOGIC;
+		 FALCON_CLUT_RDH : OUT STD_LOGIC;
+		 FALCON_CLUT_RDL : OUT STD_LOGIC;
+		 ST_CLUT_RD : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 VSYNC : OUT STD_LOGIC;
+		 nBLANK : OUT STD_LOGIC;
+		 nSYNC : OUT STD_LOGIC;
+		 nPD_VGA : OUT STD_LOGIC;
+		 FIFO_RDE : OUT STD_LOGIC;
+		 COLOR2 : OUT STD_LOGIC;
+		 COLOR4 : OUT STD_LOGIC;
+		 PIXEL_CLK : OUT STD_LOGIC;
+		 BLITTER_ON : OUT STD_LOGIC;
+		 VIDEO_MOD_TA : OUT STD_LOGIC;
+		 INTER_ZEI : OUT STD_LOGIC;
+		 DOP_FIFO_CLR : OUT STD_LOGIC;
+		 VIDEO_RECONFIG : OUT STD_LOGIC;
+		 VR_WR : OUT STD_LOGIC;
+		 VR_RD : OUT STD_LOGIC;
+		 CLR_FIFO : OUT STD_LOGIC;
+		 ACP_CLUT_WR : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 BORDER_COLOR : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 CCSEL : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 CLUT_MUX_ADR : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CLUT_OFF : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 FALCON_CLUT_WR : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 ST_CLUT_WR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 VIDEO_RAM_CTR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+SIGNAL	ACP_CLUT_RD :  STD_LOGIC;
+SIGNAL	ACP_CLUT_WR :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	BLITTER_ADR :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	BLITTER_DACK :  STD_LOGIC_VECTOR(4 DOWNTO 0);
+SIGNAL	BLITTER_DIN :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	BLITTER_DOUT :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	BLITTER_ON :  STD_LOGIC;
+SIGNAL	BLITTER_RUN :  STD_LOGIC;
+SIGNAL	BLITTER_SIG :  STD_LOGIC;
+SIGNAL	BLITTER_TA :  STD_LOGIC;
+SIGNAL	BLITTER_WR :  STD_LOGIC;
+SIGNAL	BORDER_COLOR :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	CC16 :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	CC24 :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	CCA :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	CCF :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	CCS :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	CCSEL :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+SIGNAL	CLR_FIFO :  STD_LOGIC;
+SIGNAL	CLUT_ADR :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CLUT_ADR1A :  STD_LOGIC;
+SIGNAL	CLUT_ADR2A :  STD_LOGIC;
+SIGNAL	CLUT_ADR3A :  STD_LOGIC;
+SIGNAL	CLUT_ADR4A :  STD_LOGIC;
+SIGNAL	CLUT_ADR5A :  STD_LOGIC;
+SIGNAL	CLUT_ADR6A :  STD_LOGIC;
+SIGNAL	CLUT_ADR7A :  STD_LOGIC;
+SIGNAL	CLUT_MUX_ADR :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	CLUT_OFF :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	COLOR1 :  STD_LOGIC;
+SIGNAL	COLOR2 :  STD_LOGIC;
+SIGNAL	COLOR4 :  STD_LOGIC;
+SIGNAL	COLOR8 :  STD_LOGIC;
+SIGNAL	DDR_FB :  STD_LOGIC_VECTOR(4 DOWNTO 0);
+SIGNAL	DDR_WR :  STD_LOGIC;
+SIGNAL	DDRWR_D_SEL :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	DOP_FIFO_CLR :  STD_LOGIC;
+SIGNAL	FALCON_CLUT_RDH :  STD_LOGIC;
+SIGNAL	FALCON_CLUT_RDL :  STD_LOGIC;
+SIGNAL	FALCON_CLUT_WR :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	FB_DDR :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	FB_LE :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	FB_VDOE :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	FIFO_D :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	FIFO_MW :  STD_LOGIC_VECTOR(8 DOWNTO 0);
+SIGNAL	FIFO_RDE :  STD_LOGIC;
+SIGNAL	FIFO_WRE :  STD_LOGIC;
+SIGNAL	INTER_ZEI :  STD_LOGIC;
+SIGNAL	nFB_BURST :  STD_LOGIC;
+SIGNAL	PIXEL_CLK_ALTERA_SYNTHESIZED :  STD_LOGIC;
+SIGNAL	SR_BLITTER_DACK :  STD_LOGIC;
+SIGNAL	SR_DDR_FB :  STD_LOGIC;
+SIGNAL	SR_DDR_WR :  STD_LOGIC;
+SIGNAL	SR_DDRWR_D_SEL :  STD_LOGIC;
+SIGNAL	SR_FIFO_WRE :  STD_LOGIC;
+SIGNAL	SR_VDMP :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ST_CLUT_RD :  STD_LOGIC;
+SIGNAL	ST_CLUT_WR :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	VDM_SEL :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	VDMA :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	VDMB :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	VDMC :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	VDMP :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	VDOUT_OE :  STD_LOGIC;
+SIGNAL	VDP_IN :  STD_LOGIC_VECTOR(63 DOWNTO 0);
+SIGNAL	VDP_OUT :  STD_LOGIC_VECTOR(63 DOWNTO 0);
+SIGNAL	VDR :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	VDVZ :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	VIDEO_DDR_TA :  STD_LOGIC;
+SIGNAL	VIDEO_MOD_TA :  STD_LOGIC;
+SIGNAL	VIDEO_RAM_CTR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ZR_C8 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ZR_C8B :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_60 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	DFF_inst93 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_61 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_11 :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_12 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_13 :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_14 :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_15 :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_16 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_18 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_19 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_20 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_21 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_22 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_23 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_24 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_25 :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_26 :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_62 :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_29 :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_30 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_31 :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_32 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_33 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_34 :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_63 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_36 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_38 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_40 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_41 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_42 :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_43 :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_44 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_45 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_46 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_47 :  STD_LOGIC_VECTOR(6 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_48 :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	DFF_inst91 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_64 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_49 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_50 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_51 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_52 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_53 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_54 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_55 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_56 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_57 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_65 :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+
+SIGNAL	GDFX_TEMP_SIGNAL_16 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_0 :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_6 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_5 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_4 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_3 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_2 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_1 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_15 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_14 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_13 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_12 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_11 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_10 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_9 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_8 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_7 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+
+BEGIN 
+VB(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(7 DOWNTO 0);
+VG(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(15 DOWNTO 8);
+VR(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(23 DOWNTO 16);
+SYNTHESIZED_WIRE_0 <= '0';
+SYNTHESIZED_WIRE_1 <= '0';
+SYNTHESIZED_WIRE_2 <= '0';
+SYNTHESIZED_WIRE_3 <= '0';
+SYNTHESIZED_WIRE_4 <= '0';
+SYNTHESIZED_WIRE_5 <= '0';
+SYNTHESIZED_WIRE_19 <= '0';
+SYNTHESIZED_WIRE_20 <= '0';
+SYNTHESIZED_WIRE_21 <= '0';
+SYNTHESIZED_WIRE_22 <= '0';
+SYNTHESIZED_WIRE_23 <= '0';
+SYNTHESIZED_WIRE_24 <= '0';
+SYNTHESIZED_WIRE_55 <= '0';
+SYNTHESIZED_WIRE_56 <= '0';
+SYNTHESIZED_WIRE_57 <= '0';
+
+CC16(18) <= GDFX_TEMP_SIGNAL_16(7);
+CC16(17) <= GDFX_TEMP_SIGNAL_16(6);
+CC16(16) <= GDFX_TEMP_SIGNAL_16(5);
+CC16(9) <= GDFX_TEMP_SIGNAL_16(4);
+CC16(8) <= GDFX_TEMP_SIGNAL_16(3);
+CC16(2) <= GDFX_TEMP_SIGNAL_16(2);
+CC16(1) <= GDFX_TEMP_SIGNAL_16(1);
+CC16(0) <= GDFX_TEMP_SIGNAL_16(0);
+
+CC16(23) <= GDFX_TEMP_SIGNAL_0(15);
+CC16(22) <= GDFX_TEMP_SIGNAL_0(14);
+CC16(21) <= GDFX_TEMP_SIGNAL_0(13);
+CC16(20) <= GDFX_TEMP_SIGNAL_0(12);
+CC16(19) <= GDFX_TEMP_SIGNAL_0(11);
+CC16(15) <= GDFX_TEMP_SIGNAL_0(10);
+CC16(14) <= GDFX_TEMP_SIGNAL_0(9);
+CC16(13) <= GDFX_TEMP_SIGNAL_0(8);
+CC16(12) <= GDFX_TEMP_SIGNAL_0(7);
+CC16(11) <= GDFX_TEMP_SIGNAL_0(6);
+CC16(10) <= GDFX_TEMP_SIGNAL_0(5);
+CC16(7) <= GDFX_TEMP_SIGNAL_0(4);
+CC16(6) <= GDFX_TEMP_SIGNAL_0(3);
+CC16(5) <= GDFX_TEMP_SIGNAL_0(2);
+CC16(4) <= GDFX_TEMP_SIGNAL_0(1);
+CC16(3) <= GDFX_TEMP_SIGNAL_0(0);
+
+GDFX_TEMP_SIGNAL_6 <= (VDMB(7 DOWNTO 0) & VDMA(127 DOWNTO 8));
+GDFX_TEMP_SIGNAL_5 <= (VDMB(15 DOWNTO 0) & VDMA(127 DOWNTO 16));
+GDFX_TEMP_SIGNAL_4 <= (VDMB(23 DOWNTO 0) & VDMA(127 DOWNTO 24));
+GDFX_TEMP_SIGNAL_3 <= (VDMB(31 DOWNTO 0) & VDMA(127 DOWNTO 32));
+GDFX_TEMP_SIGNAL_2 <= (VDMB(39 DOWNTO 0) & VDMA(127 DOWNTO 40));
+GDFX_TEMP_SIGNAL_1 <= (VDMB(47 DOWNTO 0) & VDMA(127 DOWNTO 48));
+GDFX_TEMP_SIGNAL_15 <= (VDMB(55 DOWNTO 0) & VDMA(127 DOWNTO 56));
+GDFX_TEMP_SIGNAL_14 <= (VDMB(63 DOWNTO 0) & VDMA(127 DOWNTO 64));
+GDFX_TEMP_SIGNAL_13 <= (VDMB(71 DOWNTO 0) & VDMA(127 DOWNTO 72));
+GDFX_TEMP_SIGNAL_12 <= (VDMB(79 DOWNTO 0) & VDMA(127 DOWNTO 80));
+GDFX_TEMP_SIGNAL_11 <= (VDMB(87 DOWNTO 0) & VDMA(127 DOWNTO 88));
+GDFX_TEMP_SIGNAL_10 <= (VDMB(95 DOWNTO 0) & VDMA(127 DOWNTO 96));
+GDFX_TEMP_SIGNAL_9 <= (VDMB(103 DOWNTO 0) & VDMA(127 DOWNTO 104));
+GDFX_TEMP_SIGNAL_8 <= (VDMB(111 DOWNTO 0) & VDMA(127 DOWNTO 112));
+GDFX_TEMP_SIGNAL_7 <= (VDMB(119 DOWNTO 0) & VDMA(127 DOWNTO 120));
+
+
+b2v_ACP_CLUT_RAM : altdpram2
+PORT MAP(wren_a => ACP_CLUT_WR(3),
+		 wren_b => SYNTHESIZED_WIRE_0,
+		 clock_a => MAIN_CLK,
+		 clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 address_a => FB_ADR(9 DOWNTO 2),
+		 address_b => ZR_C8B,
+		 data_a => FB_AD(7 DOWNTO 0),
+         data_b => (OTHERS => '0'),
+		 q_a => SYNTHESIZED_WIRE_30,
+		 q_b => CCA(7 DOWNTO 0));
+
+
+b2v_ACP_CLUT_RAM54 : altdpram2
+PORT MAP(wren_a => ACP_CLUT_WR(2),
+		 wren_b => SYNTHESIZED_WIRE_1,
+		 clock_a => MAIN_CLK,
+		 clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 address_a => FB_ADR(9 DOWNTO 2),
+		 address_b => ZR_C8B,
+		 data_a => FB_AD(15 DOWNTO 8),
+         data_b => (OTHERS => '0'),
+		 q_a => SYNTHESIZED_WIRE_32,
+		 q_b => CCA(15 DOWNTO 8));
+
+
+b2v_ACP_CLUT_RAM55 : altdpram2
+PORT MAP(wren_a => ACP_CLUT_WR(1),
+		 wren_b => SYNTHESIZED_WIRE_2,
+		 clock_a => MAIN_CLK,
+		 clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 address_a => FB_ADR(9 DOWNTO 2),
+		 address_b => ZR_C8B,
+		 data_a => FB_AD(23 DOWNTO 16),
+         data_b => (OTHERS => '0'),
+		 q_a => SYNTHESIZED_WIRE_33,
+		 q_b => CCA(23 DOWNTO 16));
+
+
+b2v_BLITTER : blitter
+PORT MAP(nRSTO => nRSTO,
+		 MAIN_CLK => MAIN_CLK,
+		 FB_ALE => FB_ALE,
+		 nFB_WR => nFB_WR,
+		 nFB_OE => nFB_OE,
+		 FB_SIZE0 => FB_SIZE0,
+		 FB_SIZE1 => FB_SIZE1,
+		 BLITTER_ON => BLITTER_ON,
+		 nFB_CS1 => nFB_CS1,
+		 nFB_CS2 => nFB_CS2,
+		 nFB_CS3 => nFB_CS3,
+		 DDRCLK0 => DDRCLK(0),
+		 SR_BLITTER_DACK => SR_BLITTER_DACK,
+		 BLITTER_DACK => BLITTER_DACK,
+		 BLITTER_DIN => BLITTER_DIN,
+		 FB_AD => FB_AD,
+		 FB_ADR => FB_ADR,
+		 VIDEO_RAM_CTR => VIDEO_RAM_CTR,
+		 BLITTER_RUN => BLITTER_RUN,
+		 BLITTER_SIG => BLITTER_SIG,
+		 BLITTER_WR => BLITTER_WR,
+		 BLITTER_TA => BLITTER_TA,
+		 BLITTER_ADR => BLITTER_ADR,
+		 BLITTER_DOUT => BLITTER_DOUT);
+
+
+b2v_DDR_CTR : ddr_ctr
+PORT MAP(nFB_CS1 => nFB_CS1,
+		 nFB_CS2 => nFB_CS2,
+		 nFB_CS3 => nFB_CS3,
+		 nFB_OE => nFB_OE,
+		 FB_SIZE0 => FB_SIZE0,
+		 FB_SIZE1 => FB_SIZE1,
+		 nRSTO => nRSTO,
+		 MAIN_CLK => MAIN_CLK,
+		 FB_ALE => FB_ALE,
+		 nFB_WR => nFB_WR,
+		 DDR_SYNC_66M => DDR_SYNC_66M,
+		 BLITTER_SIG => BLITTER_SIG,
+		 BLITTER_WR => BLITTER_WR,
+		 DDRCLK0 => DDRCLK(0),
+		 CLK33M => CLK33M,
+		 CLR_FIFO => CLR_FIFO,
+		 BLITTER_ADR => BLITTER_ADR,
+		 FB_AD => FB_AD,
+		 FB_ADR => FB_ADR,
+		 FIFO_MW => FIFO_MW,
+		 VIDEO_RAM_CTR => VIDEO_RAM_CTR,
+		 nVWE => nVWE,
+		 nVRAS => nVRAS,
+		 nVCS => nVCS,
+		 VCKE => VCKE,
+		 nVCAS => nVCAS,
+		 SR_FIFO_WRE => SR_FIFO_WRE,
+		 SR_DDR_FB => SR_DDR_FB,
+		 SR_DDR_WR => SR_DDR_WR,
+		 SR_DDRWR_D_SEL => SR_DDRWR_D_SEL,
+		 VIDEO_DDR_TA => VIDEO_DDR_TA,
+		 SR_BLITTER_DACK => SR_BLITTER_DACK,
+		 DDRWR_D_SEL1 => DDRWR_D_SEL(1),
+		 BA => BA,
+		 FB_LE => FB_LE,
+		 FB_VDOE => FB_VDOE,
+		 SR_VDMP => SR_VDMP,
+		 VA => VA,
+		 VDM_SEL => VDM_SEL);
+
+
+b2v_FALCON_CLUT_BLUE : altdpram1
+PORT MAP(wren_a => FALCON_CLUT_WR(3),
+		 wren_b => SYNTHESIZED_WIRE_3,
+		 clock_a => MAIN_CLK,
+		 clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 address_a => FB_ADR(9 DOWNTO 2),
+		 address_b => CLUT_ADR,
+		 data_a => FB_AD(23 DOWNTO 18),
+         data_b => (OTHERS => '0'),
+		 q_a => SYNTHESIZED_WIRE_45,
+		 q_b => CCF(7 DOWNTO 2));
+
+
+b2v_FALCON_CLUT_GREEN : altdpram1
+PORT MAP(wren_a => FALCON_CLUT_WR(1),
+		 wren_b => SYNTHESIZED_WIRE_4,
+		 clock_a => MAIN_CLK,
+		 clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 address_a => FB_ADR(9 DOWNTO 2),
+		 address_b => CLUT_ADR,
+		 data_a => FB_AD(23 DOWNTO 18),
+         data_b => (OTHERS => '0'),
+		 q_a => SYNTHESIZED_WIRE_44,
+		 q_b => CCF(15 DOWNTO 10));
+
+
+b2v_FALCON_CLUT_RED : altdpram1
+PORT MAP(wren_a => FALCON_CLUT_WR(0),
+		 wren_b => SYNTHESIZED_WIRE_5,
+		 clock_a => MAIN_CLK,
+		 clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 address_a => FB_ADR(9 DOWNTO 2),
+		 address_b => CLUT_ADR,
+		 data_a => FB_AD(31 DOWNTO 26),
+         data_b => (OTHERS => '0'),
+		 q_a => SYNTHESIZED_WIRE_41,
+		 q_b => CCF(23 DOWNTO 18));
+
+
+b2v_inst : lpm_fifo_dc0
+PORT MAP(wrreq => FIFO_WRE,
+		 wrclk => DDRCLK(0),
+		 rdreq => SYNTHESIZED_WIRE_60,
+		 rdclk => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 aclr => CLR_FIFO,
+		 data => VDMC,
+		 q => SYNTHESIZED_WIRE_63,
+		 wrusedw => FIFO_MW);
+
+
+b2v_inst1 : altddio_bidir0
+PORT MAP(oe => VDOUT_OE,
+		 inclock => DDRCLK(1),
+		 outclock => DDRCLK(3),
+		 datain_h => VDP_OUT(63 DOWNTO 32),
+		 datain_l => VDP_OUT(31 DOWNTO 0),
+		 padio => VD,
+		 combout => SYNTHESIZED_WIRE_15,
+		 dataout_h => VDP_IN(31 DOWNTO 0),
+		 dataout_l => VDP_IN(63 DOWNTO 32));
+
+
+b2v_inst10 : lpm_ff4
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data => SYNTHESIZED_WIRE_7,
+		 q => GDFX_TEMP_SIGNAL_0);
+
+
+b2v_inst100 : lpm_muxvdm
+PORT MAP(data0x => VDMB,
+		 data10x => GDFX_TEMP_SIGNAL_1,
+		 data11x => GDFX_TEMP_SIGNAL_2,
+		 data12x => GDFX_TEMP_SIGNAL_3,
+		 data13x => GDFX_TEMP_SIGNAL_4,
+		 data14x => GDFX_TEMP_SIGNAL_5,
+		 data15x => GDFX_TEMP_SIGNAL_6,
+		 data1x => GDFX_TEMP_SIGNAL_7,
+		 data2x => GDFX_TEMP_SIGNAL_8,
+		 data3x => GDFX_TEMP_SIGNAL_9,
+		 data4x => GDFX_TEMP_SIGNAL_10,
+		 data5x => GDFX_TEMP_SIGNAL_11,
+		 data6x => GDFX_TEMP_SIGNAL_12,
+		 data7x => GDFX_TEMP_SIGNAL_13,
+		 data8x => GDFX_TEMP_SIGNAL_14,
+		 data9x => GDFX_TEMP_SIGNAL_15,
+		 sel => VDM_SEL,
+		 result => VDMC);
+
+
+b2v_inst102 : lpm_mux3
+PORT MAP(data1 => DFF_inst93,
+		 data0 => ZR_C8(0),
+		 sel => COLOR1,
+		 result => ZR_C8B(0));
+
+
+CLUT_ADR(4) <= CLUT_OFF(0) OR SYNTHESIZED_WIRE_8;
+
+
+CLUT_ADR(6) <= CLUT_OFF(2) OR SYNTHESIZED_WIRE_9;
+
+
+SYNTHESIZED_WIRE_61 <= COLOR8 OR COLOR4;
+
+
+CLUT_ADR(2) <= CLUT_ADR2A AND SYNTHESIZED_WIRE_61;
+
+
+SYNTHESIZED_WIRE_16 <= COLOR4 OR COLOR8 OR COLOR2;
+
+
+b2v_inst108 : lpm_bustri_long
+PORT MAP(enabledt => FB_VDOE(0),
+		 data => VDR,
+		 tridata => FB_AD);
+
+
+b2v_inst109 : lpm_bustri_long
+PORT MAP(enabledt => FB_VDOE(1),
+		 data => SYNTHESIZED_WIRE_11,
+		 tridata => FB_AD);
+
+
+b2v_inst11 : lpm_ff5
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data => SYNTHESIZED_WIRE_12,
+		 q => ZR_C8);
+
+
+b2v_inst110 : lpm_bustri_long
+PORT MAP(enabledt => FB_VDOE(2),
+		 data => SYNTHESIZED_WIRE_13,
+		 tridata => FB_AD);
+
+
+b2v_inst119 : lpm_bustri_long
+PORT MAP(enabledt => FB_VDOE(3),
+		 data => SYNTHESIZED_WIRE_14,
+		 tridata => FB_AD);
+
+
+b2v_inst12 : lpm_ff1
+PORT MAP(clock => DDRCLK(0),
+		 data => VDP_IN(31 DOWNTO 0),
+		 q => VDVZ(31 DOWNTO 0));
+
+
+b2v_inst13 : lpm_ff0
+PORT MAP(clock => DDR_SYNC_66M,
+		 enable => FB_LE(0),
+		 data => FB_AD,
+		 q => FB_DDR(127 DOWNTO 96));
+
+
+b2v_inst14 : lpm_ff0
+PORT MAP(clock => DDR_SYNC_66M,
+		 enable => FB_LE(1),
+		 data => FB_AD,
+		 q => FB_DDR(95 DOWNTO 64));
+
+
+b2v_inst15 : lpm_ff0
+PORT MAP(clock => DDR_SYNC_66M,
+		 enable => FB_LE(2),
+		 data => FB_AD,
+		 q => FB_DDR(63 DOWNTO 32));
+
+
+b2v_inst16 : lpm_ff0
+PORT MAP(clock => DDR_SYNC_66M,
+		 enable => FB_LE(3),
+		 data => FB_AD,
+		 q => FB_DDR(31 DOWNTO 0));
+
+
+b2v_inst17 : lpm_ff0
+PORT MAP(clock => DDRCLK(0),
+		 enable => DDR_FB(1),
+		 data => VDP_IN(31 DOWNTO 0),
+		 q => SYNTHESIZED_WIRE_11);
+
+
+b2v_inst18 : lpm_ff0
+PORT MAP(clock => DDRCLK(0),
+		 enable => DDR_FB(0),
+		 data => VDP_IN(63 DOWNTO 32),
+		 q => SYNTHESIZED_WIRE_13);
+
+
+b2v_inst19 : lpm_ff0
+PORT MAP(clock => DDRCLK(0),
+		 enable => DDR_FB(0),
+		 data => VDP_IN(31 DOWNTO 0),
+		 q => SYNTHESIZED_WIRE_14);
+
+
+b2v_inst2 : altddio_out0
+PORT MAP(outclock => DDRCLK(3),
+		 datain_h => VDMP(7 DOWNTO 4),
+		 datain_l => VDMP(3 DOWNTO 0),
+		 dataout => VDM);
+
+
+b2v_inst20 : lpm_ff1
+PORT MAP(clock => DDRCLK(0),
+		 data => VDVZ(31 DOWNTO 0),
+		 q => VDVZ(95 DOWNTO 64));
+
+
+b2v_inst21 : lpm_mux0
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data0x => FIFO_D(127 DOWNTO 96),
+		 data1x => FIFO_D(95 DOWNTO 64),
+		 data2x => FIFO_D(63 DOWNTO 32),
+		 data3x => FIFO_D(31 DOWNTO 0),
+		 sel => CLUT_MUX_ADR(1 DOWNTO 0),
+		 result => SYNTHESIZED_WIRE_48);
+
+
+b2v_inst22 : lpm_mux5
+PORT MAP(data0x => FB_DDR(127 DOWNTO 64),
+		 data1x => FB_DDR(63 DOWNTO 0),
+		 data2x => BLITTER_DOUT(127 DOWNTO 64),
+		 data3x => BLITTER_DOUT(63 DOWNTO 0),
+		 sel => DDRWR_D_SEL,
+		 result => VDP_OUT);
+
+
+b2v_inst23 : lpm_constant2
+PORT MAP(		 result => GDFX_TEMP_SIGNAL_16);
+
+
+b2v_inst24 : lpm_mux1
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data0x => FIFO_D(127 DOWNTO 112),
+		 data1x => FIFO_D(111 DOWNTO 96),
+		 data2x => FIFO_D(95 DOWNTO 80),
+		 data3x => FIFO_D(79 DOWNTO 64),
+		 data4x => FIFO_D(63 DOWNTO 48),
+		 data5x => FIFO_D(47 DOWNTO 32),
+		 data6x => FIFO_D(31 DOWNTO 16),
+		 data7x => FIFO_D(15 DOWNTO 0),
+		 sel => CLUT_MUX_ADR(2 DOWNTO 0),
+		 result => SYNTHESIZED_WIRE_7);
+
+
+b2v_inst25 : lpm_mux2
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data0x => FIFO_D(127 DOWNTO 120),
+		 data10x => FIFO_D(47 DOWNTO 40),
+		 data11x => FIFO_D(39 DOWNTO 32),
+		 data12x => FIFO_D(31 DOWNTO 24),
+		 data13x => FIFO_D(23 DOWNTO 16),
+		 data14x => FIFO_D(15 DOWNTO 8),
+		 data15x => FIFO_D(7 DOWNTO 0),
+		 data1x => FIFO_D(119 DOWNTO 112),
+		 data2x => FIFO_D(111 DOWNTO 104),
+		 data3x => FIFO_D(103 DOWNTO 96),
+		 data4x => FIFO_D(95 DOWNTO 88),
+		 data5x => FIFO_D(87 DOWNTO 80),
+		 data6x => FIFO_D(79 DOWNTO 72),
+		 data7x => FIFO_D(71 DOWNTO 64),
+		 data8x => FIFO_D(63 DOWNTO 56),
+		 data9x => FIFO_D(55 DOWNTO 48),
+		 sel => CLUT_MUX_ADR,
+		 result => SYNTHESIZED_WIRE_12);
+
+
+b2v_inst26 : lpm_shiftreg4
+PORT MAP(clock => DDRCLK(0),
+		 shiftin => SR_FIFO_WRE,
+		 shiftout => FIFO_WRE);
+
+
+b2v_inst27 : lpm_latch0
+PORT MAP(gate => DDR_SYNC_66M,
+		 data => SYNTHESIZED_WIRE_15,
+		 q => VDR);
+
+
+
+CLUT_ADR(1) <= CLUT_ADR1A AND SYNTHESIZED_WIRE_16;
+
+
+b2v_inst3 : lpm_ff1
+PORT MAP(clock => DDRCLK(0),
+		 data => VDP_IN(63 DOWNTO 32),
+		 q => VDVZ(63 DOWNTO 32));
+
+
+CLUT_ADR(3) <= SYNTHESIZED_WIRE_61 AND CLUT_ADR3A;
+
+
+CLUT_ADR(5) <= CLUT_OFF(1) OR SYNTHESIZED_WIRE_18;
+
+
+SYNTHESIZED_WIRE_8 <= CLUT_ADR4A AND COLOR8;
+
+
+SYNTHESIZED_WIRE_18 <= CLUT_ADR5A AND COLOR8;
+
+
+SYNTHESIZED_WIRE_9 <= CLUT_ADR6A AND COLOR8;
+
+
+SYNTHESIZED_WIRE_46 <= CLUT_ADR7A AND COLOR8;
+
+
+b2v_inst36 : lpm_ff6
+PORT MAP(clock => DDRCLK(0),
+		 enable => BLITTER_DACK(0),
+		 data => VDVZ,
+		 q => BLITTER_DIN);
+
+
+VDOUT_OE <= DDR_WR OR SR_DDR_WR;
+
+
+
+VIDEO_TA <= BLITTER_TA OR VIDEO_MOD_TA OR VIDEO_DDR_TA;
+
+
+b2v_inst4 : lpm_ff1
+PORT MAP(clock => DDRCLK(0),
+		 data => VDVZ(63 DOWNTO 32),
+		 q => VDVZ(127 DOWNTO 96));
+
+
+b2v_inst40 : mux41_0
+PORT MAP(S0 => COLOR2,
+		 S1 => COLOR4,
+		 D0 => CLUT_ADR6A,
+		 INH => SYNTHESIZED_WIRE_19,
+		 D1 => CLUT_ADR7A,
+		 Q => SYNTHESIZED_WIRE_54);
+
+
+b2v_inst41 : mux41_1
+PORT MAP(S0 => COLOR2,
+		 S1 => COLOR4,
+		 D0 => CLUT_ADR5A,
+		 INH => SYNTHESIZED_WIRE_20,
+		 D1 => CLUT_ADR6A,
+		 Q => SYNTHESIZED_WIRE_53);
+
+
+b2v_inst42 : mux41_2
+PORT MAP(S0 => COLOR2,
+		 D2 => CLUT_ADR7A,
+		 S1 => COLOR4,
+		 D0 => CLUT_ADR4A,
+		 INH => SYNTHESIZED_WIRE_21,
+		 D1 => CLUT_ADR5A,
+		 Q => SYNTHESIZED_WIRE_52);
+
+
+b2v_inst43 : mux41_3
+PORT MAP(S0 => COLOR2,
+		 D2 => CLUT_ADR6A,
+		 S1 => COLOR4,
+		 D0 => CLUT_ADR3A,
+		 INH => SYNTHESIZED_WIRE_22,
+		 D1 => CLUT_ADR4A,
+		 Q => SYNTHESIZED_WIRE_51);
+
+
+b2v_inst44 : mux41_4
+PORT MAP(S0 => COLOR2,
+		 D2 => CLUT_ADR5A,
+		 S1 => COLOR4,
+		 D0 => CLUT_ADR2A,
+		 INH => SYNTHESIZED_WIRE_23,
+		 D1 => CLUT_ADR3A,
+		 Q => SYNTHESIZED_WIRE_50);
+
+
+b2v_inst45 : mux41_5
+PORT MAP(S0 => COLOR2,
+		 D2 => CLUT_ADR4A,
+		 S1 => COLOR4,
+		 D0 => CLUT_ADR1A,
+		 INH => SYNTHESIZED_WIRE_24,
+		 D1 => CLUT_ADR2A,
+		 Q => SYNTHESIZED_WIRE_49);
+
+
+b2v_inst46 : lpm_ff3
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data => SYNTHESIZED_WIRE_25,
+		 q => SYNTHESIZED_WIRE_43);
+
+
+b2v_inst47 : lpm_ff3
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data => CCF,
+		 q => SYNTHESIZED_WIRE_25);
+
+
+
+b2v_inst49 : lpm_ff3
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data => SYNTHESIZED_WIRE_26,
+		 q => SYNTHESIZED_WIRE_42);
+
+
+b2v_inst5 : altddio_out2
+PORT MAP(outclock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 datain_h => SYNTHESIZED_WIRE_62,
+		 datain_l => SYNTHESIZED_WIRE_62,
+		 dataout => SYNTHESIZED_WIRE_65);
+
+
+
+b2v_inst51 : lpm_bustri1
+PORT MAP(enabledt => ST_CLUT_RD,
+		 data => SYNTHESIZED_WIRE_29,
+		 tridata => FB_AD(26 DOWNTO 24));
+
+
+b2v_inst52 : lpm_ff3
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data => CCS,
+		 q => SYNTHESIZED_WIRE_26);
+
+
+b2v_inst53 : lpm_bustri_byt
+PORT MAP(enabledt => ACP_CLUT_RD,
+		 data => SYNTHESIZED_WIRE_30,
+		 tridata => FB_AD(7 DOWNTO 0));
+
+
+b2v_inst54 : lpm_constant0
+PORT MAP(		 result => CCS(20 DOWNTO 16));
+
+
+
+b2v_inst56 : lpm_bustri1
+PORT MAP(enabledt => ST_CLUT_RD,
+		 data => SYNTHESIZED_WIRE_31,
+		 tridata => FB_AD(22 DOWNTO 20));
+
+
+b2v_inst57 : lpm_bustri_byt
+PORT MAP(enabledt => ACP_CLUT_RD,
+		 data => SYNTHESIZED_WIRE_32,
+		 tridata => FB_AD(15 DOWNTO 8));
+
+
+b2v_inst58 : lpm_bustri_byt
+PORT MAP(enabledt => ACP_CLUT_RD,
+		 data => SYNTHESIZED_WIRE_33,
+		 tridata => FB_AD(23 DOWNTO 16));
+
+
+b2v_inst59 : lpm_constant0
+PORT MAP(		 result => CCS(12 DOWNTO 8));
+
+
+
+
+b2v_inst61 : lpm_bustri1
+PORT MAP(enabledt => ST_CLUT_RD,
+		 data => SYNTHESIZED_WIRE_34,
+		 tridata => FB_AD(18 DOWNTO 16));
+
+
+b2v_inst62 : lpm_muxdz
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 clken => FIFO_RDE,
+		 sel => INTER_ZEI,
+		 data0x => SYNTHESIZED_WIRE_63,
+		 data1x => SYNTHESIZED_WIRE_36,
+		 result => FIFO_D);
+
+
+b2v_inst63 : lpm_fifodz
+PORT MAP(wrreq => SYNTHESIZED_WIRE_60,
+		 rdreq => SYNTHESIZED_WIRE_38,
+		 clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 aclr => DOP_FIFO_CLR,
+		 data => SYNTHESIZED_WIRE_63,
+		 q => SYNTHESIZED_WIRE_36);
+
+
+b2v_inst64 : lpm_constant0
+PORT MAP(		 result => CCS(4 DOWNTO 0));
+
+
+SYNTHESIZED_WIRE_60 <= FIFO_RDE AND SYNTHESIZED_WIRE_40;
+
+
+b2v_inst66 : lpm_bustri3
+PORT MAP(enabledt => FALCON_CLUT_RDH,
+		 data => SYNTHESIZED_WIRE_41,
+		 tridata => FB_AD(31 DOWNTO 26));
+
+
+SYNTHESIZED_WIRE_38 <= FIFO_RDE AND INTER_ZEI;
+
+
+
+SYNTHESIZED_WIRE_40 <= NOT(INTER_ZEI);
+
+
+
+b2v_inst7 : lpm_mux6
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data0x => SYNTHESIZED_WIRE_42,
+		 data1x => SYNTHESIZED_WIRE_43,
+         data2x => (OTHERS => '0'),
+         data3x => (OTHERS => '0'),
+		 data4x => CCA,
+		 data5x => CC16,
+		 data6x => CC24(23 DOWNTO 0),
+		 data7x => BORDER_COLOR,
+		 sel => CCSEL,
+		 result => SYNTHESIZED_WIRE_62);
+
+
+b2v_inst70 : lpm_bustri3
+PORT MAP(enabledt => FALCON_CLUT_RDH,
+		 data => SYNTHESIZED_WIRE_44,
+		 tridata => FB_AD(23 DOWNTO 18));
+
+
+b2v_inst71 : lpm_ff6
+PORT MAP(clock => DDRCLK(0),
+		 enable => FIFO_WRE,
+		 data => VDVZ,
+		 q => VDMA);
+
+
+
+
+b2v_inst74 : lpm_bustri3
+PORT MAP(enabledt => FALCON_CLUT_RDL,
+		 data => SYNTHESIZED_WIRE_45,
+		 tridata => FB_AD(23 DOWNTO 18));
+
+
+
+
+b2v_inst77 : lpm_constant1
+PORT MAP(		 result => CCF(1 DOWNTO 0));
+
+
+
+CLUT_ADR(7) <= CLUT_OFF(3) OR SYNTHESIZED_WIRE_46;
+
+
+
+b2v_inst80 : lpm_constant1
+PORT MAP(		 result => CCF(9 DOWNTO 8));
+
+
+b2v_inst81 : lpm_mux4
+PORT MAP(sel => COLOR1,
+		 data0x => ZR_C8(7 DOWNTO 1),
+		 data1x => SYNTHESIZED_WIRE_47,
+		 result => ZR_C8B(7 DOWNTO 1));
+
+
+b2v_inst82 : lpm_constant3
+PORT MAP(		 result => SYNTHESIZED_WIRE_47);
+
+
+b2v_inst83 : lpm_constant1
+PORT MAP(		 result => CCF(17 DOWNTO 16));
+
+
+PROCESS(DDRCLK(0),DDR_WR)
+BEGIN
+if (DDR_WR = '1') THEN
+	VDQS(3) <= DDRCLK(0);
+ELSE
+	VDQS(3) <= 'Z';
+END IF;
+END PROCESS;
+
+
+PROCESS(DDRCLK(0),DDR_WR)
+BEGIN
+if (DDR_WR = '1') THEN
+	VDQS(2) <= DDRCLK(0);
+ELSE
+	VDQS(2) <= 'Z';
+END IF;
+END PROCESS;
+
+
+PROCESS(DDRCLK(0),DDR_WR)
+BEGIN
+if (DDR_WR = '1') THEN
+	VDQS(1) <= DDRCLK(0);
+ELSE
+	VDQS(1) <= 'Z';
+END IF;
+END PROCESS;
+
+
+PROCESS(DDRCLK(0),DDR_WR)
+BEGIN
+if (DDR_WR = '1') THEN
+	VDQS(0) <= DDRCLK(0);
+ELSE
+	VDQS(0) <= 'Z';
+END IF;
+END PROCESS;
+
+
+PROCESS(DDRCLK(3))
+BEGIN
+IF (RISING_EDGE(DDRCLK(3))) THEN
+	DDRWR_D_SEL(0) <= SR_DDRWR_D_SEL;
+END IF;
+END PROCESS;
+
+
+b2v_inst89 : lpm_shiftreg6
+PORT MAP(clock => DDRCLK(0),
+		 shiftin => SR_BLITTER_DACK,
+		 q => BLITTER_DACK);
+
+
+b2v_inst9 : lpm_ff1
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data => SYNTHESIZED_WIRE_48,
+		 q => CC24);
+
+
+PROCESS(DDRCLK(3))
+BEGIN
+IF (RISING_EDGE(DDRCLK(3))) THEN
+	DDR_WR <= SR_DDR_WR;
+END IF;
+END PROCESS;
+
+
+PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED)
+BEGIN
+IF (RISING_EDGE(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN
+	DFF_inst91 <= CLUT_ADR(0);
+END IF;
+END PROCESS;
+
+
+b2v_inst92 : lpm_shiftreg6
+PORT MAP(clock => DDRCLK(0),
+		 shiftin => SR_DDR_FB,
+		 q => DDR_FB);
+
+
+PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED)
+BEGIN
+IF (RISING_EDGE(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN
+	DFF_inst93 <= DFF_inst91;
+END IF;
+END PROCESS;
+
+
+b2v_inst94 : lpm_ff6
+PORT MAP(clock => DDRCLK(0),
+		 enable => FIFO_WRE,
+		 data => VDMA,
+		 q => VDMB);
+
+
+PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED)
+BEGIN
+IF (RISING_EDGE(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN
+	SYNTHESIZED_WIRE_64 <= FIFO_RDE;
+END IF;
+END PROCESS;
+
+
+
+b2v_inst97 : lpm_ff5
+PORT MAP(clock => DDRCLK(2),
+		 data => SR_VDMP,
+		 q => VDMP);
+
+
+b2v_sr0 : lpm_shiftreg0
+PORT MAP(load => SYNTHESIZED_WIRE_64,
+		 clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 shiftin => SYNTHESIZED_WIRE_49,
+		 data => FIFO_D(127 DOWNTO 112),
+		 shiftout => CLUT_ADR(0));
+
+
+b2v_sr1 : lpm_shiftreg0
+PORT MAP(load => SYNTHESIZED_WIRE_64,
+		 clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 shiftin => SYNTHESIZED_WIRE_50,
+		 data => FIFO_D(111 DOWNTO 96),
+		 shiftout => CLUT_ADR1A);
+
+
+b2v_sr2 : lpm_shiftreg0
+PORT MAP(load => SYNTHESIZED_WIRE_64,
+		 clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 shiftin => SYNTHESIZED_WIRE_51,
+		 data => FIFO_D(95 DOWNTO 80),
+		 shiftout => CLUT_ADR2A);
+
+
+b2v_sr3 : lpm_shiftreg0
+PORT MAP(load => SYNTHESIZED_WIRE_64,
+		 clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 shiftin => SYNTHESIZED_WIRE_52,
+		 data => FIFO_D(79 DOWNTO 64),
+		 shiftout => CLUT_ADR3A);
+
+
+b2v_sr4 : lpm_shiftreg0
+PORT MAP(load => SYNTHESIZED_WIRE_64,
+		 clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 shiftin => SYNTHESIZED_WIRE_53,
+		 data => FIFO_D(63 DOWNTO 48),
+		 shiftout => CLUT_ADR4A);
+
+
+b2v_sr5 : lpm_shiftreg0
+PORT MAP(load => SYNTHESIZED_WIRE_64,
+		 clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 shiftin => SYNTHESIZED_WIRE_54,
+		 data => FIFO_D(47 DOWNTO 32),
+		 shiftout => CLUT_ADR5A);
+
+
+b2v_sr6 : lpm_shiftreg0
+PORT MAP(load => SYNTHESIZED_WIRE_64,
+		 clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 shiftin => CLUT_ADR7A,
+		 data => FIFO_D(31 DOWNTO 16),
+		 shiftout => CLUT_ADR6A);
+
+
+b2v_sr7 : lpm_shiftreg0
+PORT MAP(load => SYNTHESIZED_WIRE_64,
+		 clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 shiftin => CLUT_ADR(0),
+		 data => FIFO_D(15 DOWNTO 0),
+		 shiftout => CLUT_ADR7A);
+
+
+b2v_ST_CLUT_BLUE : altdpram0
+PORT MAP(wren_a => ST_CLUT_WR(1),
+		 wren_b => SYNTHESIZED_WIRE_55,
+		 clock_a => MAIN_CLK,
+		 clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 address_a => FB_ADR(4 DOWNTO 1),
+		 address_b => CLUT_ADR(3 DOWNTO 0),
+		 data_a => FB_AD(18 DOWNTO 16),
+         data_b => (OTHERS => '0'),
+		 q_a => SYNTHESIZED_WIRE_34,
+		 q_b => CCS(7 DOWNTO 5));
+
+
+b2v_ST_CLUT_GREEN : altdpram0
+PORT MAP(wren_a => ST_CLUT_WR(1),
+		 wren_b => SYNTHESIZED_WIRE_56,
+		 clock_a => MAIN_CLK,
+		 clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 address_a => FB_ADR(4 DOWNTO 1),
+		 address_b => CLUT_ADR(3 DOWNTO 0),
+		 data_a => FB_AD(22 DOWNTO 20),
+         data_b => (OTHERS => '0'),
+		 q_a => SYNTHESIZED_WIRE_31,
+		 q_b => CCS(15 DOWNTO 13));
+
+
+b2v_ST_CLUT_RED : altdpram0
+PORT MAP(wren_a => ST_CLUT_WR(0),
+		 wren_b => SYNTHESIZED_WIRE_57,
+		 clock_a => MAIN_CLK,
+		 clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 address_a => FB_ADR(4 DOWNTO 1),
+		 address_b => CLUT_ADR(3 DOWNTO 0),
+		 data_a => FB_AD(26 DOWNTO 24),
+         data_b => (OTHERS => '0'),
+		 q_a => SYNTHESIZED_WIRE_29,
+		 q_b => CCS(23 DOWNTO 21));
+
+
+b2v_VIDEO_MOD_MUX_CLUTCTR : video_mod_mux_clutctr
+PORT MAP(nRSTO => nRSTO,
+		 MAIN_CLK => MAIN_CLK,
+		 nFB_CS1 => nFB_CS1,
+		 nFB_CS2 => nFB_CS2,
+		 nFB_CS3 => nFB_CS3,
+		 nFB_WR => nFB_WR,
+		 nFB_OE => nFB_OE,
+		 FB_SIZE0 => FB_SIZE0,
+		 FB_SIZE1 => FB_SIZE1,
+		 nFB_BURST => nFB_BURST,
+		 CLK33M => CLK33M,
+		 CLK25M => CLK25M,
+		 BLITTER_RUN => BLITTER_RUN,
+		 CLK_VIDEO => CLK_VIDEO,
+		 VR_BUSY => VR_BUSY,
+		 FB_AD => FB_AD,
+		 FB_ADR => FB_ADR,
+		 VR_D => VR_D,
+		 COLOR8 => COLOR8,
+		 ACP_CLUT_RD => ACP_CLUT_RD,
+		 COLOR1 => COLOR1,
+		 FALCON_CLUT_RDH => FALCON_CLUT_RDH,
+		 FALCON_CLUT_RDL => FALCON_CLUT_RDL,
+		 ST_CLUT_RD => ST_CLUT_RD,
+		 HSYNC => HSYNC,
+		 VSYNC => VSYNC,
+		 nBLANK => nBLANK,
+		 nSYNC => nSYNC,
+		 nPD_VGA => nPD_VGA,
+		 FIFO_RDE => FIFO_RDE,
+		 COLOR2 => COLOR2,
+		 COLOR4 => COLOR4,
+		 PIXEL_CLK => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 BLITTER_ON => BLITTER_ON,
+		 VIDEO_MOD_TA => VIDEO_MOD_TA,
+		 INTER_ZEI => INTER_ZEI,
+		 DOP_FIFO_CLR => DOP_FIFO_CLR,
+		 VIDEO_RECONFIG => VIDEO_RECONFIG,
+		 VR_WR => VR_WR,
+		 VR_RD => VR_RD,
+		 CLR_FIFO => CLR_FIFO,
+		 ACP_CLUT_WR => ACP_CLUT_WR,
+		 BORDER_COLOR => BORDER_COLOR,
+		 CCSEL => CCSEL,
+		 CLUT_MUX_ADR => CLUT_MUX_ADR,
+		 CLUT_OFF => CLUT_OFF,
+		 FALCON_CLUT_WR => FALCON_CLUT_WR,
+		 ST_CLUT_WR => ST_CLUT_WR,
+		 VIDEO_RAM_CTR => VIDEO_RAM_CTR);
+
+PIXEL_CLK <= PIXEL_CLK_ALTERA_SYNTHESIZED;
+
+END bdf_type;
\ No newline at end of file
diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf
index 94b33d9..41e0e96 100644
--- a/FPGA_Quartus_13.1/firebee1.qsf
+++ b/FPGA_Quartus_13.1/firebee1.qsf
@@ -670,11 +670,18 @@ set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
 set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
 set_global_assignment -name SAVE_DISK_SPACE OFF
 set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name VHDL_FILE Video/mux41.vhd
+set_global_assignment -name VHDL_FILE Video/mux41_5.vhd
+set_global_assignment -name VHDL_FILE Video/mux41_4.vhd
+set_global_assignment -name VHDL_FILE Video/mux41_3.vhd
+set_global_assignment -name VHDL_FILE Video/mux41_2.vhd
+set_global_assignment -name VHDL_FILE Video/mux41_1.vhd
+set_global_assignment -name VHDL_FILE Video/mux41_0.vhd
 set_global_assignment -name VHDL_FILE firebee1.vhd
 set_global_assignment -name SDC_FILE firebee1.sdc
 set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf
 set_global_assignment -name AHDL_FILE altpll4.tdf
-set_global_assignment -name BDF_FILE Video/video.bdf
+set_global_assignment -name VHDL_FILE Video/video.vhd
 set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd
 set_global_assignment -name AHDL_FILE Video/DDR_CTR.tdf
 set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp