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improved timing, added timing constraints, got rid of CLK_33M

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Design compiles and runs, but still has issues with different screen resolutions and video clocks
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Markus Fröschle
2015-09-23 09:49:05 +00:00
parent ad05ca8523
commit 7e2181fbc9
19 changed files with 1631 additions and 1519 deletions
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FPGA_Quartus_13.1/altpll4.inc
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@@ -1,4 +1,4 @@
--Copyright (C) 1991-2010 Altera Corporation
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing