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fix timing

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This commit is contained in:
Markus Fröschle
2016-01-16 21:38:17 +00:00
parent 0fe61bedef
commit 7bf4d912a0
7 changed files with 232 additions and 169 deletions
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2
FPGA_Quartus_13.1/Video/video.vhd
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@@ -723,7 +723,7 @@ ARCHITECTURE rtl OF video IS
SIGNAL FIFO_RDE : std_logic;
SIGNAL FIFO_WRE : std_logic;
SIGNAL INTER_ZEI : std_logic;
SIGNAL nFB_BURST : std_logic;
SIGNAL nFB_BURST : std_logic := '0';
SIGNAL pixel_clk_i : std_logic;
SIGNAL SR_BLITTER_DACK : std_logic;
SIGNAL SR_DDR_FB : std_logic;

20
FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
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@@ -187,18 +187,18 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS
SIGNAL VERZ0 : std_logic_vector(9 DOWNTO 0);
SIGNAL VERZ0_d : std_logic_vector(9 DOWNTO 0);
SIGNAL VERZ0_q : std_logic_vector(9 DOWNTO 0);
SIGNAL RAND : std_logic_vector(6 DOWNTO 0);
SIGNAL RAND : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL RAND_d : std_logic_vector(6 DOWNTO 0);
SIGNAL RAND_q : std_logic_vector(6 DOWNTO 0);
SIGNAL CCSEL_d : std_logic_vector(2 DOWNTO 0);
SIGNAL CCSEL_q : std_logic_vector(2 DOWNTO 0);
SIGNAL ATARI_HH : std_logic_vector(31 DOWNTO 0);
SIGNAL ATARI_HH : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ATARI_HH_d : std_logic_vector(31 DOWNTO 0);
SIGNAL ATARI_HH_q : std_logic_vector(31 DOWNTO 0);
SIGNAL ATARI_VH : std_logic_vector(31 DOWNTO 0);
SIGNAL ATARI_VH_d : std_logic_vector(31 DOWNTO 0);
SIGNAL ATARI_VH_q : std_logic_vector(31 DOWNTO 0);
SIGNAL ATARI_HL : std_logic_vector(31 DOWNTO 0);
SIGNAL ATARI_HL : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL ATARI_HL_d : std_logic_vector(31 DOWNTO 0);
SIGNAL ATARI_HL_q : std_logic_vector(31 DOWNTO 0);
SIGNAL ATARI_VL : std_logic_vector(31 DOWNTO 0);
@@ -212,10 +212,10 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS
SIGNAL H_TOTAL : std_logic_vector(11 DOWNTO 0);
SIGNAL HDIS_LEN : std_logic_vector(11 DOWNTO 0);
SIGNAL MULF : std_logic_vector(5 DOWNTO 0);
SIGNAL HHT : std_logic_vector(11 DOWNTO 0);
SIGNAL HHT : std_logic_vector(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL HHT_d : std_logic_vector(11 DOWNTO 0);
SIGNAL HHT_q : std_logic_vector(11 DOWNTO 0);
SIGNAL HBE : std_logic_vector(11 DOWNTO 0);
SIGNAL HBE : std_logic_vector(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL HBE_d : std_logic_vector(11 DOWNTO 0);
SIGNAL HBE_q : std_logic_vector(11 DOWNTO 0);
SIGNAL HDB : std_logic_vector(11 DOWNTO 0);
@@ -227,7 +227,7 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS
SIGNAL HBB : std_logic_vector(11 DOWNTO 0);
SIGNAL HBB_d : std_logic_vector(11 DOWNTO 0);
SIGNAL HBB_q : std_logic_vector(11 DOWNTO 0);
SIGNAL HSS : std_logic_vector(11 DOWNTO 0);
SIGNAL HSS : std_logic_vector(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL HSS_d : std_logic_vector(11 DOWNTO 0);
SIGNAL HSS_q : std_logic_vector(11 DOWNTO 0);
SIGNAL RAND_OBEN : std_logic_vector(10 DOWNTO 0);
@@ -258,7 +258,7 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS
SIGNAL VCO_d : std_logic_vector(8 DOWNTO 0);
SIGNAL VCO_ena : std_logic_vector(8 DOWNTO 0);
SIGNAL VCO_q : std_logic_vector(8 DOWNTO 0);
SIGNAL VCNTRL : std_logic_vector(3 DOWNTO 0);
SIGNAL VCNTRL : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL VCNTRL_d : std_logic_vector(3 DOWNTO 0);
SIGNAL VCNTRL_q : std_logic_vector(3 DOWNTO 0);
SIGNAL u0_data : std_logic_vector(15 DOWNTO 0);
@@ -1825,7 +1825,7 @@ BEGIN
RAND_RECHTS <= (HBB_q and sizeIt(ACP_VIDEO_ON,12)) or
((std_logic_vector(unsigned(HDIS_END) + 1)) and sizeIt(not ACP_VIDEO_ON, 12));
hs_start <= hss WHEN acp_video_on ELSE
hs_start <= hss_q WHEN acp_video_on ELSE
atari_hl(11 DOWNTO 0) WHEN not(acp_video_on) and atari_sync and vcntrl(2) ELSE
atari_hh(11 DOWNTO 0) WHEN not(acp_video_on) and atari_sync and not vcntrl(2) ELSE
std_logic_vector(resize(unsigned(hht) + 1 + unsigned(hss) * unsigned(mulf(5 DOWNTO 1)), 12)) WHEN not acp_video_on and not atari_sync;
@@ -1835,7 +1835,7 @@ BEGIN
-- # ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2
-- # (HHT[] + 1 + HSS[]) * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
--
h_total <= hht WHEN acp_video_on ELSE
h_total <= hht_q WHEN acp_video_on ELSE
atari_hl(27 DOWNTO 16) WHEN not acp_video_on and atari_sync and vcntrl(2) ELSE
atari_hh(27 DOWNTO 16) WHEN not acp_video_on and atari_sync and not vcntrl(2) ELSE
std_logic_vector(resize((unsigned(hht) + 2) * unsigned(mulf), 12)) WHEN not acp_video_on and not atari_sync;
@@ -1848,6 +1848,7 @@ BEGIN
sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or
(std_logic_vector'('0' & VBE_q(10 DOWNTO 1)) and sizeIt(not
ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11));
VDIS_START <= (VDB_q and sizeIt(ACP_VIDEO_ON,11)) or
("00000100000" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or
((std_logic_vector(unsigned(std_logic_vector('0' & VDB_q(10 DOWNTO 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11));
@@ -1978,6 +1979,7 @@ BEGIN
-- nBLANK = VERZ[0][8];
nblank_d <= verz0_q(8);
-- nBLANK_d <= DISP_ON_q;
HSYNC_clk <= PIXEL_CLK;

20
FPGA_Quartus_13.1/firebee1.qsf
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@@ -365,12 +365,12 @@ set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK
@@ -664,7 +664,7 @@ set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
@@ -672,14 +672,18 @@ set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF
set_global_assignment -name SDC_FILE firebee_groups.sdc
set_global_assignment -name VHDL_FILE Video/video.vhd
set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd
set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd
set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp
set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd
set_global_assignment -name SOURCE_FILE altpll4.cmp
set_global_assignment -name SDC_FILE firebee1.sdc
set_global_assignment -name VHDL_FILE firebee1.vhd
set_global_assignment -name VHDL_FILE Video/video.vhd
set_global_assignment -name VHDL_FILE Video/mux41.vhd
set_global_assignment -name VHDL_FILE Video/mux41_5.vhd
set_global_assignment -name VHDL_FILE Video/mux41_4.vhd
@@ -854,4 +858,6 @@ set_global_assignment -name QIP_FILE lpm_mux0.qip
set_global_assignment -name QIP_FILE lpm_shiftreg0.qip
set_global_assignment -name QIP_FILE lpm_counter1.qip
set_global_assignment -name QIP_FILE altiobuf_bidir0.qip
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
FPGA_Quartus_13.1/firebee1.qws
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Binary file not shown.

12
FPGA_Quartus_13.1/firebee1.sdc
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@@ -109,8 +109,8 @@ derive_pll_clocks
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 2.00
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 2.00
#set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 2.00
#set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 2.00
derive_clock_uncertainty
@@ -118,8 +118,8 @@ derive_clock_uncertainty
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_inputs]
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_inputs]
# set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_inputs]
# set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_inputs]
#set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}]
#set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE}
@@ -130,8 +130,8 @@ set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_inputs
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_outputs]
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_outputs]
# set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_outputs]
# set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_outputs]
#set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}]
#set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_TA}

49
FPGA_Quartus_13.1/firebee1.vhd
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@@ -242,6 +242,53 @@ ARCHITECTURE rtl OF firebee1 IS
);
END COMPONENT altpll4;
COMPONENT Video
PORT
(
FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
MAIN_CLK : IN STD_LOGIC;
nFB_CS1 : IN STD_LOGIC;
nFB_CS2 : IN STD_LOGIC;
nFB_CS3 : IN STD_LOGIC;
nFB_WR : IN STD_LOGIC;
FB_SIZE0 : IN STD_LOGIC;
FB_SIZE1 : IN STD_LOGIC;
nRSTO : IN STD_LOGIC;
nFB_OE : IN STD_LOGIC;
FB_ALE : IN STD_LOGIC;
DDRCLK : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DDR_SYNC_66M : IN STD_LOGIC;
CLK33M : IN STD_LOGIC;
CLK25M : IN STD_LOGIC;
CLK_VIDEO : IN STD_LOGIC;
VR_D : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
VR_BUSY : IN STD_LOGIC;
VG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
VR : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
nBLANK : OUT STD_LOGIC;
VA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
nVWE : OUT STD_LOGIC;
nVCAS : OUT STD_LOGIC;
nVRAS : OUT STD_LOGIC;
nVCS : OUT STD_LOGIC;
VDM : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
nPD_VGA : OUT STD_LOGIC;
VCKE : OUT STD_LOGIC;
VSYNC : OUT STD_LOGIC;
HSYNC : OUT STD_LOGIC;
nSYNC : OUT STD_LOGIC;
VIDEO_TA : OUT STD_LOGIC;
PIXEL_CLK : OUT STD_LOGIC;
BA : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
VIDEO_RECONFIG : OUT STD_LOGIC;
VR_WR : OUT STD_LOGIC;
VR_RD : OUT STD_LOGIC;
VDQS : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
VD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
BEGIN
nDREQ1 <= nDACK1;
@@ -472,7 +519,7 @@ BEGIN
);
i_video : work.video
i_video : video
PORT MAP
(
MAIN_CLK => MAIN_CLK,

30
FPGA_Quartus_13.1/firebee_groups.sdc
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@@ -91,6 +91,9 @@ create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_por
derive_pll_clocks
create_generated_clock -divide_by 2 -source MAIN_CLK i_video|i_video_mod_mux_clutctr|CLK17M_q
create_generated_clock -divide_by 2 -source i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[2] i_video|i_video_mod_mux_clutctr|CLK13M_q
# PIXEL_CLK is either
# CLK13M, CLK17M, CLK25M, CLK33M or CLK_VIDEO
# where CLK13M is half of CLK25M,
@@ -109,8 +112,8 @@ derive_pll_clocks
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 2.0
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 2.0
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.5
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.5
derive_clock_uncertainty
@@ -147,24 +150,29 @@ set_clock_groups -asynchronous -group [get_clocks {MAIN_CLK}] \
-group [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] \
-group [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] \
-group [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] \
-group [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
-group [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] \
-group [get_clocks {video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|CLK17M_q}] \
-group [get_clocks {video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|CLK13M_q}]
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2
#set_multicycle_path -start -from video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|CLK17M_q -to i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0] 2
#set_multicycle_path -start -from video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|CLK13M_q -to i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0] 2
#set_multicycle_path -end -from video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|CLK13M_q -to MAIN_CLK 2
#set_multicycle_path -start -from MAIN_CLK -to i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0] 2
#set_multicycle_path -start -from MAIN_CLK -to i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1] 2
#set_multicycle_path -start -from MAIN_CLK -to i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0] 2
# set_multicycle_path -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2
#**************************************************************
# Set Maximum Delay