diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd index f15df82..c209bd1 100644 --- a/FPGA_Quartus_13.1/Video/video.vhd +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -723,8 +723,8 @@ ARCHITECTURE rtl OF video IS SIGNAL FIFO_RDE : std_logic; SIGNAL FIFO_WRE : std_logic; SIGNAL INTER_ZEI : std_logic; - SIGNAL nFB_BURST : std_logic; - SIGNAL pixel_clk_i : std_logic; + SIGNAL nFB_BURST : std_logic := '0'; + SIGNAL pixel_clk_i : std_logic; SIGNAL SR_BLITTER_DACK : std_logic; SIGNAL SR_DDR_FB : std_logic; SIGNAL SR_DDR_WR : std_logic; diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index 50ec8f9..0ea49e4 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -187,18 +187,18 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS SIGNAL VERZ0 : std_logic_vector(9 DOWNTO 0); SIGNAL VERZ0_d : std_logic_vector(9 DOWNTO 0); SIGNAL VERZ0_q : std_logic_vector(9 DOWNTO 0); - SIGNAL RAND : std_logic_vector(6 DOWNTO 0); + SIGNAL RAND : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0'); SIGNAL RAND_d : std_logic_vector(6 DOWNTO 0); SIGNAL RAND_q : std_logic_vector(6 DOWNTO 0); SIGNAL CCSEL_d : std_logic_vector(2 DOWNTO 0); SIGNAL CCSEL_q : std_logic_vector(2 DOWNTO 0); - SIGNAL ATARI_HH : std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_HH : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL ATARI_HH_d : std_logic_vector(31 DOWNTO 0); SIGNAL ATARI_HH_q : std_logic_vector(31 DOWNTO 0); SIGNAL ATARI_VH : std_logic_vector(31 DOWNTO 0); SIGNAL ATARI_VH_d : std_logic_vector(31 DOWNTO 0); SIGNAL ATARI_VH_q : std_logic_vector(31 DOWNTO 0); - SIGNAL ATARI_HL : std_logic_vector(31 DOWNTO 0); + SIGNAL ATARI_HL : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL ATARI_HL_d : std_logic_vector(31 DOWNTO 0); SIGNAL ATARI_HL_q : std_logic_vector(31 DOWNTO 0); SIGNAL ATARI_VL : std_logic_vector(31 DOWNTO 0); @@ -212,10 +212,10 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS SIGNAL H_TOTAL : std_logic_vector(11 DOWNTO 0); SIGNAL HDIS_LEN : std_logic_vector(11 DOWNTO 0); SIGNAL MULF : std_logic_vector(5 DOWNTO 0); - SIGNAL HHT : std_logic_vector(11 DOWNTO 0); + SIGNAL HHT : std_logic_vector(11 DOWNTO 0) := (OTHERS => '0'); SIGNAL HHT_d : std_logic_vector(11 DOWNTO 0); SIGNAL HHT_q : std_logic_vector(11 DOWNTO 0); - SIGNAL HBE : std_logic_vector(11 DOWNTO 0); + SIGNAL HBE : std_logic_vector(11 DOWNTO 0) := (OTHERS => '0'); SIGNAL HBE_d : std_logic_vector(11 DOWNTO 0); SIGNAL HBE_q : std_logic_vector(11 DOWNTO 0); SIGNAL HDB : std_logic_vector(11 DOWNTO 0); @@ -227,7 +227,7 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS SIGNAL HBB : std_logic_vector(11 DOWNTO 0); SIGNAL HBB_d : std_logic_vector(11 DOWNTO 0); SIGNAL HBB_q : std_logic_vector(11 DOWNTO 0); - SIGNAL HSS : std_logic_vector(11 DOWNTO 0); + SIGNAL HSS : std_logic_vector(11 DOWNTO 0) := (OTHERS => '0'); SIGNAL HSS_d : std_logic_vector(11 DOWNTO 0); SIGNAL HSS_q : std_logic_vector(11 DOWNTO 0); SIGNAL RAND_OBEN : std_logic_vector(10 DOWNTO 0); @@ -258,7 +258,7 @@ ARCHITECTURE rtl OF video_mod_mux_clutctr IS SIGNAL VCO_d : std_logic_vector(8 DOWNTO 0); SIGNAL VCO_ena : std_logic_vector(8 DOWNTO 0); SIGNAL VCO_q : std_logic_vector(8 DOWNTO 0); - SIGNAL VCNTRL : std_logic_vector(3 DOWNTO 0); + SIGNAL VCNTRL : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0'); SIGNAL VCNTRL_d : std_logic_vector(3 DOWNTO 0); SIGNAL VCNTRL_q : std_logic_vector(3 DOWNTO 0); SIGNAL u0_data : std_logic_vector(15 DOWNTO 0); @@ -1825,17 +1825,17 @@ BEGIN RAND_RECHTS <= (HBB_q and sizeIt(ACP_VIDEO_ON,12)) or ((std_logic_vector(unsigned(HDIS_END) + 1)) and sizeIt(not ACP_VIDEO_ON, 12)); - hs_start <= hss WHEN acp_video_on ELSE - atari_hl(11 DOWNTO 0) WHEN not(acp_video_on) and atari_sync and vcntrl(2) ELSE - atari_hh(11 DOWNTO 0) WHEN not(acp_video_on) and atari_sync and not vcntrl(2) ELSE - std_logic_vector(resize(unsigned(hht) + 1 + unsigned(hss) * unsigned(mulf(5 DOWNTO 1)), 12)) WHEN not acp_video_on and not atari_sync; + hs_start <= hss_q WHEN acp_video_on ELSE + atari_hl(11 DOWNTO 0) WHEN not(acp_video_on) and atari_sync and vcntrl(2) ELSE + atari_hh(11 DOWNTO 0) WHEN not(acp_video_on) and atari_sync and not vcntrl(2) ELSE + std_logic_vector(resize(unsigned(hht) + 1 + unsigned(hss) * unsigned(mulf(5 DOWNTO 1)), 12)) WHEN not acp_video_on and not atari_sync; -- HS_START[] = HSS[] & ACP_VIDEO_ON -- # ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 -- # ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 -- # (HHT[] + 1 + HSS[]) * (0, MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- -- - h_total <= hht WHEN acp_video_on ELSE + h_total <= hht_q WHEN acp_video_on ELSE atari_hl(27 DOWNTO 16) WHEN not acp_video_on and atari_sync and vcntrl(2) ELSE atari_hh(27 DOWNTO 16) WHEN not acp_video_on and atari_sync and not vcntrl(2) ELSE std_logic_vector(resize((unsigned(hht) + 2) * unsigned(mulf), 12)) WHEN not acp_video_on and not atari_sync; @@ -1844,158 +1844,160 @@ BEGIN -- # ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VCNTRL2 -- # ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VCNTRL2 -- # (HHT[] + 2) * (0, MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- - RAND_OBEN <= (VBE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00000011111" and + RAND_OBEN <= (VBE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00000011111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or (std_logic_vector'('0' & VBE_q(10 DOWNTO 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - VDIS_START <= (VDB_q and sizeIt(ACP_VIDEO_ON,11)) or + + VDIS_START <= (VDB_q and sizeIt(ACP_VIDEO_ON,11)) or ("00000100000" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or ((std_logic_vector(unsigned(std_logic_vector('0' & VDB_q(10 DOWNTO 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - VDIS_END <= (VDE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00110101111" and + VDIS_END <= (VDE_q and sizeIt(ACP_VIDEO_ON,11)) or ("00110101111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(ST_VIDEO,11)) or ("00111111111" and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not ST_VIDEO,11)) or (std_logic_vector'('0' & VDE_q(10 DOWNTO 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - RAND_UNTEN <= (VBB_q and sizeIt(ACP_VIDEO_ON,11)) or + RAND_UNTEN <= (VBB_q and sizeIt(ACP_VIDEO_ON,11)) or ((std_logic_vector(unsigned(VDIS_END) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11)) or ((std_logic_vector(unsigned(std_logic_vector('0' & VBB_q(10 DOWNTO 1))) + 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - VS_START <= (VSS_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(10 DOWNTO 0) + VS_START <= (VSS_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(10 DOWNTO 0) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(VCNTRL_q(2),11)) or (ATARI_VH_q(10 DOWNTO 0) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not VCNTRL_q(2),11)) or (std_logic_vector'('0' & VSS_q(10 DOWNTO 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); - V_TOTAL <= (VFT_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(26 DOWNTO 16) + V_TOTAL <= (VFT_q and sizeIt(ACP_VIDEO_ON,11)) or (ATARI_VL_q(26 DOWNTO 16) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(VCNTRL_q(2),11)) or (ATARI_VH_q(26 DOWNTO 16) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(ATARI_SYNC,11) and sizeIt(not VCNTRL_q(2),11)) or (std_logic_vector'('0' & VFT_q(10 DOWNTO 1)) and sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11)); --- ZÄHLER - LAST_clk <= PIXEL_CLK; - LAST_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(H_TOTAL) - 2))); - VHCNT0_clk_ctrl <= PIXEL_CLK; - VHCNT_d <= (std_logic_vector(unsigned(VHCNT_q) + 1)) and sizeIt(not LAST_q,12); - VVCNT0_clk_ctrl <= PIXEL_CLK; - VVCNT0_ena_ctrl <= LAST_q; - VVCNT_d <= (std_logic_vector(unsigned(VVCNT_q) + 1)) and sizeIt(to_std_logic(VVCNT_q /= (std_logic_vector(unsigned(V_TOTAL) - 1))), 11); + -- ZÄHLER + LAST_clk <= PIXEL_CLK; + LAST_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(H_TOTAL) - 2))); + VHCNT0_clk_ctrl <= PIXEL_CLK; + VHCNT_d <= (std_logic_vector(unsigned(VHCNT_q) + 1)) and sizeIt(not LAST_q,12); + VVCNT0_clk_ctrl <= PIXEL_CLK; + VVCNT0_ena_ctrl <= LAST_q; + VVCNT_d <= (std_logic_vector(unsigned(VVCNT_q) + 1)) and sizeIt(to_std_logic(VVCNT_q /= (std_logic_vector(unsigned(V_TOTAL) - 1))), 11); --- DISPLAY ON OFF - DPO_ZL_clk <= PIXEL_CLK; + -- DISPLAY ON OFF + DPO_ZL_clk <= PIXEL_CLK; --- 1 ZEILE DAVOR ON OFF - DPO_ZL_d <= to_std_logic((unsigned(VVCNT_q) > unsigned(std_logic_vector(unsigned(RAND_OBEN) - 1))) and (unsigned(VVCNT_q) < unsigned(std_logic_vector(unsigned(RAND_UNTEN) - 1)))); + -- 1 ZEILE DAVOR ON OFF + DPO_ZL_d <= to_std_logic((unsigned(VVCNT_q) > unsigned(std_logic_vector(unsigned(RAND_OBEN) - 1))) and (unsigned(VVCNT_q) < unsigned(std_logic_vector(unsigned(RAND_UNTEN) - 1)))); --- AM ZEILENENDE ÜBERNEHMEN - DPO_ZL_ena <= LAST_q; - DPO_ON_clk <= PIXEL_CLK; + -- AM ZEILENENDE ÜBERNEHMEN + DPO_ZL_ena <= LAST_q; + DPO_ON_clk <= PIXEL_CLK; --- BESSER EINZELN WEGEN TIMING - DPO_ON_d <= to_std_logic(VHCNT_q = RAND_LINKS); - DPO_OFF_clk <= PIXEL_CLK; - DPO_OFF_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(RAND_RECHTS) - 1))); - DISP_ON_clk <= PIXEL_CLK; - DISP_ON_d <= (DISP_ON_q and (not DPO_OFF_q)) or (DPO_ON_q and DPO_ZL_q); + -- BESSER EINZELN WEGEN TIMING + DPO_ON_d <= to_std_logic(VHCNT_q = RAND_LINKS); + DPO_OFF_clk <= PIXEL_CLK; + DPO_OFF_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(RAND_RECHTS) - 1))); + DISP_ON_clk <= PIXEL_CLK; + DISP_ON_d <= (DISP_ON_q and (not DPO_OFF_q)) or (DPO_ON_q and DPO_ZL_q); --- DATENTRANSFER ON OFF - VCO_ON_clk <= PIXEL_CLK; + -- DATENTRANSFER ON OFF + VCO_ON_clk <= PIXEL_CLK; --- BESSER EINZELN WEGEN TIMING - VCO_ON_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HDIS_START) - 1))); - VCO_OFF_clk <= PIXEL_CLK; - VCO_OFF_d <= to_std_logic(VHCNT_q = HDIS_END); - VCO_ZL_clk <= PIXEL_CLK; + -- BESSER EINZELN WEGEN TIMING + VCO_ON_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HDIS_START) - 1))); + VCO_OFF_clk <= PIXEL_CLK; + VCO_OFF_d <= to_std_logic(VHCNT_q = HDIS_END); + VCO_ZL_clk <= PIXEL_CLK; --- AM ZEILENENDE ÜBERNEHMEN - VCO_ZL_ena <= LAST_q; + -- AM ZEILENENDE ÜBERNEHMEN + VCO_ZL_ena <= LAST_q; --- 1 ZEILE DAVOR ON OFF - VCO_ZL_d <= to_std_logic((unsigned(VVCNT_q) >= unsigned(std_logic_vector(unsigned(VDIS_START) - 1))) and (unsigned(VVCNT_q) < unsigned(VDIS_END))); - VDTRON_clk <= PIXEL_CLK; - VDTRON_d <= (VDTRON_q and (not VCO_OFF_q)) or (VCO_ON_q and VCO_ZL_q); + -- 1 ZEILE DAVOR ON OFF + VCO_ZL_d <= to_std_logic((unsigned(VVCNT_q) >= unsigned(std_logic_vector(unsigned(VDIS_START) - 1))) and (unsigned(VVCNT_q) < unsigned(VDIS_END))); + VDTRON_clk <= PIXEL_CLK; + VDTRON_d <= (VDTRON_q and (not VCO_OFF_q)) or (VCO_ON_q and VCO_ZL_q); --- VERZÖGERUNG UND SYNC - HSYNC_START_clk <= PIXEL_CLK; - HSYNC_START_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HS_START) - 3))); - HSYNC_I0_clk_ctrl <= PIXEL_CLK; - HSYNC_I_d <= (HSY_LEN_q and sizeIt(HSYNC_START_q,8)) or + -- VERZÖGERUNG UND SYNC + HSYNC_START_clk <= PIXEL_CLK; + HSYNC_START_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HS_START) - 3))); + HSYNC_I0_clk_ctrl <= PIXEL_CLK; + HSYNC_I_d <= (HSY_LEN_q and sizeIt(HSYNC_START_q,8)) or ((std_logic_vector(unsigned(HSYNC_I_q) - 1)) and sizeIt(not HSYNC_START_q,8) and sizeIt(to_std_logic(HSYNC_I_q /= "00000000"),8)); - VSYNC_START_clk <= PIXEL_CLK; - VSYNC_START_ena <= LAST_q; + VSYNC_START_clk <= PIXEL_CLK; + VSYNC_START_ena <= LAST_q; --- start am ende der Zeile vor dem vsync - VSYNC_START_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(VS_START) - 3))); - VSYNC_I0_clk_ctrl <= PIXEL_CLK; + -- start am ende der Zeile vor dem vsync + VSYNC_START_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(VS_START) - 3))); + VSYNC_I0_clk_ctrl <= PIXEL_CLK; --- start am ende der Zeile vor dem vsync - VSYNC_I0_ena_ctrl <= LAST_q; + -- start am ende der Zeile vor dem vsync + VSYNC_I0_ena_ctrl <= LAST_q; --- 3 zeilen vsync length --- runterzählen bis 0 - VSYNC_I_d <= ("011" and sizeIt(VSYNC_START_q,3)) or + -- 3 zeilen vsync length + -- runterzählen bis 0 + VSYNC_I_d <= ("011" and sizeIt(VSYNC_START_q,3)) or ((std_logic_vector(unsigned(VSYNC_I_q) - 1)) and sizeIt(not VSYNC_START_q,3) and sizeIt(to_std_logic(VSYNC_I_q /= "000"),3)); - VERZ2_0_clk_ctrl <= PIXEL_CLK; - VERZ1_0_clk_ctrl <= PIXEL_CLK; - VERZ0_0_clk_ctrl <= PIXEL_CLK; + VERZ2_0_clk_ctrl <= PIXEL_CLK; + VERZ1_0_clk_ctrl <= PIXEL_CLK; + VERZ0_0_clk_ctrl <= PIXEL_CLK; - (VERZ2_d(1), VERZ1_d(1), VERZ0_d(1)) <= std_logic_vector'(VERZ2_q(0) & + (VERZ2_d(1), VERZ1_d(1), VERZ0_d(1)) <= std_logic_vector'(VERZ2_q(0) & VERZ1_q(0) & VERZ0_q(0)); - (VERZ2_d(2), VERZ1_d(2), VERZ0_d(2)) <= std_logic_vector'(VERZ2_q(1) & + (VERZ2_d(2), VERZ1_d(2), VERZ0_d(2)) <= std_logic_vector'(VERZ2_q(1) & VERZ1_q(1) & VERZ0_q(1)); - (VERZ2_d(3), VERZ1_d(3), VERZ0_d(3)) <= std_logic_vector'(VERZ2_q(2) & + (VERZ2_d(3), VERZ1_d(3), VERZ0_d(3)) <= std_logic_vector'(VERZ2_q(2) & VERZ1_q(2) & VERZ0_q(2)); - (VERZ2_d(4), VERZ1_d(4), VERZ0_d(4)) <= std_logic_vector'(VERZ2_q(3) & + (VERZ2_d(4), VERZ1_d(4), VERZ0_d(4)) <= std_logic_vector'(VERZ2_q(3) & VERZ1_q(3) & VERZ0_q(3)); - (VERZ2_d(5), VERZ1_d(5), VERZ0_d(5)) <= std_logic_vector'(VERZ2_q(4) & + (VERZ2_d(5), VERZ1_d(5), VERZ0_d(5)) <= std_logic_vector'(VERZ2_q(4) & VERZ1_q(4) & VERZ0_q(4)); - (VERZ2_d(6), VERZ1_d(6), VERZ0_d(6)) <= std_logic_vector'(VERZ2_q(5) & + (VERZ2_d(6), VERZ1_d(6), VERZ0_d(6)) <= std_logic_vector'(VERZ2_q(5) & VERZ1_q(5) & VERZ0_q(5)); - (VERZ2_d(7), VERZ1_d(7), VERZ0_d(7)) <= std_logic_vector'(VERZ2_q(6) & + (VERZ2_d(7), VERZ1_d(7), VERZ0_d(7)) <= std_logic_vector'(VERZ2_q(6) & VERZ1_q(6) & VERZ0_q(6)); - (VERZ2_d(8), VERZ1_d(8), VERZ0_d(8)) <= std_logic_vector'(VERZ2_q(7) & + (VERZ2_d(8), VERZ1_d(8), VERZ0_d(8)) <= std_logic_vector'(VERZ2_q(7) & VERZ1_q(7) & VERZ0_q(7)); - (VERZ2_d(9), VERZ1_d(9), VERZ0_d(9)) <= std_logic_vector'(VERZ2_q(8) & + (VERZ2_d(9), VERZ1_d(9), VERZ0_d(9)) <= std_logic_vector'(VERZ2_q(8) & VERZ1_q(8) & VERZ0_q(8)); - VERZ0_d(0) <= DISP_ON_q; + VERZ0_d(0) <= DISP_ON_q; --- VERZ[1][0] = HSYNC_I[] != 0; --- NUR MÖGLICH WENN BEIDE - VERZ1_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') + -- VERZ[1][0] = HSYNC_I[] != 0; + -- NUR MÖGLICH WENN BEIDE + VERZ1_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') and HSYNC_I_q /= "00000000")) or (to_std_logic((ACP_VCTR_q(15) and VCO_q(6))='1' and HSYNC_I_q = "00000000")); --- NUR MÖGLICH WENN BEIDE - VERZ2_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') + -- NUR MÖGLICH WENN BEIDE + VERZ2_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') and VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and VCO_q(5))='1' and VSYNC_I_q = "000")); - nBLANK_clk <= PIXEL_CLK; + nBLANK_clk <= PIXEL_CLK; --- nBLANK = VERZ[0][8]; + -- nBLANK = VERZ[0][8]; nblank_d <= verz0_q(8); --- nBLANK_d <= DISP_ON_q; - HSYNC_clk <= PIXEL_CLK; + + -- nBLANK_d <= DISP_ON_q; + HSYNC_clk <= PIXEL_CLK; --- HSYNC = VERZ[1][9]; --- NUR MÖGLICH WENN BEIDE - HSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') and + -- HSYNC = VERZ[1][9]; + -- NUR MÖGLICH WENN BEIDE + HSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') and HSYNC_I_q /= "00000000")) or (to_std_logic((ACP_VCTR_q(15) and VCO_q(6))='1' and HSYNC_I_q = "00000000")); - VSYNC_clk <= PIXEL_CLK; + VSYNC_clk <= PIXEL_CLK; --- VSYNC = VERZ[2][9]; --- NUR MÖGLICH WENN BEIDE + -- VSYNC = VERZ[2][9]; + -- NUR MÖGLICH WENN BEIDE VSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') and VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and VCO_q(5))='1' and VSYNC_I_q = "000")); nSYNC <= gnd; --- RANDFARBE MACHEN ------------------------------------ + -- RANDFARBE MACHEN ------------------------------------ RAND0_clk_ctrl <= PIXEL_CLK; RAND_d(0) <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25); RAND_d(1) <= RAND_q(0); @@ -2005,63 +2007,63 @@ BEGIN RAND_d(5) <= RAND_q(4); RAND_d(6) <= RAND_q(5); --- RAND_ON = RAND[6]; + -- RAND_ON = RAND[6]; rand_on <= rand(6); -- RAND_ON <= DISP_ON_q and (not VDTRON_q) and ACP_VCTR_q(25); --- -------------------------------------------------------- - CLR_FIFO_clk <= PIXEL_CLK; - CLR_FIFO_ena <= LAST_q; + -- -------------------------------------------------------- + CLR_FIFO_clk <= PIXEL_CLK; + CLR_FIFO_ena <= LAST_q; --- IN LETZTER ZEILE LÖSCHEN - CLR_FIFO_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(V_TOTAL) - 2))); - START_ZEILE_clk <= PIXEL_CLK; - START_ZEILE_ena <= LAST_q; + -- IN LETZTER ZEILE LÖSCHEN + CLR_FIFO_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(V_TOTAL) - 2))); + START_ZEILE_clk <= PIXEL_CLK; + START_ZEILE_ena <= LAST_q; --- ZEILE 1 - START_ZEILE_d <= to_std_logic(VVCNT_q = "00000000000"); - SYNC_PIX_clk <= PIXEL_CLK; + -- ZEILE 1 + START_ZEILE_d <= to_std_logic(VVCNT_q = "00000000000"); + SYNC_PIX_clk <= PIXEL_CLK; --- SUB PIXEL ZÄHLER SYNCHRONISIEREN - SYNC_PIX_d <= to_std_logic(VHCNT_q = "000000000011") and START_ZEILE_q; - SYNC_PIX1_clk <= PIXEL_CLK; + -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + SYNC_PIX_d <= to_std_logic(VHCNT_q = "000000000011") and START_ZEILE_q; + SYNC_PIX1_clk <= PIXEL_CLK; --- SUB PIXEL ZÄHLER SYNCHRONISIEREN - SYNC_PIX1_d <= to_std_logic(VHCNT_q = "000000000101") and START_ZEILE_q; - SYNC_PIX2_clk <= PIXEL_CLK; + -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + SYNC_PIX1_d <= to_std_logic(VHCNT_q = "000000000101") and START_ZEILE_q; + SYNC_PIX2_clk <= PIXEL_CLK; --- SUB PIXEL ZÄHLER SYNCHRONISIEREN - SYNC_PIX2_d <= to_std_logic(VHCNT_q = "000000000111") and START_ZEILE_q; - SUB_PIXEL_CNT0_clk_ctrl <= PIXEL_CLK; - SUB_PIXEL_CNT0_ena_ctrl <= VDTRON_q or SYNC_PIX_q; + -- SUB PIXEL ZÄHLER SYNCHRONISIEREN + SYNC_PIX2_d <= to_std_logic(VHCNT_q = "000000000111") and START_ZEILE_q; + SUB_PIXEL_CNT0_clk_ctrl <= PIXEL_CLK; + SUB_PIXEL_CNT0_ena_ctrl <= VDTRON_q or SYNC_PIX_q; --- count up if display on sonst clear bei sync pix - SUB_PIXEL_CNT_d <= (std_logic_vector(unsigned(SUB_PIXEL_CNT_q) + 1)) and sizeIt(not SYNC_PIX_q,7); - FIFO_RDE_clk <= PIXEL_CLK; + -- count up if display on sonst clear bei sync pix + SUB_PIXEL_CNT_d <= (std_logic_vector(unsigned(SUB_PIXEL_CNT_q) + 1)) and sizeIt(not SYNC_PIX_q,7); + FIFO_RDE_clk <= PIXEL_CLK; --- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION - FIFO_RDE_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and COLOR1) or + -- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION + FIFO_RDE_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and COLOR1) or (to_std_logic(SUB_PIXEL_CNT_q(5 DOWNTO 0) = "000001") and COLOR2) or (to_std_logic(SUB_PIXEL_CNT_q(4 DOWNTO 0) = "00001") and COLOR4) or (to_std_logic(SUB_PIXEL_CNT_q(3 DOWNTO 0) = "0001") and COLOR8) or (to_std_logic(SUB_PIXEL_CNT_q(2 DOWNTO 0) = "001") and COLOR16) or (to_std_logic(SUB_PIXEL_CNT_q(1 DOWNTO 0) = "01") and COLOR24)) and VDTRON_q) or SYNC_PIX_q or SYNC_PIX1_q or SYNC_PIX2_q; - CLUT_MUX_ADR0_clk_ctrl <= PIXEL_CLK; - CLUT_MUX_AV1_0_clk_ctrl <= PIXEL_CLK; - CLUT_MUX_AV0_0_clk_ctrl <= PIXEL_CLK; - CLUT_MUX_AV0_d <= SUB_PIXEL_CNT_q(3 DOWNTO 0); - CLUT_MUX_AV1_d <= CLUT_MUX_AV0_q; - CLUT_MUX_ADR_d <= CLUT_MUX_AV1_q; + CLUT_MUX_ADR0_clk_ctrl <= PIXEL_CLK; + CLUT_MUX_AV1_0_clk_ctrl <= PIXEL_CLK; + CLUT_MUX_AV0_0_clk_ctrl <= PIXEL_CLK; + CLUT_MUX_AV0_d <= SUB_PIXEL_CNT_q(3 DOWNTO 0); + CLUT_MUX_AV1_d <= CLUT_MUX_AV0_q; + CLUT_MUX_ADR_d <= CLUT_MUX_AV1_q; --- Assignments added to explicitly combine the --- effects of multiple drivers in the source - COLOR16 <= COLOR16_1 or COLOR16_2; - COLOR4 <= COLOR4_1 or COLOR4_2; - COLOR1 <= COLOR1_1 or COLOR1_2 or COLOR1_3; - COLOR8 <= COLOR8_1 or COLOR8_2; + -- Assignments added to explicitly combine the + -- effects of multiple drivers in the source + COLOR16 <= COLOR16_1 or COLOR16_2; + COLOR4 <= COLOR4_1 or COLOR4_2; + COLOR1 <= COLOR1_1 or COLOR1_2 or COLOR1_3; + COLOR8 <= COLOR8_1 or COLOR8_2; --- Define power SIGNAL(s) - gnd <= '0'; + -- Define power SIGNAL(s) + gnd <= '0'; END ARCHITECTURE rtl; diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf index a73de2d..5e7140b 100644 --- a/FPGA_Quartus_13.1/firebee1.qsf +++ b/FPGA_Quartus_13.1/firebee1.qsf @@ -365,12 +365,12 @@ set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" -set_global_assignment -name FITTER_EFFORT "AUTO FIT" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK @@ -664,7 +664,7 @@ set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON -set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS" set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON set_global_assignment -name SAVE_DISK_SPACE OFF set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON @@ -672,14 +672,18 @@ set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF +set_global_assignment -name SDC_FILE firebee_groups.sdc +set_global_assignment -name VHDL_FILE Video/video.vhd set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd set_global_assignment -name SOURCE_FILE altpll4.cmp -set_global_assignment -name SDC_FILE firebee1.sdc set_global_assignment -name VHDL_FILE firebee1.vhd -set_global_assignment -name VHDL_FILE Video/video.vhd set_global_assignment -name VHDL_FILE Video/mux41.vhd set_global_assignment -name VHDL_FILE Video/mux41_5.vhd set_global_assignment -name VHDL_FILE Video/mux41_4.vhd @@ -854,4 +858,6 @@ set_global_assignment -name QIP_FILE lpm_mux0.qip set_global_assignment -name QIP_FILE lpm_shiftreg0.qip set_global_assignment -name QIP_FILE lpm_counter1.qip set_global_assignment -name QIP_FILE altiobuf_bidir0.qip +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/FPGA_Quartus_13.1/firebee1.qws b/FPGA_Quartus_13.1/firebee1.qws index e98d7ce..80b4fbf 100644 Binary files a/FPGA_Quartus_13.1/firebee1.qws and b/FPGA_Quartus_13.1/firebee1.qws differ diff --git a/FPGA_Quartus_13.1/firebee1.sdc b/FPGA_Quartus_13.1/firebee1.sdc index 189849d..993879a 100644 --- a/FPGA_Quartus_13.1/firebee1.sdc +++ b/FPGA_Quartus_13.1/firebee1.sdc @@ -109,8 +109,8 @@ derive_pll_clocks # Set Clock Uncertainty #************************************************************** -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 2.00 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 2.00 +#set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 2.00 +#set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 2.00 derive_clock_uncertainty @@ -118,8 +118,8 @@ derive_clock_uncertainty # Set Input Delay #************************************************************** -set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_inputs] -set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_inputs] +# set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_inputs] +# set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_inputs] #set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}] #set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE} @@ -130,8 +130,8 @@ set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_inputs # Set Output Delay #************************************************************** -set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_outputs] -set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_outputs] +# set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_outputs] +# set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_outputs] #set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}] #set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_TA} diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index 5ebfa52..d7c0db0 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -242,6 +242,53 @@ ARCHITECTURE rtl OF firebee1 IS ); END COMPONENT altpll4; + COMPONENT Video + PORT + ( + FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + MAIN_CLK : IN STD_LOGIC; + nFB_CS1 : IN STD_LOGIC; + nFB_CS2 : IN STD_LOGIC; + nFB_CS3 : IN STD_LOGIC; + nFB_WR : IN STD_LOGIC; + FB_SIZE0 : IN STD_LOGIC; + FB_SIZE1 : IN STD_LOGIC; + nRSTO : IN STD_LOGIC; + nFB_OE : IN STD_LOGIC; + FB_ALE : IN STD_LOGIC; + DDRCLK : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + DDR_SYNC_66M : IN STD_LOGIC; + CLK33M : IN STD_LOGIC; + CLK25M : IN STD_LOGIC; + CLK_VIDEO : IN STD_LOGIC; + VR_D : IN STD_LOGIC_VECTOR(8 DOWNTO 0); + VR_BUSY : IN STD_LOGIC; + VG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + VB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + VR : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + nBLANK : OUT STD_LOGIC; + VA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); + nVWE : OUT STD_LOGIC; + nVCAS : OUT STD_LOGIC; + nVRAS : OUT STD_LOGIC; + nVCS : OUT STD_LOGIC; + VDM : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + nPD_VGA : OUT STD_LOGIC; + VCKE : OUT STD_LOGIC; + VSYNC : OUT STD_LOGIC; + HSYNC : OUT STD_LOGIC; + nSYNC : OUT STD_LOGIC; + VIDEO_TA : OUT STD_LOGIC; + PIXEL_CLK : OUT STD_LOGIC; + BA : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + VIDEO_RECONFIG : OUT STD_LOGIC; + VR_WR : OUT STD_LOGIC; + VR_RD : OUT STD_LOGIC; + VDQS : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0); + FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + VD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; BEGIN nDREQ1 <= nDACK1; @@ -472,7 +519,7 @@ BEGIN ); - i_video : work.video + i_video : video PORT MAP ( MAIN_CLK => MAIN_CLK, diff --git a/FPGA_Quartus_13.1/firebee_groups.sdc b/FPGA_Quartus_13.1/firebee_groups.sdc index 97bcc70..3924ec3 100644 --- a/FPGA_Quartus_13.1/firebee_groups.sdc +++ b/FPGA_Quartus_13.1/firebee_groups.sdc @@ -90,6 +90,9 @@ create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_por #************************************************************** derive_pll_clocks + +create_generated_clock -divide_by 2 -source MAIN_CLK i_video|i_video_mod_mux_clutctr|CLK17M_q +create_generated_clock -divide_by 2 -source i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[2] i_video|i_video_mod_mux_clutctr|CLK13M_q # PIXEL_CLK is either # CLK13M, CLK17M, CLK25M, CLK33M or CLK_VIDEO @@ -109,8 +112,8 @@ derive_pll_clocks # Set Clock Uncertainty #************************************************************** -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 2.0 -set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 2.0 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.5 +set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.5 derive_clock_uncertainty @@ -133,38 +136,43 @@ set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 0.500 [all_outpu #************************************************************** # Set Clock Groups #************************************************************** - + set_clock_groups -asynchronous -group [get_clocks {MAIN_CLK}] \ [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] \ -group [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] \ - [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] \ - [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] \ - [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] \ - -group [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] \ + [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] \ + [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] \ + [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] \ + -group [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] \ -group [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] \ -group [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] \ -group [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] \ -group [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] \ -group [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] \ -group [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] \ - -group [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] - + -group [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] \ + -group [get_clocks {video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|CLK17M_q}] \ + -group [get_clocks {video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|CLK13M_q}] + + #************************************************************** # Set False Path #************************************************************** -set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}] -set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}] -set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}] -set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}] -set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}] - - #************************************************************** # Set Multicycle Path #************************************************************** -set_multicycle_path -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2 +#set_multicycle_path -start -from video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|CLK17M_q -to i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0] 2 +#set_multicycle_path -start -from video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|CLK13M_q -to i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0] 2 + +#set_multicycle_path -end -from video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|CLK13M_q -to MAIN_CLK 2 + +#set_multicycle_path -start -from MAIN_CLK -to i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0] 2 +#set_multicycle_path -start -from MAIN_CLK -to i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1] 2 +#set_multicycle_path -start -from MAIN_CLK -to i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0] 2 + +# set_multicycle_path -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2 #************************************************************** # Set Maximum Delay