remove unneeded component declarations

FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd

@@ -5096,8 +5096,7 @@ BEGIN
    INT_CTR0_clk_ctrl <= MAIN_CLK;
 
 --  $10000/4
-   INT_CTR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) =
+   INT_CTR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4000" else '0';
-	 "00000000000100000000000000");
    INT_CTR_d <= FB_AD;
    INT_CTR24_ena_ctrl <= INT_CTR_CS and FB_B(0) and (not nFB_WR);
    INT_CTR16_ena_ctrl <= INT_CTR_CS and FB_B(1) and (not nFB_WR);
@@ -5109,8 +5108,10 @@ BEGIN
    INT_ENA0_clrn_ctrl <= nRSTO;
 
 --  $10004/4
-   INT_ENA_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) =
+    int_ena_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4001";
-	 "00000000000100000000000001");
+    
+    -- INT_ENA_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) =
+    -- "00000000000100000000000001");
    INT_ENA_d <= FB_AD;
    INT_ENA24_ena_ctrl <= INT_ENA_CS and FB_B(0) and (not nFB_WR);
    INT_ENA16_ena_ctrl <= INT_ENA_CS and FB_B(1) and (not nFB_WR);
@@ -5121,8 +5122,8 @@ BEGIN
    INT_CLEAR0_clk_ctrl <= MAIN_CLK;
 
 --  $10008/4
-   INT_CLEAR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) =
+    int_clear_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4002" else '0';
-	 "00000000000100000000000010");
+    -- INT_CLEAR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000100000000000010");
    INT_CLEAR_d(31 DOWNTO 24) <= FB_AD(31 DOWNTO 24) and sizeIt(INT_CLEAR_CS,8)
 	 and sizeIt(FB_B(0),8) and sizeIt(not nFB_WR,8);
    INT_CLEAR_d(23 DOWNTO 16) <= FB_AD(23 DOWNTO 16) and sizeIt(INT_CLEAR_CS,8)
@@ -5134,8 +5135,10 @@ BEGIN
 
 --  INTERRUPT LATCH REGISTER READ ONLY
 --  $1000C/4
-   INT_LATCH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) =
+
-	 "00000000000100000000000011");
+    int_latch_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4003";
+    -- INT_LATCH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) =
+	--  "00000000000100000000000011");
 
 --  INTERRUPT
    nIRQ(2) <= not (HSYNC and INT_ENA_q(26));
@@ -6238,7 +6241,7 @@ BEGIN
    u3_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or
 	 ACP_CONF_CS) and (not nFB_OE);
    FB_AD(7 DOWNTO 0) <= u3_tridata;
-   INT_HANDLER_TA <= INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS;
+   INT_HANDLER_TA <= int_ctr_cs or int_ena_cs or int_latch_cs or int_clear_cs;
 
 
 -- Assignments added to explicitly combine the

FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd

@@ -20,11 +20,11 @@
 -- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
 -- Created on Fri Oct 16 15:40:59 2009
 
-LIBRARY ieee;
+library ieee;
-    USE ieee.std_logic_1164.ALL;
+    use ieee.std_logic_1164.all;
-    USE ieee.numeric_std.ALL;
+    use ieee.numeric_std.all;
 
-ENTITY blitter IS
+entity blitter is
 	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
 	PORT
 	(
@@ -50,7 +50,7 @@ ENTITY blitter IS
 		BLITTER_ADR     : OUT std_logic_vector(31 DOWNTO 0);
 		BLITTER_SIG     : OUT std_logic;
 		BLITTER_WR      : OUT std_logic;
-		BLITTER_TA      : OUT std_logic;
+		blitter_ta      : OUT std_logic;
 		FB_AD           : INOUT std_logic_vector(31 DOWNTO 0)
 	);
 	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
@@ -67,6 +67,6 @@ BEGIN
 	BLITTER_ADR <=  x"76543210";
 	BLITTER_SIG <= '0';
 	BLITTER_WR <= '0';
-	BLITTER_TA <= '0';
+	blitter_ta <= '0';
 
 END rtl;

FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd

@@ -116,7 +116,7 @@ end video_mod_mux_clutctr;
 architecture rtl of video_mod_mux_clutctr is
     --  DIV. CONTROL REGISTER
     --  BRAUCHT EIN WAITSTAT
-    --  LÄNGE HSYNC PULS IN PIXEL_CLK
+    --  LÄNGE HSYNC PULS IN PIXEL_CLK
     --  LETZTES PIXEL EINER ZEILE ERREICHT
     --  ATARI RESOLUTION
     --  HORIZONTAL TIMING 640x480
@@ -971,7 +971,8 @@ begin
     --  ST SHIFT MODE
 
     --  $F8260/2
-    ST_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110000");
+    st_shift_mode_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = 19x"7c130" else '0';
+    -- ST_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110000");
     ST_SHIFT_MODE_d <= FB_AD(25 downto 24);
     ST_SHIFT_MODE0_ena_ctrl <= ST_SHIFT_MODE_CS and (not nFB_WR) and FB_B(0);
 
@@ -1027,7 +1028,7 @@ begin
     nPD_VGA <= ACP_VCTR_q(1);
 
     --  ATARI MODUS
-    --  WENN 1 AUTOMATISCHE AUFLÖSUNG
+    --  WENN 1 AUTOMATISCHE AUFLÖSUNG
     ATARI_SYNC <= ACP_VCTR_q(26);
 
     --  HORIZONTAL TIMING 640x480
@@ -1310,7 +1311,7 @@ begin
     u1_enabledt <= (ACP_VCTR_CS or BORDER_COLOR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE);
     FB_AD(15 downto 0) <= u1_tridata;
 
-    VIDEO_MOD_TA <= CLUT_TA_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or
+    video_mod_ta <= clut_ta_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or
                     HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or
                     VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS;
 
@@ -1331,7 +1332,7 @@ begin
                  (CLK_VIDEO and ACP_VIDEO_ON and ACP_VCTR_q(9));
 
     -- ------------------------------------------------------------
-    --  HORIZONTALE SYNC LÄNGE in PIXEL_CLK
+    --  HORIZONTALE SYNC LÄNGE in PIXEL_CLK
     -- --------------------------------------------------------------
 
     --  320 pixels, 32 MHz, RGB
@@ -1378,7 +1379,7 @@ begin
 	 VVCNT_q(0) = VDIS_START(0) and VVCNT_q /= "00000000000" and
 	 (unsigned(VHCNT_q) > unsigned(std_logic_vector(unsigned(HDIS_END) - 2)))));
 
---  DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
+--  DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
    DOP_FIFO_CLR_d <= (INTER_ZEI_q and HSYNC_START_q) or SYNC_PIX_q;
 
 --    RAND_LINKS[]    =  HBE[]                                    &  ACP_VIDEO_ON
@@ -1457,7 +1458,7 @@ begin
 	 VCNTRL_q(2),11)) or (std_logic_vector'('0' & VFT_q(10 downto 1)) and
 	 sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11));
 
-    --  ZÄHLER
+    --  ZÄHLER
     LAST_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(H_TOTAL) - 2)));
 
     VHCNT_d <= (std_logic_vector(unsigned(VHCNT_q) + 1)) and sizeIt(not LAST_q,12);
@@ -1469,7 +1470,7 @@ begin
     --  1 ZEILE DAVOR ON OFF
     DPO_ZL_d <= to_std_logic((unsigned(VVCNT_q) > unsigned(std_logic_vector(unsigned(RAND_OBEN) - 1))) and (unsigned(VVCNT_q) < unsigned(std_logic_vector(unsigned(RAND_UNTEN) - 1))));
 
-    --  AM ZEILENENDE ÜBERNEHMEN
+    --  AM ZEILENENDE ÃœBERNEHMEN
     DPO_ZL_ena <= LAST_q;
 
     --  BESSER EINZELN WEGEN TIMING
@@ -1485,7 +1486,7 @@ begin
     VCO_OFF_d <= to_std_logic(VHCNT_q = HDIS_END);
 
     
-    --  AM ZEILENENDE ÜBERNEHMEN
+    --  AM ZEILENENDE ÃœBERNEHMEN
     VCO_ZL_ena <= LAST_q;
 
     --  1 ZEILE DAVOR ON OFF
@@ -1493,7 +1494,7 @@ begin
 
     VDTRON_d <= (VDTRON_q and (not VCO_OFF_q)) or (VCO_ON_q and VCO_ZL_q);
 
-    --  VERZÖGERUNG UND SYNC
+    --  VERZÖGERUNG UND SYNC
 
     HSYNC_START_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HS_START) - 3)));
 
@@ -1511,7 +1512,7 @@ begin
     VSYNC_I0_ena_ctrl <= LAST_q;
 
     --  3 zeilen vsync length
-    --  runterzählen bis 0
+    --  runterzählen bis 0
     VSYNC_I_d <= 3x"3" when VSYNC_START_q = '1' else
                  std_logic_vector(unsigned(VSYNC_I_q) - 1) when VSYNC_START_q = '0' and VSYNC_I_q /= x"0" else
                  (others => '0');
@@ -1531,12 +1532,12 @@ begin
     VERZ0_d(0) <= DISP_ON_q;
 
     --   VERZ[1][0] = HSYNC_I[] != 0;
-    --  NUR MÖGLICH WENN BEIDE
+    --  NUR MÖGLICH WENN BEIDE
     VERZ1_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1')
 	 and HSYNC_I_q /= "00000000")) or (to_std_logic((ACP_VCTR_q(15) and
 	 VCO_q(6))='1' and HSYNC_I_q = "00000000"));
 
-    --  NUR MÖGLICH WENN BEIDE
+    --  NUR MÖGLICH WENN BEIDE
     VERZ2_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1')
 	 and VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and
 	 VCO_q(5))='1' and VSYNC_I_q = "000"));
@@ -1547,13 +1548,13 @@ begin
     --  nBLANK_d <= DISP_ON_q;
 
     --  HSYNC  =  VERZ[1][9];
-    --  NUR MÖGLICH WENN BEIDE
+    --  NUR MÖGLICH WENN BEIDE
     HSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') and
 	 HSYNC_I_q /= "00000000")) or (to_std_logic((ACP_VCTR_q(15) and
 	 VCO_q(6))='1' and HSYNC_I_q = "00000000"));
 
     --  VSYNC  =  VERZ[2][9];
-    --  NUR MÖGLICH WENN BEIDE
+    --  NUR MÖGLICH WENN BEIDE
     VSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') and
 	 VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and
 	 VCO_q(5))='1' and VSYNC_I_q = "000"));
@@ -1575,20 +1576,20 @@ begin
     -- --------------------------------------------------------
     CLR_FIFO_ena <= LAST_q;
 
-    --  IN LETZTER ZEILE LÖSCHEN
+    --  IN LETZTER ZEILE LÖSCHEN
     CLR_FIFO_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(V_TOTAL) - 2)));
     START_ZEILE_ena <= LAST_q;
 
     --  ZEILE 1
     START_ZEILE_d <= to_std_logic(VVCNT_q = "00000000000");
 
-    --  SUB PIXEL ZÄHLER SYNCHRONISIEREN
+    --  SUB PIXEL ZÄHLER SYNCHRONISIEREN
     SYNC_PIX_d <= to_std_logic(VHCNT_q = "000000000011") and START_ZEILE_q;
 
-    --  SUB PIXEL ZÄHLER SYNCHRONISIEREN
+    --  SUB PIXEL ZÄHLER SYNCHRONISIEREN
     SYNC_PIX1_d <= to_std_logic(VHCNT_q = "000000000101") and START_ZEILE_q;
 
-    --  SUB PIXEL ZÄHLER SYNCHRONISIEREN
+    --  SUB PIXEL ZÄHLER SYNCHRONISIEREN
     SYNC_PIX2_d <= to_std_logic(VHCNT_q = "000000000111") and START_ZEILE_q;
 
     SUB_PIXEL_CNT0_ena_ctrl <= VDTRON_q or SYNC_PIX_q;
@@ -1596,7 +1597,7 @@ begin
     -- count up if display on sonst clear bei sync pix
     SUB_PIXEL_CNT_d <= (std_logic_vector(unsigned(SUB_PIXEL_CNT_q) + 1)) and sizeIt(not SYNC_PIX_q,7);
 
-    --  3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
+    --  3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
     FIFO_RDE_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and COLOR1) or
 	 (to_std_logic(SUB_PIXEL_CNT_q(5 downto 0) = "000001") and COLOR2) or
 	 (to_std_logic(SUB_PIXEL_CNT_q(4 downto 0) = "00001") and color4_i) or

FPGA_Quartus_13.1/firebee1.vhd

@@ -242,53 +242,53 @@ ARCHITECTURE rtl OF firebee1 IS
         );
     END COMPONENT altpll4;
 
-    COMPONENT video
+--    COMPONENT video
-	PORT
+--	PORT
-	(
+--	(
-		FB_ADR		    : IN std_logic_vector(31 DOWNTO 0);
+--		FB_ADR		    : IN std_logic_vector(31 DOWNTO 0);
-		MAIN_CLK	    : IN std_logic;
+--		MAIN_CLK	    : IN std_logic;
-		nFB_CS1		    : IN std_logic;
+--		nFB_CS1		    : IN std_logic;
-		nFB_CS2		    : IN std_logic;
+--		nFB_CS2		    : IN std_logic;
-		nFB_CS3		    : IN std_logic;
+--		nFB_CS3		    : IN std_logic;
-		nFB_WR		    : IN std_logic;
+--		nFB_WR		    : IN std_logic;
-		FB_SIZE0	    : IN std_logic;
+--		FB_SIZE0	    : IN std_logic;
-		FB_SIZE1	    : IN std_logic;
+--		FB_SIZE1	    : IN std_logic;
-		nRSTO		    : IN std_logic;
+--		nRSTO		    : IN std_logic;
-		nFB_OE		    : IN std_logic;
+--		nFB_OE		    : IN std_logic;
-		FB_ALE		    : IN std_logic;
+--		FB_ALE		    : IN std_logic;
-		DDRCLK		    : IN std_logic_vector(3 DOWNTO 0);
+--		DDRCLK		    : IN std_logic_vector(3 DOWNTO 0);
-		DDR_SYNC_66M	: IN std_logic;
+--		DDR_SYNC_66M	: IN std_logic;
-		CLK33M		    : IN std_logic;
+--		CLK33M		    : IN std_logic;
-		CLK25M		    : IN std_logic;
+--		CLK25M		    : IN std_logic;
-		CLK_VIDEO		: IN std_logic;
+--		CLK_VIDEO		: IN std_logic;
-		VR_D		    : IN std_logic_vector(8 DOWNTO 0);
+--		VR_D		    : IN std_logic_vector(8 DOWNTO 0);
-		VR_BUSY		    : IN std_logic;
+--		VR_BUSY		    : IN std_logic;
-		VG		        : OUT std_logic_vector(7 DOWNTO 0);
+--		VG		        : OUT std_logic_vector(7 DOWNTO 0);
-		VB		        : OUT std_logic_vector(7 DOWNTO 0);
+--		VB		        : OUT std_logic_vector(7 DOWNTO 0);
-		VR		        : OUT std_logic_vector(7 DOWNTO 0);
+--		VR		        : OUT std_logic_vector(7 DOWNTO 0);
-		nBLANK		    : OUT std_logic;
+--		nBLANK		    : OUT std_logic;
-		VA		        : OUT std_logic_vector(12 DOWNTO 0);
+--		VA		        : OUT std_logic_vector(12 DOWNTO 0);
-		nVWE		    : OUT std_logic;
+--		nVWE		    : OUT std_logic;
-		nVCAS		    : OUT std_logic;
+--		nVCAS		    : OUT std_logic;
-		nVRAS		    : OUT std_logic;
+--		nVRAS		    : OUT std_logic;
-		nVCS		    : OUT std_logic;
+--		nVCS		    : OUT std_logic;
-		VDM		        : OUT std_logic_vector(3 DOWNTO 0);
+--		VDM		        : OUT std_logic_vector(3 DOWNTO 0);
-		nPD_VGA		    : OUT std_logic;
+--		nPD_VGA		    : OUT std_logic;
-		VCKE		    : OUT std_logic;
+--		VCKE		    : OUT std_logic;
-		VSYNC		    : OUT std_logic;
+--		VSYNC		    : OUT std_logic;
-		HSYNC		    : OUT std_logic;
+--		HSYNC		    : OUT std_logic;
-		nSYNC		    : OUT std_logic;
+--		nSYNC		    : OUT std_logic;
-		VIDEO_TA		: OUT std_logic;
+--		VIDEO_TA		: OUT std_logic;
-		PIXEL_CLK		: OUT std_logic;
+--		PIXEL_CLK		: OUT std_logic;
-		BA		        : OUT std_logic_vector(1 DOWNTO 0);
+--		BA		        : OUT std_logic_vector(1 DOWNTO 0);
-		VIDEO_RECONFIG	: OUT std_logic;
+--		VIDEO_RECONFIG	: OUT std_logic;
-		VR_WR		    : OUT std_logic;
+--		VR_WR		    : OUT std_logic;
-		VR_RD		    : OUT std_logic;
+--		VR_RD		    : OUT std_logic;
-		VDQS		    : INOUT std_logic_vector(3 DOWNTO 0);
+--		VDQS		    : INOUT std_logic_vector(3 DOWNTO 0);
-		FB_AD		    : INOUT std_logic_vector(31 DOWNTO 0);
+--		FB_AD		    : INOUT std_logic_vector(31 DOWNTO 0);
-		VD		        : INOUT std_logic_vector(31 DOWNTO 0)
+--		VD		        : INOUT std_logic_vector(31 DOWNTO 0)
-	);
+--	);
-    END COMPONENT video;
+--    END COMPONENT video;
 BEGIN 
     nDREQ1 <= nDACK1;
     
@@ -519,7 +519,7 @@ BEGIN
         );
     
     
-    i_video : video
+    i_video : entity work.video
         PORT MAP
         (
             MAIN_CLK => MAIN_CLK,
@@ -606,7 +606,7 @@ BEGIN
     
     nWR_GATE <= not(WR_GATE);
 
-    nFB_TA <= not(Video_TA or INT_HANDLER_TA or DSP_TA or FALCON_IO_TA);
+    nFB_TA <= not(video_ta or int_handler_ta or dsp_ta or falcon_io_ta);
     
     CLK33M <= MAIN_CLK;