From 790663a7cf572558095cfe46a58ac2d2e9eb1850 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= <mfro@mubf.de>
Date: Wed, 27 Apr 2016 11:32:14 +0000
Subject: [PATCH] remove unneeded component declarations

---
 .../Interrupt_Handler/interrupt_handler.vhd   |   21 +-
 FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd   |   12 +-
 FPGA_Quartus_13.1/Video/video.vhd             |  892 ++--------
 .../Video/video_mod_mux_clutctr.vhd           |   41 +-
 FPGA_Quartus_13.1/firebee1.qsf                | 1490 ++++++++---------
 FPGA_Quartus_13.1/firebee1.vhd                |   98 +-
 6 files changed, 1005 insertions(+), 1549 deletions(-)

diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd
index 2c56b5b..74699d5 100755
--- a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd
+++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd
@@ -5096,8 +5096,7 @@ BEGIN
    INT_CTR0_clk_ctrl <= MAIN_CLK;
 
 --  $10000/4
-   INT_CTR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) =
-	 "00000000000100000000000000");
+   INT_CTR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4000" else '0';
    INT_CTR_d <= FB_AD;
    INT_CTR24_ena_ctrl <= INT_CTR_CS and FB_B(0) and (not nFB_WR);
    INT_CTR16_ena_ctrl <= INT_CTR_CS and FB_B(1) and (not nFB_WR);
@@ -5109,8 +5108,10 @@ BEGIN
    INT_ENA0_clrn_ctrl <= nRSTO;
 
 --  $10004/4
-   INT_ENA_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) =
-	 "00000000000100000000000001");
+    int_ena_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4001";
+    
+    -- INT_ENA_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) =
+    -- "00000000000100000000000001");
    INT_ENA_d <= FB_AD;
    INT_ENA24_ena_ctrl <= INT_ENA_CS and FB_B(0) and (not nFB_WR);
    INT_ENA16_ena_ctrl <= INT_ENA_CS and FB_B(1) and (not nFB_WR);
@@ -5121,8 +5122,8 @@ BEGIN
    INT_CLEAR0_clk_ctrl <= MAIN_CLK;
 
 --  $10008/4
-   INT_CLEAR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) =
-	 "00000000000100000000000010");
+    int_clear_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4002" else '0';
+    -- INT_CLEAR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000100000000000010");
    INT_CLEAR_d(31 DOWNTO 24) <= FB_AD(31 DOWNTO 24) and sizeIt(INT_CLEAR_CS,8)
 	 and sizeIt(FB_B(0),8) and sizeIt(not nFB_WR,8);
    INT_CLEAR_d(23 DOWNTO 16) <= FB_AD(23 DOWNTO 16) and sizeIt(INT_CLEAR_CS,8)
@@ -5134,8 +5135,10 @@ BEGIN
 
 --  INTERRUPT LATCH REGISTER READ ONLY
 --  $1000C/4
-   INT_LATCH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) =
-	 "00000000000100000000000011");
+
+    int_latch_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = x"4003";
+    -- INT_LATCH_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) =
+	--  "00000000000100000000000011");
 
 --  INTERRUPT
    nIRQ(2) <= not (HSYNC and INT_ENA_q(26));
@@ -6238,7 +6241,7 @@ BEGIN
    u3_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or
 	 ACP_CONF_CS) and (not nFB_OE);
    FB_AD(7 DOWNTO 0) <= u3_tridata;
-   INT_HANDLER_TA <= INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS;
+   INT_HANDLER_TA <= int_ctr_cs or int_ena_cs or int_latch_cs or int_clear_cs;
 
 
 -- Assignments added to explicitly combine the
diff --git a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd
index b083539..933b8b2 100644
--- a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd
+++ b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd
@@ -20,11 +20,11 @@
 -- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
 -- Created on Fri Oct 16 15:40:59 2009
 
-LIBRARY ieee;
-    USE ieee.std_logic_1164.ALL;
-    USE ieee.numeric_std.ALL;
+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
 
-ENTITY blitter IS
+entity blitter is
 	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
 	PORT
 	(
@@ -50,7 +50,7 @@ ENTITY blitter IS
 		BLITTER_ADR     : OUT std_logic_vector(31 DOWNTO 0);
 		BLITTER_SIG     : OUT std_logic;
 		BLITTER_WR      : OUT std_logic;
-		BLITTER_TA      : OUT std_logic;
+		blitter_ta      : OUT std_logic;
 		FB_AD           : INOUT std_logic_vector(31 DOWNTO 0)
 	);
 	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
@@ -67,6 +67,6 @@ BEGIN
 	BLITTER_ADR <=  x"76543210";
 	BLITTER_SIG <= '0';
 	BLITTER_WR <= '0';
-	BLITTER_TA <= '0';
+	blitter_ta <= '0';
 
 END rtl;
diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd
index 0706292..f99242b 100644
--- a/FPGA_Quartus_13.1/Video/video.vhd
+++ b/FPGA_Quartus_13.1/Video/video.vhd
@@ -72,638 +72,90 @@ END video;
 ARCHITECTURE rtl OF video IS 
     ATTRIBUTE black_box     : BOOLEAN;
     ATTRIBUTE noopt         : BOOLEAN;
-    
-    COMPONENT mux41_0
-        PORT
-        (
-            S0  : IN std_logic;
-            S1  : IN std_logic;
-            D0  : IN std_logic;
-            INH : IN std_logic;
-            D1  : IN std_logic;
-            Q   : OUT std_logic
-        );
-    END COMPONENT mux41_0;
-    
-    ATTRIBUTE black_box OF mux41_0: COMPONENT IS true;
-    ATTRIBUTE noopt OF mux41_0: COMPONENT IS true;
-    
-    COMPONENT mux41_1
-        PORT
-        (
-            S0  : IN std_logic;
-            S1  : IN std_logic;
-            D0  : IN std_logic;
-            INH : IN std_logic;
-            D1  : IN std_logic;
-            Q   : OUT std_logic
-        );
-    END COMPONENT mux41_1;
-    
-    ATTRIBUTE black_box OF mux41_1: COMPONENT IS true;
-    ATTRIBUTE noopt OF mux41_1: COMPONENT IS true;
-    
-    COMPONENT mux41_2
-        PORT
-        (
-            S0  : IN std_logic;
-            D2  : IN std_logic;
-            S1  : IN std_logic;
-            D0  : IN std_logic;
-            INH : IN std_logic;
-            D1  : IN std_logic;
-            Q   : OUT std_logic
-        );
-    END COMPONENT mux41_2;
-    
-    ATTRIBUTE black_box OF mux41_2: COMPONENT IS true;
-    ATTRIBUTE noopt OF mux41_2: COMPONENT IS true;
-    
-    COMPONENT mux41_3
-        PORT
-        (
-            S0  : IN std_logic;
-            D2  : IN std_logic;
-            S1  : IN std_logic;
-            D0  : IN std_logic;
-            INH : IN std_logic;
-            D1  : IN std_logic;
-            Q   : OUT std_logic
-        );
-    END COMPONENT mux41_3;
-    
-    ATTRIBUTE black_box OF mux41_3: COMPONENT IS true;
-    ATTRIBUTE noopt OF mux41_3: COMPONENT IS true;
-    
-    COMPONENT mux41_4
-        PORT
-        (
-            S0  : IN std_logic;
-            D2  : IN std_logic;
-            S1  : IN std_logic;
-            D0  : IN std_logic;
-            INH : IN std_logic;
-            D1  : IN std_logic;
-            Q   : OUT std_logic
-        );
-    END COMPONENT;
-    
-    ATTRIBUTE black_box OF mux41_4: COMPONENT IS true;
-    ATTRIBUTE noopt OF mux41_4: COMPONENT IS true;
-    
-    COMPONENT mux41_5
-        PORT
-        (
-            S0  : IN std_logic;
-            D2  : IN std_logic;
-            S1  : IN std_logic;
-            D0  : IN std_logic;
-            INH : IN std_logic;
-            D1  : IN std_logic;
-            Q   : OUT std_logic
-        );
-    END COMPONENT;
-    
-    ATTRIBUTE black_box OF mux41_5: COMPONENT IS true;
-    ATTRIBUTE noopt OF mux41_5: COMPONENT IS true;
-    
-    COMPONENT altdpram2
-        PORT
-        (
-            wren_a      : IN std_logic;
-            wren_b      : IN std_logic;
-            clock_a     : IN std_logic;
-            clock_b     : IN std_logic;
-            address_a   : IN std_logic_vector(7 DOWNTO 0);
-            address_b   : IN std_logic_vector(7 DOWNTO 0);
-            data_a      : IN std_logic_vector(7 DOWNTO 0);
-            data_b      : IN std_logic_vector(7 DOWNTO 0);
-            q_a         : OUT std_logic_vector(7 DOWNTO 0);
-            q_b         : OUT std_logic_vector(7 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT ddr_ctr
-        PORT
-        (
-            nFB_CS1         : IN std_logic;
-            nFB_CS2         : IN std_logic;
-            nFB_CS3         : IN std_logic;
-            nFB_OE          : IN std_logic;
-            FB_SIZE0        : IN std_logic;
-            FB_SIZE1        : IN std_logic;
-            nRSTO           : IN std_logic;
-            MAIN_CLK        : IN std_logic;
-            FB_ALE          : IN std_logic;
-            nFB_WR          : IN std_logic;
-            DDR_SYNC_66M    : IN std_logic;
-            BLITTER_SIG     : IN std_logic;
-            BLITTER_WR      : IN std_logic;
-            DDRCLK0         : IN std_logic;
-            CLK33M          : IN std_logic;
-            CLR_FIFO        : IN std_logic;
-            BLITTER_ADR     : IN std_logic_vector(31 DOWNTO 0);
-            FB_AD           : INOUT std_logic_vector(31 DOWNTO 0);
-            FB_ADR          : IN std_logic_vector(31 DOWNTO 0);
-            FIFO_MW         : IN std_logic_vector(8 DOWNTO 0);
-            VIDEO_RAM_CTR   : IN std_logic_vector(15 DOWNTO 0);
-            nVWE            : OUT std_logic;
-            nVRAS           : OUT std_logic;
-            nVCS            : OUT std_logic;
-            VCKE            : OUT std_logic;
-            nVCAS           : OUT std_logic;
-            SR_FIFO_WRE     : OUT std_logic;
-            SR_DDR_FB       : OUT std_logic;
-            SR_DDR_WR       : OUT std_logic;
-            SR_DDRWR_D_SEL  : OUT std_logic;
-            VIDEO_DDR_TA    : OUT std_logic;
-            SR_BLITTER_DACK : OUT std_logic;
-            DDRWR_D_SEL1    : OUT std_logic;
-            BA              : OUT std_logic_vector(1 DOWNTO 0);
-            FB_LE           : OUT std_logic_vector(3 DOWNTO 0);
-            FB_VDOE         : OUT std_logic_vector(3 DOWNTO 0);
-            SR_VDMP         : OUT std_logic_vector(7 DOWNTO 0);
-            VA              : OUT std_logic_vector(12 DOWNTO 0);
-            VDM_SEL         : OUT std_logic_vector(3 DOWNTO 0)
-        );
-    END COMPONENT ddr_ctr;
-    
-    COMPONENT altdpram1
-        PORT
-        (
-            wren_a      : IN std_logic;
-            wren_b      : IN std_logic;
-            clock_a     : IN std_logic;
-            clock_b     : IN std_logic;
-            address_a   : IN std_logic_vector(7 DOWNTO 0);
-            address_b   : IN std_logic_vector(7 DOWNTO 0);
-            data_a      : IN std_logic_vector(5 DOWNTO 0);
-            data_b      : IN std_logic_vector(5 DOWNTO 0);
-            q_a         : OUT std_logic_vector(5 DOWNTO 0);
-            q_b         : OUT std_logic_vector(5 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_fifo_dc0
-        PORT
-        (
-            wrreq   : IN std_logic;
-            wrclk   : IN std_logic;
-            rdreq   : IN std_logic;
-            rdclk   : IN std_logic;
-            aclr    : IN std_logic;
-            data    : IN std_logic_vector(127 DOWNTO 0);
-            rdempty : OUT std_logic;
-            q       : OUT std_logic_vector(127 DOWNTO 0);
-            wrusedw : OUT std_logic_vector(8 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT altddio_bidir0
-        PORT
-        (
-            oe          : IN std_logic;
-            inclock     : IN std_logic;
-            outclock    : IN std_logic;
-            datain_h    : IN std_logic_vector(31 DOWNTO 0);
-            datain_l    : IN std_logic_vector(31 DOWNTO 0);
-            padio       : INOUT std_logic_vector(31 DOWNTO 0);
-            combout     : OUT std_logic_vector(31 DOWNTO 0);
-            dataout_h   : OUT std_logic_vector(31 DOWNTO 0);
-            dataout_l   : OUT std_logic_vector(31 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_ff4
-        PORT
-        (
-            clock   : IN std_logic;
-            data    : IN std_logic_vector(15 DOWNTO 0);
-            q       : OUT std_logic_vector(15 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_muxvdm
-        PORT
-        (
-            data0x  : IN std_logic_vector(127 DOWNTO 0);
-            data10x : IN std_logic_vector(127 DOWNTO 0);
-            data11x : IN std_logic_vector(127 DOWNTO 0);
-            data12x : IN std_logic_vector(127 DOWNTO 0);
-            data13x : IN std_logic_vector(127 DOWNTO 0);
-            data14x : IN std_logic_vector(127 DOWNTO 0);
-            data15x : IN std_logic_vector(127 DOWNTO 0);
-            data1x  : IN std_logic_vector(127 DOWNTO 0);
-            data2x  : IN std_logic_vector(127 DOWNTO 0);
-            data3x  : IN std_logic_vector(127 DOWNTO 0);
-            data4x  : IN std_logic_vector(127 DOWNTO 0);
-            data5x  : IN std_logic_vector(127 DOWNTO 0);
-            data6x  : IN std_logic_vector(127 DOWNTO 0);
-            data7x  : IN std_logic_vector(127 DOWNTO 0);
-            data8x  : IN std_logic_vector(127 DOWNTO 0);
-            data9x  : IN std_logic_vector(127 DOWNTO 0);
-            sel     : IN std_logic_vector(3 DOWNTO 0);
-            result  : OUT std_logic_vector(127 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_mux3
-        PORT
-        (
-            data1   : IN std_logic;
-            data0   : IN std_logic;
-            sel     : IN std_logic;
-            result  : OUT std_logic
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_bustri_long
-        PORT
-        (
-            enabledt    : IN std_logic;
-            data        : IN std_logic_vector(31 DOWNTO 0);
-            tridata     : INOUT std_logic_vector(31 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_ff5
-        PORT
-        (
-            clock   : IN std_logic;
-            data    : IN std_logic_vector(7 DOWNTO 0);
-            q       : OUT std_logic_vector(7 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_ff1
-        PORT
-        (
-            clock   : IN std_logic;
-            data    : IN std_logic_vector(31 DOWNTO 0);
-            q       : OUT std_logic_vector(31 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_ff0
-        PORT
-        (
-            clock   : IN std_logic;
-            enable  : IN std_logic;
-            data    : IN std_logic_vector(31 DOWNTO 0);
-            q       : OUT std_logic_vector(31 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT altddio_out0
-        PORT
-        (
-            outclock    : IN std_logic;
-            datain_h    : IN std_logic_vector(3 DOWNTO 0);
-            datain_l    : IN std_logic_vector(3 DOWNTO 0);
-            dataout     : OUT std_logic_vector(3 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_mux0
-        PORT
-        (
-            clock   : IN std_logic;
-            data0x  : IN std_logic_vector(31 DOWNTO 0);
-            data1x  : IN std_logic_vector(31 DOWNTO 0);
-            data2x  : IN std_logic_vector(31 DOWNTO 0);
-            data3x  : IN std_logic_vector(31 DOWNTO 0);
-            sel     : IN std_logic_vector(1 DOWNTO 0);
-            result  : OUT std_logic_vector(31 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_mux5
-        PORT
-        (
-            data0x  : IN std_logic_vector(63 DOWNTO 0);
-            data1x  : IN std_logic_vector(63 DOWNTO 0);
-            data2x  : IN std_logic_vector(63 DOWNTO 0);
-            data3x  : IN std_logic_vector(63 DOWNTO 0);
-            sel     : IN std_logic_vector(1 DOWNTO 0);
-            result  : OUT std_logic_vector(63 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_constant2
-        PORT
-        (
-            result  : OUT std_logic_vector(7 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_mux1
-        PORT
-        (
-            clock   : IN std_logic;
-            data0x  : IN std_logic_vector(15 DOWNTO 0);
-            data1x  : IN std_logic_vector(15 DOWNTO 0);
-            data2x  : IN std_logic_vector(15 DOWNTO 0);
-            data3x  : IN std_logic_vector(15 DOWNTO 0);
-            data4x  : IN std_logic_vector(15 DOWNTO 0);
-            data5x  : IN std_logic_vector(15 DOWNTO 0);
-            data6x  : IN std_logic_vector(15 DOWNTO 0);
-            data7x  : IN std_logic_vector(15 DOWNTO 0);
-            sel     : IN std_logic_vector(2 DOWNTO 0);
-            result  : OUT std_logic_vector(15 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_mux2
-        PORT
-        (
-            clock   : IN std_logic;
-            data0x  : IN std_logic_vector(7 DOWNTO 0);
-            data10x : IN std_logic_vector(7 DOWNTO 0);
-            data11x : IN std_logic_vector(7 DOWNTO 0);
-            data12x : IN std_logic_vector(7 DOWNTO 0);
-            data13x : IN std_logic_vector(7 DOWNTO 0);
-            data14x : IN std_logic_vector(7 DOWNTO 0);
-            data15x : IN std_logic_vector(7 DOWNTO 0);
-            data1x  : IN std_logic_vector(7 DOWNTO 0);
-            data2x  : IN std_logic_vector(7 DOWNTO 0);
-            data3x  : IN std_logic_vector(7 DOWNTO 0);
-            data4x  : IN std_logic_vector(7 DOWNTO 0);
-            data5x  : IN std_logic_vector(7 DOWNTO 0);
-            data6x  : IN std_logic_vector(7 DOWNTO 0);
-            data7x  : IN std_logic_vector(7 DOWNTO 0);
-            data8x  : IN std_logic_vector(7 DOWNTO 0);
-            data9x  : IN std_logic_vector(7 DOWNTO 0);
-            sel     : IN std_logic_vector(3 DOWNTO 0);
-            result  : OUT std_logic_vector(7 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_shiftreg4
-        PORT
-        (
-            clock       : IN std_logic;
-            shiftin     : IN std_logic;
-            shiftout    : OUT std_logic
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_latch0
-        PORT
-        (
-            gate    : IN std_logic;
-            data    : IN std_logic_vector(31 DOWNTO 0);
-            q       : OUT std_logic_vector(31 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_ff6
-        PORT
-        (
-            clock   : IN std_logic;
-            enable  : IN std_logic;
-            data    : IN std_logic_vector(127 DOWNTO 0);
-            q       : OUT std_logic_vector(127 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_ff3
-        PORT
-        (
-            clock   : IN std_logic;
-            data    : IN std_logic_vector(23 DOWNTO 0);
-            q       : OUT std_logic_vector(23 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT altddio_out2
-        PORT
-        (
-            outclock    : IN std_logic;
-            datain_h    : IN std_logic_vector(23 DOWNTO 0);
-            datain_l    : IN std_logic_vector(23 DOWNTO 0);
-            dataout     : OUT std_logic_vector(23 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_bustri1
-        PORT
-        (
-            enabledt    : IN std_logic;
-            data        : IN std_logic_vector(2 DOWNTO 0);
-            tridata     : INOUT std_logic_vector(2 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_bustri_byt
-        PORT
-        (
-            enabledt    : IN std_logic;
-            data        : IN std_logic_vector(7 DOWNTO 0);
-            tridata     : INOUT std_logic_vector(7 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_constant0
-        PORT
-        (
-            result  : OUT std_logic_vector(4 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_muxdz
-        PORT
-        (
-            clock   : IN std_logic;
-            clken   : IN std_logic;
-            sel     : IN std_logic;
-            data0x  : IN std_logic_vector(127 DOWNTO 0);
-            data1x  : IN std_logic_vector(127 DOWNTO 0);
-            result  : OUT std_logic_vector(127 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_fifodz
-        PORT
-        (
-            wrreq   : IN std_logic;
-            rdreq   : IN std_logic;
-            clock   : IN std_logic;
-            aclr    : IN std_logic;
-            data    : IN std_logic_vector(127 DOWNTO 0);
-            q       : OUT std_logic_vector(127 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_bustri3
-        PORT
-        (
-            enabledt    : IN std_logic;
-            data        : IN std_logic_vector(5 DOWNTO 0);
-            tridata     : INOUT std_logic_vector(5 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_mux6
-        PORT
-        (
-            clock   : IN std_logic;
-            data0x  : IN std_logic_vector(23 DOWNTO 0);
-            data1x  : IN std_logic_vector(23 DOWNTO 0);
-            data2x  : IN std_logic_vector(23 DOWNTO 0);
-            data3x  : IN std_logic_vector(23 DOWNTO 0);
-            data4x  : IN std_logic_vector(23 DOWNTO 0);
-            data5x  : IN std_logic_vector(23 DOWNTO 0);
-            data6x  : IN std_logic_vector(23 DOWNTO 0);
-            data7x  : IN std_logic_vector(23 DOWNTO 0);
-            sel     : IN std_logic_vector(2 DOWNTO 0);
-            result  : OUT std_logic_vector(23 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_constant1
-        PORT
-        (
-            result  : OUT std_logic_vector(1 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_mux4
-        PORT
-        (
-            sel     : IN std_logic;
-            data0x  : IN std_logic_vector(6 DOWNTO 0);
-            data1x  : IN std_logic_vector(6 DOWNTO 0);
-            result  : OUT std_logic_vector(6 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_constant3
-        PORT
-        (
-            result  : OUT std_logic_vector(6 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_shiftreg6
-        PORT
-        (
-            clock   : IN std_logic;
-            shiftin : IN std_logic;
-            q       : OUT std_logic_vector(4 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    COMPONENT lpm_shiftreg0
-        PORT
-        (
-            load        : IN std_logic;
-            clock       : IN std_logic;
-            shiftin     : IN std_logic;
-            data        : IN std_logic_vector(15 DOWNTO 0);
-            shiftout    : OUT std_logic
-        );
-    END COMPONENT;
-    
-    COMPONENT altdpram0
-        PORT
-        (
-            wren_a      : IN std_logic;
-            wren_b      : IN std_logic;
-            clock_a     : IN std_logic;
-            clock_b     : IN std_logic;
-            address_a   : IN std_logic_vector(3 DOWNTO 0);
-            address_b   : IN std_logic_vector(3 DOWNTO 0);
-            data_a      : IN std_logic_vector(2 DOWNTO 0);
-            data_b      : IN std_logic_vector(2 DOWNTO 0);
-            q_a         : OUT std_logic_vector(2 DOWNTO 0);
-            q_b         : OUT std_logic_vector(2 DOWNTO 0)
-        );
-    END COMPONENT;
-    
-    SIGNAL	ACP_CLUT_RD     :  std_logic;
-    SIGNAL	ACP_CLUT_WR     :  std_logic_vector(3 DOWNTO 0);
-    SIGNAL	BLITTER_ADR     :  std_logic_vector(31 DOWNTO 0);
-    SIGNAL	BLITTER_DACK    :  std_logic_vector(4 DOWNTO 0);
-    SIGNAL	BLITTER_DIN     :  std_logic_vector(127 DOWNTO 0);
-    SIGNAL	BLITTER_DOUT    :  std_logic_vector(127 DOWNTO 0);
-    SIGNAL	BLITTER_ON      :  std_logic;
-    SIGNAL	BLITTER_RUN     :  std_logic;
-    SIGNAL	BLITTER_SIG     :  std_logic;
-    SIGNAL	BLITTER_TA      :  std_logic;
-    SIGNAL	BLITTER_WR      :  std_logic;
-    SIGNAL	BORDER_COLOR    :  std_logic_vector(23 DOWNTO 0);
-    SIGNAL	CC16            :  std_logic_vector(23 DOWNTO 0);
-    SIGNAL	CC24            :  std_logic_vector(31 DOWNTO 0);
-    SIGNAL	CCA             :  std_logic_vector(23 DOWNTO 0);
-    SIGNAL	CCF             :  std_logic_vector(23 DOWNTO 0);
-    SIGNAL	CCS             :  std_logic_vector(23 DOWNTO 0);
-    SIGNAL	CCSEL           :  std_logic_vector(2 DOWNTO 0);
-    SIGNAL	CLR_FIFO        :  std_logic;
-    SIGNAL	CLUT_ADR        :  std_logic_vector(7 DOWNTO 0);
-    SIGNAL	CLUT_ADR1A      :  std_logic;
-    SIGNAL	CLUT_ADR2A      :  std_logic;
-    SIGNAL	CLUT_ADR3A      :  std_logic;
-    SIGNAL	CLUT_ADR4A      :  std_logic;
-    SIGNAL	CLUT_ADR5A      :  std_logic;
-    SIGNAL	CLUT_ADR6A      :  std_logic;
-    SIGNAL	CLUT_ADR7A      :  std_logic;
-    SIGNAL	CLUT_MUX_ADR    :  std_logic_vector(3 DOWNTO 0);
-    SIGNAL	CLUT_OFF        :  std_logic_vector(3 DOWNTO 0);
-    SIGNAL	COLOR1          :  std_logic;
-    SIGNAL	COLOR2          :  std_logic;
-    SIGNAL	COLOR4          :  std_logic;
-    SIGNAL	COLOR8          :  std_logic;
-    SIGNAL	DDR_FB          :  std_logic_vector(4 DOWNTO 0);
-    SIGNAL	DDR_WR          :  std_logic;
-    SIGNAL	DDRWR_D_SEL     :  std_logic_vector(1 DOWNTO 0);
-    SIGNAL	DOP_FIFO_CLR    :  std_logic;
-    SIGNAL	FALCON_CLUT_RDH :  std_logic;
-    SIGNAL	FALCON_CLUT_RDL :  std_logic;
-    SIGNAL	FALCON_CLUT_WR  :  std_logic_vector(3 DOWNTO 0);
-    SIGNAL	FB_DDR          :  std_logic_vector(127 DOWNTO 0);
-    SIGNAL	FB_LE           :  std_logic_vector(3 DOWNTO 0);
-    SIGNAL	FB_VDOE         :  std_logic_vector(3 DOWNTO 0);
-    SIGNAL	FIFO_D          :  std_logic_vector(127 DOWNTO 0);
-    SIGNAL	FIFO_MW         :  std_logic_vector(8 DOWNTO 0);
-    SIGNAL	FIFO_RDE        :  std_logic;
-    SIGNAL	FIFO_WRE        :  std_logic;
-    SIGNAL	INTER_ZEI       :  std_logic;
-    SIGNAL	nFB_BURST       :  std_logic := '0';
-    SIGNAL	pixel_clk_i     :  std_logic;
-    SIGNAL	SR_BLITTER_DACK :  std_logic;
-    SIGNAL	SR_DDR_FB       :  std_logic;
-    SIGNAL	SR_DDR_WR       :  std_logic;
-    SIGNAL	SR_DDRWR_D_SEL  :  std_logic;
-    SIGNAL	SR_FIFO_WRE     :  std_logic;
-    SIGNAL	SR_VDMP         :  std_logic_vector(7 DOWNTO 0);
-    SIGNAL	ST_CLUT_RD      :  std_logic;
-    SIGNAL	ST_CLUT_WR      :  std_logic_vector(1 DOWNTO 0);
-    SIGNAL	VDM_SEL         :  std_logic_vector(3 DOWNTO 0);
-    SIGNAL	VDMA            :  std_logic_vector(127 DOWNTO 0);
-    SIGNAL	VDMB            :  std_logic_vector(127 DOWNTO 0);
-    SIGNAL	VDMC            :  std_logic_vector(127 DOWNTO 0);
-    SIGNAL	VDMP            :  std_logic_vector(7 DOWNTO 0);
-    SIGNAL	VDOUT_OE        :  std_logic;
-    SIGNAL	VDP_IN          :  std_logic_vector(63 DOWNTO 0);
-    SIGNAL	VDP_OUT         :  std_logic_vector(63 DOWNTO 0);
-    SIGNAL	VDR             :  std_logic_vector(31 DOWNTO 0);
-    SIGNAL	VDVZ            :  std_logic_vector(127 DOWNTO 0);
-    SIGNAL	VIDEO_DDR_TA    :  std_logic;
-    SIGNAL	VIDEO_MOD_TA    :  std_logic;
-    SIGNAL	VIDEO_RAM_CTR   :  std_logic_vector(15 DOWNTO 0);
-    SIGNAL	ZR_C8           :  std_logic_vector(7 DOWNTO 0);
-    SIGNAL	ZR_C8B          :  std_logic_vector(7 DOWNTO 0);
-    SIGNAL	SYNTHESIZED_WIRE_0 :  std_logic;
-    SIGNAL	SYNTHESIZED_WIRE_1 :  std_logic;
-    SIGNAL	SYNTHESIZED_WIRE_2 :  std_logic;
-    SIGNAL	SYNTHESIZED_WIRE_3 :  std_logic;
-    SIGNAL	SYNTHESIZED_WIRE_4 :  std_logic;
-    SIGNAL	SYNTHESIZED_WIRE_5 :  std_logic;
+    SIGNAL	ACP_CLUT_RD     : std_logic;
+    SIGNAL	ACP_CLUT_WR     : std_logic_vector(3 DOWNTO 0);
+    SIGNAL	BLITTER_ADR     : std_logic_vector(31 DOWNTO 0);
+    SIGNAL	BLITTER_DACK    : std_logic_vector(4 DOWNTO 0);
+    SIGNAL	BLITTER_DIN     : std_logic_vector(127 DOWNTO 0);
+    SIGNAL	BLITTER_DOUT    : std_logic_vector(127 DOWNTO 0);
+    SIGNAL	BLITTER_ON      : std_logic;
+    SIGNAL	BLITTER_RUN     : std_logic;
+    SIGNAL	BLITTER_SIG     : std_logic;
+    SIGNAL	BLITTER_TA      : std_logic;
+    SIGNAL	BLITTER_WR      : std_logic;
+    SIGNAL	BORDER_COLOR    : std_logic_vector(23 DOWNTO 0);
+    SIGNAL	CC16            : std_logic_vector(23 DOWNTO 0);
+    SIGNAL	CC24            : std_logic_vector(31 DOWNTO 0);
+    SIGNAL	CCA             : std_logic_vector(23 DOWNTO 0);
+    SIGNAL	CCF             : std_logic_vector(23 DOWNTO 0);
+    SIGNAL	CCS             : std_logic_vector(23 DOWNTO 0);
+    SIGNAL	CCSEL           : std_logic_vector(2 DOWNTO 0);
+    SIGNAL	CLR_FIFO        : std_logic;
+    SIGNAL	CLUT_ADR        : std_logic_vector(7 DOWNTO 0);
+    SIGNAL	CLUT_ADR1A      : std_logic;
+    SIGNAL	CLUT_ADR2A      : std_logic;
+    SIGNAL	CLUT_ADR3A      : std_logic;
+    SIGNAL	CLUT_ADR4A      : std_logic;
+    SIGNAL	CLUT_ADR5A      : std_logic;
+    SIGNAL	CLUT_ADR6A      : std_logic;
+    SIGNAL	CLUT_ADR7A      : std_logic;
+    SIGNAL	CLUT_MUX_ADR    : std_logic_vector(3 DOWNTO 0);
+    SIGNAL	CLUT_OFF        : std_logic_vector(3 DOWNTO 0);
+    SIGNAL	COLOR1          : std_logic;
+    SIGNAL	COLOR2          : std_logic;
+    SIGNAL	COLOR4          : std_logic;
+    SIGNAL	COLOR8          : std_logic;
+    SIGNAL	DDR_FB          : std_logic_vector(4 DOWNTO 0);
+    SIGNAL	DDR_WR          : std_logic;
+    SIGNAL	DDRWR_D_SEL     : std_logic_vector(1 DOWNTO 0);
+    SIGNAL	DOP_FIFO_CLR    : std_logic;
+    SIGNAL	FALCON_CLUT_RDH : std_logic;
+    SIGNAL	FALCON_CLUT_RDL : std_logic;
+    SIGNAL	FALCON_CLUT_WR  : std_logic_vector(3 DOWNTO 0);
+    SIGNAL	FB_DDR          : std_logic_vector(127 DOWNTO 0);
+    SIGNAL	FB_LE           : std_logic_vector(3 DOWNTO 0);
+    SIGNAL	FB_VDOE         : std_logic_vector(3 DOWNTO 0);
+    SIGNAL	FIFO_D          : std_logic_vector(127 DOWNTO 0);
+    SIGNAL	FIFO_MW         : std_logic_vector(8 DOWNTO 0);
+    SIGNAL	FIFO_RDE        : std_logic;
+    SIGNAL	FIFO_WRE        : std_logic;
+    SIGNAL	INTER_ZEI       : std_logic;
+    SIGNAL	nFB_BURST       : std_logic := '0';
+    SIGNAL	pixel_clk_i     : std_logic;
+    SIGNAL	SR_BLITTER_DACK : std_logic;
+    SIGNAL	SR_DDR_FB       : std_logic;
+    SIGNAL	SR_DDR_WR       : std_logic;
+    SIGNAL	SR_DDRWR_D_SEL  : std_logic;
+    SIGNAL	SR_FIFO_WRE     : std_logic;
+    SIGNAL	SR_VDMP         : std_logic_vector(7 DOWNTO 0);
+    SIGNAL	ST_CLUT_RD      : std_logic;
+    SIGNAL	ST_CLUT_WR      : std_logic_vector(1 DOWNTO 0);
+    SIGNAL	VDM_SEL         : std_logic_vector(3 DOWNTO 0);
+    SIGNAL	VDMA            : std_logic_vector(127 DOWNTO 0);
+    SIGNAL	VDMB            : std_logic_vector(127 DOWNTO 0);
+    SIGNAL	VDMC            : std_logic_vector(127 DOWNTO 0);
+    SIGNAL	VDMP            : std_logic_vector(7 DOWNTO 0);
+    SIGNAL	VDOUT_OE        : std_logic;
+    SIGNAL	VDP_IN          : std_logic_vector(63 DOWNTO 0);
+    SIGNAL	VDP_OUT         : std_logic_vector(63 DOWNTO 0);
+    SIGNAL	VDR             : std_logic_vector(31 DOWNTO 0);
+    SIGNAL	VDVZ            : std_logic_vector(127 DOWNTO 0);
+    SIGNAL	VIDEO_DDR_TA    : std_logic;
+    SIGNAL	VIDEO_MOD_TA    : std_logic;
+    SIGNAL	VIDEO_RAM_CTR   : std_logic_vector(15 DOWNTO 0);
+    SIGNAL	ZR_C8           : std_logic_vector(7 DOWNTO 0);
+    SIGNAL	ZR_C8B          : std_logic_vector(7 DOWNTO 0);
+    SIGNAL	SYNTHESIZED_WIRE_0 : std_logic;
+    SIGNAL	SYNTHESIZED_WIRE_1 : std_logic;
+    SIGNAL	SYNTHESIZED_WIRE_2 : std_logic;
+    SIGNAL	SYNTHESIZED_WIRE_3 : std_logic;
+    SIGNAL	SYNTHESIZED_WIRE_4 : std_logic;
+    SIGNAL	SYNTHESIZED_WIRE_5 : std_logic;
     SIGNAL	SYNTHESIZED_WIRE_60 :  std_logic;
-    SIGNAL	SYNTHESIZED_WIRE_7 :  std_logic_vector(15 DOWNTO 0);
-    SIGNAL	DFF_inst93      :  std_logic;
-    SIGNAL	SYNTHESIZED_WIRE_8 :  std_logic;
-    SIGNAL	SYNTHESIZED_WIRE_9 :  std_logic;
+    SIGNAL	SYNTHESIZED_WIRE_7 : std_logic_vector(15 DOWNTO 0);
+    SIGNAL	DFF_inst93      : std_logic;
+    SIGNAL	SYNTHESIZED_WIRE_8 : std_logic;
+    SIGNAL	SYNTHESIZED_WIRE_9 : std_logic;
     SIGNAL	SYNTHESIZED_WIRE_61 :  std_logic;
     SIGNAL	SYNTHESIZED_WIRE_11 :  std_logic_vector(31 DOWNTO 0);
     SIGNAL	SYNTHESIZED_WIRE_12 :  std_logic_vector(7 DOWNTO 0);
@@ -828,7 +280,7 @@ BEGIN
     GDFX_TEMP_SIGNAL_1 <= (VDMB(47 DOWNTO 0) & VDMA(127 DOWNTO 48));
     
     
-    ACP_CLUT_RAM : altdpram2
+    ACP_CLUT_RAM : entity work.altdpram2
         PORT MAP
         (
             wren_a => ACP_CLUT_WR(3),
@@ -844,7 +296,7 @@ BEGIN
         );
     
     
-    ACP_CLUT_RAM54 : altdpram2
+    ACP_CLUT_RAM54 : entity work.altdpram2
         PORT MAP
         (
             wren_a => ACP_CLUT_WR(2),
@@ -860,7 +312,7 @@ BEGIN
         );
     
     
-    ACP_CLUT_RAM55 : altdpram2
+    ACP_CLUT_RAM55 : entity work.altdpram2
         PORT MAP
         (
             wren_a => ACP_CLUT_WR(1),
@@ -876,7 +328,7 @@ BEGIN
         );
     
     
-    i_blitter : work.blitter
+    i_blitter : entity work.blitter
         PORT MAP
         (
             nRSTO => nRSTO,
@@ -900,13 +352,13 @@ BEGIN
             BLITTER_RUN => BLITTER_RUN,
             BLITTER_SIG => BLITTER_SIG,
             BLITTER_WR => BLITTER_WR,
-            BLITTER_TA => BLITTER_TA,
+            blitter_ta => blitter_ta,
             BLITTER_ADR => BLITTER_ADR,
             BLITTER_DOUT => BLITTER_DOUT
         );
     
     
-    i_ddr_ctr : ddr_ctr
+    i_ddr_ctr : entity work.ddr_ctr
         PORT MAP
         (
             nFB_CS1 => nFB_CS1,
@@ -951,7 +403,7 @@ BEGIN
         );
     
     
-    FALCON_CLUT_BLUE : altdpram1
+    FALCON_CLUT_BLUE : entity work.altdpram1
         PORT MAP
         (
             wren_a => FALCON_CLUT_WR(3),
@@ -967,7 +419,7 @@ BEGIN
         );
     
     
-    FALCON_CLUT_GREEN : altdpram1
+    FALCON_CLUT_GREEN : entity work.altdpram1
         PORT MAP
         (
             wren_a => FALCON_CLUT_WR(1),
@@ -983,7 +435,7 @@ BEGIN
         );
     
     
-    FALCON_CLUT_RED : altdpram1
+    FALCON_CLUT_RED : entity work.altdpram1
         PORT MAP
         (
             wren_a => FALCON_CLUT_WR(0),
@@ -999,7 +451,7 @@ BEGIN
         );
     
     
-    inst : lpm_fifo_dc0
+    inst : entity work.lpm_fifo_dc0
         PORT MAP
         (
             wrreq => FIFO_WRE,
@@ -1013,7 +465,7 @@ BEGIN
         );
     
     
-    inst1 : altddio_bidir0
+    inst1 : entity work.altddio_bidir0
         PORT MAP
         (
             oe => VDOUT_OE,
@@ -1028,7 +480,7 @@ BEGIN
         );
     
     
-    inst10 : lpm_ff4
+    inst10 : entity work.lpm_ff4
         PORT MAP
         (
             clock => pixel_clk_i,
@@ -1037,7 +489,7 @@ BEGIN
         );
     
     
-    inst100 : lpm_muxvdm
+    inst100 : entity work.lpm_muxvdm
         PORT MAP
         (
             data0x => VDMB,
@@ -1061,7 +513,7 @@ BEGIN
         );
     
     
-    inst102 : lpm_mux3
+    inst102 : entity work.lpm_mux3
         PORT MAP
         (
             data1 => DFF_inst93,
@@ -1080,7 +532,7 @@ BEGIN
     SYNTHESIZED_WIRE_16 <= COLOR4 OR COLOR8 OR COLOR2;
     
     
-    inst108 : lpm_bustri_long
+    inst108 : entity work.lpm_bustri_long
         PORT MAP
         (
             enabledt => FB_VDOE(0),
@@ -1089,7 +541,7 @@ BEGIN
         );
     
     
-    inst109 : lpm_bustri_long
+    inst109 : entity work.lpm_bustri_long
         PORT MAP
         (
             enabledt => FB_VDOE(1),
@@ -1098,7 +550,7 @@ BEGIN
         );
     
     
-    inst11 : lpm_ff5
+    inst11 : entity work.lpm_ff5
         PORT MAP
         (
             clock => pixel_clk_i,
@@ -1107,7 +559,7 @@ BEGIN
         );
     
     
-    inst110 : lpm_bustri_long
+    inst110 : entity work.lpm_bustri_long
         PORT MAP
         (
             enabledt => FB_VDOE(2),
@@ -1116,7 +568,7 @@ BEGIN
         );
     
     
-    inst119 : lpm_bustri_long
+    inst119 : entity work.lpm_bustri_long
         PORT MAP
         (
             enabledt => FB_VDOE(3),
@@ -1125,7 +577,7 @@ BEGIN
         );
     
     
-    inst12 : lpm_ff1
+    inst12 : entity work.lpm_ff1
         PORT MAP
         (
             clock => DDRCLK(0),
@@ -1134,7 +586,7 @@ BEGIN
         );
     
     
-    inst13 : lpm_ff0
+    inst13 : entity work.lpm_ff0
         PORT MAP
         (
             clock => DDR_SYNC_66M,
@@ -1144,7 +596,7 @@ BEGIN
         );
     
     
-    inst14 : lpm_ff0
+    inst14 : entity work.lpm_ff0
         PORT MAP
         (
             clock => DDR_SYNC_66M,
@@ -1154,7 +606,7 @@ BEGIN
         );
     
     
-    inst15 : lpm_ff0
+    inst15 : entity work.lpm_ff0
         PORT MAP
         (
             clock => DDR_SYNC_66M,
@@ -1164,7 +616,7 @@ BEGIN
         );
     
     
-    inst16 : lpm_ff0
+    inst16 : entity work.lpm_ff0
         PORT MAP
         (
             clock => DDR_SYNC_66M,
@@ -1174,7 +626,7 @@ BEGIN
         );
     
     
-    inst17 : lpm_ff0
+    inst17 : entity work.lpm_ff0
         PORT MAP
         (
             clock => DDRCLK(0),
@@ -1184,7 +636,7 @@ BEGIN
         );
     
     
-    inst18 : lpm_ff0
+    inst18 : entity work.lpm_ff0
         PORT MAP
         (
             clock => DDRCLK(0),
@@ -1194,7 +646,7 @@ BEGIN
         );
     
     
-    inst19 : lpm_ff0
+    inst19 : entity work.lpm_ff0
         PORT MAP
         (
             clock => DDRCLK(0),
@@ -1204,7 +656,7 @@ BEGIN
         );
     
     
-    inst2 : altddio_out0
+    inst2 : entity work.altddio_out0
         PORT MAP
         (
             outclock => DDRCLK(3),
@@ -1214,7 +666,7 @@ BEGIN
         );
     
     
-    inst20 : lpm_ff1
+    inst20 : entity work.lpm_ff1
         PORT MAP
         (
             clock => DDRCLK(0),
@@ -1223,7 +675,7 @@ BEGIN
         );
     
     
-    inst21 : lpm_mux0
+    inst21 : entity work.lpm_mux0
         PORT MAP
         (
             clock => pixel_clk_i,
@@ -1236,7 +688,7 @@ BEGIN
         );
     
     
-    inst22 : lpm_mux5
+    inst22 : entity work.lpm_mux5
         PORT MAP
         (
             data0x => FB_DDR(127 DOWNTO 64),
@@ -1248,14 +700,14 @@ BEGIN
         );
     
     
-    inst23 : lpm_constant2
+    inst23 : entity work.lpm_constant2
         PORT MAP
         (
             result => GDFX_TEMP_SIGNAL_16
         );
     
     
-    inst24 : lpm_mux1
+    inst24 : entity work.lpm_mux1
         PORT MAP
         (
             clock => pixel_clk_i,
@@ -1272,7 +724,7 @@ BEGIN
         );
     
     
-    inst25 : lpm_mux2
+    inst25 : entity work.lpm_mux2
         PORT MAP
         (
             clock => pixel_clk_i,
@@ -1297,7 +749,7 @@ BEGIN
         );
     
     
-    inst26 : lpm_shiftreg4
+    inst26 : entity work.lpm_shiftreg4
         PORT MAP
         (
             clock => DDRCLK(0),
@@ -1306,7 +758,7 @@ BEGIN
         );
     
     
-    inst27 : lpm_latch0
+    inst27 : entity work.lpm_latch0
         PORT MAP
         (
             gate => DDR_SYNC_66M,
@@ -1317,7 +769,7 @@ BEGIN
     CLUT_ADR(1) <= CLUT_ADR1A AND SYNTHESIZED_WIRE_16;
     
     
-    inst3 : lpm_ff1
+    inst3 : entity work.lpm_ff1
         PORT MAP
         (
             clock => DDRCLK(0),
@@ -1332,7 +784,7 @@ BEGIN
     SYNTHESIZED_WIRE_9 <= CLUT_ADR6A AND COLOR8;
     SYNTHESIZED_WIRE_46 <= CLUT_ADR7A AND COLOR8;
       
-    inst36 : lpm_ff6
+    inst36 : entity work.lpm_ff6
         PORT MAP
         (
             clock => DDRCLK(0),
@@ -1342,9 +794,9 @@ BEGIN
         );
     
     VDOUT_OE <= DDR_WR OR SR_DDR_WR;
-    VIDEO_TA <= BLITTER_TA OR VIDEO_MOD_TA OR VIDEO_DDR_TA;
+    video_ta <= blitter_ta or video_mod_ta or video_ddr_ta;
     
-    inst4 : lpm_ff1
+    inst4 : entity work.lpm_ff1
         PORT MAP
         (
             clock => DDRCLK(0),
@@ -1353,7 +805,7 @@ BEGIN
         );
     
     
-    inst40 : mux41_0
+    inst40 : entity work.mux41_0
         PORT MAP
         (
             S0 => COLOR2,
@@ -1365,7 +817,7 @@ BEGIN
         );
     
     
-    inst41 : mux41_1
+    inst41 : entity work.mux41_1
         PORT MAP
         (
             S0 => COLOR2,
@@ -1377,7 +829,7 @@ BEGIN
         );
     
     
-    inst42 : mux41_2
+    inst42 : entity work.mux41_2
         PORT MAP
         (
             S0 => COLOR2,
@@ -1390,7 +842,7 @@ BEGIN
         );
     
     
-    inst43 : mux41_3
+    inst43 : entity work.mux41_3
         PORT MAP
         (
             S0 => COLOR2,
@@ -1403,7 +855,7 @@ BEGIN
         );
     
     
-    inst44 : mux41_4
+    inst44 : entity work.mux41_4
         PORT MAP
         (
             S0 => COLOR2,
@@ -1416,7 +868,7 @@ BEGIN
         );
     
     
-    inst45 : mux41_5
+    inst45 : entity work.mux41_5
         PORT MAP
         (
             S0 => COLOR2,
@@ -1429,7 +881,7 @@ BEGIN
         );
     
     
-    inst46 : lpm_ff3
+    inst46 : entity work.lpm_ff3
         PORT MAP
         (
             clock => pixel_clk_i,
@@ -1438,7 +890,7 @@ BEGIN
         );
     
     
-    inst47 : lpm_ff3
+    inst47 : entity work.lpm_ff3
         PORT MAP
         (
             clock => pixel_clk_i,
@@ -1448,7 +900,7 @@ BEGIN
     
     
     
-    inst49 : lpm_ff3
+    inst49 : entity work.lpm_ff3
         PORT MAP
         (
             clock => pixel_clk_i,
@@ -1457,7 +909,7 @@ BEGIN
         );
     
     
-    inst5 : altddio_out2
+    inst5 : entity work.altddio_out2
         PORT MAP
         (
             outclock => pixel_clk_i,
@@ -1468,7 +920,7 @@ BEGIN
     
     
     
-    inst51 : lpm_bustri1
+    inst51 : entity work.lpm_bustri1
         PORT MAP
         (
             enabledt => ST_CLUT_RD,
@@ -1477,7 +929,7 @@ BEGIN
         );
     
     
-    inst52 : lpm_ff3
+    inst52 : entity work.lpm_ff3
         PORT MAP
         (
             clock => pixel_clk_i,
@@ -1486,7 +938,7 @@ BEGIN
         );
     
     
-    inst53 : lpm_bustri_byt
+    inst53 : entity work.lpm_bustri_byt
         PORT MAP
         (
             enabledt => ACP_CLUT_RD,
@@ -1495,7 +947,7 @@ BEGIN
         );
     
     
-    inst54 : lpm_constant0
+    inst54 : entity work.lpm_constant0
         PORT MAP
         (
             result => CCS(20 DOWNTO 16)
@@ -1503,7 +955,7 @@ BEGIN
     
     
     
-    inst56 : lpm_bustri1
+    inst56 : entity work.lpm_bustri1
         PORT MAP
         (
             enabledt => ST_CLUT_RD,
@@ -1512,7 +964,7 @@ BEGIN
         );
     
     
-    inst57 : lpm_bustri_byt
+    inst57 : entity work.lpm_bustri_byt
         PORT MAP
         (
             enabledt => ACP_CLUT_RD,
@@ -1521,7 +973,7 @@ BEGIN
         );
     
     
-    inst58 : lpm_bustri_byt
+    inst58 : entity work.lpm_bustri_byt
         PORT MAP
         (
             enabledt => ACP_CLUT_RD,
@@ -1530,7 +982,7 @@ BEGIN
         );
     
     
-    inst59 : lpm_constant0
+    inst59 : entity work.lpm_constant0
         PORT MAP
         (
             result => CCS(12 DOWNTO 8)
@@ -1539,7 +991,7 @@ BEGIN
     
     
     
-    inst61 : lpm_bustri1
+    inst61 : entity work.lpm_bustri1
         PORT MAP
         (
             enabledt => ST_CLUT_RD,
@@ -1548,7 +1000,7 @@ BEGIN
         );
     
     
-    inst62 : lpm_muxdz
+    inst62 : entity work.lpm_muxdz
         PORT MAP
         (
             clock => pixel_clk_i,
@@ -1560,7 +1012,7 @@ BEGIN
         );
     
     
-    inst63 : lpm_fifodz
+    inst63 : entity work.lpm_fifodz
         PORT MAP
         (
             wrreq => SYNTHESIZED_WIRE_60,
@@ -1572,7 +1024,7 @@ BEGIN
         );
     
     
-    inst64 : lpm_constant0
+    inst64 : entity work.lpm_constant0
         PORT MAP
         (
             result => CCS(4 DOWNTO 0)
@@ -1582,7 +1034,7 @@ BEGIN
     SYNTHESIZED_WIRE_60 <= FIFO_RDE AND SYNTHESIZED_WIRE_40;
     
     
-    inst66 : lpm_bustri3
+    inst66 : entity work.lpm_bustri3
         PORT MAP
         (
             enabledt => FALCON_CLUT_RDH,
@@ -1594,7 +1046,7 @@ BEGIN
     SYNTHESIZED_WIRE_38 <= FIFO_RDE AND INTER_ZEI;
     SYNTHESIZED_WIRE_40 <= NOT(INTER_ZEI);
     
-    inst7 : lpm_mux6
+    inst7 : entity work.lpm_mux6
         PORT MAP
         (
             clock => pixel_clk_i,
@@ -1611,7 +1063,7 @@ BEGIN
         );
     
     
-    inst70 : lpm_bustri3
+    inst70 : entity work.lpm_bustri3
         PORT MAP
         (
             enabledt => FALCON_CLUT_RDH,
@@ -1620,7 +1072,7 @@ BEGIN
         );
     
     
-    inst71 : lpm_ff6
+    inst71 : entity work.lpm_ff6
         PORT MAP
         (
             clock => DDRCLK(0),
@@ -1632,7 +1084,7 @@ BEGIN
     
     
     
-    inst74 : lpm_bustri3
+    inst74 : entity work.lpm_bustri3
         PORT MAP
         (
             enabledt => FALCON_CLUT_RDL,
@@ -1643,7 +1095,7 @@ BEGIN
     
     
     
-    inst77 : lpm_constant1
+    inst77 : entity work.lpm_constant1
         PORT MAP
         (
             result => CCF(1 DOWNTO 0)
@@ -1655,14 +1107,14 @@ BEGIN
     
     
     
-    inst80 : lpm_constant1
+    inst80 : entity work.lpm_constant1
         PORT MAP
         (
             result => CCF(9 DOWNTO 8)
         );
     
     
-    inst81 : lpm_mux4
+    inst81 : entity work.lpm_mux4
         PORT MAP
         (
             sel => COLOR1,
@@ -1672,14 +1124,14 @@ BEGIN
         );
     
     
-    inst82 : lpm_constant3
+    inst82 : entity work.lpm_constant3
         PORT MAP
         (
             result => SYNTHESIZED_WIRE_47
         );
     
     
-    inst83 : lpm_constant1
+    inst83 : entity work.lpm_constant1
         PORT MAP
         (
             result => CCF(17 DOWNTO 16)
@@ -1705,7 +1157,7 @@ BEGIN
     END PROCESS;
     
     
-    inst89 : lpm_shiftreg6
+    inst89 : entity work.lpm_shiftreg6
         PORT MAP
         (
             clock => DDRCLK(0),
@@ -1714,7 +1166,7 @@ BEGIN
         );
     
     
-    inst9 : lpm_ff1
+    inst9 : entity work.lpm_ff1
         PORT MAP
         (
             clock => pixel_clk_i,
@@ -1731,7 +1183,7 @@ BEGIN
     END PROCESS;
     
     
-    inst92 : lpm_shiftreg6
+    inst92 : entity work.lpm_shiftreg6
         PORT MAP
         (
             clock => DDRCLK(0),
@@ -1748,7 +1200,7 @@ BEGIN
     END PROCESS;
     
     
-    inst94 : lpm_ff6
+    inst94 : entity work.lpm_ff6
         PORT MAP
         (
             clock => DDRCLK(0),
@@ -1767,7 +1219,7 @@ BEGIN
     
     
     
-    inst97 : lpm_ff5
+    inst97 : entity work.lpm_ff5
         PORT MAP
         (
             clock => DDRCLK(2),
@@ -1776,7 +1228,7 @@ BEGIN
         );
     
     
-    sr0 : lpm_shiftreg0
+    sr0 : entity work.lpm_shiftreg0
         PORT MAP
         (
             load => SYNTHESIZED_WIRE_64,
@@ -1787,7 +1239,7 @@ BEGIN
         );
     
     
-    sr1 : lpm_shiftreg0
+    sr1 : entity work.lpm_shiftreg0
         PORT MAP
         (
             load => SYNTHESIZED_WIRE_64,
@@ -1798,7 +1250,7 @@ BEGIN
         );
     
     
-    sr2 : lpm_shiftreg0
+    sr2 : entity work.lpm_shiftreg0
         PORT MAP
         (
             load => SYNTHESIZED_WIRE_64,
@@ -1809,7 +1261,7 @@ BEGIN
         );
     
     
-    sr3 : lpm_shiftreg0
+    sr3 : entity work.lpm_shiftreg0
         PORT MAP
         (
             load => SYNTHESIZED_WIRE_64,
@@ -1820,7 +1272,7 @@ BEGIN
         );
     
     
-    sr4 : lpm_shiftreg0
+    sr4 : entity work.lpm_shiftreg0
         PORT MAP
         (
             load => SYNTHESIZED_WIRE_64,
@@ -1831,7 +1283,7 @@ BEGIN
         );
     
     
-    sr5 : lpm_shiftreg0
+    sr5 : entity work.lpm_shiftreg0
         PORT MAP
         (
             load => SYNTHESIZED_WIRE_64,
@@ -1842,7 +1294,7 @@ BEGIN
         );
     
     
-    sr6 : lpm_shiftreg0
+    sr6 : entity work.lpm_shiftreg0
         PORT MAP
         (
             load => SYNTHESIZED_WIRE_64,
@@ -1853,7 +1305,7 @@ BEGIN
         );
     
     
-    sr7 : lpm_shiftreg0
+    sr7 : entity work.lpm_shiftreg0
         PORT MAP
         (
             load => SYNTHESIZED_WIRE_64,
@@ -1864,7 +1316,7 @@ BEGIN
         );
     
     
-    ST_CLUT_BLUE : altdpram0
+    ST_CLUT_BLUE : entity work.altdpram0
         PORT MAP
         (
             wren_a => ST_CLUT_WR(1),
@@ -1880,7 +1332,7 @@ BEGIN
         );
     
     
-    ST_CLUT_GREEN : altdpram0
+    ST_CLUT_GREEN : entity work.altdpram0
         PORT MAP
         (
             wren_a => ST_CLUT_WR(1),
@@ -1896,7 +1348,7 @@ BEGIN
         );
     
     
-    ST_CLUT_RED : altdpram0
+    ST_CLUT_RED : entity work.altdpram0
         PORT MAP
         (
             wren_a => ST_CLUT_WR(0),
@@ -1912,7 +1364,7 @@ BEGIN
         );
     
     
-    i_video_mod_mux_clutctr : work.video_mod_mux_clutctr
+    i_video_mod_mux_clutctr : entity work.video_mod_mux_clutctr
         PORT MAP
         (
             nRSTO => nRSTO,
diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
index 56110e5..1a1993d 100755
--- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
+++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd
@@ -116,7 +116,7 @@ end video_mod_mux_clutctr;
 architecture rtl of video_mod_mux_clutctr is
     --  DIV. CONTROL REGISTER
     --  BRAUCHT EIN WAITSTAT
-    --  LÄNGE HSYNC PULS IN PIXEL_CLK
+    --  LÄNGE HSYNC PULS IN PIXEL_CLK
     --  LETZTES PIXEL EINER ZEILE ERREICHT
     --  ATARI RESOLUTION
     --  HORIZONTAL TIMING 640x480
@@ -971,7 +971,8 @@ begin
     --  ST SHIFT MODE
 
     --  $F8260/2
-    ST_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110000");
+    st_shift_mode_cs <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = 19x"7c130" else '0';
+    -- ST_SHIFT_MODE_CS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 downto 1) = "1111100000100110000");
     ST_SHIFT_MODE_d <= FB_AD(25 downto 24);
     ST_SHIFT_MODE0_ena_ctrl <= ST_SHIFT_MODE_CS and (not nFB_WR) and FB_B(0);
 
@@ -1027,7 +1028,7 @@ begin
     nPD_VGA <= ACP_VCTR_q(1);
 
     --  ATARI MODUS
-    --  WENN 1 AUTOMATISCHE AUFLÖSUNG
+    --  WENN 1 AUTOMATISCHE AUFLÖSUNG
     ATARI_SYNC <= ACP_VCTR_q(26);
 
     --  HORIZONTAL TIMING 640x480
@@ -1310,7 +1311,7 @@ begin
     u1_enabledt <= (ACP_VCTR_CS or BORDER_COLOR_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS) and (not nFB_OE);
     FB_AD(15 downto 0) <= u1_tridata;
 
-    VIDEO_MOD_TA <= CLUT_TA_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or
+    video_mod_ta <= clut_ta_q or ST_SHIFT_MODE_CS or FALCON_SHIFT_MODE_CS or ACP_VCTR_CS or SYS_CTR_CS or LOF_CS or LWD_CS or HBE_CS or HDB_CS or
                     HDE_CS or HBB_CS or HSS_CS or HHT_CS or ATARI_HH_CS or ATARI_VH_CS or ATARI_HL_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or
                     VSS_CS or VFT_CS or VCO_CS or VCNTRL_CS;
 
@@ -1331,7 +1332,7 @@ begin
                  (CLK_VIDEO and ACP_VIDEO_ON and ACP_VCTR_q(9));
 
     -- ------------------------------------------------------------
-    --  HORIZONTALE SYNC LÄNGE in PIXEL_CLK
+    --  HORIZONTALE SYNC LÄNGE in PIXEL_CLK
     -- --------------------------------------------------------------
 
     --  320 pixels, 32 MHz, RGB
@@ -1378,7 +1379,7 @@ begin
 	 VVCNT_q(0) = VDIS_START(0) and VVCNT_q /= "00000000000" and
 	 (unsigned(VHCNT_q) > unsigned(std_logic_vector(unsigned(HDIS_END) - 2)))));
 
---  DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
+--  DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
    DOP_FIFO_CLR_d <= (INTER_ZEI_q and HSYNC_START_q) or SYNC_PIX_q;
 
 --    RAND_LINKS[]    =  HBE[]                                    &  ACP_VIDEO_ON
@@ -1457,7 +1458,7 @@ begin
 	 VCNTRL_q(2),11)) or (std_logic_vector'('0' & VFT_q(10 downto 1)) and
 	 sizeIt(not ACP_VIDEO_ON,11) and sizeIt(not ATARI_SYNC,11));
 
-    --  ZÄHLER
+    --  ZÄHLER
     LAST_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(H_TOTAL) - 2)));
 
     VHCNT_d <= (std_logic_vector(unsigned(VHCNT_q) + 1)) and sizeIt(not LAST_q,12);
@@ -1469,7 +1470,7 @@ begin
     --  1 ZEILE DAVOR ON OFF
     DPO_ZL_d <= to_std_logic((unsigned(VVCNT_q) > unsigned(std_logic_vector(unsigned(RAND_OBEN) - 1))) and (unsigned(VVCNT_q) < unsigned(std_logic_vector(unsigned(RAND_UNTEN) - 1))));
 
-    --  AM ZEILENENDE ÜBERNEHMEN
+    --  AM ZEILENENDE ÃœBERNEHMEN
     DPO_ZL_ena <= LAST_q;
 
     --  BESSER EINZELN WEGEN TIMING
@@ -1485,7 +1486,7 @@ begin
     VCO_OFF_d <= to_std_logic(VHCNT_q = HDIS_END);
 
     
-    --  AM ZEILENENDE ÜBERNEHMEN
+    --  AM ZEILENENDE ÃœBERNEHMEN
     VCO_ZL_ena <= LAST_q;
 
     --  1 ZEILE DAVOR ON OFF
@@ -1493,7 +1494,7 @@ begin
 
     VDTRON_d <= (VDTRON_q and (not VCO_OFF_q)) or (VCO_ON_q and VCO_ZL_q);
 
-    --  VERZÖGERUNG UND SYNC
+    --  VERZÖGERUNG UND SYNC
 
     HSYNC_START_d <= to_std_logic(VHCNT_q = (std_logic_vector(unsigned(HS_START) - 3)));
 
@@ -1511,7 +1512,7 @@ begin
     VSYNC_I0_ena_ctrl <= LAST_q;
 
     --  3 zeilen vsync length
-    --  runterzählen bis 0
+    --  runterzählen bis 0
     VSYNC_I_d <= 3x"3" when VSYNC_START_q = '1' else
                  std_logic_vector(unsigned(VSYNC_I_q) - 1) when VSYNC_START_q = '0' and VSYNC_I_q /= x"0" else
                  (others => '0');
@@ -1531,12 +1532,12 @@ begin
     VERZ0_d(0) <= DISP_ON_q;
 
     --   VERZ[1][0] = HSYNC_I[] != 0;
-    --  NUR MÖGLICH WENN BEIDE
+    --  NUR MÖGLICH WENN BEIDE
     VERZ1_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1')
 	 and HSYNC_I_q /= "00000000")) or (to_std_logic((ACP_VCTR_q(15) and
 	 VCO_q(6))='1' and HSYNC_I_q = "00000000"));
 
-    --  NUR MÖGLICH WENN BEIDE
+    --  NUR MÖGLICH WENN BEIDE
     VERZ2_d(0) <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1')
 	 and VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and
 	 VCO_q(5))='1' and VSYNC_I_q = "000"));
@@ -1547,13 +1548,13 @@ begin
     --  nBLANK_d <= DISP_ON_q;
 
     --  HSYNC  =  VERZ[1][9];
-    --  NUR MÖGLICH WENN BEIDE
+    --  NUR MÖGLICH WENN BEIDE
     HSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(6)))='1') and
 	 HSYNC_I_q /= "00000000")) or (to_std_logic((ACP_VCTR_q(15) and
 	 VCO_q(6))='1' and HSYNC_I_q = "00000000"));
 
     --  VSYNC  =  VERZ[2][9];
-    --  NUR MÖGLICH WENN BEIDE
+    --  NUR MÖGLICH WENN BEIDE
     VSYNC_d <= (to_std_logic((((not ACP_VCTR_q(15)) or (not VCO_q(5)))='1') and
 	 VSYNC_I_q /= "000")) or (to_std_logic((ACP_VCTR_q(15) and
 	 VCO_q(5))='1' and VSYNC_I_q = "000"));
@@ -1575,20 +1576,20 @@ begin
     -- --------------------------------------------------------
     CLR_FIFO_ena <= LAST_q;
 
-    --  IN LETZTER ZEILE LÖSCHEN
+    --  IN LETZTER ZEILE LÖSCHEN
     CLR_FIFO_d <= to_std_logic(VVCNT_q = (std_logic_vector(unsigned(V_TOTAL) - 2)));
     START_ZEILE_ena <= LAST_q;
 
     --  ZEILE 1
     START_ZEILE_d <= to_std_logic(VVCNT_q = "00000000000");
 
-    --  SUB PIXEL ZÄHLER SYNCHRONISIEREN
+    --  SUB PIXEL ZÄHLER SYNCHRONISIEREN
     SYNC_PIX_d <= to_std_logic(VHCNT_q = "000000000011") and START_ZEILE_q;
 
-    --  SUB PIXEL ZÄHLER SYNCHRONISIEREN
+    --  SUB PIXEL ZÄHLER SYNCHRONISIEREN
     SYNC_PIX1_d <= to_std_logic(VHCNT_q = "000000000101") and START_ZEILE_q;
 
-    --  SUB PIXEL ZÄHLER SYNCHRONISIEREN
+    --  SUB PIXEL ZÄHLER SYNCHRONISIEREN
     SYNC_PIX2_d <= to_std_logic(VHCNT_q = "000000000111") and START_ZEILE_q;
 
     SUB_PIXEL_CNT0_ena_ctrl <= VDTRON_q or SYNC_PIX_q;
@@ -1596,7 +1597,7 @@ begin
     -- count up if display on sonst clear bei sync pix
     SUB_PIXEL_CNT_d <= (std_logic_vector(unsigned(SUB_PIXEL_CNT_q) + 1)) and sizeIt(not SYNC_PIX_q,7);
 
-    --  3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
+    --  3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
     FIFO_RDE_d <= (((to_std_logic(SUB_PIXEL_CNT_q = "0000001") and COLOR1) or
 	 (to_std_logic(SUB_PIXEL_CNT_q(5 downto 0) = "000001") and COLOR2) or
 	 (to_std_logic(SUB_PIXEL_CNT_q(4 downto 0) = "00001") and color4_i) or
diff --git a/FPGA_Quartus_13.1/firebee1.qsf b/FPGA_Quartus_13.1/firebee1.qsf
index f42b241..78a9acc 100644
--- a/FPGA_Quartus_13.1/firebee1.qsf
+++ b/FPGA_Quartus_13.1/firebee1.qsf
@@ -39,389 +39,389 @@
 
 # Project-Wide Assignments
 # ========================
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29  SEPTEMBER 03, 2009"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29  SEPTEMBER 03, 2009"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
 
 # Pin & Location Assignments
 # ==========================
-set_location_assignment PIN_G2 -to MAIN_CLK
-set_location_assignment PIN_Y3 -to FB_AD[0]
-set_location_assignment PIN_Y6 -to FB_AD[1]
-set_location_assignment PIN_AA3 -to FB_AD[2]
-set_location_assignment PIN_AB3 -to FB_AD[3]
-set_location_assignment PIN_W6 -to FB_AD[4]
-set_location_assignment PIN_V7 -to FB_AD[5]
-set_location_assignment PIN_AA4 -to FB_AD[6]
-set_location_assignment PIN_AB4 -to FB_AD[7]
-set_location_assignment PIN_AA5 -to FB_AD[8]
-set_location_assignment PIN_AB5 -to FB_AD[9]
-set_location_assignment PIN_W7 -to FB_AD[10]
-set_location_assignment PIN_Y7 -to FB_AD[11]
-set_location_assignment PIN_U9 -to FB_AD[12]
-set_location_assignment PIN_V8 -to FB_AD[13]
-set_location_assignment PIN_W8 -to FB_AD[14]
-set_location_assignment PIN_AA7 -to FB_AD[15]
-set_location_assignment PIN_AB7 -to FB_AD[16]
-set_location_assignment PIN_Y8 -to FB_AD[17]
-set_location_assignment PIN_V9 -to FB_AD[18]
-set_location_assignment PIN_V10 -to FB_AD[19]
-set_location_assignment PIN_T10 -to FB_AD[20]
-set_location_assignment PIN_U10 -to FB_AD[21]
-set_location_assignment PIN_AA8 -to FB_AD[22]
-set_location_assignment PIN_AB8 -to FB_AD[23]
-set_location_assignment PIN_T11 -to FB_AD[24]
-set_location_assignment PIN_AA9 -to FB_AD[25]
-set_location_assignment PIN_AB9 -to FB_AD[26]
-set_location_assignment PIN_U11 -to FB_AD[27]
-set_location_assignment PIN_V11 -to FB_AD[28]
-set_location_assignment PIN_W10 -to FB_AD[29]
-set_location_assignment PIN_Y10 -to FB_AD[30]
-set_location_assignment PIN_AA10 -to FB_AD[31]
-set_location_assignment PIN_R7 -to FB_ALE
-set_location_assignment PIN_N19 -to LED_FPGA_OK
-set_location_assignment PIN_AB10 -to CLK24M576
-set_location_assignment PIN_J1 -to CLKUSB
-set_location_assignment PIN_T4 -to CLK25M
-set_location_assignment PIN_U8 -to FB_SIZE0
-set_location_assignment PIN_Y4 -to FB_SIZE1
-set_location_assignment PIN_T3 -to nFB_BURST
-set_location_assignment PIN_T8 -to nFB_CS1
-set_location_assignment PIN_T9 -to nFB_CS2
-set_location_assignment PIN_V6 -to nFB_CS3
-set_location_assignment PIN_R6 -to nFB_OE
-set_location_assignment PIN_T5 -to nFB_WR
-set_location_assignment PIN_R5 -to TIN0
-set_location_assignment PIN_T21 -to nMASTER
-set_location_assignment PIN_E11 -to nDREQ1
-set_location_assignment PIN_A12 -to nDACK1
-set_location_assignment PIN_B12 -to nDACK0
-set_location_assignment PIN_T22 -to TOUT0
-set_location_assignment PIN_AB17 -to DDR_CLK
-set_location_assignment PIN_AA17 -to nDDR_CLK
-set_location_assignment PIN_AB18 -to nVCAS
-set_location_assignment PIN_T18 -to nVCS
-set_location_assignment PIN_W17 -to nVRAS
-set_location_assignment PIN_Y17 -to nVWE
-set_location_assignment PIN_W20 -to VA[0]
-set_location_assignment PIN_W22 -to VA[1]
-set_location_assignment PIN_W21 -to VA[2]
-set_location_assignment PIN_Y22 -to VA[3]
-set_location_assignment PIN_AA22 -to VA[4]
-set_location_assignment PIN_Y21 -to VA[5]
-set_location_assignment PIN_AA21 -to VA[6]
-set_location_assignment PIN_AA20 -to VA[7]
-set_location_assignment PIN_AB20 -to VA[8]
-set_location_assignment PIN_AB19 -to VA[9]
-set_location_assignment PIN_V21 -to VA[10]
-set_location_assignment PIN_U19 -to VA[11]
-set_location_assignment PIN_AA18 -to VA[12]
-set_location_assignment PIN_U15 -to VCKE
-set_location_assignment PIN_M22 -to VD[0]
-set_location_assignment PIN_M21 -to VD[1]
-set_location_assignment PIN_P22 -to VD[2]
-set_location_assignment PIN_R20 -to VD[3]
-set_location_assignment PIN_P21 -to VD[4]
-set_location_assignment PIN_R17 -to VD[5]
-set_location_assignment PIN_R19 -to VD[6]
-set_location_assignment PIN_U21 -to VD[7]
-set_location_assignment PIN_V22 -to VD[8]
-set_location_assignment PIN_R18 -to VD[9]
-set_location_assignment PIN_P17 -to VD[10]
-set_location_assignment PIN_R21 -to VD[11]
-set_location_assignment PIN_N17 -to VD[12]
-set_location_assignment PIN_P20 -to VD[13]
-set_location_assignment PIN_R22 -to VD[14]
-set_location_assignment PIN_N20 -to VD[15]
-set_location_assignment PIN_T12 -to VD[16]
-set_location_assignment PIN_Y13 -to VD[17]
-set_location_assignment PIN_AA13 -to VD[18]
-set_location_assignment PIN_V14 -to VD[19]
-set_location_assignment PIN_U13 -to VD[20]
-set_location_assignment PIN_V15 -to VD[21]
-set_location_assignment PIN_W14 -to VD[22]
-set_location_assignment PIN_AB16 -to VD[23]
-set_location_assignment PIN_AB15 -to VD[24]
-set_location_assignment PIN_AA14 -to VD[25]
-set_location_assignment PIN_AB14 -to VD[26]
-set_location_assignment PIN_V13 -to VD[27]
-set_location_assignment PIN_W13 -to VD[28]
-set_location_assignment PIN_AB13 -to VD[29]
-set_location_assignment PIN_V12 -to VD[30]
-set_location_assignment PIN_U12 -to VD[31]
-set_location_assignment PIN_AA16 -to VDM[0]
-set_location_assignment PIN_V16 -to VDM[1]
-set_location_assignment PIN_U20 -to VDM[2]
-set_location_assignment PIN_T17 -to VDM[3]
-set_location_assignment PIN_AA15 -to VDQS[0]
-set_location_assignment PIN_W15 -to VDQS[1]
-set_location_assignment PIN_U22 -to VDQS[2]
-set_location_assignment PIN_T16 -to VDQS[3]
-set_location_assignment PIN_V1 -to nPD_VGA
-set_location_assignment PIN_G18 -to VB[0]
-set_location_assignment PIN_H17 -to VB[1]
-set_location_assignment PIN_C22 -to VB[2]
-set_location_assignment PIN_C21 -to VB[3]
-set_location_assignment PIN_B22 -to VB[4]
-set_location_assignment PIN_B21 -to VB[5]
-set_location_assignment PIN_C20 -to VB[6]
-set_location_assignment PIN_D20 -to VB[7]
-set_location_assignment PIN_H19 -to VG[0]
-set_location_assignment PIN_E22 -to VG[1]
-set_location_assignment PIN_E21 -to VG[2]
-set_location_assignment PIN_H18 -to VG[3]
-set_location_assignment PIN_J17 -to VG[4]
-set_location_assignment PIN_H16 -to VG[5]
-set_location_assignment PIN_D22 -to VG[6]
-set_location_assignment PIN_D21 -to VG[7]
-set_location_assignment PIN_J22 -to VR[0]
-set_location_assignment PIN_J21 -to VR[1]
-set_location_assignment PIN_H22 -to VR[2]
-set_location_assignment PIN_H21 -to VR[3]
-set_location_assignment PIN_K17 -to VR[4]
-set_location_assignment PIN_K18 -to VR[5]
-set_location_assignment PIN_J18 -to VR[6]
-set_location_assignment PIN_F22 -to VR[7]
-set_location_assignment PIN_M6 -to ACSI_A1
-set_location_assignment PIN_B1 -to ACSI_D[0]
-set_location_assignment PIN_G5 -to ACSI_D[1]
-set_location_assignment PIN_E3 -to ACSI_D[2]
-set_location_assignment PIN_C2 -to ACSI_D[3]
-set_location_assignment PIN_C1 -to ACSI_D[4]
-set_location_assignment PIN_D2 -to ACSI_D[5]
-set_location_assignment PIN_H7 -to ACSI_D[6]
-set_location_assignment PIN_H6 -to ACSI_D[7]
-set_location_assignment PIN_L6 -to ACSI_DIR
-set_location_assignment PIN_N1 -to AMKB_TX
-set_location_assignment PIN_F15 -to DSA_D
-set_location_assignment PIN_D15 -to DTR
-set_location_assignment PIN_A11 -to DVI_INT
-set_location_assignment PIN_G21 -to E0_INT
-set_location_assignment PIN_M5 -to IDE_RES
-set_location_assignment PIN_A8 -to IO[0]
-set_location_assignment PIN_A7 -to IO[1]
-set_location_assignment PIN_B7 -to IO[2]
-set_location_assignment PIN_A6 -to IO[3]
-set_location_assignment PIN_B6 -to IO[4]
-set_location_assignment PIN_E9 -to IO[5]
-set_location_assignment PIN_C8 -to IO[6]
-set_location_assignment PIN_C7 -to IO[7]
-set_location_assignment PIN_G10 -to IO[8]
-set_location_assignment PIN_A15 -to IO[9]
-set_location_assignment PIN_B15 -to IO[10]
-set_location_assignment PIN_C13 -to IO[11]
-set_location_assignment PIN_D13 -to IO[12]
-set_location_assignment PIN_E13 -to IO[13]
-set_location_assignment PIN_A14 -to IO[14]
-set_location_assignment PIN_B14 -to IO[15]
-set_location_assignment PIN_A13 -to IO[16]
-set_location_assignment PIN_B13 -to IO[17]
-set_location_assignment PIN_F7 -to LP_D[0]
-set_location_assignment PIN_C4 -to LP_D[1]
-set_location_assignment PIN_C3 -to LP_D[2]
-set_location_assignment PIN_E7 -to LP_D[3]
-set_location_assignment PIN_D6 -to LP_D[4]
-set_location_assignment PIN_B3 -to LP_D[5]
-set_location_assignment PIN_A3 -to LP_D[6]
-set_location_assignment PIN_G8 -to LP_D[7]
-set_location_assignment PIN_E6 -to LP_STR
-set_location_assignment PIN_H5 -to MIDI_OLR
-set_location_assignment PIN_B2 -to MIDI_TLR
-set_location_assignment PIN_M4 -to nACSI_ACK
-set_location_assignment PIN_M2 -to nACSI_CS
-set_location_assignment PIN_M1 -to nACSI_RESET
-set_location_assignment PIN_W2 -to nCF_CS0
-set_location_assignment PIN_W1 -to nCF_CS1
-set_location_assignment PIN_T7 -to nFB_TA
-set_location_assignment PIN_R2 -to nIDE_CS0
-set_location_assignment PIN_R1 -to nIDE_CS1
-set_location_assignment PIN_P1 -to nIDE_RD
-set_location_assignment PIN_P2 -to nIDE_WR
-set_location_assignment PIN_F21 -to nIRQ[2]
-set_location_assignment PIN_H20 -to nIRQ[3]
-set_location_assignment PIN_F20 -to nIRQ[4]
-set_location_assignment PIN_P5 -to nIRQ[5]
-set_location_assignment PIN_P7 -to nIRQ[6]
-set_location_assignment PIN_N7 -to nIRQ[7]
-set_location_assignment PIN_AA1 -to nPCI_INTA
-set_location_assignment PIN_V4 -to nPCI_INTB
-set_location_assignment PIN_V3 -to nPCI_INTC
-set_location_assignment PIN_P6 -to nPCI_INTD
-set_location_assignment PIN_P3 -to nROM3
-set_location_assignment PIN_U2 -to nROM4
-set_location_assignment PIN_N5 -to nRP_LDS
-set_location_assignment PIN_P4 -to nRP_UDS
-set_location_assignment PIN_N2 -to nSCSI_ACK
-set_location_assignment PIN_M3 -to nSCSI_ATN
-set_location_assignment PIN_N8 -to nSCSI_BUSY
-set_location_assignment PIN_N6 -to nSCSI_RST
-set_location_assignment PIN_M8 -to nSCSI_SEL
-set_location_assignment PIN_B20 -to nSDSEL
-set_location_assignment PIN_B4 -to nSRBHE
-set_location_assignment PIN_A4 -to nSRBLE
-set_location_assignment PIN_B8 -to nSRCS
-set_location_assignment PIN_F11 -to nSROE
-set_location_assignment PIN_F8 -to nSRWE
-set_location_assignment PIN_G14 -to nWR
-set_location_assignment PIN_D17 -to nWR_GATE
-set_location_assignment PIN_AA2 -to PIC_INT
-set_location_assignment PIN_B18 -to RTS
-set_location_assignment PIN_J6 -to SCSI_D[0]
-set_location_assignment PIN_E1 -to SCSI_D[1]
-set_location_assignment PIN_F2 -to SCSI_D[2]
-set_location_assignment PIN_F1 -to SCSI_D[3]
-set_location_assignment PIN_G4 -to SCSI_D[4]
-set_location_assignment PIN_G3 -to SCSI_D[5]
-set_location_assignment PIN_L8 -to SCSI_D[6]
-set_location_assignment PIN_K8 -to SCSI_D[7]
-set_location_assignment PIN_J7 -to SCSI_DIR
-set_location_assignment PIN_M7 -to SCSI_PAR
-set_location_assignment PIN_F13 -to SD_CD_DATA3
-set_location_assignment PIN_C15 -to SD_CLK
-set_location_assignment PIN_E14 -to SD_CMD_D1
-set_location_assignment PIN_B5 -to SRD[0]
-set_location_assignment PIN_A5 -to SRD[1]
-set_location_assignment PIN_C6 -to SRD[2]
-set_location_assignment PIN_G11 -to SRD[3]
-set_location_assignment PIN_C10 -to SRD[4]
-set_location_assignment PIN_F9 -to SRD[5]
-set_location_assignment PIN_E10 -to SRD[6]
-set_location_assignment PIN_H11 -to SRD[7]
-set_location_assignment PIN_B9 -to SRD[8]
-set_location_assignment PIN_A10 -to SRD[9]
-set_location_assignment PIN_A9 -to SRD[10]
-set_location_assignment PIN_B10 -to SRD[11]
-set_location_assignment PIN_D10 -to SRD[12]
-set_location_assignment PIN_F10 -to SRD[13]
-set_location_assignment PIN_G9 -to SRD[14]
-set_location_assignment PIN_H10 -to SRD[15]
-set_location_assignment PIN_A18 -to TxD
-set_location_assignment PIN_A17 -to YM_QA
-set_location_assignment PIN_G13 -to YM_QB
-set_location_assignment PIN_E15 -to YM_QC
-set_location_assignment PIN_T1 -to WP_CF_CARD
-set_location_assignment PIN_C19 -to TRACK00
-set_location_assignment PIN_M19 -to SD_WP
-set_location_assignment PIN_B17 -to SD_DATA2
-set_location_assignment PIN_A16 -to SD_DATA1
-set_location_assignment PIN_B16 -to SD_DATA0
-set_location_assignment PIN_M20 -to SD_CARD_DEDECT
-set_location_assignment PIN_H15 -to RxD
-set_location_assignment PIN_B19 -to RI
-set_location_assignment PIN_L7 -to PIC_AMKB_RX
-set_location_assignment PIN_D19 -to nWP
-set_location_assignment PIN_H2 -to nSCSI_MSG
-set_location_assignment PIN_J3 -to nSCSI_I_O
-set_location_assignment PIN_U1 -to nSCSI_DRQ
-set_location_assignment PIN_H1 -to nSCSI_C_D
-set_location_assignment PIN_A20 -to nRD_DATA
-set_location_assignment PIN_C17 -to nDCHG
-set_location_assignment PIN_J4 -to nACSI_INT
-set_location_assignment PIN_K7 -to nACSI_DRQ
-set_location_assignment PIN_G7 -to LP_BUSY
-set_location_assignment PIN_Y1 -to IDE_RDY
-set_location_assignment PIN_G22 -to IDE_INT
-set_location_assignment PIN_F16 -to HD_DD
-set_location_assignment PIN_A19 -to DCD
-set_location_assignment PIN_H14 -to CTS
-set_location_assignment PIN_Y2 -to AMKB_RX
-set_location_assignment PIN_E16 -to nINDEX
-set_location_assignment PIN_W19 -to BA[0]
-set_location_assignment PIN_AA19 -to BA[1]
-set_location_assignment PIN_K21 -to HSYNC_PAD
-set_location_assignment PIN_K19 -to VSYNC_PAD
-set_location_assignment PIN_G17 -to nBLANK_PAD
-set_location_assignment PIN_F19 -to PIXEL_CLK_PAD
-set_location_assignment PIN_F17 -to nSYNC
-set_location_assignment PIN_G15 -to nSTEP_DIR
-set_location_assignment PIN_F14 -to nSTEP
-set_location_assignment PIN_G16 -to nMOT_ON
+set_location_assignment PIN_G2 -to MAIN_CLK
+set_location_assignment PIN_Y3 -to FB_AD[0]
+set_location_assignment PIN_Y6 -to FB_AD[1]
+set_location_assignment PIN_AA3 -to FB_AD[2]
+set_location_assignment PIN_AB3 -to FB_AD[3]
+set_location_assignment PIN_W6 -to FB_AD[4]
+set_location_assignment PIN_V7 -to FB_AD[5]
+set_location_assignment PIN_AA4 -to FB_AD[6]
+set_location_assignment PIN_AB4 -to FB_AD[7]
+set_location_assignment PIN_AA5 -to FB_AD[8]
+set_location_assignment PIN_AB5 -to FB_AD[9]
+set_location_assignment PIN_W7 -to FB_AD[10]
+set_location_assignment PIN_Y7 -to FB_AD[11]
+set_location_assignment PIN_U9 -to FB_AD[12]
+set_location_assignment PIN_V8 -to FB_AD[13]
+set_location_assignment PIN_W8 -to FB_AD[14]
+set_location_assignment PIN_AA7 -to FB_AD[15]
+set_location_assignment PIN_AB7 -to FB_AD[16]
+set_location_assignment PIN_Y8 -to FB_AD[17]
+set_location_assignment PIN_V9 -to FB_AD[18]
+set_location_assignment PIN_V10 -to FB_AD[19]
+set_location_assignment PIN_T10 -to FB_AD[20]
+set_location_assignment PIN_U10 -to FB_AD[21]
+set_location_assignment PIN_AA8 -to FB_AD[22]
+set_location_assignment PIN_AB8 -to FB_AD[23]
+set_location_assignment PIN_T11 -to FB_AD[24]
+set_location_assignment PIN_AA9 -to FB_AD[25]
+set_location_assignment PIN_AB9 -to FB_AD[26]
+set_location_assignment PIN_U11 -to FB_AD[27]
+set_location_assignment PIN_V11 -to FB_AD[28]
+set_location_assignment PIN_W10 -to FB_AD[29]
+set_location_assignment PIN_Y10 -to FB_AD[30]
+set_location_assignment PIN_AA10 -to FB_AD[31]
+set_location_assignment PIN_R7 -to FB_ALE
+set_location_assignment PIN_N19 -to LED_FPGA_OK
+set_location_assignment PIN_AB10 -to CLK24M576
+set_location_assignment PIN_J1 -to CLKUSB
+set_location_assignment PIN_T4 -to CLK25M
+set_location_assignment PIN_U8 -to FB_SIZE0
+set_location_assignment PIN_Y4 -to FB_SIZE1
+set_location_assignment PIN_T3 -to nFB_BURST
+set_location_assignment PIN_T8 -to nFB_CS1
+set_location_assignment PIN_T9 -to nFB_CS2
+set_location_assignment PIN_V6 -to nFB_CS3
+set_location_assignment PIN_R6 -to nFB_OE
+set_location_assignment PIN_T5 -to nFB_WR
+set_location_assignment PIN_R5 -to TIN0
+set_location_assignment PIN_T21 -to nMASTER
+set_location_assignment PIN_E11 -to nDREQ1
+set_location_assignment PIN_A12 -to nDACK1
+set_location_assignment PIN_B12 -to nDACK0
+set_location_assignment PIN_T22 -to TOUT0
+set_location_assignment PIN_AB17 -to DDR_CLK
+set_location_assignment PIN_AA17 -to nDDR_CLK
+set_location_assignment PIN_AB18 -to nVCAS
+set_location_assignment PIN_T18 -to nVCS
+set_location_assignment PIN_W17 -to nVRAS
+set_location_assignment PIN_Y17 -to nVWE
+set_location_assignment PIN_W20 -to VA[0]
+set_location_assignment PIN_W22 -to VA[1]
+set_location_assignment PIN_W21 -to VA[2]
+set_location_assignment PIN_Y22 -to VA[3]
+set_location_assignment PIN_AA22 -to VA[4]
+set_location_assignment PIN_Y21 -to VA[5]
+set_location_assignment PIN_AA21 -to VA[6]
+set_location_assignment PIN_AA20 -to VA[7]
+set_location_assignment PIN_AB20 -to VA[8]
+set_location_assignment PIN_AB19 -to VA[9]
+set_location_assignment PIN_V21 -to VA[10]
+set_location_assignment PIN_U19 -to VA[11]
+set_location_assignment PIN_AA18 -to VA[12]
+set_location_assignment PIN_U15 -to VCKE
+set_location_assignment PIN_M22 -to VD[0]
+set_location_assignment PIN_M21 -to VD[1]
+set_location_assignment PIN_P22 -to VD[2]
+set_location_assignment PIN_R20 -to VD[3]
+set_location_assignment PIN_P21 -to VD[4]
+set_location_assignment PIN_R17 -to VD[5]
+set_location_assignment PIN_R19 -to VD[6]
+set_location_assignment PIN_U21 -to VD[7]
+set_location_assignment PIN_V22 -to VD[8]
+set_location_assignment PIN_R18 -to VD[9]
+set_location_assignment PIN_P17 -to VD[10]
+set_location_assignment PIN_R21 -to VD[11]
+set_location_assignment PIN_N17 -to VD[12]
+set_location_assignment PIN_P20 -to VD[13]
+set_location_assignment PIN_R22 -to VD[14]
+set_location_assignment PIN_N20 -to VD[15]
+set_location_assignment PIN_T12 -to VD[16]
+set_location_assignment PIN_Y13 -to VD[17]
+set_location_assignment PIN_AA13 -to VD[18]
+set_location_assignment PIN_V14 -to VD[19]
+set_location_assignment PIN_U13 -to VD[20]
+set_location_assignment PIN_V15 -to VD[21]
+set_location_assignment PIN_W14 -to VD[22]
+set_location_assignment PIN_AB16 -to VD[23]
+set_location_assignment PIN_AB15 -to VD[24]
+set_location_assignment PIN_AA14 -to VD[25]
+set_location_assignment PIN_AB14 -to VD[26]
+set_location_assignment PIN_V13 -to VD[27]
+set_location_assignment PIN_W13 -to VD[28]
+set_location_assignment PIN_AB13 -to VD[29]
+set_location_assignment PIN_V12 -to VD[30]
+set_location_assignment PIN_U12 -to VD[31]
+set_location_assignment PIN_AA16 -to VDM[0]
+set_location_assignment PIN_V16 -to VDM[1]
+set_location_assignment PIN_U20 -to VDM[2]
+set_location_assignment PIN_T17 -to VDM[3]
+set_location_assignment PIN_AA15 -to VDQS[0]
+set_location_assignment PIN_W15 -to VDQS[1]
+set_location_assignment PIN_U22 -to VDQS[2]
+set_location_assignment PIN_T16 -to VDQS[3]
+set_location_assignment PIN_V1 -to nPD_VGA
+set_location_assignment PIN_G18 -to VB[0]
+set_location_assignment PIN_H17 -to VB[1]
+set_location_assignment PIN_C22 -to VB[2]
+set_location_assignment PIN_C21 -to VB[3]
+set_location_assignment PIN_B22 -to VB[4]
+set_location_assignment PIN_B21 -to VB[5]
+set_location_assignment PIN_C20 -to VB[6]
+set_location_assignment PIN_D20 -to VB[7]
+set_location_assignment PIN_H19 -to VG[0]
+set_location_assignment PIN_E22 -to VG[1]
+set_location_assignment PIN_E21 -to VG[2]
+set_location_assignment PIN_H18 -to VG[3]
+set_location_assignment PIN_J17 -to VG[4]
+set_location_assignment PIN_H16 -to VG[5]
+set_location_assignment PIN_D22 -to VG[6]
+set_location_assignment PIN_D21 -to VG[7]
+set_location_assignment PIN_J22 -to VR[0]
+set_location_assignment PIN_J21 -to VR[1]
+set_location_assignment PIN_H22 -to VR[2]
+set_location_assignment PIN_H21 -to VR[3]
+set_location_assignment PIN_K17 -to VR[4]
+set_location_assignment PIN_K18 -to VR[5]
+set_location_assignment PIN_J18 -to VR[6]
+set_location_assignment PIN_F22 -to VR[7]
+set_location_assignment PIN_M6 -to ACSI_A1
+set_location_assignment PIN_B1 -to ACSI_D[0]
+set_location_assignment PIN_G5 -to ACSI_D[1]
+set_location_assignment PIN_E3 -to ACSI_D[2]
+set_location_assignment PIN_C2 -to ACSI_D[3]
+set_location_assignment PIN_C1 -to ACSI_D[4]
+set_location_assignment PIN_D2 -to ACSI_D[5]
+set_location_assignment PIN_H7 -to ACSI_D[6]
+set_location_assignment PIN_H6 -to ACSI_D[7]
+set_location_assignment PIN_L6 -to ACSI_DIR
+set_location_assignment PIN_N1 -to AMKB_TX
+set_location_assignment PIN_F15 -to DSA_D
+set_location_assignment PIN_D15 -to DTR
+set_location_assignment PIN_A11 -to DVI_INT
+set_location_assignment PIN_G21 -to E0_INT
+set_location_assignment PIN_M5 -to IDE_RES
+set_location_assignment PIN_A8 -to IO[0]
+set_location_assignment PIN_A7 -to IO[1]
+set_location_assignment PIN_B7 -to IO[2]
+set_location_assignment PIN_A6 -to IO[3]
+set_location_assignment PIN_B6 -to IO[4]
+set_location_assignment PIN_E9 -to IO[5]
+set_location_assignment PIN_C8 -to IO[6]
+set_location_assignment PIN_C7 -to IO[7]
+set_location_assignment PIN_G10 -to IO[8]
+set_location_assignment PIN_A15 -to IO[9]
+set_location_assignment PIN_B15 -to IO[10]
+set_location_assignment PIN_C13 -to IO[11]
+set_location_assignment PIN_D13 -to IO[12]
+set_location_assignment PIN_E13 -to IO[13]
+set_location_assignment PIN_A14 -to IO[14]
+set_location_assignment PIN_B14 -to IO[15]
+set_location_assignment PIN_A13 -to IO[16]
+set_location_assignment PIN_B13 -to IO[17]
+set_location_assignment PIN_F7 -to LP_D[0]
+set_location_assignment PIN_C4 -to LP_D[1]
+set_location_assignment PIN_C3 -to LP_D[2]
+set_location_assignment PIN_E7 -to LP_D[3]
+set_location_assignment PIN_D6 -to LP_D[4]
+set_location_assignment PIN_B3 -to LP_D[5]
+set_location_assignment PIN_A3 -to LP_D[6]
+set_location_assignment PIN_G8 -to LP_D[7]
+set_location_assignment PIN_E6 -to LP_STR
+set_location_assignment PIN_H5 -to MIDI_OLR
+set_location_assignment PIN_B2 -to MIDI_TLR
+set_location_assignment PIN_M4 -to nACSI_ACK
+set_location_assignment PIN_M2 -to nACSI_CS
+set_location_assignment PIN_M1 -to nACSI_RESET
+set_location_assignment PIN_W2 -to nCF_CS0
+set_location_assignment PIN_W1 -to nCF_CS1
+set_location_assignment PIN_T7 -to nFB_TA
+set_location_assignment PIN_R2 -to nIDE_CS0
+set_location_assignment PIN_R1 -to nIDE_CS1
+set_location_assignment PIN_P1 -to nIDE_RD
+set_location_assignment PIN_P2 -to nIDE_WR
+set_location_assignment PIN_F21 -to nIRQ[2]
+set_location_assignment PIN_H20 -to nIRQ[3]
+set_location_assignment PIN_F20 -to nIRQ[4]
+set_location_assignment PIN_P5 -to nIRQ[5]
+set_location_assignment PIN_P7 -to nIRQ[6]
+set_location_assignment PIN_N7 -to nIRQ[7]
+set_location_assignment PIN_AA1 -to nPCI_INTA
+set_location_assignment PIN_V4 -to nPCI_INTB
+set_location_assignment PIN_V3 -to nPCI_INTC
+set_location_assignment PIN_P6 -to nPCI_INTD
+set_location_assignment PIN_P3 -to nROM3
+set_location_assignment PIN_U2 -to nROM4
+set_location_assignment PIN_N5 -to nRP_LDS
+set_location_assignment PIN_P4 -to nRP_UDS
+set_location_assignment PIN_N2 -to nSCSI_ACK
+set_location_assignment PIN_M3 -to nSCSI_ATN
+set_location_assignment PIN_N8 -to nSCSI_BUSY
+set_location_assignment PIN_N6 -to nSCSI_RST
+set_location_assignment PIN_M8 -to nSCSI_SEL
+set_location_assignment PIN_B20 -to nSDSEL
+set_location_assignment PIN_B4 -to nSRBHE
+set_location_assignment PIN_A4 -to nSRBLE
+set_location_assignment PIN_B8 -to nSRCS
+set_location_assignment PIN_F11 -to nSROE
+set_location_assignment PIN_F8 -to nSRWE
+set_location_assignment PIN_G14 -to nWR
+set_location_assignment PIN_D17 -to nWR_GATE
+set_location_assignment PIN_AA2 -to PIC_INT
+set_location_assignment PIN_B18 -to RTS
+set_location_assignment PIN_J6 -to SCSI_D[0]
+set_location_assignment PIN_E1 -to SCSI_D[1]
+set_location_assignment PIN_F2 -to SCSI_D[2]
+set_location_assignment PIN_F1 -to SCSI_D[3]
+set_location_assignment PIN_G4 -to SCSI_D[4]
+set_location_assignment PIN_G3 -to SCSI_D[5]
+set_location_assignment PIN_L8 -to SCSI_D[6]
+set_location_assignment PIN_K8 -to SCSI_D[7]
+set_location_assignment PIN_J7 -to SCSI_DIR
+set_location_assignment PIN_M7 -to SCSI_PAR
+set_location_assignment PIN_F13 -to SD_CD_DATA3
+set_location_assignment PIN_C15 -to SD_CLK
+set_location_assignment PIN_E14 -to SD_CMD_D1
+set_location_assignment PIN_B5 -to SRD[0]
+set_location_assignment PIN_A5 -to SRD[1]
+set_location_assignment PIN_C6 -to SRD[2]
+set_location_assignment PIN_G11 -to SRD[3]
+set_location_assignment PIN_C10 -to SRD[4]
+set_location_assignment PIN_F9 -to SRD[5]
+set_location_assignment PIN_E10 -to SRD[6]
+set_location_assignment PIN_H11 -to SRD[7]
+set_location_assignment PIN_B9 -to SRD[8]
+set_location_assignment PIN_A10 -to SRD[9]
+set_location_assignment PIN_A9 -to SRD[10]
+set_location_assignment PIN_B10 -to SRD[11]
+set_location_assignment PIN_D10 -to SRD[12]
+set_location_assignment PIN_F10 -to SRD[13]
+set_location_assignment PIN_G9 -to SRD[14]
+set_location_assignment PIN_H10 -to SRD[15]
+set_location_assignment PIN_A18 -to TxD
+set_location_assignment PIN_A17 -to YM_QA
+set_location_assignment PIN_G13 -to YM_QB
+set_location_assignment PIN_E15 -to YM_QC
+set_location_assignment PIN_T1 -to WP_CF_CARD
+set_location_assignment PIN_C19 -to TRACK00
+set_location_assignment PIN_M19 -to SD_WP
+set_location_assignment PIN_B17 -to SD_DATA2
+set_location_assignment PIN_A16 -to SD_DATA1
+set_location_assignment PIN_B16 -to SD_DATA0
+set_location_assignment PIN_M20 -to SD_CARD_DEDECT
+set_location_assignment PIN_H15 -to RxD
+set_location_assignment PIN_B19 -to RI
+set_location_assignment PIN_L7 -to PIC_AMKB_RX
+set_location_assignment PIN_D19 -to nWP
+set_location_assignment PIN_H2 -to nSCSI_MSG
+set_location_assignment PIN_J3 -to nSCSI_I_O
+set_location_assignment PIN_U1 -to nSCSI_DRQ
+set_location_assignment PIN_H1 -to nSCSI_C_D
+set_location_assignment PIN_A20 -to nRD_DATA
+set_location_assignment PIN_C17 -to nDCHG
+set_location_assignment PIN_J4 -to nACSI_INT
+set_location_assignment PIN_K7 -to nACSI_DRQ
+set_location_assignment PIN_G7 -to LP_BUSY
+set_location_assignment PIN_Y1 -to IDE_RDY
+set_location_assignment PIN_G22 -to IDE_INT
+set_location_assignment PIN_F16 -to HD_DD
+set_location_assignment PIN_A19 -to DCD
+set_location_assignment PIN_H14 -to CTS
+set_location_assignment PIN_Y2 -to AMKB_RX
+set_location_assignment PIN_E16 -to nINDEX
+set_location_assignment PIN_W19 -to BA[0]
+set_location_assignment PIN_AA19 -to BA[1]
+set_location_assignment PIN_K21 -to HSYNC_PAD
+set_location_assignment PIN_K19 -to VSYNC_PAD
+set_location_assignment PIN_G17 -to nBLANK_PAD
+set_location_assignment PIN_F19 -to PIXEL_CLK_PAD
+set_location_assignment PIN_F17 -to nSYNC
+set_location_assignment PIN_G15 -to nSTEP_DIR
+set_location_assignment PIN_F14 -to nSTEP
+set_location_assignment PIN_G16 -to nMOT_ON
 
 # Classic Timing Assignments
 # ==========================
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name TPD_REQUIREMENT "1 ns"
-set_global_assignment -name TSU_REQUIREMENT "1 ns"
-set_global_assignment -name TCO_REQUIREMENT "1 ns"
-set_global_assignment -name TH_REQUIREMENT "1 ns"
-set_global_assignment -name FMAX_REQUIREMENT "30 ns"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name TPD_REQUIREMENT "1 ns"
+set_global_assignment -name TSU_REQUIREMENT "1 ns"
+set_global_assignment -name TCO_REQUIREMENT "1 ns"
+set_global_assignment -name TH_REQUIREMENT "1 ns"
+set_global_assignment -name FMAX_REQUIREMENT "30 ns"
 
 # Analysis & Synthesis Assignments
 # ================================
-set_global_assignment -name FAMILY CycloneIII
-set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
-set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name SAFE_STATE_MACHINE OFF
-set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
+set_global_assignment -name FAMILY CycloneIII
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name SAFE_STATE_MACHINE OFF
+set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
 
 # Fitter Assignments
 # ==================
-set_global_assignment -name DEVICE EP3C40F484C6
-set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON
-set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON
-set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
-set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
-set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
-set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VA
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VD
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS
-set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE
-set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK
-set_instance_assignment -name IO_STANDARD "2.5 V" -to BA
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD
-set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX
+set_global_assignment -name DEVICE EP3C40F484C6
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
+set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VA
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VD
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to BA
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX
 
 # Assembler Assignments
 # =====================
-set_global_assignment -name GENERATE_TTF_FILE OFF
-set_global_assignment -name GENERATE_RBF_FILE ON
-set_global_assignment -name GENERATE_HEX_FILE OFF
-set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000
+set_global_assignment -name GENERATE_TTF_FILE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name GENERATE_HEX_FILE OFF
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000
 
 # Simulator Assignments
 # =====================
-set_global_assignment -name END_TIME "2 us"
-set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
-set_global_assignment -name SETUP_HOLD_DETECTION OFF
-set_global_assignment -name GLITCH_DETECTION OFF
-set_global_assignment -name CHECK_OUTPUTS OFF
-set_global_assignment -name SIMULATION_MODE TIMING
-set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf
+set_global_assignment -name END_TIME "2 us"
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
+set_global_assignment -name SETUP_HOLD_DETECTION OFF
+set_global_assignment -name GLITCH_DETECTION OFF
+set_global_assignment -name CHECK_OUTPUTS OFF
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf
 
 # start EDA_TOOL_SETTINGS(eda_blast_fpga)
 # ---------------------------------------
 
 	# Analysis & Synthesis Assignments
 	# ================================
-set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
 
 # end EDA_TOOL_SETTINGS(eda_blast_fpga)
 # -------------------------------------
@@ -431,7 +431,7 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e
 
 	# Classic Timing Assignments
 	# ==========================
-set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast
+set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast
 
 # end CLOCK(fast)
 # ---------------
@@ -441,21 +441,21 @@ set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast
 
 	# Assignment Group Assignments
 	# ============================
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast
-set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[0]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[1]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[2]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDRCLK[3]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast
 
 # end ASSIGNMENT_GROUP(fast)
 # --------------------------
@@ -465,76 +465,76 @@ set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "Video:Fredi_Aschwanden|DDR_
 
 	# Classic Timing Assignments
 	# ==========================
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0]
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1]
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2]
-set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3]
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]"
-set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]"
-set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE
-set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD
-set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA
-set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS
-set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0]
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1]
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2]
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3]
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[0]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[1]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[2]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDRCLK[3]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]"
+set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE
+set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD
+set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA
+set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS
+set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA
 
 	# Fitter Assignments
 	# ==================
-set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS
-set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD
-set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA
-set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VCKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to FB_AD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nVCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nPD_VGA
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to SRD
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to IO
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBLE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nSRBHE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX
 
 	# Simulator Assignments
 	# =====================
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3
 
 	# start LOGICLOCK_REGION(Root Region)
 	# -----------------------------------
@@ -556,311 +556,311 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3
 
 # end ENTITY(firebee1)
 # --------------------
-set_location_assignment PIN_E5 -to LPDIR
-set_location_assignment PIN_B11 -to nRSTO_MCF
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD
-set_location_assignment PIN_AB12 -to CLK33MDIR
-set_location_assignment PIN_E12 -to MIDI_IN_PIN
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN
-set_instance_assignment -name PCI_IO ON -to nPCI_INTA
-set_instance_assignment -name PCI_IO ON -to nPCI_INTB
-set_instance_assignment -name PCI_IO ON -to nPCI_INTC
-set_instance_assignment -name PCI_IO ON -to nPCI_INTD
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6]
-set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3]
-set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2]
-set_global_assignment -name POWER_USE_TA_VALUE 35
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR
-set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1]
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS
-set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE
-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name SMART_RECOMPILE ON
+set_location_assignment PIN_E5 -to LPDIR
+set_location_assignment PIN_B11 -to nRSTO_MCF
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to E0_INT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to DVI_INT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTA
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTB
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTC
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nPCI_INTD
+set_location_assignment PIN_AB12 -to CLK33MDIR
+set_location_assignment PIN_E12 -to MIDI_IN_PIN
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to MIDI_IN_PIN
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MIDI_IN_PIN
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to MIDI_IN_PIN
+set_instance_assignment -name PCI_IO ON -to nPCI_INTA
+set_instance_assignment -name PCI_IO ON -to nPCI_INTB
+set_instance_assignment -name PCI_IO ON -to nPCI_INTC
+set_instance_assignment -name PCI_IO ON -to nPCI_INTD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_DRQ
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nACSI_INT
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTA
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTB
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTC
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nPCI_INTD
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_WP
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to SD_CARD_DEDECT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK1
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TOUT0
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to MAIN_CLK
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to CLK33MDIR
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nRSTO_MCF
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nDACK0
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[2]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[3]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to TIN0
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to TIN0
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[5]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[4]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[4]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[5]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[6]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nIRQ[3]
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nIRQ[2]
+set_global_assignment -name POWER_USE_TA_VALUE 35
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DSA_D
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nMOT_ON
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSTEP
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nWR_GATE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSDSEL
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_PAR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SCSI_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_SEL
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_RST
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_BUSY
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ATN
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nSCSI_ACK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_A1
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_CS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ACSI_DIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_ACK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nACSI_RESET
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LPDIR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_STR
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LP_D
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_D
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LPDIR
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to LP_STR
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to SRD
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[0]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[7]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[6]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[5]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[4]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[3]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[2]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[1]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBHE
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRWE
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRCS
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSRBLE
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_RX
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name SMART_RECOMPILE ON
 set_global_assignment -name TOP_LEVEL_ENTITY firebee1
-set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED
-set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
-set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
-set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
-set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
-set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
-set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS"
-set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
-set_global_assignment -name SAVE_DISK_SPACE OFF
-set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK
-set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
-set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
-set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q
-set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf
-set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf
-set_global_assignment -name AHDL_FILE altpll4.tdf
-set_global_assignment -name SDC_FILE firebee_groups.sdc
-set_global_assignment -name VHDL_FILE Video/video.vhd
-set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd
-set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd
-set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp
-set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd
-set_global_assignment -name SOURCE_FILE altpll4.cmp
-set_global_assignment -name VHDL_FILE firebee1.vhd
-set_global_assignment -name VHDL_FILE Video/mux41.vhd
-set_global_assignment -name VHDL_FILE Video/mux41_5.vhd
-set_global_assignment -name VHDL_FILE Video/mux41_4.vhd
-set_global_assignment -name VHDL_FILE Video/mux41_3.vhd
-set_global_assignment -name VHDL_FILE Video/mux41_2.vhd
-set_global_assignment -name VHDL_FILE Video/mux41_1.vhd
-set_global_assignment -name VHDL_FILE Video/mux41_0.vhd
-set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp
-set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp
-set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp
-set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp
-set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp
-set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd
-set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp
-set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp
-set_global_assignment -name VHDL_FILE Video/altdpram0.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp
-set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip
-set_global_assignment -name QIP_FILE Video/altdpram0.qip
-set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip
-set_global_assignment -name QIP_FILE Video/altdpram1.qip
-set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip
-set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant0.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant1.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux0.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux1.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux2.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant2.qip
-set_global_assignment -name QIP_FILE Video/altdpram2.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip
-set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip
-set_global_assignment -name QIP_FILE Video/altddio_out0.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux5.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip
-set_global_assignment -name QIP_FILE Video/altddio_out1.qip
-set_global_assignment -name QIP_FILE Video/altddio_out2.qip
-set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux6.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux3.qip
-set_global_assignment -name QIP_FILE Video/lpm_mux4.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant3.qip
-set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip
-set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip
-set_global_assignment -name QIP_FILE Video/lpm_latch1.qip
-set_global_assignment -name QIP_FILE Video/lpm_constant4.qip
-set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip
-set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip
-set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT
-set_global_assignment -name QIP_FILE Video/lpm_compare1.qip
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd
-set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp
-set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd
-set_global_assignment -name QIP_FILE Video/lpm_ff4.qip
-set_global_assignment -name QIP_FILE Video/lpm_ff5.qip
-set_global_assignment -name QIP_FILE Video/lpm_ff6.qip
-set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp
-set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip
-set_global_assignment -name VHDL_FILE DSP/DSP.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
-set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd
-set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
-set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip
-set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
-set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
-set_global_assignment -name VHDL_FILE lpm_latch0.vhd
-set_global_assignment -name SOURCE_FILE lpm_latch0.cmp
-set_global_assignment -name QIP_FILE altpll1.qip
-set_global_assignment -name QIP_FILE altpll2.qip
-set_global_assignment -name QIP_FILE altpll3.qip
-set_global_assignment -name SOURCE_FILE altpll0.cmp
-set_global_assignment -name SOURCE_FILE altpll2.cmp
-set_global_assignment -name VHDL_FILE altpll2.vhd
-set_global_assignment -name SOURCE_FILE altpll3.cmp
-set_global_assignment -name VHDL_FILE altpll3.vhd
-set_global_assignment -name SOURCE_FILE lpm_counter0.cmp
-set_global_assignment -name VHDL_FILE altpll1.vhd
-set_global_assignment -name SOURCE_FILE altpll1.cmp
-set_global_assignment -name QIP_FILE altpll0.qip
-set_global_assignment -name QIP_FILE lpm_counter0.qip
-set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
-set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
-set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
-set_global_assignment -name QIP_FILE altddio_out3.qip
-set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
-set_global_assignment -name QIP_FILE altpll4.qip
-set_global_assignment -name QIP_FILE lpm_mux0.qip
-set_global_assignment -name QIP_FILE lpm_shiftreg0.qip
-set_global_assignment -name QIP_FILE lpm_counter1.qip
-set_global_assignment -name QIP_FILE altiobuf_bidir0.qip
-set_global_assignment -name VHDL_FILE flexbus_register.vhd
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION "FORCED IF ASYNCHRONOUS"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to MAIN_CLK
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to DDR_CLK
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to nDDR_CLK
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q
+set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf
+set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf
+set_global_assignment -name AHDL_FILE altpll4.tdf
+set_global_assignment -name SDC_FILE firebee_groups.sdc
+set_global_assignment -name VHDL_FILE Video/video.vhd
+set_global_assignment -name VHDL_FILE Video/video_mod_mux_clutctr.vhd
+set_global_assignment -name VHDL_FILE Video/DDR_CTR.vhd
+set_global_assignment -name SOURCE_FILE altpll_reconfig1.cmp
+set_global_assignment -name VHDL_FILE Interrupt_Handler/interrupt_handler.vhd
+set_global_assignment -name SOURCE_FILE altpll4.cmp
+set_global_assignment -name VHDL_FILE firebee1.vhd
+set_global_assignment -name VHDL_FILE Video/mux41.vhd
+set_global_assignment -name VHDL_FILE Video/mux41_5.vhd
+set_global_assignment -name VHDL_FILE Video/mux41_4.vhd
+set_global_assignment -name VHDL_FILE Video/mux41_3.vhd
+set_global_assignment -name VHDL_FILE Video/mux41_2.vhd
+set_global_assignment -name VHDL_FILE Video/mux41_1.vhd
+set_global_assignment -name VHDL_FILE Video/mux41_0.vhd
+set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri7.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff4.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_fifoDZ.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_compare1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_constant3.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_ff6.cmp
+set_global_assignment -name SOURCE_FILE Video/altddio_out0.cmp
+set_global_assignment -name SOURCE_FILE Video/altddio_out1.cmp
+set_global_assignment -name SOURCE_FILE Video/altddio_bidir0.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_constant2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri0.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_constant4.cmp
+set_global_assignment -name SOURCE_FILE Video/altdpram2.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_latch1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux0.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg4.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri3.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg5.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg6.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri4.cmp
+set_global_assignment -name SOURCE_FILE Video/altddio_out2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_constant0.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_constant1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri5.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg0.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_ff3.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd
+set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_fifo_dc0.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux3.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux4.cmp
+set_global_assignment -name SOURCE_FILE Video/altdpram0.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_mux5.cmp
+set_global_assignment -name VHDL_FILE Video/altdpram0.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_mux6.cmp
+set_global_assignment -name SOURCE_FILE Video/altdpram1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ2.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_muxDZ.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_ff5.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg1.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_ff0.cmp
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip
+set_global_assignment -name QIP_FILE Video/altdpram0.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip
+set_global_assignment -name QIP_FILE Video/altdpram1.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant0.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant1.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux0.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux1.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux2.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant2.qip
+set_global_assignment -name QIP_FILE Video/altdpram2.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip
+set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip
+set_global_assignment -name QIP_FILE Video/altddio_out0.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux5.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip
+set_global_assignment -name QIP_FILE Video/altddio_out1.qip
+set_global_assignment -name QIP_FILE Video/altddio_out2.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux6.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux3.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux4.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant3.qip
+set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip
+set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip
+set_global_assignment -name QIP_FILE Video/lpm_latch1.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant4.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip
+set_global_assignment -name QIP_FILE Video/BLITTER/lpm_clshift0.qip
+set_global_assignment -name SOURCE_FILE Video/BLITTER/blitter.tdf.ALT
+set_global_assignment -name QIP_FILE Video/lpm_compare1.qip
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg2.cmp
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri2.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd
+set_global_assignment -name SOURCE_FILE Video/lpm_shiftreg3.cmp
+set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd
+set_global_assignment -name QIP_FILE Video/lpm_ff4.qip
+set_global_assignment -name QIP_FILE Video/lpm_ff5.qip
+set_global_assignment -name QIP_FILE Video/lpm_ff6.qip
+set_global_assignment -name SOURCE_FILE Video/lpm_bustri6.cmp
+set_global_assignment -name QIP_FILE Video/BLITTER/altsyncram0.qip
+set_global_assignment -name VHDL_FILE DSP/DSP.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
+set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo0.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd
+set_global_assignment -name SOURCE_FILE FalconIO_SDCard_IDE_CF/dcfifo1.cmp
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
+set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip
+set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
+set_global_assignment -name VHDL_FILE lpm_latch0.vhd
+set_global_assignment -name SOURCE_FILE lpm_latch0.cmp
+set_global_assignment -name QIP_FILE altpll1.qip
+set_global_assignment -name QIP_FILE altpll2.qip
+set_global_assignment -name QIP_FILE altpll3.qip
+set_global_assignment -name SOURCE_FILE altpll0.cmp
+set_global_assignment -name SOURCE_FILE altpll2.cmp
+set_global_assignment -name VHDL_FILE altpll2.vhd
+set_global_assignment -name SOURCE_FILE altpll3.cmp
+set_global_assignment -name VHDL_FILE altpll3.vhd
+set_global_assignment -name SOURCE_FILE lpm_counter0.cmp
+set_global_assignment -name VHDL_FILE altpll1.vhd
+set_global_assignment -name SOURCE_FILE altpll1.cmp
+set_global_assignment -name QIP_FILE altpll0.qip
+set_global_assignment -name QIP_FILE lpm_counter0.qip
+set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
+set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
+set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
+set_global_assignment -name QIP_FILE altddio_out3.qip
+set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
+set_global_assignment -name QIP_FILE altpll4.qip
+set_global_assignment -name QIP_FILE lpm_mux0.qip
+set_global_assignment -name QIP_FILE lpm_shiftreg0.qip
+set_global_assignment -name QIP_FILE lpm_counter1.qip
+set_global_assignment -name QIP_FILE altiobuf_bidir0.qip
+set_global_assignment -name VHDL_FILE flexbus_register.vhd
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd
index 699c1d4..3388ae3 100644
--- a/FPGA_Quartus_13.1/firebee1.vhd
+++ b/FPGA_Quartus_13.1/firebee1.vhd
@@ -242,53 +242,53 @@ ARCHITECTURE rtl OF firebee1 IS
         );
     END COMPONENT altpll4;
 
-    COMPONENT video
-	PORT
-	(
-		FB_ADR		    : IN std_logic_vector(31 DOWNTO 0);
-		MAIN_CLK	    : IN std_logic;
-		nFB_CS1		    : IN std_logic;
-		nFB_CS2		    : IN std_logic;
-		nFB_CS3		    : IN std_logic;
-		nFB_WR		    : IN std_logic;
-		FB_SIZE0	    : IN std_logic;
-		FB_SIZE1	    : IN std_logic;
-		nRSTO		    : IN std_logic;
-		nFB_OE		    : IN std_logic;
-		FB_ALE		    : IN std_logic;
-		DDRCLK		    : IN std_logic_vector(3 DOWNTO 0);
-		DDR_SYNC_66M	: IN std_logic;
-		CLK33M		    : IN std_logic;
-		CLK25M		    : IN std_logic;
-		CLK_VIDEO		: IN std_logic;
-		VR_D		    : IN std_logic_vector(8 DOWNTO 0);
-		VR_BUSY		    : IN std_logic;
-		VG		        : OUT std_logic_vector(7 DOWNTO 0);
-		VB		        : OUT std_logic_vector(7 DOWNTO 0);
-		VR		        : OUT std_logic_vector(7 DOWNTO 0);
-		nBLANK		    : OUT std_logic;
-		VA		        : OUT std_logic_vector(12 DOWNTO 0);
-		nVWE		    : OUT std_logic;
-		nVCAS		    : OUT std_logic;
-		nVRAS		    : OUT std_logic;
-		nVCS		    : OUT std_logic;
-		VDM		        : OUT std_logic_vector(3 DOWNTO 0);
-		nPD_VGA		    : OUT std_logic;
-		VCKE		    : OUT std_logic;
-		VSYNC		    : OUT std_logic;
-		HSYNC		    : OUT std_logic;
-		nSYNC		    : OUT std_logic;
-		VIDEO_TA		: OUT std_logic;
-		PIXEL_CLK		: OUT std_logic;
-		BA		        : OUT std_logic_vector(1 DOWNTO 0);
-		VIDEO_RECONFIG	: OUT std_logic;
-		VR_WR		    : OUT std_logic;
-		VR_RD		    : OUT std_logic;
-		VDQS		    : INOUT std_logic_vector(3 DOWNTO 0);
-		FB_AD		    : INOUT std_logic_vector(31 DOWNTO 0);
-		VD		        : INOUT std_logic_vector(31 DOWNTO 0)
-	);
-    END COMPONENT video;
+--    COMPONENT video
+--	PORT
+--	(
+--		FB_ADR		    : IN std_logic_vector(31 DOWNTO 0);
+--		MAIN_CLK	    : IN std_logic;
+--		nFB_CS1		    : IN std_logic;
+--		nFB_CS2		    : IN std_logic;
+--		nFB_CS3		    : IN std_logic;
+--		nFB_WR		    : IN std_logic;
+--		FB_SIZE0	    : IN std_logic;
+--		FB_SIZE1	    : IN std_logic;
+--		nRSTO		    : IN std_logic;
+--		nFB_OE		    : IN std_logic;
+--		FB_ALE		    : IN std_logic;
+--		DDRCLK		    : IN std_logic_vector(3 DOWNTO 0);
+--		DDR_SYNC_66M	: IN std_logic;
+--		CLK33M		    : IN std_logic;
+--		CLK25M		    : IN std_logic;
+--		CLK_VIDEO		: IN std_logic;
+--		VR_D		    : IN std_logic_vector(8 DOWNTO 0);
+--		VR_BUSY		    : IN std_logic;
+--		VG		        : OUT std_logic_vector(7 DOWNTO 0);
+--		VB		        : OUT std_logic_vector(7 DOWNTO 0);
+--		VR		        : OUT std_logic_vector(7 DOWNTO 0);
+--		nBLANK		    : OUT std_logic;
+--		VA		        : OUT std_logic_vector(12 DOWNTO 0);
+--		nVWE		    : OUT std_logic;
+--		nVCAS		    : OUT std_logic;
+--		nVRAS		    : OUT std_logic;
+--		nVCS		    : OUT std_logic;
+--		VDM		        : OUT std_logic_vector(3 DOWNTO 0);
+--		nPD_VGA		    : OUT std_logic;
+--		VCKE		    : OUT std_logic;
+--		VSYNC		    : OUT std_logic;
+--		HSYNC		    : OUT std_logic;
+--		nSYNC		    : OUT std_logic;
+--		VIDEO_TA		: OUT std_logic;
+--		PIXEL_CLK		: OUT std_logic;
+--		BA		        : OUT std_logic_vector(1 DOWNTO 0);
+--		VIDEO_RECONFIG	: OUT std_logic;
+--		VR_WR		    : OUT std_logic;
+--		VR_RD		    : OUT std_logic;
+--		VDQS		    : INOUT std_logic_vector(3 DOWNTO 0);
+--		FB_AD		    : INOUT std_logic_vector(31 DOWNTO 0);
+--		VD		        : INOUT std_logic_vector(31 DOWNTO 0)
+--	);
+--    END COMPONENT video;
 BEGIN 
     nDREQ1 <= nDACK1;
     
@@ -519,7 +519,7 @@ BEGIN
         );
     
     
-    i_video : video
+    i_video : entity work.video
         PORT MAP
         (
             MAIN_CLK => MAIN_CLK,
@@ -606,7 +606,7 @@ BEGIN
     
     nWR_GATE <= not(WR_GATE);
 
-    nFB_TA <= not(Video_TA or INT_HANDLER_TA or DSP_TA or FALCON_IO_TA);
+    nFB_TA <= not(video_ta or int_handler_ta or dsp_ta or falcon_io_ta);
     
     CLK33M <= MAIN_CLK;