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fix capitalization

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This commit is contained in:
Markus Fröschle
2016-07-29 04:49:50 +00:00
parent 7bb446d5ce
commit 02e1530cce
2 changed files with 40 additions and 40 deletions
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4
FPGA_Quartus_13.1/firebee1.qsf
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@@ -677,6 +677,7 @@ set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY OFF
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK13M_q
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to i_video|i_video_mod_mux_clutctr|CLK17M_q
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name VHDL_FILE firebee_utils_pkg.vhd
set_global_assignment -name AHDL_FILE altpll_reconfig1_pllrcfg_t4q.tdf
set_global_assignment -name AHDL_FILE altpll_reconfig1.tdf
@@ -863,5 +864,4 @@ set_global_assignment -name QIP_FILE lpm_mux0.qip
set_global_assignment -name QIP_FILE lpm_shiftreg0.qip
set_global_assignment -name QIP_FILE lpm_counter1.qip
set_global_assignment -name QIP_FILE altiobuf_bidir0.qip
set_global_assignment -name VHDL_FILE flexbus_register.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name VHDL_FILE flexbus_register.vhd

76
FPGA_Quartus_13.1/flexbus_register.vhd
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@@ -1,51 +1,51 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY flexbus_register IS
GENERIC
entity flexbus_register is
generic
(
reg_width : integer := 11;
match_address : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
match_mask : std_logic_vector(31 DOWNTO 0) := (OTHERS => '1');
match_address : std_logic_vector(31 downto 0) := (others => '0');
match_mask : std_logic_vector(31 downto 0) := (others => '1');
match_fbcs : integer := 0
);
PORT
port
(
clk : IN std_logic;
fb_addr : IN std_logic_vector(31 DOWNTO 0);
fb_data : INOUT std_logic_vector(31 DOWNTO 0);
fb_cs : IN std_logic_vector(5 DOWNTO 1);
fb_wr_n : IN std_logic;
fb_ta_n : OUT std_logic;
reg_value : INOUT std_logic_vector(reg_width - 1 DOWNTO 0);
cs : OUT std_logic := '0'
clk : in std_logic;
fb_addr : in std_logic_vector(31 downto 0);
fb_data : inout std_logic_vector(31 downto 0);
fb_cs : in std_logic_vector(5 downto 1);
fb_wr_n : in std_logic;
fb_ta_n : out std_logic;
reg_value : inout std_logic_vector(reg_width - 1 downto 0);
cs : out std_logic := '0'
);
END ENTITY flexbus_register;
end entity flexbus_register;
ARCHITECTURE rtl OF flexbus_register IS
SIGNAL fbcs_match : std_logic;
SIGNAL address_match : std_logic;
BEGIN
fbcs_match <= '1' WHEN fb_cs(match_fbcs) = '1' ELSE '0';
address_match <= '1' WHEN (fb_addr and match_mask) = (match_address and match_mask) ELSE '0';
architecture rtl of flexbus_register is
signal fbcs_match : std_logic;
signal address_match : std_logic;
begin
fbcs_match <= '1' when fb_cs(match_fbcs) = '1' else '0';
address_match <= '1' when (fb_addr and match_mask) = (match_address and match_mask) else '0';
p_register_access : PROCESS(ALL)
BEGIN
IF rising_edge(clk) THEN
IF fbcs_match = '1' and address_match = '1' THEN
p_register_access : process(all)
begin
if rising_edge(clk) then
if fbcs_match = '1' and address_match = '1' then
cs <= '1';
IF fb_wr_n = '0' THEN -- write access
reg_value <= fb_data(reg_width - 1 DOWNTO 0);
ELSE -- read access
fb_data(reg_width - 1 DOWNTO 0) <= reg_value;
if fb_wr_n = '0' then -- write access
reg_value <= fb_data(reg_width - 1 downto 0);
else -- read access
fb_data(reg_width - 1 downto 0) <= reg_value;
fb_ta_n <= '0';
END IF;
ELSE
fb_data <= (OTHERS => 'Z');
end if;
else
fb_data <= (others => 'Z');
fb_ta_n <= 'Z';
cs <= '0';
END IF;
END IF;
END PROCESS p_register_access;
END ARCHITECTURE rtl;
end if;
end if;
end process p_register_access;
end architecture rtl;