78 lines
2.1 KiB
ArmAsm
78 lines
2.1 KiB
ArmAsm
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/*
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* This object file must be the first to be linked,
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* so it will be placed at the very beginning of the ROM.
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*/
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.equ MCF_MMU_MMUCR, __MMUBAR + 0
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.globl _rom_header
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.globl _rom_entry
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.extern _initialize_hardware
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.extern _rt_mbar
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/* ROM header */
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_rom_header:
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/* The first long is supposed to be the initial SP.
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* We replace it by bra.s to allow running the ROM from the first byte.
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* Then we add a fake jmp instruction for pretty disassembly.
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*/
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bra.s _rom_entry // Short jump to the real entry point
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.short 0x4ef9 // Fake jmp instruction
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/* The second long is the initial PC */
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.long _rom_entry // Real entry point
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/* ROM entry point */
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_rom_entry:
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/* disable interrupts */
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move.w #0x2700,sr
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#if !defined(MACHINE_M54455) // MCF54455 does not have the MBAR register
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/* Initialize MBAR */
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move.l #__MBAR,d0
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movec d0,MBAR
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move.l d0,_rt_mbar
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#endif
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/* mmu off */
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move.l #__MMUBAR+1,d0
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movec d0,MMUBAR
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clr.l d0
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move.l d0,MCF_MMU_MMUCR
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nop
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#if !defined(MACHINE_M54455) // MCF54455 does not have RAMBAR0 and RAMBAR1 registers */
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/* Initialize RAMBARs: locate SRAM and validate it */
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move.l #__RAMBAR0 + 0x7,d0 // supervisor only
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movec d0,RAMBAR0
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move.l #__RAMBAR1 + 0x1,d0
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movec d0,RAMBAR1
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#else
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move.l #__RAMBAR0 + 0x7,d0
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movec d0,RAMBAR
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#endif
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/* set stack pointer to end of SRAM */
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lea __SUP_SP,a7
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move.l #0,(sp)
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/*
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* Initialize the processor caches.
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* The instruction cache is fully enabled.
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* The data cache is enabled, but cache-inhibited by default.
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* Later, the MMU will fully activate the data cache for specific areas.
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* It is important to enable both caches now, otherwise cpushl would hang.
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*/
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move.l #0xa50c8120,d0
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movec d0,cacr
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andi.l #0xfefbfeff,d0 // Clear invalidate bits
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move.l d0,_rt_cacr
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/* initialize any hardware specific issues */
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bra _initialize_hardware
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