222 lines
7.4 KiB
VHDL
222 lines
7.4 KiB
VHDL
LIBRARY work;
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USE work.firebee_pkg.ALL;
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USE work.ddr2_ram_model_pkg.ALL;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE std.textio.ALL;
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ENTITY ddr_ctlr_tb IS
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END ddr_ctlr_tb;
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ARCHITECTURE beh OF ddr_ctlr_tb IS
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SIGNAL clock : STD_LOGIC := '0'; -- main clock
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SIGNAL ddr_clk : STD_LOGIC := '0'; -- ddr clock
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SIGNAL fb_adr : UNSIGNED(31 DOWNTO 0);
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SIGNAL ddr_sync_66m : STD_LOGIC := '0';
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SIGNAL fb_cs1_n : STD_LOGIC;
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SIGNAL fb_oe_n : STD_LOGIC := '1'; -- only write cycles for now
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SIGNAL fb_size0 : STD_LOGIC := '1';
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SIGNAL fb_size1 : STD_LOGIC := '1'; -- long word access
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SIGNAL fb_ale : STD_LOGIC := 'Z'; -- defined reset state
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SIGNAL fb_wr_n : STD_LOGIC;
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SIGNAL fifo_clr : STD_LOGIC;
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SIGNAL video_ram_ctr : UNSIGNED(15 DOWNTO 0);
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SIGNAL blitter_adr : UNSIGNED(31 DOWNTO 0);
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SIGNAL blitter_sig : STD_LOGIC;
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SIGNAL blitter_wr : STD_LOGIC;
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SIGNAL ddrclk0 : STD_LOGIC;
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SIGNAL clk_33m : STD_LOGIC := '0';
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SIGNAL fifo_mw : UNSIGNED (8 DOWNTO 0) := (OTHERS => '0');
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SIGNAL va : UNSIGNED(12 DOWNTO 0);
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SIGNAL vwe_n : STD_LOGIC;
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SIGNAL vras_n : STD_LOGIC;
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SIGNAL vcs_n : STD_LOGIC;
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SIGNAL vcke : STD_LOGIC;
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SIGNAL vcas_n : STD_LOGIC;
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SIGNAL fb_le : UNSIGNED(3 DOWNTO 0);
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SIGNAL fb_vdoe : UNSIGNED(3 DOWNTO 0);
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SIGNAL sr_fifo_wre : STD_LOGIC;
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SIGNAL sr_ddr_fb : STD_LOGIC;
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SIGNAL sr_ddr_wr : STD_LOGIC;
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SIGNAL sr_ddrwr_d_sel : STD_LOGIC;
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SIGNAL sr_vdmp : UNSIGNED(7 DOWNTO 0);
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SIGNAL video_ddr_ta : STD_LOGIC;
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SIGNAL sr_blitter_dack : STD_LOGIC;
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SIGNAL ba : UNSIGNED(1 DOWNTO 0);
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SIGNAL ddrwr_d_sel1 : STD_LOGIC;
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SIGNAL vdm_sel : UNSIGNED(3 DOWNTO 0);
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SIGNAL data_in : UNSIGNED(31 DOWNTO 0);
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SIGNAL data_out : UNSIGNED(31 DOWNTO 16);
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SIGNAL data_en_h : STD_LOGIC;
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SIGNAL data_en_l : STD_LOGIC;
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TYPE bus_state_t IS (S0, S1, S2, S3); -- according to state machine description on p 17-14 of the MCF ref manual
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SIGNAL bus_state : bus_state_t := S0;
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BEGIN
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i_ddr_ctrl : DDR_CTRL
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PORT map
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(
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clk_main => clock,
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ddr_sync_66m => ddr_sync_66m,
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fb_adr => fb_adr,
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fb_cs1_n => fb_cs1_n,
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fb_oe_n => fb_oe_n,
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fb_size0 => fb_size0,
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fb_size1 => fb_size1,
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fb_ale => fb_ale,
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FB_WR_n => fb_wr_n,
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fifo_clr => fifo_clr,
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video_control_register => video_ram_ctr,
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blitter_adr => blitter_adr,
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blitter_sig => blitter_sig,
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blitter_wr => blitter_wr,
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ddrclk0 => ddrclk0,
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clk_33m => clk_33m,
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fifo_mw => fifo_mw,
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va => va,
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vwe_n => vwe_n,
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vras_n => vras_n,
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vcs_n => vcs_n,
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vcke => vcke,
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vcas_n => vcas_n,
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fb_le => fb_le,
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fb_vdoe => fb_vdoe,
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sr_fifo_wre => sr_fifo_wre,
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sr_ddr_fb => sr_ddr_fb,
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sr_ddr_wr => sr_ddr_wr,
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sr_ddrwr_d_sel => sr_ddrwr_d_sel,
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sr_vdmp => sr_vdmp,
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video_ddr_ta => video_ddr_ta,
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sr_blitter_dack => sr_blitter_dack,
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ba => ba,
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ddrwr_d_sel1 => ddrwr_d_sel1,
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vdm_sel => vdm_sel,
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data_in => data_in,
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data_out => data_out,
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data_en_h => data_en_h,
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data_en_l => data_en_l
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);
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i_ddr2_ram_1 : ddr2_ram_model
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GENERIC MAP
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(
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VERBOSE => TRUE, -- define if you want additional debug output
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CLOCK_TICK => (1000000 / 132000) * 1 ps, -- time for one clock tick
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BA_BITS => 2, -- number of banks
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ADDR_BITS => 13, -- number of address bits
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DM_BITS => 2, -- number of data mask bits
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DQ_BITS => 8, -- number of data bits
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DQS_BITS => 2 -- number of data strobes
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)
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PORT map
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(
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ck => ddrclk0,
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ck_n => NOT ddrclk0,
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cke => vcke,
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cs_n => vcs_n,
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ras_n => vras_n,
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cas_n => vcas_n,
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we_n => vwe_n,
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dm_rdqs(0) => data_en_l,
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dm_rdqs(1) => data_en_h,
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ba => ba,
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addr => va,
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dq => sr_vdmp,
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dqs(0) => data_en_l,
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dqs(1) => data_en_h,
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odt => '0'
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);
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i_ddr2_ram_2 : ddr2_ram_model
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GENERIC MAP
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(
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VERBOSE => TRUE, -- define if you want additional debug output
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CLOCK_TICK => (1000000 / 132000) * 1 ps, -- time for one clock tick
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BA_BITS => 2, -- number of banks
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ADDR_BITS => 13, -- number of address bits
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DM_BITS => 2, -- number of data mask bits
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DQ_BITS => 8, -- number of data bits
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DQS_BITS => 2 -- number of data strobes
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)
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PORT map
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(
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ck => ddrclk0,
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ck_n => NOT ddrclk0,
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cke => vcke,
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cs_n => vcs_n,
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ras_n => vras_n,
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cas_n => vcas_n,
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we_n => vwe_n,
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dm_rdqs(0) => data_en_l,
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dm_rdqs(1) => data_en_h,
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ba => ba,
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addr => va,
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dq => sr_vdmp,
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dqs(0) => data_en_l,
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dqs(1) => data_en_h,
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odt => '0'
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);
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stimulate_main_clock : process
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BEGIN
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WAIT FOR 4.31 ns;
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clock <= NOT clock;
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END process;
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stimulate_33mHz_clock : process
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BEGIN
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WAIT FOR 30.3 ns;
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clk_33m <= NOT clk_33m;
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END process;
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stimulate_66MHz_clock : process
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BEGIN
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WAIT FOR 66.6 ns;
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ddr_sync_66m <= NOT ddr_sync_66m;
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ddrclk0 <= ddr_sync_66m;
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END process;
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stimulate : process
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VARIABLE adr : UNSIGNED (31 DOWNTO 0) := x"00000000";
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BEGIN
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WAIT UNTIL RISING_EDGE(clock);
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CASE bus_state IS
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WHEN S0 =>
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-- address phase
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fb_adr <= adr;
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fb_ale <= '1';
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fb_wr_n <= '0';
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bus_state <= S1;
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WHEN S1 =>
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-- data phase
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fb_ale <= '0';
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fb_cs1_n <= '0';
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fb_adr <= x"47114711";
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if (video_ddr_ta = '1') then
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bus_state <= S2;
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END if;
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WHEN S2 =>
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fb_cs1_n <= '0';
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bus_state <= S3;
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WHEN S3 =>
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fb_adr <= fb_adr + 4;
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bus_state <= S0;
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fb_wr_n <= 'Z';
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WHEN others =>
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REPORT("bus_state: ");
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END CASE;
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END process;
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END beh;
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