Markus Fröschle 71db27849b started implementing SAMSUNG's Verilog DDR model in VHDL

2014-12-23 22:30:23 +00:00

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ddr_ctlr_tb.vhd

converted more STD_LOGIC_VECTORs to UNSIGNED

2014-12-22 19:58:01 +00:00

ddr_ram_model.vhd

started implementing SAMSUNG's Verilog DDR model in VHDL

2014-12-23 22:30:23 +00:00

firebee_tb.vhd

started implementing SAMSUNG's Verilog DDR model in VHDL

2014-12-23 22:30:23 +00:00

k4h560438e_a2_0501.v

renamed files, fixed testbench

2014-12-23 18:20:11 +00:00