Markus Fröschle 5cb3becb63 reformatted

2014-12-27 07:07:46 +00:00

..

Blitter

reformatted

2014-12-27 07:07:46 +00:00

DDR

reformatted

2014-12-27 07:07:46 +00:00

DMA

implemented video_control_register as ALIAS

2014-12-23 11:21:56 +00:00

DSP

reenabled all modules

2014-12-24 16:11:12 +00:00

Firebee

reenabled all modules

2014-12-24 16:11:12 +00:00

Interrupt

implemented video_control_register as ALIAS

2014-12-23 11:21:56 +00:00

Peripherals

implemented video_control_register as ALIAS

2014-12-23 11:21:56 +00:00

RTC

reenabled all modules

2014-12-24 16:11:12 +00:00

Video

reformatted

2014-12-27 07:07:46 +00:00

WF5380

added to the DDR RAM model

2014-12-25 15:20:14 +00:00

WF_FDC1772_IP

got rid of BIT signal types

2014-12-24 17:07:51 +00:00

WF_MFP68901_IP

fifo_mw never got a value assigned - fixed for testbench, but still open for toplevel

2014-12-22 08:31:07 +00:00

WF_SND2149_IP

now gets accepted by Modelsim

2014-09-01 14:24:55 +00:00

WF_UART6850_IP

DDR2 simulation compiles in ModelSim

2014-12-22 05:57:17 +00:00

io_register.vhd

reformatted

2014-12-27 07:07:46 +00:00