Markus Fröschle 32d08e5ac6 added derive_clock_uncertainty

2015-09-20 19:50:38 +00:00

DSP

reformatted, forced tighter timing

2015-09-20 17:13:10 +00:00

FalconIO_SDCard_IDE_CF

reformatted, forced tighter timing

2015-09-20 17:13:10 +00:00

Interrupt_Handler

reformatted, forced tighter timing

2015-09-20 17:13:10 +00:00

Video

add false paths to design constraints

2015-09-20 16:23:52 +00:00

altddio_out0.bsf

2010-12-27 13:20:36 +00:00

altddio_out0.cmp

2010-12-27 13:20:36 +00:00

altddio_out0.inc

2010-12-27 13:20:36 +00:00

altddio_out0.ppf

2010-12-27 13:20:36 +00:00

altddio_out0.qip

2010-12-27 13:20:36 +00:00

altddio_out0.vhd

2010-12-27 13:20:36 +00:00

altddio_out3.bsf

2010-12-27 13:20:36 +00:00

altddio_out3.cmp

2010-12-27 13:20:36 +00:00

altddio_out3.inc

2010-12-27 13:20:36 +00:00

altddio_out3.ppf

2010-12-27 13:20:36 +00:00

altddio_out3.qip

2010-12-27 13:20:36 +00:00

altddio_out3.vhd

2010-12-27 13:20:36 +00:00

altpll0.bsf

2010-12-27 13:20:36 +00:00

altpll0.cmp

2010-12-27 13:20:36 +00:00

altpll0.inc

2010-12-27 13:20:36 +00:00

altpll0.ppf

2010-12-27 13:20:36 +00:00

altpll0.qip

2010-12-27 13:20:36 +00:00

altpll0.vhd

2010-12-27 13:20:36 +00:00

altpll1.bsf

2010-12-27 13:20:36 +00:00

altpll1.cmp

2010-12-27 13:20:36 +00:00

altpll1.inc

2010-12-27 13:20:36 +00:00

altpll1.ppf

2010-12-27 13:20:36 +00:00

altpll1.qip

2010-12-27 13:20:36 +00:00

altpll1.vhd

2010-12-27 13:20:36 +00:00

altpll2.bsf

2010-12-27 13:20:36 +00:00

altpll2.cmp

2010-12-27 13:20:36 +00:00

altpll2.inc

2010-12-27 13:20:36 +00:00

altpll2.ppf

2010-12-27 13:20:36 +00:00

altpll2.qip

2010-12-27 13:20:36 +00:00

altpll2.vhd

2010-12-27 13:20:36 +00:00

altpll3.bsf

add false paths to design constraints

2015-09-20 16:23:52 +00:00

altpll3.cmp

add false paths to design constraints

2015-09-20 16:23:52 +00:00

altpll3.inc

add false paths to design constraints

2015-09-20 16:23:52 +00:00

altpll3.ppf

add false paths to design constraints

2015-09-20 16:23:52 +00:00

altpll3.qip

add false paths to design constraints

2015-09-20 16:23:52 +00:00

altpll3.vhd

add false paths to design constraints

2015-09-20 16:23:52 +00:00

altpll4.bsf

2010-12-27 13:20:36 +00:00

altpll4.cmp

2010-12-27 13:20:36 +00:00

altpll4.inc

2010-12-27 13:20:36 +00:00

altpll4.mif

2010-12-27 13:20:36 +00:00

altpll4.ppf

2010-12-27 13:20:36 +00:00

altpll4.qip

2010-12-27 13:20:36 +00:00

altpll4.tdf

2010-12-27 13:20:36 +00:00

altpll_reconfig0.bsf

2010-12-27 13:20:36 +00:00

altpll_reconfig0.qip

2010-12-27 13:20:36 +00:00

altpll_reconfig1_pllrcfg_bju.tdf

2010-12-27 13:20:36 +00:00

altpll_reconfig1_pllrcfg_t4q.tdf

2010-12-27 13:20:36 +00:00

altpll_reconfig1.bsf

2010-12-27 13:20:36 +00:00

altpll_reconfig1.cmp

2010-12-27 13:20:36 +00:00

altpll_reconfig1.inc

2010-12-27 13:20:36 +00:00

altpll_reconfig1.qip

2010-12-27 13:20:36 +00:00

altpll_reconfig1.tdf

2010-12-27 13:20:36 +00:00

Coldari1.qsf

2010-12-27 13:20:36 +00:00

firebee1_assignment_defaults.qdf

2010-12-27 13:20:36 +00:00

firebee1.bdf

upgrade lpm components

2015-09-20 18:08:31 +00:00

firebee1.dpf

2010-12-27 13:20:36 +00:00

firebee1.qsf

reformatted, forced tighter timing

2015-09-20 17:13:10 +00:00

firebee1.qws

added derive_clock_uncertainty

2015-09-20 19:50:38 +00:00

firebee1.sdc

added derive_clock_uncertainty

2015-09-20 19:50:38 +00:00

firebeei1.qpf

2010-12-27 13:20:36 +00:00

firebeei1.qws

2010-12-27 13:20:36 +00:00

lpm_bustri_BYT.bsf

2010-12-27 13:20:36 +00:00

lpm_bustri_BYT.cmp

2010-12-27 13:20:36 +00:00

lpm_bustri_BYT.inc

2010-12-27 13:20:36 +00:00

lpm_bustri_BYT.qip

2010-12-27 13:20:36 +00:00

lpm_bustri_BYT.vhd

2010-12-27 13:20:36 +00:00

lpm_bustri_LONG.bsf

2010-12-27 13:20:36 +00:00

lpm_bustri_LONG.cmp

2010-12-27 13:20:36 +00:00

lpm_bustri_LONG.inc

2010-12-27 13:20:36 +00:00

lpm_bustri_LONG.qip

2010-12-27 13:20:36 +00:00

lpm_bustri_LONG.vhd

2010-12-27 13:20:36 +00:00

lpm_bustri_WORD.bsf

2010-12-27 13:20:36 +00:00

lpm_bustri_WORD.cmp

2010-12-27 13:20:36 +00:00

lpm_bustri_WORD.inc

2010-12-27 13:20:36 +00:00

lpm_bustri_WORD.qip

2010-12-27 13:20:36 +00:00

lpm_bustri_WORD.vhd

2010-12-27 13:20:36 +00:00

lpm_counter0.bsf

2010-12-27 13:20:36 +00:00

lpm_counter0.cmp

2010-12-27 13:20:36 +00:00

lpm_counter0.qip

2010-12-27 13:20:36 +00:00

lpm_counter0.vhd

2010-12-27 13:20:36 +00:00

lpm_latch0.bsf

2010-12-27 13:20:36 +00:00

lpm_latch0.cmp

2010-12-27 13:20:36 +00:00

lpm_latch0.qip

2010-12-27 13:20:36 +00:00

lpm_latch0.vhd

2010-12-27 13:20:36 +00:00

UNUSED

2010-12-27 13:20:36 +00:00

Description

FireBee's old SVN AtariForge repository (historical backup)

10 MiB

Languages

C 63%

VHDL 24.4%

Verilog 10.1%

Assembly 1.9%

PHP 0.3%

Other 0.2%