171 lines
7.7 KiB
VHDL
171 lines
7.7 KiB
VHDL
----------------------------------------------------------------------
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---- ----
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---- YM2149 compatible sound generator. ----
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---- ----
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---- This file is part of the SUSKA ATARI clone project. ----
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---- http://www.experiment-s.de ----
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---- ----
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---- Description: ----
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---- Model of the ST or STE's YM2149 sound generator. ----
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---- This IP core of the sound generator differs slightly from ----
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---- the original. Firstly it is a synchronous design without any ----
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---- latches (like assumed in the original chip). This required ----
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---- the introduction of a system adequate clock. In detail this ----
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---- SYS_CLK should on the one hand be fast enough to meet the ----
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---- timing requirements of the system's bus cycle and should one ----
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---- the other hand drive the PWM modules correctly. To meet both ----
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---- a SYS_CLK of 16MHz or above is recommended. ----
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---- Secondly, the original chip has an implemented DA converter. ----
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---- This feature is not possible in today's FPGAs. Therefore the ----
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---- converter is replaced by pulse width modulators. This solu- ----
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---- tion is very simple in comparison to other approaches like ----
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---- external DA converters with wave tables etc. The soltution ----
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---- with the pulse width modulators is probably not as accurate ----
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---- DAs with wavetables. For a detailed descrition of the hard- ----
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---- ware PWM filter look at the end of the wave file, where the ----
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---- pulse width modulators can be found. ----
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---- For a proper operation it is required, that the wave clock ----
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---- is lower than the system clock. A good choice is for example ----
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---- 2MHz for the wave clock and 16MHz for the system clock. ----
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---- ----
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---- Main module file. ----
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---- ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2006 Wolfgang Foerster ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.gnu.org/licenses/lgpl.html ----
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---- ----
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----------------------------------------------------------------------
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--
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-- Revision History
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--
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-- Revision 2K6A 2006/06/03 WF
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-- Initial Release.
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-- Revision 2K6B 2006/11/07 WF
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-- Modified Source to compile with the Xilinx ISE.
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-- Revision 2K8B 2008/12/24 WF
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-- Rewritten this top level file as a wrapper for the top_soc file.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use work.wf2149ip_pkg.all;
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entity WF2149IP_TOP is
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port(
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SYS_CLK : in std_logic; -- Read the inforation in the header!
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RESETn : in std_logic;
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WAV_CLK : in std_logic; -- Read the inforation in the header!
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SELn : in std_logic;
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BDIR : in std_logic;
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BC2, BC1 : in std_logic;
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A9n, A8 : in std_logic;
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DA : inout std_logic_vector(7 downto 0);
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IO_A : inout std_logic_vector(7 downto 0);
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IO_B : inout std_logic_vector(7 downto 0);
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OUT_A : out std_logic; -- Analog (PWM) outputs.
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OUT_B : out std_logic;
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OUT_C : out std_logic
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);
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end WF2149IP_TOP;
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architecture STRUCTURE of WF2149IP_TOP is
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component WF2149IP_TOP_SOC
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port(
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SYS_CLK : in std_logic;
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RESETn : in std_logic;
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WAV_CLK : in std_logic;
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SELn : in std_logic;
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BDIR : in std_logic;
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BC2, BC1 : in std_logic;
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A9n, A8 : in std_logic;
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DA_IN : in std_logic_vector(7 downto 0);
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DA_OUT : out std_logic_vector(7 downto 0);
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DA_EN : out std_logic;
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IO_A_IN : in std_logic_vector(7 downto 0);
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IO_A_OUT : out std_logic_vector(7 downto 0);
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IO_A_EN : out std_logic;
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IO_B_IN : in std_logic_vector(7 downto 0);
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IO_B_OUT : out std_logic_vector(7 downto 0);
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IO_B_EN : out std_logic;
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OUT_A : out std_logic;
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OUT_B : out std_logic;
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OUT_C : out std_logic
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);
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end component;
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--
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signal DA_OUT : std_logic_vector(7 downto 0);
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signal DA_EN : std_logic;
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signal IO_A_IN : std_logic_vector(7 downto 0);
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signal IO_A_OUT : std_logic_vector(7 downto 0);
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signal IO_A_EN : std_logic;
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signal IO_B_IN : std_logic_vector(7 downto 0);
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signal IO_B_OUT : std_logic_vector(7 downto 0);
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signal IO_B_EN : std_logic;
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begin
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IO_A_IN <= (IO_A);
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IO_B_IN <= (IO_B);
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IO_A <= (IO_A_OUT) when IO_A_EN = '1' else (others => 'Z');
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IO_B <= (IO_B_OUT) when IO_B_EN = '1' else (others => 'Z');
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DA <= DA_OUT when DA_EN = '1' else (others => 'Z');
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I_SOUND: WF2149IP_TOP_SOC
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port map(SYS_CLK => SYS_CLK,
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RESETn => RESETn,
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WAV_CLK => WAV_CLK,
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SELn => SELn,
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BDIR => BDIR,
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BC2 => BC2,
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BC1 => BC1,
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A9n => A9n,
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A8 => A8,
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DA_IN => DA,
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DA_OUT => DA_OUT,
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DA_EN => DA_EN,
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IO_A_IN => IO_A_IN,
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IO_A_OUT => IO_A_OUT,
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IO_A_EN => IO_A_EN,
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IO_B_IN => IO_B_IN,
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IO_B_OUT => IO_B_OUT,
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IO_B_EN => IO_B_EN,
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OUT_A => OUT_A,
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OUT_B => OUT_B,
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OUT_C => OUT_C
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);
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end STRUCTURE;
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