Markus Fröschle 282c631601 added false_path to CLK_MAIN

2014-08-17 08:43:43 +00:00

..

backend/Altera/Firebee

added false_path to CLK_MAIN

2014-08-17 08:43:43 +00:00

rtl/vhdl

fixed missing (not "translated" from the original .tdf) statements

2014-08-14 05:33:56 +00:00

testbenches

started simulator for DDR RAM

2014-06-16 14:35:54 +00:00