for ITLB misses, map following page also since sometimes (prefetch?) the

fault PC reported by the access error exceptions seems to be off a few instructions.
lowered interrupt mask where not needed
2014-09-28 16:44:39 +00:00 · 2014-09-28 16:36:55 +00:00 · 2014-09-28 16:04:15 +00:00 · 2014-09-28 12:31:14 +00:00 · 2014-09-28 11:27:07 +00:00 · 2014-09-27 06:19:43 +00:00
252 changed files with 66636 additions and 12786 deletions
--- a/.cproject
+++ b/.cproject
@@ -1,263 +0,0 @@
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--- a/.gdbinit
+++ b/.gdbinit
@@ -1,10 +1,16 @@
 #set disassemble-next-line on
 define tr
+	#!killall m68k-bdm-gdbserver
 	target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3
-	monitor bdm-reset
+	#target remote localhost:1234
+	#target remote | m68k-bdm-gdbserver pipe /dev/tblcf3
+	#target dbug /dev/ttyS0
+	#monitor bdm-reset
 end
 define tbtr
 	target remote | m68k-bdm-gdbserver pipe /dev/tblcf3
 end
 source mcf5474.gdb
+set breakpoint auto-hw
+

--- a/.indent.pro
+++ b/.indent.pro
@@ -0,0 +1,22 @@
+-bad
+-bap
+-bbb
+-bbo
+-bl
+-blf
+-bli0
+-bls
+-bs
+-cbi0
+-cdb
+-cli4
+-cs
+-i4
+-lp
+-saf
+-sai
+-saw
+-ts4
+-npcs
+-npsl
+
--- a/.project
+++ b/.project
@@ -1,77 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<projectDescription>
-	<name>BaS_gcc</name>
-	<comment></comment>
-	<projects>
-	</projects>
-	<buildSpec>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
-			<triggers>clean,full,incremental,</triggers>
-			<arguments>
-				<dictionary>
-					<key>?name?</key>
-					<value></value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.append_environment</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
-					<value>all</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.buildArguments</key>
-					<value></value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.buildCommand</key>
-					<value>make</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
-					<value>clean</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.contents</key>
-					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
-					<value>all</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.stopOnError</key>
-					<value>true</value>
-				</dictionary>
-				<dictionary>
-					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
-					<value>true</value>
-				</dictionary>
-			</arguments>
-		</buildCommand>
-		<buildCommand>
-			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
-			<arguments>
-			</arguments>
-		</buildCommand>
-	</buildSpec>
-	<natures>
-		<nature>org.eclipse.cdt.core.cnature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
-		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
-	</natures>
-</projectDescription>
--- a/.settings/org.eclipse.cdt.codan.core.prefs
+++ b/.settings/org.eclipse.cdt.codan.core.prefs
@@ -1,68 +0,0 @@
-eclipse.preferences.version=1
-org.eclipse.cdt.codan.checkers.errnoreturn=Warning
-org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},implicit\=>false}
-org.eclipse.cdt.codan.checkers.errreturnvalue=Error
-org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.checkers.noreturn=Error
-org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},implicit\=>false}
-org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error
-org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error
-org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning
-org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error
-org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem=Warning
-org.eclipse.cdt.codan.internal.checkers.CaseBreakProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},no_break_comment\=>"no break",last_case_param\=>true,empty_case_param\=>false}
-org.eclipse.cdt.codan.internal.checkers.CatchByReference=Warning
-org.eclipse.cdt.codan.internal.checkers.CatchByReference.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},unknown\=>false,exceptions\=>()}
-org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem=Error
-org.eclipse.cdt.codan.internal.checkers.CircularReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization=Warning
-org.eclipse.cdt.codan.internal.checkers.ClassMembersInitialization.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},skip\=>true}
-org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error
-org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error
-org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error
-org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error
-org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error
-org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error
-org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error
-org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=Info
-org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},pattern\=>"^[a-z]",macro\=>true,exceptions\=>()}
-org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning
-org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.OverloadProblem=Error
-org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem=Error
-org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem=Error
-org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning
-org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning
-org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning
-org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true,exceptions\=>()}
-org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning
-org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},paramNot\=>false}
-org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning
-org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},else\=>false,afterelse\=>false}
-org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error
-org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning
-org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true}
-org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning
-org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true}
-org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning
-org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},macro\=>true,exceptions\=>("@(\#)","$Id")}
-org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error
-org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true}}
-useParentScope=false
--- a/.settings/org.eclipse.cdt.core.prefs
+++ b/.settings/org.eclipse.cdt.core.prefs
@@ -1,173 +0,0 @@
-eclipse.preferences.version=1
-indexer/filesToParseUpFront=cstdarg, stdarg.h, stddef.h, sys/resource.h, ctime, sys/types.h, signal.h, cstdio
-indexer/indexAllFiles=true
-indexer/indexOnOpen=true
-indexer/indexUnusedHeadersWithDefaultLang=true
-indexer/indexerId=org.eclipse.cdt.core.fastIndexer
-indexer/skipFilesLargerThanMB=80
-indexer/skipImplicitReferences=false
-indexer/skipMacroReferences=false
-indexer/skipReferences=false
-indexer/skipTypeReferences=false
-indexer/useHeuristicIncludeResolution=true
-org.eclipse.cdt.core.formatter.alignment_for_arguments_in_method_invocation=16
-org.eclipse.cdt.core.formatter.alignment_for_assignment=16
-org.eclipse.cdt.core.formatter.alignment_for_base_clause_in_type_declaration=80
-org.eclipse.cdt.core.formatter.alignment_for_binary_expression=16
-org.eclipse.cdt.core.formatter.alignment_for_compact_if=0
-org.eclipse.cdt.core.formatter.alignment_for_conditional_expression=80
-org.eclipse.cdt.core.formatter.alignment_for_conditional_expression_chain=18
-org.eclipse.cdt.core.formatter.alignment_for_constructor_initializer_list=0
-org.eclipse.cdt.core.formatter.alignment_for_declarator_list=16
-org.eclipse.cdt.core.formatter.alignment_for_enumerator_list=48
-org.eclipse.cdt.core.formatter.alignment_for_expression_list=0
-org.eclipse.cdt.core.formatter.alignment_for_expressions_in_array_initializer=16
-org.eclipse.cdt.core.formatter.alignment_for_member_access=0
-org.eclipse.cdt.core.formatter.alignment_for_overloaded_left_shift_chain=16
-org.eclipse.cdt.core.formatter.alignment_for_parameters_in_method_declaration=16
-org.eclipse.cdt.core.formatter.alignment_for_throws_clause_in_method_declaration=16
-org.eclipse.cdt.core.formatter.brace_position_for_array_initializer=next_line
-org.eclipse.cdt.core.formatter.brace_position_for_block=next_line
-org.eclipse.cdt.core.formatter.brace_position_for_block_in_case=next_line
-org.eclipse.cdt.core.formatter.brace_position_for_method_declaration=next_line
-org.eclipse.cdt.core.formatter.brace_position_for_namespace_declaration=next_line
-org.eclipse.cdt.core.formatter.brace_position_for_switch=next_line
-org.eclipse.cdt.core.formatter.brace_position_for_type_declaration=next_line
-org.eclipse.cdt.core.formatter.comment.min_distance_between_code_and_line_comment=1
-org.eclipse.cdt.core.formatter.comment.preserve_white_space_between_code_and_line_comments=false
-org.eclipse.cdt.core.formatter.compact_else_if=true
-org.eclipse.cdt.core.formatter.continuation_indentation=2
-org.eclipse.cdt.core.formatter.continuation_indentation_for_array_initializer=2
-org.eclipse.cdt.core.formatter.format_guardian_clause_on_one_line=false
-org.eclipse.cdt.core.formatter.indent_access_specifier_compare_to_type_header=false
-org.eclipse.cdt.core.formatter.indent_access_specifier_extra_spaces=0
-org.eclipse.cdt.core.formatter.indent_body_declarations_compare_to_access_specifier=true
-org.eclipse.cdt.core.formatter.indent_body_declarations_compare_to_namespace_header=false
-org.eclipse.cdt.core.formatter.indent_breaks_compare_to_cases=true
-org.eclipse.cdt.core.formatter.indent_declaration_compare_to_template_header=false
-org.eclipse.cdt.core.formatter.indent_empty_lines=false
-org.eclipse.cdt.core.formatter.indent_statements_compare_to_block=true
-org.eclipse.cdt.core.formatter.indent_statements_compare_to_body=true
-org.eclipse.cdt.core.formatter.indent_switchstatements_compare_to_cases=true
-org.eclipse.cdt.core.formatter.indent_switchstatements_compare_to_switch=false
-org.eclipse.cdt.core.formatter.indentation.size=4
-org.eclipse.cdt.core.formatter.insert_new_line_after_opening_brace_in_array_initializer=do not insert
-org.eclipse.cdt.core.formatter.insert_new_line_after_template_declaration=do not insert
-org.eclipse.cdt.core.formatter.insert_new_line_at_end_of_file_if_missing=do not insert
-org.eclipse.cdt.core.formatter.insert_new_line_before_catch_in_try_statement=do not insert
-org.eclipse.cdt.core.formatter.insert_new_line_before_closing_brace_in_array_initializer=do not insert
-org.eclipse.cdt.core.formatter.insert_new_line_before_colon_in_constructor_initializer_list=do not insert
-org.eclipse.cdt.core.formatter.insert_new_line_before_else_in_if_statement=insert
-org.eclipse.cdt.core.formatter.insert_new_line_before_identifier_in_function_declaration=do not insert
-org.eclipse.cdt.core.formatter.insert_new_line_before_while_in_do_statement=do not insert
-org.eclipse.cdt.core.formatter.insert_new_line_in_empty_block=insert
-org.eclipse.cdt.core.formatter.insert_space_after_assignment_operator=insert
-org.eclipse.cdt.core.formatter.insert_space_after_binary_operator=insert
-org.eclipse.cdt.core.formatter.insert_space_after_closing_angle_bracket_in_template_arguments=insert
-org.eclipse.cdt.core.formatter.insert_space_after_closing_angle_bracket_in_template_parameters=insert
-org.eclipse.cdt.core.formatter.insert_space_after_closing_brace_in_block=insert
-org.eclipse.cdt.core.formatter.insert_space_after_closing_paren_in_cast=insert
-org.eclipse.cdt.core.formatter.insert_space_after_colon_in_base_clause=insert
-org.eclipse.cdt.core.formatter.insert_space_after_colon_in_case=insert
-org.eclipse.cdt.core.formatter.insert_space_after_colon_in_conditional=insert
-org.eclipse.cdt.core.formatter.insert_space_after_colon_in_labeled_statement=insert
-org.eclipse.cdt.core.formatter.insert_space_after_comma_in_array_initializer=insert
-org.eclipse.cdt.core.formatter.insert_space_after_comma_in_base_types=insert
-org.eclipse.cdt.core.formatter.insert_space_after_comma_in_declarator_list=insert
-org.eclipse.cdt.core.formatter.insert_space_after_comma_in_enum_declarations=insert
-org.eclipse.cdt.core.formatter.insert_space_after_comma_in_expression_list=insert
-org.eclipse.cdt.core.formatter.insert_space_after_comma_in_method_declaration_parameters=insert
-org.eclipse.cdt.core.formatter.insert_space_after_comma_in_method_declaration_throws=insert
-org.eclipse.cdt.core.formatter.insert_space_after_comma_in_method_invocation_arguments=insert
-org.eclipse.cdt.core.formatter.insert_space_after_comma_in_template_arguments=insert
-org.eclipse.cdt.core.formatter.insert_space_after_comma_in_template_parameters=insert
-org.eclipse.cdt.core.formatter.insert_space_after_opening_angle_bracket_in_template_arguments=do not insert
-org.eclipse.cdt.core.formatter.insert_space_after_opening_angle_bracket_in_template_parameters=do not insert
-org.eclipse.cdt.core.formatter.insert_space_after_opening_brace_in_array_initializer=insert
-org.eclipse.cdt.core.formatter.insert_space_after_opening_bracket=do not insert
-org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_cast=do not insert
-org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_catch=do not insert
-org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_exception_specification=do not insert
-org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_for=do not insert
-org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_if=do not insert
-org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_method_declaration=do not insert
-org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_method_invocation=do not insert
-org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_parenthesized_expression=do not insert
-org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_switch=do not insert
-org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_while=do not insert
-org.eclipse.cdt.core.formatter.insert_space_after_postfix_operator=do not insert
-org.eclipse.cdt.core.formatter.insert_space_after_prefix_operator=do not insert
-org.eclipse.cdt.core.formatter.insert_space_after_question_in_conditional=insert
-org.eclipse.cdt.core.formatter.insert_space_after_semicolon_in_for=insert
-org.eclipse.cdt.core.formatter.insert_space_after_unary_operator=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_assignment_operator=insert
-org.eclipse.cdt.core.formatter.insert_space_before_binary_operator=insert
-org.eclipse.cdt.core.formatter.insert_space_before_closing_angle_bracket_in_template_arguments=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_closing_angle_bracket_in_template_parameters=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_closing_brace_in_array_initializer=insert
-org.eclipse.cdt.core.formatter.insert_space_before_closing_bracket=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_cast=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_catch=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_exception_specification=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_for=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_if=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_method_declaration=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_method_invocation=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_parenthesized_expression=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_switch=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_while=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_colon_in_base_clause=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_colon_in_case=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_colon_in_conditional=insert
-org.eclipse.cdt.core.formatter.insert_space_before_colon_in_default=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_colon_in_labeled_statement=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_comma_in_array_initializer=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_comma_in_base_types=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_comma_in_declarator_list=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_comma_in_enum_declarations=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_comma_in_expression_list=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_comma_in_method_declaration_parameters=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_comma_in_method_declaration_throws=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_comma_in_method_invocation_arguments=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_comma_in_template_arguments=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_comma_in_template_parameters=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_opening_angle_bracket_in_template_arguments=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_opening_angle_bracket_in_template_parameters=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_array_initializer=insert
-org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_block=insert
-org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_method_declaration=insert
-org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_namespace_declaration=insert
-org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_switch=insert
-org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_type_declaration=insert
-org.eclipse.cdt.core.formatter.insert_space_before_opening_bracket=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_catch=insert
-org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_exception_specification=insert
-org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_for=insert
-org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_if=insert
-org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_method_declaration=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_method_invocation=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_parenthesized_expression=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_switch=insert
-org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_while=insert
-org.eclipse.cdt.core.formatter.insert_space_before_postfix_operator=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_prefix_operator=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_question_in_conditional=insert
-org.eclipse.cdt.core.formatter.insert_space_before_semicolon=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_semicolon_in_for=do not insert
-org.eclipse.cdt.core.formatter.insert_space_before_unary_operator=do not insert
-org.eclipse.cdt.core.formatter.insert_space_between_empty_braces_in_array_initializer=do not insert
-org.eclipse.cdt.core.formatter.insert_space_between_empty_brackets=do not insert
-org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_exception_specification=do not insert
-org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_method_declaration=do not insert
-org.eclipse.cdt.core.formatter.insert_space_between_empty_parens_in_method_invocation=do not insert
-org.eclipse.cdt.core.formatter.join_wrapped_lines=true
-org.eclipse.cdt.core.formatter.keep_else_statement_on_same_line=false
-org.eclipse.cdt.core.formatter.keep_empty_array_initializer_on_one_line=false
-org.eclipse.cdt.core.formatter.keep_imple_if_on_one_line=false
-org.eclipse.cdt.core.formatter.keep_then_statement_on_same_line=false
-org.eclipse.cdt.core.formatter.lineSplit=80
-org.eclipse.cdt.core.formatter.number_of_empty_lines_to_preserve=1
-org.eclipse.cdt.core.formatter.put_empty_statement_on_new_line=true
-org.eclipse.cdt.core.formatter.tabulation.char=tab
-org.eclipse.cdt.core.formatter.tabulation.size=4
-org.eclipse.cdt.core.formatter.use_tabs_only_for_leading_indentations=false
--- a/.settings/org.eclipse.cdt.ui.prefs
+++ b/.settings/org.eclipse.cdt.ui.prefs
@@ -1,3 +0,0 @@
-eclipse.preferences.version=1
-formatter_profile=org.eclipse.cdt.ui.default.allman_profile
-formatter_settings_version=1
--- a/.settings/org.eclipse.core.resources.prefs
+++ b/.settings/org.eclipse.core.resources.prefs
@@ -1,2 +0,0 @@
-eclipse.preferences.version=1
-encoding/<project>=UTF-8
--- a/.settings/org.eclipse.ltk.core.refactoring.prefs
+++ b/.settings/org.eclipse.ltk.core.refactoring.prefs
@@ -1,2 +0,0 @@
-eclipse.preferences.version=1
-org.eclipse.ltk.core.refactoring.enable.project.refactoring.history=false
--- a/BaS_gcc.config
+++ b/BaS_gcc.config
@@ -0,0 +1 @@
+// ADD PREDEFINED MACROS HERE!
--- a/BaS_gcc.creator
+++ b/BaS_gcc.creator
@@ -0,0 +1 @@
+[General]
--- a/BaS_gcc.files
+++ b/BaS_gcc.files
@@ -0,0 +1,271 @@
+dma/dma.c
+dma/MCD_dmaApi.c
+dma/MCD_tasks.c
+dma/MCD_tasksInit.c
+exe/basflash.c
+exe/basflash_start.c
+firebee/bas.elf
+firebee/bas.lk
+firebee/bas.map
+firebee/bas.s19
+firebee/basflash.elf
+firebee/basflash.map
+firebee/basflash.s19
+firebee/bashflash.lk
+firebee/depend
+firebee/libbas.a
+firebee/ram.elf
+firebee/ram.lk
+firebee/ram.map
+firebee/ram.s19
+flash/flash.c
+flash/s19reader.c
+fs/cc932.c
+fs/cc936.c
+fs/cc949.c
+fs/cc950.c
+fs/ccsbcs.c
+fs/ff.c
+fs/unicode.c
+if/driver_vec.c
+include/acia.h
+include/am79c874.h
+include/arp.h
+include/ati_ids.h
+include/bas_printf.h
+include/bas_string.h
+include/bas_types.h
+include/bas_utils.h
+include/bcm5222.h
+include/bootp.h
+include/cache.h
+include/diskio.h
+include/dma.h
+include/driver_mem.h
+include/driver_vec.h
+include/edid.h
+include/ehci.h
+include/eth.h
+include/exceptions.h
+include/fb.h
+include/fec.h
+include/fecbd.h
+include/ff.h
+include/ffconf.h
+include/firebee.h
+include/i2c-algo-bit.h
+include/i2c.h
+include/icmp.h
+include/ikbd.h
+include/interrupts.h
+include/ip.h
+include/m54455.h
+include/m5484l.h
+include/MCD_dma.h
+include/mcd_initiators.h
+include/MCD_progCheck.h
+include/MCD_tasksInit.h
+include/MCF5475.h
+include/MCF5475_CLOCK.h
+include/MCF5475_CTM.h
+include/MCF5475_DMA.h
+include/MCF5475_DSPI.h
+include/MCF5475_EPORT.h
+include/MCF5475_FBCS.h
+include/MCF5475_FEC.h
+include/MCF5475_GPIO.h
+include/MCF5475_GPT.h
+include/MCF5475_I2C.h
+include/MCF5475_INTC.h
+include/MCF5475_MMU.h
+include/MCF5475_PAD.h
+include/MCF5475_PCI.h
+include/MCF5475_PCIARB.h
+include/MCF5475_PSC.h
+include/MCF5475_SDRAMC.h
+include/MCF5475_SEC.h
+include/MCF5475_SIU.h
+include/MCF5475_SLT.h
+include/MCF5475_SRAM.h
+include/MCF5475_USB.h
+include/MCF5475_XLB.h
+include/mmu.h
+include/mod_devicetable.h
+include/nbuf.h
+include/net.h
+include/net_timer.h
+include/nif.h
+include/ohci.h
+include/part.h
+include/pci.h
+include/pci_ids.h
+include/queue.h
+include/radeon_reg.h
+include/radeonfb.h
+include/s19reader.h
+include/screen.h
+include/sd_card.h
+include/startcf.h
+include/sysinit.h
+include/tftp.h
+include/udp.h
+include/usb.h
+include/usb_defs.h
+include/user_io.h
+include/util.h
+include/version.h
+include/videl.h
+include/video.h
+include/wait.h
+include/x86debug.h
+include/x86decode.h
+include/x86emu.h
+include/x86emui.h
+include/x86fpu.h
+include/x86fpu_regs.h
+include/x86ops.h
+include/x86pcibios.h
+include/x86prim_asm.h
+include/x86prim_ops.h
+include/x86regs.h
+include/xhdi_sd.h
+kbd/ikbd.c
+m54455/bas.elf
+m54455/bas.lk
+m54455/bas.map
+m54455/bas.s19
+m54455/basflash.elf
+m54455/basflash.map
+m54455/basflash.s19
+m54455/bashflash.lk
+m54455/depend
+m54455/libbas.a
+m54455/ram.elf
+m54455/ram.lk
+m54455/ram.map
+m54455/ram.s19
+m5484lite/bas.elf
+m5484lite/bas.lk
+m5484lite/bas.map
+m5484lite/bas.s19
+m5484lite/basflash.elf
+m5484lite/basflash.map
+m5484lite/basflash.s19
+m5484lite/bashflash.lk
+m5484lite/depend
+m5484lite/libbas.a
+m5484lite/ram.elf
+m5484lite/ram.lk
+m5484lite/ram.map
+m5484lite/ram.s19
+net/am79c874.c
+net/arp.c
+net/bcm5222.c
+net/bootp.c
+net/fec.c
+net/fecbd.c
+net/ip.c
+net/nbuf.c
+net/net_timer.c
+net/nif.c
+net/queue.c
+net/tftp.c
+net/udp.c
+nutil/s19header
+nutil/s19header.c
+pci/ehci-hcd.c
+pci/ohci-hcd.c
+pci/pci.c
+radeon/radeon_accel.c
+radeon/radeon_base.c
+radeon/radeon_cursor.c
+radeon/radeon_monitor.c
+spi/dspi.c
+spi/mmc.c
+spi/sd_card.c
+sys/BaS.c
+sys/cache.c
+sys/driver_mem.c
+sys/exceptions.S
+sys/fault_vectors.c
+sys/init_fpga.c
+sys/interrupts.c
+sys/mmu.c
+sys/startcf.S
+sys/sysinit.c
+usb/usb.c
+usb/usb_mouse.c
+util/bas_printf.c
+util/bas_string.c
+util/printf_helper.S
+util/wait.c
+video/fbmem.c
+video/fbmodedb.c
+video/fbmon.c
+video/fnt_st_8x16.c
+video/offscreen.c
+video/vdi_fill.c
+video/videl.c
+video/video.c
+x86emu/x86biosemu.c
+x86emu/x86debug.c
+x86emu/x86decode.c
+x86emu/x86fpu.c
+x86emu/x86ops.c
+x86emu/x86ops2.c
+x86emu/x86pcibios.c
+x86emu/x86prim_ops.c
+x86emu/x86sys.c
+xhdi/xhdi_interface.c
+xhdi/xhdi_sd.c
+xhdi/xhdi_vec.S
+bas.lk.in
+bas_firebee.bdm
+bas_m5484.bdm
+basflash.lk.in
+check.bdm
+COPYING
+COPYING.LESSER
+dump.bdm
+mcf5474.gdb
+Makefile
+tos/jtagwait/Makefile
+tos/jtagwait/sources/jtagwait.c
+tos/jtagwait/include/driver_vec.h
+tos/bascook/Makefile
+tos/mcdcook/sources/bascook.c
+tos/jtagwait/include/bas_printf.h
+tos/jtagwait/include/bas_string.h
+tos/jtagwait/include/MCF5475_CLOCK.h
+tos/jtagwait/include/MCF5475_CTM.h
+tos/jtagwait/include/MCF5475_DMA.h
+tos/jtagwait/include/MCF5475_DSPI.h
+tos/jtagwait/include/MCF5475_EPORT.h
+tos/jtagwait/include/MCF5475_FBCS.h
+tos/jtagwait/include/MCF5475_FEC.h
+tos/jtagwait/include/MCF5475_GPIO.h
+tos/jtagwait/include/MCF5475_GPT.h
+tos/jtagwait/include/MCF5475_I2C.h
+tos/jtagwait/include/MCF5475_INTC.h
+tos/jtagwait/include/MCF5475_MMU.h
+tos/jtagwait/include/MCF5475_PAD.h
+tos/jtagwait/include/MCF5475_PCI.h
+tos/jtagwait/include/MCF5475_PCIARB.h
+tos/jtagwait/include/MCF5475_PSC.h
+tos/jtagwait/include/MCF5475_SDRAMC.h
+tos/jtagwait/include/MCF5475_SEC.h
+tos/jtagwait/include/MCF5475_SIU.h
+tos/jtagwait/include/MCF5475_SLT.h
+tos/jtagwait/include/MCF5475_SRAM.h
+tos/jtagwait/include/MCF5475_USB.h
+tos/jtagwait/include/MCF5475_XLB.h
+tos/jtagwait/include/MCF5475.h
+tos/jtagwait/include/driver_vec.h
+tos/jtagwait/sources/bas_printf.c
+tos/jtagwait/sources/bas_string.c
+tos/jtagwait/sources/printf_helper.S
+tos/bascook/Makefile
+tos/bascook/sources/bascook.c
+tos/Makefile
+usb/usb_hub.c
+include/usb_hub.h
--- a/BaS_gcc.includes
+++ b/BaS_gcc.includes
@@ -0,0 +1,2 @@
+include
+/usr/m68k-elf/include
--- a/1689
+++ b/1689
--- a/357
+++ b/357
@@ -1,5 +1,4 @@
-#
-# Makefile for Firebee BaS
+# # Makefile for Firebee BaS
 #
 # This Makefile is meant for cross compiling the BaS with Vincent Riviere's cross compilers.
 # If you want to compile native on an Atari (you will need at least GCC 4.6.3), set
@@ -10,7 +9,7 @@

 # can be either "Y" or "N" (without quotes). "Y" for using the m68k-elf-, "N" for using the m68k-atari-mint
 # toolchain
-COMPILE_ELF=N
+COMPILE_ELF=Y

 ifeq (Y,$(COMPILE_ELF))
 TCPREFIX=m68k-elf-
@@ -28,24 +27,32 @@ CPP=$(TCPREFIX)cpp
 OBJCOPY=$(TCPREFIX)objcopy
 AR=$(TCPREFIX)ar
 RANLIB=$(TCPREFIX)ranlib
+NATIVECC=gcc

 INCLUDE=-Iinclude
-CFLAGS=-mcpu=5474\
-	   -Wall\
-	   -g\
-	   -Wno-multichar\
-	   -Winline\
-	   -O \
-	   -fomit-frame-pointer\
-	   -fno-strict-aliasing\
-	   -ffreestanding\
-	   -fleading-underscore\
-	   -Wa,--register-prefix-optional
+CFLAGS=-mcpu=5474 \
+		-Wall \
+		-g3 \
+		-fomit-frame-pointer \
+		-ffreestanding \
+		-fleading-underscore \
+		-Wa,--register-prefix-optional
+CFLAGS_OPTIMIZED = -mcpu=5474 \
+		-Wall \
+		-g3 \
+		-O2 \
+		-fomit-frame-pointer \
+		-ffreestanding \
+		-fleading-underscore \
+		-Wa,--register-prefix-optional

-SRCDIR=sources
-OBJDIR=objs
+TRGTDIRS= ./firebee ./m5484lite ./m54455
+OBJDIRS=$(patsubst %, %/objs,$(TRGTDIRS))
+TOOLDIR=util

-# Linker control file. The final $(LDCFILE) is intermediate only (preprocessed  version of $(LDCSRC)
+VPATH=dma exe flash fs if kbd pci spi sys usb net util video radeon x86emu xhdi
+
+# Linker control file. The final $(LDCFILE) is intermediate only (preprocessed version of $(LDCSRC)
 LDCFILE=bas.lk
 LDRFILE=ram.lk
 LDCSRC=bas.lk.in
@@ -59,115 +66,247 @@ RAM_EXEC=ram.$(EXE)
 BASFLASH_EXEC=basflash.$(EXE)

 CSRCS= \
-	$(SRCDIR)/sysinit.c \
-	$(SRCDIR)/init_fpga.c \
-	$(SRCDIR)/bas_printf.c \
-	$(SRCDIR)/bas_string.c \
-	$(SRCDIR)/BaS.c \
-	$(SRCDIR)/cache.c \
-	$(SRCDIR)/mmc.c \
-	$(SRCDIR)/unicode.c \
-	$(SRCDIR)/ff.c \
-	$(SRCDIR)/sd_card.c \
-	$(SRCDIR)/wait.c \
-	$(SRCDIR)/s19reader.c \
-	$(SRCDIR)/flash.c \
-	$(SRCDIR)/fifo.c \
-	$(SRCDIR)/i2c_firebee.c \
-	$(SRCDIR)/usb.c \
-	$(SRCDIR)/usb_kbd.c \
-	$(SRCDIR)/usb_mem.c \
-	$(SRCDIR)/usb_mouse.c \
-	$(SRCDIR)/usb_storage.c \
-	$(SRCDIR)/ehci-hcd.c \
-	$(SRCDIR)/ohci-hcd.c \
-	$(SRCDIR)/flash.c \
-	$(SRCDIR)/xhdi_sd.c \
-	$(SRCDIR)/xhdi_interface.c
+	sysinit.c \
+	init_fpga.c \
+	fault_vectors.c \
+	interrupts.c \
+	bas_printf.c \
+	bas_string.c \
+	BaS.c \
+	cache.c \
+	mmu.c \
+	mmc.c \
+	unicode.c \
+	ff.c \
+	sd_card.c \
+	wait.c \
+	s19reader.c \
+	flash.c \
+	dma.c \
+	xhdi_sd.c \
+	xhdi_interface.c \
+	pci.c \
+	dspi.c \
+	driver_vec.c \
+	driver_mem.c \
+	MCD_dmaApi.c \
+	MCD_tasks.c \
+	MCD_tasksInit.c \
+	usb.c \
+	ohci-hcd.c \
+	ehci-hcd.c \
+	usb_hub.c \
+	usb_mouse.c \
+	ikbd.c \
+	\
+	nbuf.c \
+	queue.c \
+	net_timer.c \
+	am79c874.c \
+	bcm5222.c \
+	nif.c \
+	fecbd.c \
+	fec.c \
+	ip.c \
+	udp.c \
+	arp.c \
+	bootp.c \
+	tftp.c \
+	\
+	fbmem.c \
+	fbmon.c \
+	fbmodedb.c \
+	offscreen.c \
+	\
+	videl.c \
+	video.c \
+	\
+	radeon_base.c \
+	radeon_accel.c \
+	radeon_cursor.c \
+	radeon_monitor.c \
+	fnt_st_8x16.c \
+	\
+	x86decode.c \
+	x86sys.c \
+	x86debug.c \
+	x86prim_ops.c \
+	x86ops.c \
+	x86ops2.c \
+	x86fpu.c \
+	x86biosemu.c \
+	x86pcibios.c \
+	\
+	basflash.c \
+	basflash_start.c
+

 ASRCS= \
-	$(SRCDIR)/startcf.S \
-	$(SRCDIR)/printf_helper.S \
-	$(SRCDIR)/mmu.S \
-	$(SRCDIR)/exceptions.S \
-	$(SRCDIR)/supervisor.S \
-	$(SRCDIR)/illegal_instruction.S \
-	$(SRCDIR)/xhdi_vec.S
+	startcf.S \
+	exceptions.S \
+	xhdi_vec.S \
+	pci_wrappers.S

-COBJS=$(patsubst $(SRCDIR)/%.o,$(OBJDIR)/%.o,$(patsubst %.c,%.o,$(CSRCS)))
-AOBJS=$(patsubst $(SRCDIR)/%.o,$(OBJDIR)/%.o,$(patsubst %.S,%.o,$(ASRCS)))
+SRCS=$(ASRCS) $(CSRCS)
+COBJS=$(patsubst %.c,%.o,$(CSRCS))
+AOBJS=$(patsubst %.S,%.o,$(ASRCS))

 OBJS=$(COBJS) $(AOBJS)
 LIBBAS=libbas.a

-all: fls ram bfl lib
-fls: $(FLASH_EXEC)
-ram: $(RAM_EXEC)
-bfl: $(BASFLASH_EXEC)
-lib: $(LIBBAS)
+LIBS=$(patsubst %,%/$(LIBBAS),$(TRGTDIRS))

-.PHONY clean:
-	@ rm -f $(FLASH_EXEC) $(FLASH_EXEC).elf $(FLASH_EXEC).s19 \
-			$(RAM_EXEC) $(RAM_EXEC).elf $(RAM_EXEC).s19 \
-			$(BASFLASH_EXEC) $(BASFLASH_EXEC).elf $(BASFLASH_EXEC).s19 $(OBJDIR)/basflash.o $(OBJDIR)/basflash_start.o \
-			$(OBJS) $(LIBBAS) \
-			bas.lk bas.map ram.lk ram.map basflash.lk basflash.map depend 
+all: ver fls ram bfl lib tos
+fls: $(patsubst %,%/$(FLASH_EXEC),$(TRGTDIRS))
+ram: $(patsubst %,%/$(RAM_EXEC),$(TRGTDIRS))
+bfl: $(patsubst %,%/$(BASFLASH_EXEC),$(TRGTDIRS))
+lib: $(LIBS)

-$(FLASH_EXEC): TARGET_ADDRESS=0xe0000000
-$(FLASH_EXEC): LDCFILE=bas.lk
-$(FLASH_EXEC): MAPFILE=bas.map
+.PHONY: ver
+ver:
+	touch include/version.h
+.PHONY: tos
+tos:
+	(cd tos; make)

-$(RAM_EXEC): TARGET_ADDRESS=0x10000000
-$(RAM_EXEC): LDCFILE=ram.lk
-$(RAM_EXEC): MAPFILE=ram.map
+.PHONY: clean
+clean:
+	for d in $(TRGTDIRS);\
+		do rm -f $$d/*.map $$d/*.s19 $$d/*.elf $$d/*.lk $$d/*.a $$d/objs/* $$d/depend;\
+	done
+	rm -f tags

-$(BASFLASH_EXEC): TARGET_ADDRESS=0x00100000
-$(BASFLASH_EXEC): LDCFILE=basflash.lk
-$(BASFLASH_EXEC): MAPFILE=basflash.map

-# the final link stage (BaS in RAM and BaS in flash)
-$(FLASH_EXEC) $(RAM_EXEC): $(LIBBAS) $(LDCSRC)
-	$(CPP) -P -DTARGET_ADDRESS=$(TARGET_ADDRESS) -DFORMAT=$(FORMAT) $(LDCSRC) -o $(LDCFILE)
-	$(LD) --oformat $(FORMAT) -Map $(MAPFILE) --cref -T $(LDCFILE) -o $@
-ifeq ($(COMPILE_ELF),Y)
-	$(OBJCOPY) -O srec $@ $@.s19
+# flags for targets
+m5484lite/bas.$(EXE): MACHINE=MACHINE_M5484LITE
+m54455/bas.$(EXE): MACHINE=MACHINE_M54455
+firebee/bas.$(EXE): MACHINE=MACHINE_FIREBEE
+m5484lite/ram.$(EXE): MACHINE=MACHINE_M5484LITE
+m54455/ram.$(EXE): MACHINE=MACHINE_M54455
+firebee/ram.$(EXE): MACHINE=MACHINE_FIREBEE
+m5484lite/basflash.$(EXE): MACHINE=MACHINE_M5484LITE
+m54455/basflash.$(EXE): MACHINE=MACHINE_M54455
+firebee/basflash.$(EXE): MACHINE=MACHINE_FIREBEE
+
+#
+# generate pattern rules for different object files
+#
+define CC_TEMPLATE
+#ifeq (firebee,$(1))
+	#MACHINE=MACHINE_FIREBEE
+#else
+	#MACHINE=MACHINE_M5484LITE
+#endif
+
+# always optimize x86 emulator objects
+#$(1)/objs/x86decode.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
+#$(1)/objs/x86sys.o:		CFLAGS=$(CFLAGS_OPTIMIZED)
+#$(1)/objs/x86debug.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
+#$(1)/objs/x86prim_ops.o:CFLAGS=$(CFLAGS_OPTIMIZED)
+#$(1)/objs/x86ops.o:		CFLAGS=$(CFLAGS_OPTIMIZED)
+#$(1)/objs/x86ops2.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
+#$(1)/objs/x86fpu.o:		CFLAGS=$(CFLAGS_OPTIMIZED)
+#$(1)/objs/x86biosemu.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
+#$(1)/objs/x86pcibios.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
+
+$(1)/objs/%.o:%.c
+	$(CC) $$(CFLAGS) -D$$(MACHINE) $(INCLUDE) -c $$< -o $$@
+
+$(1)/objs/%.o:%.S
+	$(CC) $$(CFLAGS) -Wa,--bitwise-or -D$$(MACHINE) $(INCLUDE) -c $$< -o $$@
+endef
+$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
+
+# rules for depend
+define DEP_TEMPLATE
+ifneq (clean,$$(MAKECMDGOALS))
+include $(1)/depend
+endif
+
+ifeq (firebee,$(1))
+	MACHINE=MACHINE_FIREBEE
 else
-	objcopy -I srec -O elf32-big --alt-machine-code 4 $@ $@.elf
+	MACHINE=MACHINE_M5484LITE
 endif
+$(1)/depend:$(SRCS)
+	$(CC) $$(CFLAGS) -D$$(MACHINE) $(INCLUDE) -M $$^ | sed -e "s#^\(.*\).o:#"$(1)"/objs/\1.o:#" > $$@
+endef
+$(foreach DIR,$(TRGTDIRS),$(eval $(call DEP_TEMPLATE,$(DIR))))
+
+
+#
+# generate pattern rules for libraries
+#
+define AR_TEMPLATE
+$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
+$(1)/$(LIBBAS): $$($(1)_OBJS)
+	$(AR) rv $$@ $$?
+	$(RANLIB) $$@
+endef
+$(foreach DIR,$(TRGTDIRS),$(eval $(call AR_TEMPLATE,$(DIR))))

-# the basflash (SD-card executable called from BaS) final link stage
-$(BASFLASH_EXEC): $(OBJDIR)/basflash.o $(OBJDIR)/basflash_start.o $(LIBBAS) $(LDCBFL)
-	$(CPP) -P -DTARGET_ADDRESS=$(TARGET_ADDRESS) -DFORMAT=$(FORMAT) $(LDCBSRC) -o $(LDCFILE)
-	$(LD) --oformat $(FORMAT) -Map $(MAPFILE) --cref -T $(LDCFILE) -L. -lbas -o $@
 ifeq ($(COMPILE_ELF),Y)
-	$(OBJCOPY) -O srec $@ $@.s19
+	FORMAT_ELF=1
 else
-	objcopy -I srec -O elf32-big --alt-machine-code 4 $@ $@.elf
+	FORMAT_ELF=0
+endif
+#
+# define pattern rules for binaries
+#
+define EX_TEMPLATE
+# pattern rule for flash
+$(1)_MAPFILE=$(1)/$$(basename $$(FLASH_EXEC)).map
+$(1)/$$(FLASH_EXEC): $(1)/$(LIBBAS) $(LDCSRC)
+	$(CPP) $(INCLUDE) -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCSRC) -o $(1)/$$(LDCFILE)
+	$(LD) --oformat $$(FORMAT) -Map $$($(1)_MAPFILE) --cref -T $(1)/$$(LDCFILE) -o $$@
+ifeq ($(COMPILE_ELF),Y)
+	$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
+else
+	objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
 endif

-# (re)create library. Currently suboptimal because it rewrites the whole lib even if only a single object changed
-$(LIBBAS): $(OBJS)
-	$(AR) rv $@ $(OBJS)
-	$(RANLIB) $@
-
-# compile init_fpga with -mbitfield for testing purposes
-#$(OBJDIR)/init_fpga.o:	CFLAGS += -mbitfield
-
-# compile printf pc-relative so it can be used as well before and after copy of BaS
-$(OBJDIR)/bas_printf.o:	CFLAGS += -mpcrel
-# the same for flush_and_invalidate_cache()
-$(OBJDIR)/cache.o: CFLAGS += -mpcrel
-
-$(OBJDIR)/%.o:$(SRCDIR)/%.c
-	$(CC) -c $(CFLAGS) $(INCLUDE) $< -o $@
-
-$(OBJDIR)/%.o:$(SRCDIR)/%.S
-	$(CC) -c $(CFLAGS) -Wa,--bitwise-or $(INCLUDE) $< -o $@
-
-depend: $(ASRCS) $(CSRCS)
-		$(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e 's/^\(.*\).o:/$(OBJDIR)\/\1.o:/' > depend
-
-
-ifneq (clean,$(MAKECMDGOALS))
-include depend
+# pattern rule for RAM
+$(1)_MAPFILE_RAM=$(1)/$$(basename $$(RAM_EXEC)).map
+$(1)/$$(RAM_EXEC): $(1)/$(LIBBAS) $(LDCSRC)
+	$(CPP) $(INCLUDE) -DCOMPILE_RAM -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCSRC) -o $(1)/$$(LDRFILE)
+	$(LD) -g --oformat $$(FORMAT) -Map $$($(1)_MAPFILE_RAM) --cref -T $(1)/$$(LDRFILE) -o $$@
+ifeq ($(COMPILE_ELF),Y)
+	$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
+else
+	objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
 endif
+
+# pattern rule for basflash
+$(1)_MAPFILE_BFL=$(1)/$$(basename $$(BASFLASH_EXEC)).map
+$(1)/$$(BASFLASH_EXEC): $(1)/objs/basflash.o $(1)/objs/basflash_start.o $(1)/$(LIBBAS) $(LDCBFL)
+	$(CPP) $(INCLUDE) -P -DOBJDIR=$(1)/objs -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCBSRC) -o $(1)/$$(LDCBFS)
+	$(LD) --oformat $$(FORMAT) -Map $$($(1)_MAPFILE_BFL) --cref -T $(1)/$$(LDCFILE) -L$(1) -lbas -o $$@
+ifeq ($(COMPILE_ELF),Y)
+	$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
+else
+	objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
+endif
+endef
+$(foreach DIR,$(TRGTDIRS),$(eval $(call EX_TEMPLATE,$(DIR))))
+
+
+indent: $(CSRCS)
+	indent $<
+
+.PHONY: tags
+tags:
+	ctags $(patsubst %,%/*,$(VPATH))
+
+.PHONY: printvars
+printvars:
+	@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
+ifeq (MACHINE_M5484LITE,$$(MACHINE))
+	MNAME=m5484lite
+else ifeq (MACHINE_FIREBEE,$(MACHINE))
+	MNAME=firebee
+endif
+
+tools:
+	$(NATIVECC) $(INCLUDE) -c $(TOOLDIR)/s19header.c -o $(TOOLDIR)/s19header.o
+	$(NATIVECC) -o $(TOOLDIR)/s19header $(TOOLDIR)/s19header.o
+
--- a/bas.lk.in
+++ b/bas.lk.in
@@ -1,7 +1,31 @@
+#if defined(MACHINE_FIREBEE)
+#include "firebee.h"
+#elif defined(MACHINE_M5484LITE)
+#include "m5484l.h"
+#elif defined(MACHINE_M54455)
+#include "m54455.h"
+#else
+#error "unknown machine!"
+#endif /* MACHINE_M5484LITE */
+
+/* make bas_rom access flags rx if compiling to RAM */
+#ifdef COMPILE_RAM
+#define ROMFLAGS	WX
+#else
+#define ROMFLAGS	RX
+#endif /* COMPILE_RAM */
+
 MEMORY
 {
-   bas_rom (RX) : ORIGIN = TARGET_ADDRESS, LENGTH = 0x00100000
-   bas_ram (WX) : ORIGIN = 0x1FE00000, LENGTH = 0x00100000		/* target to copy BaS to */
+   bas_rom (ROMFLAGS) : ORIGIN = TARGET_ADDRESS, LENGTH = 0x00100000
+   /*
+	* target to copy BaS data segment to. 1M should be enough for now
+	*/
+   bas_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00200000, LENGTH = 0x00100000
+   /*
+	* driver_ram is an uncached, reserved memory area for drivers (e.g. USB) that need this type of memory
+	*/
+   driver_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00100000, LENGTH = 0x00100000
 }

 SECTIONS
@@ -9,70 +33,136 @@ SECTIONS
 	/* BaS in ROM */
 	.text :
 	{
-		objs/startcf.o(.text) /* this one is the entry point so it must be the first */
-		objs/sysinit.o(.text)
-		objs/init_fpga.o(.text)
-		objs/wait.o(.text)
+		OBJDIR/startcf.o(.text) /* this one is the entry point so it must be the first */

-#if (FORMAT == elf32-m68k)
+		OBJDIR/sysinit.o(.text)
+		OBJDIR/fault_vectors.o(.text)
+#ifdef MACHINE_FIREBEE
+		OBJDIR/init_fpga.o(.text)
+#endif /* MACHINE_FIREBEE */
+		OBJDIR/wait.o(.text)
+		OBJDIR/exceptions.o(.text)
+		OBJDIR/driver_vec.o(.text)
+		OBJDIR/interrupts.o(.text)
+		OBJDIR/mmu.o(.text)
+
+		OBJDIR/BaS.o(.text)
+		OBJDIR/pci.o(.text)
+		OBJDIR/pci_wrappers.o(.text)
+		OBJDIR/usb.o(.text)
+		OBJDIR/driver_mem.o(.text)
+		OBJDIR/usb_hub.o(.text)
+		OBJDIR/usb_mouse.o(.text)
+		OBJDIR/ohci-hcd.o(.text)
+		OBJDIR/ehci-hcd.o(.text)
+		OBJDIR/wait.o(.text)
+
+		OBJDIR/nbuf.o(.text)
+		OBJDIR/net_timer.o(.text)
+		OBJDIR/queue.o(.text)
+		OBJDIR/nif.o(.text)
+		OBJDIR/fecbd.o(.text)
+		OBJDIR/fec.o(.text)
+		OBJDIR/am79c874.o(.text)
+		OBJDIR/bcm5222.o(.text)
+		OBJDIR/ip.o(.text)
+		OBJDIR/udp.o(text)
+		OBJDIR/bootp.o(text)
+		OBJDIR/tftp.o(text)
+		OBJDIR/arp.o(text)
+
+		OBJDIR/unicode.o(.text)
+		OBJDIR/mmc.o(.text)
+		OBJDIR/ff.o(.text)
+		OBJDIR/sd_card.o(.text)
+		OBJDIR/s19reader.o(.text)
+		OBJDIR/bas_printf.o(.text)
+		OBJDIR/bas_string.o(.text)
+		OBJDIR/cache.o(.text)
+		OBJDIR/dma.o(.text)
+		OBJDIR/MCD_dmaApi.o(.text)
+		OBJDIR/MCD_tasks.o(.text)
+		OBJDIR/MCD_tasksInit.o(.text)
+
+		OBJDIR/video.o(.text)
+		OBJDIR/videl.o(.text)
+		OBJDIR/fbmem.o(.text)
+		OBJDIR/fbmon.o(.text)
+		OBJDIR/fbmodedb.o(.text)
+		OBJDIR/offscreen.o(.text)
+
+		OBJDIR/x86decode.o(.text)
+		OBJDIR/x86ops.o(.text)
+		OBJDIR/x86ops2.o(.text)
+		OBJDIR/x86fpu.o(.text)
+		OBJDIR/x86sys.o(.text)
+		OBJDIR/x86biosemu.o(.text)
+		OBJDIR/x86debug.o(.text)
+		OBJDIR/x86prim_ops.o(.text)
+		OBJDIR/x86pcibios.o(.text)
+
+		OBJDIR/radeon_base.o(.text)
+		OBJDIR/radeon_accel.o(.text)
+		OBJDIR/radeon_cursor.o(.text)
+		OBJDIR/radeon_monitor.o(.text)
+
+		OBJDIR/xhdi_sd.o(.text)
+		OBJDIR/xhdi_interface.o(.text)
+		OBJDIR/xhdi_vec.o(.text)
+
+#ifdef COMPILE_RAM
+		/*
+		 * if we compile to RAM anyway, there is no need to copy anything
+		 */
+		. = ALIGN(4);
+		__BAS_DATA_START = .;
+		*(.data)
+		__BAS_DATA_END = .;
+		__BAS_BSS_START = .;
+		*(.bss)
+		__BAS_BSS_END = .;
+#endif /* COMPILE_RAM */
+
+#if (FORMAT_ELF == 1)
 		*(.rodata)
 		*(.rodata.*)
 #endif
 	} > bas_rom

-	/* BaS in RAM */
+#if (TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS)
+	/*
+	 * put BaS .data and .bss segments to flash, but relocate it to RAM after initialize_hardware() ran
+	 */
 	.bas :
-		/* The BaS is stored in the flash, just after the init part.
-		 * Then it will be copied to its final location in the RAM.
-		 * This data must be aligned for optimal copy loop speed.
-		 */
-		AT (ALIGN(ADDR(.text) + SIZEOF(.text), 4))
+	AT (ALIGN(ADDR(.text) + SIZEOF(.text), 4))
 	{
-		objs/BaS.o(.text)
-		objs/wait.o(.text)
-		/* put other routines into the same segment (RAM) as BaS.o */ 
-		objs/unicode.o(.text)
-		objs/mmc.o(.text)
-		objs/ff.o(.text)
-		objs/sd_card.o(.text)
-		objs/s19reader.o(.text)
-		objs/bas_printf.o(.text)
-		objs/bas_string.o(.text)
-		objs/printf_helper.o(.text)
-		objs/cache.o(.text)
-		objs/mmu.o(.text)
-		objs/exceptions.o(.text)
-		objs/supervisor.o(.text)
-		objs/illegal_instruction.o(.text)
-		objs/xhdi_sd.o(.text)
-		objs/xhdi_interface.o(text)
-		objs/xhdi_vec.o(text)
+		. = ALIGN(4);		/* same alignment than AT() statement! */
+		__BAS_DATA_START = .;
 		*(.data)
+		__BAS_DATA_END = .;
+		__BAS_BSS_START = .;
 		*(.bss)
+		__BAS_BSS_END = .;

-		/* The BaS copy routine assumes that tha BaS size
-		 * is a multiple of the following value.
-		 */
 		. = ALIGN(16);
 	} > bas_ram
+#endif

-	/* The following labels are BaS routines in the flash,
-	 * before they are copied to their final location in the RAM.
-	 * This is to allow using them before and after the actual copy.
-	 * Hence they must contain only pc-relative code (compiled with -mpcrel).
-	 */
-#define BAS_LABEL_LMA(x) ((x) + (__BAS_LMA - __BAS_IN_RAM))
-	_xprintf_before_copy = BAS_LABEL_LMA(_xprintf);
-	_display_progress_before_copy = BAS_LABEL_LMA(_display_progress);
-	_flush_and_invalidate_caches_before_copy = BAS_LABEL_LMA(_flush_and_invalidate_caches);
+	.driver_memory :
+	{
+		. = ALIGN(4);
+		_driver_mem_buffer = .;
+		//. = . + DRIVER_MEM_BUFFER_SIZE;
+	} > driver_ram

 	/*
 	 * Global memory map
 	 */

-	/* SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes */
- 	___SDRAM                = 0x00000000;
- 	___SDRAM_SIZE           = 0x20000000;
+	/* SDRAM Initialization */
+	___SDRAM                = SDRAM_START;
+	___SDRAM_SIZE           = SDRAM_SIZE;
+	_SDRAM_VECTOR_TABLE		= ___SDRAM;

 	/* ST-RAM */
 	__STRAM                 = ___SDRAM;
@@ -83,42 +173,70 @@ SECTIONS

 	/* FastRAM */
 	__FASTRAM               = 0x10000000;
+	__TARGET_ADDRESS		= TARGET_ADDRESS;
+
+#if TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS
 	__FASTRAM_END           = __BAS_IN_RAM;
+#else
+	__FASTRAM_END			= TARGET_ADDRESS;
+#endif
+	__FASTRAM_SIZE			= __FASTRAM_END - __FASTRAM;

 	/* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */
-	___BOOT_FLASH           = 0xe0000000;
- 	___BOOT_FLASH_SIZE      = 0x00800000;
+	___BOOT_FLASH           = BOOTFLASH_BASE_ADDRESS;
+	___BOOT_FLASH_SIZE      = BOOTFLASH_SIZE;

+#if TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS
 	/* BaS */
 	__BAS_LMA               = LOADADDR(.bas);
 	__BAS_IN_RAM            = ADDR(.bas);
 	__BAS_SIZE              = SIZEOF(.bas);
+#else
+	/* BaS is already in RAM - no need to copy anything */
+	__BAS_IN_RAM			= __FASTRAM_END;
+	__BAS_SIZE				= 0;
+	__BAS_LMA				= __BAS_IN_RAM;
+#endif

 	/* Other flash components */
 	__FIRETOS               = 0xe0400000;
-	__EMUTOS                = 0xe0600000;
+	__EMUTOS                = EMUTOS_BASE_ADDRESS;
 	__EMUTOS_SIZE           = 0x00100000;

+	/* where FPGA data lives in flash */
+	__FPGA_CONFIG 		= 0xe0700000;
+	__FPGA_CONFIG_SIZE 	= 0x100000;
+
 	/* VIDEO RAM BASIS */
 	__VRAM                  = 0x60000000;

 	/* Memory mapped registers */
- 	__MBAR                  = 0xFF000000;
+	__MBAR                  = 0xFF000000;

 	/* 32KB on-chip System SRAM */
- 	__SYS_SRAM              = 0xFF010000;
+	__SYS_SRAM              = __MBAR + 0x10000;
 	__SYS_SRAM_SIZE         = 0x00008000;

 	/* MMU memory mapped registers */
- 	__MMUBAR                = 0xFF040000;
+	__MMUBAR                = 0xFF040000;

 	/*
-	 * 4KB on-chip Core SRAM0: -> exception table and exception stack
+	 * 4KB on-chip Core SRAM0: -> exception table
 	 */
- 	__RAMBAR0               = 0xFF100000;
- 	__RAMBAR0_SIZE          = 0x00001000;
- 	__SUP_SP                = __RAMBAR0 + __RAMBAR0_SIZE - 4;
+	__RAMBAR0               = 0xFF100000;
+	__RAMBAR0_SIZE          = 0x00001000;

+	/* 4KB on-chip Core SRAM1 */
+	__RAMBAR1               = 0xFF101000;
+	__RAMBAR1_SIZE          = 0x00001000;
+	__SUP_SP                = __RAMBAR1 + __RAMBAR1_SIZE - 4;
+
+	/*
+	 * this flag (if 1) indicates that FPGA configuration has been loaded through JTAG
+	 * and shouldn't be overwritten on boot
+	 */
+	__FPGA_JTAG_LOADED		= __RAMBAR1;
+	__FPGA_JTAG_VALID		= __RAMBAR1 + 4;
 	/* system variables */

 	/* RAMBAR0 0 to 0x7FF -> exception vectors */
@@ -140,7 +258,4 @@ SECTIONS
 	_video_sbt = __RAMBAR0 + 0x83C;
 	_rt_mbar   = __RAMBAR0 + 0x844;   	/* (c)0f */

-	/* 4KB on-chip Core SRAM1: -> modified code */
- 	__RAMBAR1               = 0xFF101000;
- 	__RAMBAR1_SIZE          = 0x00001000;
 }
--- a/bas_firebee.bdm
+++ b/bas_firebee.bdm
@@ -1,4 +1,4 @@
-#!/usr/local/bin/bdmctrl -D2
+#!/usr/local/bin/bdmctrl -D2 -v9 -d9
 #
 # firebee board initialization for bdmctrl 
 #
@@ -6,28 +6,24 @@ open $1
 reset
 sleep 10

-wait
-
-# set VBR
-#write-ctrl 0x0801 0x00000000
-sleep 10
 # Turn on MBAR at 0xFF00_0000
 write-ctrl 0x0C0F 0xFF000000

-# Turn on MMUBAR at 0xFF04_0000
-write-ctrl 0x0008	0xFF040001
+# set VBR
+write-ctrl 0x0801 0x00000000

 # Turn on RAMBAR0 at address FF10_0000 
 write-ctrl 0x0C04 0xFF100007
-sleep 10
-# Turn on RAMBAR1 at address FF10_1000 
+
+# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently)
 write-ctrl 0x0C05 0xFF101001
-sleep 10

 # Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
 write 0xFF000500 0xE0000000 4
-write 0xFF000508 0x00001180 4
+write 0xFF000508 0x00041180 4
 write 0xFF000504 0x007F0001 4
+wait
+
 # Init CS1 (Atari I/O address range)
 write 0xFF00050C 0xFFF00000 4
 write 0xFF000514 0x00002180 4
@@ -58,15 +54,19 @@ write 0xFF00010C 0x46770000 4	# SDCFG2
 write 0xFF000104 0xE10D0002 4	# SDCR + IPALL
 write 0xFF000100 0x40010000 4	# SDMR (write to LEMR)
 write 0xFF000100 0x048D0000 4	# SDMR (write to LMR)
+sleep 100
 write 0xFF000104 0xE10D0002 4	# SDCR + IPALL
 write 0xFF000104 0xE10D0004 4	# SDCR + IREF (first refresh)
 write 0xFF000104 0xE10D0004 4	# SDCR + IREF (first refresh)
 write 0xFF000100 0x008D0000 4	# SDMR (write to LMR)
 write 0xFF000104 0x710D0F00 4	# SDCR (lock SDMR and enable refresh)
-
-write 0xFF000240 0x80000000 4	# disable watchdog arbiter
-
-load -v ram.elf
-wait
 sleep 100
+
+load -v firebee/ram.elf
+write-ctrl 0x80e	0x2700
+write-ctrl 0x2	0xa50c8120
+dump-register SR
+dump-register CACR
+dump-register MBAR
 execute
+wait
--- a/bas_m5484.bdm
+++ b/bas_m5484.bdm
@@ -0,0 +1,56 @@
+#!/usr/local/bin/bdmctrl -D2 -v9 -d9
+#
+# firebee board initialization for bdmctrl 
+#
+open $1
+reset
+sleep 10
+
+wait
+
+# set VBR
+write-ctrl 0x0801 0x00000000
+dump-register VBR
+
+# Turn on MBAR at 0xFF00_0000
+write-ctrl 0x0C0F 0xFF000000
+dump-register MBAR
+
+# Turn on RAMBAR0 at address FF10_0000 
+write-ctrl 0x0C04 0xFF100007
+
+# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently)
+write-ctrl 0x0C05 0xFF101001
+
+# Init CS0 (BootFLASH @ E000_0000 - E03F_FFFF 8Mbytes)
+write 0xFF000500 0xE0000000 4
+write 0xFF000508 0x00041180 4
+write 0xFF000504 0x003F0001 4
+wait
+
+# SDRAM Initialization @ 0000_0000 - 0400_0000 64 MBytes
+write 0xFF000004 0x000002AA 4	# SDRAMDS configuration
+write 0xFF000020 0x00000019 4	# SDRAM CS0 configuration (64Mbytes 0000_0000 - 07FF_FFFF)
+write 0xFF000024 0x00000000 4	# SDRAM CS1 configuration
+write 0xFF000028 0x00000000 4	# SDRAM CS2 configuration
+write 0xFF00002C 0x00000000 4	# SDRAM CS3 configuration
+
+write 0xFF000108 0x73711630 4	# SDCFG1
+write 0xFF00010C 0x46370000 4	# SDCFG2
+
+write 0xFF000104 0xE10B0002 4	# SDCR + IPALL
+write 0xFF000100 0x40010000 4	# SDMR (write to LEMR)
+write 0xFF000100 0x058D0000 4	# SDMR (write to LMR)
+sleep 100
+write 0xFF000104 0xE10D0002 4	# SDCR + IPALL
+write 0xFF000104 0xE10D0004 4	# SDCR + IREF (first refresh)
+write 0xFF000104 0xE10D0004 4	# SDCR + IREF (first refresh)
+write 0xFF000100 0x018D0000 4	# SDMR (write to LMR)
+write 0xFF000104 0x710D0F00 4	# SDCR (lock SDMR and enable refresh)
+sleep 100
+
+load -v m5484lite/ram.elf
+execute
+# wait is _needed_ here if using the P&E BDM interface. Otherwise 
+# the Coldfire resets after some time!
+wait
--- a/basflash.lk.in
+++ b/basflash.lk.in
@@ -1,3 +1,11 @@
+#ifdef MACHINE_FIREBEE
+#include "firebee.h"
+#endif /* MACHINE_FIREBEE */
+
+#ifdef MACHINE_M5484LITE
+#include "m5484l.h"
+#endif /* MACHINE_M5484LITE */
+
 MEMORY
 {
   flasher (WX) : ORIGIN = TARGET_ADDRESS, LENGTH = 0x00100000		/* target to load basflash */
@@ -7,8 +15,8 @@ SECTIONS
 {
 	.text :
 	{
-		objs/basflash_start.o(.text)
-		objs/basflash.o(.text)
+		OBJDIR/basflash_start.o(.text)
+		OBJDIR/basflash.o(.text)

 		*(.data)
 		*(.bss)	
@@ -21,8 +29,8 @@ SECTIONS
 	}
 		
 	#define BAS_LABEL_LMA(x) ((x))
-	_xprintf_before_copy = BAS_LABEL_LMA(_xprintf);
-	_display_progress_before_copy = BAS_LABEL_LMA(_display_progress);
+	/* _xprintf_before_copy = BAS_LABEL_LMA(_xprintf); */
+	/* _display_progress_before_copy = BAS_LABEL_LMA(_display_progress); */
 	/* _flush_and_invalidate_caches_before_copy = BAS_LABEL_LMA(_flush_and_invalidate_caches); */
 	
 	/*
--- a/check.bdm
+++ b/check.bdm
@@ -0,0 +1,76 @@
+#!/usr/local/bin/bdmctrl -D2 -v9 -d9
+#
+# firebee board initialization for bdmctrl 
+#
+open $1
+reset
+
+# set VBR
+write-ctrl 0x0801 0x00000000
+# Turn on MBAR at 0xFF00_0000
+write-ctrl 0x0C0F 0xFF000000
+
+# Turn on RAMBAR0 at address FF10_0000 
+write-ctrl 0x0C04 0xFF100007
+
+# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently)
+write-ctrl 0x0C05 0xFF101001
+
+# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
+write 0xFF000500 0xE0000000 4
+write 0xFF000508 0x00041180 4
+write 0xFF000504 0x007F0001 4
+wait
+
+# Init CS1 (Atari I/O address range)
+write 0xFF00050C 0xFFF00000 4
+write 0xFF000514 0x00002180 4
+write 0xFF000510 0x000F0001 4
+# Init CS2 (FireBee 32 bit I/O address range)
+write 0xFF000518 0xF0000000 4
+write 0xFF000520 0x00002100 4
+write 0xFF00051C 0x07FF0001 4
+# Init CS3 (FireBee 16 bit I/O address range)
+write 0xFF000524 0xF8000000 4
+write 0xFF00052C 0x00000180 4
+write 0xFF000528 0x03FF0001 4
+# Init CS4 (FireBee video address range)
+write 0xFF000530 0x40000000 4
+write 0xFF000538 0x00000018 4
+write 0xFF000534 0x003F0001 4
+
+
+# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
+write 0xFF000004 0x000002AA 4	# SDRAMDS configuration
+write 0xFF000020 0x0000001A 4	# SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
+write 0xFF000024 0x0800001A 4	# SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
+write 0xFF000028 0x1000001A 4	# SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
+write 0xFF00002C 0x1800001A 4	# SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
+write 0xFF000108 0x73622830 4	# SDCFG1
+write 0xFF00010C 0x46770000 4	# SDCFG2
+
+write 0xFF000104 0xE10D0002 4	# SDCR + IPALL
+write 0xFF000100 0x40010000 4	# SDMR (write to LEMR)
+write 0xFF000100 0x048D0000 4	# SDMR (write to LMR)
+
+write 0xFF000104 0xE10D0002 4	# SDCR + IPALL
+write 0xFF000104 0xE10D0004 4	# SDCR + IREF (first refresh)
+write 0xFF000104 0xE10D0004 4	# SDCR + IREF (first refresh)
+write 0xFF000100 0x008D0000 4	# SDMR (write to LMR)
+write 0xFF000104 0x710D0F00 4	# SDCR (lock SDMR and enable refresh)
+
+dump-register SR
+write-ctrl 0x80e	0x2700
+write-ctrl 0x2	0xa50c8120
+dump-register D0
+dump-register ASID
+dump-register ACR0
+dump-register ACR1
+dump-register ACR2
+dump-register ACR3
+dump-register SR
+dump-register CACR
+dump-register RAMBAR1
+dump-register RAMBAR2
+dump-register MBAR
+dump-register 0xc05
--- a/dma/MCD_dmaApi.c
+++ b/dma/MCD_dmaApi.c
@@ -0,0 +1,975 @@
+/*
+ * File:        MCD_dmaApi.c
+ * Purpose:     Main C file for multi-channel DMA API.
+ *
+ * Notes:
+ */
+
+#include "MCD_dma.h"
+#include "MCD_tasksInit.h"
+#include "MCD_progCheck.h"
+#include "bas_types.h"
+
+/********************************************************************/
+/*
+ * This is an API-internal pointer to the DMA's registers
+ */
+dmaRegs *MCD_dmaBar;
+
+/*
+ * These are the real and model task tables as generated by the
+ * build process
+ */
+extern TaskTableEntry MCD_realTaskTableSrc[NCHANNELS];
+extern TaskTableEntry MCD_modelTaskTableSrc[NUMOFVARIANTS];
+
+/*
+ * However, this (usually) gets relocated to on-chip SRAM, at which
+ * point we access them as these tables
+ */
+volatile TaskTableEntry *MCD_taskTable;
+TaskTableEntry *MCD_modelTaskTable;
+
+/*
+ * MCD_chStatus[] is an array of status indicators for remembering
+ * whether a DMA has ever been attempted on each channel, pausing
+ * status, etc.
+ */
+static int MCD_chStatus[NCHANNELS] =
+{
+	MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
+	MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
+	MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
+	MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA
+};
+
+/*
+ * Prototypes for local functions
+ */
+static void MCD_memcpy(int *dest, int *src, uint32_t size);
+static void MCD_resmActions(int channel);
+
+/*
+ * Buffer descriptors used for storage of progress info for single Dmas
+ * Also used as storage for the DMA for CRCs for single DMAs
+ * Otherwise, the DMA does not parse these buffer descriptors
+ */
+#ifdef MCD_INCLUDE_EU
+extern MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
+#else
+MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
+#endif
+MCD_bufDesc *MCD_relocBuffDesc;
+
+/*
+ * Defines for the debug control register's functions
+ */
+#define DBG_CTL_COMP1_TASK  (0x00002000) /* have comparator 1 look for a task # */
+#define DBG_CTL_ENABLE      (DBG_CTL_AUTO_ARM    | \
+							 DBG_CTL_BREAK       | \
+							 DBG_CTL_INT_BREAK   | \
+							 DBG_CTL_COMP1_TASK)
+#define DBG_CTL_DISABLE     (DBG_CTL_AUTO_ARM    | \
+							 DBG_CTL_INT_BREAK   | \
+							 DBG_CTL_COMP1_TASK)
+#define DBG_KILL_ALL_STAT   (0xFFFFFFFF)
+
+/*
+ * Offset to context save area where progress info is stored
+ */
+#define CSAVE_OFFSET        10
+
+/*
+ * Defines for Byte Swapping
+ */
+#define MCD_BYTE_SWAP_KILLER    0xFFF8888F
+#define MCD_NO_BYTE_SWAP_ATALL  0x00040000
+
+/*
+ * Execution Unit Identifiers
+ */
+#define MAC  0  /* legacy - not used */
+#define LUAC 1  /* legacy - not used */
+#define CRC  2  /* legacy - not used */
+#define LURC 3  /* Logic Unit with CRC */
+
+/*
+ * Task Identifiers
+ */
+#define TASK_CHAINNOEU  0
+#define TASK_SINGLENOEU 1
+#ifdef MCD_INCLUDE_EU
+#define TASK_CHAINEU    2
+#define TASK_SINGLEEU   3
+#define TASK_FECRX      4
+#define TASK_FECTX      5
+#else
+#define TASK_CHAINEU    0
+#define TASK_SINGLEEU   1
+#define TASK_FECRX      2
+#define TASK_FECTX      3
+#endif
+
+/*
+ * Structure to remember which variant is on which channel
+ * TBD- need this?
+ */
+typedef struct MCD_remVariants_struct MCD_remVariant;
+struct MCD_remVariants_struct
+{
+	int remDestRsdIncr[NCHANNELS]; /* -1,0,1 */
+	int remSrcRsdIncr[NCHANNELS]; /* -1,0,1 */
+	int16_t remDestIncr[NCHANNELS]; /* DestIncr */
+	int16_t remSrcIncr[NCHANNELS]; /* srcIncr */
+	uint32_t remXferSize[NCHANNELS]; /* xferSize */
+};
+
+/*
+ * Structure to remember the startDma parameters for each channel
+ */
+MCD_remVariant MCD_remVariants;
+/********************************************************************/
+/*
+ * Function: MCD_initDma
+ * Purpose:  Initializes the DMA API by setting up a pointer to the DMA
+ *           registers, relocating and creating the appropriate task
+ *           structures, and setting up some global settings
+ * Arguments:
+ *  dmaBarAddr    - pointer to the multichannel DMA registers
+ *  taskTableDest - location to move DMA task code and structs to
+ *  flags         - operational parameters
+ * Return Value:
+ *  MCD_TABLE_UNALIGNED if taskTableDest is not 512-byte aligned
+ *  MCD_OK otherwise
+ */
+extern uint32_t MCD_funcDescTab0[];
+
+int MCD_initDma(dmaRegs *dmaBarAddr, void *taskTableDest, uint32_t flags)
+{
+	int i;
+	TaskTableEntry *entryPtr;
+
+	/* setup the local pointer to register set */
+	MCD_dmaBar = dmaBarAddr;
+
+	/* do we need to move/create a task table */
+	if ((flags & MCD_RELOC_TASKS) != 0)
+	{
+		int fixedSize;
+		uint32_t *fixedPtr;
+		/*int *tablePtr = taskTableDest;TBD*/
+		int varTabsOffset, funcDescTabsOffset, contextSavesOffset;
+		int taskDescTabsOffset;
+		int taskTableSize, varTabsSize, funcDescTabsSize, contextSavesSize;
+		int taskDescTabSize;
+
+		int i;
+
+		/* check if physical address is aligned on 512 byte boundary */
+		if (((uint32_t) taskTableDest & 0x000001ff) != 0)
+			return (MCD_TABLE_UNALIGNED);
+
+		MCD_taskTable = taskTableDest; /* set up local pointer to task Table */
+
+		/*
+		 * Create a task table:
+		 * - compute aligned base offsets for variable tables and
+		 *   function descriptor tables, then
+		 * - loop through the task table and setup the pointers
+		 * - copy over model task table with the the actual task descriptor
+		 *   tables
+		 */
+
+		taskTableSize = NCHANNELS * sizeof(TaskTableEntry);
+		/* align variable tables to size */
+		varTabsOffset = taskTableSize + (uint32_t) taskTableDest;
+		if ((varTabsOffset & (VAR_TAB_SIZE - 1)) != 0)
+			varTabsOffset = (varTabsOffset + VAR_TAB_SIZE) & (~VAR_TAB_SIZE);
+		/* align function descriptor tables */
+		varTabsSize = NCHANNELS * VAR_TAB_SIZE;
+		funcDescTabsOffset = varTabsOffset + varTabsSize;
+
+		if ((funcDescTabsOffset & (FUNCDESC_TAB_SIZE - 1)) != 0)
+			funcDescTabsOffset = (funcDescTabsOffset + FUNCDESC_TAB_SIZE)
+					& (~FUNCDESC_TAB_SIZE);
+
+		funcDescTabsSize = FUNCDESC_TAB_NUM * FUNCDESC_TAB_SIZE;
+		contextSavesOffset = funcDescTabsOffset + funcDescTabsSize;
+		contextSavesSize = (NCHANNELS * CONTEXT_SAVE_SIZE);
+		fixedSize = taskTableSize + varTabsSize + funcDescTabsSize
+				+ contextSavesSize;
+
+		/* zero the thing out */
+		fixedPtr = (uint32_t *) taskTableDest;
+		for (i = 0; i < (fixedSize / 4); i++)
+			fixedPtr[i] = 0;
+
+		entryPtr = (TaskTableEntry*) MCD_taskTable;
+		/* set up fixed pointers */
+		for (i = 0; i < NCHANNELS; i++)
+		{
+			entryPtr[i].varTab = (uint32_t) varTabsOffset; /* update ptr to local value */
+			entryPtr[i].FDTandFlags = (uint32_t) funcDescTabsOffset
+					| MCD_TT_FLAGS_DEF;
+			entryPtr[i].contextSaveSpace = (uint32_t) contextSavesOffset;
+			varTabsOffset += VAR_TAB_SIZE;
+#ifdef MCD_INCLUDE_EU /* if not there is only one, just point to the same one */
+			funcDescTabsOffset += FUNCDESC_TAB_SIZE;
+#endif
+			contextSavesOffset += CONTEXT_SAVE_SIZE;
+		}
+		/* copy over the function descriptor table */
+		for (i = 0; i < FUNCDESC_TAB_NUM; i++)
+		{
+			MCD_memcpy((void*) (entryPtr[i].FDTandFlags & ~MCD_TT_FLAGS_MASK),
+					(void*) MCD_funcDescTab0, FUNCDESC_TAB_SIZE);
+		}
+
+		/* copy model task table to where the context saves stuff leaves off*/
+		MCD_modelTaskTable = (TaskTableEntry*) contextSavesOffset;
+
+		MCD_memcpy((void*) MCD_modelTaskTable, (void*) MCD_modelTaskTableSrc,
+				NUMOFVARIANTS * sizeof(TaskTableEntry));
+
+		entryPtr = MCD_modelTaskTable; /* point to local version of
+		 model task table */
+		taskDescTabsOffset = (uint32_t) MCD_modelTaskTable
+				+ (NUMOFVARIANTS * sizeof(TaskTableEntry));
+
+		/* copy actual task code and update TDT ptrs in local model task table */
+		for (i = 0; i < NUMOFVARIANTS; i++)
+		{
+			taskDescTabSize = entryPtr[i].TDTend - entryPtr[i].TDTstart + 4;
+			MCD_memcpy((void*) taskDescTabsOffset, (void*) entryPtr[i].TDTstart,
+					taskDescTabSize);
+			entryPtr[i].TDTstart = (uint32_t) taskDescTabsOffset;
+			taskDescTabsOffset += taskDescTabSize;
+			entryPtr[i].TDTend = (uint32_t) taskDescTabsOffset - 4;
+		}
+#ifdef MCD_INCLUDE_EU /* Tack single DMA BDs onto end of code so API controls
+						 where they are since DMA might write to them */
+		MCD_relocBuffDesc = (MCD_bufDesc*)(entryPtr[NUMOFVARIANTS - 1].TDTend + 4);
+#else /* DMA does not touch them so they can be wherever and we don't need to
+		 waste SRAM on them */
+		MCD_relocBuffDesc = MCD_singleBufDescs;
+#endif
+	}
+	else
+	{
+		/* point the would-be relocated task tables and the
+		 buffer descriptors to the ones the linker generated */
+
+		if (((uint32_t) MCD_realTaskTableSrc & 0x000001ff) != 0)
+			return (MCD_TABLE_UNALIGNED);
+
+		/* need to add code to make sure that every thing else is aligned properly TBD*/
+		/* this is problematic if we init more than once or after running tasks,
+		 need to add variable to see if we have aleady init'd */
+		entryPtr = MCD_realTaskTableSrc;
+		for (i = 0; i < NCHANNELS; i++)
+		{
+			if (((entryPtr[i].varTab & (VAR_TAB_SIZE - 1)) != 0)
+					|| ((entryPtr[i].FDTandFlags & (FUNCDESC_TAB_SIZE - 1)) != 0))
+				return (MCD_TABLE_UNALIGNED);
+		}
+
+		MCD_taskTable = MCD_realTaskTableSrc;
+		MCD_modelTaskTable = MCD_modelTaskTableSrc;
+		MCD_relocBuffDesc = MCD_singleBufDescs;
+	}
+
+	/* Make all channels as totally inactive, and remember them as such: */
+
+	MCD_dmaBar->taskbar = (uint32_t) MCD_taskTable;
+	for (i = 0; i < NCHANNELS; i++)
+	{
+		MCD_dmaBar->taskControl[i] = 0x0;
+		MCD_chStatus[i] = MCD_NO_DMA;
+	}
+
+	/* Set up pausing mechanism to inactive state: */
+	MCD_dmaBar->debugComp1 = 0; /* no particular values yet for either comparator registers */
+	MCD_dmaBar->debugComp2 = 0;
+	MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
+	MCD_dmaBar->debugStatus = DBG_KILL_ALL_STAT;
+
+	/* enable or disable commbus prefetch, really need an ifdef or
+	 something to keep from trying to set this in the 8220 */
+	if ((flags & MCD_COMM_PREFETCH_EN) != 0)
+		MCD_dmaBar->ptdControl &= ~PTD_CTL_COMM_PREFETCH;
+	else
+		MCD_dmaBar->ptdControl |= PTD_CTL_COMM_PREFETCH;
+
+	return (MCD_OK);
+}
+/*********************** End of MCD_initDma() ***********************/
+
+/********************************************************************/
+/* Function:   MCD_dmaStatus
+ * Purpose:    Returns the status of the DMA on the requested channel
+ * Arguments:  channel - channel number
+ * Returns:    Predefined status indicators
+ */
+int MCD_dmaStatus(int channel)
+{
+	uint16_t tcrValue;
+
+	if ((channel < 0) || (channel >= NCHANNELS))
+		return (MCD_CHANNEL_INVALID);
+
+	tcrValue = MCD_dmaBar->taskControl[channel];
+	if ((tcrValue & TASK_CTL_EN) == 0)
+	{ /* nothing running */
+		/* if last reported with task enabled */
+		if (MCD_chStatus[channel] == MCD_RUNNING
+				|| MCD_chStatus[channel] == MCD_IDLE)
+			MCD_chStatus[channel] = MCD_DONE;
+	}
+	else /* something is running */
+	{
+		/* There are three possibilities: paused, running or idle. */
+		if (MCD_chStatus[channel] == MCD_RUNNING
+				|| MCD_chStatus[channel] == MCD_IDLE)
+		{
+			MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT;
+			/* This register is selected to know which initiator is
+			 actually asserted. */
+			if ((MCD_dmaBar->ptdDebug >> channel) & 0x1)
+				MCD_chStatus[channel] = MCD_RUNNING;
+			else
+				MCD_chStatus[channel] = MCD_IDLE;
+			/* do not change the status if it is already paused. */
+		}
+	}
+	return MCD_chStatus[channel];
+}
+/******************** End of MCD_dmaStatus() ************************/
+
+/********************************************************************/
+/* Function:    MCD_startDma
+ * Ppurpose:    Starts a particular kind of DMA
+ * Arguments:   see below
+ * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
+ */
+
+int MCD_startDma(int channel, /* the channel on which to run the DMA */
+		int8_t *srcAddr, /* the address to move data from, or physical buffer-descriptor address */
+		int16_t srcIncr, /* the amount to increment the source address per transfer */
+		int8_t *destAddr, /* the address to move data to */
+		int16_t destIncr, /* the amount to increment the destination address per transfer */
+		uint32_t dmaSize, /* the number of bytes to transfer independent of the transfer size */
+		uint32_t xferSize, /* the number bytes in of each data movement (1, 2, or 4) */
+		uint32_t initiator, /* what device initiates the DMA */
+		int priority, /* priority of the DMA */
+		uint32_t flags, /* flags describing the DMA */
+		uint32_t funcDesc /* a description of byte swapping, bit swapping, and CRC actions */
+#ifdef MCD_NEED_ADDR_TRANS
+		int8_t *srcAddrVirt /* virtual buffer descriptor address TBD*/
+#endif
+		)
+{
+	int srcRsdIncr, destRsdIncr;
+	int *cSave;
+	short xferSizeIncr;
+	int tcrCount = 0;
+#ifdef MCD_INCLUDE_EU
+	uint32_t *realFuncArray;
+#endif
+
+	if ((channel < 0) || (channel >= NCHANNELS))
+		return (MCD_CHANNEL_INVALID);
+
+	/* tbd - need to determine the proper response to a bad funcDesc when not
+	 including EU functions, for now, assign a benign funcDesc, but maybe
+	 should return an error */
+#ifndef MCD_INCLUDE_EU
+	funcDesc = MCD_FUNC_NOEU1;
+#endif
+
+#ifdef MCD_DEBUG
+	printf("startDma:Setting up params\n");
+#endif
+	/* Set us up for task-wise priority.  We don't technically need to do this on every start, but
+	 since the register involved is in the same longword as other registers that users are in control
+	 of, setting it more than once is probably preferable.  That since the documentation doesn't seem
+	 to be completely consistent about the nature of the PTD control register. */
+	MCD_dmaBar->ptdControl |= (uint16_t) 0x8000;
+#if 1 /* Not sure what we need to keep here rtm TBD */
+	/* Calculate additional parameters to the regular DMA calls. */
+	srcRsdIncr = srcIncr < 0 ? -1 : (srcIncr > 0 ? 1 : 0);
+	destRsdIncr = destIncr < 0 ? -1 : (destIncr > 0 ? 1 : 0);
+
+	xferSizeIncr = (xferSize & 0xffff) | 0x20000000;
+
+	/* Remember for each channel which variant is running. */
+	MCD_remVariants.remSrcRsdIncr[channel] = srcRsdIncr;
+	MCD_remVariants.remDestRsdIncr[channel] = destRsdIncr;
+	MCD_remVariants.remDestIncr[channel] = destIncr;
+	MCD_remVariants.remSrcIncr[channel] = srcIncr;
+	MCD_remVariants.remXferSize[channel] = xferSize;
+#endif
+
+	cSave = (int*) (MCD_taskTable[channel].contextSaveSpace) + CSAVE_OFFSET
+			+ CURRBD;
+
+#ifdef MCD_INCLUDE_EU /* may move this to EU specific calls */
+	realFuncArray = (uint32_t *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00);
+	/* Modify the LURC's normal and byte-residue-loop functions according to parameter. */
+	realFuncArray[(LURC*16)] = xferSize == 4 ? funcDesc : xferSize == 2 ? funcDesc & 0xfffff00f : funcDesc & 0xffff000f;
+	realFuncArray[(LURC*16+1)] = (funcDesc & MCD_BYTE_SWAP_KILLER) | MCD_NO_BYTE_SWAP_ATALL;
+#endif
+	/*
+	 * Write the initiator field in the TCR, and also set the initiator-hold
+	 * bit.  Note that,due to a hardware quirk, this could collide with an
+	 * MDE access to the initiator-register file, so we have to verify that the write
+	 * reads back correctly.
+	 */
+
+	MCD_dmaBar->taskControl[channel] = (initiator << 8) | TASK_CTL_HIPRITSKEN
+			| TASK_CTL_HLDINITNUM;
+
+	while (((MCD_dmaBar->taskControl[channel] & 0x1fff)
+			!= ((initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM))
+			&& (tcrCount < 1000))
+	{
+		tcrCount++;
+		/*MCD_dmaBar->ptd_tcr[channel] = (initiator << 8) | 0x0020;*/
+		MCD_dmaBar->taskControl[channel] = (initiator << 8)
+				| TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM;
+	}
+
+	MCD_dmaBar->priority[channel] = (uint8_t) priority & PRIORITY_PRI_MASK;
+
+	/* should be albe to handle this stuff with only one write to ts reg - tbd */
+	if (channel < 8 && channel >= 0)
+	{
+		MCD_dmaBar->taskSize0 &= ~(0xf << (7 - channel) * 4);
+		MCD_dmaBar->taskSize0 |= (xferSize & 3) << (((7 - channel) * 4) + 2);
+		MCD_dmaBar->taskSize0 |= (xferSize & 3) << ((7 - channel) * 4);
+	}
+	else
+	{
+		MCD_dmaBar->taskSize1 &= ~(0xf << (15 - channel) * 4);
+		MCD_dmaBar->taskSize1 |= (xferSize & 3) << (((15 - channel) * 4) + 2);
+		MCD_dmaBar->taskSize1 |= (xferSize & 3) << ((15 - channel) * 4);
+	}
+
+	/* setup task table flags/options which mostly control the line buffers */
+	MCD_taskTable[channel].FDTandFlags &= ~MCD_TT_FLAGS_MASK;
+	MCD_taskTable[channel].FDTandFlags |= (MCD_TT_FLAGS_MASK & flags);
+
+	if (flags & MCD_FECTX_DMA)
+	{
+		/* TDTStart and TDTEnd */
+		MCD_taskTable[channel].TDTstart =
+				MCD_modelTaskTable[TASK_FECTX].TDTstart;
+		MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECTX].TDTend;
+		MCD_startDmaENetXmit(srcAddr, srcAddr, destAddr, MCD_taskTable, channel);
+	}
+	else if (flags & MCD_FECRX_DMA)
+	{
+		/* TDTStart and TDTEnd */
+		MCD_taskTable[channel].TDTstart =
+				MCD_modelTaskTable[TASK_FECRX].TDTstart;
+		MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECRX].TDTend;
+		MCD_startDmaENetRcv(srcAddr, srcAddr, destAddr, MCD_taskTable, channel);
+	}
+	else if (flags & MCD_SINGLE_DMA)
+	{
+		/*
+		 * this buffer descriptor is used for storing off initial parameters for later
+		 * progress query calculation and for the DMA to write the resulting checksum
+		 * The DMA does not use this to determine how to operate, that info is passed
+		 * with the init routine
+		 */
+		MCD_relocBuffDesc[channel].srcAddr = srcAddr;
+		MCD_relocBuffDesc[channel].destAddr = destAddr;
+		MCD_relocBuffDesc[channel].lastDestAddr = destAddr; /* definitely not its final value */
+		MCD_relocBuffDesc[channel].dmaSize = dmaSize;
+		MCD_relocBuffDesc[channel].flags = 0; /* not used */
+		MCD_relocBuffDesc[channel].csumResult = 0; /* not used */
+		MCD_relocBuffDesc[channel].next = 0; /* not used */
+
+		/* Initialize the progress-querying stuff to show no progress:*/
+		((volatile int *) MCD_taskTable[channel].contextSaveSpace)[SRCPTR
+				+ CSAVE_OFFSET] = (int) srcAddr;
+		((volatile int *) MCD_taskTable[channel].contextSaveSpace)[DESTPTR
+				+ CSAVE_OFFSET] = (int) destAddr;
+		((volatile int *) MCD_taskTable[channel].contextSaveSpace)[DCOUNT
+				+ CSAVE_OFFSET] = 0;
+		((volatile int *) MCD_taskTable[channel].contextSaveSpace)[CURRBD
+				+ CSAVE_OFFSET] = (uint32_t) &(MCD_relocBuffDesc[channel]);
+		/* tbd - need to keep the user from trying to call the EU routine
+		 when MCD_INCLUDE_EU is not defined */
+		if (funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2)
+		{
+			/* TDTStart and TDTEnd */
+			MCD_taskTable[channel].TDTstart =
+					MCD_modelTaskTable[TASK_SINGLENOEU].TDTstart;
+			MCD_taskTable[channel].TDTend =
+					MCD_modelTaskTable[TASK_SINGLENOEU].TDTend;
+			MCD_startDmaSingleNoEu(srcAddr, srcIncr, destAddr, destIncr,
+					dmaSize, xferSizeIncr, flags,
+					(int *) &(MCD_relocBuffDesc[channel]), cSave, MCD_taskTable,
+					channel);
+		}
+		else
+		{
+			/* TDTStart and TDTEnd */
+			MCD_taskTable[channel].TDTstart =
+					MCD_modelTaskTable[TASK_SINGLEEU].TDTstart;
+			MCD_taskTable[channel].TDTend =
+					MCD_modelTaskTable[TASK_SINGLEEU].TDTend;
+			MCD_startDmaSingleEu(srcAddr, srcIncr, destAddr, destIncr, dmaSize,
+					xferSizeIncr, flags, (int *) &(MCD_relocBuffDesc[channel]),
+					cSave, MCD_taskTable, channel);
+		}
+	}
+	else
+	{ /* chained DMAS */
+		/* Initialize the progress-querying stuff to show no progress:*/
+#if 1 /* (!defined(MCD_NEED_ADDR_TRANS)) */
+		((volatile int *) MCD_taskTable[channel].contextSaveSpace)[SRCPTR
+				+ CSAVE_OFFSET] = (int) ((MCD_bufDesc*) srcAddr)->srcAddr;
+		((volatile int *) MCD_taskTable[channel].contextSaveSpace)[DESTPTR
+				+ CSAVE_OFFSET] = (int) ((MCD_bufDesc*) srcAddr)->destAddr;
+#else /* if using address translation, need the virtual addr of the first buffdesc */
+
+		((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
+		= (int)((MCD_bufDesc*) srcAddrVirt)->srcAddr;
+		((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
+		= (int)((MCD_bufDesc*) srcAddrVirt)->destAddr;
+#endif
+		((volatile int *) MCD_taskTable[channel].contextSaveSpace)[DCOUNT
+				+ CSAVE_OFFSET] = 0;
+		((volatile int *) MCD_taskTable[channel].contextSaveSpace)[CURRBD
+				+ CSAVE_OFFSET] = (uint32_t) srcAddr;
+
+		if (funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2)
+		{
+			/*TDTStart and TDTEnd*/
+			MCD_taskTable[channel].TDTstart =
+					MCD_modelTaskTable[TASK_CHAINNOEU].TDTstart;
+			MCD_taskTable[channel].TDTend =
+					MCD_modelTaskTable[TASK_CHAINNOEU].TDTend;
+			MCD_startDmaChainNoEu((int *) srcAddr, srcIncr, destIncr, xferSize,
+					xferSizeIncr, cSave, MCD_taskTable, channel);
+		}
+		else
+		{
+			/*TDTStart and TDTEnd*/
+			MCD_taskTable[channel].TDTstart =
+					MCD_modelTaskTable[TASK_CHAINEU].TDTstart;
+			MCD_taskTable[channel].TDTend =
+					MCD_modelTaskTable[TASK_CHAINEU].TDTend;
+			MCD_startDmaChainEu((int *) srcAddr, srcIncr, destIncr, xferSize,
+					xferSizeIncr, cSave, MCD_taskTable, channel);
+		}
+	}
+	MCD_chStatus[channel] = MCD_IDLE;
+	return (MCD_OK);
+}
+
+/************************ End of MCD_startDma() *********************/
+
+/********************************************************************/
+/* Function:    MCD_XferProgrQuery
+ * Purpose:     Returns progress of DMA on requested channel
+ * Arguments:   channel - channel to retrieve progress for
+ *              progRep - pointer to user supplied MCD_XferProg struct
+ * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
+ *
+ * Notes:
+ *  MCD_XferProgrQuery() upon completing or after aborting a DMA, or
+ *  while the DMA is in progress, this function returns the first
+ *  DMA-destination address not (or not yet) used in the DMA. When
+ *  encountering a non-ready buffer descriptor, the information for
+ *  the last completed descriptor is returned.
+ *
+ *  MCD_XferProgQuery() has to avoid the possibility of getting
+ *  partially-updated information in the event that we should happen
+ *  to query DMA progress just as the DMA is updating it. It does that
+ *  by taking advantage of the fact context is not saved frequently for
+ *  the most part. We therefore read it at least twice until we get the
+ *  same information twice in a row.
+ *
+ *  Because a small, but not insignificant, amount of time is required
+ *  to write out the progress-query information, especially upon
+ *  completion of the DMA, it would be wise to guarantee some time lag
+ *  between successive readings of the progress-query information.
+ */
+
+/*
+ * How many iterations of the loop below to execute to stabilize values
+ */
+#define STABTIME 0
+
+int MCD_XferProgrQuery(int channel, MCD_XferProg *progRep)
+{
+	MCD_XferProg prevRep;
+	int again; /* true if we are to try again to get consistent results */
+	int i; /* used as a time-waste counter */
+	int destDiffBytes; /* Total number of bytes that we think actually got xfered. */
+	int numIterations; /* number of iterations */
+	int bytesNotXfered; /* bytes that did not get xfered. */
+	int8_t *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr;
+	int subModVal, addModVal; /* Mode values to added and subtracted from the
+	 final destAddr */
+
+	if ((channel < 0) || (channel >= NCHANNELS))
+		return (MCD_CHANNEL_INVALID);
+
+	/* Read a trial value for the progress-reporting values*/
+	prevRep.lastSrcAddr =
+			(int8_t *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR
+					+ CSAVE_OFFSET];
+	prevRep.lastDestAddr =
+			(int8_t *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR
+					+ CSAVE_OFFSET];
+	prevRep.dmaSize =
+			((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT
+					+ CSAVE_OFFSET];
+	prevRep.currBufDesc =
+			(MCD_bufDesc*) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[CURRBD
+					+ CSAVE_OFFSET];
+	/* Repeatedly reread those values until they match previous values: */
+	do
+	{
+		/* Waste a little bit of time to ensure stability: */
+		for (i = 0; i < STABTIME; i++)
+			i += i >> 2; /* make sure this loop does something so that it doesn't get optimized out */
+		/* Check them again: */
+		progRep->lastSrcAddr =
+				(int8_t *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR
+						+ CSAVE_OFFSET];
+		progRep->lastDestAddr =
+				(int8_t *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR
+						+ CSAVE_OFFSET];
+		progRep->dmaSize =
+				((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT
+						+ CSAVE_OFFSET];
+		progRep->currBufDesc =
+				(MCD_bufDesc*) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[CURRBD
+						+ CSAVE_OFFSET];
+		/* See if they match: */
+		if (prevRep.lastSrcAddr != progRep->lastSrcAddr
+				|| prevRep.lastDestAddr != progRep->lastDestAddr
+				|| prevRep.dmaSize != progRep->dmaSize
+				|| prevRep.currBufDesc != progRep->currBufDesc)
+		{
+			/* If they don't match, remember previous values and try again:*/
+			prevRep.lastSrcAddr = progRep->lastSrcAddr;
+			prevRep.lastDestAddr = progRep->lastDestAddr;
+			prevRep.dmaSize = progRep->dmaSize;
+			prevRep.currBufDesc = progRep->currBufDesc;
+			again = MCD_TRUE;
+		}
+		else
+			again = MCD_FALSE;
+	} while (again == MCD_TRUE);
+
+	/* Update the dCount, srcAddr and destAddr */
+	/* To calculate dmaCount, we consider destination address. C
+	 overs M1,P1,Z for destination */
+	switch (MCD_remVariants.remDestRsdIncr[channel])
+	{
+	case MINUS1:
+		subModVal = ((int) progRep->lastDestAddr)
+				& ((MCD_remVariants.remXferSize[channel]) - 1);
+		addModVal = ((int) progRep->currBufDesc->destAddr)
+				& ((MCD_remVariants.remXferSize[channel]) - 1);
+		LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) - addModVal;
+		LWAlignedCurrDestAddr = (progRep->lastDestAddr) - subModVal;
+		destDiffBytes = LWAlignedInitDestAddr - LWAlignedCurrDestAddr;
+		bytesNotXfered = (destDiffBytes / MCD_remVariants.remDestIncr[channel])
+				* (MCD_remVariants.remDestIncr[channel]
+						+ MCD_remVariants.remXferSize[channel]);
+		progRep->dmaSize = destDiffBytes - bytesNotXfered + addModVal
+				- subModVal;
+		break;
+	case ZERO:
+		progRep->lastDestAddr = progRep->currBufDesc->destAddr;
+		break;
+	case PLUS1:
+		/* This value has to be subtracted from the final calculated dCount. */
+		subModVal = ((int) progRep->currBufDesc->destAddr)
+				& ((MCD_remVariants.remXferSize[channel]) - 1);
+		/* These bytes are already in lastDestAddr. */
+		addModVal = ((int) progRep->lastDestAddr)
+				& ((MCD_remVariants.remXferSize[channel]) - 1);
+		LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) - subModVal;
+		LWAlignedCurrDestAddr = (progRep->lastDestAddr) - addModVal;
+		destDiffBytes = (progRep->lastDestAddr - LWAlignedInitDestAddr);
+		numIterations = (LWAlignedCurrDestAddr - LWAlignedInitDestAddr)
+				/ MCD_remVariants.remDestIncr[channel];
+		bytesNotXfered = numIterations
+				* (MCD_remVariants.remDestIncr[channel]
+						- MCD_remVariants.remXferSize[channel]);
+		progRep->dmaSize = destDiffBytes - bytesNotXfered - subModVal;
+		break;
+	default:
+		break;
+	}
+
+	/* This covers M1,P1,Z for source */
+	switch (MCD_remVariants.remSrcRsdIncr[channel])
+	{
+	case MINUS1:
+		progRep->lastSrcAddr = progRep->currBufDesc->srcAddr
+				+ (MCD_remVariants.remSrcIncr[channel]
+						* (progRep->dmaSize
+								/ MCD_remVariants.remXferSize[channel]));
+		break;
+	case ZERO:
+		progRep->lastSrcAddr = progRep->currBufDesc->srcAddr;
+		break;
+	case PLUS1:
+		progRep->lastSrcAddr = progRep->currBufDesc->srcAddr
+				+ (MCD_remVariants.remSrcIncr[channel]
+						* (progRep->dmaSize
+								/ MCD_remVariants.remXferSize[channel]));
+		break;
+	default:
+		break;
+	}
+
+	return (MCD_OK);
+}
+/******************* End of MCD_XferProgrQuery() ********************/
+
+/********************************************************************/
+/* MCD_resmActions() does the majority of the actions of a DMA resume.
+ * It is called from MCD_killDma() and MCD_resumeDma().  It has to be
+ * a separate function because the kill function has to negate the task
+ * enable before resuming it, but the resume function has to do nothing
+ * if there is no DMA on that channel (i.e., if the enable bit is 0).
+ */
+static void MCD_resmActions(int channel)
+{
+	uint32_t debugStatus;
+
+	MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
+	debugStatus = MCD_dmaBar->debugStatus;
+	MCD_dmaBar->debugStatus = debugStatus;
+	MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT; /* This register is selected to know
+	 which initiator is actually asserted. */
+	if ((MCD_dmaBar->ptdDebug >> channel) & 0x1)
+		MCD_chStatus[channel] = MCD_RUNNING;
+	else
+		MCD_chStatus[channel] = MCD_IDLE;
+}
+/********************* End of MCD_resmActions() *********************/
+
+/********************************************************************/
+/* Function:    MCD_killDma
+ * Purpose:     Halt the DMA on the requested channel, without any
+ *              intention of resuming the DMA.
+ * Arguments:   channel - requested channel
+ * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
+ *
+ * Notes:
+ *  A DMA may be killed from any state, including paused state, and it
+ *  always goes to the MCD_HALTED state even if it is killed while in
+ *  the MCD_NO_DMA or MCD_IDLE states.
+ */
+int MCD_killDma(int channel)
+{
+	/* MCD_XferProg progRep; */
+
+	if ((channel < 0) || (channel >= NCHANNELS))
+		return (MCD_CHANNEL_INVALID);
+
+	MCD_dmaBar->taskControl[channel] = 0x0;
+	MCD_resumeDma(channel);
+	/*
+	 * This must be after the write to the TCR so that the task doesn't
+	 * start up again momentarily, and before the status assignment so
+	 * as to override whatever MCD_resumeDma() may do to the channel
+	 * status.
+	 */
+	MCD_chStatus[channel] = MCD_HALTED;
+
+	/*
+	 * Update the current buffer descriptor's lastDestAddr field
+	 *
+	 * MCD_XferProgrQuery (channel, &progRep);
+	 * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
+	 */
+	return (MCD_OK);
+}
+/************************ End of MCD_killDma() **********************/
+
+/********************************************************************/
+/* Function:    MCD_continDma
+ * Purpose:     Continue a DMA which as stopped due to encountering an
+ *              unready buffer descriptor.
+ * Arguments:   channel - channel to continue the DMA on
+ * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
+ *
+ * Notes:
+ *  This routine does not check to see if there is a task which can
+ *  be continued. Also this routine should not be used with single DMAs.
+ */
+int MCD_continDma(int channel)
+{
+	if ((channel < 0) || (channel >= NCHANNELS))
+		return (MCD_CHANNEL_INVALID);
+
+	MCD_dmaBar->taskControl[channel] |= TASK_CTL_EN;
+	MCD_chStatus[channel] = MCD_RUNNING;
+
+	return (MCD_OK);
+}
+/********************** End of MCD_continDma() **********************/
+
+/*********************************************************************
+ * MCD_pauseDma() and MCD_resumeDma() below use the DMA's debug unit
+ * to freeze a task and resume it.  We freeze a task by breakpointing
+ * on the stated task.  That is, not any specific place in the task,
+ * but any time that task executes.  In particular, when that task
+ * executes, we want to freeze that task and only that task.
+ *
+ * The bits of the debug control register influence interrupts vs.
+ * breakpoints as follows:
+ * - Bits 14 and 0 enable or disable debug functions.  If enabled, you
+ *   will get the interrupt but you may or may not get a breakpoint.
+ * - Bits 2 and 1 decide whether you also get a breakpoint in addition
+ *   to an interrupt.
+ *
+ * The debug unit can do these actions in response to either internally
+ * detected breakpoint conditions from the comparators, or in response
+ * to the external breakpoint pin, or both.
+ * - Bits 14 and 1 perform the above-described functions for
+ *   internally-generated conditions, i.e., the debug comparators.
+ * - Bits 0 and 2 perform the above-described functions for external
+ *   conditions, i.e., the breakpoint external pin.
+ *
+ * Note that, although you "always" get the interrupt when you turn
+ * the debug functions, the interrupt can nevertheless, if desired, be
+ * masked by the corresponding bit in the PTD's IMR. Note also that
+ * this means that bits 14 and 0 must enable debug functions before
+ * bits 1 and 2, respectively, have any effect.
+ *
+ * NOTE: It's extremely important to not pause more than one DMA channel
+ *  at a time.
+ ********************************************************************/
+
+/********************************************************************/
+/* Function:    MCD_pauseDma
+ * Purpose:     Pauses the DMA on a given channel (if any DMA is running
+ *              on that channel).
+ * Arguments:   channel
+ * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
+ */
+int MCD_pauseDma(int channel)
+{
+	/* MCD_XferProg progRep; */
+
+	if ((channel < 0) || (channel >= NCHANNELS))
+		return (MCD_CHANNEL_INVALID);
+
+	if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
+	{
+		MCD_dmaBar->debugComp1 = channel;
+		MCD_dmaBar->debugControl = DBG_CTL_ENABLE | (1 << (channel + 16));
+		MCD_chStatus[channel] = MCD_PAUSED;
+
+		/*
+		 * Update the current buffer descriptor's lastDestAddr field
+		 *
+		 * MCD_XferProgrQuery (channel, &progRep);
+		 * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
+		 */
+	}
+	return (MCD_OK);
+}
+/************************* End of MCD_pauseDma() ********************/
+
+/********************************************************************/
+/* Function:    MCD_resumeDma
+ * Purpose:     Resumes the DMA on a given channel (if any DMA is
+ *              running on that channel).
+ * Arguments:   channel - channel on which to resume DMA
+ * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
+ */
+int MCD_resumeDma(int channel)
+{
+	if ((channel < 0) || (channel >= NCHANNELS))
+		return (MCD_CHANNEL_INVALID);
+
+	if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
+		MCD_resmActions(channel);
+
+	return (MCD_OK);
+}
+/************************ End of MCD_resumeDma() ********************/
+
+/********************************************************************/
+/* Function:    MCD_csumQuery
+ * Purpose:     Provide the checksum after performing a non-chained DMA
+ * Arguments:   channel - channel to report on
+ *              csum - pointer to where to write the checksum/CRC
+ * Returns:     MCD_ERROR if the channel is invalid, else MCD_OK
+ *
+ * Notes:
+ *
+ */
+int MCD_csumQuery(int channel, uint32_t *csum)
+{
+#ifdef MCD_INCLUDE_EU
+	if((channel < 0) || (channel >= NCHANNELS))
+	return(MCD_CHANNEL_INVALID);
+
+	*csum = MCD_relocBuffDesc[channel].csumResult;
+	return(MCD_OK);
+#else
+	return (MCD_ERROR);
+#endif
+}
+/*********************** End of MCD_resumeDma() *********************/
+
+/********************************************************************/
+/* Function:    MCD_getCodeSize
+ * Purpose:     Provide the size requirements of the microcoded tasks
+ * Returns:     Size in bytes
+ */
+int MCD_getCodeSize(void)
+{
+#ifdef MCD_INCLUDE_EU
+	return(0x2b5c);
+#else
+	return (0x173c);
+#endif
+}
+/********************** End of MCD_getCodeSize() ********************/
+
+/********************************************************************/
+/* Function:    MCD_getVersion
+ * Purpose:     Provide the version string and number
+ * Arguments:   longVersion - user supplied pointer to a pointer to a char
+ *                    which points to the version string
+ * Returns:     Version number and version string (by reference)
+ */
+char MCD_versionString[] = "Multi-channel DMA API Alpha v0.3 (2004-04-26)";
+#define MCD_REV_MAJOR   0x00
+#define MCD_REV_MINOR   0x03
+
+int MCD_getVersion(char **longVersion)
+{
+	*longVersion = MCD_versionString;
+	return ((MCD_REV_MAJOR << 8) | MCD_REV_MINOR);
+}
+/********************** End of MCD_getVersion() *********************/
+
+/********************************************************************/
+/* Private version of memcpy()
+ * Note that everything this is used for is longword-aligned.
+ */
+static void MCD_memcpy(int *dest, int *src, uint32_t size)
+{
+	uint32_t i;
+
+	for (i = 0; i < size; i += sizeof(int), dest++, src++)
+		*dest = *src;
+}
+/********************************************************************/
--- a/dma/MCD_tasks.c
+++ b/dma/MCD_tasks.c
--- a/dma/MCD_tasksInit.c
+++ b/dma/MCD_tasksInit.c
@@ -0,0 +1,225 @@
+/*
+ * File:        MCD_tasksInit.c
+ * Purpose:     Functions for initializing variable tables of different
+ *              types of tasks.
+ *
+ * Notes:
+ */
+
+/*
+ * Do not edit!
+ */
+
+#include "MCD_dma.h"
+#include "MCD_tasksInit.h"
+
+extern dmaRegs *MCD_dmaBar;
+
+
+/*
+ * Task 0
+ */
+ 
+void  MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
+{
+
+    MCD_SET_VAR(taskTable+channel, 2, (uint32_t)currBD); /* var[2] */
+    MCD_SET_VAR(taskTable+channel, 25, (uint32_t)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
+    MCD_SET_VAR(taskTable+channel, 24, (uint32_t)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
+    MCD_SET_VAR(taskTable+channel, 11, (uint32_t)xferSize);  /* var[11] */
+    MCD_SET_VAR(taskTable+channel, 26, (uint32_t)(0x2000 << 16) | (0xffff & xferSizeIncr));  /* inc[2] */
+    MCD_SET_VAR(taskTable+channel, 0, (uint32_t)cSave);  /* var[0] */
+    MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */
+    MCD_SET_VAR(taskTable+channel, 3, (uint32_t)0x00000000); /* var[3] */
+    MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */
+    MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */
+    MCD_SET_VAR(taskTable+channel, 6, (uint32_t)0x00000000); /* var[6] */
+    MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */
+    MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */
+    MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000000); /* var[9] */
+    MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x00000000);    /* var[10] */
+    MCD_SET_VAR(taskTable+channel, 12, (uint32_t)0x00000000);    /* var[12] */
+    MCD_SET_VAR(taskTable+channel, 13, (uint32_t)0x80000000);    /* var[13] */
+    MCD_SET_VAR(taskTable+channel, 14, (uint32_t)0x00000010);    /* var[14] */
+    MCD_SET_VAR(taskTable+channel, 15, (uint32_t)0x00000004);    /* var[15] */
+    MCD_SET_VAR(taskTable+channel, 16, (uint32_t)0x08000000);    /* var[16] */
+    MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x00000000);    /* inc[3] */
+    MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0x80000000);    /* inc[4] */
+    MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0x80000001);    /* inc[5] */
+    MCD_SET_VAR(taskTable+channel, 30, (uint32_t)0x40000000);    /* inc[6] */
+
+    /* Set the task's Enable bit in its Task Control Register */
+    MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000;
+}
+
+
+/*
+ * Task 1
+ */
+ 
+void  MCD_startDmaSingleNoEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
+{
+
+    MCD_SET_VAR(taskTable+channel, 7, (uint32_t)srcAddr);    /* var[7] */
+    MCD_SET_VAR(taskTable+channel, 25, (uint32_t)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
+    MCD_SET_VAR(taskTable+channel, 2, (uint32_t)destAddr);   /* var[2] */
+    MCD_SET_VAR(taskTable+channel, 24, (uint32_t)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
+    MCD_SET_VAR(taskTable+channel, 3, (uint32_t)dmaSize);    /* var[3] */
+    MCD_SET_VAR(taskTable+channel, 26, (uint32_t)(0x2000 << 16) | (0xffff & xferSizeIncr));  /* inc[2] */
+    MCD_SET_VAR(taskTable+channel, 5, (uint32_t)flags);  /* var[5] */
+    MCD_SET_VAR(taskTable+channel, 1, (uint32_t)currBD); /* var[1] */
+    MCD_SET_VAR(taskTable+channel, 0, (uint32_t)cSave);  /* var[0] */
+    MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */
+    MCD_SET_VAR(taskTable+channel, 6, (uint32_t)0x00000000); /* var[6] */
+    MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */
+    MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000004); /* var[9] */
+    MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x08000000);    /* var[10] */
+    MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x00000000);    /* inc[3] */
+    MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0x80000001);    /* inc[4] */
+    MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0x40000000);    /* inc[5] */
+
+    /* Set the task's Enable bit in its Task Control Register */
+    MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000;
+}
+
+
+/*
+ * Task 2
+ */
+ 
+void  MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
+{
+
+    MCD_SET_VAR(taskTable+channel, 3, (uint32_t)currBD); /* var[3] */
+    MCD_SET_VAR(taskTable+channel, 25, (uint32_t)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
+    MCD_SET_VAR(taskTable+channel, 24, (uint32_t)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
+    MCD_SET_VAR(taskTable+channel, 12, (uint32_t)xferSize);  /* var[12] */
+    MCD_SET_VAR(taskTable+channel, 26, (uint32_t)(0x2000 << 16) | (0xffff & xferSizeIncr));  /* inc[2] */
+    MCD_SET_VAR(taskTable+channel, 0, (uint32_t)cSave);  /* var[0] */
+    MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */
+    MCD_SET_VAR(taskTable+channel, 2, (uint32_t)0x00000000); /* var[2] */
+    MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */
+    MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */
+    MCD_SET_VAR(taskTable+channel, 6, (uint32_t)0x00000000); /* var[6] */
+    MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */
+    MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */
+    MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000000); /* var[9] */
+    MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x00000000);    /* var[10] */
+    MCD_SET_VAR(taskTable+channel, 11, (uint32_t)0x00000000);    /* var[11] */
+    MCD_SET_VAR(taskTable+channel, 13, (uint32_t)0x00000000);    /* var[13] */
+    MCD_SET_VAR(taskTable+channel, 14, (uint32_t)0x80000000);    /* var[14] */
+    MCD_SET_VAR(taskTable+channel, 15, (uint32_t)0x00000010);    /* var[15] */
+    MCD_SET_VAR(taskTable+channel, 16, (uint32_t)0x00000001);    /* var[16] */
+    MCD_SET_VAR(taskTable+channel, 17, (uint32_t)0x00000004);    /* var[17] */
+    MCD_SET_VAR(taskTable+channel, 18, (uint32_t)0x08000000);    /* var[18] */
+    MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x00000000);    /* inc[3] */
+    MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0x80000000);    /* inc[4] */
+    MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0xc0000000);    /* inc[5] */
+    MCD_SET_VAR(taskTable+channel, 30, (uint32_t)0x80000001);    /* inc[6] */
+    MCD_SET_VAR(taskTable+channel, 31, (uint32_t)0x40000000);    /* inc[7] */
+
+    /* Set the task's Enable bit in its Task Control Register */
+    MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000;
+}
+
+
+/*
+ * Task 3
+ */
+ 
+void  MCD_startDmaSingleEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
+{
+
+    MCD_SET_VAR(taskTable+channel, 8, (uint32_t)srcAddr);    /* var[8] */
+    MCD_SET_VAR(taskTable+channel, 25, (uint32_t)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
+    MCD_SET_VAR(taskTable+channel, 3, (uint32_t)destAddr);   /* var[3] */
+    MCD_SET_VAR(taskTable+channel, 24, (uint32_t)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
+    MCD_SET_VAR(taskTable+channel, 4, (uint32_t)dmaSize);    /* var[4] */
+    MCD_SET_VAR(taskTable+channel, 26, (uint32_t)(0x2000 << 16) | (0xffff & xferSizeIncr));  /* inc[2] */
+    MCD_SET_VAR(taskTable+channel, 6, (uint32_t)flags);  /* var[6] */
+    MCD_SET_VAR(taskTable+channel, 2, (uint32_t)currBD); /* var[2] */
+    MCD_SET_VAR(taskTable+channel, 0, (uint32_t)cSave);  /* var[0] */
+    MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */
+    MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */
+    MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */
+    MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000000); /* var[9] */
+    MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x00000001);    /* var[10] */
+    MCD_SET_VAR(taskTable+channel, 11, (uint32_t)0x00000004);    /* var[11] */
+    MCD_SET_VAR(taskTable+channel, 12, (uint32_t)0x08000000);    /* var[12] */
+    MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x00000000);    /* inc[3] */
+    MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0xc0000000);    /* inc[4] */
+    MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0x80000000);    /* inc[5] */
+    MCD_SET_VAR(taskTable+channel, 30, (uint32_t)0x80000001);    /* inc[6] */
+    MCD_SET_VAR(taskTable+channel, 31, (uint32_t)0x40000000);    /* inc[7] */
+
+    /* Set the task's Enable bit in its Task Control Register */
+    MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000;
+}
+
+
+/*
+ * Task 4
+ */
+ 
+void  MCD_startDmaENetRcv(int8_t *bDBase, int8_t *currBD, int8_t *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel)
+{
+
+    MCD_SET_VAR(taskTable+channel, 0, (uint32_t)bDBase); /* var[0] */
+    MCD_SET_VAR(taskTable+channel, 3, (uint32_t)currBD); /* var[3] */
+    MCD_SET_VAR(taskTable+channel, 6, (uint32_t)rcvFifoPtr); /* var[6] */
+    MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */
+    MCD_SET_VAR(taskTable+channel, 2, (uint32_t)0x00000000); /* var[2] */
+    MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */
+    MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */
+    MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */
+    MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */
+    MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x0000ffff); /* var[9] */
+    MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x30000000);    /* var[10] */
+    MCD_SET_VAR(taskTable+channel, 11, (uint32_t)0x0fffffff);    /* var[11] */
+    MCD_SET_VAR(taskTable+channel, 12, (uint32_t)0x00000008);    /* var[12] */
+    MCD_SET_VAR(taskTable+channel, 24, (uint32_t)0x00000000);    /* inc[0] */
+    MCD_SET_VAR(taskTable+channel, 25, (uint32_t)0x60000000);    /* inc[1] */
+    MCD_SET_VAR(taskTable+channel, 26, (uint32_t)0x20000004);    /* inc[2] */
+    MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x40000000);    /* inc[3] */
+
+    /* Set the task's Enable bit in its Task Control Register */
+    MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000;
+}
+
+
+/*
+ * Task 5
+ */
+ 
+void  MCD_startDmaENetXmit(int8_t *bDBase, int8_t *currBD, int8_t *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel)
+{
+
+    MCD_SET_VAR(taskTable+channel, 0, (uint32_t)bDBase); /* var[0] */
+    MCD_SET_VAR(taskTable+channel, 3, (uint32_t)currBD); /* var[3] */
+    MCD_SET_VAR(taskTable+channel, 11, (uint32_t)xmitFifoPtr);   /* var[11] */
+    MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */
+    MCD_SET_VAR(taskTable+channel, 2, (uint32_t)0x00000000); /* var[2] */
+    MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */
+    MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */
+    MCD_SET_VAR(taskTable+channel, 6, (uint32_t)0x00000000); /* var[6] */
+    MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */
+    MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */
+    MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000000); /* var[9] */
+    MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x00000000);    /* var[10] */
+    MCD_SET_VAR(taskTable+channel, 12, (uint32_t)0x00000000);    /* var[12] */
+    MCD_SET_VAR(taskTable+channel, 13, (uint32_t)0x0000ffff);    /* var[13] */
+    MCD_SET_VAR(taskTable+channel, 14, (uint32_t)0xffffffff);    /* var[14] */
+    MCD_SET_VAR(taskTable+channel, 15, (uint32_t)0x00000004);    /* var[15] */
+    MCD_SET_VAR(taskTable+channel, 16, (uint32_t)0x00000008);    /* var[16] */
+    MCD_SET_VAR(taskTable+channel, 24, (uint32_t)0x00000000);    /* inc[0] */
+    MCD_SET_VAR(taskTable+channel, 25, (uint32_t)0x60000000);    /* inc[1] */
+    MCD_SET_VAR(taskTable+channel, 26, (uint32_t)0x40000000);    /* inc[2] */
+    MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0xc000fffc);    /* inc[3] */
+    MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0xe0000004);    /* inc[4] */
+    MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0x80000000);    /* inc[5] */
+    MCD_SET_VAR(taskTable+channel, 30, (uint32_t)0x4000ffff);    /* inc[6] */
+    MCD_SET_VAR(taskTable+channel, 31, (uint32_t)0xe0000001);    /* inc[7] */
+
+    /* Set the task's Enable bit in its Task Control Register */
+    MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000;
+}
--- a/dma/dma.c
+++ b/dma/dma.c
@@ -0,0 +1,677 @@
+/*
+ * dma.c
+ *
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 26.02.2013
+ *      Author: Markus Fröschle
+ */
+
+#include "dma.h"
+#include <MCD_dma.h>
+#include "mcd_initiators.h"
+#include "bas_printf.h"
+#include "bas_string.h"
+#include "cache.h"
+#include "exceptions.h"
+
+#if defined(MACHINE_FIREBEE)
+#include "firebee.h"
+#elif defined(MACHINE_M5484LITE)
+#include "m5484l.h"
+#elif defined(MACHINE_M54455)
+#include "m54455.h"
+#else
+#error "unknown machine!"
+#endif /* MACHINE_FIREBEE */
+
+#define DBG_DMA
+#ifdef DBG_DMA
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
+#else
+#define dbg(format, arg...) do { ; } while (0)
+#endif /* DBG_DMA */
+
+extern char _SYS_SRAM[];
+#define SYS_SRAM &_SYS_SRAM[0]
+
+struct dma_channel
+{
+	int req;
+	void (*handler)(void);
+};
+
+static char used_reqs[32] =
+{
+	DMA_ALWAYS,  DMA_DSPI_RXFIFO, DMA_DSPI_TXFIFO, DMA_DREQ0,
+	DMA_PSC0_RX, DMA_PSC0_TX, DMA_USB_EP0,  DMA_USB_EP1,
+	DMA_USB_EP2,  DMA_USB_EP3,  DMA_PCI_TX,  DMA_PCI_RX,
+	DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX,  DMA_I2C_TX,
+	0,           0,           0,           0,
+	0,           0,           0,           0,
+	0,           0,           0,           0,
+	0,           0,           0,           0
+};
+
+static struct dma_channel dma_channel[NCHANNELS] =
+{
+	{-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL},
+	{-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL},
+	{-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL},
+	{-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL},
+};
+
+/*
+ * Enable all DMA interrupts
+ *
+ * Parameters:
+ *  pri     Interrupt Priority
+ *  lvl     Interrupt Level
+ */
+void dma_irq_enable(uint8_t lvl, uint8_t pri)
+{
+	/* Setup the DMA ICR (#48) */
+	MCF_INTC_ICR48 = 0
+		| MCF_INTC_ICR_IP(pri)
+		| MCF_INTC_ICR_IL(lvl);
+	dbg("DMA irq assigned level %d, priority %d\r\n", lvl, pri);
+
+	/* Unmask all task interrupts */
+	MCF_DMA_DIMR = 0;
+
+	/* Clear the interrupt pending register */
+	MCF_DMA_DIPR = 0;
+
+	/* Unmask the DMA interrupt in the interrupt controller */
+	MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK48;
+
+	dbg("DMA task interrupts unmasked, pending interrupts cleared, interrupt controller active\r\n");
+}
+
+/*
+ * Disable all DMA interrupts
+ */
+void dma_irq_disable(void)
+{
+	/* Mask all task interrupts */
+	MCF_DMA_DIMR = (uint32_t) ~0;
+
+	/* Clear any pending task interrupts */
+	MCF_DMA_DIPR = (uint32_t) ~0;
+
+	/* Mask the DMA interrupt in the interrupt controller */
+	MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK48;
+
+	dbg("DMA interrupts masked and disabled\r\n");
+}
+
+int dma_set_initiator(int initiator)
+{
+	switch (initiator)
+	{
+		/* these initiators are always active */
+		case DMA_ALWAYS:
+		case DMA_DSPI_RXFIFO:
+		case DMA_DSPI_TXFIFO:
+		case DMA_DREQ0:
+		case DMA_PSC0_RX:
+		case DMA_PSC0_TX:
+		case DMA_USB_EP0:
+		case DMA_USB_EP1:
+		case DMA_USB_EP2:
+		case DMA_USB_EP3:
+		case DMA_PCI_TX:
+		case DMA_PCI_RX:
+		case DMA_PSC1_RX:
+		case DMA_I2C_RX:
+		case DMA_I2C_TX:
+			break;
+
+		case DMA_FEC0_RX:
+			MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC16(3)) | MCF_DMA_IMCR_IMC16_FEC0RX;
+			used_reqs[16] = DMA_FEC0_RX;
+			break;
+
+		case DMA_FEC0_TX:
+			MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC17(3)) | MCF_DMA_IMCR_IMC17_FEC0TX;
+			used_reqs[17] = DMA_FEC0_TX;
+			break;
+
+		case DMA_FEC1_RX:
+			MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC20(3)) | MCF_DMA_IMCR_IMC20_FEC1RX;
+			used_reqs[20] = DMA_FEC1_RX;
+			break;
+
+		case DMA_FEC1_TX:
+			if (used_reqs[21] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC21(3)) | MCF_DMA_IMCR_IMC21_FEC1TX;
+				used_reqs[21] = DMA_FEC1_TX;
+			}
+			else if (used_reqs[25] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC25(3)) | MCF_DMA_IMCR_IMC25_FEC1TX;
+				used_reqs[25] = DMA_FEC1_TX;
+			}
+			else if (used_reqs[31] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC31(3)) | MCF_DMA_IMCR_IMC31_FEC1TX;
+				used_reqs[31] = DMA_FEC1_TX;
+			}
+			else /* No empty slots */
+			{
+				dbg("no free slot found\r\n");
+
+				return 1;
+			}
+			break;
+
+		case DMA_DREQ1:
+			if (used_reqs[29] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC29(3)) | MCF_DMA_IMCR_IMC29_DREQ1;
+				used_reqs[29] = DMA_DREQ1;
+			}
+			else if (used_reqs[21] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC21(3)) | MCF_DMA_IMCR_IMC21_DREQ1;
+				used_reqs[21] = DMA_DREQ1;
+			}
+			else /* No empty slots */
+			{
+				dbg("no free slot\r\n");
+
+				return 1;
+			}
+			break;
+
+		case DMA_CTM0:
+			if (used_reqs[24] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC24(3)) | MCF_DMA_IMCR_IMC24_CTM0;
+				used_reqs[24] = DMA_CTM0;
+			}
+			else /* No empty slots */
+			{
+				dbg("no free slot\r\n");
+
+				return 1;
+			}
+			break;
+
+		case DMA_CTM1:
+			if (used_reqs[25] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC25(3)) | MCF_DMA_IMCR_IMC25_CTM1;
+				used_reqs[25] = DMA_CTM1;
+			}
+			else /* No empty slots */
+			{
+				dbg("no free slot\r\n");
+
+				return 1;
+			}
+			break;
+
+		case DMA_CTM2:
+			if (used_reqs[26] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC26(3)) | MCF_DMA_IMCR_IMC26_CTM2;
+				used_reqs[26] = DMA_CTM2;
+			}
+			else /* No empty slots */
+			{
+				dbg("no free slot\r\n");
+
+				return 1;
+			}
+			break;
+
+		case DMA_CTM3:
+			if (used_reqs[27] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC27(3)) | MCF_DMA_IMCR_IMC27_CTM3;
+				used_reqs[27] = DMA_CTM3;
+			}
+			else /* No empty slots */
+			{
+				dbg("no free slot\r\n");
+
+				return 1;
+			}
+			break;
+
+		case DMA_CTM4:
+			if (used_reqs[28] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC28(3)) | MCF_DMA_IMCR_IMC28_CTM4;
+				used_reqs[28] = DMA_CTM4;
+			}
+			else /* No empty slots */
+			{
+				dbg("no free slot\r\n");
+
+				return 1;
+			}
+			break;
+
+		case DMA_CTM5:
+			if (used_reqs[29] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC29(3)) | MCF_DMA_IMCR_IMC29_CTM5;
+				used_reqs[29] = DMA_CTM5;
+			}
+			else /* No empty slots */
+			{
+				dbg("no free slot\r\n");
+
+				return 1;
+			}
+			break;
+
+		case DMA_CTM6:
+			if (used_reqs[30] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC30(3)) | MCF_DMA_IMCR_IMC30_CTM6;
+				used_reqs[30] = DMA_CTM6;
+			}
+			else /* No empty slots */
+			{
+				dbg("no free slot\r\n");
+
+				return 1;
+			}
+			break;
+
+		case DMA_CTM7:
+			if (used_reqs[31] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC31(3)) | MCF_DMA_IMCR_IMC31_CTM7;
+				used_reqs[31] = DMA_CTM7;
+			}
+			else /* No empty slots */
+			{
+				dbg("no free slot\r\n");
+
+				return 1;
+			}
+			break;
+
+		case DMA_USBEP4:
+			if (used_reqs[26] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC26(3)) | MCF_DMA_IMCR_IMC26_USBEP4;
+				used_reqs[26] = DMA_USBEP4;
+			}
+			else /* No empty slots */
+			{
+				dbg("no free slot\r\n");
+
+				return 1;
+			}
+			break;
+
+		case DMA_USBEP5:
+			if (used_reqs[27] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC27(3)) | MCF_DMA_IMCR_IMC27_USBEP5;
+				used_reqs[27] = DMA_USBEP5;
+			}
+			else /* No empty slots */
+			{
+				dbg("no free slot\r\n");
+
+				return 1;
+			}
+			break;
+
+		case DMA_USBEP6:
+			if (used_reqs[28] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC28(3)) | MCF_DMA_IMCR_IMC28_USBEP6;
+				used_reqs[28] = DMA_USBEP6;
+			}
+			else /* No empty slots */
+				return 1;
+			break;
+
+		case DMA_PSC2_RX:
+			if (used_reqs[28] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC28(3)) | MCF_DMA_IMCR_IMC28_PSC2RX;
+				used_reqs[28] = DMA_PSC2_RX;            }
+			else /* No empty slots */
+			{
+				dbg("no free slot\r\n");
+
+				return 1;
+			}
+			break;
+
+		case DMA_PSC2_TX:
+			if (used_reqs[29] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC29(3)) | MCF_DMA_IMCR_IMC29_PSC2TX;
+				used_reqs[29] = DMA_PSC2_TX;
+			}
+			else /* No empty slots */
+			{
+				dbg("no free slot\r\n");
+
+				return 1;
+			}
+			break;
+
+		case DMA_PSC3_RX:
+			if (used_reqs[30] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC30(3)) | MCF_DMA_IMCR_IMC30_PSC3RX;
+				used_reqs[30] = DMA_PSC3_RX;
+			}
+			else /* No empty slots */
+			{
+				dbg("no free slot\r\n");
+
+				return 1;
+			}
+			break;
+
+		case DMA_PSC3_TX:
+			if (used_reqs[31] == 0)
+			{
+				MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC31(3)) | MCF_DMA_IMCR_IMC31_PSC3TX;
+				used_reqs[31] = DMA_PSC3_TX;
+			}
+			else /* No empty slots */
+			{
+				dbg("no free slot\r\n");
+
+				return 1;
+			}
+			break;
+
+		default:
+			{
+				dbg("don't know what to do\r\n");
+
+				return 1;
+			}
+	}
+	return 0;
+}
+
+/*
+ * Return the initiator number for the given requestor
+ *
+ * Parameters:
+ *  requestor   Initiator/Requestor identifier
+ *
+ * Return Value:
+ *  The initiator number (0-31) if initiator has been assigned
+ *  0 (always initiator) otherwise
+ */
+uint32_t dma_get_initiator(int requestor)
+{
+	uint32_t i;
+
+	for (i = 0; i < sizeof(used_reqs); ++i)
+	{
+		if (used_reqs[i] == requestor)
+			return i;
+	}
+	dbg("no initiator found for requestor %d\r\n", requestor);
+
+	return 0;
+}
+
+/*
+ * Remove the given initiator from the active list
+ *
+ * Parameters:
+ *  requestor   Initiator/Requestor identifier
+ */
+void dma_free_initiator(int requestor)
+{
+	uint32_t i;
+
+	for (i = 16; i < sizeof(used_reqs); ++i)
+	{
+		if (used_reqs[i] == requestor)
+		{
+			used_reqs[i] = 0;
+			break;
+		}
+	}
+	dbg("DMA requestor %d freed\r\n", requestor);
+}
+
+/*
+ * Attempt to find an available channel and mark it as used
+ *
+ * Parameters:
+ *  requestor   Initiator/Requestor identifier
+ *
+ * Return Value:
+ *  First available channel or -1 if they are all occupied
+ */
+int dma_set_channel(int requestor, void (*handler)(void))
+{
+	int i;
+
+	/* Check to see if this requestor is already assigned to a channel */
+	dbg("check if requestor %d is already assigned to a channel\r\n", requestor);
+	if ((i = dma_get_channel(requestor)) != -1)
+		return i;
+
+	for (i = 0; i < NCHANNELS; ++i)
+	{
+		if (dma_channel[i].req == -1)
+		{
+			dma_channel[i].req = requestor;
+			dma_channel[i].handler = handler;
+			dbg("assigned channel %d to requestor %d\r\n", i, requestor);
+			return i;
+		}
+	}
+	dbg("no free DMA channel found for requestor %d\r\n", requestor);
+
+	/* All channels taken */
+	return -1;
+}
+
+void dma_clear_channel(int channel)
+{
+	if(channel >= 0 && channel < NCHANNELS)
+	{
+		dma_channel[channel].req = -1;
+		dma_channel[channel].handler = NULL;
+		dbg("cleared DMA channel %d\r\n", channel);
+	}
+}
+
+/*
+ * Return the channel being initiated by the given requestor
+ *
+ * Parameters:
+ *  requestor   Initiator/Requestor identifier
+ *
+ * Return Value:
+ *  Channel that the requestor is controlling or -1 if hasn't been
+ *  activated
+ */
+int dma_get_channel(int requestor)
+{
+	uint32_t i;
+
+	for (i = 0; i < NCHANNELS; ++i)
+	{
+		if (dma_channel[i].req == requestor)
+			return i;
+	}
+	dbg("no channel occupied by requestor %d\r\n", requestor);
+	return -1;
+}
+
+/*
+ * Remove the channel being initiated by the given requestor from
+ * the active list
+ *
+ * Parameters:
+ *  requestor   Initiator/Requestor identifier
+ */
+void dma_free_channel(int requestor)
+{
+	uint32_t i;
+
+	for (i = 0; i < NCHANNELS; ++i)
+	{
+		if (dma_channel[i].req == requestor)
+		{
+			dma_channel[i].req = -1;
+			dma_channel[i].handler = NULL;
+			break;
+		}
+	}
+}
+
+/*
+ * This is the catch-all interrupt handler for the mult-channel DMA
+ */
+int dma_interrupt_handler(void *arg1, void *arg2)
+{
+	int i, interrupts;
+	uint32_t ipl;
+
+	ipl = set_ipl(7);		/* do not disturb */
+
+	/*
+	 * Determine which interrupt(s) triggered by AND'ing the
+	 * pending interrupts with those that aren't masked.
+	 */
+	interrupts = MCF_DMA_DIPR & ~MCF_DMA_DIMR;
+
+	/* Make sure we are here for a reason */
+	if (interrupts == 0)
+	{
+		dbg("not DMA interrupt! Spurious?\r\n");
+		return 0;
+	}
+
+	/* Clear the interrupt in the pending register */
+	MCF_DMA_DIPR = interrupts;
+
+	for (i = 0; i < 16; ++i, interrupts >>= 1)
+	{
+		if (interrupts & 0x1)
+		{
+			/* If there is a handler, call it */
+			if (dma_channel[i].handler != NULL)
+			{
+				dbg("call handler for DMA channel %d (%p)\r\n", i, dma_channel[i].handler);
+				dma_channel[i].handler();
+			}
+		}
+	}
+
+	set_ipl(ipl);
+
+	return 1;	/* handled */
+}
+/********************************************************************/
+
+void *dma_memcpy(void *dst, void *src, size_t n)
+{
+	int ret;
+
+#ifdef DBG_DMA
+	int32_t time;
+	int32_t start;
+	int32_t end;
+
+	start = MCF_SLT0_SCNT;
+#endif /* DBG_DMA */
+
+	ret = MCD_startDma(1, src, 4, dst, 4, n, 4, DMA_ALWAYS, 0, MCD_SINGLE_DMA, 0);
+	if (ret == MCD_OK)
+	{
+		dbg("DMA on channel 1 successfully started\r\n");
+	}
+
+	do
+	{
+		ret = MCD_dmaStatus(1);
+#ifdef _NOT_USED_ /* suppress annoying printout for now */
+		switch (ret)
+		{
+			case MCD_NO_DMA:
+				xprintf("MCD_NO_DMA: no DMA active on this channel\r\n");
+				return NULL;
+				break;
+			case MCD_IDLE:
+				xprintf("MCD_IDLE: DMA defined but not active (initiator not ready)\r\n");
+				break;
+			case MCD_RUNNING:
+				xprintf("MCD_RUNNING: DMA active and working on this channel\r\n");
+				break;
+			case MCD_PAUSED:
+				xprintf("MCD_PAUSED: DMA defined and enabled, but currently paused\r\n");
+				break;
+			case MCD_HALTED:
+				xprintf("MCD_HALTED: DMA killed\r\n");
+				return NULL;
+				break;
+			case MCD_DONE:
+				xprintf("MCD_DONE: DMA finished\r\n");
+				break;
+			case MCD_CHANNEL_INVALID:
+				xprintf("MCD_CHANNEL_INVALID: invalid DMA channel\r\n");
+				return NULL;
+				break;
+			default:
+				xprintf("unknown DMA status %d\r\n", ret);
+				break;
+		}
+#endif
+	} while (ret != MCD_DONE);
+
+#ifdef DBG_DMA
+	end = MCF_SLT0_SCNT;
+	time = (start - end) / (SYSCLK / 1000) / 1000;
+#endif /* DBG_DMA */
+	dbg("took %d ms (%f Mbytes/second)\r\n", time, n / (float) time / 1000.0);
+
+	return dst;
+}
+
+int dma_init(void)
+{
+	int res;
+
+	dbg("MCD DMA API initialization: ");
+	res = MCD_initDma((dmaRegs *) &_MBAR[0x8000], SYS_SRAM, MCD_RELOC_TASKS | MCD_COMM_PREFETCH_EN);
+	if (res != MCD_OK)
+	{
+		dbg("DMA API initialization failed (0x%x)\r\n", res);
+		return 0;
+	}
+
+	// test
+	dma_memcpy((void *) 0x10000, (void *) 0x03e00000, 0x00100000);	/* copy one megabyte of flash to RAM */
+
+	return 0;
+}
+
--- a/dump.bdm
+++ b/dump.bdm
@@ -0,0 +1,17 @@
+#!/usr/local/bin/bdmctrl -D2 -v9 -d9
+#
+# firebee board initialization for bdmctrl 
+#
+open $1
+
+dump-register D0
+#dump-register ASID
+dump-register ACR0
+dump-register ACR1
+#dump-register ACR2
+#dump-register ACR3
+dump-register SR
+dump-register CACR
+# dump-register RAMBAR1
+# dump-register RAMBAR2
+dump-register MBAR
--- a/exe/basflash.c
+++ b/exe/basflash.c
@@ -0,0 +1,675 @@
+/*
+ * basflash.c
+ *
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 26.02.2013
+ *      Author: Markus Fröschle
+ */
+
+#include <bas_types.h>
+#include "bas_printf.h"
+#include "bas_string.h"
+#include "diskio.h"
+#include "ff.h"
+#include "s19reader.h"
+
+#ifdef MACHINE_FIREBEE
+#include "firebee.h"
+#endif /* MACHINE_FIREBEE */
+
+#ifdef MACHINE_M5484LITE
+#include "m5484l.h"
+#endif /* MACHINE_M5484LITE */
+
+#define AMD_FLASH_BUS_SHIFT     1
+#define AMD_FLASH_CELL          volatile uint16_t
+#define AMD_FLASH_CELL_BYTES    2
+#define AMD_FLASH_CELL_MASK     0x1
+#define AMD_FLASH_CMD_DATA(x)   ((uint16_t) x)
+
+struct amd_flash_sector_info
+{
+	uint32_t size; /* sector size in bytes */
+	uint32_t offset; /* offset from base of device */
+};
+
+/*
+ * AM29LV640D flash layout (bottom boot as used in the Firebee )
+ */
+static struct amd_flash_sector_info sector[] =
+{
+		{  8 * 1024, 0x00000000 }, /* SA0 */
+		{  8 * 1024, 0x00008000 }, /* SA1 */
+		{  8 * 1024, 0x00010000 }, /* SA2 */
+		{  8 * 1024, 0x00018000 }, /* SA3 */
+		{  8 * 1024, 0x00020000 }, /* SA4 */
+		{  8 * 1024, 0x00028000 }, /* SA5 */
+		{  8 * 1024, 0x00030000 }, /* SA6 */
+		{  8 * 1024, 0x00038000 }, /* SA7 */
+		{  8 * 1024, 0x00040000 }, /* SA8 */
+		{ 64 * 1024, 0x00048000 }, /* SA9 */
+		{ 64 * 1024, 0x00050000 }, /* SA10 */
+		{ 64 * 1024, 0x00058000 }, /* SA11 */
+		{ 64 * 1024, 0x00060000 }, /* SA12 */
+		{ 64 * 1024, 0x00068000 }, /* SA13 */
+		{ 64 * 1024, 0x00070000 }, /* SA14 */
+		{ 64 * 1024, 0x00078000 }, /* SA15 */
+		{ 64 * 1024, 0x00080000 }, /* SA16 */
+		{ 64 * 1024, 0x00088000 }, /* SA17 */
+		{ 64 * 1024, 0x00090000 }, /* SA18 */
+		{ 64 * 1024, 0x00098000 }, /* SA19 */
+		{ 64 * 1024, 0x000a0000 }, /* SA20 */
+		{ 64 * 1024, 0x000a8000 }, /* SA21 */
+		{ 64 * 1024, 0x000b0000 }, /* SA22 */
+		{ 64 * 1024, 0x000b8000 }, /* SA23 */
+		{ 64 * 1024, 0x000c0000 }, /* SA24 */
+		{ 64 * 1024, 0x000c8000 }, /* SA25 */
+		{ 64 * 1024, 0x000d0000 }, /* SA26 */
+		{ 64 * 1024, 0x000d8000 }, /* SA27 */
+		{ 64 * 1024, 0x000e0000 }, /* SA28 */
+		{ 64 * 1024, 0x000e8000 }, /* SA29 */
+		{ 64 * 1024, 0x000f0000 }, /* SA30 */
+		{ 64 * 1024, 0x000f8000 }, /* SA31 */
+		{ 64 * 1024, 0x00100000 }, /* SA32 */
+		{ 64 * 1024, 0x00108000 }, /* SA32 */
+		{ 64 * 1024, 0x00110000 }, /* SA34 */
+		{ 64 * 1024, 0x00118000 }, /* SA35 */
+		{ 64 * 1024, 0x00120000 }, /* SA36 */
+		{ 64 * 1024, 0x00128000 }, /* SA37 */
+		{ 64 * 1024, 0x00130000 }, /* SA38 */
+		{ 64 * 1024, 0x00138000 }, /* SA39 */
+		{ 64 * 1024, 0x00140000 }, /* SA40 */
+		{ 64 * 1024, 0x00148000 }, /* SA41 */
+		{ 64 * 1024, 0x00150000 }, /* SA42 */
+		{ 64 * 1024, 0x00158000 }, /* SA43 */
+		{ 64 * 1024, 0x00160000 }, /* SA44 */
+		{ 64 * 1024, 0x00168000 }, /* SA45 */
+		{ 64 * 1024, 0x00170000 }, /* SA46 */
+		{ 64 * 1024, 0x00178000 }, /* SA47 */
+		{ 64 * 1024, 0x00180000 }, /* SA48 */
+		{ 64 * 1024, 0x00188000 }, /* SA49 */
+		{ 64 * 1024, 0x00190000 }, /* SA50 */
+		{ 64 * 1024, 0x00198000 }, /* SA51 */
+		{ 64 * 1024, 0x001a0000 }, /* SA52 */
+		{ 64 * 1024, 0x001a8000 }, /* SA53 */
+		{ 64 * 1024, 0x001b0000 }, /* SA54 */
+		{ 64 * 1024, 0x001b8000 }, /* SA55 */
+		{ 64 * 1024, 0x001c0000 }, /* SA56 */
+		{ 64 * 1024, 0x001c8000 }, /* SA57 */
+		{ 64 * 1024, 0x001d0000 }, /* SA58 */
+		{ 64 * 1024, 0x001d8000 }, /* SA59 */
+		{ 64 * 1024, 0x001e0000 }, /* SA60 */
+		{ 64 * 1024, 0x001e8000 }, /* SA61 */
+		{ 64 * 1024, 0x001f0000 }, /* SA62 */
+		{ 64 * 1024, 0x001f8000 }, /* SA63 */
+		{ 64 * 1024, 0x00200000 }, /* SA64 */
+		{ 64 * 1024, 0x00208000 }, /* SA65 */
+		{ 64 * 1024, 0x00210000 }, /* SA66 */
+		{ 64 * 1024, 0x00218000 }, /* SA67 */
+		{ 64 * 1024, 0x00220000 }, /* SA68 */
+		{ 64 * 1024, 0x00228000 }, /* SA69 */
+		{ 64 * 1024, 0x00230000 }, /* SA70 */
+		{ 64 * 1024, 0x00238000 }, /* SA71 */
+		{ 64 * 1024, 0x00240000 }, /* SA72 */
+		{ 64 * 1024, 0x00248000 }, /* SA73 */
+		{ 64 * 1024, 0x00250000 }, /* SA74 */
+		{ 64 * 1024, 0x00258000 }, /* SA75 */
+		{ 64 * 1024, 0x00260000 }, /* SA76 */
+		{ 64 * 1024, 0x00268000 }, /* SA77 */
+		{ 64 * 1024, 0x00270000 }, /* SA78 */
+		{ 64 * 1024, 0x00278000 }, /* SA79 */
+		{ 64 * 1024, 0x00280000 }, /* SA80 */
+		{ 64 * 1024, 0x00288000 }, /* SA81 */
+		{ 64 * 1024, 0x00290000 }, /* SA82 */
+		{ 64 * 1024, 0x00298000 }, /* SA83 */
+		{ 64 * 1024, 0x002a0000 }, /* SA84 */
+		{ 64 * 1024, 0x002a8000 }, /* SA85 */
+		{ 64 * 1024, 0x002b0000 }, /* SA86 */
+		{ 64 * 1024, 0x002b8000 }, /* SA87 */
+		{ 64 * 1024, 0x002c0000 }, /* SA88 */
+		{ 64 * 1024, 0x002c8000 }, /* SA89 */
+		{ 64 * 1024, 0x002d0000 }, /* SA90 */
+		{ 64 * 1024, 0x002d8000 }, /* SA91 */
+		{ 64 * 1024, 0x002e0000 }, /* SA92 */
+		{ 64 * 1024, 0x002e8000 }, /* SA93 */
+		{ 64 * 1024, 0x002f0000 }, /* SA94 */
+		{ 64 * 1024, 0x002f8000 }, /* SA95 */
+		{ 64 * 1024, 0x00300000 }, /* SA96 */
+		{ 64 * 1024, 0x00308000 }, /* SA97 */
+		{ 64 * 1024, 0x00310000 }, /* SA98 */
+		{ 64 * 1024, 0x00318000 }, /* SA99 */
+		{ 64 * 1024, 0x00320000 }, /* SA100 */
+		{ 64 * 1024, 0x00328000 }, /* SA101 */
+		{ 64 * 1024, 0x00330000 }, /* SA102 */
+		{ 64 * 1024, 0x00338000 }, /* SA103 */
+		{ 64 * 1024, 0x00340000 }, /* SA104 */
+		{ 64 * 1024, 0x00348000 }, /* SA105 */
+		{ 64 * 1024, 0x00350000 }, /* SA106 */
+		{ 64 * 1024, 0x00358000 }, /* SA107 */
+		{ 64 * 1024, 0x00360000 }, /* SA108 */
+		{ 64 * 1024, 0x00368000 }, /* SA109 */
+		{ 64 * 1024, 0x00370000 }, /* SA110 */
+		{ 64 * 1024, 0x00378000 }, /* SA111 */
+		{ 64 * 1024, 0x00380000 }, /* SA112 */
+		{ 64 * 1024, 0x00388000 }, /* SA113 */
+		{ 64 * 1024, 0x00390000 }, /* SA114 */
+		{ 64 * 1024, 0x00398000 }, /* SA115 */
+		{ 64 * 1024, 0x003a0000 }, /* SA116 */
+		{ 64 * 1024, 0x003a8000 }, /* SA117 */
+		{ 64 * 1024, 0x003b0000 }, /* SA118 */
+		{ 64 * 1024, 0x003b8000 }, /* SA119 */
+		{ 64 * 1024, 0x003c0000 }, /* SA120 */
+		{ 64 * 1024, 0x003c8000 }, /* SA121 */
+		{ 64 * 1024, 0x003d0000 }, /* SA122 */
+		{ 64 * 1024, 0x003d8000 }, /* SA123 */
+		{ 64 * 1024, 0x003e0000 }, /* SA124 */
+		{ 64 * 1024, 0x003e8000 }, /* SA125 */
+		{ 64 * 1024, 0x003f0000 }, /* SA126 */
+		{ 64 * 1024, 0x003f8000 }, /* SA127 */
+};
+
+static const int AMD_FLASH_SECTORS = sizeof(sector)	/ sizeof(struct amd_flash_sector_info);
+
+#define SOFFSET(n)  (sector[n].offset)
+#define SADDR(n)    (SOFFSET(n) >> AMD_FLASH_BUS_SHIFT)
+#define SSIZE(n)	(sector[n].size)
+
+#define AMD_FLASH_DEVICES	1
+
+static AMD_FLASH_CELL *pFlash;
+
+typedef struct romram
+{
+	uint32_t flash_address;
+	uint32_t ram_address;
+	char *name;
+} ROMRAM;
+
+static const struct romram flash_areas[] =
+{
+		{ 0xe0600000, 0x00e00000, "EmuTOS" }, /* EmuTOS */
+		{ 0xe0400000, 0x00e00000, "FireTOS" }, /* FireTOS */
+		{ 0xe0700000, 0x00e00000, "FPGA" }, /* FPGA config */
+};
+static const int num_flash_areas = sizeof(flash_areas) / sizeof(struct romram);
+
+#define FLASH_ADDRESS 0xe0000000
+
+/*
+ * erase a flash sector
+ *
+ * sector_num is the index into the sector table above.
+ *
+ * FIXME: need to disable data cache to ensure proper operation
+ */
+void amd_flash_sector_erase(int n)
+{
+	volatile AMD_FLASH_CELL status;
+
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);
+
+	do
+		status = pFlash[SADDR(n)];
+	while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));
+
+	/*
+	 * Place device in read mode
+	 */
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+}
+
+int amd_flash_erase(void *start, int bytes, void (*putchar)(int))
+{
+	int i, ebytes = 0;
+
+	if (bytes == 0)
+		return 0;
+
+	for (i = 0; i < AMD_FLASH_SECTORS; i++)
+	{
+		if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
+			start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
+		{
+			break;
+		}
+	}
+
+	while (ebytes < bytes)
+	{
+		if (putchar != NULL)
+		{
+			putchar('.');
+		}
+		amd_flash_sector_erase(i);
+		ebytes += SSIZE(i);
+		i++;
+	}
+
+	if (putchar != NULL)
+	{
+		putchar(10);    /* LF */
+		putchar(13);    /* CR */
+	}
+
+	return ebytes;
+}
+
+void amd_flash_program_cell(AMD_FLASH_CELL *dst, AMD_FLASH_CELL data)
+{
+	volatile AMD_FLASH_CELL status;
+	int retry;
+
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
+	*dst = data;
+
+	/*
+	 * Wait for program operation to finish
+	 *  (Data# Polling Algorithm)
+	 */
+	retry = 0;
+	while (1)
+	{
+		status = *dst;
+		if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
+			(data & AMD_FLASH_CMD_DATA(0x80)))
+		{
+			break;
+		}
+		if (status & AMD_FLASH_CMD_DATA(0x20))
+		{
+			status = *dst;
+			if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
+				(data & AMD_FLASH_CMD_DATA(0x80)))
+			{
+				break;
+			}
+			if (++retry > 1024)
+			{
+				break;
+			}
+		}
+	}
+}
+
+
+int amd_flash_program(void *dest, void *source, int bytes, int erase, void (*func)(void), void (*putchar)(int))
+{
+	AMD_FLASH_CELL *src, *dst;
+	int hashi=1,hashj=0;
+	char hash[5];
+
+	hash[0]=8;  /* Backspace */
+	hash[1]=124;/* "|" */
+	hash[2]=47; /* "/" */
+	hash[3]=45; /* "-" */
+	hash[4]=92; /* "\" */
+
+	src = (AMD_FLASH_CELL *)source;
+	dst = (AMD_FLASH_CELL *)dest;
+
+	/*
+	 * Place device in read mode
+	 */
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+
+	/*
+	 * Erase device if necessary
+	 */
+	if (erase)
+	{
+		amd_flash_erase(dest, bytes, putchar);
+	}
+
+	/*
+	 * Program device
+	 */
+	while (bytes > 0)
+	{
+		amd_flash_program_cell(dst,*src);
+
+		/* Verify Write */
+		if (*dst == *src)
+		{
+			bytes -= AMD_FLASH_CELL_BYTES;
+			*dst++, *src++;
+
+			if ((putchar != NULL))
+			{
+				/* Hash marks to indicate progress */
+				if (hashj == 0x1000)
+				{
+					hashj = -1;
+					putchar(hash[0]);
+					putchar(hash[hashi]);
+
+					hashi++;
+					if (hashi == 5)
+					{
+						hashi=1;
+					}
+
+				}
+				hashj++;
+			}
+		}
+		else
+			break;
+	}
+
+	/*
+	 * Place device in read mode
+	 */
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+
+	if (putchar != NULL)
+	{
+		putchar(hash[0]);
+	}
+
+	/*
+	 * If a function was passed in, call it now
+	 */
+	if ((func != NULL))
+	{
+		func();
+	}
+
+	return ((int)src - (int)source);
+}
+
+/*
+ * this callback just does nothing besides returning OK. Meant to do a dry run over the file to check its integrity
+ */
+static err_t simulate()
+{
+	err_t ret = OK;
+
+	return ret;
+}
+
+static err_t flash(uint8_t *dst, uint8_t *src, uint32_t length)
+{
+	err_t ret = OK;
+
+	/* TODO: do the actual flash */
+	amd_flash_program(dst, src, length, 1, NULL, xputchar);
+	return ret;
+}
+
+/*
+ * this callback verifies the data against the S-record file contents after a write to destination
+ */
+static err_t verify(uint8_t *dst, uint8_t *src, size_t length)
+{
+	uint8_t *end = src + length;
+
+	do
+	{
+		if (*src++ != *dst++)
+			return FAIL;
+	} while (src < end);
+
+	return OK;
+}
+
+void srec_flash(char *flash_filename)
+{
+	DRESULT res;
+	FRESULT fres;
+	FATFS fs;
+	FIL file;
+	err_t err;
+	void *start_address;
+	uint32_t length;
+
+	res = disk_status(0);
+	if (res == RES_OK)
+	{
+		fres = f_mount(0, &fs);
+		if (fres == FR_OK)
+		{
+			if ((fres = f_open(&file, flash_filename, FA_READ) != FR_OK))
+			{
+				xprintf("flasher file %s not present on disk\r\n",
+						flash_filename);
+			}
+			else
+			{
+				f_close(&file);
+
+				/* first pass: parse and check for inconsistencies */
+				xprintf("check file integrity: ");
+				err = read_srecords(flash_filename, &start_address, &length,
+						simulate);
+				if (err == OK)
+				{
+					xprintf("OK.\r\nerase flash area (from %p, length 0x%lx): ",
+							start_address, length);
+					err = amd_flash_erase(start_address, length, xputchar);
+
+					/* next pass: copy data to destination */
+					xprintf("OK.\r\flash data: ");
+					err = read_srecords(flash_filename, &start_address, &length, flash);
+					if (err == OK)
+					{
+						/* next pass: verify data */
+						xprintf("OK.\r\nverify data: ");
+						err = read_srecords(flash_filename, &start_address,
+								&length, verify);
+						if (err == OK)
+						{
+							typedef void void_func(void);
+							void_func *func;
+
+							xprintf("OK.\r\n");
+
+							xprintf(
+									"target successfully written and verified. Start address: %p\r\n",
+									start_address);
+
+							func = (void_func *) start_address;
+							(*func)();
+						}
+						else
+						{
+							xprintf("failed\r\n");
+						}
+					}
+					else
+					{
+						xprintf("failed\r\n");
+					}
+				}
+				else
+				{
+					xprintf("failed\r\n");
+				}
+			}
+		}
+		else
+		{
+			// xprintf("could not mount FAT FS\r\n");
+		}
+		f_mount(0, 0L);
+	}
+	else
+	{
+		// xprintf("could not initialize SD card\r\n");
+	}
+}
+
+err_t srec_load(char *flash_filename)
+{
+	FRESULT fres;
+	FIL file;
+	err_t err;
+	void *start_address;
+	uint32_t length;
+
+	if ((fres = f_open(&file, flash_filename, FA_READ) != FR_OK))
+	{
+		xprintf("flasher file %s not present on disk\r\n", flash_filename);
+	}
+	else
+	{
+		f_close(&file);
+
+		/* first pass: parse and check for inconsistencies */
+		xprintf("check file integrity: ");
+		err = read_srecords(flash_filename, &start_address, &length, simulate);
+		if (err == OK)
+		{
+			/* next pass: copy data to destination */
+			xprintf("OK.\r\ncopy/flash data: ");
+			err = read_srecords(flash_filename, &start_address, &length, flash);
+			if (err == OK)
+			{
+				/* next pass: verify data */
+				xprintf("OK.\r\nverify data: ");
+				err = read_srecords(flash_filename, &start_address, &length, verify);
+				if (err == OK)
+				{
+					typedef void void_func(void);
+					void_func *func;
+
+					xprintf("OK.\r\n");
+					xprintf(
+							"target successfully written and verified. Start address: %p\r\n",
+							start_address);
+
+					func = (void_func *) start_address;
+					(*func)();
+				}
+				else
+				{
+					xprintf("failed\r\n");
+				}
+			}
+			else
+			{
+				xprintf("failed\r\n");
+			}
+		}
+		else
+		{
+			xprintf("failed\r\n");
+		}
+	}
+	return OK;
+}
+
+void basflash(void)
+{
+	// const char *basflash_str = "\\BASFLASH";
+	const char *bastest_str = "\\BASTEST";
+	DRESULT res;
+	FRESULT fres;
+	FATFS fs;
+
+	xprintf("\r\nHello from BASFLASH.S19!\r\n\r\n");
+
+	/*
+	 * read \BASTEST\ folder contents (search for .S19-files). If found load them to their final destination
+	 * (after BaS has copied them, not their flash location) and return.
+	 *
+	 * Files located in the BASTEST-folder thus override those in flash. Useful for testing before flashing
+	 */
+	res = disk_status(0);
+	xprintf("disk_status(0) = %d\r\n", res);
+	if (res == RES_OK)
+	{
+		fres = f_mount(0, &fs);
+		xprintf("f_mount() = %d\r\n", fres);
+		if (fres == FR_OK)
+		{
+			DIR directory;
+
+			fres = f_opendir(&directory, bastest_str);
+			xprintf("f_opendir() = %d\r\n", fres);
+			if (fres == FR_OK)
+			{
+				FILINFO fileinfo;
+
+				fres = f_readdir(&directory, &fileinfo);
+				xprintf("f_readdir() = %d\r\n", fres);
+				while (fres == FR_OK)
+				{
+					const char *srec_ext = ".S19";
+					char path[30];
+
+					if (fileinfo.fname[0] != '\0') /* found a file */
+					{
+						xprintf("check file %s (%s == %s ?)\r\n",
+								fileinfo.fname,
+								&fileinfo.fname[strlen(fileinfo.fname) - 4],
+								srec_ext);
+						if (strlen(fileinfo.fname) >= 4
+								&& strncmp(
+										&fileinfo.fname[strlen(fileinfo.fname)
+														- 4], srec_ext, 4) == 0) /* we have a .S19 file */
+						{
+							/*
+							 * build path + filename
+							 */
+							strcpy(path, bastest_str);
+							strcat(path, "\\");
+							strncat(path, fileinfo.fname, 13);
+
+							xprintf("loading file %s\r\n", path);
+							/*
+							 * load file
+							 */
+							if (srec_load(path) != OK)
+							{
+								xprintf("failed to load file %s\r\n", path);
+								// error handling
+							}
+						}
+					}
+					else
+						break; /* exit if no file found */
+					fres = f_readdir(&directory, &fileinfo);
+					xprintf("f_readdir() = %d\r\n", fres);
+				}
+			}
+			else
+			{
+				xprintf("f_opendir %s failed with error code %d\r\n",
+						bastest_str, fres);
+			}
+		}
+		else
+		{
+			// xprintf("could not mount FAT FS\r\n");
+		}
+		f_mount(0, 0L); /* unmount SD card */
+	}
+}
--- a/exe/basflash_start.c
+++ b/exe/basflash_start.c
@@ -1,5 +1,6 @@
 /*
- * cache handling
+ * basflash_start.c
+ *
 *
 * This file is part of BaS_gcc.
 *
@@ -16,33 +17,26 @@
 * You should have received a copy of the GNU General Public License
 * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
 *
- * Copyright 2010 - 2012 F. Aschwanden
- * Copyright 2011 - 2012 V. Riviere
- * Copyright 2012        M. Froeschle
- *
+ *  Created on: 26.02.2013
+ *      Author: Markus Fröschle
 */

-#include "cache.h"
+#include <bas_types.h>

-void flush_and_invalidate_caches(void)
+static uint32_t ownstack[4096];
+static uint32_t *stackptr = &ownstack[4095];
+
+/*
+ * setup our own stack in SDRAM to prevent clashing BaS's in SRAM (size limited).
+ */
+void startup(void)
 {
-	__asm__ (
-	"	clr.l		d0\n\t"
-	"	clr.l		d1\n\t"
-	"	move.l		d0,a0\n\t"
-	"cfa_setloop:\n\t"
-	"	cpushl		bc,(a0)				| flush\n\t"
-	"	lea			0x10(a0),a0			| index+1\n\t"
-	"	addq.l		#1,d1				| index+1\n\t"
-	"	cmpi.w		#512,d1				| all sets?\n\t"
-	"	bne.s		cfa_setloop			| no->\n\t"
-	"	clr.l		d1\n\t"
-	"	addq.l		#1,d0\n\t"
-	"	move.l		d0,a0\n\t"
-	"	cmpi.w		#4,d0				| all ways?\n\t"
-	"	bne.s		cfa_setloop			| no->\n\t"
-	/* input */	:
-	/* output */	:
-	/* clobber */	: "d0", "d1", "a0"
-	);
+	static uint32_t oldstack;
+
+	void basflash(void);
+	__asm__ __volatile__("move.l	sp,%0\n\t" : "=g"(oldstack) : :);
+	__asm__ __volatile__("move.l	%0,sp\n\t" : : "g"(stackptr) : );
+	basflash();
+	__asm__ __volatile__("move.l	%0,sp\n\t" : : "g"(oldstack) : "sp");
+	(void) stackptr; /* make compiler happy about unused variables */
 }
--- a/flash/flash.c
+++ b/flash/flash.c
@@ -0,0 +1,381 @@
+#include <stddef.h>
+#include "bas_types.h"
+
+#if MACHINE_FIREBEE
+#include "firebee.h"
+#elif MACHINE_M5484LITE
+#include "m5484l.h"
+#endif /* MACHINE_FIREBEE */
+
+#define AMD_FLASH_BUS_SHIFT     1
+#define AMD_FLASH_CELL          volatile uint16_t
+#define AMD_FLASH_CELL_BYTES    2
+#define AMD_FLASH_CELL_MASK     0x1
+#define AMD_FLASH_CMD_DATA(x)   ((uint16_t) x)
+
+struct amd_flash_sector_info
+{
+	uint32_t size; /* sector size in bytes */
+	uint32_t offset; /* offset from base of device */
+};
+
+/*
+ * AM29LV640D flash layout (bottom boot as used in the Firebee )
+ */
+static struct amd_flash_sector_info sector[] =
+{
+		{  8 * 1024, 0x00000000 }, /* SA0 */
+		{  8 * 1024, 0x00008000 }, /* SA1 */
+		{  8 * 1024, 0x00010000 }, /* SA2 */
+		{  8 * 1024, 0x00018000 }, /* SA3 */
+		{  8 * 1024, 0x00020000 }, /* SA4 */
+		{  8 * 1024, 0x00028000 }, /* SA5 */
+		{  8 * 1024, 0x00030000 }, /* SA6 */
+		{  8 * 1024, 0x00038000 }, /* SA7 */
+		{  8 * 1024, 0x00040000 }, /* SA8 */
+		{ 64 * 1024, 0x00048000 }, /* SA9 */
+		{ 64 * 1024, 0x00050000 }, /* SA10 */
+		{ 64 * 1024, 0x00058000 }, /* SA11 */
+		{ 64 * 1024, 0x00060000 }, /* SA12 */
+		{ 64 * 1024, 0x00068000 }, /* SA13 */
+		{ 64 * 1024, 0x00070000 }, /* SA14 */
+		{ 64 * 1024, 0x00078000 }, /* SA15 */
+		{ 64 * 1024, 0x00080000 }, /* SA16 */
+		{ 64 * 1024, 0x00088000 }, /* SA17 */
+		{ 64 * 1024, 0x00090000 }, /* SA18 */
+		{ 64 * 1024, 0x00098000 }, /* SA19 */
+		{ 64 * 1024, 0x000a0000 }, /* SA20 */
+		{ 64 * 1024, 0x000a8000 }, /* SA21 */
+		{ 64 * 1024, 0x000b0000 }, /* SA22 */
+		{ 64 * 1024, 0x000b8000 }, /* SA23 */
+		{ 64 * 1024, 0x000c0000 }, /* SA24 */
+		{ 64 * 1024, 0x000c8000 }, /* SA25 */
+		{ 64 * 1024, 0x000d0000 }, /* SA26 */
+		{ 64 * 1024, 0x000d8000 }, /* SA27 */
+		{ 64 * 1024, 0x000e0000 }, /* SA28 */
+		{ 64 * 1024, 0x000e8000 }, /* SA29 */
+		{ 64 * 1024, 0x000f0000 }, /* SA30 */
+		{ 64 * 1024, 0x000f8000 }, /* SA31 */
+		{ 64 * 1024, 0x00100000 }, /* SA32 */
+		{ 64 * 1024, 0x00108000 }, /* SA32 */
+		{ 64 * 1024, 0x00110000 }, /* SA34 */
+		{ 64 * 1024, 0x00118000 }, /* SA35 */
+		{ 64 * 1024, 0x00120000 }, /* SA36 */
+		{ 64 * 1024, 0x00128000 }, /* SA37 */
+		{ 64 * 1024, 0x00130000 }, /* SA38 */
+		{ 64 * 1024, 0x00138000 }, /* SA39 */
+		{ 64 * 1024, 0x00140000 }, /* SA40 */
+		{ 64 * 1024, 0x00148000 }, /* SA41 */
+		{ 64 * 1024, 0x00150000 }, /* SA42 */
+		{ 64 * 1024, 0x00158000 }, /* SA43 */
+		{ 64 * 1024, 0x00160000 }, /* SA44 */
+		{ 64 * 1024, 0x00168000 }, /* SA45 */
+		{ 64 * 1024, 0x00170000 }, /* SA46 */
+		{ 64 * 1024, 0x00178000 }, /* SA47 */
+		{ 64 * 1024, 0x00180000 }, /* SA48 */
+		{ 64 * 1024, 0x00188000 }, /* SA49 */
+		{ 64 * 1024, 0x00190000 }, /* SA50 */
+		{ 64 * 1024, 0x00198000 }, /* SA51 */
+		{ 64 * 1024, 0x001a0000 }, /* SA52 */
+		{ 64 * 1024, 0x001a8000 }, /* SA53 */
+		{ 64 * 1024, 0x001b0000 }, /* SA54 */
+		{ 64 * 1024, 0x001b8000 }, /* SA55 */
+		{ 64 * 1024, 0x001c0000 }, /* SA56 */
+		{ 64 * 1024, 0x001c8000 }, /* SA57 */
+		{ 64 * 1024, 0x001d0000 }, /* SA58 */
+		{ 64 * 1024, 0x001d8000 }, /* SA59 */
+		{ 64 * 1024, 0x001e0000 }, /* SA60 */
+		{ 64 * 1024, 0x001e8000 }, /* SA61 */
+		{ 64 * 1024, 0x001f0000 }, /* SA62 */
+		{ 64 * 1024, 0x001f8000 }, /* SA63 */
+		{ 64 * 1024, 0x00200000 }, /* SA64 */
+		{ 64 * 1024, 0x00208000 }, /* SA65 */
+		{ 64 * 1024, 0x00210000 }, /* SA66 */
+		{ 64 * 1024, 0x00218000 }, /* SA67 */
+		{ 64 * 1024, 0x00220000 }, /* SA68 */
+		{ 64 * 1024, 0x00228000 }, /* SA69 */
+		{ 64 * 1024, 0x00230000 }, /* SA70 */
+		{ 64 * 1024, 0x00238000 }, /* SA71 */
+		{ 64 * 1024, 0x00240000 }, /* SA72 */
+		{ 64 * 1024, 0x00248000 }, /* SA73 */
+		{ 64 * 1024, 0x00250000 }, /* SA74 */
+		{ 64 * 1024, 0x00258000 }, /* SA75 */
+		{ 64 * 1024, 0x00260000 }, /* SA76 */
+		{ 64 * 1024, 0x00268000 }, /* SA77 */
+		{ 64 * 1024, 0x00270000 }, /* SA78 */
+		{ 64 * 1024, 0x00278000 }, /* SA79 */
+		{ 64 * 1024, 0x00280000 }, /* SA80 */
+		{ 64 * 1024, 0x00288000 }, /* SA81 */
+		{ 64 * 1024, 0x00290000 }, /* SA82 */
+		{ 64 * 1024, 0x00298000 }, /* SA83 */
+		{ 64 * 1024, 0x002a0000 }, /* SA84 */
+		{ 64 * 1024, 0x002a8000 }, /* SA85 */
+		{ 64 * 1024, 0x002b0000 }, /* SA86 */
+		{ 64 * 1024, 0x002b8000 }, /* SA87 */
+		{ 64 * 1024, 0x002c0000 }, /* SA88 */
+		{ 64 * 1024, 0x002c8000 }, /* SA89 */
+		{ 64 * 1024, 0x002d0000 }, /* SA90 */
+		{ 64 * 1024, 0x002d8000 }, /* SA91 */
+		{ 64 * 1024, 0x002e0000 }, /* SA92 */
+		{ 64 * 1024, 0x002e8000 }, /* SA93 */
+		{ 64 * 1024, 0x002f0000 }, /* SA94 */
+		{ 64 * 1024, 0x002f8000 }, /* SA95 */
+		{ 64 * 1024, 0x00300000 }, /* SA96 */
+		{ 64 * 1024, 0x00308000 }, /* SA97 */
+		{ 64 * 1024, 0x00310000 }, /* SA98 */
+		{ 64 * 1024, 0x00318000 }, /* SA99 */
+		{ 64 * 1024, 0x00320000 }, /* SA100 */
+		{ 64 * 1024, 0x00328000 }, /* SA101 */
+		{ 64 * 1024, 0x00330000 }, /* SA102 */
+		{ 64 * 1024, 0x00338000 }, /* SA103 */
+		{ 64 * 1024, 0x00340000 }, /* SA104 */
+		{ 64 * 1024, 0x00348000 }, /* SA105 */
+		{ 64 * 1024, 0x00350000 }, /* SA106 */
+		{ 64 * 1024, 0x00358000 }, /* SA107 */
+		{ 64 * 1024, 0x00360000 }, /* SA108 */
+		{ 64 * 1024, 0x00368000 }, /* SA109 */
+		{ 64 * 1024, 0x00370000 }, /* SA110 */
+		{ 64 * 1024, 0x00378000 }, /* SA111 */
+		{ 64 * 1024, 0x00380000 }, /* SA112 */
+		{ 64 * 1024, 0x00388000 }, /* SA113 */
+		{ 64 * 1024, 0x00390000 }, /* SA114 */
+		{ 64 * 1024, 0x00398000 }, /* SA115 */
+		{ 64 * 1024, 0x003a0000 }, /* SA116 */
+		{ 64 * 1024, 0x003a8000 }, /* SA117 */
+		{ 64 * 1024, 0x003b0000 }, /* SA118 */
+		{ 64 * 1024, 0x003b8000 }, /* SA119 */
+		{ 64 * 1024, 0x003c0000 }, /* SA120 */
+		{ 64 * 1024, 0x003c8000 }, /* SA121 */
+		{ 64 * 1024, 0x003d0000 }, /* SA122 */
+		{ 64 * 1024, 0x003d8000 }, /* SA123 */
+		{ 64 * 1024, 0x003e0000 }, /* SA124 */
+		{ 64 * 1024, 0x003e8000 }, /* SA125 */
+		{ 64 * 1024, 0x003f0000 }, /* SA126 */
+		{ 64 * 1024, 0x003f8000 }, /* SA127 */
+};
+
+static const int AMD_FLASH_SECTORS = sizeof(sector)	/ sizeof(struct amd_flash_sector_info);
+
+#define SOFFSET(n)  (sector[n].offset)
+#define SADDR(n)    (SOFFSET(n) >> AMD_FLASH_BUS_SHIFT)
+#define SSIZE(n)	(sector[n].size)
+
+#define AMD_FLASH_DEVICES	1
+
+static AMD_FLASH_CELL *pFlash;
+
+typedef struct romram
+{
+	uint32_t flash_address;
+	uint32_t ram_address;
+	char *name;
+} ROMRAM;
+
+static const struct romram flash_areas[] =
+{
+	{ 0xe0000000, 0x00e00000, "BaS" },		/* BaS */
+	{ 0xe0600000, 0x00e00000, "EmuTOS" }, 	/* EmuTOS */
+	{ 0xe0400000, 0x00e00000, "FireTOS" }, 	/* FireTOS */
+	{ 0xe0700000, 0x00e00000, "FPGA" },		/* FPGA config */
+};
+static const int num_flash_areas = sizeof(flash_areas) / sizeof(struct romram);
+
+#define FLASH_ADDRESS BOOTFLASH_BASE_ADDRESS
+
+/*
+ * erase a flash sector
+ *
+ * sector_num is the index into the sector table above.
+ *
+ * FIXME: need to disable data cache to ensure proper operation
+ */
+void amd_flash_sector_erase(int n)
+{
+	volatile AMD_FLASH_CELL status;
+
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);
+
+	do
+		status = pFlash[SADDR(n)];
+	while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));
+
+	/*
+	 * Place device in read mode
+	 */
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+}
+
+int amd_flash_erase(void *start, int bytes, void (*putchar)(int))
+{
+	int i, ebytes = 0;
+
+	if (bytes == 0)
+		return 0;
+
+	for (i = 0; i < AMD_FLASH_SECTORS; i++)
+	{
+		if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
+			start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
+		{
+			break;
+		}
+	}
+
+	while (ebytes < bytes)
+	{
+		if (putchar != NULL)
+		{
+			putchar('.');
+		}
+		amd_flash_sector_erase(i);
+		ebytes += SSIZE(i);
+		i++;
+	}
+
+	if (putchar != NULL)
+	{
+		putchar(10);    /* LF */
+		putchar(13);    /* CR */
+	}
+
+	return ebytes;
+}
+
+void amd_flash_program_cell(AMD_FLASH_CELL *dst, AMD_FLASH_CELL data)
+{
+	volatile AMD_FLASH_CELL status;
+	int retry;
+
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
+	*dst = data;
+
+	/*
+	 * Wait for program operation to finish
+	 *  (Data# Polling Algorithm)
+	 */
+	retry = 0;
+	while (1)
+	{
+		status = *dst;
+		if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
+			(data & AMD_FLASH_CMD_DATA(0x80)))
+		{
+			break;
+		}
+		if (status & AMD_FLASH_CMD_DATA(0x20))
+		{
+			status = *dst;
+			if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
+				(data & AMD_FLASH_CMD_DATA(0x80)))
+			{
+				break;
+			}
+			if (++retry > 1024)
+			{
+				break;
+			}
+		}
+	}
+}
+
+
+int amd_flash_program(void *dest, void *source, int bytes, int erase, void (*func)(void), void (*putchar)(int))
+{
+	AMD_FLASH_CELL *src;
+	AMD_FLASH_CELL *dst;
+	int hashi = 1;
+	int hashj = 0;
+	char hash[5];
+
+	hash[0] = 8;  /* Backspace */
+	hash[1] = 124;/* "|" */
+	hash[2] = 47; /* "/" */
+	hash[3] = 45; /* "-" */
+	hash[4] = 92; /* "\" */
+
+	src = (AMD_FLASH_CELL *)source;
+	dst = (AMD_FLASH_CELL *)dest;
+
+	/*
+	 * Place device in read mode
+	 */
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+
+	/*
+	 * Erase device if necessary
+	 */
+	if (erase)
+	{
+		amd_flash_erase(dest, bytes, putchar);
+	}
+
+	/*
+	 * Program device
+	 */
+	while (bytes > 0)
+	{
+		amd_flash_program_cell(dst, *src);
+
+		/* Verify Write */
+		if (*dst == *src)
+		{
+			bytes -= AMD_FLASH_CELL_BYTES;
+			*dst++, *src++;
+
+			if ((putchar != NULL))
+			{
+				/* Hash marks to indicate progress */
+				if (hashj == 0x1000)
+				{
+					hashj = -1;
+					putchar(hash[0]);
+					putchar(hash[hashi]);
+
+					hashi++;
+					if (hashi == 5)
+					{
+						hashi = 1;
+					}
+
+				}
+				hashj++;
+			}
+		}
+		else
+			break;
+	}
+
+	/*
+	 * Place device in read mode
+	 */
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+
+	if (putchar != NULL)
+	{
+		putchar(hash[0]);
+	}
+
+	/*
+	 * If a function was passed in, call it now
+	 */
+	if ((func != NULL))
+	{
+		func();
+	}
+
+	return ((int)src - (int)source);
+}
+
--- a/sources/s19reader.c
+++ b/sources/s19reader.c
@@ -23,11 +23,10 @@
 * Copyright 2012        M. Froeschle
 */

-#include <stdint.h>
-#include <stdbool.h>
-#include <stdlib.h>
+#include <bas_types.h>

 #include "bas_printf.h"
+#include "bas_string.h"
 #include "sd_card.h"
 #include "diskio.h"
 #include "ff.h"
@@ -78,6 +77,7 @@ static uint8_t hex_to_byte(uint8_t hex[2])
 	return 16 * (nibble_to_byte(hex[0])) + (nibble_to_byte(hex[1]));
 }

+#ifdef _NOT_USED_
 /*
 * convert four hex characters into a 16 bit word
 */
@@ -93,6 +93,7 @@ static uint32_t hex_to_long(uint8_t hex[8])
 {
 	return 65536 * hex_to_word(&hex[0]) + hex_to_word(&hex[4]);
 }
+#endif /* _NOT_USED_ */

 /*
 * compute the record checksum
@@ -308,26 +309,19 @@ static err_t simulate()
 	return ret;
 }

-static err_t memcpy(uint8_t *dst, uint8_t *src, uint32_t length)
-{
-	uint8_t *end = src + length;
-
-	do
-	{
-		*dst++ = *src++;
-	} while (src < end);
-
-	return OK;
-}

+#ifdef _NOT_USED_
 static err_t flash(uint8_t *dst, uint8_t *src, uint32_t length)
 {
 	err_t ret = OK;

 	/* TODO: do the actual flash */
+	amd_flash_program(dst, src, length, false, NULL, xputchar);

 	return ret;
 }
+#endif /* _NOT_USED_ */
+

 /*
 * this callback verifies the data against the S-record file contents after a write to destination
@@ -345,6 +339,17 @@ static err_t verify(uint8_t *dst, uint8_t *src, uint32_t length)
 	return OK;
 }

+/*
+ * needed to avoid missing type cast warning below
+ */
+static inline err_t srec_memcpy(uint8_t *dst, uint8_t *src, size_t n)
+{
+	err_t e = OK;
+
+	memcpy((void *) dst, (void *) src, n);
+	return e;
+}
+
 void srec_execute(char *flasher_filename)
 {
 	DRESULT res;
@@ -377,7 +382,7 @@ void srec_execute(char *flasher_filename)
 				{
 					/* next pass: copy data to destination */
 					xprintf("OK.\r\ncopy/flash data: ");
-					err = read_srecords(flasher_filename, &start_address, &length, memcpy);
+					err = read_srecords(flasher_filename, &start_address, &length, srec_memcpy);
 					if (err == OK)
 					{
 						/* next pass: verify data */
--- a/flash_scripts/flash_bas.bdm
+++ b/flash_scripts/flash_bas.bdm
@@ -1,52 +0,0 @@
-#!/usr/local/bin/bdmctrl -D2
-#
-# firebee board initialization for bdmctrl 
-#
-open $1
-reset
-sleep 10
-
-wait
-
-# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
-write 0xFF000500 0xE0000000 4
-write 0xFF000508 0x00001180 4
-write 0xFF000504 0x007F0001 4
-
-
-# notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
-flash 0xE0000000
-
-# flash-plugin (target-based flashing) does not work yet 
-#flash-plugin 0x10000000 0x4000 flash29.plugin
-
-# Erase flash from 0xE0000000 to 0xE00FFFFF (reserved space for BaS)
-#
-# Caution: sector offset numbers need to be the ones from the x16 address range
-# column and they vary in size - needs to be exactly as in the data sheet (p. 9)
-#
-# contrary to documentation, it seems we need to erase-wait after each sector
-
-erase 0xE0000000 0x00000
-erase-wait 0xE0000000
-erase 0xE0000000 0x01000
-erase-wait 0xE0000000
-erase 0xE0000000 0x02000
-erase-wait 0xE0000000
-erase 0xE0000000 0x03000
-erase-wait 0xE0000000
-erase 0xE0000000 0x04000
-erase-wait 0xE0000000
-erase 0xE0000000 0x05000
-erase-wait 0xE0000000
-erase 0xE0000000 0x06000
-erase-wait 0xE0000000
-erase 0xE0000000 0x07000
-erase-wait 0xE0000000
-erase 0xE0000000 0x08000
-erase-wait 0xE0000000
-erase 0xE0000000 0x10000
-erase-wait 0xE0000000
-blank-chk 0xE0000000 0x00000 
-load -v bas.elf
-wait
--- a/flash_scripts/flash_firebee_bas.bdm
+++ b/flash_scripts/flash_firebee_bas.bdm
@@ -0,0 +1,53 @@
+#!/usr/local/bin/bdmctrl -D2
+#
+# firebee board initialization for bdmctrl 
+#
+open $1
+reset
+sleep 1
+
+wait
+
+# use system sdram as flashlib scratch area.
+# TODO: plugin flashing seems to work o.k. now for smaller binaries, while it doesn't for larger ones (EmuTOS) yet.
+# This seems to be related to large flash buffers and PC-relative adressing of the plugin
+#flash-plugin 0x1000 0xf000 flash29-5475.plugin
+# notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
+flash 0xe0000000
+
+# Erase flash from 0xE0000000 to 0xE00FFFFF (reserved space for BaS)
+#
+# Caution: sector offset numbers need to be the ones from the x16 address range
+# column and they vary in size - needs to be exactly as in the data sheet (p. 9)
+#
+
+erase 0xe0000000 0
+erase 0xe0000000 0x1000
+erase 0xe0000000 0x2000
+erase 0xe0000000 0x3000
+erase 0xe0000000 0x4000
+erase 0xe0000000 0x5000
+erase 0xe0000000 0x6000
+erase 0xe0000000 0x7000
+erase 0xe0000000 0x8000
+erase 0xe0000000 0x10000
+erase 0xe0000000 0x18000
+erase 0xe0000000 0x20000
+erase 0xe0000000 0x28000
+erase 0xe0000000 0x30000
+erase 0xe0000000 0x38000
+erase 0xe0000000 0x40000
+erase 0xe0000000 0x48000
+erase 0xe0000000 0x50000
+erase 0xe0000000 0x58000
+erase 0xe0000000 0x60000
+erase 0xe0000000 0x70000
+erase 0xe0000000 0x78000
+
+erase-wait 0xe0000000
+# should now have erased from 0xe0000000 to 0xe00fffff
+
+dump-mem 0xe0010000 0x20 b
+
+load -v ../firebee/bas.elf
+wait
--- a/flash_scripts/flash_firebee_etos.bdm
+++ b/flash_scripts/flash_firebee_etos.bdm
@@ -10,6 +10,31 @@ write 0xFF000500 0xE0000000 4
 write 0xFF000508 0x00001180 4
 write 0xFF000504 0x007F0001 4

+# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
+write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
+write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
+write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
+write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
+write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
+write 0xFF000108 0x73622830 4 # SDCFG1
+write 0xFF00010C 0x46770000 4 # SDCFG2
+
+write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
+write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
+write 0xFF000100 0x048D0000 4 # SDMR (write to LMR)
+sleep 100
+write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
+write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
+write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
+write 0xFF000100 0x008D0000 4 # SDMR (write to LMR)
+write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
+sleep 10
+
+
+# use system sdram as flashlib scratch area
+# flashing EmuTOS with plugin does not work yet (at least not for 64bit hosts)
+#flash-plugin 0x1000 0xf000 flash29.plugin
+
 # notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
 flash 0xe0000000

@@ -53,4 +78,4 @@ erase-wait 0xe0000000
 erase 0xe0000000 0x378000
 erase-wait 0xe0000000

-load -v emutosfb.elf
+load -v emutos-firebee.elf
--- a/flash_scripts/flash_firebee_firetos.bdm
+++ b/flash_scripts/flash_firebee_firetos.bdm
--- a/flash_scripts/flash_firebee_fpga.bdm
+++ b/flash_scripts/flash_firebee_fpga.bdm
--- a/flash_scripts/flash_m548x_bas.bdm
+++ b/flash_scripts/flash_m548x_bas.bdm
@@ -0,0 +1,92 @@
+#!/usr/local/bin/bdmctrl 
+#
+# m548x board initialization for bdmctrl 
+#
+open $1
+reset
+wait
+
+# set VBR
+write-ctrl 0x0801 0x00000000
+dump-register VBR
+
+# Turn on MBAR at 0xFF00_0000
+write-ctrl 0x0C0F 0xFF000000
+dump-register MBAR
+
+# Turn on RAMBAR0 at address FF10_0000 
+write-ctrl 0x0C04 0xFF100007
+
+# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently)
+write-ctrl 0x0C05 0xFF101001
+
+#
+# Init CS0 (BootFLASH @ E000_0000 - E03F_FFFF 4Mbytes)
+write 0xFF000500 0xE0000000 4
+#write 0xFF000508 0x00041180 4
+write 0xFF000508 0x00100D80 4
+write 0xFF000504 0x003F0001 4
+
+# SDRAM Initialization @ 0000_0000 - 03FF_FFFF 64 Mbytes
+write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
+write 0xFF000020 0x00000019 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
+write 0xFF000024 0x08000000 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
+write 0xFF000028 0x10000000 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
+write 0xFF00002C 0x18000000 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
+write 0xFF000108 0x73711630 4 # SDCFG1
+write 0xFF00010C 0x46370000 4 # SDCFG2
+
+write 0xFF000104 0xE10B0002 4 # SDCR + IPALL
+write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
+write 0xFF000100 0x058D0000 4 # SDMR (write to LMR)
+sleep 100
+write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
+write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
+write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
+write 0xFF000100 0x018D0000 4 # SDMR (write to LMR)
+write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
+sleep 10
+
+
+# use system sdram as flashlib scratch area.
+# TODO: plugin flashing seems to work o.k. now for smaller binaries, while it doesn't for larger ones (EmuTOS) yet.
+# This seems to be related to large flash buffers and PC-relative adressing of the plugin
+#flash-plugin 0x1000 0xf000 flash29.plugin
+# notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
+flash 0xE0000000
+flash-plugin 0x1000 0xf000 flashintelc3.plugin
+
+# Erase flash from 0xE0000000 to 0xE00FFFFF (reserved space for bas)
+#
+# Caution: sector offset numbers need to be the ones from the x16 address range
+# column and they vary in size - needs to be exactly as in the data sheet (p. 9)
+#
+# contrary to documentation, it seems we need to erase-wait after each sector
+
+erase 0xE0000000 0
+erase 0xE0000000 1
+erase 0xE0000000 2
+erase 0xE0000000 3
+erase 0xE0000000 4
+erase 0xE0000000 5
+erase 0xE0000000 6
+erase 0xE0000000 7
+erase 0xE0000000 8
+erase 0xE0000000 9
+erase 0xE0000000 10
+erase 0xE0000000 11
+erase 0xE0000000 12
+erase 0xE0000000 13
+#erase 0xE0000000 0x2000
+#erase 0xE0000000 0x3000
+#erase 0xE0000000 0x4000
+#erase 0xE0000000 0x5000
+#erase 0xE0000000 0x00006000
+#erase 0xE0000000 0x00007000
+#erase 0xE0000000 0x00008000
+#erase 0xE0000000 0x00009000
+#erase 0xE0000000 0x0000a000
+#erase 0xE0000000 0x0000b000
+#erase-wait 0xe0000000
+load -v ../m5484lite/bas.elf
+wait
--- a/flash_scripts/flash_m548x_dbug.bdm
+++ b/flash_scripts/flash_m548x_dbug.bdm
@@ -0,0 +1,78 @@
+#!/usr/local/bin/bdmctrl 
+#
+# m548x board initialization for bdmctrl 
+#
+open $1
+reset
+wait
+
+# set VBR
+write-ctrl 0x0801 0x00000000
+dump-register VBR
+
+# Turn on MBAR at 0xFF00_0000
+write-ctrl 0x0C0F 0xFF000000
+dump-register MBAR
+
+# Turn on RAMBAR0 at address FF10_0000 
+write-ctrl 0x0C04 0xFF100007
+
+# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently)
+write-ctrl 0x0C05 0xFF101001
+
+#
+# Init CS0 (BootFLASH @ E000_0000 - E03F_FFFF 4Mbytes)
+write 0xFF000500 0xE0000000 4
+write 0xFF000508 0x00041180 4
+write 0xFF000504 0x003F0001 4
+
+# SDRAM Initialization @ 0000_0000 - 03FF_FFFF 64 Mbytes
+write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
+write 0xFF000020 0x00000019 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
+write 0xFF000024 0x08000000 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
+write 0xFF000028 0x10000000 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
+write 0xFF00002C 0x18000000 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
+write 0xFF000108 0x73711630 4 # SDCFG1
+write 0xFF00010C 0x46370000 4 # SDCFG2
+
+write 0xFF000104 0xE10B0002 4 # SDCR + IPALL
+write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
+write 0xFF000100 0x058D0000 4 # SDMR (write to LMR)
+sleep 100
+write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
+write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
+write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
+write 0xFF000100 0x018D0000 4 # SDMR (write to LMR)
+write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
+sleep 10
+
+
+# use system sdram as flashlib scratch area.
+# TODO: plugin flashing seems to work o.k. now for smaller binaries, while it doesn't for larger ones (EmuTOS) yet.
+# This seems to be related to large flash buffers and PC-relative adressing of the plugin
+#flash-plugin 0x1000 0xf000 flash29.plugin
+# notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
+flash 0xE0000000
+flash-plugin 0x1000 0xf000 flashintelc3.plugin
+
+# Erase flash from 0xE0000000 to 0xE00FFFFF (reserved space for bas)
+#
+# Caution: sector offset numbers need to be the ones from the x16 address range
+# column and they vary in size - needs to be exactly as in the data sheet (p. 9)
+#
+# contrary to documentation, it seems we need to erase-wait after each sector
+
+#erase 0xE0000000 0x0
+#erase 0xE0002000 0x0
+#erase 0xE0000000 0x00004000
+#erase 0xE0000000 0x00005000
+#erase 0xE0000000 0x00006000
+#erase 0xE0000000 0x00007000
+#erase 0xE0000000 0x00008000
+#erase 0xE0000000 0x00009000
+#erase 0xE0000000 0x0000a000
+#erase 0xE0000000 0x0000b000
+#erase-wait 0xe0000000
+#blank-chk 0xE0000000 0x0
+load -v m5484lite_dbug_flash.elf
+wait
--- a/flash_scripts/flash_m548x_etos.bdm
+++ b/flash_scripts/flash_m548x_etos.bdm
@@ -0,0 +1,66 @@
+#!/usr/local/bin/bdmctrl -D2
+#
+# flash EmuTOS using bdmctrl
+#
+open $1
+reset
+
+# Turn on RAMBAR0 at address FF10_0000 
+write-ctrl 0x0C04 0xFF100007
+
+# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
+write 0xFF000500 0xE0000000 4
+write 0xFF000508 0x00001180 4
+write 0xFF000504 0x007F0001 4
+
+# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
+write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
+write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
+write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
+write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
+write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
+write 0xFF000108 0x73622830 4 # SDCFG1
+write 0xFF00010C 0x46770000 4 # SDCFG2
+
+write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
+write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
+write 0xFF000100 0x048D0000 4 # SDMR (write to LMR)
+sleep 100
+write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
+write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
+write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
+write 0xFF000100 0x008D0000 4 # SDMR (write to LMR)
+write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
+sleep 10
+
+
+# use sram as flashlib scratch area
+# flashing EmuTOS with plugin does not work yet (at least not for 64bit hosts)
+#flash-plugin 0xFF101000 0xffff flashintelc3.plugin
+
+# notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
+flash 0xe0000000
+
+# Erase flash from 0xE0100000 to 0xE01FFFFF (reserved space for EmuTOS on the m5484lite)
+
+erase 0xe0000000 21
+erase 0xe0000000 22
+erase 0xe0000000 23
+erase 0xe0000000 24
+erase 0xe0000000 25
+erase 0xe0000000 26
+erase 0xe0000000 27
+erase 0xe0000000 28
+erase 0xe0000000 29
+erase 0xe0000000 30
+erase 0xe0000000 31
+erase 0xe0000000 32
+erase 0xe0000000 33
+erase 0xe0000000 34
+erase 0xe0000000 35
+erase 0xe0000000 36
+erase 0xe0000000 37
+erase 0xe0000000 38
+erase 0xe0000000 39
+
+load ../../emutos/emutos-m548x_bas.elf
--- a/sources/cc932.c
+++ b/sources/cc932.c
--- a/sources/cc936.c
+++ b/sources/cc936.c
--- a/sources/cc949.c
+++ b/sources/cc949.c
--- a/sources/cc950.c
+++ b/sources/cc950.c
--- a/sources/ccsbcs.c
+++ b/sources/ccsbcs.c
@@ -26,7 +26,7 @@
 */

 #include <ff.h>
-#include <stdint.h>
+#include <bas_types.h>

 #if _CODE_PAGE == 437
 #define _TBLDEF 1
--- a/sources/ff.c
+++ b/sources/ff.c
@@ -95,7 +95,7 @@
 /                   Changed option name _FS_SHARE to _FS_LOCK.
 /---------------------------------------------------------------------------*/

-#include <stdint.h>
+#include <bas_types.h>
 #include <ff.h>			/* FatFs configurations and declarations */
 #include <diskio.h>		/* Declarations of low level disk I/O functions */

@@ -356,11 +356,11 @@ typedef struct {
 uint32_t get_fattime (void)
 {
   return     ((uint32_t)(2012 - 1980) << 25)   /* Year = 2012 */
-         | ((uint32_t)1 << 21)            /* Month = 1 */
-         | ((uint32_t)1 << 16)            /* Day_m = 1*/
-         | ((uint32_t)0 << 11)            /* Hour = 0 */
-         | ((uint32_t)0 << 5)          /* Min = 0 */
-         | ((uint32_t)0 >> 1);            /* Sec = 0 */
+		 | ((uint32_t)1 << 21)            /* Month = 1 */
+		 | ((uint32_t)1 << 16)            /* Day_m = 1*/
+		 | ((uint32_t)0 << 11)            /* Hour = 0 */
+		 | ((uint32_t)0 << 5)          /* Min = 0 */
+		 | ((uint32_t)0 >> 1);            /* Sec = 0 */
 }

 /* Character code support macros */
@@ -2190,7 +2190,7 @@ FRESULT chk_mounted (	/* FR_OK(0): successful, !=0: any error occurred */

 	/* Get fsinfo if available */
 	if (fmt == FS_FAT32) {
-	 	fs->fsi_flag = 0;
+		fs->fsi_flag = 0;
 		fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo);
 		if (disk_read(fs->drv, fs->win, fs->fsi_sector, 1) == RES_OK &&
 			LD_WORD(fs->win+BS_55AA) == 0xAA55 &&
--- a/sources/unicode.c
+++ b/sources/unicode.c
--- a/if/driver_vec.c
+++ b/if/driver_vec.c
@@ -0,0 +1,196 @@
+/*
+ * driver_vec.c
+ *
+ * Expose BaS drivers to OS
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *
+ *  Created on: 24.10.2013
+ *      Author: Markus Fröschle
+ */
+
+#include <bas_types.h>
+#include "version.h"
+#include "xhdi_sd.h"
+#include "dma.h"
+#include "driver_vec.h"
+#include "driver_mem.h"
+#include "pci.h"
+
+/*
+ * driver interface struct for the SD card BaS driver
+ */
+static struct xhdi_driver_interface xhdi_call_interface =
+{
+	xhdi_call
+};
+
+/*
+ * driver interface struct for the BaS multichannel DMA driver
+ * This is exactly the same thing FireTOS provides and the MiNT FEC drivers expect.
+ * It can be directly used in TOS to register the corresponding cookie ("DMAC").
+ */
+static struct dma_driver_interface dma_interface =
+{
+	.version = 0x0101,
+	.magic = 0x444d4143, 						/* 'DMAC' */
+	.dma_set_initiator = dma_set_initiator,
+	.dma_get_initiator = dma_get_initiator,
+	.dma_free_initiator = dma_free_initiator,
+	.dma_set_channel = dma_set_channel,
+	.dma_get_channel = dma_get_channel,
+	.dma_free_channel = dma_free_channel,
+	.dma_clear_channel = dma_clear_channel,
+	.MCD_startDma = (int (*)(long, int8_t *, unsigned int, int8_t *, unsigned int,
+					unsigned int, unsigned int, unsigned int, int,
+					unsigned int, unsigned int)) MCD_startDma,
+	.MCD_dmaStatus = (int32_t (*)(int32_t)) MCD_dmaStatus,
+	.MCD_XferProgrQuery = (int32_t (*)(int32_t, MCD_XferProg *)) MCD_XferProgrQuery,
+	.MCD_killDma = (int32_t (*)(int32_t)) MCD_killDma,
+	.MCD_continDma = (int32_t (*)(int32_t)) MCD_continDma,
+	.MCD_pauseDma = (int32_t (*)(int32_t)) MCD_pauseDma,
+	.MCD_resumeDma = (int32_t (*)(int32_t)) MCD_resumeDma,
+	.MCD_csumQuery = (int32_t (*)(int32_t, uint32_t *)) MCD_csumQuery,
+	.dma_malloc = driver_mem_alloc,
+	.dma_free = driver_mem_free
+};
+
+extern struct fb_info *info_fb;
+
+/*
+ * driver interface struct for the PCI_BIOS BaS driver
+ */
+static struct pci_bios_interface pci_interface =
+{
+	.subjar = 0,
+	.version = 0x00010000,
+	.find_pci_device = wrapper_find_pci_device,
+	.find_pci_classcode = wrapper_find_pci_classcode,
+	.read_config_byte = wrapper_read_config_byte,
+	.read_config_word = wrapper_read_config_word,
+	.read_config_longword = wrapper_read_config_longword,
+	.fast_read_config_byte = wrapper_fast_read_config_byte,
+	.fast_read_config_word = wrapper_fast_read_config_word,
+	.fast_read_config_longword = wrapper_fast_read_config_longword,
+	.write_config_byte = wrapper_write_config_byte,
+	.write_config_word = wrapper_write_config_word,
+	.write_config_longword = wrapper_write_config_longword,
+	.hook_interrupt = wrapper_hook_interrupt,
+	.unhook_interrupt = wrapper_unhook_interrupt,
+	.special_cycle = wrapper_special_cycle,
+	.get_routing = wrapper_get_routing,
+	.set_interrupt = wrapper_set_interrupt,
+	.get_resource = wrapper_get_resource,
+	.get_card_used = wrapper_get_card_used,
+	.set_card_used = wrapper_set_card_used,
+	.read_mem_byte = wrapper_read_mem_byte,
+	.read_mem_word = wrapper_read_mem_word,
+	.read_mem_longword = wrapper_read_mem_longword,
+	.fast_read_mem_byte = wrapper_fast_read_mem_byte,
+	.fast_read_mem_word = wrapper_fast_read_mem_word,
+	.fast_read_mem_longword = wrapper_fast_read_mem_longword,
+	.write_mem_byte = wrapper_write_mem_byte,
+	.write_mem_word = wrapper_write_mem_word,
+	.write_mem_longword = wrapper_write_mem_longword,
+	.read_io_byte = wrapper_read_io_byte,
+	.read_io_word = wrapper_read_io_word,
+	.read_io_longword = wrapper_read_io_longword,
+	.fast_read_io_byte = wrapper_fast_read_io_byte,
+	.fast_read_io_word = wrapper_fast_read_io_word,
+	.fast_read_io_longword = wrapper_fast_read_io_longword,
+	.write_io_byte = wrapper_write_io_byte,
+	.write_io_word = wrapper_write_io_word,
+	.write_io_longword = wrapper_write_io_longword,
+	.get_machine_id = wrapper_get_machine_id,
+	.get_pagesize = wrapper_get_pagesize,
+	.virt_to_bus = wrapper_virt_to_bus,
+	.bus_to_virt = wrapper_bus_to_virt,
+	.virt_to_phys = wrapper_virt_to_phys,
+	.phys_to_virt = wrapper_phys_to_virt,
+};
+
+/*
+ * driver interface struct for the BaS framebuffer video driver
+ */
+static struct framebuffer_driver_interface framebuffer_interface =
+{
+	.framebuffer_info = &info_fb
+};
+
+static struct generic_interface interfaces[] =
+{
+	{
+		/* BaS SD-card driver interface */
+
+		.type = XHDI_DRIVER,
+		.name = "SDCARD",
+		.description = "BaS SD Card driver",
+		.version = 0,
+		.revision = 1,
+		.interface.xhdi = &xhdi_call_interface
+	},
+	{
+		.type = MCD_DRIVER,
+		.name = "MCDDMA",
+		.description = "BaS Multichannel DMA driver",
+		.version = 0,
+		.revision = 1,
+		.interface.dma = &dma_interface,
+	},
+	{
+		.type = VIDEO_DRIVER,
+		.name = "RADEON",
+		.description = "BaS RADEON framebuffer driver",
+		.version = 0,
+		.revision = 1,
+		.interface.fb = &framebuffer_interface,
+	},
+	{
+		.type = PCI_DRIVER,
+		.name = "PCI",
+		.description = "BaS PCI_BIOS driver",
+		.version = 0,
+		.revision = 1,
+		.interface.pci = &pci_interface,
+	},
+	/* insert new drivers here */
+
+	{
+		.type = END_OF_DRIVERS
+	}
+};
+
+/*
+ * this is the driver table we expose to the OS
+ */
+static struct driver_table bas_drivers =
+{
+	.bas_version = MAJOR_VERSION,
+	.bas_revision = MINOR_VERSION,
+	.remove_handler = NULL,
+	.interfaces = interfaces
+};
+
+void __attribute__((interrupt)) get_bas_drivers(void)
+{
+	__asm__ __volatile__(
+		"move.l	#%[drivers],d0\n\t"
+		:	                            /* no output */
+		:	[drivers] "o" (bas_drivers)		/* input */
+		:									/* clobber */
+	);
+}
--- a/include/MCD_dma.h
+++ b/include/MCD_dma.h
@@ -0,0 +1,359 @@
+/*
+ * File:        MCD_dma.h
+ * Purpose:     Main header file for multi-channel DMA API.
+ *
+ * Notes:
+ */
+#ifndef _MCD_API_H
+#define _MCD_API_H
+
+#include "bas_types.h"
+
+/*
+ * Turn Execution Unit tasks ON (#define) or OFF (#undef)
+ */
+#undef MCD_INCLUDE_EU
+//#define MCD_INCLUDE_EU
+
+/*
+ * Number of DMA channels
+ */
+#define NCHANNELS 16
+
+/*
+ * Total number of variants
+ */
+#ifdef MCD_INCLUDE_EU
+#define NUMOFVARIANTS   6
+#else
+#define NUMOFVARIANTS   4
+#endif
+
+/*
+ * Define sizes of the various tables
+ */
+#define TASK_TABLE_SIZE     (NCHANNELS*32)
+#define VAR_TAB_SIZE        (128)
+#define CONTEXT_SAVE_SIZE   (128)
+#define FUNCDESC_TAB_SIZE   (256)
+
+#ifdef MCD_INCLUDE_EU
+#define FUNCDESC_TAB_NUM    16
+#else
+#define FUNCDESC_TAB_NUM    1
+#endif
+
+
+#ifndef DEFINESONLY
+
+/*
+ * Portability typedefs
+ */
+
+/*
+ * These structures represent the internal registers of the
+ * multi-channel DMA
+ */
+struct dmaRegs_s {
+   uint32_t taskbar;         /* task table base address register */
+   uint32_t currPtr;
+   uint32_t endPtr;
+   uint32_t varTablePtr;
+   uint16_t dma_rsvd0;
+   uint16_t ptdControl;      /* ptd control */
+   uint32_t intPending;      /* interrupt pending register */
+   uint32_t intMask;         /* interrupt mask register */
+   uint16_t taskControl[16]; /* task control registers */
+   uint8_t  priority[32];    /* priority registers */
+   uint32_t initiatorMux;    /* initiator mux control */
+   uint32_t taskSize0;       /* task size control register 0. */
+   uint32_t taskSize1;       /* task size control register 1. */
+   uint32_t dma_rsvd1;       /* reserved */
+   uint32_t dma_rsvd2;       /* reserved */
+   uint32_t debugComp1;      /* debug comparator 1 */
+   uint32_t debugComp2;      /* debug comparator 2 */
+   uint32_t debugControl;    /* debug control */
+   uint32_t debugStatus;     /* debug status */
+   uint32_t ptdDebug;        /* priority task decode debug */
+   uint32_t dma_rsvd3[31];   /* reserved */
+};
+typedef volatile struct dmaRegs_s dmaRegs;
+
+#endif
+
+/*
+ * PTD contrl reg bits
+ */
+#define PTD_CTL_TSK_PRI         0x8000
+#define PTD_CTL_COMM_PREFETCH   0x0001
+
+/*
+ * Task Control reg bits and field masks
+ */
+#define TASK_CTL_EN             0x8000
+#define TASK_CTL_VALID          0x4000
+#define TASK_CTL_ALWAYS         0x2000
+#define TASK_CTL_INIT_MASK      0x1f00
+#define TASK_CTL_ASTRT          0x0080
+#define TASK_CTL_HIPRITSKEN     0x0040
+#define TASK_CTL_HLDINITNUM     0x0020
+#define TASK_CTL_ASTSKNUM_MASK  0x000f
+
+/*
+ * Priority reg bits and field masks
+ */
+#define PRIORITY_HLD            0x80
+#define PRIORITY_PRI_MASK       0x07
+
+/*
+ * Debug Control reg bits and field masks
+ */
+#define DBG_CTL_BLOCK_TASKS_MASK    0xffff0000
+#define DBG_CTL_AUTO_ARM            0x00008000
+#define DBG_CTL_BREAK               0x00004000
+#define DBG_CTL_COMP1_TYP_MASK      0x00003800
+#define DBG_CTL_COMP2_TYP_MASK      0x00000070
+#define DBG_CTL_EXT_BREAK           0x00000004
+#define DBG_CTL_INT_BREAK           0x00000002
+
+/*
+ * PTD Debug reg selector addresses
+ * This reg must be written with a value to show the contents of
+ * one of the desired internal register.
+ */
+#define PTD_DBG_REQ             0x00 /* shows the state of 31 initiators */
+#define PTD_DBG_TSK_VLD_INIT    0x01 /* shows which 16 tasks are valid and
+                                        have initiators asserted */
+
+
+/*
+ * General return values
+ */
+#define MCD_OK                   0
+#define MCD_ERROR               -1
+#define MCD_TABLE_UNALIGNED     -2
+#define MCD_CHANNEL_INVALID     -3
+
+/*
+ * MCD_initDma input flags
+ */
+#define MCD_RELOC_TASKS         0x00000001
+#define MCD_NO_RELOC_TASKS      0x00000000
+#define MCD_COMM_PREFETCH_EN    0x00000002  /* Commbus Prefetching - MCF547x/548x ONLY */
+
+/*
+ * MCD_dmaStatus Status Values for each channel
+ */
+#define MCD_NO_DMA  1 /* No DMA has been requested since reset */
+#define MCD_IDLE    2 /* DMA active, but the initiator is currently inactive */
+#define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */
+#define MCD_PAUSED  4 /* DMA active but it is currently paused */
+#define MCD_HALTED  5 /* the most recent DMA has been killed with MCD_killTask() */
+#define MCD_DONE    6 /* the most recent DMA has completed. */
+
+
+/*
+ * MCD_startDma parameter defines
+ */
+
+/*
+ * Constants for the funcDesc parameter
+ */
+/* Byte swapping: */
+#define MCD_NO_BYTE_SWAP    0x00045670  /* to disable byte swapping. */
+#define MCD_BYTE_REVERSE    0x00076540  /* to reverse the bytes of each uint32_t of the DMAed data. */
+#define MCD_U16_REVERSE     0x00067450  /* to reverse the 16-bit halves of
+                                           each 32-bit data value being DMAed.*/
+#define MCD_U16_BYTE_REVERSE    0x00054760 /* to reverse the byte halves of each
+                                            16-bit half of each 32-bit data value DMAed */
+#define MCD_NO_BIT_REV  0x00000000  /* do not reverse the bits of each byte DMAed. */
+#define MCD_BIT_REV     0x00088880  /* reverse the bits of each byte DMAed */
+/* CRCing: */
+#define MCD_CRC16       0xc0100000  /* to perform CRC-16 on DMAed data. */
+#define MCD_CRCCCITT    0xc0200000  /* to perform CRC-CCITT on DMAed data. */
+#define MCD_CRC32       0xc0300000  /* to perform CRC-32 on DMAed data. */
+#define MCD_CSUMINET    0xc0400000  /* to perform internet checksums on DMAed data.*/
+#define MCD_NO_CSUM     0xa0000000  /* to perform no checksumming. */
+
+#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM)
+#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
+
+/*
+ * Constants for the flags parameter
+ */
+#define MCD_TT_FLAGS_RL   0x00000001 /* Read line */
+#define MCD_TT_FLAGS_CW   0x00000002 /* Combine Writes */
+#define MCD_TT_FLAGS_SP   0x00000004 /* Speculative prefetch(XLB) MCF547x/548x ONLY  */
+#define MCD_TT_FLAGS_MASK 0x000000ff
+#define MCD_TT_FLAGS_DEF  (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
+
+#define MCD_SINGLE_DMA  0x00000100 /* Unchained DMA */
+#define MCD_CHAIN_DMA              /* TBD */
+#define MCD_EU_DMA                 /* TBD */
+#define MCD_FECTX_DMA   0x00001000 /* FEC TX ring DMA */
+#define MCD_FECRX_DMA   0x00002000 /* FEC RX ring DMA */
+
+
+/* these flags are valid for MCD_startDma and the chained buffer descriptors */
+#define MCD_BUF_READY   0x80000000 /* indicates that this buffer is now under the DMA's control */
+#define MCD_WRAP        0x20000000 /* to tell the FEC Dmas to wrap to the first BD */
+#define MCD_INTERRUPT   0x10000000 /* to generate an interrupt after completion of the DMA. */
+#define MCD_END_FRAME   0x08000000 /* tell the DMA to end the frame when transferring
+                                      last byte of data in buffer */
+#define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum
+                                      prior to performing the DMA. */
+
+/* Defines for the FEC buffer descriptor control/status word*/
+#define MCD_FEC_BUF_READY   0x8000
+#define MCD_FEC_WRAP        0x2000
+#define MCD_FEC_INTERRUPT   0x1000
+#define MCD_FEC_END_FRAME   0x0800
+
+
+/*
+ * Defines for general intuitiveness
+ */
+
+#define MCD_TRUE  1
+#define MCD_FALSE 0
+
+/*
+ * Three different cases for destination and source.
+ */
+#define MINUS1          -1
+#define ZERO            0
+#define PLUS1           1
+
+#ifndef DEFINESONLY
+
+/* Task Table Entry struct*/
+typedef struct {
+    uint32_t TDTstart;   /* task descriptor table start */
+    uint32_t TDTend;     /* task descriptor table end */
+    uint32_t varTab;     /* variable table start */
+    uint32_t FDTandFlags;    /* function descriptor table start and flags */
+    volatile uint32_t descAddrAndStatus;
+    volatile uint32_t modifiedVarTab;
+    uint32_t contextSaveSpace;   /* context save space start */
+    uint32_t literalBases;
+} TaskTableEntry;
+
+
+/* Chained buffer descriptor */
+typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
+struct MCD_bufDesc_struct {
+   uint32_t flags;         /* flags describing the DMA */
+   uint32_t csumResult;    /* checksum from checksumming performed since last checksum reset */
+   int8_t  *srcAddr;      /* the address to move data from */
+   int8_t  *destAddr;     /* the address to move data to */
+   int8_t  *lastDestAddr; /* the last address written to */
+   uint32_t dmaSize;       /* the number of bytes to transfer independent of the transfer size */
+   MCD_bufDesc *next; /* next buffer descriptor in chain */
+   uint32_t info;          /* private information about this descriptor;  DMA does not affect it */
+};
+
+/* Progress Query struct */
+typedef volatile struct MCD_XferProg_struct {
+   int8_t *lastSrcAddr;         /* the most-recent or last, post-increment source address */
+   int8_t *lastDestAddr;        /* the most-recent or last, post-increment destination address */
+   uint32_t  dmaSize;            /* the amount of data transferred for the current buffer */
+   MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */
+} MCD_XferProg;
+
+
+/* FEC buffer descriptor */
+typedef volatile struct MCD_bufDescFec_struct {
+    uint16_t statCtrl;
+    uint16_t length;
+    uint32_t dataPointer;
+} MCD_bufDescFec;
+
+
+/*************************************************************************/
+/*
+ * API function Prototypes  - see MCD_dmaApi.c for further notes
+ */
+
+/*
+ * MCD_startDma starts a particular kind of DMA .
+ */
+int MCD_startDma (
+   int channel,   /* the channel on which to run the DMA */
+   int8_t  *srcAddr,  /* the address to move data from, or buffer-descriptor address */
+   int16_t srcIncr,   /* the amount to increment the source address per transfer */
+   int8_t  *destAddr, /* the address to move data to */
+   int16_t destIncr,  /* the amount to increment the destination address per transfer */
+   uint32_t dmaSize,   /* the number of bytes to transfer independent of the transfer size */
+   uint32_t xferSize,  /* the number bytes in of each data movement (1, 2, or 4) */
+   uint32_t initiator, /* what device initiates the DMA */
+   int priority,  /* priority of the DMA */
+   uint32_t flags,     /* flags describing the DMA */
+   uint32_t funcDesc   /* a description of byte swapping, bit swapping, and CRC actions */
+);
+
+/* 
+ * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA 
+ * registers, relocating and creating the appropriate task structures, and 
+ * setting up some global settings
+ */
+int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, uint32_t flags);
+
+/* 
+ * MCD_dmaStatus() returns the status of the DMA on the requested channel.
+ */
+int MCD_dmaStatus (int channel);
+
+/* 
+ * MCD_XferProgrQuery() returns progress of DMA on requested channel
+ */
+int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep);
+
+/* 
+ * MCD_killDma() halts the DMA on the requested channel, without any
+ * intention of resuming the DMA.
+ */
+int MCD_killDma (int channel);
+
+/* 
+ * MCD_continDma() continues a DMA which as stopped due to encountering an
+ * unready buffer descriptor.
+ */
+int MCD_continDma (int channel);
+
+/* 
+ * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
+ * running on that channel). 
+ */
+int MCD_pauseDma (int channel);
+
+/* 
+ * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
+ * running on that channel).
+ */
+int MCD_resumeDma (int channel);
+
+/* 
+ * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA
+ */
+int MCD_csumQuery (int channel, uint32_t *csum);
+
+/* 
+ * MCD_getCodeSize provides the packed size required by the microcoded task
+ * and structures.
+ */
+int MCD_getCodeSize(void);
+
+/*
+ * MCD_getVersion provides a pointer to a version string and returns a
+ * version number.
+ */
+int MCD_getVersion(char **longVersion);
+
+/* macro for setting a location in the variable table */
+#define MCD_SET_VAR(taskTab,idx,value) ((uint32_t *)(taskTab)->varTab)[idx] = value
+   /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
+      so I'm avoiding surrounding it with "do {} while(0)" */
+
+#endif  /* DEFINESONLY */
+
+#endif /* _MCD_API_H */
--- a/include/MCD_progCheck.h
+++ b/include/MCD_progCheck.h
@@ -0,0 +1,5 @@
+ /* This file is autogenerated. Do not change */
+#define CURRBD 4
+#define DCOUNT 6
+#define DESTPTR 5
+#define SRCPTR 7
--- a/include/MCD_tasksInit.h
+++ b/include/MCD_tasksInit.h
@@ -0,0 +1,44 @@
+#ifndef MCD_TSK_INIT_H
+#define MCD_TSK_INIT_H 1
+
+/*
+ * Do not edit!
+ */
+
+
+/*
+ * Task 0
+ */
+void  MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel);
+
+
+/*
+ * Task 1
+ */
+void  MCD_startDmaSingleNoEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
+
+
+/*
+ * Task 2
+ */
+void  MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel);
+
+
+/*
+ * Task 3
+ */
+void  MCD_startDmaSingleEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
+
+
+/*
+ * Task 4
+ */
+void  MCD_startDmaENetRcv(int8_t *bDBase, int8_t *currBD, int8_t *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel);
+
+
+/*
+ * Task 5
+ */
+void  MCD_startDmaENetXmit(int8_t *bDBase, int8_t *currBD, int8_t *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel);
+
+#endif  /* MCD_TSK_INIT_H */
--- a/include/MCF5475.h
+++ b/include/MCF5475.h
@@ -16,13 +16,15 @@
 #ifndef __MCF5475_H__
 #define __MCF5475_H__

-#include <stdint.h>
+#include <bas_types.h>
 /***
 * MCF5475 Derivative Memory map definitions from linker command files:
 * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
 * linker symbols must be defined in the linker command file.
 */

+typedef uint32_t __attribute__((__may_alias__)) uint32_t_a;	/* a type to avoid gcc's complaints about pointer aliasing */
+
 extern uint8_t _MBAR[];
 extern uint8_t _MMUBAR[];
 extern uint8_t _RAMBAR0[];
--- a/include/MCF5475_DMA.h
+++ b/include/MCF5475_DMA.h
@@ -129,22 +129,54 @@
 #define MCF_DMA_PRIOR_HLD                    (0x80)

 /* Bit definitions and macros for MCF_DMA_IMCR */
-#define MCF_DMA_IMCR_IMC0(x)                 (((x)&0x3)<<0)
-#define MCF_DMA_IMCR_IMC1(x)                 (((x)&0x3)<<0x2)
-#define MCF_DMA_IMCR_IMC2(x)                 (((x)&0x3)<<0x4)
-#define MCF_DMA_IMCR_IMC3(x)                 (((x)&0x3)<<0x6)
-#define MCF_DMA_IMCR_IMC4(x)                 (((x)&0x3)<<0x8)
-#define MCF_DMA_IMCR_IMC5(x)                 (((x)&0x3)<<0xA)
-#define MCF_DMA_IMCR_IMC6(x)                 (((x)&0x3)<<0xC)
-#define MCF_DMA_IMCR_IMC7(x)                 (((x)&0x3)<<0xE)
-#define MCF_DMA_IMCR_IMC8(x)                 (((x)&0x3)<<0x10)
-#define MCF_DMA_IMCR_IMC9(x)                 (((x)&0x3)<<0x12)
-#define MCF_DMA_IMCR_IMC10(x)                (((x)&0x3)<<0x14)
-#define MCF_DMA_IMCR_IMC11(x)                (((x)&0x3)<<0x16)
-#define MCF_DMA_IMCR_IMC12(x)                (((x)&0x3)<<0x18)
-#define MCF_DMA_IMCR_IMC13(x)                (((x)&0x3)<<0x1A)
-#define MCF_DMA_IMCR_IMC14(x)                (((x)&0x3)<<0x1C)
-#define MCF_DMA_IMCR_IMC15(x)                (((x)&0x3)<<0x1E)
+#define MCF_DMA_IMCR_IMC16(x)	(((x)&0x3)<<0)
+#define MCF_DMA_IMCR_IMC17(x)	(((x)&0x3)<<0x2)
+#define MCF_DMA_IMCR_IMC18(x)	(((x)&0x3)<<0x4)
+#define MCF_DMA_IMCR_IMC19(x)	(((x)&0x3)<<0x6)
+#define MCF_DMA_IMCR_IMC20(x)	(((x)&0x3)<<0x8)
+#define MCF_DMA_IMCR_IMC21(x)	(((x)&0x3)<<0xA)
+#define MCF_DMA_IMCR_IMC22(x)	(((x)&0x3)<<0xC)
+#define MCF_DMA_IMCR_IMC23(x)	(((x)&0x3)<<0xE)
+#define MCF_DMA_IMCR_IMC24(x)	(((x)&0x3)<<0x10)
+#define MCF_DMA_IMCR_IMC25(x)	(((x)&0x3)<<0x12)
+#define MCF_DMA_IMCR_IMC26(x)	(((x)&0x3)<<0x14)
+#define MCF_DMA_IMCR_IMC27(x)	(((x)&0x3)<<0x16)
+#define MCF_DMA_IMCR_IMC28(x)	(((x)&0x3)<<0x18)
+#define MCF_DMA_IMCR_IMC29(x)	(((x)&0x3)<<0x1A)
+#define MCF_DMA_IMCR_IMC30(x)	(((x)&0x3)<<0x1C)
+#define MCF_DMA_IMCR_IMC31(x)	(((x)&0x3)<<0x1E)
+
+
+#define MCF_DMA_IMCR_IMC16_FEC0RX    (0x00000000)
+#define MCF_DMA_IMCR_IMC17_FEC0TX    (0x00000000)
+#define MCF_DMA_IMCR_IMC18_FEC0RX    (0x00000020)
+#define MCF_DMA_IMCR_IMC19_FEC0TX    (0x00000080)
+#define MCF_DMA_IMCR_IMC20_FEC1RX    (0x00000100)
+#define MCF_DMA_IMCR_IMC21_DREQ1     (0x00000000)
+#define MCF_DMA_IMCR_IMC21_FEC1TX    (0x00000400)
+#define MCF_DMA_IMCR_IMC22_FEC0RX    (0x00001000)
+#define MCF_DMA_IMCR_IMC23_FEC0TX    (0x00004000)
+#define MCF_DMA_IMCR_IMC24_CTM0      (0x00010000)
+#define MCF_DMA_IMCR_IMC24_FEC1RX    (0x00020000)
+#define MCF_DMA_IMCR_IMC25_CTM1      (0x00040000)
+#define MCF_DMA_IMCR_IMC25_FEC1TX    (0x00080000)
+#define MCF_DMA_IMCR_IMC26_USBEP4    (0x00000000)
+#define MCF_DMA_IMCR_IMC26_CTM2      (0x00200000)
+#define MCF_DMA_IMCR_IMC27_USBEP5    (0x00000000)
+#define MCF_DMA_IMCR_IMC27_CTM3      (0x00800000)
+#define MCF_DMA_IMCR_IMC28_USBEP6    (0x00000000)
+#define MCF_DMA_IMCR_IMC28_CTM4      (0x01000000)
+#define MCF_DMA_IMCR_IMC28_DREQ1     (0x02000000)
+#define MCF_DMA_IMCR_IMC28_PSC2RX    (0x03000000)
+#define MCF_DMA_IMCR_IMC29_DREQ1     (0x04000000)
+#define MCF_DMA_IMCR_IMC29_CTM5      (0x08000000)
+#define MCF_DMA_IMCR_IMC29_PSC2TX    (0x0C000000)
+#define MCF_DMA_IMCR_IMC30_FEC1RX    (0x00000000)
+#define MCF_DMA_IMCR_IMC30_CTM6      (0x10000000)
+#define MCF_DMA_IMCR_IMC30_PSC3RX    (0x30000000)
+#define MCF_DMA_IMCR_IMC31_FEC1TX    (0x00000000)
+#define MCF_DMA_IMCR_IMC31_CTM7      (0x80000000)
+#define MCF_DMA_IMCR_IMC31_PSC3TX    (0xC0000000)

 /* Bit definitions and macros for MCF_DMA_TSKSZ0 */
 #define MCF_DMA_TSKSZ0_DSTSZ7(x)             (((x)&0x3)<<0)
--- a/include/MCF5475_MMU.h
+++ b/include/MCF5475_MMU.h
@@ -24,12 +24,14 @@
 *********************************************************************/

 /* Register read/write macros */
-#define MCF_MMU_MMUCR                        (*(volatile uint32_t*)(&_MMUBAR[0]))
-#define MCF_MMU_MMUOR                        (*(volatile uint32_t*)(&_MMUBAR[0x4]))
-#define MCF_MMU_MMUSR                        (*(volatile uint32_t*)(&_MMUBAR[0x8]))
-#define MCF_MMU_MMUAR                        (*(volatile uint32_t*)(&_MMUBAR[0x10]))
-#define MCF_MMU_MMUTR                        (*(volatile uint32_t*)(&_MMUBAR[0x14]))
-#define MCF_MMU_MMUDR                        (*(volatile uint32_t*)(&_MMUBAR[0x18]))
+
+/* note the uint32_t_a - this is to avoid gcc warnings about pointer aliasing */
+#define MCF_MMU_MMUCR                        (*(volatile uint32_t_a*)(&_MMUBAR[0]))
+#define MCF_MMU_MMUOR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x4]))
+#define MCF_MMU_MMUSR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x8]))
+#define MCF_MMU_MMUAR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x10]))
+#define MCF_MMU_MMUTR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x14]))
+#define MCF_MMU_MMUDR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x18]))


 /* Bit definitions and macros for MCF_MMU_MMUCR */
@@ -60,7 +62,7 @@
 /* Bit definitions and macros for MCF_MMU_MMUTR */
 #define MCF_MMU_MMUTR_V                      (0x1)
 #define MCF_MMU_MMUTR_SG                     (0x2)
-#define MCF_MMU_MMUTR_ID(x)                  (((x)&0xFF)<<0x2)
+#define MCF_MMU_MMUTR_ID(x)                  (((x) & 0xFF) << 0x2)
 #define MCF_MMU_MMUTR_VA(x)                  (((x)&0x3FFFFF)<<0xA)

 /* Bit definitions and macros for MCF_MMU_MMUDR */
@@ -69,9 +71,9 @@
 #define MCF_MMU_MMUDR_W                      (0x8)
 #define MCF_MMU_MMUDR_R                      (0x10)
 #define MCF_MMU_MMUDR_SP                     (0x20)
-#define MCF_MMU_MMUDR_CM(x)                  (((x)&0x3)<<0x6)
-#define MCF_MMU_MMUDR_SZ(x)                  (((x)&0x3)<<0x8)
-#define MCF_MMU_MMUDR_PA(x)                  (((x)&0x3FFFFF)<<0xA)
+#define MCF_MMU_MMUDR_CM(x)                  (((x) & 0x3) << 0x6)
+#define MCF_MMU_MMUDR_SZ(x)                  (((x) & 0x3) << 0x8)
+#define MCF_MMU_MMUDR_PA(x)                  (((x) & 0x3FFFFF) << 0xA)


 #endif /* __MCF5475_MMU_H__ */
--- a/include/MCF5475_SIU.h
+++ b/include/MCF5475_SIU.h
@@ -48,5 +48,20 @@
 /* Bit definitions and macros for MCF_SIU_JTAGID */
 #define MCF_SIU_JTAGID_JTAGID(x)             (((x)&0xFFFFFFFF)<<0)

+/* Bit definitions and macros for MCF_SIU_JTAGID */
+#define MCF_SIU_JTAGID_REV          (0xF0000000)
+#define MCF_SIU_JTAGID_PROCESSOR    (0x0FFFFFFF)
+#define MCF_SIU_JTAGID_MCF5485      (0x0800C01D)
+#define MCF_SIU_JTAGID_MCF5484      (0x0800D01D)
+#define MCF_SIU_JTAGID_MCF5483      (0x0800E01D)
+#define MCF_SIU_JTAGID_MCF5482      (0x0800F01D)
+#define MCF_SIU_JTAGID_MCF5481      (0x0801001D)
+#define MCF_SIU_JTAGID_MCF5480      (0x0801101D)
+#define MCF_SIU_JTAGID_MCF5475      (0x0801201D)
+#define MCF_SIU_JTAGID_MCF5474      (0x0801301D)
+#define MCF_SIU_JTAGID_MCF5473      (0x0801401D)
+#define MCF_SIU_JTAGID_MCF5472      (0x0801501D)
+#define MCF_SIU_JTAGID_MCF5471      (0x0801601D)
+#define MCF_SIU_JTAGID_MCF5470      (0x0801701D)

 #endif /* __MCF5475_SIU_H__ */
--- a/include/MCF5475_SLT.h
+++ b/include/MCF5475_SLT.h
@@ -36,7 +36,7 @@

 #define MCF_SLT_STCNT(x)                     (*(volatile uint32_t*)(&_MBAR[0x900 + ((x)*0x10)]))
 #define MCF_SLT_SCR(x)                       (*(volatile uint32_t*)(&_MBAR[0x904 + ((x)*0x10)]))
-#define MCF_SLT_SCNT(x)                      (*(volatile uint32_t*)(&_MBAR[0x908 + ((x)*0x10)]))
+#define MCF_SLT_SCNT(x)                      (*(volatile int32_t*)(&_MBAR[0x908 + ((x)*0x10)]))
 #define MCF_SLT_SSR(x)                       (*(volatile uint32_t*)(&_MBAR[0x90C + ((x)*0x10)]))


--- a/include/MCF5475_XLB.h
+++ b/include/MCF5475_XLB.h
@@ -24,17 +24,17 @@
 *********************************************************************/

 /* Register read/write macros */
-#define MCF_XLB_XARB_CFG                     (*(volatile uint32_t*)(&__MBAR[0x240]))
-#define MCF_XLB_XARB_VER                     (*(volatile uint32_t*)(&__MBAR[0x244]))
-#define MCF_XLB_XARB_SR                      (*(volatile uint32_t*)(&__MBAR[0x248]))
-#define MCF_XLB_XARB_IMR                     (*(volatile uint32_t*)(&__MBAR[0x24C]))
-#define MCF_XLB_XARB_ADRCAP                  (*(volatile uint32_t*)(&__MBAR[0x250]))
-#define MCF_XLB_XARB_SIGCAP                  (*(volatile uint32_t*)(&__MBAR[0x254]))
-#define MCF_XLB_XARB_ADRTO                   (*(volatile uint32_t*)(&__MBAR[0x258]))
-#define MCF_XLB_XARB_DATTO                   (*(volatile uint32_t*)(&__MBAR[0x25C]))
-#define MCF_XLB_XARB_BUSTO                   (*(volatile uint32_t*)(&__MBAR[0x260]))
-#define MCF_XLB_XARB_PRIEN                   (*(volatile uint32_t*)(&__MBAR[0x264]))
-#define MCF_XLB_XARB_PRI                     (*(volatile uint32_t*)(&__MBAR[0x268]))
+#define MCF_XLB_XARB_CFG                     (*(volatile uint32_t*)(&_MBAR[0x240]))
+#define MCF_XLB_XARB_VER                     (*(volatile uint32_t*)(&_MBAR[0x244]))
+#define MCF_XLB_XARB_SR                      (*(volatile uint32_t*)(&_MBAR[0x248]))
+#define MCF_XLB_XARB_IMR                     (*(volatile uint32_t*)(&_MBAR[0x24C]))
+#define MCF_XLB_XARB_ADRCAP                  (*(volatile uint32_t*)(&_MBAR[0x250]))
+#define MCF_XLB_XARB_SIGCAP                  (*(volatile uint32_t*)(&_MBAR[0x254]))
+#define MCF_XLB_XARB_ADRTO                   (*(volatile uint32_t*)(&_MBAR[0x258]))
+#define MCF_XLB_XARB_DATTO                   (*(volatile uint32_t*)(&_MBAR[0x25C]))
+#define MCF_XLB_XARB_BUSTO                   (*(volatile uint32_t*)(&_MBAR[0x260]))
+#define MCF_XLB_XARB_PRIEN                   (*(volatile uint32_t*)(&_MBAR[0x264]))
+#define MCF_XLB_XARB_PRI                     (*(volatile uint32_t*)(&_MBAR[0x268]))


 /* Bit definitions and macros for MCF_XLB_XARB_CFG */
--- a/include/acia.h
+++ b/include/acia.h
@@ -0,0 +1,12 @@
+#ifndef _ACIA_H_
+#define _ACIA_H_
+
+/*
+ * ACIA registers
+ */
+#define keyctl	0xfffc00
+#define keybd	0xfffc02
+#define midictl	0xfffc04
+#define midi	0xfffc06
+
+#endif /* _ACIA_H_ */
--- a/include/am79c874.h
+++ b/include/am79c874.h
@@ -0,0 +1,85 @@
+/*
+ * File:		am79c874.h
+ * Purpose:		Driver for the AM79C874 10/100 Ethernet PHY
+ *
+ * Notes:		
+ */
+
+#ifndef _AM79C874_H_
+#define _AM79C874_H_
+
+
+extern int am79c874_init(uint8_t fec_ch, uint8_t phy_addr, uint8_t speed, uint8_t duplex);
+
+
+/* MII Register Addresses */
+#define MII_AM79C874_CR         0  /* MII Management Control Register */
+#define MII_AM79C874_SR         1  /* MII Management Status Register */
+#define MII_AM79C874_PHYIDR1    2  /* PHY Identifier 1 Register */
+#define MII_AM79C874_PHYIDR2    3  /* PHY Identifier 2 Register */
+#define MII_AM79C874_ANAR       4  /* Auto-Negociation Advertissement Register */
+#define MII_AM79C874_ANLPAR     5  /* Auto-Negociation Link Partner Register */
+#define MII_AM79C874_ANER       6  /* Auto-Negociation Expansion Register */
+#define MII_AM79C874_ANNPTR     7  /* Next Page Advertisement Register */
+#define MII_AM79C874_MFR       16  /* Miscellaneous Feature Register */
+#define MII_AM79C874_ICSR      17  /* Interrupt/Status Register      */
+#define MII_AM79C874_DR        18  /* Diagnostic Register            */
+#define MII_AM79C874_PMLR      19  /* Power and Loopback Register    */
+#define MII_AM79C874_MCR       21  /* ModeControl Register           */
+#define MII_AM79C874_DC        23  /* Disconnect Counter             */
+#define MII_AM79C874_REC       24  /* Recieve Error Counter          */
+
+/* Bit definitions and macros for MII_AM79C874_CR */
+#define MII_AM79C874_CR_RESET       (0x8000)
+#define MII_AM79C874_CR_LOOP        (0x4000)
+#define MII_AM79C874_CR_100MB       (0x2000)
+#define MII_AM79C874_CR_AUTON       (0x1000)
+#define MII_AM79C874_CR_POWD        (0x0800)
+#define MII_AM79C874_CR_ISO         (0x0400)
+#define MII_AM79C874_CR_RST_NEG     (0x0200)
+#define MII_AM79C874_CR_DPLX        (0x0100)
+#define MII_AM79C874_CR_COL_TST     (0x0080)
+#define MII_AM79C874_CR_SPEED_MASK  (0x2040)
+#define MII_AM79C874_CR_1000_MPS    (0x0040)
+#define MII_AM79C874_CR_100_MPS     (0x2000)
+#define MII_AM79C874_CR_10_MPS      (0x0000)
+
+/* Bit definitions and macros for MII_AM79C874_SR */
+#define MII_AM79C874_SR_100T4       (0x8000)
+#define MII_AM79C874_SR_100TXF      (0x4000)
+#define MII_AM79C874_SR_100TXH      (0x2000)
+#define MII_AM79C874_SR_10TF        (0x1000)
+#define MII_AM79C874_SR_10TH        (0x0800)
+#define MII_AM79C874_SR_PRE_SUP     (0x0040)
+#define MII_AM79C874_SR_AUTN_COMP   (0x0020)
+#define MII_AM79C874_SR_RF          (0x0010)
+#define MII_AM79C874_SR_AUTN_ABLE   (0x0008)
+#define MII_AM79C874_SR_LS          (0x0004)
+#define MII_AM79C874_SR_JD          (0x0002)
+#define MII_AM79C874_SR_EXT         (0x0001)
+
+/* Bit definitions and macros for MII_AM79C874_ANLPAR */
+#define MII_AM79C874_ANLPAR_NP        (0x8000)
+#define MII_AM79C874_ANLPAR_ACK       (0x4000)
+#define MII_AM79C874_ANLPAR_RF        (0x2000)
+#define MII_AM79C874_ANLPAR_T4        (0x0200)
+#define MII_AM79C874_ANLPAR_TXFD      (0x0100)
+#define MII_AM79C874_ANLPAR_TX        (0x0080)
+#define MII_AM79C874_ANLPAR_10FD      (0x0040)
+#define MII_AM79C874_ANLPAR_10        (0x0020)
+#define MII_AM79C874_ANLPAR_100       (0x0380)
+#define MII_AM79C874_ANLPAR_PSB_MASK  (0x001F)
+#define MII_AM79C874_ANLPAR_PSB_802_3 (0x0001)
+#define MII_AM79C874_ANLPAR_PSB_802_9 (0x0002)
+
+/* Bit definitions and macros for MII_AM79C874_DR */
+#define MII_AM79C874_DR_DPLX          (0x0800)
+#define MII_AM79C874_DR_DATA_RATE     (0x0400)
+#define MII_AM79C874_DR_RX_PASS       (0x0200)
+#define MII_AM79C874_DR_RX_LOCK       (0x0100)
+
+#define AUTONEGLINK		(MII_AM79C874_SR_AUTN_COMP | MII_AM79C874_SR_LS)
+
+/********************************************************************/
+
+#endif /* _AM79C874_H_ */
--- a/include/arp.h
+++ b/include/arp.h
@@ -0,0 +1,99 @@
+/*
+ * File:        arp.h
+ * Purpose:     ARP definitions.
+ *
+ * Notes:
+ */
+
+#ifndef _ARP_H
+#define _ARP_H
+
+/********************************************************************/
+
+/*
+ * This data definition is defined for Ethernet only!
+ */
+typedef struct
+{
+    uint16_t      ar_hrd;
+    uint16_t      ar_pro;
+    uint8_t       ar_hln;
+    uint8_t       ar_pln;
+    uint16_t      opcode;
+    uint8_t       ar_sha[6];  /* ethernet hw address */
+    uint8_t       ar_spa[4];  /* ip address */
+    uint8_t       ar_tha[6];  /* ethernet hw address */
+    uint8_t       ar_tpa[4];  /* ip address */
+} arp_frame_hdr;
+
+#define ARP_HDR_LEN     sizeof(arp_frame_hdr)
+
+/*
+ * ARP table entry definition.  Note that this table only designed
+ * with Ethernet and IP in mind.
+ */
+#define MAX_HWA_SIZE    (6) /* 6 is enough for Ethernet address */
+#define MAX_PA_SIZE     (4) /* 4 is enough for Protocol address */
+typedef struct
+{
+    uint16_t  protocol;
+    uint8_t   hwa_size;
+    uint8_t   hwa[MAX_HWA_SIZE];
+    uint8_t   pa_size;
+    uint8_t   pa[MAX_PA_SIZE];
+    int     longevity;
+} ARPENTRY;
+#define MAX_ARP_ENTRY   (10)
+
+typedef struct
+{
+    unsigned int    tab_size;
+    ARPENTRY        table[MAX_ARP_ENTRY];
+} ARP_INFO;
+
+#define ARP_ENTRY_EMPTY (0)
+#define ARP_ENTRY_PERM  (1)
+#define ARP_ENTRY_TEMP  (2)
+
+
+#define ETHERNET        (1)
+#define ARP_REQUEST     (1)
+#define ARP_REPLY       (2)
+
+#define ARP_TIMEOUT     (1)     /* Timeout in seconds */
+
+/* Protocol Header information */
+#define ARP_HDR_OFFSET  ETH_HDR_LEN
+
+/********************************************************************/
+
+uint8_t *
+arp_get_mypa (void);
+
+uint8_t *
+arp_get_myha (void);
+
+uint8_t *
+arp_get_broadcast (void);
+
+void
+arp_merge (ARP_INFO *, uint16_t, int, uint8_t *, int, uint8_t *, int);
+
+void
+arp_remove (ARP_INFO *, uint16_t, uint8_t *, uint8_t *);
+
+void
+arp_request (NIF *, uint8_t *);
+
+void
+arp_handler (NIF *, NBUF *);
+
+uint8_t *
+arp_resolve (NIF *, uint16_t, uint8_t *);
+
+void
+arp_init (ARP_INFO *);
+
+/********************************************************************/
+
+#endif  /* _ARP_H */
--- a/include/ati_ids.h
+++ b/include/ati_ids.h
@@ -0,0 +1,211 @@
+/*
+ * ATI PCI IDs from XFree86, kept here to make sync'ing with
+ * XFree much simpler. Currently, this list is only used by
+ * radeonfb
+ */
+
+#define PCI_CHIP_RV380_3150             0x3150
+#define PCI_CHIP_RV380_3151             0x3151
+#define PCI_CHIP_RV380_3152             0x3152
+#define PCI_CHIP_RV380_3153             0x3153
+#define PCI_CHIP_RV380_3154             0x3154
+#define PCI_CHIP_RV380_3156             0x3156
+#define PCI_CHIP_RV380_3E50             0x3E50
+#define PCI_CHIP_RV380_3E51             0x3E51
+#define PCI_CHIP_RV380_3E52             0x3E52
+#define PCI_CHIP_RV380_3E53             0x3E53
+#define PCI_CHIP_RV380_3E54             0x3E54
+#define PCI_CHIP_RV380_3E56             0x3E56
+#define PCI_CHIP_RS100_4136		0x4136
+#define PCI_CHIP_RS200_4137		0x4137
+#define PCI_CHIP_R300_AD		0x4144
+#define PCI_CHIP_R300_AE		0x4145
+#define PCI_CHIP_R300_AF		0x4146
+#define PCI_CHIP_R300_AG		0x4147
+#define PCI_CHIP_R350_AH                0x4148
+#define PCI_CHIP_R350_AI                0x4149
+#define PCI_CHIP_R350_AJ                0x414A
+#define PCI_CHIP_R350_AK                0x414B
+#define PCI_CHIP_RV350_AP               0x4150
+#define PCI_CHIP_RV350_AQ               0x4151
+#define PCI_CHIP_RV360_AR               0x4152
+#define PCI_CHIP_RV350_AS               0x4153
+#define PCI_CHIP_RV350_AT               0x4154
+#define PCI_CHIP_RV350_AV               0x4156
+#define PCI_CHIP_MACH32			0x4158
+#define PCI_CHIP_RS250_4237		0x4237
+#define PCI_CHIP_R200_BB		0x4242
+#define PCI_CHIP_R200_BC		0x4243
+#define PCI_CHIP_RS100_4336		0x4336
+#define PCI_CHIP_RS200_4337		0x4337
+#define PCI_CHIP_MACH64CT		0x4354
+#define PCI_CHIP_MACH64CX		0x4358
+#define PCI_CHIP_RS250_4437		0x4437
+#define PCI_CHIP_MACH64ET		0x4554
+#define PCI_CHIP_MACH64GB		0x4742
+#define PCI_CHIP_MACH64GD		0x4744
+#define PCI_CHIP_MACH64GI		0x4749
+#define PCI_CHIP_MACH64GL		0x474C
+#define PCI_CHIP_MACH64GM		0x474D
+#define PCI_CHIP_MACH64GN		0x474E
+#define PCI_CHIP_MACH64GO		0x474F
+#define PCI_CHIP_MACH64GP		0x4750
+#define PCI_CHIP_MACH64GQ		0x4751
+#define PCI_CHIP_MACH64GR		0x4752
+#define PCI_CHIP_MACH64GS		0x4753
+#define PCI_CHIP_MACH64GT		0x4754
+#define PCI_CHIP_MACH64GU		0x4755
+#define PCI_CHIP_MACH64GV		0x4756
+#define PCI_CHIP_MACH64GW		0x4757
+#define PCI_CHIP_MACH64GX		0x4758
+#define PCI_CHIP_MACH64GY		0x4759
+#define PCI_CHIP_MACH64GZ		0x475A
+#define PCI_CHIP_RV250_Id		0x4964
+#define PCI_CHIP_RV250_Ie		0x4965
+#define PCI_CHIP_RV250_If		0x4966
+#define PCI_CHIP_RV250_Ig		0x4967
+#define PCI_CHIP_R420_JH                0x4A48
+#define PCI_CHIP_R420_JI                0x4A49
+#define PCI_CHIP_R420_JJ                0x4A4A
+#define PCI_CHIP_R420_JK                0x4A4B
+#define PCI_CHIP_R420_JL                0x4A4C
+#define PCI_CHIP_R420_JM                0x4A4D
+#define PCI_CHIP_R420_JN                0x4A4E
+#define PCI_CHIP_R420_JP                0x4A50
+#define PCI_CHIP_MACH64LB		0x4C42
+#define PCI_CHIP_MACH64LD		0x4C44
+#define PCI_CHIP_RAGE128LE		0x4C45
+#define PCI_CHIP_RAGE128LF		0x4C46
+#define PCI_CHIP_MACH64LG		0x4C47
+#define PCI_CHIP_MACH64LI		0x4C49
+#define PCI_CHIP_MACH64LM		0x4C4D
+#define PCI_CHIP_MACH64LN		0x4C4E
+#define PCI_CHIP_MACH64LP		0x4C50
+#define PCI_CHIP_MACH64LQ		0x4C51
+#define PCI_CHIP_MACH64LR		0x4C52
+#define PCI_CHIP_MACH64LS		0x4C53
+#define PCI_CHIP_MACH64LT		0x4C54
+#define PCI_CHIP_RADEON_LW		0x4C57
+#define PCI_CHIP_RADEON_LX		0x4C58
+#define PCI_CHIP_RADEON_LY		0x4C59
+#define PCI_CHIP_RADEON_LZ		0x4C5A
+#define PCI_CHIP_RV250_Ld		0x4C64
+#define PCI_CHIP_RV250_Le		0x4C65
+#define PCI_CHIP_RV250_Lf		0x4C66
+#define PCI_CHIP_RV250_Lg		0x4C67
+#define PCI_CHIP_RV250_Ln		0x4C6E
+#define PCI_CHIP_RAGE128MF		0x4D46
+#define PCI_CHIP_RAGE128ML		0x4D4C
+#define PCI_CHIP_R300_ND		0x4E44
+#define PCI_CHIP_R300_NE		0x4E45
+#define PCI_CHIP_R300_NF		0x4E46
+#define PCI_CHIP_R300_NG		0x4E47
+#define PCI_CHIP_R350_NH                0x4E48  
+#define PCI_CHIP_R350_NI                0x4E49  
+#define PCI_CHIP_R360_NJ                0x4E4A  
+#define PCI_CHIP_R350_NK                0x4E4B  
+#define PCI_CHIP_RV350_NP               0x4E50
+#define PCI_CHIP_RV350_NQ               0x4E51
+#define PCI_CHIP_RV350_NR               0x4E52
+#define PCI_CHIP_RV350_NS               0x4E53
+#define PCI_CHIP_RV350_NT               0x4E54
+#define PCI_CHIP_RV350_NV               0x4E56
+#define PCI_CHIP_RAGE128PA		0x5041
+#define PCI_CHIP_RAGE128PB		0x5042
+#define PCI_CHIP_RAGE128PC		0x5043
+#define PCI_CHIP_RAGE128PD		0x5044
+#define PCI_CHIP_RAGE128PE		0x5045
+#define PCI_CHIP_RAGE128PF		0x5046
+#define PCI_CHIP_RAGE128PG		0x5047
+#define PCI_CHIP_RAGE128PH		0x5048
+#define PCI_CHIP_RAGE128PI		0x5049
+#define PCI_CHIP_RAGE128PJ		0x504A
+#define PCI_CHIP_RAGE128PK		0x504B
+#define PCI_CHIP_RAGE128PL		0x504C
+#define PCI_CHIP_RAGE128PM		0x504D
+#define PCI_CHIP_RAGE128PN		0x504E
+#define PCI_CHIP_RAGE128PO		0x504F
+#define PCI_CHIP_RAGE128PP		0x5050
+#define PCI_CHIP_RAGE128PQ		0x5051
+#define PCI_CHIP_RAGE128PR		0x5052
+#define PCI_CHIP_RAGE128PS		0x5053
+#define PCI_CHIP_RAGE128PT		0x5054
+#define PCI_CHIP_RAGE128PU		0x5055
+#define PCI_CHIP_RAGE128PV		0x5056
+#define PCI_CHIP_RAGE128PW		0x5057
+#define PCI_CHIP_RAGE128PX		0x5058
+#define PCI_CHIP_RADEON_QD		0x5144
+#define PCI_CHIP_RADEON_QE		0x5145
+#define PCI_CHIP_RADEON_QF		0x5146
+#define PCI_CHIP_RADEON_QG		0x5147
+#define PCI_CHIP_R200_QH		0x5148
+#define PCI_CHIP_R200_QI		0x5149
+#define PCI_CHIP_R200_QJ		0x514A
+#define PCI_CHIP_R200_QK		0x514B
+#define PCI_CHIP_R200_QL		0x514C
+#define PCI_CHIP_R200_QM		0x514D
+#define PCI_CHIP_R200_QN		0x514E
+#define PCI_CHIP_R200_QO		0x514F
+#define PCI_CHIP_RV200_QW		0x5157
+#define PCI_CHIP_RV200_QX		0x5158
+#define PCI_CHIP_RV100_QY		0x5159
+#define PCI_CHIP_RV100_QZ		0x515A
+#define PCI_CHIP_RAGE128RE		0x5245
+#define PCI_CHIP_RAGE128RF		0x5246
+#define PCI_CHIP_RAGE128RG		0x5247
+#define PCI_CHIP_RAGE128RK		0x524B
+#define PCI_CHIP_RAGE128RL		0x524C
+#define PCI_CHIP_RAGE128SE		0x5345
+#define PCI_CHIP_RAGE128SF		0x5346
+#define PCI_CHIP_RAGE128SG		0x5347
+#define PCI_CHIP_RAGE128SH		0x5348
+#define PCI_CHIP_RAGE128SK		0x534B
+#define PCI_CHIP_RAGE128SL		0x534C
+#define PCI_CHIP_RAGE128SM		0x534D
+#define PCI_CHIP_RAGE128SN		0x534E
+#define PCI_CHIP_RAGE128TF		0x5446
+#define PCI_CHIP_RAGE128TL		0x544C
+#define PCI_CHIP_RAGE128TR		0x5452
+#define PCI_CHIP_RAGE128TS		0x5453
+#define PCI_CHIP_RAGE128TT		0x5454
+#define PCI_CHIP_RAGE128TU		0x5455
+#define PCI_CHIP_RV370_5460             0x5460
+#define PCI_CHIP_RV370_5461             0x5461
+#define PCI_CHIP_RV370_5462             0x5462
+#define PCI_CHIP_RV370_5463             0x5463
+#define PCI_CHIP_RV370_5464             0x5464
+#define PCI_CHIP_RV370_5465             0x5465
+#define PCI_CHIP_RV370_5466             0x5466
+#define PCI_CHIP_RV370_5467             0x5467
+#define PCI_CHIP_R423_UH                0x5548
+#define PCI_CHIP_R423_UI                0x5549
+#define PCI_CHIP_R423_UJ                0x554A
+#define PCI_CHIP_R423_UK                0x554B
+#define PCI_CHIP_R423_UQ                0x5551
+#define PCI_CHIP_R423_UR                0x5552
+#define PCI_CHIP_R423_UT                0x5554
+#define PCI_CHIP_MACH64VT		0x5654
+#define PCI_CHIP_MACH64VU		0x5655
+#define PCI_CHIP_MACH64VV		0x5656
+#define PCI_CHIP_RS300_5834		0x5834
+#define PCI_CHIP_RS300_5835		0x5835
+#define PCI_CHIP_RS300_5836		0x5836
+#define PCI_CHIP_RS300_5837		0x5837
+#define PCI_CHIP_RV370_5B60             0x5B60
+#define PCI_CHIP_RV370_5B61             0x5B61
+#define PCI_CHIP_RV370_5B62             0x5B62
+#define PCI_CHIP_RV370_5B63             0x5B63
+#define PCI_CHIP_RV370_5B64             0x5B64
+#define PCI_CHIP_RV370_5B65             0x5B65
+#define PCI_CHIP_RV370_5B66             0x5B66
+#define PCI_CHIP_RV370_5B67             0x5B67
+#define PCI_CHIP_RV280_5960		0x5960
+#define PCI_CHIP_RV280_5961		0x5961
+#define PCI_CHIP_RV280_5962		0x5962
+#define PCI_CHIP_RV280_5964		0x5964
+#define PCI_CHIP_RV280_5C61		0x5C61
+#define PCI_CHIP_RV280_5C63		0x5C63
+#define PCI_CHIP_R423_5D57              0x5D57
+#define PCI_CHIP_RS350_7834             0x7834
+#define PCI_CHIP_RS350_7835             0x7835
+
--- a/include/bas_printf.h
+++ b/include/bas_printf.h
@@ -17,12 +17,8 @@
 *
 */

-#include <stdarg.h>
-
 #ifndef _BAS_PRINTF_H_
 #define _BAS_PRINTF_H_
-
-#include <stddef.h>
 #include <stdarg.h>
 #include <stddef.h>

@@ -30,7 +26,10 @@ extern void xvsnprintf(char *str, size_t size, const char *fmt, va_list va);
 extern void xvprintf(const char *fmt, va_list va);
 extern void xprintf(const char *fmt, ...);
 extern void xsnprintf(char *str, size_t size, const char *fmt, ...);
+extern void xputchar(int c);
+extern int sprintf(char *str, const char *format, ...);
+

 extern void display_progress(void);
-
+extern void hexdump(uint8_t buffer[], int size);
 #endif /* _BAS_PRINTF_H_ */
--- a/include/bas_string.h
+++ b/include/bas_string.h
@@ -1,8 +1,23 @@
 /*
 * bas_string.h
 *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
 *  Created on: 26.02.2013
- *      Author: mfro
+ *      Author: Markus Fröschle
 */

 #ifndef BAS_STRING_H_
@@ -10,13 +25,18 @@

 #include <stddef.h>

-extern int strncmp(const char *s1, const char *s2, int max);
+extern int strncmp(const char *s1, const char *s2, size_t max);
 extern char *strcpy(char *dst, const char *src);
-char *strncpy(char *dst, const char *src, int max);
+char *strncpy(char *dst, const char *src, size_t max);
+extern int strcmp(const char *s1, const char *s2);
 extern size_t strlen(const char *str);
 extern char *strcat(char *dst, const char *src);
-extern char *strncat(char *dst, const char *src, int max);
+extern char *strncat(char *dst, const char *src, size_t max);
 extern int atoi(const char *c);
+extern void *memcpy(void *dst, const void *src, size_t n);
+extern void *memset(void *s, int c, size_t n);
+extern int memcmp(const void *s1, const void *s2, size_t max);
+extern void bzero(void *s, size_t n);

 #define isdigit(c)	(((c) >= '0') && ((c) <= '9'))
 #define isupper(c)	((c) >= 'A' && ((c) <= 'Z'))
--- a/include/bas_types.h
+++ b/include/bas_types.h
@@ -28,10 +28,8 @@
 #ifndef BAS_TYPES_H_
 #define BAS_TYPES_H_

-#ifndef __cplusplus
+#include <stdint.h>
 #include <stdbool.h>
-#endif /* __cplusplus */
-
-
+#include <stddef.h>		/* for sizeof() etc. */

 #endif /* BAS_TYPES_H_ */
--- a/sources/illegal_instruction.S
+++ b/sources/illegal_instruction.S
@@ -1,5 +1,5 @@
 /*
- * illegal_instruction.S
+ * bas_utils.h
 *
 * This file is part of BaS_gcc.
 *
@@ -16,27 +16,14 @@
 * You should have received a copy of the GNU General Public License
 * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
 *
- * Copyright 2010 - 2012 F. Aschwanden
- * Copyright 2011 - 2012 V. Riviere
- * Copyright 2012        M. Froeschle
+ *  Created on: 26.02.2013
+ *      Author: Markus Fröschle
 */

-.global 	_illegal_instruction
-.global 	_illegal_table_make
+#ifndef _BAS_UTILS_H_
+#define _BAS_UTILS_H_

-#include 	"startcf.h"
+#define CLEAR_BIT(p,bit)        p &= ~(bit)
+#define CLEAR_BIT_NO(p,nr)      CLEAR_BIT(p, (1 << (nr)))

-.extern		_ii_shift_vec
-.extern		ewf
-
-/*******************************************************/
-.text
-ii_error:
-	nop
-	halt
-	nop
-	nop
-	
-_illegal_instruction:
-_illegal_table_make:
-	rts
+#endif /* _BAS_UTILS_H_ */
--- a/include/bcm5222.h
+++ b/include/bcm5222.h
@@ -0,0 +1,71 @@
+/*
+ * File:		bcm5222.h
+ * Purpose:		Driver for the BCM5222 10/100 Ethernet PHY
+ *
+ * Notes:		
+ */
+
+#ifndef _BCM5222_H_
+#define _BCM5222_H_
+
+extern int bcm5222_init(uint8_t, uint8_t, uint8_t, uint8_t);
+extern void bcm5222_get_reg(uint16_t*, uint16_t*);
+
+/********************************************************************/
+
+/* MII Register Addresses */
+#define BCM5222_CTRL				(0x00)
+#define BCM5222_STAT				(0x01)
+#define BCM5222_PHY_ID1				(0x02)
+#define BCM5222_PHY_ID2				(0x03)
+#define BCM5222_AN_ADV				(0x04)
+#define BCM5222_AN_LINK_PAR			(0x05)
+#define BCM5222_AN_EXP				(0x06)
+#define BCM5222_AN_NPR				(0x07)
+#define BCM5222_LINK_NPA			(0x08)
+#define BCM5222_ACSR    			(0x18)
+
+/* Bit definitions and macros for BCM5222_CTRL */
+#define BCM5222_CTRL_RESET			(0x8000)
+#define BCM5222_CTRL_LOOP			(0x4000)
+#define BCM5222_CTRL_SPEED			(0x2000)
+#define BCM5222_CTRL_ANE			(0x1000)
+#define BCM5222_CTRL_PD				(0x0800)
+#define BCM5222_CTRL_ISOLATE		(0x0400)
+#define BCM5222_CTRL_RESTART_AN		(0x0200)
+#define BCM5222_CTRL_FDX			(0x0100)
+#define BCM5222_CTRL_COL_TEST		(0x0080)
+
+
+/* Bit definitions and macros for BCM5222_STAT */
+#define BCM5222_STAT_100BT4         (0x8000)
+#define BCM5222_STAT_100BTX_FDX     (0x4000)
+#define BCM5222_STAT_100BTX         (0x2000)
+#define BCM5222_STAT_10BT_FDX       (0x1000)
+#define BCM5222_STAT_10BT           (0x0800)
+#define BCM5222_STAT_NO_PREAMBLE    (0x0040)
+#define BCM5222_STAT_AN_COMPLETE    (0x0020)
+#define BCM5222_STAT_REMOTE_FAULT   (0x0010)
+#define BCM5222_STAT_AN_ABILITY     (0x0008)
+#define BCM5222_STAT_LINK           (0x0004)
+#define BCM5222_STAT_JABBER         (0x0002)
+#define BCM5222_STAT_EXTENDED       (0x0001)
+
+/* Bit definitions and macros for BCM5222_AN_ADV */
+#define BCM5222_AN_ADV_NEXT_PAGE    (0x8001)
+#define BCM5222_AN_ADV_REM_FAULT	(0x2001)
+#define BCM5222_AN_ADV_PAUSE		(0x0401)
+#define BCM5222_AN_ADV_100BT4		(0x0201)
+#define BCM5222_AN_ADV_100BTX_FDX	(0x0101)
+#define BCM5222_AN_ADV_100BTX		(0x0081)
+#define BCM5222_AN_ADV_10BT_FDX		(0x0041)
+#define BCM5222_AN_ADV_10BT		    (0x0021)
+#define BCM5222_AN_ADV_802_3		(0x0001)
+
+/* Bit definitions and macros for BCM5222_ACSR */
+#define BCM5222_ACSR_100BTX         (0x0002)
+#define BCM5222_ACSR_FDX            (0x0001)
+										  
+/********************************************************************/
+
+#endif /* _BCM5222_H_ */
--- a/include/bootp.h
+++ b/include/bootp.h
@@ -0,0 +1,69 @@
+/*
+ * File:        bootp.h
+ * Purpose:     BOOTP definitions.
+ *
+ * Notes:
+ */
+
+#ifndef _BOOTP_H_
+#define _BOOTP_H_
+
+#define BOOTP_SERVER_PORT	67
+#define BOOTP_CLIENT_PORT	68
+
+/* protocol header information */
+#define BOOTP_HDR_OFFSET	(ETH_HDR_LEN + IP_HDR_SIZE + UDP_HDR_SIZE)
+
+/* timeout in seconds */
+#define BOOTP_TIMEOUT		2
+
+/* BOOTP connection status */
+
+struct bootp_connection
+{
+	bool open;				/* connection established flag */
+	NIF *nif;				/* pointer to network interface */
+	IP_ADDR server_ip;		/* server IP address */
+};
+
+/*
+ * This data definition is defined for Ethernet only!
+ */
+struct bootp_packet
+{
+    uint8_t type;			/* bootp operation type */
+    uint8_t htype;			/* hardware type */
+    uint8_t hlen;			/* hardware address length */
+	uint8_t hops;			/* hops */
+	uint32_t xid;			/* transaction identifier */
+	uint16_t secs;			/* seconds since trying to boot */
+	uint16_t flags;			/* only broadcast flag in use */
+	uint32_t cl_addr;		/* client ip address. Set to all 0 on request */
+	uint32_t yi_addr;		/* this field contains the new IP */
+	uint32_t gi_addr;		/* gateway address */
+	uint8_t ch_addr[16];	/* client hw address */
+	uint8_t sname[64];		/* server name */
+	uint8_t file[128];		/* name of bootfile */
+	uint8_t vend[64];		/* vendor specific (see below) */
+};
+
+#define BOOTP_PACKET_LEN	(BOOTP_HDR_OFFSET + sizeof(struct bootp_packet))
+
+/* possible values for type field */
+#define BOOTP_TYPE_BOOTREQUEST	1
+#define BOOTP_TYPE_BOOTREPLY	2
+
+/* values for hardware type - we only use ethernet */
+#define BOOTP_HTYPE_ETHERNET	1
+
+/* values for hlen - again only ethernet defined */
+#define BOOTP_HLEN_ETHERNET		6
+
+/* values for flags - only broadcast flag in use */
+#define BOOTP_FLAGS_BROADCAST	1
+
+extern void bootp_request(NIF *, uint8_t *);
+extern void bootp_handler(NIF *, NBUF *);
+//extern void bootp_init(BOOTP_INFO *);
+
+#endif  /* _BOOTP_H_ */
--- a/include/cache.h
+++ b/include/cache.h
@@ -25,8 +25,64 @@
 *
 */

-#include <stdint.h>
+#include <bas_types.h>
+
+/*
+ * CACR Cache Control Register
+ */
+#define CF_CACR_DEC         (0x80000000) /* Data Cache Enable                */
+#define CF_CACR_DW          (0x40000000) /* Data default Write-protect       */
+#define CF_CACR_DESB        (0x20000000) /* Data Enable Store Buffer         */
+#define CF_CACR_DPI         (0x10000000) /* Data Disable CPUSHL Invalidate   */
+#define CF_CACR_DHLCK       (0x08000000) /* 1/2 Data Cache Lock Mode         */
+#define CF_CACR_DDCM_00     (0x00000000) /* Cacheable writethrough imprecise */
+#define CF_CACR_DDCM_01     (0x02000000) /* Cacheable copyback               */
+#define CF_CACR_DDCM_10     (0x04000000) /* Noncacheable precise             */
+#define CF_CACR_DDCM_11     (0x06000000) /* Noncacheable imprecise           */
+#define CF_CACR_DCINVA      (0x01000000) /* Data Cache Invalidate All        */
+#define CF_CACR_DDSP        (0x00800000) /* Data default supervisor-protect  */
+#define CF_CACR_IVO         (0x00100000) /* Invalidate only                  */
+#define CF_CACR_BEC         (0x00080000) /* Branch Cache Enable              */
+#define CF_CACR_BCINVA      (0x00040000) /* Branch Cache Invalidate All      */
+#define CF_CACR_IEC         (0x00008000) /* Instruction Cache Enable         */
+#define CF_CACR_SPA         (0x00004000) /* Search by Physical Address       */
+#define CF_CACR_DNFB        (0x00002000) /* Default cache-inhibited fill buf */
+#define CF_CACR_IDPI        (0x00001000) /* Instr Disable CPUSHL Invalidate  */
+#define CF_CACR_IHLCK       (0x00000800) /* 1/2 Instruction Cache Lock Mode  */
+#define CF_CACR_IDCM        (0x00000400) /* Noncacheable Instr default mode  */
+#define CF_CACR_ICINVA      (0x00000100) /* Instr Cache Invalidate All       */
+#define CF_CACR_IDSP        (0x00000080) /* Ins default supervisor-protect   */
+#define CF_CACR_EUSP        (0x00000020) /* Switch stacks in user mode       */
+#define CF_CACR_DF          (0x00000010) /* Disable FPU                      */
+
+#define ICACHE_SIZE 0x8000              /* instruction - 32k */
+#define DCACHE_SIZE 0x8000              /* data - 32k */
+
+#define CACHE_LINE_SIZE 0x0010          /* 16 bytes */
+#define CACHE_SETS 0x0200               /* 512 sets */
+#define CACHE_WAYS 0x0004               /* 4 way */
+
+#define _DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS)
+#define _ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS)
+#define LAST_DCACHE_ADDR _DCACHE_SET_MASK
+#define LAST_ICACHE_ADDR _ICACHE_SET_MASK
+
+#define CACHE_DISABLE_MODE      (CF_CACR_DCINVA+        \
+									CF_CACR_BCINVA+        \
+									CF_CACR_ICINVA)
+
+#define CACHE_INITIAL_MODE      (CF_CACR_DEC+           \
+									CF_CACR_BEC+           \
+									CF_CACR_IEC+           \
+									CF_CACR_DESB+          \
+									CF_CACR_EUSP)

 extern void flush_and_invalidate_caches(void);
+extern uint32_t cacr_get(void);
+extern void cacr_set(uint32_t);
+extern void flush_icache_range(void *address, size_t size);
+extern void flush_dcache_range(void *address, size_t size);
+extern void flush_cache_range(void *address, size_t size);
+

 #endif /* _CACHE_H_ */
--- a/include/config.h
+++ b/include/config.h
@@ -1,115 +0,0 @@
-#ifndef _CONFIG_H_
-#define _CONFIG_H_
-
-#ifndef COLDFIRE
-#define COLDFIRE
-#endif
-
-/* DEBUG */
-#define DEBUG
-
-/* DBUG */
-#define DBUG
-
-/* PCI XBIOS */
-#undef PCI_XBIOS              /* faster by cookie */
-
-/* NETWORK */
-#ifdef COLDFIRE
-#define NETWORK
-#define ETHERNET_PORT 0       /* FEC channel */
-#undef TEST_NETWORK
-#undef DEBUG_PRINT
-#define LWIP
-#define WEB_LIGHT
-#undef FTP_SERVER
-#define ERRNO
-#define MCD_PROGQUERY
-#undef MCD_DEBUG
-
-#ifdef MCF5445X               /* target untested */
-#ifndef LWIP
-#undef NETWORK                /* to do */
-#endif /* LWIP */
-#endif /* MCF5445X */
-
-/* XBIOS */
-#define TOS_ATARI_LOGO /* defined for use TOS4.04 logo */
-
-/* BDOS */
-#define NEWCODE
-#endif /* COLDFIRE */
-
-/* fVDI */
-#define FVDI_STRUCT_2006
-
-/* NVDI */
-#define PATCH_NVDI
-
-/* VDI */
-#undef TOS_TABLES /* defined for use TOS4.04 index tables */
-    
-/* X86 emulator */
-#undef DEBUG_X86EMU
-#undef DEBUG_X86EMU_PCI
-#define __BIG_ENDIAN__
-#define NO_LONG_LONG
-
-/* Radeon */
-#define DEFAULT_MONITOR_LAYOUT ""
-#define ATI_LOGO
-#define CONFIG_FB_RADEON_I2C
-#define CONFIG_FB_MODE_HELPERS
-#undef RADEON_TILING /* normally faster but tile 16 x 16 is not compatible with accel.c read_pixel, blit/expand_area and writes on screen frame buffer */
-#ifndef COLDFIRE
-#define RADEON_RENDER
-#endif
-#undef RADEON_THEATRE /* unfinished */
-#define RADEON_DIRECT_ACCESS /* MMIO access faster but don't check endian - little -> big conversion !!! */
-
-/* Radeon VIDIX */
-#undef VIDIX_FILTER
-#undef VIDIX_ENABLE_BM /* unfinished */
-
-/* RTC M5485EVB */
-#undef USE_RTC
-
-/* LynxEM M5485EVB */
-#ifdef COLDFIRE
-#ifndef MCF5445X
-#ifndef MCF547X
-#undef CONFIG_VIDEO_SMI_LYNXEM
-#endif
-#endif
-#endif /* COLDFIRE */
-
-/* XBIOS Setscreen */
-#define MAX_WIDTH_EMU_MONO 1024
-#define MAX_HEIGHT_EMU_MONO 768
-
-/* AC97 */
-#define SOUND_AC97
-
-/* USB */
-#undef USB_DEVICE /* Coldfire USB device */
-#define USB_BUFFER_SIZE 0x10000
-#define CONFIG_USB_OHCI /* PCI USB 1.1 */
-#define CONFIG_USB_EHCI /* PCI USB 2.0 */
-#undef CONFIG_EHCI_DCACHE
-#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 15
-#if defined(COLDFIRE) && !defined(MCF547X)
-#undef CONFIG_USB_INTERRUPT_POLLING
-#else
-#define CONFIG_USB_INTERRUPT_POLLING
-#endif /* COLDFIRE */
-#undef CONFIG_LEGACY_USB_INIT_SEQ
-#define CONFIG_USB_KEYBOARD
-#define CONFIG_USB_MOUSE
-#define CONFIG_USB_STORAGE
-#ifdef COLDFIRE
-#define CONFIG_USB_MEM_NO_CACHE
-#endif /* COLDFIRE */
-
-#endif /* _CONFIG_H_ */
--- a/include/diskio.h
+++ b/include/diskio.h
@@ -12,7 +12,7 @@ extern "C" {
 #define _USE_WRITE	1	/* 1: Enable disk_write function */
 #define _USE_IOCTL	1	/* 1: Enable disk_ioctl fucntion */

-#include <stdint.h>
+#include <bas_types.h>


 /* Status of Disk Functions */
@@ -33,6 +33,7 @@ typedef enum {


 DSTATUS disk_initialize (uint8_t);
+DSTATUS disk_reset(uint8_t);
 DSTATUS disk_status (uint8_t);
 DRESULT disk_read (uint8_t, uint8_t*, uint32_t, uint8_t);
 #if	_READONLY == 0
--- a/include/dma.h
+++ b/include/dma.h
@@ -0,0 +1,47 @@
+/*
+ * spidma.h *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 26.02.2013
+ *      Author: Markus Fröschle
+ */
+
+#ifndef _DMA_H_
+#define _DMA_H_
+
+#include "MCF5475.h"
+#include "MCD_dma.h"
+#include "bas_string.h"
+
+#define DMA_INTC_LVL        5
+#define DMA_INTC_PRI        3
+
+
+void *dma_memcpy(void *dst, void *src, size_t n);
+extern int dma_init(void);
+extern int dma_get_channel(int requestor);
+extern int dma_set_channel(int, void (*)(void));
+extern void dma_free_channel(int requestor);
+extern void dma_clear_channel(int channel);
+extern uint32_t dma_get_initiator(int requestor);
+extern int dma_set_initiator(int initiator);
+extern void dma_free_initiator(int initiator);
+extern void dma_irq_enable(uint8_t lvl, uint8_t pri);
+extern void dma_irq_disable(void);
+extern int dma_interrupt_handler(void *arg1, void *arg2);
+
+
+#endif /* _DMA_H_ */
--- a/include/driver_mem.h
+++ b/include/driver_mem.h
@@ -0,0 +1,15 @@
+#ifndef _DRIVER_MEM_H_
+#define _DRIVER_MEM_H_
+
+#include "bas_types.h"
+
+/*
+ * the driver_mem module provides a block of _uncached_ memory for USB and other drivers as
+ * well as some memory handling functions for it
+ */
+extern int driver_mem_init(void);
+extern void *driver_mem_alloc(uint32_t amount);
+extern int32_t driver_mem_free(void *addr);
+extern void driver_mem_release(void);
+
+#endif /* _DRIVER_MEM_H_ */
--- a/include/driver_vec.h
+++ b/include/driver_vec.h
@@ -0,0 +1,290 @@
+/*
+ * driver_vec.h
+ *
+ * Interface for exposure of BaS drivers to the OS
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 24.10.2013
+ *      Author: Markus Fröschle
+ */
+
+#ifndef _DRIVER_VEC_H_
+#define _DRIVER_VEC_H_
+
+#include "xhdi_sd.h"
+#include "MCD_dma.h"
+#include "pci.h"
+
+enum driver_type
+{
+	BLOCKDEV_DRIVER,
+	CHARDEV_DRIVER,
+	XHDI_DRIVER,
+	MCD_DRIVER,
+	VIDEO_DRIVER,
+	PCI_DRIVER,
+	END_OF_DRIVERS,		/* marks end of driver list */
+};
+
+struct generic_driver_interface
+{
+	uint32_t (*init)(void);
+	uint32_t (*read)(void *buf, size_t count);
+	uint32_t (*write)(const void *buf, size_t count);
+	uint32_t (*ioctl)(uint32_t request, ...);
+};
+
+struct dma_driver_interface
+{
+	int32_t version;
+	int32_t magic;
+	int (*dma_set_initiator)(int initiator);
+	uint32_t (*dma_get_initiator)(int requestor);
+	void (*dma_free_initiator)(int requestor);
+	int (*dma_set_channel)(int requestor, void (*handler)(void));
+	int (*dma_get_channel)(int requestor);
+	void (*dma_free_channel)(int requestor);
+	void (*dma_clear_channel)(int channel);
+	int (*MCD_startDma)(long channel,
+						int8_t *srcAddr, unsigned int srcIncr, int8_t *destAddr, unsigned int destIncr,
+						unsigned int dmaSize, unsigned int xferSize, unsigned int initiator, int priority,
+						unsigned int flags, unsigned int funcDesc);
+	int32_t (*MCD_dmaStatus)(int32_t channel);
+	int32_t (*MCD_XferProgrQuery)(int32_t channel, MCD_XferProg *progRep);
+	int32_t (*MCD_killDma)(int32_t channel);
+	int32_t (*MCD_continDma)(int32_t channel);
+	int32_t (*MCD_pauseDma)(int32_t channel);
+	int32_t (*MCD_resumeDma)(int32_t channel);
+	int32_t (*MCD_csumQuery)(int32_t channel, uint32_t *csum);
+	void *(*dma_malloc)(uint32_t amount);
+	int32_t (*dma_free)(void *addr);
+};
+
+struct xhdi_driver_interface
+{
+	uint32_t (*xhdivec)();
+};
+
+/* Interpretation of offset for color fields: All offsets are from the right,
+ * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you
+ * can use the offset as right argument to <<). A pixel afterwards is a bit
+ * stream and is written to video memory as that unmodified. This implies
+ * big-endian byte order if bits_per_pixel is greater than 8.
+ */
+struct fb_bitfield
+{
+	unsigned long offset;           /* beginning of bitfield    */
+	unsigned long length;           /* length of bitfield       */
+	unsigned long msb_right;        /* != 0 : Most significant bit is */
+									/* right */
+};
+
+/*
+ * the following structures define the interface to the BaS-builtin-framebuffer video driver
+ */
+struct fb_var_screeninfo
+{
+	unsigned long xres;             /* visible resolution       */
+	unsigned long yres;
+	unsigned long xres_virtual;     /* virtual resolution       */
+	unsigned long yres_virtual;
+	unsigned long xoffset;          /* offset from virtual to visible */
+	unsigned long yoffset;          /* resolution           */
+
+	unsigned long bits_per_pixel;   /* guess what           */
+	unsigned long grayscale;        /* != 0 Graylevels instead of colors */
+
+	struct fb_bitfield red;         /* bitfield in fb mem if true color, */
+	struct fb_bitfield green;       /* else only length is significant */
+	struct fb_bitfield blue;
+	struct fb_bitfield transp;      /* transparency         */
+
+	unsigned long nonstd;           /* != 0 Non standard pixel format */
+
+	unsigned long activate;         /* see FB_ACTIVATE_*        */
+
+	unsigned long height;           /* height of picture in mm    */
+	unsigned long width;            /* width of picture in mm     */
+
+	unsigned long accel_flags;      /* (OBSOLETE) see fb_info.flags */
+
+	/* Timing: All values in pixclocks, except pixclock (of course) */
+	unsigned long pixclock;         /* pixel clock in ps (pico seconds) */
+	unsigned long left_margin;      /* time from sync to picture    */
+	unsigned long right_margin;     /* time from picture to sync    */
+	unsigned long upper_margin;     /* time from sync to picture    */
+	unsigned long lower_margin;
+	unsigned long hsync_len;        /* length of horizontal sync    */
+	unsigned long vsync_len;        /* length of vertical sync  */
+	unsigned long sync;             /* see FB_SYNC_*        */
+	unsigned long vmode;            /* see FB_VMODE_*       */
+	unsigned long rotate;           /* angle we rotate counter clockwise */
+	unsigned long refresh;
+	unsigned long reserved[4];      /* Reserved for future compatibility */
+};
+
+struct fb_fix_screeninfo
+{
+	char id[16];                    /* identification string eg "TT Builtin" */
+	unsigned long smem_start;       /* Start of frame buffer mem */
+									/* (physical address) */
+	unsigned long smem_len;         /* Length of frame buffer mem */
+	unsigned long type;             /* see FB_TYPE_*        */
+	unsigned long type_aux;         /* Interleave for interleaved Planes */
+	unsigned long visual;           /* see FB_VISUAL_*      */
+	unsigned short xpanstep;        /* zero if no hardware panning  */
+	unsigned short ypanstep;        /* zero if no hardware panning  */
+	unsigned short ywrapstep;       /* zero if no hardware ywrap    */
+	unsigned long line_length;      /* length of a line in bytes    */
+	unsigned long mmio_start;       /* Start of Memory Mapped I/O   */
+									/* (physical address) */
+	unsigned long mmio_len;         /* Length of Memory Mapped I/O  */
+	unsigned long accel;            /* Indicate to driver which */
+									/*  specific chip/card we have  */
+	unsigned short reserved[3];     /* Reserved for future compatibility */
+};
+
+struct fb_chroma
+{
+	unsigned long redx; /* in fraction of 1024 */
+	unsigned long greenx;
+	unsigned long bluex;
+	unsigned long whitex;
+	unsigned long redy;
+	unsigned long greeny;
+	unsigned long bluey;
+	unsigned long whitey;
+};
+
+struct fb_monspecs
+{
+	struct fb_chroma chroma;
+	struct fb_videomode *modedb;    /* mode database */
+	unsigned char  manufacturer[4]; /* Manufacturer */
+	unsigned char  monitor[14];     /* Monitor String */
+	unsigned char  serial_no[14];   /* Serial Number */
+	unsigned char  ascii[14];       /* ? */
+	unsigned long modedb_len;       /* mode database length */
+	unsigned long model;            /* Monitor Model */
+	unsigned long serial;           /* Serial Number - Integer */
+	unsigned long year;             /* Year manufactured */
+	unsigned long week;             /* Week Manufactured */
+	unsigned long hfmin;            /* hfreq lower limit (Hz) */
+	unsigned long hfmax;            /* hfreq upper limit (Hz) */
+	unsigned long dclkmin;          /* pixelclock lower limit (Hz) */
+	unsigned long dclkmax;          /* pixelclock upper limit (Hz) */
+	unsigned short input;           /* display type - see FB_DISP_* */
+	unsigned short dpms;            /* DPMS support - see FB_DPMS_ */
+	unsigned short signal;          /* Signal Type - see FB_SIGNAL_* */
+	unsigned short vfmin;           /* vfreq lower limit (Hz) */
+	unsigned short vfmax;           /* vfreq upper limit (Hz) */
+	unsigned short gamma;           /* Gamma - in fractions of 100 */
+	unsigned short gtf  : 1;        /* supports GTF */
+	unsigned short misc;            /* Misc flags - see FB_MISC_* */
+	unsigned char  version;         /* EDID version... */
+	unsigned char  revision;        /* ...and revision */
+	unsigned char  max_x;           /* Maximum horizontal size (cm) */
+	unsigned char  max_y;           /* Maximum vertical size (cm) */
+};
+
+struct framebuffer_driver_interface
+{
+	struct fb_info **framebuffer_info;	/* pointer to an fb_info struct (defined in include/fb.h) */
+};
+
+struct pci_bios_interface {
+	uint32_t subjar;
+	uint32_t version;
+	/* Although we declare this functions as standard gcc functions (cdecl),
+	 * they expect paramenters inside registers (fastcall) unsupported by gcc m68k.
+	 * Caller will take care of parameters passing convention.
+	 */
+	int32_t (*find_pci_device)	(uint32_t id, uint16_t index);
+	int32_t (*find_pci_classcode)	(uint32_t class, uint16_t index);
+	int32_t (*read_config_byte)	(int32_t handle, uint16_t reg, uint8_t *address);
+	int32_t (*read_config_word)	(int32_t handle, uint16_t reg, uint16_t *address);
+	int32_t (*read_config_longword)	(int32_t handle, uint16_t reg, uint32_t *address);
+	uint8_t (*fast_read_config_byte)	(int32_t handle, uint16_t reg);
+	uint16_t (*fast_read_config_word)	(int32_t handle, uint16_t reg);
+	uint32_t (*fast_read_config_longword)	(int32_t handle, uint16_t reg);
+	int32_t (*write_config_byte)	(int32_t handle, uint16_t reg, uint16_t val);
+	int32_t (*write_config_word)	(int32_t handle, uint16_t reg, uint16_t val);
+	int32_t (*write_config_longword)	(int32_t handle, uint16_t reg, uint32_t val);
+	int32_t (*hook_interrupt)	(int32_t handle, uint32_t *routine, uint32_t *parameter);
+	int32_t (*unhook_interrupt)	(int32_t handle);
+	int32_t (*special_cycle)	(uint16_t bus, uint32_t data);
+	int32_t (*get_routing)	(int32_t handle);
+	int32_t (*set_interrupt)	(int32_t handle);
+	int32_t (*get_resource)	(int32_t handle);
+	int32_t (*get_card_used)	(int32_t handle, uint32_t *address);
+	int32_t (*set_card_used)	(int32_t handle, uint32_t *callback);
+	int32_t (*read_mem_byte)	(int32_t handle, uint32_t offset, uint8_t *address);
+	int32_t (*read_mem_word)	(int32_t handle, uint32_t offset, uint16_t *address);
+	int32_t (*read_mem_longword)	(int32_t handle, uint32_t offset, uint32_t *address);
+	uint8_t (*fast_read_mem_byte)	(int32_t handle, uint32_t offset);
+	uint16_t (*fast_read_mem_word)	(int32_t handle, uint32_t offset);
+	uint32_t (*fast_read_mem_longword)	(int32_t handle, uint32_t offset);
+	int32_t (*write_mem_byte)	(int32_t handle, uint32_t offset, uint16_t val);
+	int32_t (*write_mem_word)	(int32_t handle, uint32_t offset, uint16_t val);
+	int32_t (*write_mem_longword)	(int32_t handle, uint32_t offset, uint32_t val);
+	int32_t (*read_io_byte)	(int32_t handle, uint32_t offset, uint8_t *address);
+	int32_t (*read_io_word)	(int32_t handle, uint32_t offset, uint16_t *address);
+	int32_t (*read_io_longword)	(int32_t handle, uint32_t offset, uint32_t *address);
+	uint8_t (*fast_read_io_byte)	(int32_t handle, uint32_t offset);
+	uint16_t (*fast_read_io_word)	(int32_t handle, uint32_t offset);
+	uint32_t (*fast_read_io_longword)	(int32_t handle, uint32_t offset);
+	int32_t (*write_io_byte)	(int32_t handle, uint32_t offset, uint16_t val);
+	int32_t (*write_io_word)	(int32_t handle, uint32_t offset, uint16_t val);
+	int32_t (*write_io_longword)	(int32_t handle, uint32_t offset, uint32_t val);
+	int32_t (*get_machine_id)	(void);
+	int32_t (*get_pagesize)	(void);
+	int32_t (*virt_to_bus)	(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+	int32_t (*bus_to_virt)	(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+	int32_t (*virt_to_phys)	(uint32_t address, PCI_CONV_ADR *pointer);
+	int32_t (*phys_to_virt)	(uint32_t address, PCI_CONV_ADR *pointer);
+//	int32_t reserved[2];
+};
+
+union interface
+{
+	struct generic_driver_interface *gdi;
+	struct xhdi_driver_interface *xhdi;
+	struct dma_driver_interface *dma;
+	struct framebuffer_driver_interface *fb;
+	struct pci_bios_interface *pci;
+};
+
+struct generic_interface
+{
+	enum driver_type type;
+	char name[16];
+	char description[64];
+	int version;
+	int revision;
+	union interface interface;
+};
+
+struct driver_table
+{
+	uint32_t bas_version;
+	uint32_t bas_revision;
+	uint32_t (*remove_handler)();			/* calling this will disable the BaS' hook into trap #0 */
+	struct generic_interface *interfaces;
+};
+
+
+#endif /* _DRIVER_VEC_H_ */
--- a/include/edid.h
+++ b/include/edid.h
@@ -0,0 +1,138 @@
+/* 
+ * edid.h - EDID/DDC Header
+ *
+ * Based on:
+ *   1. XFree86 4.3.0, edid.h
+ *      Copyright 1998 by Egbert Eich <Egbert.Eich@Physik.TU-Darmstadt.DE>
+ * 
+ *   2. John Fremlin <vii@users.sourceforge.net> and 
+ *      Ani Joshi <ajoshi@unixbox.com>
+ *
+ * DDC is a Trademark of VESA (Video Electronics Standard Association).
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+*/
+
+#ifndef __EDID_H__
+#define __EDID_H__
+
+#define EDID_LENGTH				0x80
+#define EDID_HEADER				0x00
+#define EDID_HEADER_END				0x07
+
+#define ID_MANUFACTURER_NAME			0x08
+#define ID_MANUFACTURER_NAME_END		0x09
+#define ID_MODEL				0x0a
+
+#define ID_SERIAL_NUMBER			0x0c
+
+#define MANUFACTURE_WEEK			0x10
+#define MANUFACTURE_YEAR			0x11
+
+#define EDID_STRUCT_VERSION			0x12
+#define EDID_STRUCT_REVISION			0x13
+
+#define EDID_STRUCT_DISPLAY                     0x14
+
+#define DPMS_FLAGS				0x18
+#define ESTABLISHED_TIMING_1			0x23
+#define ESTABLISHED_TIMING_2			0x24
+#define MANUFACTURERS_TIMINGS			0x25
+
+/* standard timings supported */
+#define STD_TIMING                              8
+#define STD_TIMING_DESCRIPTION_SIZE             2
+#define STD_TIMING_DESCRIPTIONS_START           0x26
+
+#define DETAILED_TIMING_DESCRIPTIONS_START	0x36
+#define DETAILED_TIMING_DESCRIPTION_SIZE	18
+#define NO_DETAILED_TIMING_DESCRIPTIONS		4
+
+#define DETAILED_TIMING_DESCRIPTION_1		0x36
+#define DETAILED_TIMING_DESCRIPTION_2		0x48
+#define DETAILED_TIMING_DESCRIPTION_3		0x5a
+#define DETAILED_TIMING_DESCRIPTION_4		0x6c
+
+#define DESCRIPTOR_DATA				5
+
+#define UPPER_NIBBLE( x ) \
+        (((128|64|32|16) & (x)) >> 4)
+
+#define LOWER_NIBBLE( x ) \
+        ((1|2|4|8) & (x))
+
+#define COMBINE_HI_8LO( hi, lo ) \
+        ( (((unsigned)hi) << 8) | (unsigned)lo )
+
+#define COMBINE_HI_4LO( hi, lo ) \
+        ( (((unsigned)hi) << 4) | (unsigned)lo )
+
+#define PIXEL_CLOCK_LO     (unsigned)block[ 0 ]
+#define PIXEL_CLOCK_HI     (unsigned)block[ 1 ]
+#define PIXEL_CLOCK	   (COMBINE_HI_8LO( PIXEL_CLOCK_HI,PIXEL_CLOCK_LO )*10000)
+#define H_ACTIVE_LO        (unsigned)block[ 2 ]
+#define H_BLANKING_LO      (unsigned)block[ 3 ]
+#define H_ACTIVE_HI        UPPER_NIBBLE( (unsigned)block[ 4 ] )
+#define H_ACTIVE           COMBINE_HI_8LO( H_ACTIVE_HI, H_ACTIVE_LO )
+#define H_BLANKING_HI      LOWER_NIBBLE( (unsigned)block[ 4 ] )
+#define H_BLANKING         COMBINE_HI_8LO( H_BLANKING_HI, H_BLANKING_LO )
+
+#define V_ACTIVE_LO        (unsigned)block[ 5 ]
+#define V_BLANKING_LO      (unsigned)block[ 6 ]
+#define V_ACTIVE_HI        UPPER_NIBBLE( (unsigned)block[ 7 ] )
+#define V_ACTIVE           COMBINE_HI_8LO( V_ACTIVE_HI, V_ACTIVE_LO )
+#define V_BLANKING_HI      LOWER_NIBBLE( (unsigned)block[ 7 ] )
+#define V_BLANKING         COMBINE_HI_8LO( V_BLANKING_HI, V_BLANKING_LO )
+
+#define H_SYNC_OFFSET_LO   (unsigned)block[ 8 ]
+#define H_SYNC_WIDTH_LO    (unsigned)block[ 9 ]
+
+#define V_SYNC_OFFSET_LO   UPPER_NIBBLE( (unsigned)block[ 10 ] )
+#define V_SYNC_WIDTH_LO    LOWER_NIBBLE( (unsigned)block[ 10 ] )
+
+#define V_SYNC_WIDTH_HI    ((unsigned)block[ 11 ] & (1|2))
+#define V_SYNC_OFFSET_HI   (((unsigned)block[ 11 ] & (4|8)) >> 2)
+
+#define H_SYNC_WIDTH_HI    (((unsigned)block[ 11 ] & (16|32)) >> 4)
+#define H_SYNC_OFFSET_HI   (((unsigned)block[ 11 ] & (64|128)) >> 6)
+
+#define V_SYNC_WIDTH       COMBINE_HI_4LO( V_SYNC_WIDTH_HI, V_SYNC_WIDTH_LO )
+#define V_SYNC_OFFSET      COMBINE_HI_4LO( V_SYNC_OFFSET_HI, V_SYNC_OFFSET_LO )
+
+#define H_SYNC_WIDTH       COMBINE_HI_4LO( H_SYNC_WIDTH_HI, H_SYNC_WIDTH_LO )
+#define H_SYNC_OFFSET      COMBINE_HI_4LO( H_SYNC_OFFSET_HI, H_SYNC_OFFSET_LO )
+
+#define H_SIZE_LO          (unsigned)block[ 12 ]
+#define V_SIZE_LO          (unsigned)block[ 13 ]
+
+#define H_SIZE_HI          UPPER_NIBBLE( (unsigned)block[ 14 ] )
+#define V_SIZE_HI          LOWER_NIBBLE( (unsigned)block[ 14 ] )
+
+#define H_SIZE             COMBINE_HI_8LO( H_SIZE_HI, H_SIZE_LO )
+#define V_SIZE             COMBINE_HI_8LO( V_SIZE_HI, V_SIZE_LO )
+
+#define H_BORDER           (unsigned)block[ 15 ]
+#define V_BORDER           (unsigned)block[ 16 ]
+
+#define FLAGS              (unsigned)block[ 17 ]
+
+#define INTERLACED         (FLAGS&128)
+#define SYNC_TYPE          (FLAGS&3<<3)	/* bits 4,3 */
+#define SYNC_SEPARATE      (3<<3)
+#define HSYNC_POSITIVE     (FLAGS & 4)
+#define VSYNC_POSITIVE     (FLAGS & 2)
+
+#define V_MIN_RATE              block[ 5 ]
+#define V_MAX_RATE              block[ 6 ]
+#define H_MIN_RATE              block[ 7 ]
+#define H_MAX_RATE              block[ 8 ]
+#define MAX_PIXEL_CLOCK         (((int)block[ 9 ]) * 10)
+#define GTF_SUPPORT		block[10]
+
+#define DPMS_ACTIVE_OFF		(1 << 5)
+#define DPMS_SUSPEND		(1 << 6)
+#define DPMS_STANDBY		(1 << 7)
+
+#endif /* __EDID_H__ */
--- a/include/ehci.h
+++ b/include/ehci.h
@@ -22,6 +22,7 @@
 #ifndef USB_EHCI_H
 #define USB_EHCI_H

+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	5
 #if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
 #endif
@@ -50,7 +51,7 @@ struct ehci_hccr {
 #define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
 #define HC_VERSION(p)		(((p) >> 16) & 0xffff)
 	uint32_t cr_hcsparams;
-#define HCS_PPC(p)		((p) & (1 << 4))
+#define HCS_PPC(p)			((p) & (1 << 4))
 #define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
 #define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
 	uint32_t cr_hccparams;
@@ -69,20 +70,20 @@ struct ehci_hcor {
 #define CMD_RUN		(1 << 0)		/* start/stop HC */
 	uint32_t or_usbsts;
 #define	STD_ASS		(1 << 15)
-#define STS_PSSTAT (1 << 14)
-#define STS_RECL  ( 1 << 13)
+#define STS_PSSTAT	(1 << 14)
+#define STS_RECL	(1 << 13)
 #define STS_HALT	(1 << 12)
-#define STS_IAA (1 << 5)
-#define STS_HSE (1 << 4)
-#define STS_FLR (1 << 3)
-#define STS_PCD (1 << 2)
+#define STS_IAA		(1 << 5)
+#define STS_HSE		(1 << 4)
+#define STS_FLR		(1 << 3)
+#define STS_PCD		(1 << 2)
 #define STS_USBERRINT (1 << 1)
-#define STS_USBINT (1 << 0)
+#define STS_USBINT	(1 << 0)
 	uint32_t or_usbintr;
-#define INTR_IAAE (1 << 5)
-#define INTR_HSEE (1 << 4)
-#define INTR_FLRE (1 << 3)
-#define INTR_PCDE (1 << 2)
+#define INTR_IAAE	(1 << 5)
+#define INTR_HSEE	(1 << 4)
+#define INTR_FLRE	(1 << 3)
+#define INTR_PCDE	(1 << 2)
 #define INTR_USBERRINTE (1 << 1)
 #define INTR_USBINTE (1 << 0)
 	uint32_t or_frindex;
@@ -96,14 +97,15 @@ struct ehci_hcor {
 	uint32_t or_systune;
 } __attribute__ ((packed));

-#define USBMODE		0x68		/* USB Device mode */
+#define USBMODE		0x68			/* USB Device mode */
 #define USBMODE_SDIS	(1 << 3)	/* Stream disable */
-#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
+#define USBMODE_BE	(1 << 2)		/* BE/LE endiannes select */
 #define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
 #define USBMODE_CM_IDLE	(0 << 0)	/* idle state */

 /* Interface descriptor */
-struct usb_linux_interface_descriptor {
+struct usb_linux_interface_descriptor
+{
 	unsigned char	bLength;
 	unsigned char	bDescriptorType;
 	unsigned char	bInterfaceNumber;
@@ -116,7 +118,8 @@ struct usb_linux_interface_descriptor {
 } __attribute__ ((packed));

 /* Configuration descriptor information.. */
-struct usb_linux_config_descriptor {
+struct usb_linux_config_descriptor
+{
 	unsigned char	bLength;
 	unsigned char	bDescriptorType;
 	unsigned short	wTotalLength;
@@ -128,36 +131,36 @@ struct usb_linux_config_descriptor {
 } __attribute__ ((packed));

 #if defined CONFIG_EHCI_DESC_BIG_ENDIAN
-#define	ehci_readl(x)		(*((volatile u32 *)(x)))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
+#define	ehci_readl(x)		(*((volatile uint32_t *)(x)))
+#define ehci_writel(a, b)	(*((volatile uint32_t *)(a)) = ((volatile uint32_t) b))
 #else
-#define ehci_readl(x)		cpu_to_le32((*((volatile u32 *)(x))))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = cpu_to_le32(((volatile u32)b)))
+#define ehci_readl(x)		swpl((*((volatile uint32_t *)(x))))
+#define ehci_writel(a, b)	(*((volatile uint32_t *)(a)) = swpl(((volatile uint32_t) b)))
 #endif

 #if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
 #define hc32_to_cpu(x)		be32_to_cpu((x))
 #define cpu_to_hc32(x)		cpu_to_be32((x))
 #else
-#define hc32_to_cpu(x)		le32_to_cpu((x))
-#define cpu_to_hc32(x)		cpu_to_le32((x))
+#define hc32_to_cpu(x)		swpl((x))
+#define cpu_to_hc32(x)		swpl((x))
 #endif

 #define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
 #define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
 #define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
-#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
-#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
-#define EHCI_PS_LS		(3 << 10)	/* RO line status */
-#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
-#define EHCI_PS_SUSP	(1 << 7)	/* RW suspend */
-#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
-#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
-#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
-#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
-#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
-#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
-#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
+#define EHCI_PS_PO			(1 << 13)	/* RW port owner */
+#define EHCI_PS_PP			(1 << 12)	/* RW,RO port power */
+#define EHCI_PS_LS			(3 << 10)	/* RO line status */
+#define EHCI_PS_PR			(1 << 8)	/* RW port reset */
+#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
+#define EHCI_PS_FPR			(1 << 6)	/* RW force port resume */
+#define EHCI_PS_OCC			(1 << 5)	/* RWC over current change */
+#define EHCI_PS_OCA			(1 << 4)	/* RO over current active */
+#define EHCI_PS_PEC			(1 << 3)	/* RWC port enable change */
+#define EHCI_PS_PE			(1 << 2)	/* RW port enable */
+#define EHCI_PS_CSC			(1 << 1)	/* RWC connect status change */
+#define EHCI_PS_CS			(1 << 0)	/* RO connect status */
 #define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)

 #define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
@@ -173,7 +176,8 @@ struct usb_linux_config_descriptor {
 */

 /* Queue Element Transfer Descriptor (qTD). */
-struct qTD {
+struct qTD
+{
 	uint32_t qt_next;
 #define	QT_NEXT_TERMINATE	1
 	uint32_t qt_altnext;
@@ -182,7 +186,8 @@ struct qTD {
 };

 /* Queue Head (QH). */
-struct QH {
+struct QH
+{
 	uint32_t qh_link;
 #define	QH_LINK_TERMINATE	1
 #define	QH_LINK_TYPE_ITD	0
--- a/include/eth.h
+++ b/include/eth.h
@@ -0,0 +1,57 @@
+/*
+ * File:        eth.h
+ * Purpose:     Definitions for Ethernet Frames.
+ *
+ * Modifications:
+ */
+
+#ifndef _ETH_H
+#define _ETH_H
+
+#include "bas_types.h"
+
+/*******************************************************************/
+
+/* Ethernet standard lengths in bytes*/
+#define ETH_ADDR_LEN    (6)
+#define ETH_TYPE_LEN    (2)
+#define ETH_CRC_LEN     (4)
+#define ETH_MAX_DATA    (1500)
+#define ETH_MIN_DATA    (46)
+#define ETH_HDR_LEN     (ETH_ADDR_LEN * 2 + ETH_TYPE_LEN)
+
+/* Defined Ethernet Frame Types */
+#define ETH_FRM_IP      (0x0800)
+#define ETH_FRM_ARP     (0x0806)
+#define ETH_FRM_RARP    (0x8035)
+#define ETH_FRM_TEST    (0xA5A5)
+
+/* Maximum and Minimum Ethernet Frame Sizes */
+#define ETH_MAX_FRM     (ETH_HDR_LEN + ETH_MAX_DATA + ETH_CRC_LEN)
+#define ETH_MIN_FRM     (ETH_HDR_LEN + ETH_MIN_DATA + ETH_CRC_LEN)
+#define ETH_MTU         (ETH_HDR_LEN + ETH_MAX_DATA)
+
+/* Ethernet Addresses */
+typedef uint8_t ETH_ADDR[ETH_ADDR_LEN];
+
+/* 16-bit Ethernet Frame Type, ie. Protocol */
+typedef uint16_t ETH_FRM_TYPE;
+
+/* Ethernet Frame Header definition */
+typedef struct
+{
+	ETH_ADDR     dest;
+	ETH_ADDR     src;
+	ETH_FRM_TYPE type;
+} ETH_HDR;
+
+/* Ethernet Frame definition */
+typedef struct
+{
+	ETH_HDR head;
+	uint8_t*  data;
+} ETH_FRAME;
+
+/*******************************************************************/
+
+#endif  /* _ETH_H */
--- a/include/exceptions.h
+++ b/include/exceptions.h
@@ -0,0 +1,28 @@
+#ifndef _EXCEPTIONS_H_
+#define _EXCEPTIONS_H_
+
+#include <bas_types.h>
+
+static inline uint32_t set_ipl(uint32_t ipl)
+{
+	uint32_t ret;
+
+	__asm__ __volatile__(
+		"		move.w	sr,%[ret]\r\n"			/* retrieve status register */
+		"		andi.l	#0x07,%[ipl]\n\t"		/* mask out ipl bits on new value */
+		"		lsl.l	#8,%[ipl]\n\t"			/* shift them to position */
+		"		move.l	%[ret],d0\n\t"			/* retrieve original value */
+		"		andi.l	#0x0000f8ff,d0\n\t"		/* clear ipl part */
+		"		or.l	%[ipl],d0\n\t"			/* or in new value */
+		"		move.w	d0,sr\n\t"				/* put it in place */
+		"		andi.l	#0x0700,%[ret]\r\n"		/* mask out ipl bits */
+		"		lsr.l	#8,%[ret]\r\n"			/* shift them to position */
+		: [ret] "=&d" (ret)		/* output */
+		: [ipl] "d" (ipl)		/* input */
+		: "cc", "d0"	/* clobber */
+	);
+
+	return ret;
+}
+
+#endif /* _EXCEPTIONS_H_ */
--- a/include/fb.h
+++ b/include/fb.h
@@ -0,0 +1,551 @@
+#ifndef _FB_H
+#define _FB_H
+
+/* Definitions of frame buffers						*/
+
+#define FB_MAJOR		29
+#define FB_MAX			32	/* sufficient for now */
+
+/* ioctls
+   0x46 is 'F'								*/
+#define FBIOGET_VSCREENINFO	0x4600
+#define FBIOPUT_VSCREENINFO	0x4601
+#define FBIOGET_FSCREENINFO	0x4602
+#define FBIOPAN_DISPLAY     0x4606
+#define FBIOBLANK		        0x4611		/* arg: 0 or vesa level + 1 */
+#define FBIO_ALLOC          0x4613
+#define FBIO_FREE           0x4614
+
+/* picture format */
+#define PICT_FORMAT(bpp,type,a,r,g,b)	(((bpp) << 24) | ((type) << 16) | ((a) << 12) | ((r) << 8) | ((g) << 4) | ((b)))
+/* gray/color formats use a visual index instead of argb */
+#define PICT_VISFORMAT(bpp,type,vi)	(((bpp) << 24) | ((type) << 16) | ((vi)))
+#define PICT_FORMAT_BPP(f)	(((f) >> 24)       )
+#define PICT_FORMAT_TYPE(f)	(((f) >> 16) & 0xff)
+#define PICT_FORMAT_A(f)	(((f) >> 12) & 0x0f)
+#define PICT_FORMAT_R(f)	(((f) >>  8) & 0x0f)
+#define PICT_FORMAT_G(f)	(((f) >>  4) & 0x0f)
+#define PICT_FORMAT_B(f)	(((f)      ) & 0x0f)
+#define PICT_FORMAT_RGB(f)	(((f)      ) & 0xfff)
+#define PICT_FORMAT_VIS(f)	(((f)      ) & 0xffff)
+#define PICT_TYPE_OTHER	0
+#define PICT_TYPE_A	1
+#define PICT_TYPE_ARGB	2
+#define PICT_TYPE_ABGR	3
+#define PICT_TYPE_COLOR	4
+#define PICT_TYPE_GRAY	5
+#define PICT_FORMAT_COLOR(f)	(PICT_FORMAT_TYPE(f) & 2)
+/* 32bpp formats */
+#define PICT_a8r8g8b8	PICT_FORMAT(32,PICT_TYPE_ARGB,8,8,8,8)
+#define PICT_x8r8g8b8	PICT_FORMAT(32,PICT_TYPE_ARGB,0,8,8,8)
+#define PICT_a8b8g8r8	PICT_FORMAT(32,PICT_TYPE_ABGR,8,8,8,8)
+#define PICT_x8b8g8r8	PICT_FORMAT(32,PICT_TYPE_ABGR,0,8,8,8)
+/* 24bpp formats */
+#define PICT_r8g8b8	PICT_FORMAT(24,PICT_TYPE_ARGB,0,8,8,8)
+#define PICT_b8g8r8	PICT_FORMAT(24,PICT_TYPE_ABGR,0,8,8,8)
+/* 16bpp formats */
+#define PICT_r5g6b5	PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,6,5)
+#define PICT_b5g6r5	PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,6,5)
+#define PICT_a1r5g5b5	PICT_FORMAT(16,PICT_TYPE_ARGB,1,5,5,5)
+#define PICT_x1r5g5b5	PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,5,5)
+#define PICT_a1b5g5r5	PICT_FORMAT(16,PICT_TYPE_ABGR,1,5,5,5)
+#define PICT_x1b5g5r5	PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,5,5)
+#define PICT_a4r4g4b4	PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4)
+#define PICT_x4r4g4b4	PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4)
+#define PICT_a4b4g4r4	PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4)
+#define PICT_x4b4g4r4	PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4)
+/* 8bpp formats */
+#define PICT_a8 PICT_FORMAT(8,PICT_TYPE_A,8,0,0,0)
+#define PICT_r3g3b2	PICT_FORMAT(8,PICT_TYPE_ARGB,0,3,3,2)
+#define PICT_b2g3r3	PICT_FORMAT(8,PICT_TYPE_ABGR,0,3,3,2)
+#define PICT_a2r2g2b2 PICT_FORMAT(8,PICT_TYPE_ARGB,2,2,2,2)
+#define PICT_a2b2g2r2 PICT_FORMAT(8,PICT_TYPE_ABGR,2,2,2,2)
+#define PICT_c8 PICT_FORMAT(8,PICT_TYPE_COLOR,0,0,0,0)
+#define PICT_g8 PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0)
+
+/* fVDI */
+#define MODE_EMUL_MONO_FLAG 1
+#define MODE_VESA_FLAG 2 /* for modedb.c */
+struct mode_option {
+	short used; /* Whether the mode option was used or not. */
+	short width;
+	short height;
+	short bpp;
+	short freq;
+	short flags;
+};
+
+extern struct mode_option resolution; /* fVDI */
+
+#define FB_TYPE_PACKED_PIXELS		0	/* Packed Pixels	*/
+#define FB_TYPE_PLANES			1	/* Non interleaved planes */
+#define FB_TYPE_INTERLEAVED_PLANES	2	/* Interleaved planes	*/
+#define FB_TYPE_TEXT			3	/* Text/attributes	*/
+#define FB_TYPE_VGA_PLANES		4	/* EGA/VGA planes	*/
+
+#define FB_AUX_TEXT_MDA		0	/* Monochrome text */
+#define FB_AUX_TEXT_CGA		1	/* CGA/EGA/VGA Color text */
+#define FB_AUX_TEXT_S3_MMIO	2	/* S3 MMIO fasttext */
+#define FB_AUX_TEXT_MGA_STEP16	3	/* MGA Millenium I: text, attr, 14 reserved bytes */
+#define FB_AUX_TEXT_MGA_STEP8	4	/* other MGAs:      text, attr,  6 reserved bytes */
+
+#define FB_AUX_VGA_PLANES_VGA4		0	/* 16 color planes (EGA/VGA) */
+#define FB_AUX_VGA_PLANES_CFB4		1	/* CFB4 in planes (VGA) */
+#define FB_AUX_VGA_PLANES_CFB8		2	/* CFB8 in planes (VGA) */
+
+#define FB_VISUAL_MONO01		0	/* Monochr. 1=Black 0=White */
+#define FB_VISUAL_MONO10		1	/* Monochr. 1=White 0=Black */
+#define FB_VISUAL_TRUECOLOR		2	/* True color	*/
+#define FB_VISUAL_PSEUDOCOLOR		3	/* Pseudo color (like atari) */
+#define FB_VISUAL_DIRECTCOLOR		4	/* Direct color */
+#define FB_VISUAL_STATIC_PSEUDOCOLOR	5	/* Pseudo color readonly */
+
+#define FB_ACCEL_NONE		0	/* no hardware accelerator	*/
+#define FB_ACCEL_ATARIBLITT	1	/* Atari Blitter		*/
+#define FB_ACCEL_AMIGABLITT	2	/* Amiga Blitter                */
+#define FB_ACCEL_S3_TRIO64	3	/* Cybervision64 (S3 Trio64)    */
+#define FB_ACCEL_NCR_77C32BLT	4	/* RetinaZ3 (NCR 77C32BLT)      */
+#define FB_ACCEL_S3_VIRGE	5	/* Cybervision64/3D (S3 ViRGE)	*/
+#define FB_ACCEL_ATI_MACH64GX	6	/* ATI Mach 64GX family		*/
+#define FB_ACCEL_DEC_TGA	7	/* DEC 21030 TGA		*/
+#define FB_ACCEL_ATI_MACH64CT	8	/* ATI Mach 64CT family		*/
+#define FB_ACCEL_ATI_MACH64VT	9	/* ATI Mach 64CT family VT class */
+#define FB_ACCEL_ATI_MACH64GT	10	/* ATI Mach 64CT family GT class */
+#define FB_ACCEL_SUN_CREATOR	11	/* Sun Creator/Creator3D	*/
+#define FB_ACCEL_SUN_CGSIX	12	/* Sun cg6			*/
+#define FB_ACCEL_SUN_LEO	13	/* Sun leo/zx			*/
+#define FB_ACCEL_IMS_TWINTURBO	14	/* IMS Twin Turbo		*/
+#define FB_ACCEL_3DLABS_PERMEDIA2 15	/* 3Dlabs Permedia 2		*/
+#define FB_ACCEL_MATROX_MGA2064W 16	/* Matrox MGA2064W (Millenium)	*/
+#define FB_ACCEL_MATROX_MGA1064SG 17	/* Matrox MGA1064SG (Mystique)	*/
+#define FB_ACCEL_MATROX_MGA2164W 18	/* Matrox MGA2164W (Millenium II) */
+#define FB_ACCEL_MATROX_MGA2164W_AGP 19	/* Matrox MGA2164W (Millenium II) */
+#define FB_ACCEL_MATROX_MGAG100	20	/* Matrox G100 (Productiva G100) */
+#define FB_ACCEL_MATROX_MGAG200	21	/* Matrox G200 (Myst, Mill, ...) */
+#define FB_ACCEL_SUN_CG14	22	/* Sun cgfourteen		 */
+#define FB_ACCEL_SUN_BWTWO	23	/* Sun bwtwo			*/
+#define FB_ACCEL_SUN_CGTHREE	24	/* Sun cgthree			*/
+#define FB_ACCEL_SUN_TCX	25	/* Sun tcx			*/
+#define FB_ACCEL_MATROX_MGAG400	26	/* Matrox G400			*/
+#define FB_ACCEL_NV3		27	/* nVidia RIVA 128              */
+#define FB_ACCEL_NV4		28	/* nVidia RIVA TNT		*/
+#define FB_ACCEL_NV5		29	/* nVidia RIVA TNT2		*/
+#define FB_ACCEL_CT_6555x	30	/* C&T 6555x			*/
+#define FB_ACCEL_3DFX_BANSHEE	31	/* 3Dfx Banshee			*/
+#define FB_ACCEL_ATI_RAGE128	32	/* ATI Rage128 family		*/
+#define FB_ACCEL_IGS_CYBER2000	33	/* CyberPro 2000		*/
+#define FB_ACCEL_IGS_CYBER2010	34	/* CyberPro 2010		*/
+#define FB_ACCEL_IGS_CYBER5000	35	/* CyberPro 5000		*/
+#define FB_ACCEL_SIS_GLAMOUR    36	/* SiS 300/630/540              */
+#define FB_ACCEL_3DLABS_PERMEDIA3 37	/* 3Dlabs Permedia 3		*/
+#define FB_ACCEL_ATI_RADEON	38	/* ATI Radeon family		*/
+#define FB_ACCEL_I810           39      /* Intel 810/815                */
+#define FB_ACCEL_SIS_GLAMOUR_2  40	/* SiS 315, 650, 740		*/
+#define FB_ACCEL_SIS_XABRE      41	/* SiS 330 ("Xabre")		*/
+#define FB_ACCEL_I830           42      /* Intel 830M/845G/85x/865G     */
+#define FB_ACCEL_NV_10          43      /* nVidia Arch 10               */
+#define FB_ACCEL_NV_20          44      /* nVidia Arch 20               */
+#define FB_ACCEL_NV_30          45      /* nVidia Arch 30               */
+#define FB_ACCEL_NV_40          46      /* nVidia Arch 40               */
+#define FB_ACCEL_NEOMAGIC_NM2070 90	/* NeoMagic NM2070              */
+#define FB_ACCEL_NEOMAGIC_NM2090 91	/* NeoMagic NM2090              */
+#define FB_ACCEL_NEOMAGIC_NM2093 92	/* NeoMagic NM2093              */
+#define FB_ACCEL_NEOMAGIC_NM2097 93	/* NeoMagic NM2097              */
+#define FB_ACCEL_NEOMAGIC_NM2160 94	/* NeoMagic NM2160              */
+#define FB_ACCEL_NEOMAGIC_NM2200 95	/* NeoMagic NM2200              */
+#define FB_ACCEL_NEOMAGIC_NM2230 96	/* NeoMagic NM2230              */
+#define FB_ACCEL_NEOMAGIC_NM2360 97	/* NeoMagic NM2360              */
+#define FB_ACCEL_NEOMAGIC_NM2380 98	/* NeoMagic NM2380              */
+
+#define FB_ACCEL_SAVAGE4        0x80	/* S3 Savage4                   */
+#define FB_ACCEL_SAVAGE3D       0x81	/* S3 Savage3D                  */
+#define FB_ACCEL_SAVAGE3D_MV    0x82	/* S3 Savage3D-MV               */
+#define FB_ACCEL_SAVAGE2000     0x83	/* S3 Savage2000                */
+#define FB_ACCEL_SAVAGE_MX_MV   0x84	/* S3 Savage/MX-MV              */
+#define FB_ACCEL_SAVAGE_MX      0x85	/* S3 Savage/MX                 */
+#define FB_ACCEL_SAVAGE_IX_MV   0x86	/* S3 Savage/IX-MV              */
+#define FB_ACCEL_SAVAGE_IX      0x87	/* S3 Savage/IX                 */
+#define FB_ACCEL_PROSAVAGE_PM   0x88	/* S3 ProSavage PM133           */
+#define FB_ACCEL_PROSAVAGE_KM   0x89	/* S3 ProSavage KM133           */
+#define FB_ACCEL_S3TWISTER_P    0x8a	/* S3 Twister                   */
+#define FB_ACCEL_S3TWISTER_K    0x8b	/* S3 TwisterK                  */
+#define FB_ACCEL_SUPERSAVAGE    0x8c    /* S3 Supersavage               */
+#define FB_ACCEL_PROSAVAGE_DDR  0x8d	/* S3 ProSavage DDR             */
+#define FB_ACCEL_PROSAVAGE_DDRK 0x8e	/* S3 ProSavage DDR-K           */
+
+struct fb_fix_screeninfo {
+	char id[16];					/* identification string eg "TT Builtin" */
+	unsigned long smem_start;		/* Start of frame buffer mem */
+									/* (physical address) */
+	unsigned long smem_len;			/* Length of frame buffer mem */
+	unsigned long type;				/* see FB_TYPE_*		*/
+	unsigned long type_aux;			/* Interleave for interleaved Planes */
+	unsigned long visual;			/* see FB_VISUAL_*		*/ 
+	unsigned short xpanstep;		/* zero if no hardware panning  */
+	unsigned short ypanstep;		/* zero if no hardware panning  */
+	unsigned short ywrapstep;		/* zero if no hardware ywrap    */
+	unsigned long line_length;		/* length of a line in bytes    */
+	unsigned long mmio_start;		/* Start of Memory Mapped I/O   */
+									/* (physical address) */
+	unsigned long mmio_len;			/* Length of Memory Mapped I/O  */
+	unsigned long accel;			/* Indicate to driver which	*/
+									/*  specific chip/card we have	*/
+	unsigned short reserved[3];		/* Reserved for future compatibility */
+};
+
+/* Interpretation of offset for color fields: All offsets are from the right,
+ * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you
+ * can use the offset as right argument to <<). A pixel afterwards is a bit
+ * stream and is written to video memory as that unmodified. This implies
+ * big-endian byte order if bits_per_pixel is greater than 8.
+ */
+struct fb_bitfield {
+	unsigned long offset;			/* beginning of bitfield	*/
+	unsigned long length;			/* length of bitfield		*/
+	unsigned long msb_right;		/* != 0 : Most significant bit is */ 
+					/* right */ 
+};
+
+#define FB_NONSTD_HAM		1	/* Hold-And-Modify (HAM)        */
+
+#define FB_ACTIVATE_NOW		0	/* set values immediately (or vbl)*/
+#define FB_ACTIVATE_NXTOPEN	1	/* activate on next open	*/
+#define FB_ACTIVATE_TEST	2	/* don't set, round up impossible */
+#define FB_ACTIVATE_MASK       15
+					/* values			*/
+#define FB_ACTIVATE_VBL	       16	/* activate values on next vbl  */
+#define FB_CHANGE_CMAP_VBL     32	/* change colormap on vbl	*/
+#define FB_ACTIVATE_ALL	       64	/* change all VCs on this fb	*/
+#define FB_ACTIVATE_FORCE     128	/* force apply even when no change*/
+#define FB_ACTIVATE_INV_MODE  256 /* invalidate videomode */
+
+#define FB_ACCELF_TEXT		1	/* (OBSOLETE) see fb_info.flags and vc_mode */
+
+#define FB_SYNC_HOR_HIGH_ACT	1	/* horizontal sync high active	*/
+#define FB_SYNC_VERT_HIGH_ACT	2	/* vertical sync high active	*/
+#define FB_SYNC_EXT		4	/* external sync		*/
+#define FB_SYNC_COMP_HIGH_ACT	8	/* composite sync high active   */
+#define FB_SYNC_BROADCAST	16	/* broadcast video timings      */
+					/* vtotal = 144d/288n/576i => PAL  */
+					/* vtotal = 121d/242n/484i => NTSC */
+#define FB_SYNC_ON_GREEN	32	/* sync on green */
+
+#define FB_VMODE_NONINTERLACED  0	/* non interlaced */
+#define FB_VMODE_INTERLACED	1	/* interlaced	*/
+#define FB_VMODE_DOUBLE		2	/* double scan */
+#define FB_VMODE_MASK		255
+
+#define FB_VMODE_YWRAP		256	/* ywrap instead of panning     */
+#define FB_VMODE_SMOOTH_XPAN	512	/* smooth xpan possible (internally used) */
+#define FB_VMODE_CONUPDATE	512	/* don't update x/yoffset	*/
+
+#define PICOS2KHZ(a) (1000000000UL/(a))
+#define KHZ2PICOS(a) (1000000000UL/(a))
+
+struct fb_var_screeninfo {
+	unsigned long xres;				/* visible resolution		*/
+	unsigned long yres;
+	unsigned long xres_virtual;		/* virtual resolution		*/
+	unsigned long yres_virtual;
+	unsigned long xoffset;			/* offset from virtual to visible */
+	unsigned long yoffset;			/* resolution			*/
+
+	unsigned long bits_per_pixel;	/* guess what			*/
+	unsigned long grayscale;		/* != 0 Graylevels instead of colors */
+
+	struct fb_bitfield red;			/* bitfield in fb mem if true color, */
+	struct fb_bitfield green;		/* else only length is significant */
+	struct fb_bitfield blue;
+	struct fb_bitfield transp;		/* transparency			*/	
+
+	unsigned long nonstd;			/* != 0 Non standard pixel format */
+
+	unsigned long activate;			/* see FB_ACTIVATE_*		*/
+
+	unsigned long height;			/* height of picture in mm    */
+	unsigned long width;			/* width of picture in mm     */
+
+	unsigned long accel_flags;		/* (OBSOLETE) see fb_info.flags */
+
+	/* Timing: All values in pixclocks, except pixclock (of course) */
+	unsigned long pixclock;			/* pixel clock in ps (pico seconds) */
+	unsigned long left_margin;		/* time from sync to picture	*/
+	unsigned long right_margin;		/* time from picture to sync	*/
+	unsigned long upper_margin;		/* time from sync to picture	*/
+	unsigned long lower_margin;
+	unsigned long hsync_len;		/* length of horizontal sync	*/
+	unsigned long vsync_len;		/* length of vertical sync	*/
+	unsigned long sync;				/* see FB_SYNC_*		*/
+	unsigned long vmode;			/* see FB_VMODE_*		*/
+	unsigned long rotate;			/* angle we rotate counter clockwise */
+	unsigned long refresh;
+	unsigned long reserved[4];		/* Reserved for future compatibility */
+};
+
+/* VESA Blanking Levels */
+#define VESA_NO_BLANKING        0
+#define VESA_VSYNC_SUSPEND      1
+#define VESA_HSYNC_SUSPEND      2
+#define VESA_POWERDOWN          3
+
+enum {
+	/* screen: unblanked, hsync: on,  vsync: on */
+	FB_BLANK_UNBLANK       = VESA_NO_BLANKING,
+	/* screen: blanked,   hsync: on,  vsync: on */
+	FB_BLANK_NORMAL        = VESA_NO_BLANKING + 1,
+	/* screen: blanked,   hsync: on,  vsync: off */
+	FB_BLANK_VSYNC_SUSPEND = VESA_VSYNC_SUSPEND + 1,
+	/* screen: blanked,   hsync: off, vsync: on */
+	FB_BLANK_HSYNC_SUSPEND = VESA_HSYNC_SUSPEND + 1,
+	/* screen: blanked,   hsync: off, vsync: off */
+	FB_BLANK_POWERDOWN     = VESA_POWERDOWN + 1
+};
+
+#define FB_VBLANK_VBLANKING	0x001	/* currently in a vertical blank */
+#define FB_VBLANK_HBLANKING	0x002	/* currently in a horizontal blank */
+#define FB_VBLANK_HAVE_VBLANK	0x004	/* vertical blanks can be detected */
+#define FB_VBLANK_HAVE_HBLANK	0x008	/* horizontal blanks can be detected */
+#define FB_VBLANK_HAVE_COUNT	0x010	/* global retrace counter is available */
+#define FB_VBLANK_HAVE_VCOUNT	0x020	/* the vcount field is valid */
+#define FB_VBLANK_HAVE_HCOUNT	0x040	/* the hcount field is valid */
+#define FB_VBLANK_VSYNCING	0x080	/* currently in a vsync */
+#define FB_VBLANK_HAVE_VSYNC	0x100	/* verical syncs can be detected */
+
+struct fb_vblank {
+	unsigned long flags;			/* FB_VBLANK flags */
+	unsigned long count;			/* counter of retraces since boot */
+	unsigned long vcount;			/* current scanline position */
+	unsigned long hcount;			/* current scandot position */
+	unsigned long reserved[4];		/* reserved for future compatibility */
+};
+
+struct vm_area_struct;
+struct fb_info;
+struct device;
+struct file;
+
+/* Definitions below are used in the parsed monitor specs */
+#define FB_DPMS_ACTIVE_OFF	1
+#define FB_DPMS_SUSPEND		2
+#define FB_DPMS_STANDBY		4
+
+#define FB_DISP_DDI		1
+#define FB_DISP_ANA_700_300	2
+#define FB_DISP_ANA_714_286	4
+#define FB_DISP_ANA_1000_400	8
+#define FB_DISP_ANA_700_000	16
+
+#define FB_DISP_MONO		32
+#define FB_DISP_RGB		64
+#define FB_DISP_MULTI		128
+#define FB_DISP_UNKNOWN		256
+
+#define FB_SIGNAL_NONE		0
+#define FB_SIGNAL_BLANK_BLANK	1
+#define FB_SIGNAL_SEPARATE	2
+#define FB_SIGNAL_COMPOSITE	4
+#define FB_SIGNAL_SYNC_ON_GREEN	8
+#define FB_SIGNAL_SERRATION_ON	16
+
+#define FB_MISC_PRIM_COLOR	1
+#define FB_MISC_1ST_DETAIL	2	/* First Detailed Timing is preferred */
+struct fb_chroma {
+	unsigned long redx;	/* in fraction of 1024 */
+	unsigned long greenx;
+	unsigned long bluex;
+	unsigned long whitex;
+	unsigned long redy;
+	unsigned long greeny;
+	unsigned long bluey;
+	unsigned long whitey;
+};
+
+struct fb_monspecs {
+	struct fb_chroma chroma;
+	struct fb_videomode *modedb;	/* mode database */
+	unsigned char  manufacturer[4];	/* Manufacturer */
+	unsigned char  monitor[14];		/* Monitor String */
+	unsigned char  serial_no[14];	/* Serial Number */
+	unsigned char  ascii[14];		/* ? */
+	unsigned long modedb_len;		/* mode database length */
+	unsigned long model;			/* Monitor Model */
+	unsigned long serial;			/* Serial Number - Integer */
+	unsigned long year;				/* Year manufactured */
+	unsigned long week;				/* Week Manufactured */
+	unsigned long hfmin;			/* hfreq lower limit (Hz) */
+	unsigned long hfmax;			/* hfreq upper limit (Hz) */
+	unsigned long dclkmin;			/* pixelclock lower limit (Hz) */
+	unsigned long dclkmax;			/* pixelclock upper limit (Hz) */
+	unsigned short input;			/* display type - see FB_DISP_* */
+	unsigned short dpms;			/* DPMS support - see FB_DPMS_ */
+	unsigned short signal;			/* Signal Type - see FB_SIGNAL_* */
+	unsigned short vfmin;			/* vfreq lower limit (Hz) */
+	unsigned short vfmax;			/* vfreq upper limit (Hz) */
+	unsigned short gamma;			/* Gamma - in fractions of 100 */
+	unsigned short gtf	: 1;		/* supports GTF */
+	unsigned short misc;			/* Misc flags - see FB_MISC_* */
+	unsigned char  version;			/* EDID version... */
+	unsigned char  revision;		/* ...and revision */
+	unsigned char  max_x;			/* Maximum horizontal size (cm) */
+	unsigned char  max_y;			/* Maximum vertical size (cm) */
+};
+
+struct fb_ops {
+	/* checks var and eventually tweaks if to soomething supported,
+	 * DO NOT MODIFY PAR  */
+	int (*fb_check_var)(struct fb_var_screeninfo *var, struct fb_info *info);
+	/* set the video mode according to info->var */
+	int (*fb_set_par)(struct fb_info *info);
+	/* set color register */
+	int (*fb_setcolreg)(unsigned regno, unsigned red, unsigned green,
+	                    unsigned blue, unsigned transp, struct fb_info *info);
+	/* pan display */
+	int (*fb_pan_display)(struct fb_var_screeninfo *var, struct fb_info *info);
+	/* blank display */
+	int (*fb_blank)(int blank, struct fb_info *info);
+	/* wait for blit idle */
+	int (*fb_sync)(struct fb_info *info);
+	/* perform fb specific ioctl */
+	int (*fb_ioctl)(unsigned int cmd, unsigned long arg, struct fb_info *info);
+	/* Buildthe modedb for head 1 (head 2 will come later), check panel infos
+	 * from either BIOS or EDID, and pick up the default mode */
+	void (*fb_check_modes)(struct fb_info *info, struct mode_option *resolution);
+  /* Accel functions */
+#define DEGREES_0	0
+#define DEGREES_90	1
+#define DEGREES_180	2
+#define DEGREES_270	3
+#define OMIT_LAST	1
+	void (*SetupForSolidFill)(struct fb_info *info, int color, int rop, unsigned int planemask);
+	void (*SubsequentSolidFillRect)(struct fb_info *info, int x, int y, int w, int h);
+	void (*SetupForSolidLine)(struct fb_info *info, int color, int rop, unsigned int planemask);
+	void (*SubsequentSolidHorVertLine)(struct fb_info *info, int x, int y, int len, int dir);   
+	void (*SubsequentSolidTwoPointLine)(struct fb_info *info, int xa, int ya, int xb, int yb, int flags);  
+	void (*SetupForDashedLine)(struct fb_info *info, int fg, int bg, int rop, unsigned int planemask, int length, unsigned char *pattern);
+	void (*SubsequentDashedTwoPointLine)(struct fb_info *info, int xa, int ya, int xb, int yb, int flags, int phase);  
+	void (*SetupForScreenToScreenCopy)(struct fb_info *info, int xdir, int ydir, int rop, unsigned int planemask, int trans_color);
+	void (*SubsequentScreenToScreenCopy)(struct fb_info *info, int xa, int ya, int xb, int yb, int w, int h);   
+	void (*ScreenToScreenCopy)(struct fb_info *info, int xa, int ya, int xb, int yb, int w, int h, int rop);
+	void (*SetupForMono8x8PatternFill)(struct fb_info *info, int patternx, int patterny, int fg, int bg, int rop, unsigned int planemask);
+	void (*SubsequentMono8x8PatternFillRect)(struct fb_info *info, int patternx, int patterny, int x, int y, int w, int h);
+	void (*SetupForScanlineCPUToScreenColorExpandFill)(struct fb_info *info, int fg, int bg, int rop, unsigned int planemask);
+	void (*SubsequentScanlineCPUToScreenColorExpandFill)(struct fb_info *info, int x, int y, int w, int h, int skipleft);
+	void (*SubsequentScanline)(struct fb_info *info, unsigned long *buf);
+	void (*SetupForScanlineImageWrite)(struct fb_info *info, int rop, unsigned int planemask, int trans_color, int bpp);
+	void (*SubsequentScanlineImageWriteRect)(struct fb_info *info, int x, int y, int w, int h, int skipleft);  
+	void (*SetClippingRectangle)(struct fb_info *info, int xa, int ya, int xb, int yb);
+	void (*DisableClipping)(struct fb_info *info);
+	int (*SetupForCPUToScreenAlphaTexture)(struct fb_info *info, 
+      int op, unsigned short red, unsigned short green, unsigned short blue, unsigned short alpha, unsigned long maskFormat, unsigned long dstFormat, unsigned char *alphaPtr, int alphaPitch, int width, int height, int flags);
+	int (*SetupForCPUToScreenTexture)(struct fb_info *info, int op, unsigned long srcFormat, unsigned long dstFormat, unsigned char *texPtr, int texPitch, int width, int height, int flags);
+	void (*SubsequentCPUToScreenTexture)(struct fb_info *info, int dstx, int dsty, int srcx, int srcy, int width, int height);
+	/* Cursor functions */
+	void (*SetCursorColors)(struct fb_info *info, int bg, int fg);
+	void (*SetCursorPosition)(struct fb_info *info, int x, int y);
+	void (*LoadCursorImage)(struct fb_info *info, unsigned short *mask, unsigned short *data, int zoom);
+	void (*HideCursor)(struct fb_info *info);
+	void (*ShowCursor)(struct fb_info *info);
+	long (*CursorInit)(struct fb_info *info);
+	void (*WaitVbl)(struct fb_info *info);
+};
+
+struct fb_info {
+	struct fb_var_screeninfo var;	/* Current var */
+	struct fb_fix_screeninfo fix;	/* Current fix */
+	struct fb_monspecs monspecs;	/* Current Monitor specs */
+	struct fb_videomode *mode;	/* current mode */
+	char *screen_base;	/* Virtual address */
+	unsigned long screen_size;
+	char *ram_base;	        /* base vram */
+	unsigned long ram_size; /* vram size */
+	char *screen_mono;
+	long update_mono;
+	struct fb_ops *fbops;
+	void *par; /* device dependent */
+};
+
+/* fbmem.c */
+extern int fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var); 
+extern int fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var); 
+extern int fb_blank(struct fb_info *info, int blank);
+extern int fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg);
+extern struct fb_info *framebuffer_alloc(unsigned long size);
+extern void framebuffer_release(struct fb_info *info);
+
+/* offscreen.c */
+extern long offscreen_free(struct fb_info *info, long addr);
+extern long offscreen_alloc(struct fb_info *info, long amount);
+extern long offscren_reserved(struct fb_info *info);
+extern void offscreen_init(struct fb_info *info);
+
+/* fbmon.c */
+#define FB_MAXTIMINGS		0
+#define FB_VSYNCTIMINGS		1
+#define FB_HSYNCTIMINGS		2
+#define FB_DCLKTIMINGS		3
+#define FB_IGNOREMON		0x100
+
+#define FB_MODE_IS_UNKNOWN	0
+#define FB_MODE_IS_DETAILED	1
+#define FB_MODE_IS_STANDARD	2
+#define FB_MODE_IS_VESA		4
+#define FB_MODE_IS_CALCULATED	8
+#define FB_MODE_IS_FIRST	16
+#define FB_MODE_IS_FROM_VAR     32
+
+extern void fb_destroy_modedb(struct fb_videomode *modedb);
+extern int fb_parse_edid(unsigned char *edid, struct fb_var_screeninfo *var);
+extern void fb_edid_to_monspecs(unsigned char *edid, struct fb_monspecs *specs);
+extern int fb_get_mode(int flags, unsigned long val, struct fb_var_screeninfo *var, struct fb_info *info);
+extern int fb_validate_mode(const struct fb_var_screeninfo *var, struct fb_info *info);
+
+/* modedb.c */
+#define VESA_MODEDB_SIZE 34
+extern int fb_find_mode(struct fb_var_screeninfo *var,
+           struct fb_info *info, struct mode_option *resolution ,
+           const struct fb_videomode *db, unsigned int dbsize,
+           const struct fb_videomode *default_mode, unsigned int default_bpp);
+extern void fb_var_to_videomode(struct fb_videomode *mode, struct fb_var_screeninfo *var);
+extern void fb_videomode_to_var(struct fb_var_screeninfo *var, struct fb_videomode *mode);
+extern int fb_mode_is_equal(struct fb_videomode *mode1, struct fb_videomode *mode2);
+
+struct fb_videomode {
+	unsigned short refresh;		/* optional */
+	unsigned short xres;
+	unsigned short yres;
+	unsigned long pixclock;
+	unsigned short left_margin;
+	unsigned short right_margin;
+	unsigned short upper_margin;
+	unsigned short lower_margin;
+	unsigned short hsync_len;
+	unsigned short vsync_len;
+	unsigned short sync;
+	unsigned short vmode;
+	unsigned short flag;
+};
+
+extern const struct fb_videomode vesa_modes[];
+
+/* timer */
+#ifdef COLDFIRE
+#ifdef MCF5445X
+#define US_TO_TIMER(a) (a)
+#define TIMER_TO_US(a) (a)
+#else /* MCF548X */
+#define US_TO_TIMER(a) ((a)*100)
+#define TIMER_TO_US(a) ((a)/100)
+#endif
+#else
+#define US_TO_TIMER(a) (((a)*256)/5000)
+#define TIMER_TO_US(a) (((a)*5000)/256)
+#endif
+
+extern void start_timeout(void);
+extern int end_timeout(long msec);
+extern void mdelay(long msec);
+extern void install_vbl_timer(void *func, int remove);
+extern void uninstall_vbl_timer(void *func);
+
+extern struct fb_info *info_fvdi;
+#endif /* _FB_H */
--- a/include/fec.h
+++ b/include/fec.h
@@ -0,0 +1,96 @@
+/*
+ * File:    fec.h
+ * Purpose: Driver for the Fast Ethernet Controller (FEC)
+ *
+ * Notes:       
+ */
+
+#ifndef _FEC_H_
+#define _FEC_H_
+
+/********************************************************************/
+/* MII Speed Settings */
+#define FEC_MII_10BASE_T        0
+#define FEC_MII_100BASE_TX      1
+
+/* MII Duplex Settings */
+#define FEC_MII_HALF_DUPLEX     0
+#define FEC_MII_FULL_DUPLEX     1
+
+/* Timeout for MII communications */
+#define FEC_MII_TIMEOUT         0x10000
+
+/* External Interface Modes */
+#define FEC_MODE_7WIRE          0
+#define FEC_MODE_MII            1
+#define FEC_MODE_LOOPBACK       2   /* Internal Loopback */
+
+/*
+ * FEC Event Log
+ */
+typedef struct
+{
+	int total;      /* total count of errors   */
+	int hberr;      /* heartbeat error         */
+	int babr;       /* babbling receiver       */
+	int babt;       /* babbling transmitter    */
+	int gra;        /* graceful stop complete  */
+	int txf;        /* transmit frame          */
+	int mii;        /* MII                     */
+	int lc;         /* late collision          */
+	int rl;         /* collision retry limit   */
+	int xfun;       /* transmit FIFO underrrun */
+	int xferr;      /* transmit FIFO error     */
+	int rferr;      /* receive FIFO error      */
+	int dtxf;       /* DMA transmit frame      */
+	int drxf;       /* DMA receive frame       */
+	int rfsw_inv;   /* Invalid bit in RFSW     */
+	int rfsw_l;     /* RFSW Last in Frame      */
+	int rfsw_m;     /* RFSW Miss               */
+	int rfsw_bc;    /* RFSW Broadcast          */
+	int rfsw_mc;    /* RFSW Multicast          */
+	int rfsw_lg;    /* RFSW Length Violation   */
+	int rfsw_no;    /* RFSW Non-octet          */
+	int rfsw_cr;    /* RFSW Bad CRC            */
+	int rfsw_ov;    /* RFSW Overflow           */
+	int rfsw_tr;    /* RFSW Truncated          */
+} FEC_EVENT_LOG;
+
+
+extern int fec_mii_write(uint8_t , uint8_t , uint8_t , uint16_t );
+extern int fec_mii_read(uint8_t , uint8_t , uint8_t , uint16_t *);
+extern void fec_mii_init(uint8_t, uint32_t);
+extern void fec_mib_init(uint8_t);
+extern void fec_mib_dump(uint8_t);
+extern void fec_log_init(uint8_t);
+extern void fec_log_dump(uint8_t);
+extern void fec_debug_dump(uint8_t);
+extern void fec_duplex (uint8_t, uint8_t);
+extern uint8_t fec_hash_address(const uint8_t *);
+extern void fec_set_address (uint8_t ch, const uint8_t *);
+extern void fec_reset (uint8_t);
+extern void fec_init(uint8_t ch, uint8_t mode, const uint8_t *pa);
+extern void fec_rx_start(uint8_t, int8_t *);
+extern void fec_rx_restart(uint8_t);
+extern void fec_rx_stop (uint8_t);
+extern void fec_rx_frame(uint8_t, NIF *);
+extern void fec0_rx_frame(void);
+extern void fec1_rx_frame(void);
+extern void fec_tx_start(uint8_t, int8_t *);
+extern void fec_tx_restart(uint8_t);
+extern void fec_tx_stop (uint8_t);
+extern void fec0_tx_frame(void);
+extern void fec1_tx_frame(void);
+extern int fec_send(uint8_t, NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *);
+extern int fec0_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *);
+extern int fec1_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *);
+extern void fec_irq_enable(uint8_t, uint8_t, uint8_t);
+extern void fec_irq_disable(uint8_t);
+extern void fec_interrupt_handler(uint8_t);
+extern int fec0_interrupt_handler(void *, void *);
+extern int fec1_interrupt_handler(void *, void *);
+extern void fec_eth_setup(uint8_t, uint8_t, uint8_t, uint8_t, const uint8_t *);
+extern void fec_eth_reset(uint8_t);
+extern void fec_eth_stop(uint8_t);
+
+#endif /* _FEC_H_ */
--- a/include/fecbd.h
+++ b/include/fecbd.h
@@ -0,0 +1,93 @@
+/*
+ * File:    fecbd.h
+ * Purpose:     
+ *
+ * Purpose: Provide a simple buffer management driver
+ */
+
+#ifndef _FECBD_H_
+#define _FECBD_H_
+
+#include "bas_types.h"
+
+/********************************************************************/
+
+#define Rx  1
+#define Tx  0
+
+/*
+ * Buffer sizes in bytes 
+ */
+#ifndef RX_BUF_SZ
+#define RX_BUF_SZ  NBUF_SZ  
+#endif
+#ifndef TX_BUF_SZ
+#define TX_BUF_SZ  NBUF_SZ
+#endif
+
+/* 
+ * Number of Rx and Tx Buffers and Buffer Descriptors 
+ */
+#ifndef NRXBD
+#define NRXBD   20
+#endif
+#ifndef NTXBD
+#define NTXBD   20
+#endif
+
+/* 
+ * Buffer Descriptor Format 
+ */
+typedef struct
+{
+	uint16_t status;  /* control and status */
+	uint16_t length;  /* transfer length */
+	uint8_t  *data;   /* buffer address */
+} FECBD;
+
+/*
+ * Bit level definitions for status field of buffer descriptors
+ */
+#define TX_BD_R         0x8000
+#define TX_BD_TO1       0x4000
+#define TX_BD_W         0x2000
+#define TX_BD_TO2       0x1000
+#define TX_BD_INTERRUPT 0x1000  /* MCF547x/8x Only */
+#define TX_BD_L         0x0800
+#define TX_BD_TC        0x0400
+#define TX_BD_DEF       0x0200  /* MCF5272 Only */
+#define TX_BD_ABC       0x0200
+#define TX_BD_HB        0x0100  /* MCF5272 Only */
+#define TX_BD_LC        0x0080  /* MCF5272 Only */
+#define TX_BD_RL        0x0040  /* MCF5272 Only */
+#define TX_BD_UN        0x0002  /* MCF5272 Only */
+#define TX_BD_CSL       0x0001  /* MCF5272 Only */
+
+#define RX_BD_E         0x8000
+#define RX_BD_R01       0x4000
+#define RX_BD_W         0x2000
+#define RX_BD_R02       0x1000
+#define RX_BD_INTERRUPT 0x1000  /* MCF547x/8x Only */
+#define RX_BD_L         0x0800
+#define RX_BD_M         0x0100
+#define RX_BD_BC        0x0080
+#define RX_BD_MC        0x0040
+#define RX_BD_LG        0x0020
+#define RX_BD_NO        0x0010
+#define RX_BD_CR        0x0004
+#define RX_BD_OV        0x0002
+#define RX_BD_TR        0x0001
+#define RX_BD_ERROR     (RX_BD_NO | RX_BD_CR | RX_BD_OV | RX_BD_TR)
+
+/* 
+ * Functions provided in fec_bd.c 
+ */
+extern void fecbd_init(uint8_t);
+extern uint32_t fecbd_get_start(uint8_t, uint8_t);
+extern FECBD *fecbd_rx_alloc(uint8_t);
+extern FECBD *fecbd_tx_alloc(uint8_t);
+extern FECBD *fecbd_tx_free(uint8_t);
+
+/*******************************************************************/
+
+#endif /* _FECBD_H_ */
--- a/include/ff.h
+++ b/include/ff.h
@@ -21,7 +21,7 @@
 extern "C" {
 #endif

-#include <stdint.h>
+#include <bas_types.h>
 #include <ffconf.h>		/* FatFs configuration options */

 #if _FATFS != _FFCONF
--- a/include/fifo.h
+++ b/include/fifo.h
@@ -1,55 +0,0 @@
-/*
- * This is taken from general implementations
- * on the internet, and definately needs some
- * work.
- *
- * good enough for now.
- *
- */
-
-#ifndef FIREBEE_FIFO
-#define FIREBEE_FIFO
-
-#include <inttypes.h>
-
-/*
- * FIFO
- * 
- * Make this look exactly like IOREC, so that
- * we can interchange the two.  But ignore the
- * low, high watermarks.  For now.
- *
- * in IOREC, the notion of head/tail is opposite
- * to ours.  So we place our head/tail, in the
- * equivalent positions as TOS use is.  So
- * we can use this structure, intermittantly
- * with TOS.
- */
-typedef struct
-{
-    char * buf;
-    int16_t size;
-    int16_t tail;
-    int16_t head;
-    int16_t low;
-    int16_t high;
-} fifo_t;
-
-void fifo_init(fifo_t*, char*, int16_t);
-void fifo_advance(fifo_t*, int16_t*);
-
-uint8_t fifo_get(fifo_t*);
-void fifo_put(fifo_t*, uint8_t);
-
-void fifo_clear(fifo_t*);
-
-int fifo_used(fifo_t*);
-int fifo_unused(fifo_t*);
-
-int fifo_full(fifo_t*);
-int fifo_empty(fifo_t*);
-
-int fifo_read(fifo_t*, unsigned char *, int16_t);
-int fifo_write(fifo_t*, const unsigned char*, int16_t);
-
-#endif
--- a/include/firebee.h
+++ b/include/firebee.h
@@ -0,0 +1,50 @@
+#ifndef _FIREBEE_H_
+#define _FIREBEE_H_
+
+/*
+ * firebee.h
+ *
+ * preprocessor definitions for the Firebee machine. This file should contain nothing but preprocessor
+ * definition that evaluate to numbers. It is intended for use in C sources as well as in linker control
+ * files, so care must be taken to not break the syntax of either one.
+ * 
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 26.02.2013
+ *      Author: Markus Fröschle
+ */
+
+#define SYSCLK			132000		/* NOTE: 132 _is_ correct. 133 _is_ wrong. Do not change! */
+
+#define BOOTFLASH_BASE_ADDRESS		0xE0000000
+#define BOOTFLASH_SIZE				0x800000		/* FireBee has 8 MByte Flash */
+#define BOOTFLASH_BAM				(BOOTFLASH_SIZE - 1)
+
+#define SDRAM_START					0x00000000	/* start at address 0 */
+#define SDRAM_SIZE					0x20000000	/* 512 MB on the Firebee */
+
+#ifdef COMPILE_RAM
+#define TARGET_ADDRESS  	(SDRAM_START + SDRAM_SIZE - 0x200000)
+#else
+#define TARGET_ADDRESS  	BOOTFLASH_BASE_ADDRESS
+
+#endif /* COMPILE_RAM */
+
+#define DRIVER_MEM_BUFFER_SIZE   	0x100000
+
+#define EMUTOS_BASE_ADDRESS	0xe0600000
+
+#endif /* _FIREBEE_H_ */
--- a/include/font.h
+++ b/include/font.h
@@ -0,0 +1,98 @@
+/*
+ * font.h - font specific definitions
+ *
+ * Copyright (c) 2001 Lineo, Inc.
+ * Copyright (c) 2004 by Authors:
+ *
+ * Authors:
+ *  MAD     Martin Doering
+ *
+ * This file is distributed under the GPL, version 2 or at your
+ * option any later version.  See doc/license.txt for details.
+ */
+
+#ifndef FONT_H
+#define FONT_H
+
+#include <stdint.h>
+
+/* font header flags */
+
+#define F_DEFAULT 1     /* this is the default font (face and size) */
+#define F_HORZ_OFF  2   /* there are left and right offset tables */
+#define F_STDFORM  4    /* is the font in standard format */
+#define F_MONOSPACE 8   /* is the font monospaced */
+
+/* font style bits */
+
+#define F_THICKEN 1
+#define F_LIGHT 2
+#define F_SKEW  4
+#define F_UNDER 8
+#define F_OUTLINE 16
+#define F_SHADOW        32
+
+/* font specific linea variables */
+
+extern const uint16_t *v_fnt_ad;   /* address of current monospace font */
+extern const uint16_t *v_off_ad;   /* address of font offset table */
+extern uint16_t v_fnt_nd;          /* ascii code of last cell in font */
+extern uint16_t v_fnt_st;          /* ascii code of first cell in font */
+extern uint16_t v_fnt_wr;          /* font cell wrap */
+
+/* character cell specific linea variables */
+
+extern uint16_t    v_cel_ht;       /* cell height (width is 8) */
+extern uint16_t    v_cel_mx;       /* needed by MiNT: columns on the screen minus 1 */
+extern uint16_t    v_cel_my;       /* needed by MiNT: rows on the screen minus 1 */
+extern uint16_t    v_cel_wr;       /* needed by MiNT: length (in int8_ts) of a line of characters */
+
+/*
+ * font_ring is a struct of four pointers, each of which points to
+ * a list of font headers linked together to form a string.
+ */
+
+extern struct font_head *font_ring[4];  /* Ring of available fonts */
+extern int16_t font_count;                 /* all three fonts and NULL */
+
+/* the font header descibes a font */
+
+struct font_head {
+    int16_t font_id;
+    int16_t point;
+    int8_t name[32];
+    uint16_t first_ade;
+    uint16_t last_ade;
+    uint16_t top;
+    uint16_t ascent;
+    uint16_t half;
+    uint16_t descent;
+    uint16_t bottom;
+    uint16_t max_char_width;
+    uint16_t max_cell_width;
+    uint16_t left_offset;          /* amount character slants left when skewed */
+    uint16_t right_offset;         /* amount character slants right */
+    uint16_t thicken;              /* number of pixels to smear */
+    uint16_t ul_size;              /* size of the underline */
+    uint16_t lighten;              /* mask to and with to lighten  */
+    uint16_t skew;                 /* mask for skewing */
+    uint16_t flags;
+
+    const uint8_t *hor_table;     /* horizontal offsets */
+    const uint16_t *off_table;     /* character offsets  */
+    const uint16_t *dat_table;     /* character definitions */
+    uint16_t form_width;
+    uint16_t form_height;
+
+    struct font_head *next_font;/* pointer to next font */
+    uint16_t font_seg;
+};
+
+
+
+/* prototypes */
+
+void font_init(void);           /* initialize BIOS font ring */
+void font_set_default(void);    /* choose the default font */
+
+#endif /* FONT_H */
--- a/include/i2c-algo-bit.h
+++ b/include/i2c-algo-bit.h
@@ -0,0 +1,54 @@
+/* ------------------------------------------------------------------------- */
+/* i2c-algo-bit.h i2c driver algorithms for bit-shift adapters               */
+/* ------------------------------------------------------------------------- */
+/*   Copyright (C) 1995-99 Simon G. Vogl
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.                */
+/* ------------------------------------------------------------------------- */
+
+/* With some changes from Ky<4B>sti M<>lkki <kmalkki@cc.hut.fi> and even
+   Frodo Looijaard <frodol@dds.nl> */
+
+/* $Id: i2c-algo-bit.h,v 1.1.1.1 2012/08/16 18:43:05 mfro Exp $ */
+
+#ifndef I2C_ALGO_BIT_H
+#define I2C_ALGO_BIT_H
+
+/* --- Defines for bit-adapters ---------------------------------------	*/
+/*
+ * This struct contains the hw-dependent functions of bit-style adapters to 
+ * manipulate the line states, and to init any hw-specific features. This is
+ * only used if you have more than one hw-type of adapter running. 
+ */
+struct i2c_algo_bit_data {
+	void *data;		/* private data for lowlevel routines */
+	void (*setsda) (void *data, int state);
+	void (*setscl) (void *data, int state);
+	int  (*getsda) (void *data);
+	int  (*getscl) (void *data);
+
+	/* local settings */
+	int udelay;		/* half-clock-cycle time in microsecs */
+				/* i.e. clock is (500 / udelay) KHz */
+	int mdelay;		/* in millisecs, unused */
+	int timeout;		/* in jiffies */
+};
+
+#define I2C_BIT_ADAP_MAX	16
+
+int i2c_bit_add_bus(struct i2c_adapter *);
+int i2c_bit_del_bus(struct i2c_adapter *);
+
+#endif /* I2C_ALGO_BIT_H */
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -0,0 +1,82 @@
+/* ------------------------------------------------------------------------- */
+/*                                                                           */
+/* i2c.h - definitions for the i2c-bus interface                             */
+/*                                                                           */
+/* ------------------------------------------------------------------------- */
+/*   Copyright (C) 1995-2000 Simon G. Vogl
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.		     */
+/* ------------------------------------------------------------------------- */
+
+/* With some changes from Ky<4B>sti M<>lkki <kmalkki@cc.hut.fi> and
+   Frodo Looijaard <frodol@dds.nl> */
+
+/* $Id: i2c.h,v 1.1.1.1 2012/08/16 18:43:05 mfro Exp $ */
+
+#ifndef _I2C_H
+#define _I2C_H
+
+/* --- General options ------------------------------------------------	*/
+
+struct i2c_msg;
+struct i2c_algorithm;
+struct i2c_adapter;
+
+/* Transfer num messages.
+ */
+extern int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num);
+
+/*
+ * The following structs are for those who like to implement new bus drivers:
+ * i2c_algorithm is the interface to a class of hardware solutions which can
+ * be addressed using the same bus algorithms - i.e. bit-banging or the PCF8584
+ * to name two of the most common.
+ */
+struct i2c_algorithm {
+	unsigned int id;
+	int (*master_xfer)(struct i2c_adapter *adap,struct i2c_msg *msgs, int num);
+	/* --- ioctl like call to set div. parameters. */
+	int (*algo_control)(struct i2c_adapter *, unsigned int, unsigned long);
+};
+
+/*
+ * i2c_adapter is the structure used to identify a physical i2c bus along
+ * with the access algorithms necessary to access it.
+ */
+struct i2c_adapter {
+	struct i2c_algorithm *algo;/* the algorithm to access the bus	*/
+	void *algo_data;
+	int timeout;
+	int retries;
+	int nr;
+};
+
+/*
+ * I2C Message - used for pure i2c transaction, also from /dev interface
+ */
+struct i2c_msg {
+	unsigned short addr;	/* slave address			*/
+ 	unsigned short flags;		
+#define I2C_M_TEN	0x10	/* we have a ten bit chip address	*/
+#define I2C_M_RD	0x01
+#define I2C_M_NOSTART	0x4000
+#define I2C_M_REV_DIR_ADDR	0x2000
+#define I2C_M_IGNORE_NAK	0x1000
+#define I2C_M_NO_RD_ACK		0x0800
+ 	unsigned short len;		/* msg length				*/
+ 	unsigned char *buf;		/* pointer to msg data			*/
+};
+
+#endif /* _I2C_H */
--- a/include/i2c_firebee.h
+++ b/include/i2c_firebee.h
@@ -1,48 +0,0 @@
-/*
- * i2c.h
- *
- */
-
-#ifndef I2CFIREBEE_h
-#define I2CFIREBEE_h
-
-#include <fifo.h>
-
-#ifndef BUFSIZ
-#define BUFSIZ 512
-#endif
-
-#define I2CTLREAD   (('i'<<8) | 1)
-#define I2CTLWRITE  (('i'<<8) | 2)
-#define I2CTLSBUF   (('i'<<8) | 3)
-#define I2CTLINIT   (('i'<<8) | 4)
-#define I2CTLDEV    (('i'<<8) | 5)
-
-// Set a specific bit
-#define set_bit(p,bit)          p |= (bit)
-#define set_bit_nr(p,nr)        set_bit(p,(1<<(nr)))
-
-// Clear a specific bit
-#define clear_bit(p,bit)        p &= ~(bit)
-#define clear_bit_nr(p,nr)      clear_bit(p,(1<<(nr)))
-
-#define ELAPSED(t)              (t - ReadTimer())
-
-#define I2C_BUFFER_LENGTH 32
-
-#define I2C_READY   0
-#define I2C_MXRX    1
-#define I2C_MXTX    2
-
-#define I2C_ADDR    6
-
-#define I2C_READ    1
-#define I2C_WRITE   0
-
-unsigned long ReadTimer();
-void DelayMicroSec(unsigned long);
-
-void I2C_Init();
-int I2C_ioctl(unsigned int, unsigned long);
-
-#endif
--- a/include/icmp.h
+++ b/include/icmp.h
@@ -0,0 +1,121 @@
+/*
+ * File:        icmp.h
+ * Purpose:     Handle Internet Control Message Protocol packets.
+ *
+ * Notes:       See RFC 792 "Internet Control Message Protocol"
+ *              for more details.
+ */
+
+#ifndef _ICMP_H
+#define _ICMP_H
+
+/********************************************************************/
+
+typedef struct
+{
+    uint32_t  unused;
+    uint8_t   ih_dg;
+} icmp_dest_unreachable;
+#define ICMP_DEST_UNREACHABLE       (3) /* type */
+#define ICMP_NET_UNREACHABLE        (0) /* code */
+#define ICMP_HOST_UNREACHABLE       (1)
+#define ICMP_PROTOCOL_UNREACHABLE   (2)
+#define ICMP_PORT_UNREACHABLE       (3)
+#define ICMP_FRAG_NEEDED            (4)
+#define ICMP_ROUTE_FAILED           (5)
+
+typedef struct
+{
+    uint32_t  unused;
+    uint8_t   ih_dg;
+} icmp_time_exceeded;
+#define ICMP_TIME_EXCEEDED          (11)    /* type */
+#define ICMP_TTL_EXCEEDED           (0)     /* code */
+#define ICMP_FRAG_TIME_EXCEEDED     (1)
+
+typedef struct
+{
+    uint8_t   pointer;
+    uint8_t   unused1;
+    uint16_t  unused2;
+    uint8_t   ih_dg;
+} icmp_parameter_problem;
+#define ICMP_PARAMETER_PROBLEM      (12)    /* type */
+#define ICMP_POINTER                (0)     /* code -- not */
+
+typedef struct
+{
+    uint32_t  unused;
+    uint8_t   ih_dg;
+} icmp_source_quench;
+#define ICMP_SOURCE_QUENCH          (4)     /* type */
+
+typedef struct
+{
+    uint32_t  gateway_addr;
+    uint8_t   ih_dg;
+} icmp_redirect;
+#define ICMP_REDIRECT               (5)     /* type */
+#define ICMP_REDIRECT_NET           (0)     /* code */
+#define ICMP_REDIRECT_HOST          (1)
+#define ICMP_REDIRECT_TOS_NET       (2)
+#define ICMP_REDIRECT_TOS_HOST      (3)
+
+typedef struct
+{
+    uint16_t  identifier;
+    uint16_t  sequence;
+    uint8_t   data;
+} icmp_echo;
+#define ICMP_ECHO                   (8)     /* type */
+#define ICMP_ECHO_REPLY             (0)     /* type */
+
+typedef struct
+{
+    uint16_t  identifier;
+    uint16_t  sequence;
+} icmp_information;
+#define ICMP_INFORMATION_REQUEST    (15)    /* type */
+#define ICMP_INFORMATION_REPLY      (16)    /* type */
+
+typedef struct
+{
+    uint16_t  identifier;
+    uint16_t  sequence;
+    uint32_t  originate_ts;
+    uint32_t  receive_ts;
+    uint32_t  transmit_ts;
+} icmp_timestamp;
+#define ICMP_TIMESTAMP              (13)    /* type */
+#define ICMP_TIMESTAMP_REPLY        (14)    /* type */
+
+typedef struct
+{
+    uint8_t   type;
+    uint8_t   code;
+    uint16_t  chksum;
+    union
+    {
+        icmp_dest_unreachable       dest_unreachable;
+        icmp_source_quench          source_quench;
+        icmp_redirect               redirect;
+        icmp_time_exceeded          time_exceeded;
+        icmp_parameter_problem      parameter_problem;
+        icmp_timestamp              timestamp;
+        icmp_information            information;
+        icmp_echo                   echo;
+    } msg;
+} icmp_message;
+
+/********************************************************************/
+
+/* Protocol Header information */
+#define ICMP_HDR_OFFSET     (ETH_HDR_LEN + IP_HDR_SIZE)
+#define ICMP_HDR_SIZE       8
+
+void
+icmp_handler(NIF *, NBUF *);
+
+/********************************************************************/
+
+#endif  /* _ICMP_H */
--- a/include/ikbd.h
+++ b/include/ikbd.h
@@ -0,0 +1,11 @@
+#ifndef _IKBD_H_
+#define _IKBD_H_
+
+extern void ikbd_init(void);
+extern void ikbd_poll(void);
+extern void ikbd_joystick(uint8_t joy, uint8_t map);
+extern void ikbd_mouse(uint8_t buttons, int8_t x, int8_t y);
+extern void ikbd_keyboard(uint8_t code);
+
+#endif /* _IKBD_H_ */
+
--- a/include/interrupts.h
+++ b/include/interrupts.h
@@ -0,0 +1,108 @@
+/*
+ * interrupts.h
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *
+ *  Created on: 08.08.2013
+ *      Author: Markus Fröschle
+ */
+
+#ifndef _INTERRUPTS_H_
+#define _INTERRUPTS_H_
+
+#include <stdbool.h>
+
+/* interrupt sources */
+#define INT_SOURCE_EPORT_EPF1		1	// edge port flag 1
+#define	INT_SOURCE_EPORT_EPF2		2	// edge port flag 2
+#define	INT_SOURCE_EPORT_EPF3		3	// edge port flag 3
+#define	INT_SOURCE_EPORT_EPF4		4	// edge port flag 4
+#define	INT_SOURCE_EPORT_EPF5		5	// edge port flag 5
+#define	INT_SOURCE_EPORT_EPF6		6	// edge port flag 6
+#define	INT_SOURCE_EPORT_EPF7		7	// edge port flag 7
+#define	INT_SOURCE_USB_EP0ISR		15	// USB endpoint 0 interrupt
+#define	INT_SOURCE_USB_EP1ISR		16	// USB endpoint 1 interrupt
+#define	INT_SOURCE_USB_EP2ISR		17	// USB endpoint 2 interrupt
+#define	INT_SOURCE_USB_EP3ISR		18	// USB endpoint 3 interrupt
+#define	INT_SOURCE_USB_EP4ISR		19	// USB endpoint 4 interrupt
+#define	INT_SOURCE_USB_EP5ISR		20	// USB endpoint 5 interrupt
+#define	INT_SOURCE_USB_EP6ISR		21	// USB endpoint 6 interrupt
+#define	INT_SOURCE_USB_USBISR		22	// USB general interrupt
+#define	INT_SOURCE_USB_USBAISR		23	// USB core interrupt
+#define	INT_SOURCE_USB_ANY			24	// OR of all USB interrupts
+#define	INT_SOURCE_USB_DSPI_OVF		25	// DSPI overflow or underflow
+#define	INT_SOURCE_USB_DSPI_RFOF	26	// receive FIFO overflow interrupt
+#define	INT_SOURCE_USB_DSPI_RFDF	27	// receive FIFO drain interrupt
+#define	INT_SOURCE_USB_DSPI_TFUF	28	// transmit FIFO underflow interrupt
+#define	INT_SOURCE_USB_DSPI_TCF		29	// transfer complete interrupt
+#define	INT_SOURCE_USB_DSPI_TFFF	30	// transfer FIFO fill interrupt
+#define	INT_SOURCE_USB_DSPI_EOQF	31	// end of queue interrupt
+#define	INT_SOURCE_PSC3				32	// PSC3 interrupt
+#define	INT_SOURCE_PSC2				33	// PSC2 interrupt
+#define	INT_SOURCE_PSC1				34	// PSC1 interrupt
+#define	INT_SOURCE_PSC0				35	// PSC0 interrupt
+#define	INT_SOURCE_CTIMERS			36	// combined source for comm timers
+#define	INT_SOURCE_SEC				37	// SEC interrupt
+#define	INT_SOURCE_FEC1				38	// FEC1 interrupt
+#define	INT_SOURCE_FEC0				39	// FEC0 interrupt
+#define	INT_SOURCE_I2C				40	// I2C interrupt
+#define	INT_SOURCE_PCIARB			41	// PCI arbiter interrupt
+#define	INT_SOURCE_CBPCI			42	// COMM bus PCI interrupt
+#define	INT_SOURCE_XLBPCI			43	// XLB PCI interrupt
+#define	INT_SOURCE_XLBARB			47	// XLBARB to PCI interrupt
+#define	INT_SOURCE_DMA				48	// multichannel DMA interrupt
+#define	INT_SOURCE_CAN0_ERROR		49	// FlexCAN error interrupt
+#define	INT_SOURCE_CAN0_BUSOFF		50	// FlexCAN bus off interrupt
+#define	INT_SOURCE_CAN0_MBOR		51	// message buffer ORed interrupt
+#define	INT_SOURCE_SLT1				53	// slice timer 1 interrupt
+#define	INT_SOURCE_SLT0				54	// slice timer 0 interrupt
+#define	INT_SOURCE_CAN1_ERROR		55	// FlexCAN error interrupt
+#define	INT_SOURCE_CAN1_BUSOFF		56	// FlexCAN bus off interrupt
+#define	INT_SOURCE_CAN1_MBOR		57	// message buffer ORed interrupt
+#define	INT_SOURCE_GPT3				59	// GPT3 timer interrupt
+#define	INT_SOURCE_GPT2				60	// GPT2 timer interrupt
+#define	INT_SOURCE_GPT1				61	// GPT1 timer interrupt
+#define	INT_SOURCE_GPT0				62	// GPT0 timer interrupt
+
+
+#define FEC0_INTC_LVL	5			/* interrupt level for FEC0 */
+#define FEC0_INTC_PRI	1			/* interrupt priority for FEC0 */
+
+#define FEC1_INTC_LVL	5			/* interrupt level for FEC1 */
+#define FEC1_INTC_PRI	0			/* interrupt priority for FEC1 */
+
+#define FEC_INTC_LVL(x)		((x == 0) ? FEC0_INTC_LVL : FEC1_INTC_LVL)
+#define FEC_INTC_PRI(x)		((x == 0) ? FEC0_INTC_PRI : FEC1_INTC_PRI)
+
+#define FEC0RX_DMA_PRI      5
+#define FEC1RX_DMA_PRI      3
+#define FECRX_DMA_PRI(x)    ((x == 0) ? FEC0RX_DMA_PRI : FEC1RX_DMA_PRI)
+#define FEC0TX_DMA_PRI      6
+#define FEC1TX_DMA_PRI      4
+#define FECTX_DMA_PRI(x)    ((x == 0) ? FEC0TX_DMA_PRI : FEC1TX_DMA_PRI)
+
+extern int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority, uint8_t intr, void (*handler)(void));
+
+#define ISR_DBUG_ISR	0x01
+#define ISR_USER_ISR 	0x02
+
+extern void isr_init(void);
+extern int isr_register_handler(int vector, int (*handler)(void *, void *), void *hdev, void *harg);
+extern void isr_remove_handler(int (*handler)(void *, void *));
+extern bool isr_execute_handler(int vector);
+extern int pic_interrupt_handler(void *arg1, void *arg2);
+#endif /* _INTERRUPTS_H_ */
--- a/include/ip.h
+++ b/include/ip.h
@@ -0,0 +1,80 @@
+/*
+ * File:        ip.h
+ * Purpose:     Definitions for the Internet Protocol, IP.
+ *
+ * Notes:       See RFC 791 "DARPA Internet Program Protocol
+ *              Specification" for more details.
+ */
+
+#ifndef _IP_H
+#define _IP_H
+
+
+/* 32-bit IP Addresses */
+typedef uint8_t IP_ADDR[4];
+
+/* Pointer to an IP Address */
+typedef uint8_t IP_ADDR_P[];
+
+/* Definition of an IP packet header */
+typedef struct
+{
+	uint8_t       version_ihl;
+	uint8_t       service_type;
+	uint16_t      total_length;
+	uint16_t      identification;
+	uint16_t      flags_frag_offset;
+	uint8_t       ttl;
+	uint8_t       protocol;
+	uint16_t      checksum;
+	IP_ADDR     source_addr;
+	IP_ADDR     dest_addr;
+	uint8_t       options;    /* actually an array of undetermined length */
+} ip_frame_hdr;
+
+/* Macros for accessing an IP datagram.  */
+#define IP_VERSION(a)   ((a->version_ihl & 0x00F0) >> 4)
+#define IP_IHL(a)       ((a->version_ihl & 0x000F))
+#define IP_SERVICE(a)   (a->service_type)
+#define IP_LENGTH(a)    (a->total_length)
+#define IP_IDENT(a)     (a->identification)
+#define IP_FLAGS(a)     ((a->flags_frag_offset & 0x0000E000) >> 13)
+#define IP_FRAGMENT(a)  ((a->flags_frag_offset & 0x00001FFF))
+#define IP_TTL(a)       (a->ttl)
+#define IP_PROTOCOL(a)  (a->protocol)
+#define IP_CHKSUM(a)    (a->checksum)
+#define IP_SRC(a)       (&a->source_addr[0])
+#define IP_DEST(a)      (&a->dest_addr[0])
+#define IP_OPTIONS(a)   (&a->options)
+#define IP_DATA(a)      (&((uint8_t *)a)[IP_IHL(a) * 4])
+
+/* Defined IP protocols */
+#define IP_PROTO_ICMP   (1)
+#define IP_PROTO_UDP    (17)
+
+/* Protocol Header information */
+#define IP_HDR_OFFSET   ETH_HDR_LEN
+#define IP_HDR_SIZE     20  /* no options */
+
+
+typedef struct
+{
+	IP_ADDR         myip;
+	IP_ADDR         gateway;
+	IP_ADDR         netmask;
+	IP_ADDR         broadcast;
+	unsigned int    rx;
+	unsigned int    rx_unsup;
+	unsigned int    tx;
+	unsigned int    err;
+} IP_INFO;
+
+
+extern void ip_handler(NIF *nif, NBUF *nbf);
+uint16_t ip_chksum(uint16_t *data, int num);
+extern int ip_send(NIF *nif, uint8_t *dest_addr, uint8_t *src_addr, uint8_t protocol, NBUF *nbf);
+extern void ip_init(IP_INFO *, IP_ADDR_P, IP_ADDR_P, IP_ADDR_P);
+extern uint8_t *ip_get_myip(IP_INFO *);
+extern uint8_t *ip_resolve_route(NIF *, IP_ADDR_P);
+
+#endif  /* _IP_H */
--- a/include/m54455.h
+++ b/include/m54455.h
@@ -0,0 +1,49 @@
+#ifndef _M54455_H_
+#define _M54455_H_
+
+/*
+ * m54455.h
+ *
+ * preprocessor definitions for the M54455 Freescale machine. This file should contain nothing but preprocessor
+ * definition that evaluate to numbers. It is intended for use in C sources as well as in linker control
+ * files, so care must be taken to not break the syntax of either one.
+ * 
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 26.02.2013
+ *      Author: Markus Fröschle
+ */
+
+#define SYSCLK			133000
+
+#define BOOTFLASH_BASE_ADDRESS		0xe0000000
+#define BOOTFLASH_SIZE				0x800000
+#define BOOTFLASH_BAM				(BOOTFLASH_SIZE - 1)
+
+#define SDRAM_START					0x00000000	/* start at address 0 */
+#define SDRAM_SIZE					0x8000000
+
+#ifdef COMPILE_RAM
+#define TARGET_ADDRESS	(SDRAM_START + SDRAM_SIZE - 0x200000)
+#else
+#define TARGET_ADDRESS	BOOTFLASH_BASE_ADDRESS
+#endif /* COMPILE_RAM */
+
+#define DRIVER_MEM_BUFFER_SIZE	0x100000
+
+#define EMUTOS_BASE_ADDRESS 	0xe0100000
+
+#endif /* _M54455_H_ */
--- a/include/m5484l.h
+++ b/include/m5484l.h
@@ -0,0 +1,49 @@
+#ifndef _M5484L_H_
+#define _M5484L_H_
+
+/*
+ * m5484l.h
+ *
+ * preprocessor definitions for the M5484LITE machine. This file should contain nothing but preprocessor
+ * definition that evaluate to numbers. It is intended for use in C sources as well as in linker control
+ * files, so care must be taken to not break the syntax of either one.
+ * 
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 26.02.2013
+ *      Author: Markus Fröschle
+ */
+
+#define SYSCLK			100000
+
+#define BOOTFLASH_BASE_ADDRESS		0xe0000000
+#define BOOTFLASH_SIZE				0x400000	/* LITEKIT has 4MB flash */
+#define BOOTFLASH_BAM				(BOOTFLASH_SIZE - 1)
+
+#define SDRAM_START					0x00000000	/* start at address 0 */
+#define SDRAM_SIZE					0x4000000  	/* 64 MB on the LITEKIT */
+
+#ifdef COMPILE_RAM
+#define TARGET_ADDRESS	(SDRAM_START + SDRAM_SIZE - 0x200000)
+#else
+#define TARGET_ADDRESS	BOOTFLASH_BASE_ADDRESS
+#endif /* COMPILE_RAM */
+
+#define DRIVER_MEM_BUFFER_SIZE	0x100000
+
+#define EMUTOS_BASE_ADDRESS 	0xe0100000
+
+#endif /* _M5484L_H_ */
--- a/include/mcd_initiators.h
+++ b/include/mcd_initiators.h
@@ -0,0 +1,48 @@
+#ifndef _MCD_INITIATORS_H_
+#define _MCD_INITIATORS_H_
+
+/* initiators */
+
+/* direct connected initiators */
+#define DMA_ALWAYS		(0)
+#define DMA_DSPI_RXFIFO	(1)
+#define DMA_DSPI_TXFIFO	(2)
+#define	DMA_DREQ0		(3)
+#define DMA_PSC0_RX		(4)
+#define	DMA_PSC0_TX		(5)
+#define	DMA_USB_EP0		(6)
+#define	DMA_USB_EP1		(7)
+#define DMA_USB_EP2		(8)
+#define DMA_USB_EP3		(9)
+#define DMA_PCI_TX		(10)
+#define DMA_PCI_RX		(11)
+#define DMA_PSC1_RX		(12)
+#define DMA_PSC1_TX		(13)
+#define	DMA_I2C_RX		(14)
+#define DMA_I2C_TX		(15)
+
+/* multiplexed initiators */
+#define DMA_FEC0_RX 	(16)
+#define DMA_FEC0_TX 	(17)
+#define DMA_FEC1_RX 	(18)
+#define DMA_FEC1_TX 	(19)
+#define DMA_DREQ1 		(20)
+#define DMA_CTM0 		(21)
+#define DMA_CTM1 		(22)
+#define DMA_CTM2 		(23)
+#define DMA_CTM3 		(24)
+#define DMA_CTM4 		(25)
+#define DMA_CTM5 		(26)
+#define DMA_CTM6 		(27)
+#define DMA_CTM7 		(28)
+#define DMA_USBEP4 		(29)
+#define DMA_USBEP5 		(30)
+#define DMA_USBEP6		(31)
+#define DMA_PSC2_RX		(32)
+#define DMA_PSC2_TX		(33)
+#define DMA_PSC3_RX		(34)
+#define DMA_PSC3_TX		(35)
+#define DMA_FEC_RX(x)	((x == 0) ? DMA_FEC0_RX : DMA_FEC1_RX)
+#define DMA_FEC_TX(x)	((x == 0) ? DMA_FEC0_TX : DMA_FEC1_TX)
+
+#endif /* _MCD_INITIATORS_H_ */
--- a/include/mmu.h
+++ b/include/mmu.h
@@ -0,0 +1,99 @@
+/*
+ * mmu.h
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 26.02.2013
+ *      Author: Markus Fröschle
+ */
+
+
+#ifndef _MMU_H_
+#define _MMU_H_
+
+#include <stddef.h>
+#include "bas_types.h"
+
+/*
+ * ACR register handling macros
+ */
+#define ACR_BA(x)                   ((x) & 0xffff0000)
+#define ACR_ADMSK(x)                (((x) & 0xffff) << 16)
+#define ACR_E(x)                    (((x) & 1) << 15)
+
+#define ACR_S(x)                    (((x) & 3) << 13)
+#define ACR_S_USERMODE              0
+#define ACR_S_SUPERVISOR_MODE       1
+#define ACR_S_ALL                   2
+
+#define ACR_ADDRESS_MASK_MODE(x)	(((x) & 1) << 10)
+
+#define ACR_CACHE_MODE(x)			(((x) & 3) << 5)
+#define ACR_SUPERVISOR_PROTECT(x)	(((x) & 1) << 3)
+#define ACR_WRITE_PROTECT(x)		(((x) & 1) << 2)
+
+
+/*
+ * MMU register handling macros
+ */
+
+#define SCA_PAGE_ID			6		/* indicates video memory page */
+#define DEFAULT_PAGE_SIZE	0x2000	/* use 8k pages for MiNT compatibility */
+/*
+ * MMU page sizes
+ */
+
+enum mmu_page_size
+{
+    MMU_PAGE_SIZE_1M	= 0,
+    MMU_PAGE_SIZE_4K	= 1,
+    MMU_PAGE_SIZE_8K	= 2,
+    MMU_PAGE_SIZE_1K	= 3
+};
+
+/*
+ * cache modes
+ */
+enum mmu_cache_modes
+{
+    CACHE_WRITETHROUGH      = 0,
+    CACHE_COPYBACK          = 1,
+    CACHE_NOCACHE_PRECISE   = 2,
+    CACHE_NOCACHE_IMPRECISE = 3
+};
+
+
+/*
+ * page flags
+ */
+#define SV_PROTECT				1
+#define SV_USER					0
+
+#define ACCESS_READ		(1 << 0)
+#define	ACCESS_WRITE	(1 << 1)
+#define ACCESS_EXECUTE	(1 << 2)
+
+/*
+ * global variables from linker script
+ */
+extern long video_tlb;
+extern long video_sbt;
+
+extern void mmu_enable(void);
+extern void mmu_init(void);
+extern int mmu_map_8k_page(uint32_t adr, uint8_t asid);
+
+#endif /* _MMU_H_ */
--- a/include/nbuf.h
+++ b/include/nbuf.h
@@ -0,0 +1,70 @@
+/*
+ * File:        nbuf.h
+ * Purpose:     Definitions for network buffer management
+ *
+ * Notes:       These routines implement a network buffer scheme
+ */
+
+#ifndef _NBUF_H_
+#define _NBUF_H_
+
+#include "bas_types.h"
+
+/*
+ * Include the Queue structure definitions
+ */
+#include "queue.h"
+
+/*
+ * Number of network buffers to use
+ */
+#define NBUF_MAX    30
+
+/*
+ * Size of each buffer in bytes
+ */
+#ifndef NBUF_SZ
+#define NBUF_SZ     2048
+#endif 
+
+/*
+ * Defines to identify all the buffer queues
+ *  - FREE must always be defined as 0
+ */
+#define NBUF_FREE       0   /* available buffers */
+#define NBUF_TX_RING    1   /* buffers in the Tx BD ring */
+#define NBUF_RX_RING    2   /* buffers in the Rx BD ring */
+#define NBUF_SCRATCH    3   /* misc */
+#define NBUF_MAXQ       4   /* total number of queueus */
+
+/* 
+ * Buffer Descriptor Format 
+ * 
+ * Fields:
+ * next     Pointer to next node in the queue
+ * data     Pointer to the data buffer
+ * offset   Index into buffer
+ * length   Remaining bytes in buffer from (data + offset)
+ */
+typedef struct
+{
+	QNODE node;
+	uint8_t *data;   
+	uint16_t offset;
+	uint16_t length;
+} NBUF;
+
+/*
+ * Functions to manipulate the network buffers.
+ */
+extern int nbuf_init(void);
+extern void nbuf_flush(void);
+extern NBUF *nbuf_alloc (void);
+extern void nbuf_free(NBUF *);
+extern NBUF *nbuf_remove(int);
+extern void nbuf_add(int, NBUF *);
+extern void nbuf_reset(void);
+extern void nbuf_debug_dump(void);
+
+
+#endif  /* _NBUF_H_ */
--- a/include/net.h
+++ b/include/net.h
@@ -0,0 +1,32 @@
+/*
+ * File:        net.h
+ * Purpose:     Network definitions and prototypes for BaS.
+ *
+ * Notes:
+ */
+
+#ifndef _NET_H
+#define _NET_H
+
+
+/*
+ * Include information and prototypes for all protocols
+ */
+#include "eth.h"
+#include "nbuf.h"
+#include "nif.h"
+#include "ip.h"
+#include "icmp.h"
+#include "arp.h"
+#include "udp.h"
+#include "tftp.h"
+
+#define TIMER_NETWORK	3		/* use GPT3 for network timers */
+#define TMR_INTC_LVL	3		/* interrupt level for network timer */
+#define TMR_INTC_PRI	0		/* interrupt priority for network timer */
+
+extern int net_init(void);
+
+
+#endif  /* _NET_H */
+
--- a/include/net_timer.h
+++ b/include/net_timer.h
@@ -0,0 +1,32 @@
+/*
+ * File:        net_timer.h
+ * Purpose:     Provide a timer use by the BaS network as a timeout
+ *              indicator
+ *
+ */
+
+#ifndef _TIMER_H_
+#define _TIMER_H_
+
+#include <bas_types.h>
+
+typedef struct
+{
+	uint8_t   ch;         /* which channel is this structure for? */
+	uint8_t   lvl;        /* Interrupt level for this channel */
+	uint8_t   pri;        /* Interrupt priority for this channel */
+	uint8_t   reference;  /* timeout indicator */
+	uint32_t  gms;        /* mode select register value */
+	uint16_t  pre;        /* prescale value */
+	uint16_t  cnt;        /* prescaled clocks for timeout */
+} NET_TIMER;
+
+
+extern bool timer_init(uint8_t, uint8_t, uint8_t);
+extern bool timer_set_secs(uint8_t ch, uint32_t secs);
+extern uint32_t timer_get_reference(uint8_t ch);
+
+/* Vector numbers for all the timer channels */
+#define TIMER_VECTOR(x)     (126-x)
+
+#endif /* _TIMER_H_ */
--- a/include/nif.h
+++ b/include/nif.h
@@ -0,0 +1,49 @@
+/*
+ * File:        nif.h
+ * Purpose:     Definition of a Network InterFace.
+ *
+ * Notes:
+ */
+
+#ifndef _NIF_H
+#define _NIF_H
+
+/* 
+ * Maximum number of supported protoocls: IP, ARP, RARP 
+ */
+#define MAX_SUP_PROTO   (3)
+
+typedef struct NIF_t
+{
+	ETH_ADDR    hwa;        /* ethernet card hardware address */
+	ETH_ADDR    broadcast;  /* broadcast address */
+	int         mtu;        /* hardware maximum transmission unit */
+	int         ch;         /* ethernet channel associated with this NIF */
+
+	struct SUP_PROTO_t
+	{
+		uint16_t  protocol;
+		void    (*handler)(struct NIF_t *, NBUF *);
+		void    *info;
+	} protocol[MAX_SUP_PROTO];
+
+	unsigned short  num_protocol;
+
+	int     (*send)(struct NIF_t *, uint8_t *, uint8_t *, uint16_t, NBUF *);
+
+	unsigned int    f_rx;
+	unsigned int    f_tx;
+	unsigned int    f_rx_err;
+	unsigned int    f_tx_err;
+	unsigned int    f_err;
+} NIF;
+
+
+extern NIF *nif_init (NIF *);
+extern int nif_protocol_exist (NIF *, uint16_t);
+extern void nif_protocol_handler (NIF *, uint16_t, NBUF *);
+extern void *nif_get_protocol_info (NIF *, uint16_t);
+extern int nif_bind_protocol (NIF *, uint16_t, void (*)(NIF *, NBUF *), void *);
+
+
+#endif /* _NIF_H */
--- a/include/ohci.h
+++ b/include/ohci.h
@@ -7,7 +7,10 @@
 * usb-ohci.h
 */
 
-static int cc_to_error[16] = {
+#define USB_OHCI_MAX_ROOT_PORTS	4
+
+static int cc_to_error[16] =
+{

 /* mapping of the OHCI CC status to error codes */
 	/* No  Error  */	       0,
@@ -28,7 +31,9 @@ static int cc_to_error[16] = {
 	/* Not Access */	       -1
 };

-static const char *cc_to_string[16] = {
+#ifdef DEBUG_OHCI
+static const char *cc_to_string[16] =
+{
 	"No Error",
 	"CRC: Last data packet from endpoint contained a CRC error.",
 	"BITSTUFFING:\r\nLast data packet from endpoint contained a bit stuffing violation",
@@ -59,6 +64,7 @@ static const char *cc_to_string[16] = {
 	"NOT ACCESSED:\r\nThis code is set by software before the TD is placed\r\n" \
 		     "on a list to be processed by the HC.(2)",
 };
+#endif /* DEBUG_OHCI */

 /* ED States */

@@ -69,25 +75,26 @@ static const char *cc_to_string[16] = {
 #define ED_URB_DEL	0x08

 /* usb_ohci_ed */
-struct ed {
-	__u32 hwINFO;
-	__u32 hwTailP;
-	__u32 hwHeadP;
-	__u32 hwNextED;
+struct ed
+{
+	uint32_t hwINFO;
+	uint32_t hwTailP;
+	uint32_t hwHeadP;
+	uint32_t hwNextED;

 	struct ed *ed_prev;
-	__u8 int_period;
-	__u8 int_branch;
-	__u8 int_load;
-	__u8 int_interval;
-	__u8 state;
-	__u8 type;
-	__u16 last_iso;
+	uint8_t int_period;
+	uint8_t int_branch;
+	uint8_t int_load;
+	uint8_t int_interval;
+	uint8_t state;
+	uint8_t type;
+	uint16_t last_iso;
 	struct ed *ed_rm_list;

 	struct usb_device *usb_dev;
 	void *purb;
-	__u32 unused[2];
+	uint32_t unused[2];
 } __attribute__((aligned(16)));
 typedef struct ed ed_t;

@@ -130,22 +137,23 @@ typedef struct ed ed_t;

 #define MAXPSW 1

-struct td {
-	__u32 hwINFO;
-	__u32 hwCBP;		/* Current Buffer Pointer */
-	__u32 hwNextTD;		/* Next TD Pointer */
-	__u32 hwBE;		/* Memory Buffer End Pointer */
+struct td
+{
+	uint32_t hwINFO;
+	uint32_t hwCBP;		/* Current Buffer Pointer */
+	uint32_t hwNextTD;		/* Next TD Pointer */
+	uint32_t hwBE;		/* Memory Buffer End Pointer */

-	__u16 hwPSW[MAXPSW];
-	__u8 unused;
-	__u8 index;
+	uint16_t hwPSW[MAXPSW];
+	uint8_t unused;
+	uint8_t index;
 	struct ed *ed;
 	struct td *next_dl_td;
 	struct usb_device *usb_dev;
 	int transfer_len;
-	__u32 data;
+	uint32_t data;

-	__u32 unused2[2];
+	uint32_t unused2[2];
 } __attribute__((aligned(32)));
 typedef struct td td_t;

@@ -158,60 +166,55 @@ typedef struct td td_t;
 */

 #define NUM_INTS 32	/* part of the OHCI standard */
-struct ohci_hcca {
-	__u32	int_table[NUM_INTS];	/* Interrupt ED table */
+struct ohci_hcca
+{
+	uint32_t	int_table[NUM_INTS];	/* Interrupt ED table */
 #if defined(CONFIG_MPC5200)
-	__u16	pad1;			/* set to 0 on each frame_no change */
-	__u16	frame_no;		/* current frame number */
+	uint16_t	pad1;			/* set to 0 on each frame_no change */
+	uint16_t	frame_no;		/* current frame number */
 #else
-	__u16	frame_no;		/* current frame number */
-	__u16	pad1;			/* set to 0 on each frame_no change */
+	uint16_t	frame_no;		/* current frame number */
+	uint16_t	pad1;			/* set to 0 on each frame_no change */
 #endif
-	__u32	done_head;		/* info returned for an interrupt */
-	u8		reserved_for_hc[116];
+	uint32_t	done_head;		/* info returned for an interrupt */
+	uint8_t		reserved_for_hc[116];
 } __attribute__((aligned(256)));

-
-/*
- * Maximum number of root hub ports.
- */
-#ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
-# error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!"
-#endif
-
 /*
 * This is the structure of the OHCI controller's memory mapped I/O
 * region.  This is Memory Mapped I/O.	You must use the readl() and
 * writel() macros defined in asm/io.h to access these!!
 */
-struct ohci_regs {
+struct ohci_regs
+{
 	/* control and status registers */
-	__u32	revision;
-	__u32	control;
-	__u32	cmdstatus;
-	__u32	intrstatus;
-	__u32	intrenable;
-	__u32	intrdisable;
+	uint32_t	revision;
+	uint32_t	control;
+	uint32_t	cmdstatus;
+	uint32_t	intrstatus;
+	uint32_t	intrenable;
+	uint32_t	intrdisable;
 	/* memory pointers */
-	__u32	hcca;
-	__u32	ed_periodcurrent;
-	__u32	ed_controlhead;
-	__u32	ed_controlcurrent;
-	__u32	ed_bulkhead;
-	__u32	ed_bulkcurrent;
-	__u32	donehead;
+	uint32_t	hcca;
+	uint32_t	ed_periodcurrent;
+	uint32_t	ed_controlhead;
+	uint32_t	ed_controlcurrent;
+	uint32_t	ed_bulkhead;
+	uint32_t	ed_bulkcurrent;
+	uint32_t	donehead;
 	/* frame counters */
-	__u32	fminterval;
-	__u32	fmremaining;
-	__u32	fmnumber;
-	__u32	periodicstart;
-	__u32	lsthresh;
+	uint32_t	fminterval;
+	uint32_t	fmremaining;
+	uint32_t	fmnumber;
+	uint32_t	periodicstart;
+	uint32_t	lsthresh;
 	/* Root hub ports */
-	struct	ohci_roothub_regs {
-		__u32	a;
-		__u32	b;
-		__u32	status;
-		__u32	portstatus[CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS];
+    struct	ohci_roothub_regs
+    {
+		uint32_t	a;
+		uint32_t	b;
+		uint32_t	status;
+		uint32_t	portstatus[USB_OHCI_MAX_ROOT_PORTS];
 	} roothub;
 } __attribute__((aligned(32)));

@@ -267,7 +270,8 @@ struct ohci_regs {


 /* Virtual Root HUB */
-struct virt_root_hub {
+struct virt_root_hub
+{
 	int devnum; /* Address of Root Hub endpoint */
 	void *dev;  /* was urb */
 	void *int_addr;
@@ -371,11 +375,11 @@ struct virt_root_hub {
 typedef struct
 {
 	ed_t *ed;
-	__u16 length;	/* number of tds associated with this request */
-	__u16 td_cnt;	/* number of tds already serviced */
+	uint16_t length;	/* number of tds associated with this request */
+	uint16_t td_cnt;	/* number of tds already serviced */
 	struct usb_device *dev;
 	int   state;
-	unsigned long pipe;
+	uint32_t pipe;
 	void *transfer_buffer;
 	int transfer_buffer_length;
 	int interval;
@@ -387,7 +391,8 @@ typedef struct

 #define NUM_EDS 8		/* num of preallocated endpoint descriptors */

-struct ohci_device {
+struct ohci_device
+{
 	ed_t	ed[NUM_EDS];
 	int ed_cnt;
 };
@@ -399,7 +404,8 @@ struct ohci_device {
 * a subset of what the full implementation needs. (Linus)
 */

-typedef struct ohci {
+typedef struct ohci
+{
 	/* ------- common part -------- */
 	long handle;              /* PCI BIOS */
 	const struct pci_device_id *ent;
@@ -420,10 +426,10 @@ typedef struct ohci {
 	int disabled;			/* e.g. got a UE, we're hung */
 	int sleeping;
 #define OHCI_FLAGS_NEC 0x80000000
-	unsigned long flags;		/* for HC bugs */
+	uint32_t flags;		/* for HC bugs */

-	unsigned long offset;
-	unsigned long dma_offset;
+	uint32_t offset;
+	uint32_t dma_offset;
 	struct ohci_regs *regs; /* OHCI controller's memory */

 	int ohci_int_load[32];	 /* load of the 32 Interrupt Chains (for load balancing)*/
@@ -431,7 +437,8 @@ typedef struct ohci {
 	ed_t *ed_bulktail;	 /* last endpoint of bulk list */
 	ed_t *ed_controltail;	 /* last endpoint of control list */
 	int intrstatus;
-	__u32 hc_control;		/* copy of the hc control reg */
+	uint32_t hc_control;		/* copy of the hc control reg */
+	uint32_t ndp;          /* copy NDP from roothub_a */
 	struct virt_root_hub rh;

 	const char *slot_name;
@@ -444,33 +451,12 @@ typedef struct ohci {
 /* endpoint */
 static int ep_link(ohci_t * ohci, ed_t * ed);
 static int ep_unlink(ohci_t * ohci, ed_t * ed);
-static ed_t * ep_add_ed(ohci_t * ohci, struct usb_device * usb_dev, unsigned long pipe, int interval, int load);
+static ed_t * ep_add_ed(ohci_t * ohci, struct usb_device * usb_dev, uint32_t pipe, int interval, int load);

-/*-------------------------------------------------------------------------*/

 /* we need more TDs than EDs */
 #define NUM_TD 64

-/* pointers to aligned storage */
-td_t *ptd;
-
-/* TDs ... */
-static inline struct td *td_alloc(struct usb_device *usb_dev)
-{
-	int i;
-	struct td	*td;
-	td = NULL;
-	for(i = 0; i < NUM_TD; i++)
-	{
-		if(ptd[i].usb_dev == NULL)
-		{
-			td = &ptd[i];
-			td->usb_dev = usb_dev;
-			break;
-		}
-	}
-	return td;
-}

 static inline void ed_free(struct ed *ed)
 {
--- a/include/part.h
+++ b/include/part.h
@@ -26,7 +26,8 @@
 typedef unsigned long long uint64_t;
 typedef unsigned long lbaint_t;

-typedef struct block_dev_desc {
+typedef struct block_dev_desc
+{
 	int		if_type;	/* type of the interface */
 	int		dev;		/* device number */
 	unsigned char	part_type;	/* partition type */
--- a/include/pci.h
+++ b/include/pci.h
@@ -0,0 +1,345 @@
+#ifndef _PCI_H_
+#define _PCI_H_
+
+/*
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 26.02.2013
+ *      Author: Markus Fröschle
+ */
+
+#include <bas_types.h>
+#include "util.h" 	/* for swpX() */
+
+#define	 PCI_MEMORY_OFFSET	(0x80000000)
+#define	 PCI_MEMORY_SIZE	(0x40000000)	/* 1 GByte PCI memory window */
+#define	 PCI_IO_OFFSET		(0xD0000000)
+#define	 PCI_IO_SIZE		(0x10000000)	/* 128 MByte PCI I/O window */
+
+/*
+ * Note: the byte offsets are in little endian format, so you can't use them
+ * on byteswapped (Motorola format) values!
+ */
+#define PCIIDR                0x00   /* PCI Configuration ID Register       */
+#define PCICSR                0x04   /* PCI Command/Status Register         */
+#define PCICR                 0x04   /* PCI Command Register                */
+#define PCISR                 0x06   /* PCI Status Register                 */
+#define PCIREV                0x08   /* PCI Revision ID Register            */
+#define PCICCR                0x0B   /* PCI Class Code Register             */
+#define PCICLSR               0x0C   /* PCI Cache Line Size Register        */
+#define PCILTR                0x0D   /* PCI Latency Timer Register          */
+#define PCIHTR                0x0E   /* PCI Header Type Register            */
+#define PCIBISTR              0x0F   /* PCI Build-In Self Test Register     */
+#define PCIBAR0               0x10   /* PCI Base Address Register for Memory
+										Accesses to Local, Runtime, and DMA */
+#define PCIBAR1               0x14   /* PCI Base Address Register for I/O
+										Accesses to Local, Runtime, and DMA */
+#define PCIBAR2               0x18   /* PCI Base Address Register for Memory
+										Accesses to Local Address Space 0   */
+#define PCIBAR3               0x1C   /* PCI Base Address Register for Memory
+										Accesses to Local Address Space 1   */
+#define PCIBAR4               0x20   /* PCI Base Address Register, reserved */
+#define PCIBAR5               0x24   /* PCI Base Address Register, reserved */
+#define PCICIS                0x28   /* PCI Cardbus CIS Pointer, not support*/
+#define PCISVID               0x2E   /* PCI Subsystem Vendor ID             */
+#define PCISID                0x2E   /* PCI Subsystem ID                    */
+#define PCIERBAR              0x30   /* PCI Expansion ROM Base Register     */
+#define CAP_PTR               0x34   /* New Capability Pointer              */
+#define PCIILR                0x3C   /* PCI Interrupt Line Register         */
+#define PCIIPR                0x3D   /* PCI Interrupt Pin Register          */
+#define PCIMGR                0x3E   /* PCI Min_Gnt Register                */
+#define PCIMLR                0x3F   /* PCI Max_Lat Register                */
+#define PMCAPID               0x40   /* Power Management Capability ID      */
+#define PMNEXT                0x41   /* Power Management Next Capability
+										Pointer                             */
+#define PMC                   0x42   /* Power Management Capabilities       */
+#define PMCSR                 0x44   /* Power Management Control/Status     */
+#define PMCSR_BSE             0x46   /* PMCSR Bridge Support Extensions     */
+#define PMDATA                0x47   /* Power Management Data               */
+#define HS_CNTL               0x48   /* Hot Swap Control                    */
+#define HS_NEXT               0x49   /* Hot Swap Next Capability Pointer    */
+#define HS_CSR                0x4A   /* Hot Swap Control/Status             */
+#define PVPDCNTL              0x4C   /* PCI Vital Product Data Control      */
+#define PVPD_NEXT             0x4D   /* PCI Vital Product Data Next
+										Capability Pointer                  */
+#define PVPDAD                0x4E   /* PCI Vital Product Data Address      */
+#define PVPDATA               0x50   /* PCI VPD Data                        */
+
+/*
+ * bit definitions for PCICSR lower half (Command Register)
+ */
+#define	PCICSR_IO			(1 << 0)	/* if set: device responds to I/O space accesses */
+#define	PCICSR_MEMORY		(1 << 1)	/* if set: device responds to memory space accesses */
+#define PCICSR_MASTER		(1 << 2)	/* if set: device is master */
+#define PCICSR_SPECIAL		(1 << 3)	/* if set: device reacts on special cycles */
+#define PCICSR_MEMWI		(1 << 4)	/* if set: device deals with memory write and invalidate */
+#define	PCICSR_VGA_SNOOP	(1 << 5)	/* if set: capable of palette snoop */
+#define PCICSR_PERR			(1 << 6)	/* if set: reacts to parity errors */
+#define PCICSR_STEPPING		(1 << 7)	/* if set: stepping enabled */
+#define PCICSR_SERR			(1 << 8)	/* if set: SERR pin enabled */
+#define PCICSR_FAST_BTOB_E	(1 << 9)	/* if set: fast back-to-back enabled */
+/*
+ * bit definitions for PCICSR upper half (Status Register)
+ */
+#define PCICSR_66MHZ		(1 << 5)	/* 66 MHz capable */
+#define PCICSR_UDF			(1 << 6)	/* UDF supported */
+#define PCICSR_FAST_BTOB	(1 << 7)	/* Fast back-to-back enabled */
+#define PCICSR_DPARITY_ERROR	(1 << 8)	/* data parity error detected */
+
+#define PCICSR_T_ABORT_S	(1 << 11)	/* target abort signaled */
+#define PCICSR_T_ABORT_R	(1 << 12)	/* target abort received */
+#define PCICSR_M_ABORT_R	(1 << 13)	/* master abort received */
+#define PCICSR_S_ERROR_S	(1 << 14)	/* system error signaled */
+#define PCICSR_PARITY_ERR	(1 << 15)	/* data parity error */
+
+/* Header type 1 (PCI-to-PCI bridges) */
+#define PCI_PRIMARY_BUS        0x18  /* Primary bus number */
+#define PCI_SECONDARY_BUS      0x19  /* Secondary bus number */
+#define PCI_SUBORDINATE_BUS    0x1A  /* Highest bus number behind the bridge */
+#define PCI_SEC_LATENCY_TIMER  0x1B  /* Latency timer for secondary interface */
+#define PCI_IO_BASE            0x1C  /* I/O range behind the bridge */
+#define PCI_IO_LIMIT           0x1D
+#define PCI_SEC_STATUS         0x1E  /* Secondary status register, only bit 14 used */
+#define PCI_MEMORY_BASE        0x20  /* Memory range behind */
+#define PCI_MEMORY_LIMIT       0x22
+#define PCI_PREF_MEMORY_BASE   0x24  /* Prefetchable memory range behind */
+#define PCI_PREF_MEMORY_LIMIT  0x26
+#define PCI_PREF_BASE_UPPER32  0x28  /* Upper half of prefetchable memory range */
+#define PCI_PREF_LIMIT_UPPER32 0x2C
+#define PCI_IO_BASE_UPPER16    0x30  /* Upper half of I/O addresses */
+#define PCI_IO_LIMIT_UPPER16   0x32
+#define PCI_BRIDGE_CONTROL     0x3E  /* Bridge Control */
+
+struct pci_rd          /* structure of resource descriptor    */
+{
+	unsigned short next;               /* length of the following structure   */
+	unsigned short flags;              /* type of resource and misc. flags    */
+	unsigned long start;               /* start-address of resource           */
+	unsigned long length;              /* length of resource                  */
+	unsigned long offset;              /* offset PCI to phys. CPU Address     */
+	unsigned long dmaoffset;           /* offset for DMA-transfers            */
+} __attribute__ ((packed));
+
+typedef struct                       /* structure of address conversion     */
+{
+	unsigned long adr;                 /* calculated address (CPU<->PCI)      */
+	unsigned long len;                 /* length of memory range              */
+} PCI_CONV_ADR;
+
+/******************************************************************************/
+/*                          PCI-BIOS Error Codes                              */
+/******************************************************************************/
+#define PCI_SUCCESSFUL            0  /* everything's fine         */
+#define PCI_FUNC_NOT_SUPPORTED   -2  /* function not supported    */
+#define PCI_BAD_VENDOR_ID        -3  /* wrong Vendor ID           */
+#define PCI_DEVICE_NOT_FOUND     -4  /* PCI-Device not found      */
+#define PCI_BAD_REGISTER_NUMBER  -5  /* wrong register number     */
+#define PCI_SET_FAILED           -6  /* reserved for later use    */
+#define PCI_BUFFER_TOO_SMALL     -7  /* reserved for later use    */
+#define PCI_GENERAL_ERROR        -8  /* general BIOS error code   */
+#define PCI_BAD_HANDLE           -9  /* wrong/unknown PCI-handle  */
+
+/******************************************************************************/
+/*                      Flags used in Resource-Descriptor                     */
+/******************************************************************************/
+#define FLG_IO        0x4000         /* Ressource in IO range               */
+#define FLG_ROM       0x2000         /* Expansion ROM */
+#define FLG_LAST      0x8000         /* last ressource                      */
+#define FLG_8BIT      0x0100         /* 8 bit accesses allowed              */
+#define FLG_16BIT     0x0200         /* 16 bit accesses allowed             */
+#define FLG_32BIT     0x0400         /* 32 bit accesses allowed             */
+#define FLG_ENDMASK   0x000F         /* mask for byte ordering              */
+
+/******************************************************************************/
+/*                 Values used in FLG_ENDMASK for Byte Ordering               */
+/******************************************************************************/
+#define ORD_MOTOROLA       0         /* Motorola (big endian)               */
+#define ORD_INTEL_AS       1         /* Intel (little endian), addr.swapped */
+#define ORD_INTEL_LS       2         /* Intel (little endian), lane swapped */
+#define ORD_UNKNOWN       15         /* unknown (BIOS-calls allowed only)   */
+
+/******************************************************************************/
+/*                   Status Info used in Device-Descriptor                    */
+/******************************************************************************/
+#define DEVICE_FREE        0         /* Device is not used                  */
+#define DEVICE_USED        1         /* Device is used by another driver    */
+#define DEVICE_CALLBACK    2         /* used, but driver can be cancelled   */
+#define DEVICE_AVAILABLE   3         /* used, not available                 */
+#define NO_DEVICE         -1         /* no device detected                  */
+
+/* PCI configuration space macros */
+
+/* register 0x00 macros */
+#define PCI_VENDOR_ID(i)	swpw((uint16_t)(((i) & 0xffff0000) >> 16))
+#define PCI_DEVICE_ID(i)	swpw((uint16_t) ((i) & 0xffff))
+
+/* register 0x04 macros */
+#define PCI_STATUS(i)		((i) & 0xffff)
+#define PCI_COMMAND(i)		(((i) >> 16) & 0xffff)
+
+/* register 0x08 macros */
+#define PCI_CLASS_CODE(i)	((swpl((i)) & 0xffff0000) >> 16)
+#define PCI_SUBCLASS(i)		((swpl((i)) & 0xffffff00) >> 8)
+#define PCI_PROG_IF(i)		((swpl((i)) & 0x0000ff00) >> 8)
+#define PCI_REVISION_ID(i)	((swpl((i)) & 0x000000ff))
+
+/* register 0x0c macros */
+#define PCI_BIST(i)			((swpl((i)) & 0xff000000) >> 24)
+#define PCI_HEADER_TYPE(i)	((swpl((i)) & 0x00ff0000) >> 16)
+#define PCI_LAT_TIMER(i)	((swpl((i)) & 0x0000ff00) >> 8)
+#define PCI_CACHELINE_SIZE(i)	((swpl((i)) & 0x000000ff))
+
+/* register 0x2c macros */
+#define PCI_SUBSYS_ID(i)	(((i) & 0xffff0000) >> 16)
+#define PCI_SUBSYS_VID(i)	(((i) & 0xffff))
+
+/* register 0x34 macros */
+#define PCI_CAPABILITIES(i)	((i) & 0xff)
+
+/* register 0x3c macros */
+#define PCI_MAX_LATENCY(i)	(((i) & 0xff000000) >> 24)
+#define PCI_MIN_GRANT(i)	(((i) & 0xff0000) >> 16)
+#define PCI_INTERRUPT_PIN(i)	(((i) & 0xff00) >> 8)
+#define PCI_INTERRUPT_LINE(i)	(((i)) & 0xff)
+
+#define IS_PCI_MEM_BAR(i)	((i) & 1) == 0
+#define IS_PCI_IO_BAR(i)	((i) & 1) == 1
+#define PCI_MEMBAR_TYPE(i)	(((i) & 0x6) >> 1)
+#define PCI_IOBAR_ADR(i)	(((i) & 0xfffffffc))
+#define PCI_MEMBAR_ADR(i)	(((i) & 0xfffffff0))
+
+extern void init_eport(void);
+extern void init_xlbus_arbiter(void);
+extern void init_pci(void);
+
+extern int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index);
+extern int32_t pci_find_classcode(uint32_t classcode, int index);
+
+/*
+ * match bits for pci_find_classcode()
+ */
+#define PCI_FIND_BASE_CLASS		(1 << 26)
+#define PCI_FIND_SUB_CLASS		(1 << 25)
+#define PCI_FIND_PROG_IF		(1 << 24)
+
+extern uint32_t pci_read_config_longword(int32_t handle, int offset);
+extern uint16_t pci_read_config_word(int32_t handle, int offset);
+extern uint8_t pci_read_config_byte(int32_t handle, int offset);
+
+extern int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t value);
+extern int32_t pci_write_config_word(int32_t handle, int offset, uint16_t value);
+extern int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value);
+
+extern int32_t pci_hook_interrupt(int32_t handle, void *interrupt_handler, void *parameter);
+extern int32_t pci_unhook_interrupt(int32_t handle);
+
+extern struct pci_rd *pci_get_resource(int32_t handle);
+
+/*
+ * Not implemented PCI_BIOS functions
+ */
+extern uint8_t pci_fast_read_config_byte(int32_t handle, uint16_t reg);
+extern uint16_t pci_fast_read_config_word(int32_t handle, uint16_t reg);
+extern uint32_t pci_fast_read_config_longword(int32_t handle, uint16_t reg);
+extern int32_t pci_special_cycle(uint16_t bus, uint32_t data);
+extern int32_t pci_get_routing(int32_t handle);
+extern int32_t pci_set_interrupt(int32_t handle);
+extern int32_t pci_get_card_used(int32_t handle, uint32_t *address);
+extern int32_t pci_set_card_used(int32_t handle, uint32_t *callback);
+extern int32_t pci_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address);
+extern int32_t pci_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address);
+extern int32_t pci_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address);
+extern uint8_t pci_fast_read_mem_byte(int32_t handle, uint32_t offset);
+extern uint16_t pci_fast_read_mem_word(int32_t handle, uint32_t offset);
+extern uint32_t pci_fast_read_mem_longword(int32_t handle, uint32_t offset);
+extern int32_t pci_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t pci_write_mem_word(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t pci_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val);
+extern int32_t pci_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address);
+extern int32_t pci_read_io_word(int32_t handle, uint32_t offset, uint16_t *address);
+extern int32_t pci_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address);
+extern uint8_t pci_fast_read_io_byte(int32_t handle, uint32_t offset);
+extern uint16_t pci_fast_read_io_word(int32_t handle, uint32_t offset);
+extern uint32_t pci_fast_read_io_longword(int32_t handle, uint32_t offset);
+extern int32_t pci_write_io_byte(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t pci_write_io_word(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t pci_write_io_longword(int32_t handle, uint32_t offset, uint32_t val);
+extern int32_t pci_get_machine_id(void);
+extern int32_t pci_get_pagesize(void);
+extern int32_t pci_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+extern int32_t pci_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+extern int32_t pci_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
+extern int32_t pci_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
+
+/*
+ * prototypes for PCI wrapper routines
+ */
+extern int32_t wrapper_find_pci_device(uint32_t id, uint16_t index);
+extern int32_t wrapper_find_pci_classcode(uint32_t class, uint16_t index);
+extern int32_t wrapper_read_config_byte(int32_t handle, uint16_t reg, uint8_t *address);
+extern int32_t wrapper_read_config_word(int32_t handle, uint16_t reg, uint16_t *address);
+extern int32_t wrapper_read_config_longword(int32_t handle, uint16_t reg, uint32_t *address);
+extern uint8_t wrapper_fast_read_config_byte(int32_t handle, uint16_t reg);
+extern uint16_t wrapper_fast_read_config_word(int32_t handle, uint16_t reg);
+extern uint32_t wrapper_fast_read_config_longword(int32_t handle, uint16_t reg);
+extern int32_t wrapper_write_config_byte(int32_t handle, uint16_t reg, uint16_t val);
+extern int32_t wrapper_write_config_word(int32_t handle, uint16_t reg, uint16_t val);
+extern int32_t wrapper_write_config_longword(int32_t handle, uint16_t reg, uint32_t val);
+extern int32_t wrapper_hook_interrupt(int32_t handle, uint32_t *routine, uint32_t *parameter);
+extern int32_t wrapper_unhook_interrupt(int32_t handle);
+extern int32_t wrapper_special_cycle(uint16_t bus, uint32_t data);
+extern int32_t wrapper_get_routing(int32_t handle);
+extern int32_t wrapper_set_interrupt(int32_t handle);
+extern int32_t wrapper_get_resource(int32_t handle);
+extern int32_t wrapper_get_card_used(int32_t handle, uint32_t *address);
+extern int32_t wrapper_set_card_used(int32_t handle, uint32_t *callback);
+extern int32_t wrapper_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address);
+extern int32_t wrapper_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address);
+extern int32_t wrapper_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address);
+extern uint8_t wrapper_fast_read_mem_byte(int32_t handle, uint32_t offset);
+extern uint16_t wrapper_fast_read_mem_word(int32_t handle, uint32_t offset);
+extern uint32_t wrapper_fast_read_mem_longword(int32_t handle, uint32_t offset);
+extern int32_t wrapper_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t wrapper_write_mem_word(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t wrapper_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val);
+extern int32_t wrapper_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address);
+extern int32_t wrapper_read_io_word(int32_t handle, uint32_t offset, uint16_t *address);
+extern int32_t wrapper_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address);
+extern uint8_t wrapper_fast_read_io_byte(int32_t handle, uint32_t offset);
+extern uint16_t wrapper_fast_read_io_word(int32_t handle, uint32_t offset);
+extern uint32_t wrapper_fast_read_io_longword(int32_t handle, uint32_t offset);
+extern int32_t wrapper_write_io_byte(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t wrapper_write_io_word(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t wrapper_write_io_longword(int32_t handle, uint32_t offset, uint32_t val);
+extern int32_t wrapper_get_machine_id(void);
+extern int32_t wrapper_get_pagesize(void);
+extern int32_t wrapper_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+extern int32_t wrapper_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+extern int32_t wrapper_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
+extern int32_t wrapper_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
+
+#define PCI_MK_CONF_ADDR(bus, device, function)	(MCF_PCI_PCICAR_E | \
+												((bus) << 16) | \
+												((device << 8) | \
+												(function))
+
+#define PCI_HANDLE(bus, slot, function)	(0 | ((bus & 0xff) << 10 | (slot & 0x1f) << 3 | (function & 7)))
+#define PCI_BUS_FROM_HANDLE(h)				(((h) & 0xff00) >> 10)
+#define PCI_DEVICE_FROM_HANDLE(h)			(((h) & 0xf8) >> 3)
+#define PCI_FUNCTION_FROM_HANDLE(h)			(((h) & 0x7))
+
+extern void chip_errata_135(void); /* needed in ohci-hcd.c */
+#endif /* _PCI_H_ */
--- a/include/pcixbios.h
+++ b/include/pcixbios.h
@@ -1,348 +0,0 @@
-/* TOS 4.04 Xbios PCI for the CT60 board
-*  Didier Mequignon 2005, e-mail: aniplay@wanadoo.fr
-*
-*  This library is free software; you can redistribute it and/or
-*  modify it under the terms of the GNU Lesser General Public
-*  License as published by the Free Software Foundation; either
-*  version 2.1 of the License, or (at your option) any later version.
-*
-*  This library is distributed in the hope that it will be useful,
-*  but WITHOUT ANY WARRANTY; without even the implied warranty of
-*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-*  Lesser General Public License for more details.
-*
-*  You should have received a copy of the GNU Lesser General Public
-*  License along with this library; if not, write to the Free Software
-*  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#ifndef	_CT60_XBIOS_PCI_H
-#define	_CT60_XBIOS_PCI_H
-
-#define PCIIDR                0x00   /* PCI Configuration ID Register       */
-#define PCICSR                0x04   /* PCI Command/Status Register         */
-#define PCICR                 0x04   /* PCI Command Register                */
-#define PCISR                 0x06   /* PCI Status Register                 */
-#define PCIREV                0x08   /* PCI Revision ID Register            */
-#define PCICCR                0x09   /* PCI Class Code Register             */
-#define PCICLSR               0x0C   /* PCI Cache Line Size Register        */
-#define PCILTR                0x0D   /* PCI Latency Timer Register          */
-#define PCIHTR                0x0E   /* PCI Header Type Register            */
-#define PCIBISTR              0x0F   /* PCI Build-In Self Test Register     */
-#define PCIBAR0               0x10   /* PCI Base Address Register for Memory
-                                        Accesses to Local, Runtime, and DMA */
-#define PCIBAR1               0x14   /* PCI Base Address Register for I/O
-                                        Accesses to Local, Runtime, and DMA */
-#define PCIBAR2               0x18   /* PCI Base Address Register for Memory
-                                        Accesses to Local Address Space 0   */
-#define PCIBAR3               0x1C   /* PCI Base Address Register for Memory
-                                        Accesses to Local Address Space 1   */ 
-#define PCIBAR4               0x20   /* PCI Base Address Register, reserved */
-#define PCIBAR5               0x24   /* PCI Base Address Register, reserved */
-#define PCICIS                0x28   /* PCI Cardbus CIS Pointer, not support*/
-#define PCISVID               0x2C   /* PCI Subsystem Vendor ID             */
-#define PCISID                0x2E   /* PCI Subsystem ID                    */
-#define PCIERBAR              0x30   /* PCI Expansion ROM Base Register     */
-#define CAP_PTR               0x34   /* New Capability Pointer              */
-#define PCIILR                0x3C   /* PCI Interrupt Line Register         */
-#define PCIIPR                0x3D   /* PCI Interrupt Pin Register          */
-#define PCIMGR                0x3E   /* PCI Min_Gnt Register                */
-#define PCIMLR                0x3F   /* PCI Max_Lat Register                */
-#define PMCAPID               0x40   /* Power Management Capability ID      */
-#define PMNEXT                0x41   /* Power Management Next Capability
-                                        Pointer                             */
-#define PMC                   0x42   /* Power Management Capabilities       */
-#define PMCSR                 0x44   /* Power Management Control/Status     */
-#define PMCSR_BSE             0x46   /* PMCSR Bridge Support Extensions     */
-#define PMDATA                0x47   /* Power Management Data               */
-#define HS_CNTL               0x48   /* Hot Swap Control                    */
-#define HS_NEXT               0x49   /* Hot Swap Next Capability Pointer    */
-#define HS_CSR                0x4A   /* Hot Swap Control/Status             */
-#define PVPDCNTL              0x4C   /* PCI Vital Product Data Control      */
-#define PVPD_NEXT             0x4D   /* PCI Vital Product Data Next
-                                        Capability Pointer                  */
-#define PVPDAD                0x4E   /* PCI Vital Product Data Address      */
-#define PVPDATA               0x50   /* PCI VPD Data                        */
-
-typedef struct
-{
-  unsigned long *subcookie;
-  unsigned long version;
-  long routine[45];
-} PCI_COOKIE;
-
-typedef struct                       /* structure of resource descriptor    */
-{
-	unsigned short next;               /* length of the following structure   */
-	unsigned short flags;              /* type of resource and misc. flags    */
-	unsigned long start;               /* start-address of resource           */
-	unsigned long length;              /* length of resource                  */
-	unsigned long offset;              /* offset PCI to phys. CPU Address     */
-	unsigned long dmaoffset;           /* offset for DMA-transfers            */
-} PCI_RSC_DESC;
-
-typedef struct                       /* structure of address conversion     */
-{
-	unsigned long adr;                 /* calculated address (CPU<->PCI)      */
-	unsigned long len;                 /* length of memory range              */
-} PCI_CONV_ADR;
-
-/******************************************************************************/
-/*                          PCI-BIOS Error Codes                              */
-/******************************************************************************/
-#define PCI_SUCCESSFUL            0  /* everything's fine         */
-#define PCI_FUNC_NOT_SUPPORTED   -2  /* function not supported    */
-#define PCI_BAD_VENDOR_ID        -3  /* wrong Vendor ID           */
-#define PCI_DEVICE_NOT_FOUND     -4  /* PCI-Device not found      */
-#define PCI_BAD_REGISTER_NUMBER  -5  /* wrong register number     */
-#define PCI_SET_FAILED           -6  /* reserved for later use    */
-#define PCI_BUFFER_TOO_SMALL     -7  /* reserved for later use    */
-#define PCI_GENERAL_ERROR        -8  /* general BIOS error code   */
-#define PCI_BAD_HANDLE           -9  /* wrong/unknown PCI-handle  */
-
-/******************************************************************************/
-/*                      Flags used in Resource-Descriptor                     */
-/******************************************************************************/
-#define FLG_IO        0x4000         /* Ressource in IO range               */
-#define FLG_ROM       0x2000         /* Expansion ROM */
-#define FLG_LAST      0x8000         /* last ressource                      */
-#define FLG_8BIT      0x0100         /* 8 bit accesses allowed              */
-#define FLG_16BIT     0x0200         /* 16 bit accesses allowed             */
-#define FLG_32BIT     0x0400         /* 32 bit accesses allowed             */
-#define FLG_ENDMASK   0x000F         /* mask for byte ordering              */
-
-/******************************************************************************/
-/*                 Values used in FLG_ENDMASK for Byte Ordering               */
-/******************************************************************************/
-#define ORD_MOTOROLA       0         /* Motorola (big endian)               */
-#define ORD_INTEL_AS       1         /* Intel (little endian), addr.swapped */
-#define ORD_INTEL_LS       2         /* Intel (little endian), lane swapped */
-#define ORD_UNKNOWN       15         /* unknown (BIOS-calls allowed only)   */
-
-/******************************************************************************/
-/*                   Status Info used in Device-Descriptor                    */
-/******************************************************************************/
-#define DEVICE_FREE        0         /* Device is not used                  */
-#define DEVICE_USED        1         /* Device is used by another driver    */
-#define DEVICE_CALLBACK    2         /* used, but driver can be cancelled   */
-#define DEVICE_AVAILABLE   3         /* used, not available                 */
-#define NO_DEVICE         -1         /* no device detected                  */
-
-/******************************************************************************/
-/*                            Callback-Routine                                */
-/******************************************************************************/
- #define GET_DRIVER_ID      0        /* CB-Routine 0: Get Driver ID         */
- #define REMOVE_DRIVER      1        /* CB-Routine 1: Remove Driver         */
-
-/******************************************************************************/
-/*                              Functions                                     */
-/******************************************************************************/
-#ifndef OSBIND_CLOBBER_LIST
-#define OSBIND_CLOBBER_LIST "d0", "d1", "d2", "a0", "a1", "a2", "memory"
-#endif
-
-#ifndef trap_14_wlw
-#define trap_14_wlw(n, a, b)	\
-__extension__	\
-({	\
-	register long retvalue __asm__("d0");	\
-	long  _a = (long) (a);	\
-	short _b = (short) (b);	\
-	\
-	__asm__ volatile (	\
-		"movw	%3,sp@-\n\t"	\
-		"movl	%2,sp@-\n\t"	\
-		"movw	%1,sp@-\n\t"	\
-		"trap	#14\n\t"	\
-		"lea	sp@(8),sp"	\
-		: "=r"(retvalue)	\
-		: "g"(n), "r"(_a), "r"(_b)	\
-		: OSBIND_CLOBBER_LIST	\
-	);	\
-	retvalue;	\
-})
-#endif
-#ifndef trap_14_wll
-#define trap_14_wll(n, a, b)	\
-__extension__	\
-({	\
-	register long retvalue __asm__("d0");	\
-	long _a = (long) (a);	\
-	long _b = (long) (b);	\
-	\
-	__asm__ volatile (	\
-		"movl	%3,sp@-\n\t"	\
-		"movl	%2,sp@-\n\t"	\
-		"movw	%1,sp@-\n\t"	\
-		"trap	#14\n\t"	\
-		"lea	sp@(10),sp"	\
-		: "=r"(retvalue)	\
-		: "g"(n), "r"(_a), "r"(_b)	\
-		: OSBIND_CLOBBER_LIST	\
-	);	\
-	retvalue;	\
-})
-#endif
-#ifndef trap_14_wlww
-#define trap_14_wlww(n, a, b, c)	\
-__extension__	\
-({	\
-	register long retvalue __asm__("d0");	\
-	long  _a = (long) (a);	\
-	short _b = (short) (b);	\
-	short  _c = (short) (c);	\
-	\
-	__asm__ volatile (	\
-		"movl	%4,sp@-\n\t"	\
-		"movw	%3,sp@-\n\t"	\
-		"movw	%2,sp@-\n\t"	\
-		"movw	%1,sp@-\n\t"	\
-		"trap	#14\n\t"	\
-		"lea	sp@(10),sp"	\
-		: "=r"(retvalue)	\
-		: "g"(n), "r"(_a), "r"(_b), "r"(_c)	\
-		: OSBIND_CLOBBER_LIST	\
-	);	\
-	retvalue;	\
-})
-#endif
-#ifndef trap_14_wlwl
-#define trap_14_wlwl(n, a, b, c)	\
-__extension__	\
-({	\
-	register long retvalue __asm__("d0");	\
-	long  _a = (long) (a);	\
-	short _b = (short) (b);	\
-	long  _c = (long) (c);	\
-	\
-	__asm__ volatile (	\
-		"movl	%4,sp@-\n\t"	\
-		"movw	%3,sp@-\n\t"	\
-		"movl	%2,sp@-\n\t"	\
-		"movw	%1,sp@-\n\t"	\
-		"trap	#14\n\t"	\
-		"lea	sp@(12),sp"	\
-		: "=r"(retvalue)	\
-		: "g"(n), "r"(_a), "r"(_b), "r"(_c)	\
-		: OSBIND_CLOBBER_LIST	\
-	);	\
-	retvalue;	\
-})
-#endif
-#ifndef trap_14_wlll
-#define trap_14_wlll(n, a, b, c)	\
-__extension__	\
-({	\
-	register long retvalue __asm__("d0");	\
-	long  _a = (long) (a);	\
-	long  _b = (long) (b);	\
-	long  _c = (long) (c);	\
-	\
-	__asm__ volatile (	\
-		"movl	%4,sp@-\n\t"	\
-		"movl	%3,sp@-\n\t"	\
-		"movl	%2,sp@-\n\t"	\
-		"movw	%1,sp@-\n\t"	\
-		"trap	#14\n\t"	\
-		"lea	sp@(14),sp"	\
-		: "=r"(retvalue)	\
-		: "g"(n), "r"(_a), "r"(_b), "r"(_c)	\
-		: OSBIND_CLOBBER_LIST	\
-	);	\
-	retvalue;	\
-})
-#endif
-
-#define find_pci_device(id,index) (long)trap_14_wlw((short)(300),(unsigned long)(id),(unsigned short)(index))
-#define find_pci_classcode(classcode,index) (long)trap_14_wlw((short)(301),(unsigned long)(classcode),(unsigned short)(index))
-#define read_config_byte(handle,reg,address) (long)trap_14_wlwl((short)(302),(long)(handle),(unsigned short)(reg),(unsigned char *)(address))
-#define read_config_word(handle,reg,address) (long)trap_14_wlwl((short)(303),(long)(handle),(unsigned short)(reg),(unsigned short *)(address))
-#define read_config_longword(handle,reg,address) (long)trap_14_wlwl((short)(304),(long)(handle),(unsigned short)(reg),(unsigned long *)(address))
-#define fast_read_config_byte(handle,reg) (unsigned char)trap_14_wlw((short)(305),(long)(handle),(unsigned short)(reg))
-#define fast_read_config_word(handle,reg) (unsigned short)trap_14_wlw((short)(306),(long)(handle),(unsigned short)(reg))
-#define fast_read_config_longword(handle,reg) (unsigned long)trap_14_wlw((short)(307),(long)(handle),(unsigned short)(reg))
-#define write_config_byte(handle,reg,data) (long)trap_14_wlww((short)(308),(long)(handle),(unsigned short)(reg),(unsigned short)(data))
-#define write_config_word(handle,reg,data) (long)trap_14_wlww((short)(309),(long)(handle),(unsigned short)(reg),(unsigned short)(data))
-#define write_config_longword(handle,reg,data) (long)trap_14_wlwl((short)(310),(long)(handle),(unsigned short)(reg),(unsigned long)(data))
-#define hook_interrupt(handle,routine,parameter) (long)trap_14_wlll((short)(311),(long)(handle),(unsigned long *)(routine),(unsigned long *)(parameter))
-#define unhook_interrupt(handle) (long)trap_14_wl((short)(312),(long)(handle))
-#define special_cycle(bus_number,special_cycle) (long)trap_14_wwl((short)(313),(unsigned short)(bus_number),(unsigned long)(special_cycle))
-#define get_routing(handle) (long)trap_14_wl((short)(314),(long)(handle))
-#define set_interrupt(handle,mode) (long)trap_14_wlw((short)(315),(long)(handle),(short)(mode))
-#define get_resource(handle) (long)trap_14_wl((short)(316),(long)(handle))
-#define get_card_used(handle,callback) (long)trap_14_wll((short)(317),(long)(handle),(long *)(address))
-#define set_card_used(handle,callback) (long)trap_14_wll((short)(318),(long)(handle),(long *)(callback))
-#define read_mem_byte(handle,offset,address) (long)trap_14_wlll((short)(319),(long)(handle),(unsigned long)(offset),(unsigned char *)(address))
-#define read_mem_word(handle,offset,address) (long)trap_14_wlll((short)(320),(unsigned long)(offset),(unsigned short *)(address))
-#define read_mem_longword(handle,offset,address) (long)trap_14_wlll((short)(321),(unsigned long)(offset),(unsigned long *)(address))
-#define fast_read_mem_byte(handle,offset) (unsigned char)trap_14_wll((short)(322),(long)(handle),(unsigned long)(offset))
-#define fast_read_mem_word(handle,offset) (unsigned short)trap_14_wll((short)(323),(long)(handle),(unsigned long)(offset))
-#define fast_read_mem_longword(handle,offset) (unsigned long)trap_14_wll((short)(324),(long)(handle),(unsigned long)(offset))
-#define write_mem_byte(handle,offset,data) (long)trap_14_wllw((short)(325),(long)(handle),(unsigned long)(offset),(unsigned short)(data))
-#define write_mem_word(handle,offset,data) (long)trap_14_wllw((short)(326),(long)(handle),(unsigned long)(offset),(unsigned short)(data))
-#define write_mem_longword(handle,offset,data) (long)trap_14_wlll((short)(327),(long)(handle),(unsigned long)(offset),(unsigned long)(data))
-#define read_io_byte(handle,offset,address) (long)trap_14_wlll((short)(328),(long)(handle),(unsigned long)(offset),(unsigned char *)(address))
-#define read_io_word(handle,offset,address) (long)trap_14_wlll((short)(329),(long)(handle),(unsigned long)(offset),(unsigned short *)(address))
-#define read_io_longword(handle,offset,address) (long)trap_14_wlll((short)(330),(long)(handle),(unsigned long)(offset),(unsigned long *)(address))
-#define fast_read_io_byte(handle,offset) (unsigned char)trap_14_wll((short)(331),(long)(handle),(unsigned long)(offset))
-#define fast_read_io_word(handle,offset) (unsigned short)trap_14_wll((short)(332),(long)(handle),(unsigned long)(offset))
-#define fast_read_io_longword(handle,offset) (unsigned long)trap_14_wll((short)(333),(long)(handle),(unsigned long)(offset))
-#define write_io_byte(handle,offset,data) (long)trap_14_wllw((short)(334),(long)(handle),(unsigned long)(offset),(unsigned short)(data))
-#define write_io_word(handle,offset,data) (long)trap_14_wllw((short)(335),(long)(handle),(unsigned long)(offset),(unsigned short)(data))
-#define write_io_longword(handle,offset,data) (long)trap_14_wlll((short)(336),(long)(handle),(unsigned long)(offset),(unsigned long)(data))
-#define get_machine_id() (long)trap_14_w((short)(337))
-#define get_pagesize() (long)trap_14_w((short)(338))
-#define virt_to_bus(handle,address,pointer) (long)trap_14_wlll((short)(339),(long)(handle),(unsigned long)(address),(unsigned long *)(pointer))
-#define bus_to_virt(handle,address,pointer) (long)trap_14_wlll((short)(340),(long)(handle),(unsigned long)(address),(unsigned long *)(pointer))
-#define virt_to_phys(address,pointer) (long)trap_14_wll((short)(341),(unsigned long)(address),(unsigned long *)(pointer))
-#define phys_to_virt(address,pointer) (long)trap_14_wll((short)(342),(unsigned long)(address),(unsigned long *)(pointer))
-#define dma_setbuffer(pci_address,local_address,size) (long)trap_14_wlll((short)(350),(unsigned long)(pci_address),(unsigned long)(local_address),(unsigned long)(size))
-#define dma_buffoper(mode) (long)trap_14_ww((short)(351),(short)(mode))
-#define read_mailbox(mailbox,pointer)  (long)trap_14_wwl((short)(352),(short)(mailbox),(unsigned long *)(pointer))
-#define write_mailbox(mailbox,data) (long)trap_14_wwl((short)(353),(short)(mailbox),(unsigned long)(data))
-
-extern long Find_pci_device(unsigned long id, unsigned short index);
-extern long Find_pci_classcode(unsigned long class, unsigned short index);
-extern long Read_config_byte(long handle, unsigned short reg, unsigned char *address);
-extern long Read_config_word(long handle, unsigned short reg, unsigned short *address);
-extern long Read_config_longword(long handle, unsigned short reg, unsigned long *address);
-extern unsigned char Fast_read_config_byte(long handle, unsigned short reg);
-extern unsigned short Fast_read_config_word(long handle, unsigned short reg);
-extern unsigned long Fast_read_config_longword(long handle, unsigned short reg);
-extern long Write_config_byte(long handle, unsigned short reg, unsigned short val);
-extern long Write_config_word(long handle, unsigned short reg, unsigned short val);
-extern long Write_config_longword(long handle, unsigned short reg, unsigned long val);
-extern long Hook_interrupt(long handle, unsigned long *routine, unsigned long *parameter);
-extern long Unhook_interrupt(long handle);
-extern long Special_cycle(unsigned short bus, unsigned long data);
-extern long Get_routing(long handle);
-extern long Set_interrupt(long handle);
-extern long Get_resource(long handle);
-extern long Get_card_used(long handle, unsigned long *address);
-extern long Set_card_used(long handle, unsigned long *callback);
-extern long Read_mem_byte(long handle, unsigned long offset, unsigned char *address);
-extern long Read_mem_word(long handle, unsigned long offset, unsigned short *address);
-extern long Read_mem_longword(long handle, unsigned long offset, unsigned long *address);
-extern unsigned char Fast_read_mem_byte(long handle, unsigned long offset);
-extern unsigned short Fast_read_mem_word(long handle, unsigned long offset);
-extern unsigned long Fast_read_mem_longword(long handle, unsigned long offset);
-extern long Write_mem_byte(long handle, unsigned long offset, unsigned short val);
-extern long Write_mem_word(long handle, unsigned long offset, unsigned short val);
-extern long Write_mem_longword(long handle, unsigned long offset, unsigned long val);
-extern long Read_io_byte(long handle, unsigned long offset, unsigned char *address);
-extern long Read_io_word(long handle, unsigned long offset, unsigned short *address);
-extern long Read_io_longword(long handle, unsigned long offset, unsigned long *address);
-extern unsigned char Fast_read_io_byte(long handle, unsigned long offset);
-extern unsigned short Fast_read_io_word(long handle, unsigned long offset);
-extern unsigned long Fast_read_io_longword(long handle, unsigned long offset);
-extern long Write_io_byte(long handle, unsigned long offset, unsigned short val);
-extern long Write_io_word(long handle, unsigned long offset, unsigned short val);
-extern long Write_io_longword(long handle, unsigned long offset, unsigned long val);
-extern long Get_machine_id(void);
-extern long Get_pagesize(void);
-extern long Virt_to_bus(long handle, unsigned long address, PCI_CONV_ADR *pointer);
-extern long Bus_to_virt(long handle, unsigned long address, PCI_CONV_ADR *pointer);
-extern long Virt_to_phys(unsigned long address, PCI_CONV_ADR *pointer);
-extern long Phys_to_virt(unsigned long address, PCI_CONV_ADR *pointer);
-
-#endif
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