consistantly use bas_types.h instead of standard headers

updated comments
added function to flush only a portion of the caches
2014-09-25 06:24:55 +00:00 · 2014-09-25 05:54:26 +00:00 · 2014-09-24 16:02:20 +00:00 · 2014-09-21 13:30:55 +00:00 · 2014-09-19 17:41:00 +00:00 · 2014-09-19 06:02:16 +00:00
117 changed files with 13269 additions and 3553 deletions
--- a/.gdbinit
+++ b/.gdbinit
@@ -1,7 +1,8 @@
 #set disassemble-next-line on
 define tr
-	!killall m68k-bdm-gdbserver
+	#!killall m68k-bdm-gdbserver
 	target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3
+	#target remote localhost:1234
 	#target remote | m68k-bdm-gdbserver pipe /dev/tblcf3
 	#target dbug /dev/ttyS0
 	#monitor bdm-reset
--- a/BaS_gcc.files
+++ b/BaS_gcc.files
@@ -229,3 +229,43 @@ COPYING.LESSER
 dump.bdm
 mcf5474.gdb
 Makefile
+tos/jtagwait/Makefile
+tos/jtagwait/sources/jtagwait.c
+tos/jtagwait/include/driver_vec.h
+tos/bascook/Makefile
+tos/mcdcook/sources/bascook.c
+tos/jtagwait/include/bas_printf.h
+tos/jtagwait/include/bas_string.h
+tos/jtagwait/include/MCF5475_CLOCK.h
+tos/jtagwait/include/MCF5475_CTM.h
+tos/jtagwait/include/MCF5475_DMA.h
+tos/jtagwait/include/MCF5475_DSPI.h
+tos/jtagwait/include/MCF5475_EPORT.h
+tos/jtagwait/include/MCF5475_FBCS.h
+tos/jtagwait/include/MCF5475_FEC.h
+tos/jtagwait/include/MCF5475_GPIO.h
+tos/jtagwait/include/MCF5475_GPT.h
+tos/jtagwait/include/MCF5475_I2C.h
+tos/jtagwait/include/MCF5475_INTC.h
+tos/jtagwait/include/MCF5475_MMU.h
+tos/jtagwait/include/MCF5475_PAD.h
+tos/jtagwait/include/MCF5475_PCI.h
+tos/jtagwait/include/MCF5475_PCIARB.h
+tos/jtagwait/include/MCF5475_PSC.h
+tos/jtagwait/include/MCF5475_SDRAMC.h
+tos/jtagwait/include/MCF5475_SEC.h
+tos/jtagwait/include/MCF5475_SIU.h
+tos/jtagwait/include/MCF5475_SLT.h
+tos/jtagwait/include/MCF5475_SRAM.h
+tos/jtagwait/include/MCF5475_USB.h
+tos/jtagwait/include/MCF5475_XLB.h
+tos/jtagwait/include/MCF5475.h
+tos/jtagwait/include/driver_vec.h
+tos/jtagwait/sources/bas_printf.c
+tos/jtagwait/sources/bas_string.c
+tos/jtagwait/sources/printf_helper.S
+tos/bascook/Makefile
+tos/bascook/sources/bascook.c
+tos/Makefile
+usb/usb_hub.c
+include/usb_hub.h
--- a/1689
+++ b/1689
--- a/13
+++ b/13
@@ -95,6 +95,7 @@ CSRCS= \
 	usb.c \
 	ohci-hcd.c \
 	ehci-hcd.c \
+	usb_hub.c \
 	usb_mouse.c \
 	ikbd.c \
 	\
@@ -124,6 +125,7 @@ CSRCS= \
 	radeon_accel.c \
 	radeon_cursor.c \
 	radeon_monitor.c \
+	fnt_st_8x16.c \
 	\
 	x86decode.c \
 	x86sys.c \
@@ -143,7 +145,8 @@ ASRCS= \
 	startcf.S \
 	printf_helper.S \
 	exceptions.S \
-	xhdi_vec.S
+	xhdi_vec.S \
+	pci_wrappers.S

 SRCS=$(ASRCS) $(CSRCS)
 COBJS=$(patsubst %.c,%.o,$(CSRCS))
@@ -154,12 +157,18 @@ LIBBAS=libbas.a

 LIBS=$(patsubst %,%/$(LIBBAS),$(TRGTDIRS))

-all: fls ram bfl lib
+all: ver fls ram bfl lib tos
 fls: $(patsubst %,%/$(FLASH_EXEC),$(TRGTDIRS))
 ram: $(patsubst %,%/$(RAM_EXEC),$(TRGTDIRS))
 bfl: $(patsubst %,%/$(BASFLASH_EXEC),$(TRGTDIRS))
 lib: $(LIBS)

+.PHONY: ver
+ver:
+	touch include/version.h
+.PHONY: tos
+tos:
+	(cd tos; make)

 .PHONY: clean
 clean:
--- a/bas.lk.in
+++ b/bas.lk.in
@@ -23,7 +23,7 @@ MEMORY
 	*/
   bas_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00200000, LENGTH = 0x00100000
   /*
-    * driver_ram is an uncached, reserved memory area for drivers (e.g. USB) that need this type of memory
+	* driver_ram is an uncached, reserved memory area for drivers (e.g. USB) that need this type of memory
 	*/
   driver_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00100000, LENGTH = 0x00100000
 }
@@ -44,12 +44,14 @@ SECTIONS
 		OBJDIR/exceptions.o(.text)
 		OBJDIR/driver_vec.o(.text)
 		OBJDIR/interrupts.o(.text)
-		OBJDIR/mmu.o(.text)		
-		
+		OBJDIR/mmu.o(.text)
+
 		OBJDIR/BaS.o(.text)
 		OBJDIR/pci.o(.text)
+		OBJDIR/pci_wrappers.o(.text)
 		OBJDIR/usb.o(.text)
 		OBJDIR/driver_mem.o(.text)
+		OBJDIR/usb_hub.o(.text)
 		OBJDIR/usb_mouse.o(.text)
 		OBJDIR/ohci-hcd.o(.text)
 		OBJDIR/ehci-hcd.o(.text)
@@ -108,7 +110,7 @@ SECTIONS
 		OBJDIR/xhdi_sd.o(.text)
 		OBJDIR/xhdi_interface.o(.text)
 		OBJDIR/xhdi_vec.o(.text)
-		
+
 #ifdef COMPILE_RAM
 		/*
 		 * if we compile to RAM anyway, there is no need to copy anything
@@ -118,7 +120,7 @@ SECTIONS
 		*(.data)
 		__BAS_DATA_END = .;
 		__BAS_BSS_START = .;
-		*(.bss)	
+		*(.bss)
 		__BAS_BSS_END = .;
 #endif /* COMPILE_RAM */

@@ -140,7 +142,7 @@ SECTIONS
 		*(.data)
 		__BAS_DATA_END = .;
 		__BAS_BSS_START = .;
-		*(.bss)	
+		*(.bss)
 		__BAS_BSS_END = .;

 		. = ALIGN(16);
@@ -153,16 +155,16 @@ SECTIONS
 		_driver_mem_buffer = .;
 		//. = . + DRIVER_MEM_BUFFER_SIZE;
 	} > driver_ram
-	
+
 	/*
 	 * Global memory map
 	 */

 	/* SDRAM Initialization */
- 	___SDRAM                = SDRAM_START;
- 	___SDRAM_SIZE           = SDRAM_SIZE;
+	___SDRAM                = SDRAM_START;
+	___SDRAM_SIZE           = SDRAM_SIZE;
 	_SDRAM_VECTOR_TABLE		= ___SDRAM;
-	
+
 	/* ST-RAM */
 	__STRAM                 = ___SDRAM;
 	__STRAM_END             = __TOS;
@@ -173,7 +175,7 @@ SECTIONS
 	/* FastRAM */
 	__FASTRAM               = 0x10000000;
 	__TARGET_ADDRESS		= TARGET_ADDRESS;
-	
+
 #if TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS
 	__FASTRAM_END           = __BAS_IN_RAM;
 #else
@@ -183,7 +185,7 @@ SECTIONS

 	/* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */
 	___BOOT_FLASH           = BOOTFLASH_BASE_ADDRESS;
- 	___BOOT_FLASH_SIZE      = BOOTFLASH_SIZE;
+	___BOOT_FLASH_SIZE      = BOOTFLASH_SIZE;

 #if TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS
 	/* BaS */
@@ -203,35 +205,41 @@ SECTIONS
 	__EMUTOS_SIZE           = 0x00100000;

 	/* where FPGA data lives in flash */
-	__FPGA_FLASH_DATA 		= 0xe0700000;
-	__FPGA_FLASH_DATA_SIZE 	= 0x100000;
+	__FPGA_CONFIG 		= 0xe0700000;
+	__FPGA_CONFIG_SIZE 	= 0x100000;

 	/* VIDEO RAM BASIS */
 	__VRAM                  = 0x60000000;

 	/* Memory mapped registers */
- 	__MBAR                  = 0xFF000000;
-	
+	__MBAR                  = 0xFF000000;
+
 	/* 32KB on-chip System SRAM */
- 	__SYS_SRAM              = __MBAR + 0x10000;
+	__SYS_SRAM              = __MBAR + 0x10000;
 	__SYS_SRAM_SIZE         = 0x00008000;

 	/* MMU memory mapped registers */
- 	__MMUBAR                = 0xFF040000;
+	__MMUBAR                = 0xFF040000;

 	/*
-	 * 4KB on-chip Core SRAM0: -> exception table 
+	 * 4KB on-chip Core SRAM0: -> exception table
 	 */
- 	__RAMBAR0               = 0xFF100000;
- 	__RAMBAR0_SIZE          = 0x00001000;
+	__RAMBAR0               = 0xFF100000;
+	__RAMBAR0_SIZE          = 0x00001000;

 	/* 4KB on-chip Core SRAM1 */
- 	__RAMBAR1               = 0xFF101000;
- 	__RAMBAR1_SIZE          = 0x00001000;
- 	__SUP_SP                = __RAMBAR0 + __RAMBAR0_SIZE - 4;
+	__RAMBAR1               = 0xFF101000;
+	__RAMBAR1_SIZE          = 0x00001000;
+	__SUP_SP                = __RAMBAR1 + __RAMBAR1_SIZE - 4;

+	/*
+	 * this flag (if 1) indicates that FPGA configuration has been loaded through JTAG
+	 * and shouldn't be overwritten on boot
+	 */
+	__FPGA_JTAG_LOADED		= __RAMBAR1;
+	__FPGA_JTAG_VALID		= __RAMBAR1 + 4;
 	/* system variables */
-	
+
 	/* RAMBAR0 0 to 0x7FF -> exception vectors */
 	_rt_mod    = __RAMBAR0 + 0x800;
 	_rt_ssp    = __RAMBAR0 + 0x804;
--- a/dma/MCD_dmaApi.c
+++ b/dma/MCD_dmaApi.c
@@ -66,12 +66,12 @@ MCD_bufDesc *MCD_relocBuffDesc;
 */
 #define DBG_CTL_COMP1_TASK  (0x00002000) /* have comparator 1 look for a task # */
 #define DBG_CTL_ENABLE      (DBG_CTL_AUTO_ARM    | \
-                             DBG_CTL_BREAK       | \
-                             DBG_CTL_INT_BREAK   | \
-                             DBG_CTL_COMP1_TASK)
+							 DBG_CTL_BREAK       | \
+							 DBG_CTL_INT_BREAK   | \
+							 DBG_CTL_COMP1_TASK)
 #define DBG_CTL_DISABLE     (DBG_CTL_AUTO_ARM    | \
-                             DBG_CTL_INT_BREAK   | \
-                             DBG_CTL_COMP1_TASK)
+							 DBG_CTL_INT_BREAK   | \
+							 DBG_CTL_COMP1_TASK)
 #define DBG_KILL_ALL_STAT   (0xFFFFFFFF)

 /*
@@ -247,10 +247,10 @@ int MCD_initDma(dmaRegs *dmaBarAddr, void *taskTableDest, uint32_t flags)
 			entryPtr[i].TDTend = (uint32_t) taskDescTabsOffset - 4;
 		}
 #ifdef MCD_INCLUDE_EU /* Tack single DMA BDs onto end of code so API controls
-                         where they are since DMA might write to them */
+						 where they are since DMA might write to them */
 		MCD_relocBuffDesc = (MCD_bufDesc*)(entryPtr[NUMOFVARIANTS - 1].TDTend + 4);
-#else /* DMA does not touch them so they can be wherever and we don't need to 
-         waste SRAM on them */
+#else /* DMA does not touch them so they can be wherever and we don't need to
+		 waste SRAM on them */
 		MCD_relocBuffDesc = MCD_singleBufDescs;
 #endif
 	}
@@ -352,7 +352,7 @@ int MCD_dmaStatus(int channel)
 * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
 */

-int __attribute__((flatten)) MCD_startDma(int channel, /* the channel on which to run the DMA */
+int MCD_startDma(int channel, /* the channel on which to run the DMA */
 		int8_t *srcAddr, /* the address to move data from, or physical buffer-descriptor address */
 		int16_t srcIncr, /* the amount to increment the source address per transfer */
 		int8_t *destAddr, /* the address to move data to */
@@ -582,7 +582,7 @@ int __attribute__((flatten)) MCD_startDma(int channel, /* the channel on which t
 * Notes:
 *  MCD_XferProgrQuery() upon completing or after aborting a DMA, or
 *  while the DMA is in progress, this function returns the first
- *  DMA-destination address not (or not yet) used in the DMA. When 
+ *  DMA-destination address not (or not yet) used in the DMA. When
 *  encountering a non-ready buffer descriptor, the information for
 *  the last completed descriptor is returned.
 *
@@ -850,7 +850,7 @@ int MCD_continDma(int channel)
 * this means that bits 14 and 0 must enable debug functions before
 * bits 1 and 2, respectively, have any effect.
 *
- * NOTE: It's extremely important to not pause more than one DMA channel 
+ * NOTE: It's extremely important to not pause more than one DMA channel
 *  at a time.
 ********************************************************************/

--- a/dma/dma.c
+++ b/dma/dma.c
@@ -41,7 +41,7 @@

 #define DBG_DMA
 #ifdef DBG_DMA
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_DMA */
@@ -58,13 +58,13 @@ struct dma_channel
 static char used_reqs[32] =
 {
 	DMA_ALWAYS,  DMA_DSPI_RXFIFO, DMA_DSPI_TXFIFO, DMA_DREQ0,
-    DMA_PSC0_RX, DMA_PSC0_TX, DMA_USB_EP0,  DMA_USB_EP1,
-    DMA_USB_EP2,  DMA_USB_EP3,  DMA_PCI_TX,  DMA_PCI_RX,
-    DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX,  DMA_I2C_TX,
-    0,           0,           0,           0,
-    0,           0,           0,           0,
-    0,           0,           0,           0,
-    0,           0,           0,           0
+	DMA_PSC0_RX, DMA_PSC0_TX, DMA_USB_EP0,  DMA_USB_EP1,
+	DMA_USB_EP2,  DMA_USB_EP3,  DMA_PCI_TX,  DMA_PCI_RX,
+	DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX,  DMA_I2C_TX,
+	0,           0,           0,           0,
+	0,           0,           0,           0,
+	0,           0,           0,           0,
+	0,           0,           0,           0
 };

 static struct dma_channel dma_channel[NCHANNELS] =
@@ -75,7 +75,6 @@ static struct dma_channel dma_channel[NCHANNELS] =
 	{-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL},
 };

-/********************************************************************/
 /*
 * Enable all DMA interrupts
 *
@@ -89,7 +88,7 @@ void dma_irq_enable(uint8_t lvl, uint8_t pri)
 	MCF_INTC_ICR48 = 0
 		| MCF_INTC_ICR_IP(pri)
 		| MCF_INTC_ICR_IL(lvl);
-	dbg("%s:DMA irq assigned level %d, priority %d\r\n", __FUNCTION__, lvl, pri);
+	dbg("DMA irq assigned level %d, priority %d\r\n", lvl, pri);

 	/* Unmask all task interrupts */
 	MCF_DMA_DIMR = 0;
@@ -100,11 +99,9 @@ void dma_irq_enable(uint8_t lvl, uint8_t pri)
 	/* Unmask the DMA interrupt in the interrupt controller */
 	MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK48;

-	dbg("%s: DMA task interrupts unmasked, pending interrupts cleared, interrupt controller active\r\n",
-		__FUNCTION__);
+	dbg("DMA task interrupts unmasked, pending interrupts cleared, interrupt controller active\r\n");
 }

-/********************************************************************/
 /*
 * Disable all DMA interrupts
 */
@@ -119,7 +116,7 @@ void dma_irq_disable(void)
 	/* Mask the DMA interrupt in the interrupt controller */
 	MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK48;

-	dbg("%s: DMA interrupts masked and disabled\r\n", __FUNCTION__);
+	dbg("DMA interrupts masked and disabled\r\n");
 }

 int dma_set_initiator(int initiator)
@@ -177,7 +174,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot found\r\n", __FUNCTION__);
+				dbg("no free slot found\r\n");

 				return 1;
 			}
@@ -196,7 +193,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");

 				return 1;
 			}
@@ -210,7 +207,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");

 				return 1;
 			}
@@ -224,8 +221,8 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
-				
+				dbg("no free slot\r\n");
+
 				return 1;
 			}
 			break;
@@ -238,7 +235,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");

 				return 1;
 			}
@@ -252,7 +249,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");

 				return 1;
 			}
@@ -266,7 +263,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");

 				return 1;
 			}
@@ -280,7 +277,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");

 				return 1;
 			}
@@ -294,7 +291,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");

 				return 1;
 			}
@@ -308,7 +305,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");

 				return 1;
 			}
@@ -322,7 +319,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");

 				return 1;
 			}
@@ -336,7 +333,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");

 				return 1;
 			}
@@ -359,7 +356,7 @@ int dma_set_initiator(int initiator)
 				used_reqs[28] = DMA_PSC2_RX;            }
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");

 				return 1;
 			}
@@ -373,7 +370,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");

 				return 1;
 			}
@@ -387,7 +384,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");

 				return 1;
 			}
@@ -401,7 +398,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");

 				return 1;
 			}
@@ -409,7 +406,7 @@ int dma_set_initiator(int initiator)

 		default:
 			{
-				dbg("%s: don't know what to do\r\n", __FUNCTION__);
+				dbg("don't know what to do\r\n");

 				return 1;
 			}
@@ -436,7 +433,7 @@ uint32_t dma_get_initiator(int requestor)
 		if (used_reqs[i] == requestor)
 			return i;
 	}
-	dbg("%s: no initiator found for requestor %d\r\n", __FUNCTION__, requestor);
+	dbg("no initiator found for requestor %d\r\n", requestor);

 	return 0;
 }
@@ -459,7 +456,7 @@ void dma_free_initiator(int requestor)
 			break;
 		}
 	}
-	dbg("%s: DMA requestor %d freed\r\n", __FUNCTION__, requestor);
+	dbg("DMA requestor %d freed\r\n", requestor);
 }

 /*
@@ -476,7 +473,7 @@ int dma_set_channel(int requestor, void (*handler)(void))
 	int i;

 	/* Check to see if this requestor is already assigned to a channel */
-	dbg("%s: check if requestor %d is already assigned to a channel\r\n", __FUNCTION__, requestor);
+	dbg("check if requestor %d is already assigned to a channel\r\n", requestor);
 	if ((i = dma_get_channel(requestor)) != -1)
 		return i;

@@ -486,11 +483,11 @@ int dma_set_channel(int requestor, void (*handler)(void))
 		{
 			dma_channel[i].req = requestor;
 			dma_channel[i].handler = handler;
-			dbg("%s: assigned channel %d to requestor %d\r\n", __FUNCTION__, i, requestor);
+			dbg("assigned channel %d to requestor %d\r\n", i, requestor);
 			return i;
 		}
 	}
-	dbg("%s: no free DMA channel found for requestor %d\r\n", __FUNCTION__, requestor);
+	dbg("no free DMA channel found for requestor %d\r\n", requestor);

 	/* All channels taken */
 	return -1;
@@ -502,7 +499,7 @@ void dma_clear_channel(int channel)
 	{
 		dma_channel[channel].req = -1;
 		dma_channel[channel].handler = NULL;
-		dbg("%s: cleared DMA channel %d\r\n", __FUNCTION__, channel);
+		dbg("cleared DMA channel %d\r\n", channel);
 	}
 }

@@ -525,12 +522,12 @@ int dma_get_channel(int requestor)
 		if (dma_channel[i].req == requestor)
 			return i;
 	}
-	dbg("%s: no channel occupied by requestor %d\r\n", __FUNCTION__, requestor);
+	dbg("no channel occupied by requestor %d\r\n", requestor);
 	return -1;
 }

 /*
- * Remove the channel being initiated by the given requestor from 
+ * Remove the channel being initiated by the given requestor from
 * the active list
 *
 * Parameters:
@@ -551,17 +548,18 @@ void dma_free_channel(int requestor)
 	}
 }

-/* 
- * This is the catch-all interrupt handler for the mult-channel DMA 
+/*
+ * This is the catch-all interrupt handler for the mult-channel DMA
 */
 int dma_interrupt_handler(void *arg1, void *arg2)
 {
 	int i, interrupts;
+	uint32_t ipl;

-	(void) set_ipl(7);
+	ipl = set_ipl(7);		/* do not disturb */

-	/* 
-	 * Determine which interrupt(s) triggered by AND'ing the 
+	/*
+	 * Determine which interrupt(s) triggered by AND'ing the
 	 * pending interrupts with those that aren't masked.
 	 */
 	interrupts = MCF_DMA_DIPR & ~MCF_DMA_DIMR;
@@ -569,7 +567,7 @@ int dma_interrupt_handler(void *arg1, void *arg2)
 	/* Make sure we are here for a reason */
 	if (interrupts == 0)
 	{
-		dbg("%s: not DMA interrupt! Spurious?\r\n", __FUNCTION__);
+		dbg("not DMA interrupt! Spurious?\r\n");
 		return 0;
 	}

@@ -583,12 +581,14 @@ int dma_interrupt_handler(void *arg1, void *arg2)
 			/* If there is a handler, call it */
 			if (dma_channel[i].handler != NULL)
 			{
-				dbg("%s: call handler for DMA channel %d (%p)\r\n", __FUNCTION__, i, dma_channel[i].handler);
+				dbg("call handler for DMA channel %d (%p)\r\n", i, dma_channel[i].handler);
 				dma_channel[i].handler();
 			}
 		}
 	}

+	set_ipl(ipl);
+
 	return 1;	/* handled */
 }
 /********************************************************************/
@@ -598,9 +598,9 @@ void *dma_memcpy(void *dst, void *src, size_t n)
 	int ret;

 #ifdef DBG_DMA
-    int32_t time;
-    int32_t start;
-    int32_t end;
+	int32_t time;
+	int32_t start;
+	int32_t end;

 	start = MCF_SLT0_SCNT;
 #endif /* DBG_DMA */
@@ -608,7 +608,7 @@ void *dma_memcpy(void *dst, void *src, size_t n)
 	ret = MCD_startDma(1, src, 4, dst, 4, n, 4, DMA_ALWAYS, 0, MCD_SINGLE_DMA, 0);
 	if (ret == MCD_OK)
 	{
-		dbg("%s: DMA on channel 1 successfully started\r\n", __FUNCTION__);
+		dbg("DMA on channel 1 successfully started\r\n");
 	}

 	do
@@ -652,7 +652,7 @@ void *dma_memcpy(void *dst, void *src, size_t n)
 	end = MCF_SLT0_SCNT;
 	time = (start - end) / (SYSCLK / 1000) / 1000;
 #endif /* DBG_DMA */
-	dbg("%s: took %d ms (%f Mbytes/second)\r\n", __FUNCTION__, time, n / (float) time / 1000.0);
+	dbg("took %d ms (%f Mbytes/second)\r\n", time, n / (float) time / 1000.0);

 	return dst;
 }
@@ -661,11 +661,11 @@ int dma_init(void)
 {
 	int res;

-	dbg("%s: MCD DMA API initialization: ", __FUNCTION__);
+	dbg("MCD DMA API initialization: ");
 	res = MCD_initDma((dmaRegs *) &_MBAR[0x8000], SYS_SRAM, MCD_RELOC_TASKS | MCD_COMM_PREFETCH_EN);
 	if (res != MCD_OK)
 	{
-		dbg("%s: DMA API initialization failed (0x%x)\r\n", __FUNCTION__, res);
+		dbg("DMA API initialization failed (0x%x)\r\n", res);
 		return 0;
 	}

--- a/exe/basflash.c
+++ b/exe/basflash.c
@@ -21,10 +21,9 @@
 *      Author: Markus Fröschle
 */

-#include <stdint.h>
-#include <stdbool.h>
-#include "bas_string.h"
+#include <bas_types.h>
 #include "bas_printf.h"
+#include "bas_string.h"
 #include "diskio.h"
 #include "ff.h"
 #include "s19reader.h"
@@ -220,190 +219,190 @@ static const int num_flash_areas = sizeof(flash_areas) / sizeof(struct romram);
 */
 void amd_flash_sector_erase(int n)
 {
-    volatile AMD_FLASH_CELL status;
+	volatile AMD_FLASH_CELL status;

-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);

-    do
-        status = pFlash[SADDR(n)];
-    while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));
+	do
+		status = pFlash[SADDR(n)];
+	while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));

-    /*
-     * Place device in read mode
-     */
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+	/*
+	 * Place device in read mode
+	 */
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
 }

 int amd_flash_erase(void *start, int bytes, void (*putchar)(int))
 {
-    int i, ebytes = 0;
+	int i, ebytes = 0;

-    if (bytes == 0)
-        return 0;
+	if (bytes == 0)
+		return 0;

-    for (i = 0; i < AMD_FLASH_SECTORS; i++)
-    {
-        if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
-            start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
-        {
-            break;
-        }
-    }
+	for (i = 0; i < AMD_FLASH_SECTORS; i++)
+	{
+		if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
+			start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
+		{
+			break;
+		}
+	}

-    while (ebytes < bytes)
-    {
-        if (putchar != NULL)
-        {
-            putchar('.');
-        }
-        amd_flash_sector_erase(i);
-        ebytes += SSIZE(i);
-        i++;
-    }
+	while (ebytes < bytes)
+	{
+		if (putchar != NULL)
+		{
+			putchar('.');
+		}
+		amd_flash_sector_erase(i);
+		ebytes += SSIZE(i);
+		i++;
+	}

-    if (putchar != NULL)
-    {
-        putchar(10);    /* LF */
-        putchar(13);    /* CR */
-    }
+	if (putchar != NULL)
+	{
+		putchar(10);    /* LF */
+		putchar(13);    /* CR */
+	}

-    return ebytes;
+	return ebytes;
 }

 void amd_flash_program_cell(AMD_FLASH_CELL *dst, AMD_FLASH_CELL data)
 {
-    volatile AMD_FLASH_CELL status;
-    int retry;
+	volatile AMD_FLASH_CELL status;
+	int retry;

-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
-    *dst = data;
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
+	*dst = data;

-    /*
-     * Wait for program operation to finish
-     *  (Data# Polling Algorithm)
-     */
-    retry = 0;
-    while (1)
-    {
-        status = *dst;
-        if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
-            (data & AMD_FLASH_CMD_DATA(0x80)))
-        {
-            break;
-        }
-        if (status & AMD_FLASH_CMD_DATA(0x20))
-        {
-            status = *dst;
-            if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
-                (data & AMD_FLASH_CMD_DATA(0x80)))
-            {
-                break;
-            }
-            if (++retry > 1024)
-            {
-                break;
-            }
-        }
-    }
+	/*
+	 * Wait for program operation to finish
+	 *  (Data# Polling Algorithm)
+	 */
+	retry = 0;
+	while (1)
+	{
+		status = *dst;
+		if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
+			(data & AMD_FLASH_CMD_DATA(0x80)))
+		{
+			break;
+		}
+		if (status & AMD_FLASH_CMD_DATA(0x20))
+		{
+			status = *dst;
+			if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
+				(data & AMD_FLASH_CMD_DATA(0x80)))
+			{
+				break;
+			}
+			if (++retry > 1024)
+			{
+				break;
+			}
+		}
+	}
 }


 int amd_flash_program(void *dest, void *source, int bytes, int erase, void (*func)(void), void (*putchar)(int))
 {
-    AMD_FLASH_CELL *src, *dst;
-    int hashi=1,hashj=0;
-    char hash[5];
+	AMD_FLASH_CELL *src, *dst;
+	int hashi=1,hashj=0;
+	char hash[5];

-    hash[0]=8;  /* Backspace */
-    hash[1]=124;/* "|" */
-    hash[2]=47; /* "/" */
-    hash[3]=45; /* "-" */
-    hash[4]=92; /* "\" */
+	hash[0]=8;  /* Backspace */
+	hash[1]=124;/* "|" */
+	hash[2]=47; /* "/" */
+	hash[3]=45; /* "-" */
+	hash[4]=92; /* "\" */

-    src = (AMD_FLASH_CELL *)source;
-    dst = (AMD_FLASH_CELL *)dest;
+	src = (AMD_FLASH_CELL *)source;
+	dst = (AMD_FLASH_CELL *)dest;

-    /*
-     * Place device in read mode
-     */
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+	/*
+	 * Place device in read mode
+	 */
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);

-    /*
-     * Erase device if necessary
-     */
-    if (erase)
-    {
-        amd_flash_erase(dest, bytes, putchar);
-    }
+	/*
+	 * Erase device if necessary
+	 */
+	if (erase)
+	{
+		amd_flash_erase(dest, bytes, putchar);
+	}

-    /*
-     * Program device
-     */
-    while (bytes > 0)
-    {
-        amd_flash_program_cell(dst,*src);
+	/*
+	 * Program device
+	 */
+	while (bytes > 0)
+	{
+		amd_flash_program_cell(dst,*src);

-        /* Verify Write */
-        if (*dst == *src)
-        {
-            bytes -= AMD_FLASH_CELL_BYTES;
-            *dst++, *src++;
+		/* Verify Write */
+		if (*dst == *src)
+		{
+			bytes -= AMD_FLASH_CELL_BYTES;
+			*dst++, *src++;

-            if ((putchar != NULL))
-            {
-                /* Hash marks to indicate progress */
-                if (hashj == 0x1000)
-                {
-                    hashj = -1;
-                    putchar(hash[0]);
-                    putchar(hash[hashi]);
+			if ((putchar != NULL))
+			{
+				/* Hash marks to indicate progress */
+				if (hashj == 0x1000)
+				{
+					hashj = -1;
+					putchar(hash[0]);
+					putchar(hash[hashi]);

-                    hashi++;
-                    if (hashi == 5)
-                    {
-                        hashi=1;
-                    }
+					hashi++;
+					if (hashi == 5)
+					{
+						hashi=1;
+					}

-                }
-                hashj++;
-            }
-        }
-        else
-            break;
-    }
+				}
+				hashj++;
+			}
+		}
+		else
+			break;
+	}

-    /*
-     * Place device in read mode
-     */
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+	/*
+	 * Place device in read mode
+	 */
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);

-    if (putchar != NULL)
-    {
-        putchar(hash[0]);
-    }
+	if (putchar != NULL)
+	{
+		putchar(hash[0]);
+	}

-    /*
-     * If a function was passed in, call it now
-     */
-    if ((func != NULL))
-    {
-        func();
-    }
+	/*
+	 * If a function was passed in, call it now
+	 */
+	if ((func != NULL))
+	{
+		func();
+	}

-    return ((int)src - (int)source);
+	return ((int)src - (int)source);
 }

 /*
@@ -635,7 +634,7 @@ void basflash(void)
 						if (strlen(fileinfo.fname) >= 4
 								&& strncmp(
 										&fileinfo.fname[strlen(fileinfo.fname)
-										                - 4], srec_ext, 4) == 0) /* we have a .S19 file */
+														- 4], srec_ext, 4) == 0) /* we have a .S19 file */
 						{
 							/*
 							 * build path + filename
--- a/exe/basflash_start.c
+++ b/exe/basflash_start.c
@@ -21,7 +21,7 @@
 *      Author: Markus Fröschle
 */

-#include <stdint.h>
+#include <bas_types.h>

 static uint32_t ownstack[4096];
 static uint32_t *stackptr = &ownstack[4095];
--- a/flash/flash.c
+++ b/flash/flash.c
@@ -1,4 +1,3 @@
-#include <stdint.h>
 #include <stddef.h>
 #include "bas_types.h"

@@ -192,191 +191,191 @@ static const int num_flash_areas = sizeof(flash_areas) / sizeof(struct romram);
 */
 void amd_flash_sector_erase(int n)
 {
-    volatile AMD_FLASH_CELL status;
+	volatile AMD_FLASH_CELL status;

-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);

-    do
-        status = pFlash[SADDR(n)];
-    while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));
+	do
+		status = pFlash[SADDR(n)];
+	while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));

-    /*
-     * Place device in read mode
-     */
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+	/*
+	 * Place device in read mode
+	 */
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
 }

 int amd_flash_erase(void *start, int bytes, void (*putchar)(int))
 {
-    int i, ebytes = 0;
+	int i, ebytes = 0;

-    if (bytes == 0)
-        return 0;
+	if (bytes == 0)
+		return 0;

-    for (i = 0; i < AMD_FLASH_SECTORS; i++)
-    {
-        if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
-            start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
-        {
-            break;
-        }
-    }
+	for (i = 0; i < AMD_FLASH_SECTORS; i++)
+	{
+		if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
+			start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
+		{
+			break;
+		}
+	}

-    while (ebytes < bytes)
-    {
-        if (putchar != NULL)
-        {
-            putchar('.');
-        }
-        amd_flash_sector_erase(i);
-        ebytes += SSIZE(i);
-        i++;
-    }
+	while (ebytes < bytes)
+	{
+		if (putchar != NULL)
+		{
+			putchar('.');
+		}
+		amd_flash_sector_erase(i);
+		ebytes += SSIZE(i);
+		i++;
+	}

-    if (putchar != NULL)
-    {
-        putchar(10);    /* LF */
-        putchar(13);    /* CR */
-    }
+	if (putchar != NULL)
+	{
+		putchar(10);    /* LF */
+		putchar(13);    /* CR */
+	}

-    return ebytes;
+	return ebytes;
 }

 void amd_flash_program_cell(AMD_FLASH_CELL *dst, AMD_FLASH_CELL data)
 {
-    volatile AMD_FLASH_CELL status;
-    int retry;
+	volatile AMD_FLASH_CELL status;
+	int retry;

-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
-    *dst = data;
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
+	*dst = data;

-    /*
-     * Wait for program operation to finish
-     *  (Data# Polling Algorithm)
-     */
-    retry = 0;
-    while (1)
-    {
-        status = *dst;
-        if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
-            (data & AMD_FLASH_CMD_DATA(0x80)))
-        {
-            break;
-        }
-        if (status & AMD_FLASH_CMD_DATA(0x20))
-        {
-            status = *dst;
-            if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
-                (data & AMD_FLASH_CMD_DATA(0x80)))
-            {
-                break;
-            }
-            if (++retry > 1024)
-            {
-                break;
-            }
-        }
-    }
+	/*
+	 * Wait for program operation to finish
+	 *  (Data# Polling Algorithm)
+	 */
+	retry = 0;
+	while (1)
+	{
+		status = *dst;
+		if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
+			(data & AMD_FLASH_CMD_DATA(0x80)))
+		{
+			break;
+		}
+		if (status & AMD_FLASH_CMD_DATA(0x20))
+		{
+			status = *dst;
+			if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
+				(data & AMD_FLASH_CMD_DATA(0x80)))
+			{
+				break;
+			}
+			if (++retry > 1024)
+			{
+				break;
+			}
+		}
+	}
 }


 int amd_flash_program(void *dest, void *source, int bytes, int erase, void (*func)(void), void (*putchar)(int))
 {
-    AMD_FLASH_CELL *src;
+	AMD_FLASH_CELL *src;
 	AMD_FLASH_CELL *dst;
-    int hashi = 1;
+	int hashi = 1;
 	int hashj = 0;
-    char hash[5];
+	char hash[5];

-    hash[0] = 8;  /* Backspace */
-    hash[1] = 124;/* "|" */
-    hash[2] = 47; /* "/" */
-    hash[3] = 45; /* "-" */
-    hash[4] = 92; /* "\" */
+	hash[0] = 8;  /* Backspace */
+	hash[1] = 124;/* "|" */
+	hash[2] = 47; /* "/" */
+	hash[3] = 45; /* "-" */
+	hash[4] = 92; /* "\" */

-    src = (AMD_FLASH_CELL *)source;
-    dst = (AMD_FLASH_CELL *)dest;
+	src = (AMD_FLASH_CELL *)source;
+	dst = (AMD_FLASH_CELL *)dest;

-    /*
-     * Place device in read mode
-     */
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+	/*
+	 * Place device in read mode
+	 */
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);

-    /*
-     * Erase device if necessary
-     */
-    if (erase)
-    {
-        amd_flash_erase(dest, bytes, putchar);
-    }
+	/*
+	 * Erase device if necessary
+	 */
+	if (erase)
+	{
+		amd_flash_erase(dest, bytes, putchar);
+	}

-    /*
-     * Program device
-     */
-    while (bytes > 0)
-    {
-        amd_flash_program_cell(dst, *src);
+	/*
+	 * Program device
+	 */
+	while (bytes > 0)
+	{
+		amd_flash_program_cell(dst, *src);

-        /* Verify Write */
-        if (*dst == *src)
-        {
-            bytes -= AMD_FLASH_CELL_BYTES;
-            *dst++, *src++;
+		/* Verify Write */
+		if (*dst == *src)
+		{
+			bytes -= AMD_FLASH_CELL_BYTES;
+			*dst++, *src++;

-            if ((putchar != NULL))
-            {
-                /* Hash marks to indicate progress */
-                if (hashj == 0x1000)
-                {
-                    hashj = -1;
-                    putchar(hash[0]);
-                    putchar(hash[hashi]);
+			if ((putchar != NULL))
+			{
+				/* Hash marks to indicate progress */
+				if (hashj == 0x1000)
+				{
+					hashj = -1;
+					putchar(hash[0]);
+					putchar(hash[hashi]);

-                    hashi++;
-                    if (hashi == 5)
-                    {
-                        hashi = 1;
-                    }
+					hashi++;
+					if (hashi == 5)
+					{
+						hashi = 1;
+					}

-                }
-                hashj++;
-            }
-        }
-        else
-            break;
-    }
+				}
+				hashj++;
+			}
+		}
+		else
+			break;
+	}

-    /*
-     * Place device in read mode
-     */
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+	/*
+	 * Place device in read mode
+	 */
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);

-    if (putchar != NULL)
-    {
-        putchar(hash[0]);
-    }
+	if (putchar != NULL)
+	{
+		putchar(hash[0]);
+	}

-    /*
-     * If a function was passed in, call it now
-     */
-    if ((func != NULL))
-    {
-        func();
-    }
+	/*
+	 * If a function was passed in, call it now
+	 */
+	if ((func != NULL))
+	{
+		func();
+	}

-    return ((int)src - (int)source);
+	return ((int)src - (int)source);
 }

--- a/flash/s19reader.c
+++ b/flash/s19reader.c
@@ -23,8 +23,7 @@
 * Copyright 2012        M. Froeschle
 */

-#include <stdint.h>
-#include <stdbool.h>
+#include <bas_types.h>

 #include "bas_printf.h"
 #include "bas_string.h"
@@ -345,10 +344,10 @@ static err_t verify(uint8_t *dst, uint8_t *src, uint32_t length)
 */
 static inline err_t srec_memcpy(uint8_t *dst, uint8_t *src, size_t n)
 {
-    err_t e = OK;
+	err_t e = OK;

-    memcpy((void *) dst, (void *) src, n);
-    return e;
+	memcpy((void *) dst, (void *) src, n);
+	return e;
 }

 void srec_execute(char *flasher_filename)
@@ -383,7 +382,7 @@ void srec_execute(char *flasher_filename)
 				{
 					/* next pass: copy data to destination */
 					xprintf("OK.\r\ncopy/flash data: ");
-                    err = read_srecords(flasher_filename, &start_address, &length, srec_memcpy);
+					err = read_srecords(flasher_filename, &start_address, &length, srec_memcpy);
 					if (err == OK)
 					{
 						/* next pass: verify data */
--- a/flash_scripts/flash_firebee_bas.bdm
+++ b/flash_scripts/flash_firebee_bas.bdm
@@ -1,71 +1,53 @@
-#!/usr/local/bin/bdmctrl 
+#!/usr/local/bin/bdmctrl -D2
 #
 # firebee board initialization for bdmctrl 
 #
 open $1
 reset
-sleep 10
+sleep 1

 wait

-# Turn on MBAR at 0xFF00_0000
-write-ctrl 0x0C0F 0xFF000000
-
-# set VBR
-write-ctrl 0x0801 0x00000000
-
-#
-# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
-write 0xFF000500 0xE0000000 4
-write 0xFF000508 0x00001180 4
-write 0xFF000504 0x007F0001 4
-
-# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
-write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
-write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
-write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
-write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
-write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
-write 0xFF000108 0x73622830 4 # SDCFG1
-write 0xFF00010C 0x46770000 4 # SDCFG2
-
-write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
-write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
-write 0xFF000100 0x048D0000 4 # SDMR (write to LMR)
-sleep 100
-write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
-write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
-write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
-write 0xFF000100 0x008D0000 4 # SDMR (write to LMR)
-write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
-sleep 10
-
-
 # use system sdram as flashlib scratch area.
 # TODO: plugin flashing seems to work o.k. now for smaller binaries, while it doesn't for larger ones (EmuTOS) yet.
 # This seems to be related to large flash buffers and PC-relative adressing of the plugin
-flash-plugin 0x1000 0xf000 flash29.plugin
+#flash-plugin 0x1000 0xf000 flash29-5475.plugin
 # notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
-flash 0xE0000000
+flash 0xe0000000

 # Erase flash from 0xE0000000 to 0xE00FFFFF (reserved space for BaS)
 #
 # Caution: sector offset numbers need to be the ones from the x16 address range
 # column and they vary in size - needs to be exactly as in the data sheet (p. 9)
 #
-# contrary to documentation, it seems we need to erase-wait after each sector

-erase 0xE0000000 0
-erase 0xE0000000 1
-erase 0xE0000000 2
-erase 0xE0000000 3
-erase 0xE0000000 4
-erase 0xE0000000 5
-erase 0xE0000000 7
-erase 0xE0000000 8
-erase 0xE0000000 9
-erase 0xE0000000 10
-erase-wait 0xE0000000
+erase 0xe0000000 0
+erase 0xe0000000 0x1000
+erase 0xe0000000 0x2000
+erase 0xe0000000 0x3000
+erase 0xe0000000 0x4000
+erase 0xe0000000 0x5000
+erase 0xe0000000 0x6000
+erase 0xe0000000 0x7000
+erase 0xe0000000 0x8000
+erase 0xe0000000 0x10000
+erase 0xe0000000 0x18000
+erase 0xe0000000 0x20000
+erase 0xe0000000 0x28000
+erase 0xe0000000 0x30000
+erase 0xe0000000 0x38000
+erase 0xe0000000 0x40000
+erase 0xe0000000 0x48000
+erase 0xe0000000 0x50000
+erase 0xe0000000 0x58000
+erase 0xe0000000 0x60000
+erase 0xe0000000 0x70000
+erase 0xe0000000 0x78000
+
+erase-wait 0xe0000000
+# should now have erased from 0xe0000000 to 0xe00fffff
+
+dump-mem 0xe0010000 0x20 b

 load -v ../firebee/bas.elf
 wait
--- a/fs/ccsbcs.c
+++ b/fs/ccsbcs.c
@@ -26,7 +26,7 @@
 */

 #include <ff.h>
-#include <stdint.h>
+#include <bas_types.h>

 #if _CODE_PAGE == 437
 #define _TBLDEF 1
--- a/fs/ff.c
+++ b/fs/ff.c
@@ -95,7 +95,7 @@
 /                   Changed option name _FS_SHARE to _FS_LOCK.
 /---------------------------------------------------------------------------*/

-#include <stdint.h>
+#include <bas_types.h>
 #include <ff.h>			/* FatFs configurations and declarations */
 #include <diskio.h>		/* Declarations of low level disk I/O functions */

@@ -356,11 +356,11 @@ typedef struct {
 uint32_t get_fattime (void)
 {
   return     ((uint32_t)(2012 - 1980) << 25)   /* Year = 2012 */
-         | ((uint32_t)1 << 21)            /* Month = 1 */
-         | ((uint32_t)1 << 16)            /* Day_m = 1*/
-         | ((uint32_t)0 << 11)            /* Hour = 0 */
-         | ((uint32_t)0 << 5)          /* Min = 0 */
-         | ((uint32_t)0 >> 1);            /* Sec = 0 */
+		 | ((uint32_t)1 << 21)            /* Month = 1 */
+		 | ((uint32_t)1 << 16)            /* Day_m = 1*/
+		 | ((uint32_t)0 << 11)            /* Hour = 0 */
+		 | ((uint32_t)0 << 5)          /* Min = 0 */
+		 | ((uint32_t)0 >> 1);            /* Sec = 0 */
 }

 /* Character code support macros */
@@ -970,7 +970,7 @@ FRESULT remove_chain (
 #if _USE_ERASE
 			if (ecl + 1 == nxt) {	/* Is next cluster contiguous? */
 				ecl = nxt;
-			} else {				/* End of contiguous clusters */ 
+			} else {				/* End of contiguous clusters */
 				rt[0] = clust2sect(fs, scl);					/* Start sector */
 				rt[1] = clust2sect(fs, ecl) + fs->csize - 1;	/* End sector */
 				disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, rt);		/* Erase the block */
@@ -2190,7 +2190,7 @@ FRESULT chk_mounted (	/* FR_OK(0): successful, !=0: any error occurred */

 	/* Get fsinfo if available */
 	if (fmt == FS_FAT32) {
-	 	fs->fsi_flag = 0;
+		fs->fsi_flag = 0;
 		fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo);
 		if (disk_read(fs->drv, fs->win, fs->fsi_sector, 1) == RES_OK &&
 			LD_WORD(fs->win+BS_55AA) == 0xAA55 &&
@@ -2721,7 +2721,7 @@ FRESULT f_close (
 		FATFS *fs = fp->fs;;
 		res = validate(fp);
 		if (res == FR_OK) {
-			res = dec_lock(fp->lockid);	
+			res = dec_lock(fp->lockid);
 			unlock_fs(fs, FR_OK);
 		}
 #else
@@ -2820,7 +2820,7 @@ FRESULT f_getcwd (
 				res = dir_read(&dj);
 				if (res != FR_OK) break;
 				if (ccl == ld_clust(dj.fs, dj.dir)) break;	/* Found the entry */
-				res = dir_next(&dj, 0);	
+				res = dir_next(&dj, 0);
 			} while (res == FR_OK);
 			if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
 			if (res != FR_OK) break;
--- a/if/driver_vec.c
+++ b/if/driver_vec.c
@@ -23,18 +23,18 @@
 *      Author: Markus Fröschle
 */

-#include <stdint.h>
-#include <stddef.h>
+#include <bas_types.h>
 #include "version.h"
 #include "xhdi_sd.h"
 #include "dma.h"
 #include "driver_vec.h"
 #include "driver_mem.h"
+#include "pci.h"

 /*
 * driver interface struct for the SD card BaS driver
 */
-static struct xhdi_driver_interface xhdi_call_interface = 
+static struct xhdi_driver_interface xhdi_call_interface =
 {
 	xhdi_call
 };
@@ -55,19 +55,73 @@ static struct dma_driver_interface dma_interface =
 	.dma_get_channel = dma_get_channel,
 	.dma_free_channel = dma_free_channel,
 	.dma_clear_channel = dma_clear_channel,
-	.MCD_startDma = MCD_startDma,
-	.MCD_dmaStatus = MCD_dmaStatus,
-	.MCD_XferProgrQuery = MCD_XferProgrQuery,
-	.MCD_killDma = MCD_killDma,
-	.MCD_continDma = MCD_continDma,
-	.MCD_pauseDma = MCD_pauseDma,
-	.MCD_resumeDma = MCD_resumeDma,
-	.MCD_csumQuery = MCD_csumQuery,
+	.MCD_startDma = (int (*)(long, int8_t *, unsigned int, int8_t *, unsigned int,
+					unsigned int, unsigned int, unsigned int, int,
+					unsigned int, unsigned int)) MCD_startDma,
+	.MCD_dmaStatus = (int32_t (*)(int32_t)) MCD_dmaStatus,
+	.MCD_XferProgrQuery = (int32_t (*)(int32_t, MCD_XferProg *)) MCD_XferProgrQuery,
+	.MCD_killDma = (int32_t (*)(int32_t)) MCD_killDma,
+	.MCD_continDma = (int32_t (*)(int32_t)) MCD_continDma,
+	.MCD_pauseDma = (int32_t (*)(int32_t)) MCD_pauseDma,
+	.MCD_resumeDma = (int32_t (*)(int32_t)) MCD_resumeDma,
+	.MCD_csumQuery = (int32_t (*)(int32_t, uint32_t *)) MCD_csumQuery,
 	.dma_malloc = driver_mem_alloc,
 	.dma_free = driver_mem_free
 };

-extern const struct fb_info *info_fb;
+extern struct fb_info *info_fb;
+
+/*
+ * driver interface struct for the PCI_BIOS BaS driver
+ */
+static struct pci_bios_interface pci_interface =
+{
+	.subjar = 0,
+	.version = 0x00010000,
+	.find_pci_device = wrapper_find_pci_device,
+	.find_pci_classcode = wrapper_find_pci_classcode,
+	.read_config_byte = wrapper_read_config_byte,
+	.read_config_word = wrapper_read_config_word,
+	.read_config_longword = wrapper_read_config_longword,
+	.fast_read_config_byte = wrapper_fast_read_config_byte,
+	.fast_read_config_word = wrapper_fast_read_config_word,
+	.fast_read_config_longword = wrapper_fast_read_config_longword,
+	.write_config_byte = wrapper_write_config_byte,
+	.write_config_word = wrapper_write_config_word,
+	.write_config_longword = wrapper_write_config_longword,
+	.hook_interrupt = wrapper_hook_interrupt,
+	.unhook_interrupt = wrapper_unhook_interrupt,
+	.special_cycle = wrapper_special_cycle,
+	.get_routing = wrapper_get_routing,
+	.set_interrupt = wrapper_set_interrupt,
+	.get_resource = wrapper_get_resource,
+	.get_card_used = wrapper_get_card_used,
+	.set_card_used = wrapper_set_card_used,
+	.read_mem_byte = wrapper_read_mem_byte,
+	.read_mem_word = wrapper_read_mem_word,
+	.read_mem_longword = wrapper_read_mem_longword,
+	.fast_read_mem_byte = wrapper_fast_read_mem_byte,
+	.fast_read_mem_word = wrapper_fast_read_mem_word,
+	.fast_read_mem_longword = wrapper_fast_read_mem_longword,
+	.write_mem_byte = wrapper_write_mem_byte,
+	.write_mem_word = wrapper_write_mem_word,
+	.write_mem_longword = wrapper_write_mem_longword,
+	.read_io_byte = wrapper_read_io_byte,
+	.read_io_word = wrapper_read_io_word,
+	.read_io_longword = wrapper_read_io_longword,
+	.fast_read_io_byte = wrapper_fast_read_io_byte,
+	.fast_read_io_word = wrapper_fast_read_io_word,
+	.fast_read_io_longword = wrapper_fast_read_io_longword,
+	.write_io_byte = wrapper_write_io_byte,
+	.write_io_word = wrapper_write_io_word,
+	.write_io_longword = wrapper_write_io_longword,
+	.get_machine_id = wrapper_get_machine_id,
+	.get_pagesize = wrapper_get_pagesize,
+	.virt_to_bus = wrapper_virt_to_bus,
+	.bus_to_virt = wrapper_bus_to_virt,
+	.virt_to_phys = wrapper_virt_to_phys,
+	.phys_to_virt = wrapper_phys_to_virt,
+};

 /*
 * driver interface struct for the BaS framebuffer video driver
@@ -87,7 +141,7 @@ static struct generic_interface interfaces[] =
 		.description = "BaS SD Card driver",
 		.version = 0,
 		.revision = 1,
-		.interface.xhdi = &xhdi_call_interface 
+		.interface.xhdi = &xhdi_call_interface
 	},
 	{
 		.type = MCD_DRIVER,
@@ -105,7 +159,14 @@ static struct generic_interface interfaces[] =
 		.revision = 1,
 		.interface.fb = &framebuffer_interface,
 	},
-
+	{
+		.type = PCI_DRIVER,
+		.name = "PCI",
+		.description = "BaS PCI_BIOS driver",
+		.version = 0,
+		.revision = 1,
+		.interface.pci = &pci_interface,
+	},
 	/* insert new drivers here */

 	{
@@ -121,7 +182,7 @@ static struct driver_table bas_drivers =
 	.bas_version = MAJOR_VERSION,
 	.bas_revision = MINOR_VERSION,
 	.remove_handler = NULL,
-	.interfaces = { interfaces }
+	.interfaces = interfaces
 };

 void __attribute__((interrupt)) get_bas_drivers(void)
--- a/include/MCF5475.h
+++ b/include/MCF5475.h
@@ -16,7 +16,7 @@
 #ifndef __MCF5475_H__
 #define __MCF5475_H__

-#include <stdint.h>
+#include <bas_types.h>
 /***
 * MCF5475 Derivative Memory map definitions from linker command files:
 * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
--- a/include/MCF5475_MMU.h
+++ b/include/MCF5475_MMU.h
@@ -62,7 +62,7 @@
 /* Bit definitions and macros for MCF_MMU_MMUTR */
 #define MCF_MMU_MMUTR_V                      (0x1)
 #define MCF_MMU_MMUTR_SG                     (0x2)
-#define MCF_MMU_MMUTR_ID(x)                  (((x)&0xFF)<<0x2)
+#define MCF_MMU_MMUTR_ID(x)                  (((x) & 0xFF) << 0x2)
 #define MCF_MMU_MMUTR_VA(x)                  (((x)&0x3FFFFF)<<0xA)

 /* Bit definitions and macros for MCF_MMU_MMUDR */
@@ -71,9 +71,9 @@
 #define MCF_MMU_MMUDR_W                      (0x8)
 #define MCF_MMU_MMUDR_R                      (0x10)
 #define MCF_MMU_MMUDR_SP                     (0x20)
-#define MCF_MMU_MMUDR_CM(x)                  (((x)&0x3)<<0x6)
-#define MCF_MMU_MMUDR_SZ(x)                  (((x)&0x3)<<0x8)
-#define MCF_MMU_MMUDR_PA(x)                  (((x)&0x3FFFFF)<<0xA)
+#define MCF_MMU_MMUDR_CM(x)                  (((x) & 0x3) << 0x6)
+#define MCF_MMU_MMUDR_SZ(x)                  (((x) & 0x3) << 0x8)
+#define MCF_MMU_MMUDR_PA(x)                  (((x) & 0x3FFFFF) << 0xA)


 #endif /* __MCF5475_MMU_H__ */
--- a/include/bas_types.h
+++ b/include/bas_types.h
@@ -30,5 +30,6 @@

 #include <stdint.h>
 #include <stdbool.h>
+#include <stddef.h>		/* for sizeof() etc. */

 #endif /* BAS_TYPES_H_ */
--- a/include/cache.h
+++ b/include/cache.h
@@ -25,8 +25,7 @@
 *
 */

-#include <stdint.h>
-#include <stddef.h>
+#include <bas_types.h>

 /*
 * CACR Cache Control Register
@@ -54,6 +53,7 @@
 #define CF_CACR_ICINVA      (0x00000100) /* Instr Cache Invalidate All       */
 #define CF_CACR_IDSP        (0x00000080) /* Ins default supervisor-protect   */
 #define CF_CACR_EUSP        (0x00000020) /* Switch stacks in user mode       */
+#define CF_CACR_DF          (0x00000010) /* Disable FPU                      */

 #define _DCACHE_SET_MASK ((DCACHE_SIZE/64-1)<<CACHE_WAYS)
 #define _ICACHE_SET_MASK ((ICACHE_SIZE/64-1)<<CACHE_WAYS)
@@ -83,7 +83,7 @@ extern uint32_t cacr_get(void);
 extern void cacr_set(uint32_t);
 extern void flush_icache_range(void *address, size_t size);
 extern void flush_dcache_range(void *address, size_t size);
-
+extern void flush_cache_range(void *address, size_t size);


 #endif /* _CACHE_H_ */
--- a/include/diskio.h
+++ b/include/diskio.h
@@ -12,7 +12,7 @@ extern "C" {
 #define _USE_WRITE	1	/* 1: Enable disk_write function */
 #define _USE_IOCTL	1	/* 1: Enable disk_ioctl fucntion */

-#include <stdint.h>
+#include <bas_types.h>


 /* Status of Disk Functions */
--- a/include/dma.h
+++ b/include/dma.h
@@ -26,8 +26,8 @@
 #include "MCD_dma.h"
 #include "bas_string.h"

-#define DMA_INTC_LVL        6
-#define DMA_INTC_PRI        0
+#define DMA_INTC_LVL        5
+#define DMA_INTC_PRI        3


 void *dma_memcpy(void *dst, void *src, size_t n);
--- a/include/driver_vec.h
+++ b/include/driver_vec.h
@@ -27,15 +27,17 @@

 #include "xhdi_sd.h"
 #include "MCD_dma.h"
+#include "pci.h"

 enum driver_type
 {
-	END_OF_DRIVERS,		/* marks end of driver list */
 	BLOCKDEV_DRIVER,
 	CHARDEV_DRIVER,
-	VIDEO_DRIVER,
 	XHDI_DRIVER,
 	MCD_DRIVER,
+	VIDEO_DRIVER,
+	PCI_DRIVER,
+	END_OF_DRIVERS,		/* marks end of driver list */
 };

 struct generic_driver_interface
@@ -71,7 +73,7 @@ struct dma_driver_interface
 	void *(*dma_malloc)(uint32_t amount);
 	int32_t (*dma_free)(void *addr);
 };
-	
+
 struct xhdi_driver_interface
 {
 	uint32_t (*xhdivec)();
@@ -85,10 +87,10 @@ struct xhdi_driver_interface
 */
 struct fb_bitfield
 {
-    unsigned long offset;           /* beginning of bitfield    */
-    unsigned long length;           /* length of bitfield       */
-    unsigned long msb_right;        /* != 0 : Most significant bit is */
-				                    /* right */
+	unsigned long offset;           /* beginning of bitfield    */
+	unsigned long length;           /* length of bitfield       */
+	unsigned long msb_right;        /* != 0 : Most significant bit is */
+									/* right */
 };

 /*
@@ -96,107 +98,107 @@ struct fb_bitfield
 */
 struct fb_var_screeninfo
 {
-    unsigned long xres;             /* visible resolution       */
-    unsigned long yres;
-    unsigned long xres_virtual;     /* virtual resolution       */
-    unsigned long yres_virtual;
-    unsigned long xoffset;          /* offset from virtual to visible */
-    unsigned long yoffset;          /* resolution           */
+	unsigned long xres;             /* visible resolution       */
+	unsigned long yres;
+	unsigned long xres_virtual;     /* virtual resolution       */
+	unsigned long yres_virtual;
+	unsigned long xoffset;          /* offset from virtual to visible */
+	unsigned long yoffset;          /* resolution           */

-    unsigned long bits_per_pixel;   /* guess what           */
-    unsigned long grayscale;        /* != 0 Graylevels instead of colors */
+	unsigned long bits_per_pixel;   /* guess what           */
+	unsigned long grayscale;        /* != 0 Graylevels instead of colors */

-    struct fb_bitfield red;         /* bitfield in fb mem if true color, */
-    struct fb_bitfield green;       /* else only length is significant */
-    struct fb_bitfield blue;
-    struct fb_bitfield transp;      /* transparency         */
+	struct fb_bitfield red;         /* bitfield in fb mem if true color, */
+	struct fb_bitfield green;       /* else only length is significant */
+	struct fb_bitfield blue;
+	struct fb_bitfield transp;      /* transparency         */

-    unsigned long nonstd;           /* != 0 Non standard pixel format */
+	unsigned long nonstd;           /* != 0 Non standard pixel format */

-    unsigned long activate;         /* see FB_ACTIVATE_*        */
+	unsigned long activate;         /* see FB_ACTIVATE_*        */

-    unsigned long height;           /* height of picture in mm    */
-    unsigned long width;            /* width of picture in mm     */
+	unsigned long height;           /* height of picture in mm    */
+	unsigned long width;            /* width of picture in mm     */

-    unsigned long accel_flags;      /* (OBSOLETE) see fb_info.flags */
+	unsigned long accel_flags;      /* (OBSOLETE) see fb_info.flags */

-    /* Timing: All values in pixclocks, except pixclock (of course) */
-    unsigned long pixclock;         /* pixel clock in ps (pico seconds) */
-    unsigned long left_margin;      /* time from sync to picture    */
-    unsigned long right_margin;     /* time from picture to sync    */
-    unsigned long upper_margin;     /* time from sync to picture    */
-    unsigned long lower_margin;
-    unsigned long hsync_len;        /* length of horizontal sync    */
-    unsigned long vsync_len;        /* length of vertical sync  */
-    unsigned long sync;             /* see FB_SYNC_*        */
-    unsigned long vmode;            /* see FB_VMODE_*       */
-    unsigned long rotate;           /* angle we rotate counter clockwise */
-    unsigned long refresh;
-    unsigned long reserved[4];      /* Reserved for future compatibility */
+	/* Timing: All values in pixclocks, except pixclock (of course) */
+	unsigned long pixclock;         /* pixel clock in ps (pico seconds) */
+	unsigned long left_margin;      /* time from sync to picture    */
+	unsigned long right_margin;     /* time from picture to sync    */
+	unsigned long upper_margin;     /* time from sync to picture    */
+	unsigned long lower_margin;
+	unsigned long hsync_len;        /* length of horizontal sync    */
+	unsigned long vsync_len;        /* length of vertical sync  */
+	unsigned long sync;             /* see FB_SYNC_*        */
+	unsigned long vmode;            /* see FB_VMODE_*       */
+	unsigned long rotate;           /* angle we rotate counter clockwise */
+	unsigned long refresh;
+	unsigned long reserved[4];      /* Reserved for future compatibility */
 };

 struct fb_fix_screeninfo
 {
-    char id[16];                    /* identification string eg "TT Builtin" */
-    unsigned long smem_start;       /* Start of frame buffer mem */
-                                    /* (physical address) */
-    unsigned long smem_len;         /* Length of frame buffer mem */
-    unsigned long type;             /* see FB_TYPE_*        */
-    unsigned long type_aux;         /* Interleave for interleaved Planes */
-    unsigned long visual;           /* see FB_VISUAL_*      */
-    unsigned short xpanstep;        /* zero if no hardware panning  */
-    unsigned short ypanstep;        /* zero if no hardware panning  */
-    unsigned short ywrapstep;       /* zero if no hardware ywrap    */
-    unsigned long line_length;      /* length of a line in bytes    */
-    unsigned long mmio_start;       /* Start of Memory Mapped I/O   */
-                                    /* (physical address) */
-    unsigned long mmio_len;         /* Length of Memory Mapped I/O  */
-    unsigned long accel;            /* Indicate to driver which */
-                                    /*  specific chip/card we have  */
-    unsigned short reserved[3];     /* Reserved for future compatibility */
+	char id[16];                    /* identification string eg "TT Builtin" */
+	unsigned long smem_start;       /* Start of frame buffer mem */
+									/* (physical address) */
+	unsigned long smem_len;         /* Length of frame buffer mem */
+	unsigned long type;             /* see FB_TYPE_*        */
+	unsigned long type_aux;         /* Interleave for interleaved Planes */
+	unsigned long visual;           /* see FB_VISUAL_*      */
+	unsigned short xpanstep;        /* zero if no hardware panning  */
+	unsigned short ypanstep;        /* zero if no hardware panning  */
+	unsigned short ywrapstep;       /* zero if no hardware ywrap    */
+	unsigned long line_length;      /* length of a line in bytes    */
+	unsigned long mmio_start;       /* Start of Memory Mapped I/O   */
+									/* (physical address) */
+	unsigned long mmio_len;         /* Length of Memory Mapped I/O  */
+	unsigned long accel;            /* Indicate to driver which */
+									/*  specific chip/card we have  */
+	unsigned short reserved[3];     /* Reserved for future compatibility */
 };

 struct fb_chroma
 {
-    unsigned long redx; /* in fraction of 1024 */
-    unsigned long greenx;
-    unsigned long bluex;
-    unsigned long whitex;
-    unsigned long redy;
-    unsigned long greeny;
-    unsigned long bluey;
-    unsigned long whitey;
+	unsigned long redx; /* in fraction of 1024 */
+	unsigned long greenx;
+	unsigned long bluex;
+	unsigned long whitex;
+	unsigned long redy;
+	unsigned long greeny;
+	unsigned long bluey;
+	unsigned long whitey;
 };

 struct fb_monspecs
 {
-    struct fb_chroma chroma;
-    struct fb_videomode *modedb;    /* mode database */
-    unsigned char  manufacturer[4]; /* Manufacturer */
-    unsigned char  monitor[14];     /* Monitor String */
-    unsigned char  serial_no[14];   /* Serial Number */
-    unsigned char  ascii[14];       /* ? */
-    unsigned long modedb_len;       /* mode database length */
-    unsigned long model;            /* Monitor Model */
-    unsigned long serial;           /* Serial Number - Integer */
-    unsigned long year;             /* Year manufactured */
-    unsigned long week;             /* Week Manufactured */
-    unsigned long hfmin;            /* hfreq lower limit (Hz) */
-    unsigned long hfmax;            /* hfreq upper limit (Hz) */
-    unsigned long dclkmin;          /* pixelclock lower limit (Hz) */
-    unsigned long dclkmax;          /* pixelclock upper limit (Hz) */
-    unsigned short input;           /* display type - see FB_DISP_* */
-    unsigned short dpms;            /* DPMS support - see FB_DPMS_ */
-    unsigned short signal;          /* Signal Type - see FB_SIGNAL_* */
-    unsigned short vfmin;           /* vfreq lower limit (Hz) */
-    unsigned short vfmax;           /* vfreq upper limit (Hz) */
-    unsigned short gamma;           /* Gamma - in fractions of 100 */
-    unsigned short gtf  : 1;        /* supports GTF */
-    unsigned short misc;            /* Misc flags - see FB_MISC_* */
-    unsigned char  version;         /* EDID version... */
-    unsigned char  revision;        /* ...and revision */
-    unsigned char  max_x;           /* Maximum horizontal size (cm) */
-    unsigned char  max_y;           /* Maximum vertical size (cm) */
+	struct fb_chroma chroma;
+	struct fb_videomode *modedb;    /* mode database */
+	unsigned char  manufacturer[4]; /* Manufacturer */
+	unsigned char  monitor[14];     /* Monitor String */
+	unsigned char  serial_no[14];   /* Serial Number */
+	unsigned char  ascii[14];       /* ? */
+	unsigned long modedb_len;       /* mode database length */
+	unsigned long model;            /* Monitor Model */
+	unsigned long serial;           /* Serial Number - Integer */
+	unsigned long year;             /* Year manufactured */
+	unsigned long week;             /* Week Manufactured */
+	unsigned long hfmin;            /* hfreq lower limit (Hz) */
+	unsigned long hfmax;            /* hfreq upper limit (Hz) */
+	unsigned long dclkmin;          /* pixelclock lower limit (Hz) */
+	unsigned long dclkmax;          /* pixelclock upper limit (Hz) */
+	unsigned short input;           /* display type - see FB_DISP_* */
+	unsigned short dpms;            /* DPMS support - see FB_DPMS_ */
+	unsigned short signal;          /* Signal Type - see FB_SIGNAL_* */
+	unsigned short vfmin;           /* vfreq lower limit (Hz) */
+	unsigned short vfmax;           /* vfreq upper limit (Hz) */
+	unsigned short gamma;           /* Gamma - in fractions of 100 */
+	unsigned short gtf  : 1;        /* supports GTF */
+	unsigned short misc;            /* Misc flags - see FB_MISC_* */
+	unsigned char  version;         /* EDID version... */
+	unsigned char  revision;        /* ...and revision */
+	unsigned char  max_x;           /* Maximum horizontal size (cm) */
+	unsigned char  max_y;           /* Maximum vertical size (cm) */
 };

 struct framebuffer_driver_interface
@@ -204,12 +206,66 @@ struct framebuffer_driver_interface
 	struct fb_info **framebuffer_info;	/* pointer to an fb_info struct (defined in include/fb.h) */
 };

+struct pci_bios_interface {
+	uint32_t subjar;
+	uint32_t version;
+	/* Although we declare this functions as standard gcc functions (cdecl),
+	 * they expect paramenters inside registers (fastcall) unsupported by gcc m68k.
+	 * Caller will take care of parameters passing convention.
+	 */
+	int32_t (*find_pci_device)	(uint32_t id, uint16_t index);
+	int32_t (*find_pci_classcode)	(uint32_t class, uint16_t index);
+	int32_t (*read_config_byte)	(int32_t handle, uint16_t reg, uint8_t *address);
+	int32_t (*read_config_word)	(int32_t handle, uint16_t reg, uint16_t *address);
+	int32_t (*read_config_longword)	(int32_t handle, uint16_t reg, uint32_t *address);
+	uint8_t (*fast_read_config_byte)	(int32_t handle, uint16_t reg);
+	uint16_t (*fast_read_config_word)	(int32_t handle, uint16_t reg);
+	uint32_t (*fast_read_config_longword)	(int32_t handle, uint16_t reg);
+	int32_t (*write_config_byte)	(int32_t handle, uint16_t reg, uint16_t val);
+	int32_t (*write_config_word)	(int32_t handle, uint16_t reg, uint16_t val);
+	int32_t (*write_config_longword)	(int32_t handle, uint16_t reg, uint32_t val);
+	int32_t (*hook_interrupt)	(int32_t handle, uint32_t *routine, uint32_t *parameter);
+	int32_t (*unhook_interrupt)	(int32_t handle);
+	int32_t (*special_cycle)	(uint16_t bus, uint32_t data);
+	int32_t (*get_routing)	(int32_t handle);
+	int32_t (*set_interrupt)	(int32_t handle);
+	int32_t (*get_resource)	(int32_t handle);
+	int32_t (*get_card_used)	(int32_t handle, uint32_t *address);
+	int32_t (*set_card_used)	(int32_t handle, uint32_t *callback);
+	int32_t (*read_mem_byte)	(int32_t handle, uint32_t offset, uint8_t *address);
+	int32_t (*read_mem_word)	(int32_t handle, uint32_t offset, uint16_t *address);
+	int32_t (*read_mem_longword)	(int32_t handle, uint32_t offset, uint32_t *address);
+	uint8_t (*fast_read_mem_byte)	(int32_t handle, uint32_t offset);
+	uint16_t (*fast_read_mem_word)	(int32_t handle, uint32_t offset);
+	uint32_t (*fast_read_mem_longword)	(int32_t handle, uint32_t offset);
+	int32_t (*write_mem_byte)	(int32_t handle, uint32_t offset, uint16_t val);
+	int32_t (*write_mem_word)	(int32_t handle, uint32_t offset, uint16_t val);
+	int32_t (*write_mem_longword)	(int32_t handle, uint32_t offset, uint32_t val);
+	int32_t (*read_io_byte)	(int32_t handle, uint32_t offset, uint8_t *address);
+	int32_t (*read_io_word)	(int32_t handle, uint32_t offset, uint16_t *address);
+	int32_t (*read_io_longword)	(int32_t handle, uint32_t offset, uint32_t *address);
+	uint8_t (*fast_read_io_byte)	(int32_t handle, uint32_t offset);
+	uint16_t (*fast_read_io_word)	(int32_t handle, uint32_t offset);
+	uint32_t (*fast_read_io_longword)	(int32_t handle, uint32_t offset);
+	int32_t (*write_io_byte)	(int32_t handle, uint32_t offset, uint16_t val);
+	int32_t (*write_io_word)	(int32_t handle, uint32_t offset, uint16_t val);
+	int32_t (*write_io_longword)	(int32_t handle, uint32_t offset, uint32_t val);
+	int32_t (*get_machine_id)	(void);
+	int32_t (*get_pagesize)	(void);
+	int32_t (*virt_to_bus)	(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+	int32_t (*bus_to_virt)	(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+	int32_t (*virt_to_phys)	(uint32_t address, PCI_CONV_ADR *pointer);
+	int32_t (*phys_to_virt)	(uint32_t address, PCI_CONV_ADR *pointer);
+//	int32_t reserved[2];
+};
+
 union interface
 {
 	struct generic_driver_interface *gdi;
 	struct xhdi_driver_interface *xhdi;
 	struct dma_driver_interface *dma;
 	struct framebuffer_driver_interface *fb;
+	struct pci_bios_interface *pci;
 };

 struct generic_interface
@@ -227,7 +283,7 @@ struct driver_table
 	uint32_t bas_version;
 	uint32_t bas_revision;
 	uint32_t (*remove_handler)();			/* calling this will disable the BaS' hook into trap #0 */
-	struct generic_interface *interfaces[];
+	struct generic_interface *interfaces;
 };


--- a/include/ehci.h
+++ b/include/ehci.h
@@ -51,7 +51,7 @@ struct ehci_hccr {
 #define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
 #define HC_VERSION(p)		(((p) >> 16) & 0xffff)
 	uint32_t cr_hcsparams;
-#define HCS_PPC(p)		((p) & (1 << 4))
+#define HCS_PPC(p)			((p) & (1 << 4))
 #define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
 #define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
 	uint32_t cr_hccparams;
@@ -70,20 +70,20 @@ struct ehci_hcor {
 #define CMD_RUN		(1 << 0)		/* start/stop HC */
 	uint32_t or_usbsts;
 #define	STD_ASS		(1 << 15)
-#define STS_PSSTAT (1 << 14)
-#define STS_RECL  ( 1 << 13)
+#define STS_PSSTAT	(1 << 14)
+#define STS_RECL	(1 << 13)
 #define STS_HALT	(1 << 12)
-#define STS_IAA (1 << 5)
-#define STS_HSE (1 << 4)
-#define STS_FLR (1 << 3)
-#define STS_PCD (1 << 2)
+#define STS_IAA		(1 << 5)
+#define STS_HSE		(1 << 4)
+#define STS_FLR		(1 << 3)
+#define STS_PCD		(1 << 2)
 #define STS_USBERRINT (1 << 1)
-#define STS_USBINT (1 << 0)
+#define STS_USBINT	(1 << 0)
 	uint32_t or_usbintr;
-#define INTR_IAAE (1 << 5)
-#define INTR_HSEE (1 << 4)
-#define INTR_FLRE (1 << 3)
-#define INTR_PCDE (1 << 2)
+#define INTR_IAAE	(1 << 5)
+#define INTR_HSEE	(1 << 4)
+#define INTR_FLRE	(1 << 3)
+#define INTR_PCDE	(1 << 2)
 #define INTR_USBERRINTE (1 << 1)
 #define INTR_USBINTE (1 << 0)
 	uint32_t or_frindex;
@@ -97,14 +97,15 @@ struct ehci_hcor {
 	uint32_t or_systune;
 } __attribute__ ((packed));

-#define USBMODE		0x68		/* USB Device mode */
+#define USBMODE		0x68			/* USB Device mode */
 #define USBMODE_SDIS	(1 << 3)	/* Stream disable */
-#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
+#define USBMODE_BE	(1 << 2)		/* BE/LE endiannes select */
 #define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
 #define USBMODE_CM_IDLE	(0 << 0)	/* idle state */

 /* Interface descriptor */
-struct usb_linux_interface_descriptor {
+struct usb_linux_interface_descriptor
+{
 	unsigned char	bLength;
 	unsigned char	bDescriptorType;
 	unsigned char	bInterfaceNumber;
@@ -117,7 +118,8 @@ struct usb_linux_interface_descriptor {
 } __attribute__ ((packed));

 /* Configuration descriptor information.. */
-struct usb_linux_config_descriptor {
+struct usb_linux_config_descriptor
+{
 	unsigned char	bLength;
 	unsigned char	bDescriptorType;
 	unsigned short	wTotalLength;
@@ -129,11 +131,11 @@ struct usb_linux_config_descriptor {
 } __attribute__ ((packed));

 #if defined CONFIG_EHCI_DESC_BIG_ENDIAN
-#define	ehci_readl(x)		(*((volatile u32 *)(x)))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
+#define	ehci_readl(x)		(*((volatile uint32_t *)(x)))
+#define ehci_writel(a, b)	(*((volatile uint32_t *)(a)) = ((volatile uint32_t) b))
 #else
-#define ehci_readl(x)		swpl((*((volatile u32 *)(x))))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = swpl(((volatile u32)b)))
+#define ehci_readl(x)		swpl((*((volatile uint32_t *)(x))))
+#define ehci_writel(a, b)	(*((volatile uint32_t *)(a)) = swpl(((volatile uint32_t) b)))
 #endif

 #if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
@@ -147,18 +149,18 @@ struct usb_linux_config_descriptor {
 #define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
 #define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
 #define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
-#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
-#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
-#define EHCI_PS_LS		(3 << 10)	/* RO line status */
-#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
-#define EHCI_PS_SUSP	(1 << 7)	/* RW suspend */
-#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
-#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
-#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
-#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
-#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
-#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
-#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
+#define EHCI_PS_PO			(1 << 13)	/* RW port owner */
+#define EHCI_PS_PP			(1 << 12)	/* RW,RO port power */
+#define EHCI_PS_LS			(3 << 10)	/* RO line status */
+#define EHCI_PS_PR			(1 << 8)	/* RW port reset */
+#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
+#define EHCI_PS_FPR			(1 << 6)	/* RW force port resume */
+#define EHCI_PS_OCC			(1 << 5)	/* RWC over current change */
+#define EHCI_PS_OCA			(1 << 4)	/* RO over current active */
+#define EHCI_PS_PEC			(1 << 3)	/* RWC port enable change */
+#define EHCI_PS_PE			(1 << 2)	/* RW port enable */
+#define EHCI_PS_CSC			(1 << 1)	/* RWC connect status change */
+#define EHCI_PS_CS			(1 << 0)	/* RO connect status */
 #define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)

 #define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
@@ -174,7 +176,8 @@ struct usb_linux_config_descriptor {
 */

 /* Queue Element Transfer Descriptor (qTD). */
-struct qTD {
+struct qTD
+{
 	uint32_t qt_next;
 #define	QT_NEXT_TERMINATE	1
 	uint32_t qt_altnext;
@@ -183,7 +186,8 @@ struct qTD {
 };

 /* Queue Head (QH). */
-struct QH {
+struct QH
+{
 	uint32_t qh_link;
 #define	QH_LINK_TERMINATE	1
 #define	QH_LINK_TYPE_ITD	0
--- a/include/exceptions.h
+++ b/include/exceptions.h
@@ -1,7 +1,7 @@
 #ifndef _EXCEPTIONS_H_
 #define _EXCEPTIONS_H_

-#include <stdint.h>
+#include <bas_types.h>

 static inline uint32_t set_ipl(uint32_t ipl)
 {
@@ -19,7 +19,7 @@ static inline uint32_t set_ipl(uint32_t ipl)
 		"		lsr.l	#8,%[ret]\r\n"			/* shift them to position */
 		: [ret] "=&d" (ret)		/* output */
 		: [ipl] "d" (ipl)		/* input */
-		: "d0"	/* clobber */
+		: "cc", "d0"	/* clobber */
 	);

 	return ret;
--- a/include/fb.h
+++ b/include/fb.h
@@ -528,7 +528,6 @@ struct fb_videomode {
 extern const struct fb_videomode vesa_modes[];

 /* timer */
-extern void udelay(long usec);
 #ifdef COLDFIRE
 #ifdef MCF5445X
 #define US_TO_TIMER(a) (a)
@@ -541,6 +540,7 @@ extern void udelay(long usec);
 #define US_TO_TIMER(a) (((a)*256)/5000)
 #define TIMER_TO_US(a) (((a)*5000)/256)
 #endif
+
 extern void start_timeout(void);
 extern int end_timeout(long msec);
 extern void mdelay(long msec);
--- a/include/ff.h
+++ b/include/ff.h
@@ -21,7 +21,7 @@
 extern "C" {
 #endif

-#include <stdint.h>
+#include <bas_types.h>
 #include <ffconf.h>		/* FatFs configuration options */

 #if _FATFS != _FFCONF
--- a/include/font.h
+++ b/include/font.h
@@ -0,0 +1,98 @@
+/*
+ * font.h - font specific definitions
+ *
+ * Copyright (c) 2001 Lineo, Inc.
+ * Copyright (c) 2004 by Authors:
+ *
+ * Authors:
+ *  MAD     Martin Doering
+ *
+ * This file is distributed under the GPL, version 2 or at your
+ * option any later version.  See doc/license.txt for details.
+ */
+
+#ifndef FONT_H
+#define FONT_H
+
+#include <stdint.h>
+
+/* font header flags */
+
+#define F_DEFAULT 1     /* this is the default font (face and size) */
+#define F_HORZ_OFF  2   /* there are left and right offset tables */
+#define F_STDFORM  4    /* is the font in standard format */
+#define F_MONOSPACE 8   /* is the font monospaced */
+
+/* font style bits */
+
+#define F_THICKEN 1
+#define F_LIGHT 2
+#define F_SKEW  4
+#define F_UNDER 8
+#define F_OUTLINE 16
+#define F_SHADOW        32
+
+/* font specific linea variables */
+
+extern const uint16_t *v_fnt_ad;   /* address of current monospace font */
+extern const uint16_t *v_off_ad;   /* address of font offset table */
+extern uint16_t v_fnt_nd;          /* ascii code of last cell in font */
+extern uint16_t v_fnt_st;          /* ascii code of first cell in font */
+extern uint16_t v_fnt_wr;          /* font cell wrap */
+
+/* character cell specific linea variables */
+
+extern uint16_t    v_cel_ht;       /* cell height (width is 8) */
+extern uint16_t    v_cel_mx;       /* needed by MiNT: columns on the screen minus 1 */
+extern uint16_t    v_cel_my;       /* needed by MiNT: rows on the screen minus 1 */
+extern uint16_t    v_cel_wr;       /* needed by MiNT: length (in int8_ts) of a line of characters */
+
+/*
+ * font_ring is a struct of four pointers, each of which points to
+ * a list of font headers linked together to form a string.
+ */
+
+extern struct font_head *font_ring[4];  /* Ring of available fonts */
+extern int16_t font_count;                 /* all three fonts and NULL */
+
+/* the font header descibes a font */
+
+struct font_head {
+    int16_t font_id;
+    int16_t point;
+    int8_t name[32];
+    uint16_t first_ade;
+    uint16_t last_ade;
+    uint16_t top;
+    uint16_t ascent;
+    uint16_t half;
+    uint16_t descent;
+    uint16_t bottom;
+    uint16_t max_char_width;
+    uint16_t max_cell_width;
+    uint16_t left_offset;          /* amount character slants left when skewed */
+    uint16_t right_offset;         /* amount character slants right */
+    uint16_t thicken;              /* number of pixels to smear */
+    uint16_t ul_size;              /* size of the underline */
+    uint16_t lighten;              /* mask to and with to lighten  */
+    uint16_t skew;                 /* mask for skewing */
+    uint16_t flags;
+
+    const uint8_t *hor_table;     /* horizontal offsets */
+    const uint16_t *off_table;     /* character offsets  */
+    const uint16_t *dat_table;     /* character definitions */
+    uint16_t form_width;
+    uint16_t form_height;
+
+    struct font_head *next_font;/* pointer to next font */
+    uint16_t font_seg;
+};
+
+
+
+/* prototypes */
+
+void font_init(void);           /* initialize BIOS font ring */
+void font_set_default(void);    /* choose the default font */
+
+#endif /* FONT_H */
--- a/include/interrupts.h
+++ b/include/interrupts.h
@@ -79,20 +79,20 @@
 #define	INT_SOURCE_GPT0				62	// GPT0 timer interrupt


-#define FEC0_INTC_LVL	1			/* interrupt level for FEC0 */
-#define FEC0_INTC_PRI	2			/* interrupt priority for FEC0 */
+#define FEC0_INTC_LVL	5			/* interrupt level for FEC0 */
+#define FEC0_INTC_PRI	1			/* interrupt priority for FEC0 */

-#define FEC1_INTC_LVL	1			/* interrupt level for FEC1 */
-#define FEC1_INTC_PRI	2			/* interrupt priority for FEC1 */
+#define FEC1_INTC_LVL	5			/* interrupt level for FEC1 */
+#define FEC1_INTC_PRI	0			/* interrupt priority for FEC1 */

 #define FEC_INTC_LVL(x)		((x == 0) ? FEC0_INTC_LVL : FEC1_INTC_LVL)
 #define FEC_INTC_PRI(x)		((x == 0) ? FEC0_INTC_PRI : FEC1_INTC_PRI)

 #define FEC0RX_DMA_PRI      5
-#define FEC1RX_DMA_PRI      5
+#define FEC1RX_DMA_PRI      3
 #define FECRX_DMA_PRI(x)    ((x == 0) ? FEC0RX_DMA_PRI : FEC1RX_DMA_PRI)
 #define FEC0TX_DMA_PRI      6
-#define FEC1TX_DMA_PRI      6
+#define FEC1TX_DMA_PRI      4
 #define FECTX_DMA_PRI(x)    ((x == 0) ? FEC0TX_DMA_PRI : FEC1TX_DMA_PRI)

 extern int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority, uint8_t intr, void (*handler)(void));
@@ -104,4 +104,5 @@ extern void isr_init(void);
 extern int isr_register_handler(int vector, int (*handler)(void *, void *), void *hdev, void *harg);
 extern void isr_remove_handler(int (*handler)(void *, void *));
 extern bool isr_execute_handler(int vector);
+extern int pic_interrupt_handler(void *arg1, void *arg2);
 #endif /* _INTERRUPTS_H_ */
--- a/include/mmu.h
+++ b/include/mmu.h
@@ -24,6 +24,7 @@
 #ifndef _MMU_H_
 #define _MMU_H_

+#include <stddef.h>
 #include "bas_types.h"

 /*
@@ -54,10 +55,14 @@
 /*
 * MMU page sizes
 */
-#define MMU_PAGE_SIZE_1M	0
-#define MMU_PAGE_SIZE_4K	1
-#define MMU_PAGE_SIZE_8K	2
-#define MMU_PAGE_SIZE_1K	3
+
+enum mmu_page_size
+{
+	MMU_PAGE_SIZE_1M	= 0,
+	MMU_PAGE_SIZE_4K	= 1,
+	MMU_PAGE_SIZE_8K	= 2,
+	MMU_PAGE_SIZE_1K	= 3
+};

 /*
 * cache modes
@@ -78,13 +83,14 @@
 #define	ACCESS_WRITE	(1 << 1)
 #define ACCESS_EXECUTE	(1 << 2)

-struct map_flags
+struct mmu_map_flags
 {
 	unsigned cache_mode:2;
 	unsigned protection:1;
 	unsigned page_id:8;
 	unsigned access:3;
-	unsigned unused:18;
+	unsigned locked:1;
+	unsigned unused:17;
 };

 /*
@@ -94,6 +100,6 @@ extern long video_tlb;
 extern long video_sbt;

 extern void mmu_init(void);
-extern void mmu_map_page(uint32_t virt, uint32_t phys, uint32_t map_size, struct map_flags flags);
+extern int mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, const struct mmu_map_flags *flags);

 #endif /* _MMU_H_ */
--- a/include/nbuf.h
+++ b/include/nbuf.h
@@ -10,7 +10,6 @@

 #include "bas_types.h"

-/********************************************************************/
 /*
 * Include the Queue structure definitions
 */
--- a/include/net_timer.h
+++ b/include/net_timer.h
@@ -8,9 +8,7 @@
 #ifndef _TIMER_H_
 #define _TIMER_H_

-#include <stdint.h>
-#include <stdbool.h>
-#include <stddef.h>
+#include <bas_types.h>

 typedef struct
 {
--- a/include/ohci.h
+++ b/include/ohci.h
@@ -9,7 +9,8 @@
 
 #define USB_OHCI_MAX_ROOT_PORTS	4

-static int cc_to_error[16] = {
+static int cc_to_error[16] =
+{

 /* mapping of the OHCI CC status to error codes */
 	/* No  Error  */	       0,
@@ -30,8 +31,9 @@ static int cc_to_error[16] = {
 	/* Not Access */	       -1
 };

-#ifdef DEBUG
-static const char *cc_to_string[16] = {
+#ifdef DEBUG_OHCI
+static const char *cc_to_string[16] =
+{
 	"No Error",
 	"CRC: Last data packet from endpoint contained a CRC error.",
 	"BITSTUFFING:\r\nLast data packet from endpoint contained a bit stuffing violation",
@@ -62,7 +64,7 @@ static const char *cc_to_string[16] = {
 	"NOT ACCESSED:\r\nThis code is set by software before the TD is placed\r\n" \
 		     "on a list to be processed by the HC.(2)",
 };
-#endif /* DEBUG */
+#endif /* DEBUG_OHCI */

 /* ED States */

@@ -73,7 +75,8 @@ static const char *cc_to_string[16] = {
 #define ED_URB_DEL	0x08

 /* usb_ohci_ed */
-struct ed {
+struct ed
+{
 	uint32_t hwINFO;
 	uint32_t hwTailP;
 	uint32_t hwHeadP;
@@ -134,7 +137,8 @@ typedef struct ed ed_t;

 #define MAXPSW 1

-struct td {
+struct td
+{
 	uint32_t hwINFO;
 	uint32_t hwCBP;		/* Current Buffer Pointer */
 	uint32_t hwNextTD;		/* Next TD Pointer */
@@ -162,7 +166,8 @@ typedef struct td td_t;
 */

 #define NUM_INTS 32	/* part of the OHCI standard */
-struct ohci_hcca {
+struct ohci_hcca
+{
 	uint32_t	int_table[NUM_INTS];	/* Interrupt ED table */
 #if defined(CONFIG_MPC5200)
 	uint16_t	pad1;			/* set to 0 on each frame_no change */
@@ -180,7 +185,8 @@ struct ohci_hcca {
 * region.  This is Memory Mapped I/O.	You must use the readl() and
 * writel() macros defined in asm/io.h to access these!!
 */
-struct ohci_regs {
+struct ohci_regs
+{
 	/* control and status registers */
 	uint32_t	revision;
 	uint32_t	control;
@@ -203,7 +209,8 @@ struct ohci_regs {
 	uint32_t	periodicstart;
 	uint32_t	lsthresh;
 	/* Root hub ports */
-	struct	ohci_roothub_regs {
+    struct	ohci_roothub_regs
+    {
 		uint32_t	a;
 		uint32_t	b;
 		uint32_t	status;
@@ -263,7 +270,8 @@ struct ohci_regs {


 /* Virtual Root HUB */
-struct virt_root_hub {
+struct virt_root_hub
+{
 	int devnum; /* Address of Root Hub endpoint */
 	void *dev;  /* was urb */
 	void *int_addr;
@@ -383,7 +391,8 @@ typedef struct

 #define NUM_EDS 8		/* num of preallocated endpoint descriptors */

-struct ohci_device {
+struct ohci_device
+{
 	ed_t	ed[NUM_EDS];
 	int ed_cnt;
 };
@@ -395,7 +404,8 @@ struct ohci_device {
 * a subset of what the full implementation needs. (Linus)
 */

-typedef struct ohci {
+typedef struct ohci
+{
 	/* ------- common part -------- */
 	long handle;              /* PCI BIOS */
 	const struct pci_device_id *ent;
@@ -443,7 +453,6 @@ static int ep_link(ohci_t * ohci, ed_t * ed);
 static int ep_unlink(ohci_t * ohci, ed_t * ed);
 static ed_t * ep_add_ed(ohci_t * ohci, struct usb_device * usb_dev, uint32_t pipe, int interval, int load);

-/*-------------------------------------------------------------------------*/

 /* we need more TDs than EDs */
 #define NUM_TD 64
--- a/include/part.h
+++ b/include/part.h
@@ -26,7 +26,8 @@
 typedef unsigned long long uint64_t;
 typedef unsigned long lbaint_t;

-typedef struct block_dev_desc {
+typedef struct block_dev_desc
+{
 	int		if_type;	/* type of the interface */
 	int		dev;		/* device number */
 	unsigned char	part_type;	/* partition type */
--- a/include/pci.h
+++ b/include/pci.h
@@ -21,7 +21,7 @@
 *      Author: Markus Fröschle
 */

-#include <stdint.h>
+#include <bas_types.h>
 #include "util.h" 	/* for swpX() */

 #define	 PCI_MEMORY_OFFSET	(0x80000000)
@@ -44,13 +44,13 @@
 #define PCIHTR                0x0E   /* PCI Header Type Register            */
 #define PCIBISTR              0x0F   /* PCI Build-In Self Test Register     */
 #define PCIBAR0               0x10   /* PCI Base Address Register for Memory
-                                        Accesses to Local, Runtime, and DMA */
+										Accesses to Local, Runtime, and DMA */
 #define PCIBAR1               0x14   /* PCI Base Address Register for I/O
-                                        Accesses to Local, Runtime, and DMA */
+										Accesses to Local, Runtime, and DMA */
 #define PCIBAR2               0x18   /* PCI Base Address Register for Memory
-                                        Accesses to Local Address Space 0   */
+										Accesses to Local Address Space 0   */
 #define PCIBAR3               0x1C   /* PCI Base Address Register for Memory
-                                        Accesses to Local Address Space 1   */ 
+										Accesses to Local Address Space 1   */
 #define PCIBAR4               0x20   /* PCI Base Address Register, reserved */
 #define PCIBAR5               0x24   /* PCI Base Address Register, reserved */
 #define PCICIS                0x28   /* PCI Cardbus CIS Pointer, not support*/
@@ -64,7 +64,7 @@
 #define PCIMLR                0x3F   /* PCI Max_Lat Register                */
 #define PMCAPID               0x40   /* Power Management Capability ID      */
 #define PMNEXT                0x41   /* Power Management Next Capability
-                                        Pointer                             */
+										Pointer                             */
 #define PMC                   0x42   /* Power Management Capabilities       */
 #define PMCSR                 0x44   /* Power Management Control/Status     */
 #define PMCSR_BSE             0x46   /* PMCSR Bridge Support Extensions     */
@@ -74,7 +74,7 @@
 #define HS_CSR                0x4A   /* Hot Swap Control/Status             */
 #define PVPDCNTL              0x4C   /* PCI Vital Product Data Control      */
 #define PVPD_NEXT             0x4D   /* PCI Vital Product Data Next
-                                        Capability Pointer                  */
+										Capability Pointer                  */
 #define PVPDAD                0x4E   /* PCI Vital Product Data Address      */
 #define PVPDATA               0x50   /* PCI VPD Data                        */

@@ -125,18 +125,18 @@

 struct pci_rd          /* structure of resource descriptor    */
 {
-    unsigned short next;               /* length of the following structure   */
-    unsigned short flags;              /* type of resource and misc. flags    */
-    unsigned long start;               /* start-address of resource           */
-    unsigned long length;              /* length of resource                  */
-    unsigned long offset;              /* offset PCI to phys. CPU Address     */
-    unsigned long dmaoffset;           /* offset for DMA-transfers            */
+	unsigned short next;               /* length of the following structure   */
+	unsigned short flags;              /* type of resource and misc. flags    */
+	unsigned long start;               /* start-address of resource           */
+	unsigned long length;              /* length of resource                  */
+	unsigned long offset;              /* offset PCI to phys. CPU Address     */
+	unsigned long dmaoffset;           /* offset for DMA-transfers            */
 } __attribute__ ((packed));

 typedef struct                       /* structure of address conversion     */
 {
-    unsigned long adr;                 /* calculated address (CPU<->PCI)      */
-    unsigned long len;                 /* length of memory range              */
+	unsigned long adr;                 /* calculated address (CPU<->PCI)      */
+	unsigned long len;                 /* length of memory range              */
 } PCI_CONV_ADR;

 /******************************************************************************/
@@ -191,8 +191,8 @@ typedef struct                       /* structure of address conversion     */
 #define PCI_COMMAND(i)		(((i) >> 16) & 0xffff)

 /* register 0x08 macros */
-#define PCI_CLASS_CODE(i)	((swpl((i)) & 0xff000000) >> 24)
-#define PCI_SUBCLASS(i)		((swpl((i)) & 0x00ff0000) >> 16)
+#define PCI_CLASS_CODE(i)	((swpl((i)) & 0xffff0000) >> 16)
+#define PCI_SUBCLASS(i)		((swpl((i)) & 0xffffff00) >> 8)
 #define PCI_PROG_IF(i)		((swpl((i)) & 0x0000ff00) >> 8)
 #define PCI_REVISION_ID(i)	((swpl((i)) & 0x000000ff))

@@ -243,14 +243,98 @@ extern int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t va
 extern int32_t pci_write_config_word(int32_t handle, int offset, uint16_t value);
 extern int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value);

-extern struct pci_rd *pci_get_resource(int32_t handle);
 extern int32_t pci_hook_interrupt(int32_t handle, void *interrupt_handler, void *parameter);
 extern int32_t pci_unhook_interrupt(int32_t handle);

+extern struct pci_rd *pci_get_resource(int32_t handle);
+
+/*
+ * Not implemented PCI_BIOS functions
+ */
+extern uint8_t pci_fast_read_config_byte(int32_t handle, uint16_t reg);
+extern uint16_t pci_fast_read_config_word(int32_t handle, uint16_t reg);
+extern uint32_t pci_fast_read_config_longword(int32_t handle, uint16_t reg);
+extern int32_t pci_special_cycle(uint16_t bus, uint32_t data);
+extern int32_t pci_get_routing(int32_t handle);
+extern int32_t pci_set_interrupt(int32_t handle);
+extern int32_t pci_get_card_used(int32_t handle, uint32_t *address);
+extern int32_t pci_set_card_used(int32_t handle, uint32_t *callback);
+extern int32_t pci_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address);
+extern int32_t pci_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address);
+extern int32_t pci_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address);
+extern uint8_t pci_fast_read_mem_byte(int32_t handle, uint32_t offset);
+extern uint16_t pci_fast_read_mem_word(int32_t handle, uint32_t offset);
+extern uint32_t pci_fast_read_mem_longword(int32_t handle, uint32_t offset);
+extern int32_t pci_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t pci_write_mem_word(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t pci_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val);
+extern int32_t pci_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address);
+extern int32_t pci_read_io_word(int32_t handle, uint32_t offset, uint16_t *address);
+extern int32_t pci_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address);
+extern uint8_t pci_fast_read_io_byte(int32_t handle, uint32_t offset);
+extern uint16_t pci_fast_read_io_word(int32_t handle, uint32_t offset);
+extern uint32_t pci_fast_read_io_longword(int32_t handle, uint32_t offset);
+extern int32_t pci_write_io_byte(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t pci_write_io_word(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t pci_write_io_longword(int32_t handle, uint32_t offset, uint32_t val);
+extern int32_t pci_get_machine_id(void);
+extern int32_t pci_get_pagesize(void);
+extern int32_t pci_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+extern int32_t pci_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+extern int32_t pci_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
+extern int32_t pci_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
+
+/*
+ * prototypes for PCI wrapper routines
+ */
+extern int32_t wrapper_find_pci_device(uint32_t id, uint16_t index);
+extern int32_t wrapper_find_pci_classcode(uint32_t class, uint16_t index);
+extern int32_t wrapper_read_config_byte(int32_t handle, uint16_t reg, uint8_t *address);
+extern int32_t wrapper_read_config_word(int32_t handle, uint16_t reg, uint16_t *address);
+extern int32_t wrapper_read_config_longword(int32_t handle, uint16_t reg, uint32_t *address);
+extern uint8_t wrapper_fast_read_config_byte(int32_t handle, uint16_t reg);
+extern uint16_t wrapper_fast_read_config_word(int32_t handle, uint16_t reg);
+extern uint32_t wrapper_fast_read_config_longword(int32_t handle, uint16_t reg);
+extern int32_t wrapper_write_config_byte(int32_t handle, uint16_t reg, uint16_t val);
+extern int32_t wrapper_write_config_word(int32_t handle, uint16_t reg, uint16_t val);
+extern int32_t wrapper_write_config_longword(int32_t handle, uint16_t reg, uint32_t val);
+extern int32_t wrapper_hook_interrupt(int32_t handle, uint32_t *routine, uint32_t *parameter);
+extern int32_t wrapper_unhook_interrupt(int32_t handle);
+extern int32_t wrapper_special_cycle(uint16_t bus, uint32_t data);
+extern int32_t wrapper_get_routing(int32_t handle);
+extern int32_t wrapper_set_interrupt(int32_t handle);
+extern int32_t wrapper_get_resource(int32_t handle);
+extern int32_t wrapper_get_card_used(int32_t handle, uint32_t *address);
+extern int32_t wrapper_set_card_used(int32_t handle, uint32_t *callback);
+extern int32_t wrapper_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address);
+extern int32_t wrapper_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address);
+extern int32_t wrapper_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address);
+extern uint8_t wrapper_fast_read_mem_byte(int32_t handle, uint32_t offset);
+extern uint16_t wrapper_fast_read_mem_word(int32_t handle, uint32_t offset);
+extern uint32_t wrapper_fast_read_mem_longword(int32_t handle, uint32_t offset);
+extern int32_t wrapper_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t wrapper_write_mem_word(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t wrapper_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val);
+extern int32_t wrapper_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address);
+extern int32_t wrapper_read_io_word(int32_t handle, uint32_t offset, uint16_t *address);
+extern int32_t wrapper_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address);
+extern uint8_t wrapper_fast_read_io_byte(int32_t handle, uint32_t offset);
+extern uint16_t wrapper_fast_read_io_word(int32_t handle, uint32_t offset);
+extern uint32_t wrapper_fast_read_io_longword(int32_t handle, uint32_t offset);
+extern int32_t wrapper_write_io_byte(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t wrapper_write_io_word(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t wrapper_write_io_longword(int32_t handle, uint32_t offset, uint32_t val);
+extern int32_t wrapper_get_machine_id(void);
+extern int32_t wrapper_get_pagesize(void);
+extern int32_t wrapper_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+extern int32_t wrapper_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+extern int32_t wrapper_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
+extern int32_t wrapper_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
+
 #define PCI_MK_CONF_ADDR(bus, device, function)	(MCF_PCI_PCICAR_E | \
 												((bus) << 16) | \
 												((device << 8) | \
-												(function)) 
+												(function))

 #define PCI_HANDLE(bus, slot, function)	(0 | ((bus & 0xff) << 10 | (slot & 0x1f) << 3 | (function & 7)))
 #define PCI_BUS_FROM_HANDLE(h)				(((h) & 0xff00) >> 10)
--- a/include/queue.h
+++ b/include/queue.h
@@ -8,8 +8,6 @@
 #ifndef _QUEUE_H_
 #define _QUEUE_H_

-/********************************************************************/
-
 /* 
 * Individual queue node
 */
--- a/include/radeonfb.h
+++ b/include/radeonfb.h
@@ -10,7 +10,9 @@
 #include "i2c-algo-bit.h"
 #include "util.h"			/* for swpX() */
 #include "wait.h"
+
 //#include "radeon_theatre.h"
+
 #include "radeon_reg.h"

 /* Buffer are aligned on 4096 byte boundaries */
--- a/include/sd_card.h
+++ b/include/sd_card.h
@@ -31,7 +31,7 @@
 #define _SD_CARD_H_

 #include <MCF5475.h>
-#include <stdint.h>
+#include <bas_types.h>

 extern void sd_card_init(void);

--- a/include/usb.h
+++ b/include/usb.h
@@ -26,7 +26,6 @@
 #ifndef _USB_H_
 #define _USB_H_

-//#include <stdlib.h>
 #include <bas_string.h>
 #include "driver_mem.h"
 #include "pci.h"
@@ -37,14 +36,6 @@

 extern long *tab_funcs_pci;

-#define in8(addr)		Fast_read_mem_byte(usb_handle,addr)
-#define in16r(addr)		Fast_read_mem_word(usb_handle,addr)
-#define in32r(addr)		Fast_read_mem_longword(usb_handle,addr)
-#define out8(addr,val)	Write_mem_byte(usb_handle,addr,val)
-#define out16r(addr,val)	Write_mem_word(usb_handle,addr,val)
-#define out32r(addr,val)	Write_mem_longword(usb_handle,addr,val)
-
-
 #define __u8 uint8_t
 #define __u16 uint16_t
 #define __u32 uint32_t
@@ -74,15 +65,19 @@ extern int sprintD(char *s, const char *fmt, ...);

 #define USB_CNTL_TIMEOUT 100 /* 100ms timeout */

+#define USB_BUFSIZ	512
+
 /* String descriptor */
-struct usb_string_descriptor {
+struct usb_string_descriptor
+{
 	uint8_t	bLength;
 	uint8_t	bDescriptorType;
 	uint16_t	wData[1];
 } __attribute__ ((packed));

 /* device request (setup) */
-struct devrequest {
+struct devrequest
+{
 	uint8_t	requesttype;
 	uint8_t	request;
 	uint16_t	value;
@@ -91,13 +86,15 @@ struct devrequest {
 } __attribute__ ((packed));

 /* All standard descriptors have these 2 fields in common */
-struct usb_descriptor_header {
+struct usb_descriptor_header
+{
 	uint8_t	bLength;
 	uint8_t	bDescriptorType;
 } __attribute__ ((packed));

 /* Device descriptor */
-struct usb_device_descriptor {
+struct usb_device_descriptor
+{
 	uint8_t	bLength;
 	uint8_t	bDescriptorType;
 	uint16_t	bcdUSB;
@@ -115,7 +112,8 @@ struct usb_device_descriptor {
 } __attribute__ ((packed));

 /* Endpoint descriptor */
-struct usb_endpoint_descriptor {
+struct usb_endpoint_descriptor
+{
 	uint8_t	bLength;
 	uint8_t	bDescriptorType;
 	uint8_t	bEndpointAddress;
@@ -127,7 +125,8 @@ struct usb_endpoint_descriptor {
 } __attribute__ ((packed)) __attribute__ ((aligned(2)));

 /* Interface descriptor */
-struct usb_interface_descriptor {
+struct usb_interface_descriptor
+{
 	uint8_t	bLength;
 	uint8_t	bDescriptorType;
 	uint8_t	bInterfaceNumber;
@@ -147,7 +146,8 @@ struct usb_interface_descriptor {


 /* Configuration descriptor information.. */
-struct usb_config_descriptor {
+struct usb_config_descriptor
+{
 	uint8_t	bLength;
 	uint8_t	bDescriptorType;
 	uint16_t	wTotalLength;
@@ -161,7 +161,8 @@ struct usb_config_descriptor {
 	struct usb_interface_descriptor if_desc[USB_MAXINTERFACES];
 } __attribute__ ((packed));

-enum {
+enum
+{
 	/* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */
 	PACKET_SIZE_8   = 0,
 	PACKET_SIZE_16  = 1,
@@ -169,7 +170,8 @@ enum {
 	PACKET_SIZE_64  = 3,
 };

-struct usb_device {
+struct usb_device
+{
 	int	devnum;			/* Device number on USB bus */
 	int	speed;			/* full/low/high */
 	char mf[32];			/* manufacturer */
@@ -229,67 +231,62 @@ typedef struct
 * this is how the lowlevel part communicate with the outer world
 */

-int ohci_usb_lowlevel_init(int32_t handle, const struct pci_device_id *ent, void **priv);
-int ohci_usb_lowlevel_stop(void *priv);
-int ohci_submit_bulk_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len);
-int ohci_submit_control_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, struct devrequest *setup);
-int ohci_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
-void ohci_usb_enable_interrupt(int enable);
+extern int ohci_usb_lowlevel_init(int32_t handle, const struct pci_device_id *ent, void **priv);
+extern int ohci_usb_lowlevel_stop(void *priv);
+extern int ohci_submit_bulk_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len);
+extern int ohci_submit_control_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, struct devrequest *setup);
+extern int ohci_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
+extern void ohci_usb_enable_interrupt(int enable);

-int ehci_usb_lowlevel_init(long handle, const struct pci_device_id *ent, void **priv);
-int ehci_usb_lowlevel_stop(void *priv);
-int ehci_submit_bulk_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len);
-int ehci_submit_control_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, struct devrequest *setup);
-int ehci_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
-void ehci_usb_enable_interrupt(int enable);
+extern int ehci_usb_lowlevel_init(long handle, const struct pci_device_id *ent, void **priv);
+extern int ehci_usb_lowlevel_stop(void *priv);
+extern int ehci_submit_bulk_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len);
+extern int ehci_submit_control_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, struct devrequest *setup);
+extern int ehci_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
+extern void ehci_usb_enable_interrupt(int enable);

-void usb_enable_interrupt(int enable);
+extern void usb_enable_interrupt(int enable);
+
+extern int usb_new_device(struct usb_device *dev);
+extern struct usb_device *usb_alloc_new_device(int bus_index, void *priv);
+extern void usb_disconnect(struct usb_device **pdev);

 #define USB_MAX_STOR_DEV 5
-block_dev_desc_t *usb_stor_get_dev(int index);
-int usb_stor_scan(void);
-int usb_stor_info(void);
-int usb_stor_register(struct usb_device *dev);
-int usb_stor_deregister(struct usb_device *dev);

-int drv_usb_kbd_init(void);
-int usb_kbd_register(struct usb_device *dev);
-int usb_kbd_deregister(struct usb_device *dev);
+extern block_dev_desc_t *usb_stor_get_dev(int index);
+extern int usb_stor_scan(void);
+extern int usb_stor_info(void);
+extern int usb_stor_register(struct usb_device *dev);
+extern int usb_stor_deregister(struct usb_device *dev);

-int drv_usb_mouse_init(void);
-int usb_mouse_register(struct usb_device *dev);
-int usb_mouse_deregister(struct usb_device *dev);
+extern int drv_usb_kbd_init(void);
+extern int usb_kbd_register(struct usb_device *dev);
+extern int usb_kbd_deregister(struct usb_device *dev);

-extern char usb_error_str[256];
-
-/* memory */
-void *usb_malloc(long amount);
-int usb_free(void *addr);
-int usb_mem_init(void);
-void usb_mem_stop(void);
+extern int drv_usb_mouse_init(void);
+extern int usb_mouse_register(struct usb_device *dev);
+extern int usb_mouse_deregister(struct usb_device *dev);

 /* routines */
-USB_COOKIE *usb_get_cookie(long id);
-void usb_error_msg(const char *const fmt, ... );
-int usb_init(int32_t handle, const struct pci_device_id *ent); /* initialize the USB Controller */
-int usb_stop(void); /* stop the USB Controller */
+extern int usb_init(int32_t handle, const struct pci_device_id *ent); /* initialize the USB Controller */
+extern int usb_stop(void); /* stop the USB Controller */

-int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol);
-int usb_set_idle(struct usb_device *dev, int ifnum, int duration, int report_id);
-struct usb_device *usb_get_dev_index(int index, int bus);
-int usb_control_msg(struct usb_device *dev, unsigned int pipe, uint8_t request, uint8_t requesttype, uint16_t value, 
- uint16_t index, void *data, uint16_t size, int timeout);
-int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, void *data, int len, int *actual_length, int timeout);
-int usb_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
-void usb_disable_asynch(int disable);
-int usb_maxpacket(struct usb_device *dev, uint32_t pipe);
-void wait_ms(uint32_t ms);
-int usb_get_configuration_no(struct usb_device *dev, uint8_t *buffer, int cfgno);
-int usb_get_report(struct usb_device *dev, int ifnum, uint8_t type, uint8_t id, void *buf, int size);
-int usb_get_class_descriptor(struct usb_device *dev, int ifnum, uint8_t type, uint8_t id, void *buf, int size);
-int usb_clear_halt(struct usb_device *dev, int pipe);
-int usb_string(struct usb_device *dev, int index, char *buf, size_t size);
-int usb_set_interface(struct usb_device *dev, int interface, int alternate);
+extern int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol);
+extern int usb_set_idle(struct usb_device *dev, int ifnum, int duration, int report_id);
+extern struct usb_device *usb_get_dev_index(int index, int bus);
+extern int usb_control_msg(struct usb_device *dev, unsigned int pipe, uint8_t request, uint8_t requesttype,
+						   uint16_t value, uint16_t index, void *data, uint16_t size, int timeout);
+extern int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, void *data, int len, int *actual_length, int timeout);
+extern int usb_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
+extern void usb_disable_asynch(int disable);
+extern int usb_maxpacket(struct usb_device *dev, uint32_t pipe);
+
+extern int usb_get_configuration_no(struct usb_device *dev, uint8_t *buffer, int cfgno);
+extern int usb_get_report(struct usb_device *dev, int ifnum, uint8_t type, uint8_t id, void *buf, int size);
+extern int usb_get_class_descriptor(struct usb_device *dev, int ifnum, uint8_t type, uint8_t id, void *buf, int size);
+extern int usb_clear_halt(struct usb_device *dev, int pipe);
+extern int usb_string(struct usb_device *dev, int index, char *buf, size_t size);
+extern int usb_set_interface(struct usb_device *dev, int interface, int alternate);

 /*
 * Calling this entity a "pipe" is glorifying it. A USB pipe
@@ -391,19 +388,22 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate);
 /*************************************************************************
 * Hub Stuff
 */
-struct usb_port_status {
+struct usb_port_status
+{
 	uint16_t wPortStatus;
 	uint16_t wPortChange;
 } __attribute__ ((packed));

-struct usb_hub_status {
+struct usb_hub_status
+{
 	uint16_t wHubStatus;
 	uint16_t wHubChange;
 } __attribute__ ((packed));


 /* Hub descriptor */
-struct usb_hub_descriptor {
+struct usb_hub_descriptor
+{
 	uint8_t  bLength;
 	uint8_t  bDescriptorType;
 	uint8_t  bNbrPorts;
@@ -417,7 +417,8 @@ struct usb_hub_descriptor {
 } __attribute__ ((packed));


-struct usb_hub_device {
+struct usb_hub_device
+{
 	struct usb_device *pusb_dev;
 	struct usb_hub_descriptor desc;
 };
--- a/include/usb_hub.h
+++ b/include/usb_hub.h
@@ -0,0 +1,10 @@
+#ifndef USB_HUB_H
+#define USB_HUB_H
+
+extern int bus_index;
+
+extern void usb_hub_reset(int bus_index);
+extern int usb_hub_probe(struct usb_device *dev, int ifnum);
+extern int hub_port_reset(struct usb_device *dev, int port, unsigned short *portstat);
+
+#endif // USB_HUB_H
--- a/include/util.h
+++ b/include/util.h
@@ -25,7 +25,7 @@
 #ifndef UTIL_H_
 #define UTIL_H_

-#include <stdint.h>
+#include <bas_types.h>

 #define NOP() __asm__ __volatile__("nop\n\t" : : : "memory")

@@ -59,7 +59,7 @@ static inline uint32_t swpl(uint32_t l)
 	register uint32_t result asm("d0");

 	__asm__ __volatile__
-	(						
+	(
 		"lea		%[input],a0\n\t"				\
 		"mvz.b	3(a0),%[output]\n\t"			\
 		"lsl.l	#8,%[output]\n\t"				\
@@ -74,7 +74,7 @@ static inline uint32_t swpl(uint32_t l)
 	);
 	return result;
 }
-	
+

 /*
 * WORD swpw2(ULONG val);
@@ -85,17 +85,17 @@ static inline uint32_t swpl(uint32_t l)
 #define swpw2(a)                          \
  __extension__                           \
  ({unsigned long _tmp;                   \
-    __asm__ __volatile__                  \
-    ("move.b  (%1),%0\n\t"                \
-     "move.b  1(%1),(%1)\n\t"             \
-     "move.b  %0,1(%1)\n\t"               \
-     "move.b  2(%1),%0\n\t"               \
-     "move.b  3(%1),2(%1)\n\t"            \
-     "move.b  %0,3(%1)"                   \
-    : "=d"(_tmp)     /* outputs */        \
-    : "a"(&a)        /* inputs  */        \
-    : "cc", "memory" /* clobbered */      \
-    );                                    \
+	__asm__ __volatile__                  \
+	("move.b  (%1),%0\n\t"                \
+	 "move.b  1(%1),(%1)\n\t"             \
+	 "move.b  %0,1(%1)\n\t"               \
+	 "move.b  2(%1),%0\n\t"               \
+	 "move.b  3(%1),2(%1)\n\t"            \
+	 "move.b  %0,3(%1)"                   \
+	: "=d"(_tmp)     /* outputs */        \
+	: "a"(&a)        /* inputs  */        \
+	: "cc", "memory" /* clobbered */      \
+	);                                    \
  })

 /*
@@ -144,10 +144,10 @@ __extension__                             \
 #define regsafe_call(addr)                         \
 __extension__                                      \
 ({__asm__ volatile ("lea     -60(sp),sp\n\t"       \
-                    "movem.l d0-d7/a0-a6,(sp)");   \
+					"movem.l d0-d7/a0-a6,(sp)");   \
  ((void (*) (void)) addr)();                      \
  __asm__ volatile ("movem.l (sp),d0-d7/a0-a6\n\t" \
-                    "lea     60(sp),sp");          \
+					"lea     60(sp),sp");          \
 })


--- a/include/version.h
+++ b/include/version.h
@@ -29,7 +29,7 @@
 */

 #define MAJOR_VERSION	0
-#define MINOR_VERSION	85
+#define MINOR_VERSION	86


 #endif /* VERSION_H_ */
--- a/include/video.h
+++ b/include/video.h
@@ -1,9 +1,7 @@
 #ifndef _VIDEO_H_
 #define _VIDEO_H_

-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
+#include <bas_types.h>
 #include "bas_printf.h"

 extern void video_init(void);
--- a/include/wait.h
+++ b/include/wait.h
@@ -44,6 +44,11 @@
 typedef bool (*checker_func)(void);

 extern void wait(uint32_t);
+inline static void udelay(long us)
+{
+    wait((uint32_t) us);
+}
+
 extern bool waitfor(uint32_t us, checker_func condition);
 extern uint32_t get_timer(void);
 extern void wait_ms(uint32_t ms);
--- a/include/x86debug.h
+++ b/include/x86debug.h
@@ -37,7 +37,7 @@
 ****************************************************************************/
 /* $XFree86: xc/extras/x86emu/src/x86emu/x86emu/debug.h,v 1.4 2000/11/21 23:10:27 tsi Exp $ */

-#include <stdint.h>
+#include <bas_types.h>
 #include "bas_printf.h"

 /*
@@ -135,7 +135,7 @@

 #define SAVE_IP_CS(x,y)                               			\
 	if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \
-              | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \
+			  | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \
 		M.x86.saved_cs = x;                          			\
 		M.x86.saved_ip = y;                          			\
 	}
--- a/kbd/ikbd.c
+++ b/kbd/ikbd.c
@@ -18,7 +18,7 @@

 */

-#include <stdint.h>
+#include <bas_types.h>
 #include "bas_printf.h"
 #include "bas_string.h"

@@ -42,298 +42,298 @@ static unsigned char wptr = 0, rptr = 0;
 // structure to keep track of ikbd state
 static struct
 {
-    unsigned char cmd;
-    unsigned char state;
-    unsigned char expect;
+	unsigned char cmd;
+	unsigned char state;
+	unsigned char expect;

-    // joystick state
-    unsigned char joystick[2];
+	// joystick state
+	unsigned char joystick[2];

-    // mouse state
-    unsigned short mouse_pos_x, mouse_pos_y;
-    unsigned char mouse_buttons;
+	// mouse state
+	unsigned short mouse_pos_x, mouse_pos_y;
+	unsigned char mouse_buttons;
 } ikbd;

 // #define IKBD_DEBUG

 void ikbd_init()
 {
-    // reset ikbd state
-    memset(&ikbd, 0, sizeof(ikbd));
-    ikbd.state = IKBD_DEFAULT;
+	// reset ikbd state
+	memset(&ikbd, 0, sizeof(ikbd));
+	ikbd.state = IKBD_DEFAULT;
 }

 static void enqueue(unsigned char b)
 {
-    if (((wptr + 1)&(QUEUE_LEN-1)) == rptr)
-    {
-        xprintf("IKBD: !!!!!!! tx queue overflow !!!!!!!!!\n");
-        return;
-    }
+	if (((wptr + 1)&(QUEUE_LEN-1)) == rptr)
+	{
+		xprintf("IKBD: !!!!!!! tx queue overflow !!!!!!!!!\n");
+		return;
+	}

-    tx_queue[wptr] = b;
-    wptr = (wptr + 1) & (QUEUE_LEN - 1);
+	tx_queue[wptr] = b;
+	wptr = (wptr + 1) & (QUEUE_LEN - 1);
 }

 // convert internal joystick format into atari ikbd format
 static unsigned char joystick_map2ikbd(unsigned in)
 {
-    unsigned char out = 0;
+	unsigned char out = 0;

-    if (in & JOY_UP)    out |= 0x01;
-    if (in & JOY_DOWN)  out |= 0x02;
-    if (in & JOY_LEFT)  out |= 0x04;
-    if (in & JOY_RIGHT) out |= 0x08;
-    if (in & JOY_BTN1)  out |= 0x80;
+	if (in & JOY_UP)    out |= 0x01;
+	if (in & JOY_DOWN)  out |= 0x02;
+	if (in & JOY_LEFT)  out |= 0x04;
+	if (in & JOY_RIGHT) out |= 0x08;
+	if (in & JOY_BTN1)  out |= 0x80;

-    return out;
+	return out;
 }

 // process inout from atari core into ikbd
 void ikbd_handle_input(unsigned char cmd)
 {
-    // expecting a second byte for command
-    if (ikbd.expect)
-    {
-        ikbd.expect--;
+	// expecting a second byte for command
+	if (ikbd.expect)
+	{
+		ikbd.expect--;

-        // last byte of command received
-        if (!ikbd.expect)
-        {
-            switch(ikbd.cmd)
-            {
-                case 0x07: // set mouse button action
-                    xprintf("IKBD: mouse button action = %x\n", cmd);
+		// last byte of command received
+		if (!ikbd.expect)
+		{
+			switch(ikbd.cmd)
+			{
+				case 0x07: // set mouse button action
+					xprintf("IKBD: mouse button action = %x\n", cmd);

-                    // bit 2: Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75)
-                    if(cmd & 0x04) ikbd.state |=  IKBD_STATE_MOUSE_BUTTON_AS_KEY;
-                    else           ikbd.state &= ~IKBD_STATE_MOUSE_BUTTON_AS_KEY;
+					// bit 2: Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75)
+					if(cmd & 0x04) ikbd.state |=  IKBD_STATE_MOUSE_BUTTON_AS_KEY;
+					else           ikbd.state &= ~IKBD_STATE_MOUSE_BUTTON_AS_KEY;

-                    break;
+					break;

-                case 0x80: // ibkd reset
-                    // reply "everything is ok"
-                    enqueue(0xf0);
-                    break;
+				case 0x80: // ibkd reset
+					// reply "everything is ok"
+					enqueue(0xf0);
+					break;

-                default:
-                    break;
-            }
-        }
+				default:
+					break;
+			}
+		}

-        return;
-    }
+		return;
+	}

-    ikbd.cmd = cmd;
+	ikbd.cmd = cmd;

-    switch(cmd)
-    {
-        case 0x07:
-            xprintf("IKBD: Set mouse button action");
-            ikbd.expect = 1;
-            break;
+	switch(cmd)
+	{
+		case 0x07:
+			xprintf("IKBD: Set mouse button action");
+			ikbd.expect = 1;
+			break;

-        case 0x08:
-            xprintf("IKBD: Set relative mouse positioning");
-            ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED;
-            ikbd.state &= ~IKBD_STATE_MOUSE_ABSOLUTE;
-            break;
+		case 0x08:
+			xprintf("IKBD: Set relative mouse positioning");
+			ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED;
+			ikbd.state &= ~IKBD_STATE_MOUSE_ABSOLUTE;
+			break;

-        case 0x09:
-            xprintf("IKBD: Set absolute mouse positioning");
-            ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED;
-            ikbd.state |=  IKBD_STATE_MOUSE_ABSOLUTE;
-            ikbd.expect = 4;
-            break;
+		case 0x09:
+			xprintf("IKBD: Set absolute mouse positioning");
+			ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED;
+			ikbd.state |=  IKBD_STATE_MOUSE_ABSOLUTE;
+			ikbd.expect = 4;
+			break;

-        case 0x0b:
-            xprintf("IKBD: Set Mouse threshold");
-            ikbd.expect = 2;
-            break;
+		case 0x0b:
+			xprintf("IKBD: Set Mouse threshold");
+			ikbd.expect = 2;
+			break;

-        case 0x0f:
-            xprintf("IKBD: Set Y at bottom");
-            ikbd.state |= IKBD_STATE_MOUSE_Y_BOTTOM;
-            break;
+		case 0x0f:
+			xprintf("IKBD: Set Y at bottom");
+			ikbd.state |= IKBD_STATE_MOUSE_Y_BOTTOM;
+			break;

-        case 0x10:
-            xprintf("IKBD: Set Y at top");
-            ikbd.state &= ~IKBD_STATE_MOUSE_Y_BOTTOM;
-            break;
+		case 0x10:
+			xprintf("IKBD: Set Y at top");
+			ikbd.state &= ~IKBD_STATE_MOUSE_Y_BOTTOM;
+			break;

-        case 0x12:
-            xprintf("IKBD: Disable mouse");
-            ikbd.state |= IKBD_STATE_MOUSE_DISABLED;
-            break;
+		case 0x12:
+			xprintf("IKBD: Disable mouse");
+			ikbd.state |= IKBD_STATE_MOUSE_DISABLED;
+			break;

-        case 0x14:
-            xprintf("IKBD: Set Joystick event reporting");
-            ikbd.state |= IKBD_STATE_JOYSTICK_EVENT_REPORTING;
-            break;
+		case 0x14:
+			xprintf("IKBD: Set Joystick event reporting");
+			ikbd.state |= IKBD_STATE_JOYSTICK_EVENT_REPORTING;
+			break;

-        case 0x15:
-            xprintf("IKBD: Set Joystick interrogation mode");
-            ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING;
-            break;
+		case 0x15:
+			xprintf("IKBD: Set Joystick interrogation mode");
+			ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING;
+			break;

-        case 0x16: // interrogate joystick
-            // send reply
-            enqueue(0xfd);
-            enqueue(joystick_map2ikbd(ikbd.joystick[0]));
-            enqueue(joystick_map2ikbd(ikbd.joystick[1]));
-            break;
+		case 0x16: // interrogate joystick
+			// send reply
+			enqueue(0xfd);
+			enqueue(joystick_map2ikbd(ikbd.joystick[0]));
+			enqueue(joystick_map2ikbd(ikbd.joystick[1]));
+			break;

-        case 0x1a:
-            xprintf("IKBD: Disable joysticks");
-            ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING;
-            break;
+		case 0x1a:
+			xprintf("IKBD: Disable joysticks");
+			ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING;
+			break;

-        case 0x1c:
-            xprintf("IKBD: Interrogate time of day");
+		case 0x1c:
+			xprintf("IKBD: Interrogate time of day");

-            enqueue(0xfc);
-            enqueue(0x13);  // year bcd
-            enqueue(0x03);  // month bcd
-            enqueue(0x07);  // day bcd
-            enqueue(0x20);  // hour bcd
-            enqueue(0x58);  // minute bcd
-            enqueue(0x00);  // second bcd
-            break;
+			enqueue(0xfc);
+			enqueue(0x13);  // year bcd
+			enqueue(0x03);  // month bcd
+			enqueue(0x07);  // day bcd
+			enqueue(0x20);  // hour bcd
+			enqueue(0x58);  // minute bcd
+			enqueue(0x00);  // second bcd
+			break;


-        case 0x80:
-            xprintf("IKBD: Reset");
-            ikbd.expect = 1;
-            ikbd.state = IKBD_DEFAULT;
-            break;
+		case 0x80:
+			xprintf("IKBD: Reset");
+			ikbd.expect = 1;
+			ikbd.state = IKBD_DEFAULT;
+			break;

-        default:
-            xprintf("IKBD: unknown command: %x\n", cmd);
-            break;
-    }
+		default:
+			xprintf("IKBD: unknown command: %x\n", cmd);
+			break;
+	}
 }

 void ikbd_poll(void) {
-    static int mtimer = 0;
-    if (CheckTimer(mtimer))
-    {
-        mtimer = GetTimer(10);
+	static int mtimer = 0;
+	if (CheckTimer(mtimer))
+	{
+		mtimer = GetTimer(10);

-        // check for incoming ikbd data
-        EnableIO();
-        SPI(UIO_IKBD_IN);
+		// check for incoming ikbd data
+		EnableIO();
+		SPI(UIO_IKBD_IN);

-        while(SPI(0))
-            ikbd_handle_input(SPI(0));
+		while(SPI(0))
+			ikbd_handle_input(SPI(0));

-        DisableIO();
-    }
+		DisableIO();
+	}

-    // send data from queue if present
-    if(rptr == wptr) return;
+	// send data from queue if present
+	if(rptr == wptr) return;

-    // transmit data from queue
-    EnableIO();
-    SPI(UIO_IKBD_OUT);
-    SPI(tx_queue[rptr]);
-    DisableIO();
+	// transmit data from queue
+	EnableIO();
+	SPI(UIO_IKBD_OUT);
+	SPI(tx_queue[rptr]);
+	DisableIO();

-    rptr = (rptr + 1) & (QUEUE_LEN - 1);
+	rptr = (rptr + 1) & (QUEUE_LEN - 1);
 }

 void ikbd_joystick(unsigned char joystick, unsigned char map)
 {
-    // todo: suppress events for joystick 0 as long as mouse
-    // is enabled?
+	// todo: suppress events for joystick 0 as long as mouse
+	// is enabled?

-    if (ikbd.state & IKBD_STATE_JOYSTICK_EVENT_REPORTING)
-    {
+	if (ikbd.state & IKBD_STATE_JOYSTICK_EVENT_REPORTING)
+	{
 #ifdef IKBD_DEBUG
-        xprintf("IKBD: joy %d %x\n", joystick, map);
+		xprintf("IKBD: joy %d %x\n", joystick, map);
 #endif

-        // only report joystick data for joystick 0 if the mouse is disabled
-        if ((ikbd.state & IKBD_STATE_MOUSE_DISABLED) || (joystick == 1))
-        {
-            enqueue(0xfe + joystick);
-            enqueue(joystick_map2ikbd(map));
-        }
+		// only report joystick data for joystick 0 if the mouse is disabled
+		if ((ikbd.state & IKBD_STATE_MOUSE_DISABLED) || (joystick == 1))
+		{
+			enqueue(0xfe + joystick);
+			enqueue(joystick_map2ikbd(map));
+		}

-        if (!(ikbd.state & IKBD_STATE_MOUSE_DISABLED))
-        {
-            // the fire button also generates a mouse event if
-            // mouse reporting is enabled
-            if ((map & JOY_BTN1) != (ikbd.joystick[joystick] & JOY_BTN1))
-            {
-                // generate mouse event (ikbd_joystick_buttons is evaluated inside
-                // user_io_mouse)
-                ikbd.joystick[joystick] = map;
-                ikbd_mouse(0, 0, 0);
-            }
-        }
-    }
+		if (!(ikbd.state & IKBD_STATE_MOUSE_DISABLED))
+		{
+			// the fire button also generates a mouse event if
+			// mouse reporting is enabled
+			if ((map & JOY_BTN1) != (ikbd.joystick[joystick] & JOY_BTN1))
+			{
+				// generate mouse event (ikbd_joystick_buttons is evaluated inside
+				// user_io_mouse)
+				ikbd.joystick[joystick] = map;
+				ikbd_mouse(0, 0, 0);
+			}
+		}
+	}
 #ifdef IKBD_DEBUG
-    else
-        xprintf("IKBD: no monitor, drop joy %d %x\n", joystick, map);
+	else
+		xprintf("IKBD: no monitor, drop joy %d %x\n", joystick, map);
 #endif

-    // save state of joystick for interrogation mode
-    ikbd.joystick[joystick] = map;
+	// save state of joystick for interrogation mode
+	ikbd.joystick[joystick] = map;
 }

 void ikbd_keyboard(unsigned char code)
 {
 #ifdef IKBD_DEBUG
-    xprintf("IKBD: send keycode %x%s\n", code&0x7f, (code&0x80)?" BREAK":"");
+	xprintf("IKBD: send keycode %x%s\n", code&0x7f, (code&0x80)?" BREAK":"");
 #endif
-    enqueue(code);
+	enqueue(code);
 }

 void ikbd_mouse(uint8_t b, int8_t x, int8_t y)
 {
-    if (ikbd.state & IKBD_STATE_MOUSE_DISABLED)
-        return;
+	if (ikbd.state & IKBD_STATE_MOUSE_DISABLED)
+		return;

-    // joystick and mouse buttons are wired together in
-    // atari st
-    b |= (ikbd.joystick[0] & JOY_BTN1)?1:0;
-    b |= (ikbd.joystick[1] & JOY_BTN1)?2:0;
+	// joystick and mouse buttons are wired together in
+	// atari st
+	b |= (ikbd.joystick[0] & JOY_BTN1)?1:0;
+	b |= (ikbd.joystick[1] & JOY_BTN1)?2:0;

-    static unsigned char b_old = 0;
-    // monitor state of two mouse buttons
-    if (b != b_old)
-    {
-        // check if mouse buttons are supposed to be treated like keys
-        if (ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY)
-        {
-            // Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75)
+	static unsigned char b_old = 0;
+	// monitor state of two mouse buttons
+	if (b != b_old)
+	{
+		// check if mouse buttons are supposed to be treated like keys
+		if (ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY)
+		{
+			// Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75)

-            // handle left mouse button
-            if((b ^ b_old) & 1) ikbd_keyboard(0x74 | ((b&1)?0x00:0x80));
-            // handle right mouse button
-            if((b ^ b_old) & 2) ikbd_keyboard(0x75 | ((b&2)?0x00:0x80));
-        }
-        b_old = b;
-    }
+			// handle left mouse button
+			if((b ^ b_old) & 1) ikbd_keyboard(0x74 | ((b&1)?0x00:0x80));
+			// handle right mouse button
+			if((b ^ b_old) & 2) ikbd_keyboard(0x75 | ((b&2)?0x00:0x80));
+		}
+		b_old = b;
+	}

 #if 0
-    if(ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY)
-    {
-        b = 0;
-        // if mouse position is 0/0 quit here
-        if(!x && !y) return;
-    }
+	if(ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY)
+	{
+		b = 0;
+		// if mouse position is 0/0 quit here
+		if(!x && !y) return;
+	}
 #endif

-    if (ikbd.state & IKBD_STATE_MOUSE_ABSOLUTE)
-    {
-    }
-    else
-    {
-        // atari has mouse button bits swapped
-        enqueue(0xf8|((b&1)?2:0)|((b&2)?1:0));
-        enqueue(x);
-        enqueue((ikbd.state & IKBD_STATE_MOUSE_Y_BOTTOM)?-y:y);
-    }
+	if (ikbd.state & IKBD_STATE_MOUSE_ABSOLUTE)
+	{
+	}
+	else
+	{
+		// atari has mouse button bits swapped
+		enqueue(0xf8|((b&1)?2:0)|((b&2)?1:0));
+		enqueue(x);
+		enqueue((ikbd.state & IKBD_STATE_MOUSE_Y_BOTTOM)?-y:y);
+	}
 }

--- a/net/am79c874.c
+++ b/net/am79c874.c
@@ -26,7 +26,7 @@
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_AM79 */

-/********************************************************************/
+
 /* Initialize the AM79C874 PHY
 *
 * This function sets up the Auto-Negotiate Advertisement register
--- a/net/arp.c
+++ b/net/arp.c
@@ -13,7 +13,7 @@

 //#define DBG_ARP
 #ifdef DBG_ARP
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_ARP */
@@ -22,459 +22,469 @@

 static uint8_t *arp_find_pair(ARP_INFO *arptab, uint16_t protocol, uint8_t *hwa, uint8_t *pa)
 {
-	/*
-	 * This function searches through the ARP table for the
-	 * specified <protocol,hwa> or <protocol,pa> address pair.
-	 * If it is found, then a a pointer to the non-specified
-	 * address is returned.  Otherwise NULL is returned.
-	 * If you pass in <protocol,pa> then you get <hwa> out.
-	 * If you pass in <protocol,hwa> then you get <pa> out.
-	 */
-	int slot, i, match = false;
-	uint8_t *rvalue;
+    /*
+     * This function searches through the ARP table for the
+     * specified <protocol,hwa> or <protocol,pa> address pair.
+     * If it is found, then a a pointer to the non-specified
+     * address is returned.  Otherwise NULL is returned.
+     * If you pass in <protocol,pa> then you get <hwa> out.
+     * If you pass in <protocol,hwa> then you get <pa> out.
+     */
+    int slot, i, match = false;
+    uint8_t *rvalue;

-	if (((hwa == 0) && (pa == 0)) || (arptab == 0))
-		return NULL;
+    if (((hwa == 0) && (pa == 0)) || (arptab == 0))
+        return NULL;

-	rvalue = NULL;
+    rvalue = NULL;

-	/* 
-	 * Check each protocol address for a match 
-	 */
-	for (slot = 0; slot < arptab->tab_size; slot++)
-	{
-		if ((arptab->table[slot].longevity != ARP_ENTRY_EMPTY) &&
-				(arptab->table[slot].protocol == protocol))
-		{
-			match = true;
-			if (hwa != 0)
-			{
-				/* 
-				 * Check the Hardware Address field 
-				 */
-				rvalue = &arptab->table[slot].pa[0];
-				for (i = 0; i < arptab->table[slot].hwa_size; i++)
-				{
-					if (arptab->table[slot].hwa[i] != hwa[i])
-					{
-						match = false;
-						break;
-					}
-				}
-			}
-			else
-			{
-				/* 
-				 * Check the Protocol Address field 
-				 */
-				rvalue = &arptab->table[slot].hwa[0];
-				for (i = 0; i < arptab->table[slot].pa_size; i++)
-				{
-					if (arptab->table[slot].pa[i] != pa[i])
-					{
-						match = false;
-						break;
-					}
-				}
-			}
-			if (match)
-			{
-				break;
-			}
-		}
-	}
+    /*
+     * Check each protocol address for a match
+     */
+    for (slot = 0; slot < arptab->tab_size; slot++)
+    {
+        if ((arptab->table[slot].longevity != ARP_ENTRY_EMPTY) &&
+                (arptab->table[slot].protocol == protocol))
+        {
+            match = true;
+            if (hwa != 0)
+            {
+                /*
+                 * Check the Hardware Address field
+                 */
+                rvalue = &arptab->table[slot].pa[0];
+                for (i = 0; i < arptab->table[slot].hwa_size; i++)
+                {
+                    if (arptab->table[slot].hwa[i] != hwa[i])
+                    {
+                        match = false;
+                        break;
+                    }
+                }
+            }
+            else
+            {
+                /*
+                 * Check the Protocol Address field
+                 */
+                rvalue = &arptab->table[slot].hwa[0];
+                for (i = 0; i < arptab->table[slot].pa_size; i++)
+                {
+                    if (arptab->table[slot].pa[i] != pa[i])
+                    {
+                        match = false;
+                        break;
+                    }
+                }
+            }
+            if (match)
+            {
+                break;
+            }
+        }
+    }

-	if (match)
-		return rvalue;
-	else
-		return NULL;
+    if (match)
+        return rvalue;
+    else
+        return NULL;
 }

 void arp_merge(ARP_INFO *arptab, uint16_t protocol, int hwa_size, uint8_t *hwa,
-		int pa_size, uint8_t *pa, int longevity)
+        int pa_size, uint8_t *pa, int longevity)
 {
-	/*
-	 * This function merges an entry into the ARP table.  If
-	 * either piece is NULL, the function exits, otherwise
-	 * the entry is merged or added, provided there is space.
-	 */
-	int i, slot;
-	uint8_t *ta;
+    /*
+     * This function merges an entry into the ARP table.  If
+     * either piece is NULL, the function exits, otherwise
+     * the entry is merged or added, provided there is space.
+     */
+    int i, slot;
+    uint8_t *ta;

-	if ((hwa == NULL) || (pa == NULL) || (arptab == NULL) ||
-			((longevity != ARP_ENTRY_TEMP) &&
-			 (longevity != ARP_ENTRY_PERM)))
-	{
-		return;
-	}
+    if ((hwa == NULL) || (pa == NULL) || (arptab == NULL) ||
+            ((longevity != ARP_ENTRY_TEMP) &&
+             (longevity != ARP_ENTRY_PERM)))
+    {
+        return;
+    }

-	/* First search ARP table for existing entry */
-	if ((ta = arp_find_pair(arptab,protocol,NULL,pa)) != 0)
-	{
-		/* Update hardware address */
-		for (i = 0; i < hwa_size; i++)
-			ta[i] = hwa[i];
-		return;
-	}
+    /* First search ARP table for existing entry */
+    if ((ta = arp_find_pair(arptab,protocol,NULL,pa)) != 0)
+    {
+        /* Update hardware address */
+        for (i = 0; i < hwa_size; i++)
+            ta[i] = hwa[i];
+        return;
+    }

-	/* Next try to find an empty slot */
-	slot = -1;
-	for (i = 0; i < MAX_ARP_ENTRY; i++)
-	{
-		if (arptab->table[i].longevity == ARP_ENTRY_EMPTY)
-		{
-			slot = i;
-			break;
-		}
-	}
+    /* Next try to find an empty slot */
+    slot = -1;
+    for (i = 0; i < MAX_ARP_ENTRY; i++)
+    {
+        if (arptab->table[i].longevity == ARP_ENTRY_EMPTY)
+        {
+            slot = i;
+            break;
+        }
+    }

-	/* if no empty slot was found, pick a temp slot */
-	if (slot == -1)
-	{
-		for (i = 0; i < MAX_ARP_ENTRY; i++)
-		{
-			if (arptab->table[i].longevity == ARP_ENTRY_TEMP)
-			{
-				slot = i;
-				break;
-			}
-		}
-	}
+    /* if no empty slot was found, pick a temp slot */
+    if (slot == -1)
+    {
+        for (i = 0; i < MAX_ARP_ENTRY; i++)
+        {
+            if (arptab->table[i].longevity == ARP_ENTRY_TEMP)
+            {
+                slot = i;
+                break;
+            }
+        }
+    }

-	/* if after all this, still no slot found, add in last slot */
-	if (slot == -1)
-		slot = (MAX_ARP_ENTRY - 1);
+    /* if after all this, still no slot found, add in last slot */
+    if (slot == -1)
+        slot = (MAX_ARP_ENTRY - 1);

-	/* add the entry into the slot */
-	arptab->table[slot].protocol = protocol;
+    /* add the entry into the slot */
+    arptab->table[slot].protocol = protocol;

-	arptab->table[slot].hwa_size = (uint8_t) hwa_size;
-	for (i = 0; i < hwa_size; i++)
-		arptab->table[slot].hwa[i] = hwa[i];
+    arptab->table[slot].hwa_size = (uint8_t) hwa_size;
+    for (i = 0; i < hwa_size; i++)
+        arptab->table[slot].hwa[i] = hwa[i];

-	arptab->table[slot].pa_size = (uint8_t) pa_size;
-	for (i = 0; i < pa_size; i++)
-		arptab->table[slot].pa[i] = pa[i];
+    arptab->table[slot].pa_size = (uint8_t) pa_size;
+    for (i = 0; i < pa_size; i++)
+        arptab->table[slot].pa[i] = pa[i];

-	arptab->table[slot].longevity = longevity;
+    arptab->table[slot].longevity = longevity;
 }


 void arp_remove(ARP_INFO *arptab, uint16_t protocol, uint8_t *hwa, uint8_t *pa)
 {
-	/*
-	 * This function removes an entry from the ARP table.  The
-	 * ARP table is searched according to the non-NULL address
-	 * that is provided.
-	 */
-	int slot, i, match;
+    /*
+     * This function removes an entry from the ARP table.  The
+     * ARP table is searched according to the non-NULL address
+     * that is provided.
+     */
+    int slot, i, match;

-	if (((hwa == 0) && (pa == 0)) || (arptab == 0))
-		return;
+    if (((hwa == 0) && (pa == 0)) || (arptab == 0))
+        return;

-	/* check each hardware adress for a match */
-	for (slot = 0; slot < arptab->tab_size; slot++)
-	{
-		if ((arptab->table[slot].longevity != ARP_ENTRY_EMPTY) &&
-				(arptab->table[slot].protocol == protocol))
-		{
-			match = true;
-			if (hwa != 0)
-			{
-				/* Check Hardware Address field */
-				for (i = 0; i < arptab->table[slot].hwa_size; i++)
-				{
-					if (arptab->table[slot].hwa[i] != hwa[i])
-					{
-						match = false;
-						break;
-					}
-				}
-			}
-			else
-			{
-				/* Check Protocol Address field */
-				for (i = 0; i < arptab->table[slot].pa_size; i++)
-				{
-					if (arptab->table[slot].pa[i] != pa[i])
-					{
-						match = false;
-						break;
-					}
-				}
-			}
-			if (match)
-			{
-				for (i = 0; i < arptab->table[slot].hwa_size; i++)
-					arptab->table[slot].hwa[i] = 0;
-				for (i = 0; i < arptab->table[slot].pa_size; i++)
-					arptab->table[slot].pa[i] = 0;
-				arptab->table[slot].longevity = ARP_ENTRY_EMPTY;
-				break;
-			}
-		}
-	}
+    /* check each hardware adress for a match */
+    for (slot = 0; slot < arptab->tab_size; slot++)
+    {
+        if ((arptab->table[slot].longevity != ARP_ENTRY_EMPTY) &&
+                (arptab->table[slot].protocol == protocol))
+        {
+            match = true;
+            if (hwa != 0)
+            {
+                /* Check Hardware Address field */
+                for (i = 0; i < arptab->table[slot].hwa_size; i++)
+                {
+                    if (arptab->table[slot].hwa[i] != hwa[i])
+                    {
+                        match = false;
+                        break;
+                    }
+                }
+            }
+            else
+            {
+                /* Check Protocol Address field */
+                for (i = 0; i < arptab->table[slot].pa_size; i++)
+                {
+                    if (arptab->table[slot].pa[i] != pa[i])
+                    {
+                        match = false;
+                        break;
+                    }
+                }
+            }
+            if (match)
+            {
+                for (i = 0; i < arptab->table[slot].hwa_size; i++)
+                    arptab->table[slot].hwa[i] = 0;
+                for (i = 0; i < arptab->table[slot].pa_size; i++)
+                    arptab->table[slot].pa[i] = 0;
+                arptab->table[slot].longevity = ARP_ENTRY_EMPTY;
+                break;
+            }
+        }
+    }
 }

 void arp_request(NIF *nif, uint8_t *pa)
 {
-	/*
-	 * This function broadcasts an ARP request for the protocol
-	 * address "pa"
-	 */
-	uint8_t *addr;
-	NBUF *pNbuf;
-	arp_frame_hdr *arpframe;
-	int i, result;
+    /*
+     * This function broadcasts an ARP request for the protocol
+     * address "pa"
+     */
+    uint8_t *addr;
+    NBUF *pNbuf;
+    arp_frame_hdr *arpframe;
+    int i, result;

+    pNbuf = nbuf_alloc();
+    if (pNbuf == NULL)
+    {
+        dbg("could not allocate Tx buffer\n");
+        return;
+    }

-	dbg("%s\r\n", __FUNCTION__);
+    arpframe = (arp_frame_hdr *)&pNbuf->data[ARP_HDR_OFFSET];

-	pNbuf = nbuf_alloc();
-	if (pNbuf == NULL)
-	{
-		dbg("%s: arp_request couldn't allocate Tx buffer\n", __FUNCTION__);
-		return;
-	}
+    /* Build the ARP request packet */
+    arpframe->ar_hrd = ETHERNET;
+    arpframe->ar_pro = ETH_FRM_IP;
+    arpframe->ar_hln = 6;
+    arpframe->ar_pln = 4;
+    arpframe->opcode = ARP_REQUEST;

-	arpframe = (arp_frame_hdr *)&pNbuf->data[ARP_HDR_OFFSET];
+    addr = &nif->hwa[0];
+    for (i = 0; i < 6; i++)
+        arpframe->ar_sha[i] = addr[i];

-	/* Build the ARP request packet */
-	arpframe->ar_hrd = ETHERNET;
-	arpframe->ar_pro = ETH_FRM_IP;
-	arpframe->ar_hln = 6;
-	arpframe->ar_pln = 4;
-	arpframe->opcode = ARP_REQUEST;
+    addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
+    for (i = 0; i < 4; i++)
+        arpframe->ar_spa[i] = addr[i];

-	addr = &nif->hwa[0];
-	for (i = 0; i < 6; i++)
-		arpframe->ar_sha[i] = addr[i];
+    for (i = 0; i < 6; i++)
+        arpframe->ar_tha[i] = 0x00;

-	addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
-	for (i = 0; i < 4; i++)
-		arpframe->ar_spa[i] = addr[i];
+    for (i = 0; i < 4; i++)
+        arpframe->ar_tpa[i] = pa[i];

-	for (i = 0; i < 6; i++)
-		arpframe->ar_tha[i] = 0x00;
+    pNbuf->length = ARP_HDR_LEN;

-	for (i = 0; i < 4; i++)
-		arpframe->ar_tpa[i] = pa[i];
+    /* Send the ARP request */
+    dbg("sending ARP request\r\n");
+    result = nif->send(nif, nif->broadcast, nif->hwa, ETH_FRM_ARP, pNbuf);

-	pNbuf->length = ARP_HDR_LEN;
-
-	/* Send the ARP request */
-	dbg("%s: sending ARP request\r\n", __FUNCTION__);
-	result = nif->send(nif, nif->broadcast, nif->hwa, ETH_FRM_ARP, pNbuf);
-
-	if (result == 0)
-		nbuf_free(pNbuf);
+    if (result == 0)
+        nbuf_free(pNbuf);
 }

 static int arp_resolve_pa(NIF *nif, uint16_t protocol, uint8_t *pa, uint8_t **ha)
 {
-	/*
-	 * This function accepts a pointer to a protocol address and
-	 * searches the ARP table for a hardware address match.  If no
-	 * no match found, false is returned.
-	 */
-	ARP_INFO *arptab;
+    /*
+     * This function accepts a pointer to a protocol address and
+     * searches the ARP table for a hardware address match.  If no
+     * no match found, false is returned.
+     */
+    ARP_INFO *arptab;

-	if ((pa == NULL) || (nif == NULL) || (protocol == 0))
-		return 0;
+    if ((pa == NULL) || (nif == NULL) || (protocol == 0))
+        return 0;

-	arptab = nif_get_protocol_info (nif,ETH_FRM_ARP);
-	*ha = arp_find_pair(arptab,protocol,0,pa);
+    arptab = nif_get_protocol_info (nif,ETH_FRM_ARP);
+    *ha = arp_find_pair(arptab,protocol,0,pa);

-	if (*ha == NULL)
-		return 0;
-	else
-		return 1;
+    if (*ha == NULL)
+        return 0;
+    else
+        return 1;
 }

 uint8_t *arp_resolve(NIF *nif, uint16_t protocol, uint8_t *pa)
 {
-	int i;
-	uint8_t *hwa;
+    int i;
+    uint8_t *hwa;

-	/* 
-	 * Check to see if the necessary MAC-to-IP translation information
-	 * is in table already 
-	 */
-	if (arp_resolve_pa(nif, protocol, pa, &hwa))
-		return hwa;
+    /*
+     * Check to see if the necessary MAC-to-IP translation information
+     * is in table already
+     */
+    if (arp_resolve_pa(nif, protocol, pa, &hwa))
+        return hwa;

-	/* 
-	 * Ok, it's not, so we need to try to obtain it by broadcasting
-	 * an ARP request.  Hopefully the desired host is listening and
-	 * will respond with it's MAC address
-	 */
-	for (i = 0; i < 3; i++)
-	{
-		arp_request(nif, pa);
+    /*
+     * Ok, it's not, so we need to try to obtain it by broadcasting
+     * an ARP request.  Hopefully the desired host is listening and
+     * will respond with it's MAC address
+     */
+    for (i = 0; i < 3; i++)
+    {
+        arp_request(nif, pa);

-		timer_set_secs(TIMER_NETWORK, ARP_TIMEOUT);
-		while (timer_get_reference(TIMER_NETWORK))
-		{
-			dbg("%s: try to resolve %d.%d.%d.%d\r\n", __FUNCTION__,
-				pa[0], pa[1], pa[2], pa[3], pa[4]);
-			if (arp_resolve_pa(nif, protocol, pa, &hwa))
-			{
-				dbg("%s: resolved to %02x:%02x:%02x:%02x:%02x:%02x.\r\n", __FUNCTION__,
-					hwa[0], hwa[1], hwa[2], hwa[3], hwa[4], hwa[5], hwa[6]);
-					
-				return hwa;
-			}
-		}
-	}
+        timer_set_secs(TIMER_NETWORK, ARP_TIMEOUT);
+        while (timer_get_reference(TIMER_NETWORK))
+        {
+            dbg("try to resolve %d.%d.%d.%d\r\n",
+                pa[0], pa[1], pa[2], pa[3], pa[4]);
+            if (arp_resolve_pa(nif, protocol, pa, &hwa))
+            {
+                dbg("resolved to %02x:%02x:%02x:%02x:%02x:%02x.\r\n",
+                    hwa[0], hwa[1], hwa[2], hwa[3], hwa[4], hwa[5], hwa[6]);

-	return NULL;
+                return hwa;
+            }
+        }
+    }
+
+    return NULL;
 }

 void arp_init(ARP_INFO *arptab)
 {
-	int slot, i;
+    int slot, i;

-	arptab->tab_size = MAX_ARP_ENTRY;
-	for (slot = 0; slot < arptab->tab_size; slot++)
-	{
-		for (i = 0; i < MAX_HWA_SIZE; i++)
-			arptab->table[slot].hwa[i] = 0;
-		for (i = 0; i < MAX_PA_SIZE; i++)
-			arptab->table[slot].pa[i] = 0;
-		arptab->table[slot].longevity = ARP_ENTRY_EMPTY;
-		arptab->table[slot].hwa_size = 0;
-		arptab->table[slot].pa_size = 0;
-	}
+    arptab->tab_size = MAX_ARP_ENTRY;
+    for (slot = 0; slot < arptab->tab_size; slot++)
+    {
+        for (i = 0; i < MAX_HWA_SIZE; i++)
+            arptab->table[slot].hwa[i] = 0;
+        for (i = 0; i < MAX_PA_SIZE; i++)
+            arptab->table[slot].pa[i] = 0;
+        arptab->table[slot].longevity = ARP_ENTRY_EMPTY;
+        arptab->table[slot].hwa_size = 0;
+        arptab->table[slot].pa_size = 0;
+    }
 }

 void arp_handler(NIF *nif, NBUF *pNbuf)
 {
-	/* 
-	 * ARP protocol handler 
-	 */
-	uint8_t *addr;
-	ARP_INFO *arptab;
-	int longevity;
-	arp_frame_hdr *rx_arpframe, *tx_arpframe;
+    /*
+     * ARP protocol handler
+     */
+    uint8_t *addr;
+    ARP_INFO *arptab;
+    int longevity;
+    arp_frame_hdr *rx_arpframe, *tx_arpframe;

-	arptab = nif_get_protocol_info(nif, ETH_FRM_ARP);
-	rx_arpframe = (arp_frame_hdr *) &pNbuf->data[pNbuf->offset];
+    arptab = nif_get_protocol_info(nif, ETH_FRM_ARP);
+    rx_arpframe = (arp_frame_hdr *) &pNbuf->data[pNbuf->offset];

-	/* 
-	 * Check for an appropriate ARP packet 
-	 */
-	if ((pNbuf->length < ARP_HDR_LEN)       ||  
-			(rx_arpframe->ar_hrd != ETHERNET)   ||
-			(rx_arpframe->ar_hln != 6)          ||
-			(rx_arpframe->ar_pro != ETH_FRM_IP) ||
-			(rx_arpframe->ar_pln != 4))
-	{
-		nbuf_free(pNbuf);
-		return;
-	}
+    /*
+     * Check for an appropriate ARP packet
+     */
+    if ((pNbuf->length < ARP_HDR_LEN)       ||
+            (rx_arpframe->ar_hrd != ETHERNET)   ||
+            (rx_arpframe->ar_hln != 6)          ||
+            (rx_arpframe->ar_pro != ETH_FRM_IP) ||
+            (rx_arpframe->ar_pln != 4))
+    {
+        dbg("received packet is not an ARP packet, discard it\r\n");
+        nbuf_free(pNbuf);
+        return;
+    }

-	/* 
-	 * Check to see if it was addressed to me - if it was, keep this
-	 * ARP entry in the table permanently; if not, mark it so that it
-	 * can be displaced later if necessary
-	 */
-	addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
-	if ((rx_arpframe->ar_tpa[0] == addr[0]) &&
-			(rx_arpframe->ar_tpa[1] == addr[1]) &&
-			(rx_arpframe->ar_tpa[2] == addr[2]) &&
-			(rx_arpframe->ar_tpa[3] == addr[3]) )
-	{
-		longevity = ARP_ENTRY_PERM;
-	}
-	else 
-		longevity = ARP_ENTRY_TEMP;
+    /*
+     * Check to see if it was addressed to me - if it was, keep this
+     * ARP entry in the table permanently; if not, mark it so that it
+     * can be displaced later if necessary
+     */
+    addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
+    if ((rx_arpframe->ar_tpa[0] == addr[0]) &&
+            (rx_arpframe->ar_tpa[1] == addr[1]) &&
+            (rx_arpframe->ar_tpa[2] == addr[2]) &&
+            (rx_arpframe->ar_tpa[3] == addr[3]) )
+    {
+        dbg("received ARP packet is a permanent one, store it\r\n");
+        longevity = ARP_ENTRY_PERM;
+    }
+    else
+    {
+        dbg("received ARP packet was not addressed to us, keep only temporarily\r\n");
+        longevity = ARP_ENTRY_TEMP;
+    }

-	/* 
-	 * Add ARP info into the table
-	 */
-	arp_merge(arptab,
-			rx_arpframe->ar_pro,
-			rx_arpframe->ar_hln,
-			&rx_arpframe->ar_sha[0],
-			rx_arpframe->ar_pln,
-			&rx_arpframe->ar_spa[0],
-			longevity
-			);
+    /*
+     * Add ARP info into the table
+     */
+    arp_merge(arptab,
+            rx_arpframe->ar_pro,
+            rx_arpframe->ar_hln,
+            &rx_arpframe->ar_sha[0],
+            rx_arpframe->ar_pln,
+            &rx_arpframe->ar_spa[0],
+            longevity
+            );

-	switch (rx_arpframe->opcode)
-	{
-		case ARP_REQUEST:
-			/* 
-			 * Check to see if request is directed to me
-			 */
-			if ((rx_arpframe->ar_tpa[0] == addr[0]) &&
-					(rx_arpframe->ar_tpa[1] == addr[1]) &&
-					(rx_arpframe->ar_tpa[2] == addr[2]) &&
-					(rx_arpframe->ar_tpa[3] == addr[3]) )
-			{
-				/*
-				 * Reuse the current network buffer to assemble an ARP reply
-				 */
-				tx_arpframe = (arp_frame_hdr *)&pNbuf->data[ARP_HDR_OFFSET];
+    switch (rx_arpframe->opcode)
+    {
+        case ARP_REQUEST:
+            /*
+             * Check to see if request is directed to me
+             */
+            if ((rx_arpframe->ar_tpa[0] == addr[0]) &&
+                    (rx_arpframe->ar_tpa[1] == addr[1]) &&
+                    (rx_arpframe->ar_tpa[2] == addr[2]) &&
+                    (rx_arpframe->ar_tpa[3] == addr[3]) )
+            {
+                dbg("received arp request directed to us, replying\r\n");
+                /*
+                 * Reuse the current network buffer to assemble an ARP reply
+                 */
+                tx_arpframe = (arp_frame_hdr *)&pNbuf->data[ARP_HDR_OFFSET];

-				/*
-				 * Build new ARP frame from the received data
-				 */
-				tx_arpframe->ar_hrd = ETHERNET;
-				tx_arpframe->ar_pro = ETH_FRM_IP;
-				tx_arpframe->ar_hln = 6;
-				tx_arpframe->ar_pln = 4;
-				tx_arpframe->opcode = ARP_REPLY;
-				tx_arpframe->ar_tha[0] = rx_arpframe->ar_sha[0];
-				tx_arpframe->ar_tha[1] = rx_arpframe->ar_sha[1];
-				tx_arpframe->ar_tha[2] = rx_arpframe->ar_sha[2];
-				tx_arpframe->ar_tha[3] = rx_arpframe->ar_sha[3];
-				tx_arpframe->ar_tha[4] = rx_arpframe->ar_sha[4];
-				tx_arpframe->ar_tha[5] = rx_arpframe->ar_sha[5];
-				tx_arpframe->ar_tpa[0] = rx_arpframe->ar_spa[0];
-				tx_arpframe->ar_tpa[1] = rx_arpframe->ar_spa[1];
-				tx_arpframe->ar_tpa[2] = rx_arpframe->ar_spa[2];
-				tx_arpframe->ar_tpa[3] = rx_arpframe->ar_spa[3];
+                /*
+                 * Build new ARP frame from the received data
+                 */
+                tx_arpframe->ar_hrd = ETHERNET;
+                tx_arpframe->ar_pro = ETH_FRM_IP;
+                tx_arpframe->ar_hln = 6;
+                tx_arpframe->ar_pln = 4;
+                tx_arpframe->opcode = ARP_REPLY;
+                tx_arpframe->ar_tha[0] = rx_arpframe->ar_sha[0];
+                tx_arpframe->ar_tha[1] = rx_arpframe->ar_sha[1];
+                tx_arpframe->ar_tha[2] = rx_arpframe->ar_sha[2];
+                tx_arpframe->ar_tha[3] = rx_arpframe->ar_sha[3];
+                tx_arpframe->ar_tha[4] = rx_arpframe->ar_sha[4];
+                tx_arpframe->ar_tha[5] = rx_arpframe->ar_sha[5];
+                tx_arpframe->ar_tpa[0] = rx_arpframe->ar_spa[0];
+                tx_arpframe->ar_tpa[1] = rx_arpframe->ar_spa[1];
+                tx_arpframe->ar_tpa[2] = rx_arpframe->ar_spa[2];
+                tx_arpframe->ar_tpa[3] = rx_arpframe->ar_spa[3];

-				/* 
-				 * Now copy in the new information 
-				 */
-				addr = &nif->hwa[0];
-				tx_arpframe->ar_sha[0] = addr[0];
-				tx_arpframe->ar_sha[1] = addr[1];
-				tx_arpframe->ar_sha[2] = addr[2];
-				tx_arpframe->ar_sha[3] = addr[3];
-				tx_arpframe->ar_sha[4] = addr[4];
-				tx_arpframe->ar_sha[5] = addr[5];
+                /*
+                 * Now copy in the new information
+                 */
+                addr = &nif->hwa[0];
+                tx_arpframe->ar_sha[0] = addr[0];
+                tx_arpframe->ar_sha[1] = addr[1];
+                tx_arpframe->ar_sha[2] = addr[2];
+                tx_arpframe->ar_sha[3] = addr[3];
+                tx_arpframe->ar_sha[4] = addr[4];
+                tx_arpframe->ar_sha[5] = addr[5];

-				addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
-				tx_arpframe->ar_spa[0] = addr[0];
-				tx_arpframe->ar_spa[1] = addr[1];
-				tx_arpframe->ar_spa[2] = addr[2];
-				tx_arpframe->ar_spa[3] = addr[3];
+                addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
+                tx_arpframe->ar_spa[0] = addr[0];
+                tx_arpframe->ar_spa[1] = addr[1];
+                tx_arpframe->ar_spa[2] = addr[2];
+                tx_arpframe->ar_spa[3] = addr[3];

-				/* 
-				 * Save the length of my packet in the buffer structure 
-				 */
-				pNbuf->length = ARP_HDR_LEN;
+                /*
+                 * Save the length of my packet in the buffer structure
+                 */
+                pNbuf->length = ARP_HDR_LEN;

-				nif->send(nif, 
-						&tx_arpframe->ar_tha[0], 
-						&tx_arpframe->ar_sha[0], 
-						ETH_FRM_ARP, 
-						pNbuf);
-			}
-			else 
-				nbuf_free(pNbuf);
-			break;
-		case ARP_REPLY:
-			/*
-			 * The ARP Reply case is already taken care of
-			 */
-		default:
-			nbuf_free(pNbuf);
-			break;
-	}
+                nif->send(nif,
+                        &tx_arpframe->ar_tha[0],
+                        &tx_arpframe->ar_sha[0],
+                        ETH_FRM_ARP,
+                        pNbuf);
+            }
+            else
+            {
+                dbg("ARP request not addressed to us, discarding\r\n");
+                nbuf_free(pNbuf);
+            }
+            break;

-	return;
+        case ARP_REPLY:
+            /*
+             * The ARP Reply case is already taken care of
+             */
+
+            /* missing break is intentional */
+
+        default:
+            nbuf_free(pNbuf);
+            break;
+    }
+
+    return;
 }
--- a/net/bootp.c
+++ b/net/bootp.c
@@ -99,7 +99,9 @@ void bootp_handler(NIF *nif, NBUF *nbuf)
 	rx_p = (struct bootp_packet *) &nbuf->data[nbuf->offset];
 	udpframe = (udp_frame_hdr *) &nbuf->data[nbuf->offset - UDP_HDR_SIZE];

-	/* check packet if it is valid and if it is really intended for us */
+    /*
+     * check packet if it is valid and if it is really intended for us
+     */

 	if (rx_p->type == BOOTP_TYPE_BOOTREPLY && rx_p->xid == XID)
 	{
@@ -109,6 +111,7 @@ void bootp_handler(NIF *nif, NBUF *nbuf)
 	}
 	else
 	{
+        dbg("received invalid bootp reply\r\n");
 		/* not valid */
 		return;
 	}
--- a/net/fec.c
+++ b/net/fec.c
@@ -32,7 +32,7 @@
 #error Unknown machine!
 #endif

-#define DBG_FEC
+// #define DBG_FEC
 #ifdef DBG_FEC
 #define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
@@ -237,33 +237,33 @@ void fec_log_init(uint8_t ch)
 */
 void fec_log_dump(uint8_t ch)
 {
-    dbg("\r\n   FEC%d Log\r\n", __FUNCTION__, ch);
-    dbg("   ---------------\r\n", __FUNCTION__);
-    dbg(" Total: %4d\r\n", fec_log[ch].total);
-    dbg(" hberr: %4d\r\n", fec_log[ch].hberr);
-    dbg(" babr:  %4d\r\n", fec_log[ch].babr);
-    dbg(" babt:  %4d\r\n", fec_log[ch].babt);
-    dbg(" gra:   %4d\r\n", fec_log[ch].gra);
-    dbg(" txf:   %4d\r\n", fec_log[ch].txf);
-    dbg(" mii:   %4d\r\n", fec_log[ch].mii);
-    dbg(" lc:    %4d\r\n", fec_log[ch].lc);
-    dbg(" rl:    %4d\r\n", fec_log[ch].rl);
-    dbg(" xfun:  %4d\r\n", fec_log[ch].xfun);
-    dbg(" xferr: %4d\r\n", fec_log[ch].xferr);
-    dbg(" rferr: %4d\r\n", fec_log[ch].rferr);
-    dbg(" dtxf:  %4d\r\n", fec_log[ch].dtxf);
-    dbg(" drxf:  %4d\r\n", fec_log[ch].drxf);
-    dbg(" \r\nRFSW:\r\n");
-    dbg(" inv:   %4d\r\n", fec_log[ch].rfsw_inv);
-    dbg(" m:     %4d\r\n", fec_log[ch].rfsw_m);
-    dbg(" bc:    %4d\r\n", fec_log[ch].rfsw_bc);
-    dbg(" mc:    %4d\r\n", fec_log[ch].rfsw_mc);
-    dbg(" lg:    %4d\r\n", fec_log[ch].rfsw_lg);
-    dbg(" no:    %4d\r\n", fec_log[ch].rfsw_no);
-    dbg(" cr:    %4d\r\n", fec_log[ch].rfsw_cr);
-    dbg(" ov:    %4d\r\n", fec_log[ch].rfsw_ov);
-    dbg(" tr:    %4d\r\n", fec_log[ch].rfsw_tr);
-    dbg(" ---------------\r\n\r\n");
+	dbg("\r\n   FEC%d Log\r\n", __FUNCTION__, ch);
+	dbg("   ---------------\r\n", __FUNCTION__);
+	dbg(" Total: %4d\r\n", fec_log[ch].total);
+	dbg(" hberr: %4d\r\n", fec_log[ch].hberr);
+	dbg(" babr:  %4d\r\n", fec_log[ch].babr);
+	dbg(" babt:  %4d\r\n", fec_log[ch].babt);
+	dbg(" gra:   %4d\r\n", fec_log[ch].gra);
+	dbg(" txf:   %4d\r\n", fec_log[ch].txf);
+	dbg(" mii:   %4d\r\n", fec_log[ch].mii);
+	dbg(" lc:    %4d\r\n", fec_log[ch].lc);
+	dbg(" rl:    %4d\r\n", fec_log[ch].rl);
+	dbg(" xfun:  %4d\r\n", fec_log[ch].xfun);
+	dbg(" xferr: %4d\r\n", fec_log[ch].xferr);
+	dbg(" rferr: %4d\r\n", fec_log[ch].rferr);
+	dbg(" dtxf:  %4d\r\n", fec_log[ch].dtxf);
+	dbg(" drxf:  %4d\r\n", fec_log[ch].drxf);
+	dbg(" \r\nRFSW:\r\n");
+	dbg(" inv:   %4d\r\n", fec_log[ch].rfsw_inv);
+	dbg(" m:     %4d\r\n", fec_log[ch].rfsw_m);
+	dbg(" bc:    %4d\r\n", fec_log[ch].rfsw_bc);
+	dbg(" mc:    %4d\r\n", fec_log[ch].rfsw_mc);
+	dbg(" lg:    %4d\r\n", fec_log[ch].rfsw_lg);
+	dbg(" no:    %4d\r\n", fec_log[ch].rfsw_no);
+	dbg(" cr:    %4d\r\n", fec_log[ch].rfsw_cr);
+	dbg(" ov:    %4d\r\n", fec_log[ch].rfsw_ov);
+	dbg(" tr:    %4d\r\n", fec_log[ch].rfsw_tr);
+	dbg(" ---------------\r\n\r\n");
 }

 /*
@@ -538,19 +538,26 @@ void fec_rx_start(uint8_t ch, int8_t *rxbd)
 {
 	uint32_t initiator;
 	int channel;
+#ifdef DBG_FEC
 	int res;
+#endif

 	/*
 	 * Make the initiator assignment
 	 */
-	res = dma_set_initiator(DMA_FEC_RX(ch));
-    dbg("dma_set_initiator(DMA_FEC_RX(%d)): %d\r\n", ch, res);
+#if defined(DBG_FEC)
+    res =
+#else
+    (void)
+#endif
+    dma_set_initiator(DMA_FEC_RX(ch));
+	dbg("dma_set_initiator(DMA_FEC_RX(%d)): %d\r\n", ch, res);

 	/*
 	 * Grab the initiator number
 	 */
 	initiator = dma_get_initiator(DMA_FEC_RX(ch));
-    dbg("dma_get_initiator(DMA_FEC_RX(%d)) = %d\r\n", ch, initiator);
+	dbg("dma_get_initiator(DMA_FEC_RX(%d)) = %d\r\n", ch, initiator);

 	/*
 	 * Determine the DMA channel running the task for the
@@ -558,7 +565,7 @@ void fec_rx_start(uint8_t ch, int8_t *rxbd)
 	 */
 	channel = dma_set_channel(DMA_FEC_RX(ch),
 			(ch == 0) ? fec0_rx_frame : fec1_rx_frame);
-    dbg("DMA channel for FEC%1d: %d\r\n", ch, channel);
+	dbg("DMA channel for FEC%1d: %d\r\n", ch, channel);

 	/*
 	 * Start the Rx DMA task
@@ -572,18 +579,18 @@ void fec_rx_start(uint8_t ch, int8_t *rxbd)
 			0,
 			initiator,
 			FECRX_DMA_PRI(ch),
-			0 
-			| MCD_FECRX_DMA   
+			0
+			| MCD_FECRX_DMA
 			| MCD_INTERRUPT
-			| MCD_TT_FLAGS_CW 
+			| MCD_TT_FLAGS_CW
 			| MCD_TT_FLAGS_RL
 			| MCD_TT_FLAGS_SP
 			,
-			0 
+			0
 			| MCD_NO_CSUM
 			| MCD_NO_BYTE_SWAP
 			);
-    dbg("Rx DMA task for FEC%1d started\r\n", ch);
+	dbg("Rx DMA task for FEC%1d started\r\n", ch);
 }

 /*
@@ -607,13 +614,13 @@ void fec_rx_continue(uint8_t ch)
 	 */
 	channel = dma_get_channel(DMA_FEC_RX(ch));

-    dbg("RX DMA channel for FEC%1d is %d\r\n", ch, channel);
+	dbg("RX DMA channel for FEC%1d is %d\r\n", ch, channel);

 	/*
 	 * Continue/restart the DMA task
 	 */
 	MCD_continDma(channel);
-    dbg("RX dma on channel %d continued\r\n", channel);
+	dbg("RX dma on channel %d continued\r\n", channel);
 }

 /*
@@ -642,9 +649,9 @@ void fec_rx_stop (uint8_t ch)
 	/* Kill the FEC Rx DMA task */
 	MCD_killDma(channel);

-	/* 
-	 * Free up the FEC requestor from the software maintained 
-	 * initiator list 
+	/*
+	 * Free up the FEC requestor from the software maintained
+	 * initiator list
 	 */
 	dma_free_initiator(DMA_FEC_RX(ch));

@@ -656,7 +663,7 @@ void fec_rx_stop (uint8_t ch)
 }

 /*
- * Receive Frame interrupt handler - this handler is called by the 
+ * Receive Frame interrupt handler - this handler is called by the
 * DMA interrupt handler indicating that a packet was successfully
 * transferred out of the Rx FIFO.
 *
@@ -671,7 +678,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
 	NBUF *cur_nbuf, *new_nbuf;
 	int keep;

-    dbg("started\r\n");
+	dbg("started\r\n");

 	while ((pRxBD = fecbd_rx_alloc(ch)) != NULL)
 	{
@@ -684,7 +691,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
 		 *  - No undefined bits should be set
 		 *  - The upper 5 bits of the length should be cleared
 		 */
-		if (!(pRxBD->status & RX_BD_L) || (pRxBD->status & 0x0608) 
+		if (!(pRxBD->status & RX_BD_L) || (pRxBD->status & 0x0608)
 				|| (pRxBD->length & 0xF800))
 		{
 			keep = false;
@@ -716,8 +723,8 @@ void fec_rx_frame(uint8_t ch, NIF *nif)

 		if (keep)
 		{
-			/* 
-			 * Pull the network buffer off the Rx ring queue 
+			/*
+			 * Pull the network buffer off the Rx ring queue
 			 */
 			cur_nbuf = nbuf_remove(NBUF_RX_RING);

@@ -733,7 +740,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
 			new_nbuf = nbuf_alloc();
 			if (new_nbuf == NULL)
 			{
-                dbg("nbuf_alloc() failed\n");
+				dbg("nbuf_alloc() failed\n");

 				/*
 				 * Can't allocate a new network buffer, so we
@@ -767,7 +774,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)


 			/*
-			 * Let the DMA know that there is a new Rx BD (in case the 
+			 * Let the DMA know that there is a new Rx BD (in case the
 			 * ring was full and the DMA was waiting for an empty one)
 			 */
 			fec_rx_continue(ch);
@@ -778,7 +785,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
 			eth_hdr = (ETH_HDR *) cur_nbuf->data;

 			/*
-			 * Pass the received packet up the network stack if the 
+			 * Pass the received packet up the network stack if the
 			 * protocol is supported in our network interface (NIF)
 			 */
 			if (nif_protocol_exist(nif, eth_hdr->type))
@@ -789,12 +796,12 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
 			else
 			{
 				nbuf_free(cur_nbuf);
-                dbg("got unsupported packet %d, trashed it\r\n", eth_hdr->type);
+				dbg("got unsupported packet %d, trashed it\r\n", eth_hdr->type);
 			}
 		}
-		else 
+		else
 		{
-			/* 
+			/*
 			 * This frame isn't a keeper
 			 * Reset the status and length, but don't need to get another
 			 * buffer since we are trashing the data in the current one
@@ -804,7 +811,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
 			pRxBD->status |= RX_BD_E;

 			/*
-			 * Move the current buffer from the beginning to the end of the 
+			 * Move the current buffer from the beginning to the end of the
 			 * Rx ring queue
 			 */
 			cur_nbuf = nbuf_remove(NBUF_RX_RING);
@@ -844,22 +851,28 @@ void fec_tx_start(uint8_t ch, int8_t *txbd)
 {
 	uint32_t initiator;
 	int channel;
-	int result;
 	void fec0_tx_frame(void);
 	void fec1_tx_frame(void);
+#ifdef DBG_FEC
 	int res;
+#endif

 	/*
 	 * Make the initiator assignment
 	 */
-	res = dma_set_initiator(DMA_FEC_TX(ch));
-    dbg("dma_set_initiator(%d) = %d\r\n", ch, res);
+#ifdef DBG_FEC
+    res =
+#else
+    (void)
+#endif
+    dma_set_initiator(DMA_FEC_TX(ch));
+	dbg("dma_set_initiator(%d) = %d\r\n", ch, res);

 	/*
 	 * Grab the initiator number
 	 */
 	initiator = dma_get_initiator(DMA_FEC_TX(ch));
-    dbg("dma_get_initiator(%d) = %d\r\n", ch, initiator);
+	dbg("dma_get_initiator(%d) = %d\r\n", ch, initiator);


 	/*
@@ -868,7 +881,7 @@ void fec_tx_start(uint8_t ch, int8_t *txbd)
 	 */
 	channel = dma_set_channel(DMA_FEC_TX(ch),
 			(ch == 0) ? fec0_tx_frame : fec1_tx_frame);
-    dbg("dma_set_channel(%d, ...) = %d\r\n", ch, channel);
+	dbg("dma_set_channel(%d, ...) = %d\r\n", ch, channel);

 	/*
 	 * Start the Tx DMA task
@@ -882,18 +895,18 @@ void fec_tx_start(uint8_t ch, int8_t *txbd)
 			0,
 			initiator,
 			FECTX_DMA_PRI(ch),
-			0 
-			| MCD_FECTX_DMA   
+			0
+			| MCD_FECTX_DMA
 			| MCD_INTERRUPT
-			| MCD_TT_FLAGS_CW 
+			| MCD_TT_FLAGS_CW
 			| MCD_TT_FLAGS_RL
 			| MCD_TT_FLAGS_SP
 			,
-			0 
+			0
 			| MCD_NO_CSUM
 			| MCD_NO_BYTE_SWAP
 			);
-    dbg("DMA tx task started\r\n");
+	dbg("DMA tx task started\r\n");
 }

 /*
@@ -916,13 +929,13 @@ void fec_tx_continue(uint8_t ch)
 	 * selected FEC
 	 */
 	channel = dma_get_channel(DMA_FEC_TX(ch));
-    dbg("dma_get_channel(DMA_FEC_TX(%d)) = %d\r\n", ch, channel);
+	dbg("dma_get_channel(DMA_FEC_TX(%d)) = %d\r\n", ch, channel);

 	/*
 	 * Continue/restart the DMA task
 	 */
 	MCD_continDma(channel);
-    dbg("DMA TX task continue\r\n");
+	dbg("DMA TX task continue\r\n");
 }

 /*
@@ -969,9 +982,9 @@ void fec_tx_stop(uint8_t ch)
 	/* Kill the FEC Tx DMA task */
 	MCD_killDma(channel);

-	/* 
-	 * Free up the FEC requestor from the software maintained 
-	 * initiator list 
+	/*
+	 * Free up the FEC requestor from the software maintained
+	 * initiator list
 	 */
 	dma_free_initiator(DMA_FEC_TX(ch));

@@ -983,7 +996,7 @@ void fec_tx_stop(uint8_t ch)
 }

 /*
- * Trasmit Frame interrupt handler - this handler is called by the 
+ * Trasmit Frame interrupt handler - this handler is called by the
 * DMA interrupt handler indicating that a packet was successfully
 * transferred to the Tx FIFO.
 *
@@ -996,7 +1009,7 @@ void fec_tx_frame(uint8_t ch)
 	NBUF *pNbuf;
 	bool is_empty = true;

-    dbg("\r\n");
+	dbg("\r\n");
 	while ((pTxBD = fecbd_tx_free(ch)) != NULL)
 	{
 		fec_log[ch].dtxf++;
@@ -1010,7 +1023,7 @@ void fec_tx_frame(uint8_t ch)
 		 * Free up the network buffer that was just transmitted
 		 */
 		nbuf_free(pNbuf);
-        dbg("free buffer %p from TX ring\r\n", pNbuf);
+		dbg("free buffer %p from TX ring\r\n", pNbuf);

 		/*
 		 * Re-initialize the Tx BD
@@ -1019,9 +1032,9 @@ void fec_tx_frame(uint8_t ch)
 		pTxBD->length = 0;
 		is_empty = false;

-	}    
+	}
 	if (is_empty)
-        dbg("transmit queue was empty!\r\n");
+		dbg("transmit queue was empty!\r\n");
 }

 void fec0_tx_frame(void)
@@ -1034,7 +1047,6 @@ void fec1_tx_frame(void)
 	fec_tx_frame(1);
 }

-/********************************************************************/
 /*
 * Send a packet out the selected FEC
 *
@@ -1044,7 +1056,7 @@ void fec1_tx_frame(void)
 *  dst     Destination MAC Address
 *  src     Source MAC Address
 *  type    Ethernet Frame Type
- *  length  Number of bytes to be transmitted (doesn't include type, 
+ *  length  Number of bytes to be transmitted (doesn't include type,
 *          src, or dest byte count)
 *  pkt     Pointer packet network buffer
 *
@@ -1059,14 +1071,14 @@ int fec_send(uint8_t ch, NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NB
 	/* Check the length */
 	if ((nbuf->length + ETH_HDR_LEN) > ETH_MTU)
 	{
-        dbg("nbuf->length (%d) + ETH_HDR_LEN (%d) exceeds ETH_MTU (%d)\r\n",
-                nbuf->length, ETH_HDR_LEN, ETH_MTU);
+		dbg("nbuf->length (%d) + ETH_HDR_LEN (%d) exceeds ETH_MTU (%d)\r\n",
+				nbuf->length, ETH_HDR_LEN, ETH_MTU);
 		return 0;
 	}

-	/* 
-	 * Copy the destination address, source address, and Ethernet 
-	 * type into the packet 
+	/*
+	 * Copy the destination address, source address, and Ethernet
+	 * type into the packet
 	 */
 	memcpy(&nbuf->data[0],  dst,   6);
 	memcpy(&nbuf->data[6],  src,   6);
@@ -1082,7 +1094,7 @@ int fec_send(uint8_t ch, NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NB
 	 */
 	nbuf_add(NBUF_TX_RING, nbuf);

-	/* 
+	/*
 	 * Setup the buffer descriptor for transmission
 	 */
 	pTxBD->data = nbuf->data;
@@ -1108,7 +1120,6 @@ int fec1_send(NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NBUF *nbuf)
 	return fec_send(1, nif, dst, src, type, nbuf);
 }

-/********************************************************************/
 /*
 * Enable interrupts on the selected FEC
 *
@@ -1145,7 +1156,7 @@ void fec_irq_enable(uint8_t ch, uint8_t lvl, uint8_t pri)
 		MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK38;
 }

-/********************************************************************/
+
 /*
 * Disable interrupts on the selected FEC
 *
@@ -1169,7 +1180,6 @@ void fec_irq_disable(uint8_t ch)
 		MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK38;
 }

-/********************************************************************/
 /*
 * FEC interrupt handler
 * All interrupts are multiplexed into a single vector for each
@@ -1192,7 +1202,7 @@ static void fec_irq_handler(uint8_t ch)
 	event = eir & MCF_FEC_EIMR(ch);

 	if (event != eir)
-        dbg("pending but not enabled: 0x%08x\r\n", (event ^ eir));
+		dbg("pending but not enabled: 0x%08x\r\n", (event ^ eir));

 	/*
 	 * Clear the event(s) in the EIR immediately
@@ -1203,8 +1213,8 @@ static void fec_irq_handler(uint8_t ch)
 	{
 		fec_log[ch].total++;
 		fec_log[ch].rferr++;
-        dbg("RFERR\r\n");
-        dbg("FECRFSR%d = 0x%08x\r\n", ch, MCF_FEC_FECRFSR(ch));
+		dbg("RFERR\r\n");
+		dbg("FECRFSR%d = 0x%08x\r\n", ch, MCF_FEC_FECRFSR(ch));
 		//fec_eth_stop(ch);
 	}

@@ -1212,14 +1222,14 @@ static void fec_irq_handler(uint8_t ch)
 	{
 		fec_log[ch].total++;
 		fec_log[ch].xferr++;
-        dbg("XFERR\r\n");
+		dbg("XFERR\r\n");
 	}

 	if (event & MCF_FEC_EIR_XFUN)
 	{
 		fec_log[ch].total++;
 		fec_log[ch].xfun++;
-        dbg("XFUN\r\n");
+		dbg("XFUN\r\n");
 		//fec_eth_stop(ch);
 	}

@@ -1227,54 +1237,54 @@ static void fec_irq_handler(uint8_t ch)
 	{
 		fec_log[ch].total++;
 		fec_log[ch].rl++;
-        dbg("RL\r\n");
+		dbg("RL\r\n");
 	}

 	if (event & MCF_FEC_EIR_LC)
 	{
 		fec_log[ch].total++;
 		fec_log[ch].lc++;
-        dbg("LC\r\n");
+		dbg("LC\r\n");
 	}

 	if (event & MCF_FEC_EIR_MII)
 	{
 		fec_log[ch].mii++;
-        dbg("MII\r\n");
+		dbg("MII\r\n");
 	}

 	if (event & MCF_FEC_EIR_TXF)
 	{
 		fec_log[ch].txf++;
-        dbg("TXF\r\n");
+		dbg("TXF\r\n");
 		fec_log_dump(0);
 	}

 	if (event & MCF_FEC_EIR_GRA)
 	{
 		fec_log[ch].gra++;
-        dbg("GRA\r\n");
+		dbg("GRA\r\n");
 	}

 	if (event & MCF_FEC_EIR_BABT)
 	{
 		fec_log[ch].total++;
 		fec_log[ch].babt++;
-        dbg("BABT\r\n");
+		dbg("BABT\r\n");
 	}

 	if (event & MCF_FEC_EIR_BABR)
 	{
 		fec_log[ch].total++;
 		fec_log[ch].babr++;
-        dbg("BABR\r\n");
+		dbg("BABR\r\n");
 	}

 	if (event & MCF_FEC_EIR_HBERR)
 	{
 		fec_log[ch].total++;
 		fec_log[ch].hberr++;
-        dbg("HBERR\r\n");
+		dbg("HBERR\r\n");
 	}
 }

@@ -1284,7 +1294,7 @@ static void fec_irq_handler(uint8_t ch)
 */
 int fec0_interrupt_handler(void* arg1, void* arg2)
 {
-	(void) arg1;
+    (void) arg1;    /* not used */
 	(void) arg2;

 	fec_irq_handler(0);
@@ -1294,7 +1304,7 @@ int fec0_interrupt_handler(void* arg1, void* arg2)

 int fec1_interrupt_handler(void* arg1, void* arg2)
 {
-	(void) arg1;
+    (void) arg1;    /* not used */
 	(void) arg2;

 	fec_irq_handler(1);
@@ -1302,7 +1312,6 @@ int fec1_interrupt_handler(void* arg1, void* arg2)
 	return 1;
 }

-/********************************************************************/
 /*
 * Configure the selected Ethernet port and enable all operations
 *
@@ -1344,9 +1353,9 @@ void fec_eth_setup(uint8_t ch, uint8_t trcvr, uint8_t speed, uint8_t duplex, con
 		 */
 #if defined(MACHINE_FIREBEE)
 		if (am79c874_init(0, 0, speed, duplex))
-            dbg("PHY init completed\r\n");
+			dbg("PHY init completed\r\n");
 		else
-            dbg("PHY init failed\r\n");
+			dbg("PHY init failed\r\n");
 #elif defined(MACHINE_M548X)
 		bcm_5222_init(0, 0, speed, duplex);
 #else
@@ -1371,7 +1380,6 @@ void fec_eth_setup(uint8_t ch, uint8_t trcvr, uint8_t speed, uint8_t duplex, con
 	MCF_FEC_ECR(ch) |= MCF_FEC_ECR_ETHER_EN;
 }

-/********************************************************************/
 /*
 * Reset the selected Ethernet port
 *
@@ -1383,7 +1391,7 @@ void fec_eth_reset(uint8_t ch)
 	// To do
 }

-/********************************************************************/
+
 /*
 * Stop the selected Ethernet port
 *
@@ -1399,7 +1407,7 @@ void fec_eth_stop(uint8_t ch)
 	 */
 	level = set_ipl(7);

-    dbg("fec %d stopped\r\n", ch);
+	dbg("fec %d stopped\r\n", ch);
 	/*
 	 * Gracefully disable the receiver and transmitter
 	 */
@@ -1421,12 +1429,12 @@ void fec_eth_stop(uint8_t ch)
 	fec_log_dump(ch);
 #endif

-	/* 
+	/*
 	 * Flush the network buffers
 	 */
 	nbuf_flush();

-	/* 
+	/*
 	 * Restore interrupt level
 	 */
 	set_ipl(level);
--- a/net/ip.c
+++ b/net/ip.c
@@ -6,11 +6,10 @@
 *
 * Modifications:
 */
+#include <bas_types.h>
 #include "net.h"
 #include "bas_printf.h"
 #include "bas_string.h"
-#include <stdint.h>
-#include <stddef.h>


 #define IP_DEBUG
@@ -44,7 +43,7 @@ uint8_t *ip_get_myip(IP_INFO *info)
 	{
 		return (uint8_t *) &info->myip[0];
 	}
-    dbg("info is NULL!\n\t");
+	dbg("info is NULL!\n\t");
 	return 0;
 }

@@ -74,9 +73,9 @@ uint8_t *ip_resolve_route(NIF *nif, IP_ADDR_P destip)

 	info = nif_get_protocol_info(nif, ETH_FRM_IP);

-    if (memcmp(destip, bc, 4) == 0)
+	if (memcmp(destip, bc, 4) == 0)
 	{
-        dbg("destip is broadcast address, no gateway needed\r\n");
+		dbg("destip is broadcast address, no gateway needed\r\n");
 		return destip;
 	}

@@ -170,7 +169,7 @@ int ip_send(NIF *nif, uint8_t *dest, uint8_t *src, uint8_t protocol, NBUF *pNbuf
 		route = ip_resolve_route(nif, dest);
 		if (route == NULL)
 		{
-            dbg("Unable to locate %d.%d.%d.%d\r\n",
+			dbg("Unable to locate %d.%d.%d.%d\r\n",
 					dest[0], dest[1], dest[2], dest[3]);
 			return 0;
 		}
@@ -178,9 +177,9 @@ int ip_send(NIF *nif, uint8_t *dest, uint8_t *src, uint8_t protocol, NBUF *pNbuf
 	else
 	{
 		route = bc;
-        dbg("route = broadcast\r\n");
-        dbg("nif = %p\r\n", nif);
-        dbg("nif->send = %p\r\n", nif->send);
+		dbg("route = broadcast\r\n");
+		dbg("nif = %p\r\n", nif);
+		dbg("nif->send = %p\r\n", nif->send);
 	}

 	return nif->send(nif, route, &nif->hwa[0], ETH_FRM_IP, pNbuf);
@@ -282,7 +281,7 @@ void ip_handler(NIF *nif, NBUF *pNbuf)
 	 */
 	ip_frame_hdr *ipframe;

-    dbg("packet received\r\n");
+	dbg("packet received\r\n");

 	ipframe = (ip_frame_hdr *) &pNbuf->data[pNbuf->offset];

@@ -291,8 +290,8 @@ void ip_handler(NIF *nif, NBUF *pNbuf)
 	 */
 	if (!validate_ip_hdr(nif, ipframe))
 	{
-        dbg("not a valid IP packet!\r\n");
-		
+		dbg("not a valid IP packet!\r\n");
+
 		nbuf_free(pNbuf);
 		return;
 	}
@@ -312,7 +311,7 @@ void ip_handler(NIF *nif, NBUF *pNbuf)
 			udp_handler(nif,pNbuf);
 			break;
 		default:
-            dbg("no protocol handler registered for protocol %d\r\n",
+			dbg("no protocol handler registered for protocol %d\r\n",
 					__FUNCTION__, IP_PROTOCOL(ipframe));
 			nbuf_free(pNbuf);
 			break;
--- a/net/nbuf.c
+++ b/net/nbuf.c
@@ -2,7 +2,7 @@
 * File:    nbuf.c
 * Purpose: Implementation of network buffer scheme.
 *
- * Notes:   
+ * Notes:
 */
 #include "queue.h"
 #include "net.h"
@@ -12,9 +12,9 @@
 #include "bas_printf.h"


-//#define DBG_NBUF
+#define DBG_NBUF
 #if defined(DBG_NBUF)
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_NBUF */
@@ -42,13 +42,13 @@ int nbuf_init(void)
 	int i;
 	NBUF *nbuf;

-	for (i=0; i<NBUF_MAXQ; ++i)
+	for (i = 0; i < NBUF_MAXQ; ++i)
 	{
 		/* Initialize all the queues */
 		queue_init(&nbuf_queue[i]);
 	}

-	dbg("%s: Creating %d net buffers of %d bytes\r\n", __FUNCTION__, NBUF_MAX, NBUF_SZ);
+	dbg("Creating %d net buffers of %d bytes\r\n", NBUF_MAX, NBUF_SZ);

 	for (i = 0; i < NBUF_MAX; ++i)
 	{
@@ -76,18 +76,19 @@ int nbuf_init(void)
 		queue_add(&nbuf_queue[NBUF_FREE], (QNODE *)nbuf);
 	}

-	dbg("%s: NBUF allocation complete\r\n", __FUNCTION__);
+	dbg("NBUF allocation complete\r\n");

 	return 0;
 }

-/* 
+/*
 * Return all the allocated memory to the heap
 */
 void nbuf_flush(void)
 {
 	NBUF *nbuf;
-	int i, level = set_ipl(7);
+	int i;
+	int level = set_ipl(7);
 	int n = 0;

 	for (i = 0; i < NBUF_MAX; ++i)
@@ -104,7 +105,7 @@ void nbuf_flush(void)
 	set_ipl(level);
 }

-/* 
+/*
 * Allocate a network buffer from the free list
 *
 * Return Value:
@@ -171,12 +172,13 @@ void nbuf_add(int q, NBUF *nbuf)
 }

 /*
- * Put all the network buffers back into the free list 
+ * Put all the network buffers back into the free list
 */
 void nbuf_reset(void)
 {
 	NBUF *nbuf;
-	int i, level = set_ipl(7);
+	int i;
+	int level = set_ipl(7);

 	for (i = 1; i < NBUF_MAXQ; ++i)
 	{
@@ -193,7 +195,9 @@ void nbuf_debug_dump(void)
 {
 #ifdef DBG_NBUF
 	NBUF *nbuf;
-	int i, j, level;
+	int i;
+	int j;
+	int level;

 	level = set_ipl(7);

@@ -204,6 +208,7 @@ void nbuf_debug_dump(void)
 		dbg("--------------------------------------\r\n");
 		j = 0;
 		nbuf = (NBUF *) queue_peek(&nbuf_queue[i]);
+
 		while (nbuf != NULL)
 		{
 			dbg("%d\t0x%08x\t0x%04x\t0x%04x\r\n", j++, nbuf->data,
--- a/net/net_timer.c
+++ b/net/net_timer.c
@@ -5,16 +5,15 @@
 *
 * Notes:
 */
+
 #include "net_timer.h"
-#include <stdint.h>
-#include <stdbool.h>
 #include "bas_printf.h"
 #include "MCF5475.h"
 #include "interrupts.h"

 //#define DBG_TMR
 #ifdef DBG_TMR
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_TMR */
@@ -43,12 +42,12 @@ int timer_default_isr(void *not_used, NET_TIMER *t)
 {
 	(void) not_used;

-	/* 
-	 * Clear the pending event 
+	/*
+	 * Clear the pending event
 	 */
 	MCF_GPT_GMS(t->ch) = 0;

-	dbg("%s: timer isr called for timer channel %d\r\n", __FUNCTION__);
+	dbg("timer isr called for timer channel %d\r\n");

 	/*
 	 * Clear the reference - the desired seconds have expired
@@ -90,8 +89,8 @@ bool timer_set_secs(uint8_t ch, uint32_t secs)
 	 */
 	MCF_GPT_GMS(ch) = 0;

-	/* 
-	 * Get the timeout in seconds 
+	/*
+	 * Get the timeout in seconds
 	 */
 	timeout = (uint16_t)(secs * net_timer[ch].cnt);

@@ -119,22 +118,21 @@ bool timer_set_secs(uint8_t ch, uint32_t secs)
 }

 uint32_t timer_get_reference(uint8_t ch)
-{   
+{
 	return (uint32_t) net_timer[ch].reference;
 }

 bool timer_init(uint8_t ch, uint8_t lvl, uint8_t pri)
 {
-	/* 
+	/*
 	 * Initialize the timer to expire after one second
-	 * 
+	 *
 	 * This routine should only be called by the project (board) specific
 	 * initialization code.
 	 */
 	if (!((ch <= 3) && (lvl <= 7) && (lvl >= 1) && (pri <= 7)))
 	{
-		dbg("%s: illegal parameters (ch=%d, lvl=%d, pri=%d)\r\n", __FUNCTION__,
-				ch, lvl, pri);
+		dbg("illegal parameters (ch=%d, lvl=%d, pri=%d)\r\n", ch, lvl, pri);

 		return false;
 	}
@@ -144,7 +142,7 @@ bool timer_init(uint8_t ch, uint8_t lvl, uint8_t pri)
 	 */
 	MCF_GPT_GMS(ch) = 0;

-	/* 
+	/*
 	 * Save off the channel, and interrupt lvl/pri information
 	 */
 	net_timer[ch].ch = ch;
@@ -154,16 +152,16 @@ bool timer_init(uint8_t ch, uint8_t lvl, uint8_t pri)
 	/*
 	 * Register the timer interrupt handler
 	 */
-	if (!isr_register_handler(TIMER_VECTOR(ch), 
+	if (!isr_register_handler(TIMER_VECTOR(ch),
 				(int (*)(void *,void *)) timer_default_isr,
-				NULL, 
+				NULL,
 				(void *) &net_timer[ch])
 	   )
 	{
-		dbg("%s: could not register timer interrupt handler\r\n", __FUNCTION__);
+		dbg("could not register timer interrupt handler\r\n");
 		return false;
 	}
-	dbg("%s: timer handler registered\r\n", __FUNCTION__);
+	dbg("timer handler registered\r\n", __FUNCTION__);

 	/*
 	 * Calculate the require CNT value to get a 1 second timeout
@@ -173,9 +171,9 @@ bool timer_init(uint8_t ch, uint8_t lvl, uint8_t pri)
 	 * CNT = Clk Freq / PRE
 	 *
 	 * The system clock frequency is defined as SYSTEM_CLOCK and
-	 * is given in MHz. We need to multiple it by 1000000 to get the 
-	 * true value.  If we assume PRE to be the maximum of 0xFFFF, 
-	 * then the CNT value needed to achieve a 1 second timeout is 
+	 * is given in MHz. We need to multiple it by 1000000 to get the
+	 * true value.  If we assume PRE to be the maximum of 0xFFFF,
+	 * then the CNT value needed to achieve a 1 second timeout is
 	 * given by:
 	 *
 	 * CNT = SYSTEM_CLOCK * (1000000/0xFFFF)
@@ -183,10 +181,10 @@ bool timer_init(uint8_t ch, uint8_t lvl, uint8_t pri)
 	net_timer[ch].pre = 0xFFFF;
 	net_timer[ch].cnt = (uint16_t) ((SYSCLK / 1000) * (1000000 / 0xFFFF));

-	/* 
-	 * Save off the appropriate mode select register value 
+	/*
+	 * Save off the appropriate mode select register value
 	 */
-	net_timer[ch].gms = (0 
+	net_timer[ch].gms = (0
 			| MCF_GPT_GMS_TMS_GPIO
 			| MCF_GPT_GMS_IEN
 			| MCF_GPT_GMS_SC
--- a/net/nif.c
+++ b/net/nif.c
@@ -11,12 +11,9 @@
 #include "bas_types.h"
 #include "bas_printf.h"

-#include <stdint.h>
-#include <stdbool.h>
-
 #define DBG_NIF
 #ifdef DBG_NIF
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_NIF */
@@ -56,13 +53,13 @@ void nif_protocol_handler(NIF *nif, uint16_t protocol, NBUF *pNbuf)
 	{
 		if (nif->protocol[index].protocol == protocol)
 		{
-			dbg("%s: call protocol handler for protocol %d at %p\r\n", __FUNCTION__, protocol,
+			dbg("call protocol handler for protocol %d at %p\r\n", protocol,
 						nif->protocol[index].handler);
 			nif->protocol[index].handler(nif,pNbuf);
 			return;
 		}
 	}
-	dbg("%s: no protocol handler found for protocol %d\r\n", __FUNCTION__, protocol);
+	dbg("no protocol handler found for protocol %d\r\n", protocol);
 }

 void *nif_get_protocol_info(NIF *nif, uint16_t protocol)
@@ -87,12 +84,12 @@ int nif_bind_protocol(NIF *nif, uint16_t protocol, void (*handler)(NIF *,NBUF *)
 {
 	/*
 	 * This function registers 'protocol' as a supported
-	 * protocol in 'nif'.  
+	 * protocol in 'nif'.
 	 */
 	if (nif->num_protocol < (MAX_SUP_PROTO - 1))
 	{
 		nif->protocol[nif->num_protocol].protocol = protocol;
-		nif->protocol[nif->num_protocol].handler = (void(*)(NIF*,NBUF*))handler;
+		nif->protocol[nif->num_protocol].handler = (void(*)(NIF *, NBUF *)) handler;
 		nif->protocol[nif->num_protocol].info = info;
 		++nif->num_protocol;

--- a/net/tftp.c
+++ b/net/tftp.c
@@ -9,10 +9,7 @@
 *
 */

-#include <stdint.h>
-#include <stdbool.h>
-#include <stddef.h>
-
+#include "bas_types.h"
 #include "bas_printf.h"
 #include "bas_string.h"
 #include "net.h"
@@ -103,7 +100,7 @@ static int tftp_ack(uint16_t blocknum)
 		nbuf_free(pNbuf);

 	return result;
-} 
+}

 static int tftp_error(uint16_t error_code, uint16_t server_port)
 {
@@ -172,7 +169,7 @@ void tftp_handler(NIF *nif, NBUF *pNbuf)
 					cnt = 0;
 				}
 				else
-				{   
+				{
 					/* Check the server's transfer ID */
 					if (tcxn.server_port != UDP_SOURCE(udpframe))
 					{
@@ -274,10 +271,10 @@ void tftp_handler(NIF *nif, NBUF *pNbuf)

 void tftp_end(int success)
 {
-	/* 
-	 * Following a successful transfer the caller should pass in 
-	 * true, there should have been no ERROR packets received, and 
-	 * the connection should have been marked as closed by the 
+	/*
+	 * Following a successful transfer the caller should pass in
+	 * true, there should have been no ERROR packets received, and
+	 * the connection should have been marked as closed by the
 	 * tftp_in_char() routine.
 	 */
 	if (success && !tcxn.error && (tcxn.open == false))
@@ -411,10 +408,10 @@ int tftp_write(NIF *nif, char *fn, IP_ADDR_P server, uint32_t begin, uint32_t en
 		/* Attempt to send the packet */
 		for (i = 0; i < 3; ++i)
 		{
-			result = udp_send(tcxn.nif, 
-					tcxn.server_ip, 
-					tcxn.my_port, 
-					tcxn.server_port, 
+			result = udp_send(tcxn.nif,
+					tcxn.server_ip,
+					tcxn.my_port,
+					tcxn.server_port,
 					pNbuf);

 			if (result == 1)
@@ -552,8 +549,8 @@ int tftp_in_char(void)

 	if (tcxn.next_char != NULL)
 	{
-		/* 
-		 * A buffer is already being worked on - grab next 
+		/*
+		 * A buffer is already being worked on - grab next
 		 * byte from it
 		 */
 		retval = *tcxn.next_char++;
@@ -561,7 +558,7 @@ int tftp_in_char(void)
 		{
 			/* The buffer is depleted; add it back to the free queue */
 			pNbuf = (NBUF *)queue_remove(&tcxn.queue);
-			
+
 			nbuf_free(pNbuf);
 			tcxn.next_char = NULL;
 		}
--- a/net/udp.c
+++ b/net/udp.c
@@ -14,7 +14,7 @@

 //#define DBG_UDP
 #if defined(DBG_UDP)
-#define dbg(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_UDP */
@@ -112,7 +112,7 @@ int udp_send(NIF *nif, uint8_t *dest, int sport, int dport, NBUF *pNbuf)

 	if (nif == NULL)
 	{
-		dbg("%s: nif is NULL\r\n", __FUNCTION__);
+        dbg("nif is NULL\r\n");
 		return 0;
 	}

@@ -141,7 +141,7 @@ int udp_send(NIF *nif, uint8_t *dest, int sport, int dport, NBUF *pNbuf)

 	myip = ip_get_myip(nif_get_protocol_info(nif, ETH_FRM_IP));

-	dbg("%s: sent UDP request to %d.%d.%d.%d from %d.%d.%d.%d\r\n", __FUNCTION__,
+    dbg("sent UDP request to %d.%d.%d.%d from %d.%d.%d.%d\r\n",
 			dest[0], dest[1], dest[2], dest[3],
 			myip[0], myip[1], myip[2], myip[3]);

@@ -159,7 +159,7 @@ void udp_handler(NIF *nif, NBUF *pNbuf)

 	udpframe = (udp_frame_hdr *) &pNbuf->data[pNbuf->offset];

-	dbg("%s: packet received\r\n", __FUNCTION__);
+    dbg("packet received\r\n",);

 	/*
 	 * Adjust the length and valid data offset of the packet we are
@@ -176,7 +176,7 @@ void udp_handler(NIF *nif, NBUF *pNbuf)
 		handler(nif, pNbuf);
 	else
 	{
-		dbg("%s: received UDP packet for non-supported port\n", __FUNCTION__);
+        dbg("received UDP packet for non-supported port\n");
 		nbuf_free(pNbuf);
 	}

--- a/pci/ehci-hcd.c
+++ b/pci/ehci-hcd.c
@@ -31,8 +31,8 @@

 //extern xQueueHandle queue_poll_hub;

-#undef DEBUG
-#undef SHOW_INFO
+//#undef DEBUG
+//#undef SHOW_INFO

 static char ehci_inited;
 static int rootdev;
@@ -112,7 +112,7 @@ static struct descriptor rom_descriptor = {
 #define ehci_is_TDI()	(0)
 #endif

-struct pci_device_id ehci_usb_pci_table[] = 
+struct pci_device_id ehci_usb_pci_table[] =
 {
 	{
 		PCI_VENDOR_ID_NEC,
@@ -208,7 +208,7 @@ static void cache_qh(struct QH *qh, int flush)
 		qh = (struct QH *)(swpl(qh->qh_link) + gehci.dma_offset);
 	}
 	qh = qh_addr(qh);
-	
+
 	/* Save first qTD pointer, needed for invalidating pass on this QH */
 	if (flush)
 	{
@@ -278,7 +278,7 @@ static int ehci_reset(void)
 	if ((gehci.ent->vendor == PCI_VENDOR_ID_NEC) && (gehci.ent->device == PCI_DEVICE_ID_NEC_USB_2))
 	{
 		debug("ehci_reset set 48MHz clock\r\n");
-	 	pci_write_config_longword(gehci.handle, 0xE4, 0x20); // oscillator
+		pci_write_config_longword(gehci.handle, 0xE4, 0x20); // oscillator
 	}
 	cmd = ehci_readl(&gehci.hcor->or_usbcmd);
 	debug("%s cmd: 0x%08x\r\n", __FUNCTION__, cmd);
@@ -291,7 +291,7 @@ static int ehci_reset(void)
 		err("EHCI fail to reset");
 		goto out;
 	}
-	
+
 	if (ehci_is_TDI())
 	{
 		reg_ptr = (uint32_t *)((u8 *)gehci.hcor + USBMODE);
@@ -553,7 +553,7 @@ static int ehci_submit_async(struct usb_device *dev, uint32_t pipe, void *buffer
 	{
 		dev->act_len = 0;
 		debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\r\n",
-		 	dev->devnum, ehci_readl(&gehci.hcor->or_usbsts),
+			dev->devnum, ehci_readl(&gehci.hcor->or_usbsts),
 			ehci_readl(&gehci.hcor->or_portsc[0]), ehci_readl(&gehci.hcor->or_portsc[1]));
 	}
 	return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
@@ -693,7 +693,7 @@ static int ehci_submit_root(struct usb_device *dev, uint32_t pipe, void *buffer,

 		case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
 			memset(tmpbuf, 0, 4);
-			reg = ehci_readl(status_reg);	
+			reg = ehci_readl(status_reg);

 			if ((reg & EHCI_PS_PR) && (portreset & (1 << swpw(req->index))))
 			{
@@ -705,7 +705,7 @@ static int ehci_submit_root(struct usb_device *dev, uint32_t pipe, void *buffer,
 				if (!ret)
 				{
 					tmpbuf[0] |= USB_PORT_STAT_RESET;
-          			reg = ehci_readl(status_reg);
+					reg = ehci_readl(status_reg);
 				}
 				else
 					err("port(%d) reset error", swpw(req->index) - 1);
@@ -739,7 +739,7 @@ static int ehci_submit_root(struct usb_device *dev, uint32_t pipe, void *buffer,
 				}
 			}
 			else
-				tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;    	
+				tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;

 			if (reg & EHCI_PS_CSC)
 				tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
@@ -886,7 +886,7 @@ static int hc_interrupt(struct ehci *ehci)
 			}
 			i--;
 		}
-	} 
+	}
 	ehci_writel(&ehci->hcor->or_usbsts, status);

 	return(1); /* interrupt was from this card */
@@ -950,7 +950,7 @@ int ehci_usb_lowlevel_init(long handle, const struct pci_device_id *ent, void **
 		gehci.ent = ent;
 	}
 	else if (!gehci.handle) /* for restart USB cmd */
-		return(-1);	
+		return(-1);

 	gehci.qh_list_unaligned = (struct QH *)driver_mem_alloc(sizeof(struct QH) + 32);
 	if (gehci.qh_list_unaligned == NULL)
@@ -983,7 +983,7 @@ int ehci_usb_lowlevel_init(long handle, const struct pci_device_id *ent, void **
 			return(-1);
 		}
 		gehci.td[i] = (struct qTD *)(((uint32_t)gehci.td_unaligned[i] + 31) & ~31);
-		memset(gehci.td[i], 0, sizeof(struct qTD));	
+		memset(gehci.td[i], 0, sizeof(struct qTD));
 	}

 	gehci.descriptor = (struct descriptor *)driver_mem_alloc(sizeof(struct descriptor));
@@ -1118,7 +1118,7 @@ int ehci_usb_lowlevel_stop(void *priv)
 	ehci_writel(&gehci.hcor->or_configflag, 0);

 	/* unblock posted write */
-	cmd = ehci_readl(&gehci.hcor->or_usbcmd);		
+	cmd = ehci_readl(&gehci.hcor->or_usbcmd);
 	ehci_reset();
 	hc_free_buffers(&gehci);
 	ehci_inited = 0;
--- a/pci/ohci-hcd.c
+++ b/pci/ohci-hcd.c
--- a/pci/pci.c
+++ b/pci/pci.c
@@ -26,7 +26,7 @@

 #include <MCF5475.h>
 #include "pci.h"
-#include "stdint.h"
+#include "bas_types.h"
 #include "bas_printf.h"
 #include "bas_string.h"
 #include "util.h"
@@ -35,7 +35,7 @@

 //#define DEBUG_PCI
 #ifdef DEBUG_PCI
-#define dbg(format, arg...) do { xprintf("DEBUG: " format "", ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DEBUG_PCI */
@@ -76,7 +76,7 @@ static int num_pci_classes = sizeof(pci_classes) / sizeof(struct pci_class);
 #define NUM_CARDS		10
 #define NUM_RESOURCES	7
 /* holds the handle of a card at position = array index */
-static int32_t handles[NUM_CARDS];	
+static int32_t handles[NUM_CARDS];

 /* holds the interrupt handler addresses (see pci_hook_interrupt() and pci_unhook_interrupt()) of the PCI cards */
 struct pci_interrupt
@@ -89,7 +89,7 @@ struct pci_interrupt
 static struct pci_interrupt interrupts[MAX_INTERRUPTS];

 /* holds the card's resource descriptors; filled in pci_device_config() */
-static struct pci_rd resource_descriptors[NUM_CARDS][NUM_RESOURCES]; 
+static struct pci_rd resource_descriptors[NUM_CARDS][NUM_RESOURCES];


 __attribute__((aligned(16))) void chip_errata_135(void)
@@ -147,13 +147,20 @@ __attribute__((interrupt)) void pci_interrupt(void)
 	dbg("PCI interrupt\r\n");
 }

+/*
+ * Although this pragma stuff should work according to the GCC docs, it doesn't seem to
+ * with m68k-atari-mint-gcc. At least not currently.
+ * I nevertheless keep it here for future reference
+ */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-function"
 static int32_t pci_get_interrupt_cause(int32_t *handles)
 {
 	int32_t handle;

 	while ((handle = *handles++) != -1)
 	{
-		uint32_t csr = swpl(pci_read_config_longword(handle, PCICSR)); 
+		uint32_t csr = swpl(pci_read_config_longword(handle, PCICSR));

 		if ((csr & (1 << 3)) && (csr & !(csr & (1 << 10))))
 		{
@@ -162,7 +169,7 @@ static int32_t pci_get_interrupt_cause(int32_t *handles)
 			return handle;
 		}
 	}
-	dbg("%s: no interrupt cause found\r\n", __FUNCTION__);
+	dbg("%s: no interrupt cause found\r\n");
 	return -1;
 }

@@ -170,6 +177,7 @@ static int32_t pci_call_interrupt_chain(int32_t handle, int32_t data)
 {
 	return data;	/* unmodified - means: not handled */
 }
+#pragma GCC diagnostic pop

 #ifdef MACHINE_M5484LITE
 /*
@@ -179,7 +187,7 @@ static int32_t pci_call_interrupt_chain(int32_t handle, int32_t data)
 void irq5_handler(void)
 {
 	int32_t handle;
-	int32_t value;
+	int32_t value = 0;
 	int32_t newvalue;

 	MCF_EPORT_EPFR |= (1 << 5);		/* clear interrupt from edge port */
@@ -189,7 +197,7 @@ void irq5_handler(void)
 		newvalue = pci_call_interrupt_chain(handle, value);
 		if (newvalue == value)
 		{
-			dbg("%s: interrupt not handled!\r\n", __FUNCTION__);
+			dbg("%s: interrupt not handled!\r\n");
 		}
 	}
 }
@@ -201,7 +209,7 @@ void irq5_handler(void)
 void irq7_handler(void)
 {
 	int32_t handle;
-	int32_t value;
+	int32_t value = 0;
 	int32_t newvalue;

 	MCF_EPORT_EPFR |= (1 << 7);
@@ -211,7 +219,7 @@ void irq7_handler(void)
 		newvalue = pci_call_interrupt_chain(handle, value);
 		if (newvalue == value)
 		{
-			dbg("%s: interrupt not handled!\r\n", __FUNCTION__);
+			dbg("%s: interrupt not handled!\r\n");
 		}
 	}
 }
@@ -266,7 +274,7 @@ uint32_t pci_read_config_longword(int32_t handle, int offset)
 			MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) |	/* device number, devices 0 - 9 are reserved */
 			MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |	/* function number */
 			MCF_PCI_PCICAR_DWORD(offset / 4);
-	
+
 	__asm__ __volatile__("nop" ::: "memory");				/* this is what the Linux BSP does */

 	pci_config_wait();
@@ -292,7 +300,7 @@ uint16_t pci_read_config_word(int32_t handle, int offset)
 			MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) |
 			MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |
 			MCF_PCI_PCICAR_DWORD(offset / 4);
-	
+
 	__asm__ __volatile("nop" ::: "memory");			/* this is what Linux BSP does */

 	value = * (volatile uint16_t *) PCI_IO_OFFSET + (offset & 2);
@@ -315,7 +323,7 @@ uint8_t pci_read_config_byte(int32_t handle, int offset)
 		MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) |		/* device number, devices 0 - 9 are reserved */
 		MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |	/* function number */
 		MCF_PCI_PCICAR_DWORD(offset / 4);
-	
+
 	__asm__ __volatile__("nop" ::: "memory");

 	value = * (volatile uint8_t *) (PCI_IO_OFFSET + (offset & 3));
@@ -366,11 +374,11 @@ int32_t pci_write_config_word(int32_t handle, int offset, uint16_t value)
 			MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) |
 			MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |
 			MCF_PCI_PCICAR_DWORD(offset / 4);
-	
+
 	__asm__ __volatile__("tpf" ::: "memory");

 	* (volatile uint16_t *) (PCI_IO_OFFSET + (offset & 2)) = value;
-	
+
 	__asm__ __volatile__("tpf" ::: "memory");

 	/* finish configuration space access cycle */
@@ -391,7 +399,7 @@ int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value)
 			MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) |
 			MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |
 			MCF_PCI_PCICAR_DWORD(offset / 4);
-	
+
 	__asm__ __volatile__("tpf" ::: "memory");

 	* (volatile uint8_t *) (PCI_IO_OFFSET + (offset & 3)) = value;
@@ -440,7 +448,7 @@ int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index)
 	uint16_t n = 0;
 	int32_t handle;

-	for (bus = 0; bus < 2; bus++)
+	for (bus = 0; bus < 1; bus++)
 	{
 		for (device = 10; device < 31; device++)
 		{
@@ -476,7 +484,7 @@ int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index)
 						value = pci_read_config_longword(handle, PCIIDR);
 						if (value != 0xFFFFFFFF)	/* device found */
 						{
-							if (vendor_id == 0xffff || 
+							if (vendor_id == 0xffff ||
 								(PCI_VENDOR_ID(value) == vendor_id && PCI_DEVICE_ID(value) == device_id))
 							{
 								if (n == index)
@@ -519,11 +527,11 @@ int32_t pci_find_classcode(uint32_t classcode, int index)
 			handle = PCI_HANDLE(bus, device, 0);

 			value = pci_read_config_longword(handle, PCIIDR);
-			
+
 			if (value != 0xffffffff)	/* device found */
 			{
 				value = pci_read_config_longword(handle, PCICCR);
-			
+
 				if ((classcode & (1 << 26) ? ((PCI_CLASS_CODE(value) == (classcode & 0xff))) : true) &&
 					(classcode & (1 << 25) ? ((PCI_SUBCLASS(value) == ((classcode & 0xff00) >> 8))) : true) &&
 					(classcode & (1 << 24) ? ((PCI_PROG_IF(value) == ((classcode & 0xff0000) >> 16))) : true))
@@ -536,10 +544,10 @@ int32_t pci_find_classcode(uint32_t classcode, int index)
 				}

 				/*
-			 	* there is a device at this position, but not the one we are looking for.
-			 	* Check to see if it is a multi-function device. We need to look "behind" it
-			 	* for the other functions in that case.
-			 	*/
+				* there is a device at this position, but not the one we are looking for.
+				* Check to see if it is a multi-function device. We need to look "behind" it
+				* for the other functions in that case.
+				*/
 				if ((htr = pci_read_config_byte(handle, PCIHTR)) & 0x80)
 				{
 					/* yes, this is a multi-function device, look for more functions */
@@ -587,7 +595,168 @@ int32_t pci_unhook_interrupt(int32_t handle)
 	return PCI_SUCCESSFUL;
 }

+/*
+ * Not implemented PCI_BIOS functions
+ */

+uint8_t pci_fast_read_config_byte(int32_t handle, uint16_t reg)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+uint16_t pci_fast_read_config_word(int32_t handle, uint16_t reg)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+uint32_t pci_fast_read_config_longword(int32_t handle, uint16_t reg)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_special_cycle(uint16_t bus, uint32_t data)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_get_routing(int32_t handle)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_set_interrupt(int32_t handle)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_get_card_used(int32_t handle, uint32_t *address)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_set_card_used(int32_t handle, uint32_t *callback)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+uint8_t pci_fast_read_mem_byte(int32_t handle, uint32_t offset)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+uint16_t pci_fast_read_mem_word(int32_t handle, uint32_t offset)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+uint32_t pci_fast_read_mem_longword(int32_t handle, uint32_t offset)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_write_mem_word(int32_t handle, uint32_t offset, uint16_t val)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_read_io_word(int32_t handle, uint32_t offset, uint16_t *address)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+uint8_t pci_fast_read_io_byte(int32_t handle, uint32_t offset)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+uint16_t pci_fast_read_io_word(int32_t handle, uint32_t offset)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+uint32_t pci_fast_read_io_longword(int32_t handle, uint32_t offset)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_write_io_byte(int32_t handle, uint32_t offset, uint16_t val)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_write_io_word(int32_t handle, uint32_t offset, uint16_t val)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_write_io_longword(int32_t handle, uint32_t offset, uint32_t val)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_get_machine_id(void)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_get_pagesize(void)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+int32_t pci_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}

 /*
 * pci_device_config()
@@ -607,6 +776,12 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
 	static uint32_t io_address = PCI_IO_OFFSET;
 	uint16_t cr;

+	/*
+	 * should make compiler happy (these are used only in debug builds)
+	 */
+	(void) value;
+	(void) il;
+
 	/* determine pci handle from bus, device + function number */
 	handle = PCI_HANDLE(bus, device, function);

@@ -622,7 +797,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
 	/*
 	 * disable device
 	 */
-	
+
 	cr = swpw(pci_read_config_word(handle, PCICSR));
 	cr &= ~3;	/* disable device response to address */
 	pci_write_config_word(handle, PCICSR, swpw(cr));
@@ -647,9 +822,9 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
 			/*
 			 * resource descriptor for this device
 			 */
-			struct pci_rd *rd = &descriptors[barnum]; 
+			struct pci_rd *rd = &descriptors[barnum];

-			dbg("%s: address = %08x\r\n", __FUNCTION__, address);
+			dbg("%s: address = %08x\r\n", address);
 			if (IS_PCI_MEM_BAR(address))
 			{
 				/* adjust base address to card's alignment requirements */
@@ -664,7 +839,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)

 				/* read it back, just to be sure */
 				value = swpl(pci_read_config_longword(handle, PCIBAR0 + i)) & ~1;
-				
+
 				dbg("set PCIBAR%d on device 0x%02x to 0x%08x\r\n",
 						i / 4, handle, value);

@@ -673,7 +848,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
 				rd->flags = 0 | FLG_32BIT | FLG_16BIT | FLG_8BIT | 2; /* little endian, lane swapped */
 				rd->start = address;
 				rd->length = size;
-				rd->offset = 0; 
+				rd->offset = 0;
 				rd->dmaoffset = 0;

 				/* adjust memory adress for next turn */
@@ -708,7 +883,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
 				cr |= 1;

 				barnum++;
-			}		
+			}
 		}
 	}

@@ -728,7 +903,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
 	address = swpl(pci_read_config_longword(handle, PCIERBAR));
 	if (address & 1)
 	{
-		struct pci_rd *rd = &descriptors[barnum]; 
+		struct pci_rd *rd = &descriptors[barnum];
 		int size = ~(address & ~0x7ff);

 		/* expansion ROM active and mapped */
@@ -738,10 +913,10 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)

 		/* write it to PCIERBAR and enable ROM */
 		pci_write_config_longword(handle, PCIERBAR, swpl(address | 1));
-		dbg("%s: set PCIERBAR on device 0x%02x to 0x%08x\r\n", __FUNCTION__, handle, address | 1);
+		dbg("%s: set PCIERBAR on device 0x%02x to 0x%08x\r\n", handle, address | 1);

 		/* read value back just to be sure */
-		dbg("%s: PCIERBAR = %p\r\n", __FUNCTION__, swpl(pci_read_config_longword(handle, PCIERBAR)));
+		dbg("%s: PCIERBAR = %p\r\n", swpl(pci_read_config_longword(handle, PCIERBAR)));


 		rd->next = sizeof(struct pci_rd);
@@ -762,11 +937,11 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
 	/* check if device requests an interrupt */
 	il = pci_read_config_byte(handle, PCIIPR);
 	dbg("device requests interrupts on interrupt pin %d\r\n", il);
-			
+
 	/* if so, register interrupts */
-	
+
 	/* TODO: register interrupts here */
-	
+
 	/*
 	 * enable device memory or I/O access
 	 */
@@ -874,7 +1049,7 @@ void init_xlbus_arbiter(void)
 	{
 		MCF_XLB_XARB_CFG = MCF_XLB_XARB_CFG_BA |
 			MCF_XLB_XARB_CFG_DT |
-			MCF_XLB_XARB_CFG_AT; 
+			MCF_XLB_XARB_CFG_AT;
 	}

 	MCF_XLB_XARB_ADRTO = 0x1fffff;
@@ -888,7 +1063,7 @@ void init_xlbus_arbiter(void)
 	 * M2 = Multichannel DMA
 	 * M3 = PCI target interface
 	 */
-	
+
 	MCF_XLB_XARB_PRIEN = MCF_XLB_XARB_PRIEN_M0 |	/* activate programmed priority for Coldfire core */
 					MCF_XLB_XARB_PRIEN_M2 |			/* activate programmed priority for Multichannel DMA */
 					MCF_XLB_XARB_PRIEN_M3;			/* activate programmed priority for PCI target interface */
@@ -920,9 +1095,9 @@ void init_pci(void)
 	 * setup the PCI arbiter
 	 */
 	MCF_PCIARB_PACR = MCF_PCIARB_PACR_INTMPRI	/* internal master priority: high */
-       | MCF_PCIARB_PACR_EXTMPRI(0xf)			/* external master priority: high */
-       | MCF_PCIARB_PACR_INTMINTEN				/* enable "internal master broken" interrupt */
-       | MCF_PCIARB_PACR_EXTMINTEN(0x0f);		/* enable "external master broken" interrupt */
+	   | MCF_PCIARB_PACR_EXTMPRI(0xf)			/* external master priority: high */
+	   | MCF_PCIARB_PACR_INTMINTEN				/* enable "internal master broken" interrupt */
+	   | MCF_PCIARB_PACR_EXTMINTEN(0x0f);		/* enable "external master broken" interrupt */

 #ifdef _NOT_USED_	/* since this is already done in sysinit.c */
 #if MACHINE_FIREBEE
@@ -939,7 +1114,7 @@ void init_pci(void)
 		MCF_PCI_PCISCR_M |		/* mem access enable */
 		MCF_PCI_PCISCR_MA |		/* clear master abort error */
 		MCF_PCI_PCISCR_MW;		/* memory write and invalidate enabled */
-		
+

 	/* Setup burst parameters */
 	MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(8) |
@@ -956,14 +1131,14 @@ void init_pci(void)
 		MCF_PCI_PCIICR_IAE; 				/* initiator abort enable */
 #endif /* NOT_USED */
 	MCF_PCI_PCIICR = 0;						/* this is what Linux does */
-	
+
 	MCF_PCI_PCIGSCR |= MCF_PCI_PCIGSCR_SEE;	/* system error interrupt enable */

 	/* Configure Initiator Windows */

 	/* initiator window 0 base / translation adress register */
 	MCF_PCI_PCIIW0BTAR = (PCI_MEMORY_OFFSET | (((PCI_MEMORY_SIZE - 1) >> 8) & 0xffff0000))
-						  | ((PCI_MEMORY_OFFSET >> 16) & 0xff00); 
+						  | ((PCI_MEMORY_OFFSET >> 16) & 0xff00);

 	dbg("PCIIW0BTAR=0x%08x\r\n", MCF_PCI_PCIIW0BTAR);

@@ -1055,4 +1230,4 @@ void pci_print_device_config(int32_t handle)
 }
 #endif /* DEBUG_PCI */

-	
+
--- a/pci/pci_wrappers.S
+++ b/pci/pci_wrappers.S
@@ -0,0 +1,469 @@
+/*
+ * pci.S
+ *
+ * Purpose:		PCI configuration for the Coldfire builtin PCI bridge.
+ *
+ * Notes:
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 08.05.2014
+ *      Author: David Galvez
+ */
+
+.global _wrapper_find_pci_device
+.global _wrapper_find_pci_classcode
+
+.global _wrapper_read_config_longword
+.global _wrapper_read_config_word
+.global _wrapper_read_config_byte
+
+.global _wrapper_fast_read_config_byte
+.global _wrapper_fast_read_config_word
+.global _wrapper_fast_read_config_longword
+
+.global _wrapper_write_config_longword
+.global _wrapper_write_config_word
+.global _wrapper_write_config_byte
+
+.global _wrapper_get_resource
+.global _wrapper_hook_interrupt
+.global _wrapper_unhook_interrupt
+
+.global _wrapper_special_cycle
+.global _wrapper_get_routing
+.global _wrapper_set_interrupt
+.global _wrapper_get_resource
+.global _wrapper_get_card_used
+.global _wrapper_set_card_used
+
+.global _wrapper_read_mem_byte
+.global _wrapper_read_mem_word
+.global _wrapper_read_mem_longword
+
+.global _wrapper_fast_read_mem_byte
+.global _wrapper_fast_read_mem_word
+.global _wrapper_fast_read_mem_longword
+
+.global _wrapper_write_mem_byte
+.global _wrapper_write_mem_word
+.global _wrapper_write_mem_longword
+
+.global _wrapper_read_io_byte
+.global _wrapper_read_io_word
+.global _wrapper_read_io_longword
+
+.global _wrapper_fast_read_io_byte
+.global _wrapper_fast_read_io_word
+.global _wrapper_fast_read_io_longword
+
+.global _wrapper_write_io_byte
+.global _wrapper_write_io_word
+.global _wrapper_write_io_longword
+
+.global _wrapper_get_machine_id
+.global _wrapper_get_pagesize
+
+.global _wrapper_virt_to_bus
+.global _wrapper_bus_to_virt
+.global _wrapper_virt_to_phys
+.global _wrapper_phys_to_virt
+
+
+_wrapper_find_pci_device:
+	move.l D1,-(SP)			// index
+	move.l D0,-(SP)			// Vendor ID
+	move.l #16,D1
+	lsr.l D1,D0
+	move.l D0,-(SP)			// Device ID
+	jsr _pci_find_device
+	add.l #12,SP
+	rts
+
+_wrapper_find_pci_classcode:
+	move.l D1,-(SP)			// index
+	move.l D0,-(SP)			// ID
+	jsr _pci_find_classcode
+	addq.l #8,SP
+	rts
+
+_wrapper_read_config_byte:
+	move.l A0,-(SP)			// pointer to space for read data
+	move.l D1,-(SP)			// PCI register
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_config_byte
+	move.l 8(SP),A0			// PCI_BIOS expects value in memory
+	move.l D0,(A0)
+	add.l #12,SP
+	move.l #0,D0
+	rts
+
+_wrapper_read_config_word:
+	move.l A0,-(SP)			// pointer to space for read data
+	move.l D1,-(SP)			// PCI register
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_config_word
+	move.l 8(SP),A0			// little to big endian
+	move.l D0,(A0)
+	mvz.b 1(A0),D0
+	lsl.l #8,D0
+	move.b (A0),D0
+	move.l D0,(A0)			// PCI_BIOS expects value in memory, not in D0
+	add.l #12,SP
+	move.l #0,D0
+	rts
+
+_wrapper_read_config_longword:
+	move.l A0,-(SP)			// pointer to space for read data
+	move.l D1,-(SP)			// PCI register
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_config_longword
+	move.l 8(SP),A0			// little to big endian
+	move.l D0,(A0)
+	mvz.b 3(A0),D0
+	lsl.l #8,D0
+	move.b 2(A0),D0
+	lsl.l #8,D0
+	move.b 1(A0),D0
+	lsl.l #8,D0
+	move.b (A0),D0
+	move.l D0,(A0)			// PCI_BIOS expects value in memory, not in D0
+	add.l #12,SP
+	move.l #0,D0
+	rts
+
+/* Not implemented */
+_wrapper_fast_read_config_byte:
+	move.l D1,-(SP)			// PCI register
+	move.l D0,-(SP)			// handle
+	jsr _pci_fast_read_config_byte
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_fast_read_config_word:
+	move.l D1,-(SP)			// PCI register
+	move.l D0,-(SP)			// handle
+	jsr _pci_fast_read_config_word
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_fast_read_config_longword:
+	move.l D1,-(SP)			// PCI register
+	move.l D0,-(SP)			// handle
+	jsr _pci_fast_read_config_longword
+	addq.l #8,SP
+	rts
+
+_wrapper_write_config_byte:
+	move.l D2,-(SP)			// data to write
+	move.l D1,-(SP)			// PCI register
+	move.l D0,-(SP)			// handle
+	jsr _pci_write_config_byte
+	add.l #12,SP
+	rts
+
+_wrapper_write_config_word:
+	move.l D0,-(SP)			// make data little endian
+	moveq #0,D1
+	move.w D2,D1
+	lsr.l #8,D1
+	asl.l #8,D2
+	or.l D1,D2
+	move.l (SP)+,D0
+	move.l D2,-(SP)			// data to write
+	move.l D1,-(SP)			// PCI register
+	move.l D0,-(SP)			// handle
+	jsr _pci_write_config_word
+	add.l #12,SP
+	rts
+
+_wrapper_write_config_longword:
+	move.l D0,-(SP)
+	move.l D2,D0			// make data little endian
+	lsr.l #8,D0
+	asl.l #8,D2
+	and.l #0x00FF00FF,D0
+	and.l #0xFF00FF00,D2
+	or.l D0,D2
+	swap D2
+	move.l (SP)+,D0
+	move.l D2,-(SP)			// data to write
+	move.l D1,-(SP)			// PCI register
+	move.l D0,-(SP)			// handle
+	jsr _pci_write_config_longword
+	add.l #12,SP
+	rts
+
+_wrapper_hook_interrupt:
+	move.l A1,-(SP)			// parameter for interrupt handler
+	move.l A0,-(SP)			// pointer to interrupt handler
+	move.l D0,-(SP)			// handle
+	jsr _pci_hook_interrupt
+	add.l #12,SP
+	rts
+
+_wrapper_unhook_interrupt:
+	move.l D0,-(SP)			// handle
+	jsr _pci_unhook_interrupt
+	addq.l #4,SP
+	rts
+
+/* Not implemented */
+_wrapper_special_cycle:
+	move.l D1,-(SP)			// special cycle data
+	move.l D0,-(SP)			// bus number
+	jsr _pci_special_cycle
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_get_routing:
+	move.l D0,-(SP)			// handle
+	jsr _pci_get_routing
+	addq.l #4,SP
+	rts
+
+/* Not implemented */
+_wrapper_set_interrupt:
+	move.l D1,-(SP)			// mode
+	move.l D0,-(SP)			// handle
+	jsr _pci_set_interrupt
+	addq.l #8,SP
+	rts
+
+_wrapper_get_resource:
+	move.l D0,-(SP)			// handle
+	jsr _pci_get_resource
+	addq.l #4,SP
+	rts
+
+/* Not implemented */
+_wrapper_get_card_used:
+	move.l D1,-(SP)			// address
+	move.l D0,-(SP)			// handle
+	jsr _pci_get_card_used
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_set_card_used:
+	move.l A0,-(SP)			// callback
+	move.l D0,-(SP)			// handle
+	jsr _pci_set_card_used
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_read_mem_byte:
+	move.l A0,-(SP)			// pointer to data in memory
+	move.l D1,-(SP)			// address to access (in PCI memory address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_mem_byte
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_read_mem_word:
+	move.l A0,-(SP)			// pointer to data in memory
+	move.l D1,-(SP)			// address to access (in PCI memory address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_mem_word
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_read_mem_longword:
+	move.l A0,-(SP)			// pointer to data in memory
+	move.l D1,-(SP)			// address to access (in PCI memory address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_mem_longword
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_fast_read_mem_byte:
+	move.l D1,-(SP)			// address to access (in PCI memory address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_mem_byte
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_fast_read_mem_word:
+	move.l D1,-(SP)			// address to access (in PCI memory address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_mem_word
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_fast_read_mem_longword:
+	move.l D1,-(SP)			// address to access (in PCI memory address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_mem_longword
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_write_mem_byte:
+	move.l D2,-(SP)			// data to write
+	move.l D1,-(SP)			// address to access (in PCI memory address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_write_mem_byte
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_write_mem_word:
+	move.l D2,-(SP)			// data to write
+	move.l D1,-(SP)			// address to access (in PCI memory address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_write_mem_word
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_write_mem_longword:
+	move.l D2,-(SP)			// data to write
+	move.l D1,-(SP)			// address to access (in PCI memory address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_write_mem_longword
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_read_io_byte:
+	move.l A0,-(SP)			// pointer to data in memory
+	move.l D1,-(SP)			// address to access (in PCI I/O address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_io_byte
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_read_io_word:
+	move.l A0,-(SP)			// pointer to data in memory
+	move.l D1,-(SP)			// address to access (in PCI I/O address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_io_word
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_read_io_longword:
+	move.l A0,-(SP)			// pointer to data in memory
+	move.l D1,-(SP)			// address to access (in PCI I/O address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_io_longword
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_fast_read_io_byte:
+	move.l D1,-(SP)			// address to access (in PCI I/O address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_io_byte
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_fast_read_io_word:
+	move.l D1,-(SP)			// address to access (in PCI I/O address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_io_word
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_fast_read_io_longword:
+	move.l D1,-(SP)			// address to access (in PCI I/O address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_io_longword
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_write_io_byte:
+	move.l D2,-(SP)			// data to write
+	move.l D1,-(SP)			// address to access (in PCI I/O address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_write_io_byte
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_write_io_word:
+	move.l D2,-(SP)			// data to write
+	move.l D1,-(SP)			// address to access (in PCI I/O address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_write_io_word
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_write_io_longword:
+	move.l D2,-(SP)			// data to write
+	move.l D1,-(SP)			// address to access (in PCI I/O address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_write_io_longword
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_get_machine_id:
+	jsr _pci_get_machine_id
+	rts
+
+/* Not implemented */
+_wrapper_get_pagesize:
+	jsr _pci_get_pagesize
+	rts
+
+/* Not implemented */
+_wrapper_virt_to_bus:
+	move.l A0,-(SP)			// ptr
+	move.l D1,-(SP)			// address in virtual CPU space
+	move.l D0,-(SP)			// handle
+	jsr _pci_virt_to_bus
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_bus_to_virt:
+	move.l A0,-(SP)			// ptr
+	move.l D1,-(SP)			// PCI bus address
+	move.l D0,-(SP)			// handle
+	jsr _pci_bus_to_virt
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_virt_to_phys:
+	move.l A0,-(SP)			// ptr
+	move.l D0,-(SP)			// address in virtual CPU space
+	jsr _pci_virt_to_phys
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_phys_to_virt:
+	move.l A0,-(SP)			// ptr
+	move.l D0,-(SP)			// physical CPU address 
+	jsr _pci_phys_to_virt
+	addq.l #8,SP
+	rts
--- a/radeon/radeon_cursor.c
+++ b/radeon/radeon_cursor.c
@@ -44,11 +44,13 @@
 *
 */

+#include "bas_types.h"
+#include "bas_printf.h"
 #include "radeonfb.h"

 #define DBG_RADEON
 #ifdef DBG_RADEON
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_RADEON */
@@ -66,20 +68,20 @@
 #define CURSOR_SWAPPING_DECL_MMIO
 #define CURSOR_SWAPPING_DECL	    unsigned long  __surface_cntl=0;
 #define CURSOR_SWAPPING_START() \
-	if(rinfo->big_endian) \
+    if (rinfo->big_endian) \
    OUTREG(SURFACE_CNTL, \
 	   ((__surface_cntl = INREG(SURFACE_CNTL)) | \
 	    NONSURF_AP0_SWP_32BPP) & \
 	   ~NONSURF_AP0_SWP_16BPP);
 #define CURSOR_SWAPPING_END() \
-	if(rinfo->big_endian) \
+    if (rinfo->big_endian) \
 	(OUTREG(SURFACE_CNTL, __surface_cntl));

 /* Set cursor foreground and background colors */
 void radeon_set_cursor_colors(struct fb_info *info, int bg, int fg)
 {
 	struct radeonfb_info *rinfo = info->par;
-	unsigned long *pixels = (unsigned long *)((unsigned long) rinfo->fb_base+rinfo->cursor_start);
+    unsigned long *pixels = (unsigned long *)((unsigned long) rinfo->fb_base + rinfo->cursor_start);
 	int pixel, i;
 	CURSOR_SWAPPING_DECL_MMIO
 	CURSOR_SWAPPING_DECL
@@ -88,15 +90,17 @@ void radeon_set_cursor_colors(struct fb_info *info, int bg, int fg)
 	fg |= 0xff000000;
 	bg |= 0xff000000;
 	/* Don't recolour the image if we don't have to. */
-	if(fg == rinfo->cursor_fg && bg == rinfo->cursor_bg)
+    if (fg == rinfo->cursor_fg && bg == rinfo->cursor_bg)
 		return;
 	CURSOR_SWAPPING_START();
-	/* Note: We assume that the pixels are either fully opaque or fully
+
+    /*
+     * Note: We assume that the pixels are either fully opaque or fully
 	 * transparent, so we won't premultiply them, and we can just
 	 * check for non-zero pixel values; those are either fg or bg
 	 */
-	for(i = 0; i < CURSOR_WIDTH * CURSOR_HEIGHT; i++, pixels++)
-		if((pixel = *pixels))
+    for (i = 0; i < CURSOR_WIDTH * CURSOR_HEIGHT; i++, pixels++)
+        if ((pixel = *pixels))
 			*pixels = (pixel == rinfo->cursor_fg) ? fg : bg;
 	CURSOR_SWAPPING_END();
 	rinfo->cursor_fg = fg;
@@ -112,27 +116,30 @@ void radeon_set_cursor_position(struct fb_info *info, int x, int y)
 	struct fb_var_screeninfo *mode = &info->var;
 	int xorigin = 0;
 	int yorigin = 0;
-	if(mode->vmode & FB_VMODE_DOUBLE)
+    if (mode->vmode & FB_VMODE_DOUBLE)
 		y <<= 1;
-	if(x < 0)
+    if (x < 0)
 		xorigin = 1 - x;
-	if(y < 0)
+    if (y < 0)
 	  yorigin = 1 - y;
+
 //	DPRINTVALHEX("radeonfb: RADEONSetCursorPosition: cursor_start ",rinfo->cursor_start);
 //	DPRINTVAL(" x ",x);
 //	DPRINTVAL(" y ",y);
 //	DPRINT("\r\n");
+
 	OUTREG(CUR_HORZ_VERT_OFF, (CUR_LOCK  | (xorigin << 16) | yorigin));
 	OUTREG(CUR_HORZ_VERT_POSN, (CUR_LOCK | ((xorigin ? 0 : x) << 16) | (yorigin ? 0 : y)));
 	OUTREG(CUR_OFFSET, rinfo->cursor_start + yorigin * 256);
 	rinfo->cursor_x = (unsigned long)x;
-	if(mode->vmode & FB_VMODE_DOUBLE)
-		rinfo->cursor_y = (unsigned long)y >> 1;
+    if (mode->vmode & FB_VMODE_DOUBLE)
+        rinfo->cursor_y = (unsigned long) y >> 1;
 	else
-		rinfo->cursor_y = (unsigned long)y;
+        rinfo->cursor_y = (unsigned long) y;
 }

-/* Copy cursor image from `image' to video memory.  RADEONSetCursorPosition
+/*
+ * Copy cursor image from `image' to video memory.  RADEONSetCursorPosition
 * will be called after this, so we can ignore xorigin and yorigin.
 */
 void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsigned short *data, int zoom)
@@ -143,11 +150,14 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
 	unsigned short chunk, mchunk;
 	unsigned long i, j, k;
 	CURSOR_SWAPPING_DECL
+
 //	DPRINTVALHEX("radeonfb: RADEONLoadCursorImage: cursor_start ",rinfo->cursor_start);
-//	DPRINT("\r\n");	
+//	DPRINT("\r\n");
+
 	save = INREG(CRTC_GEN_CNTL) & ~(unsigned long) (3 << 20);
 	save |= (unsigned long) (2 << 20);
 	OUTREG(CRTC_GEN_CNTL, save & (unsigned long)~CRTC_CUR_EN);
+
 	/*
 	 * Convert the bitmap to ARGB32.
 	 */
@@ -157,22 +167,22 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
 	{
 	case 1:
 	default:
-		for(i = 0; i < CURSOR_HEIGHT; i++)
+        for (i = 0; i < CURSOR_HEIGHT; i++)
 		{
-			if(i < 16)
+            if (i < 16)
 			{
 				mchunk = *mask++;
 				chunk = *data++;
 			}
 			else
 				mchunk = chunk = 0;
-			for(j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j++)
+            for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j++)
 			{
-				for(k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
+                for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
 				{
-					if(mchunk & 0x8000)
+                    if (mchunk & 0x8000)
 					{
-						if(chunk & 0x8000)
+                        if (chunk & 0x8000)
 							*d++ = 0xff000000; /* Black, fully opaque. */				
 						else
 							*d++ = 0xffffffff; /* White, fully opaque. */
@@ -184,13 +194,13 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
 		}
 		break;
 	case 2:
-		for(i = 0; i < CURSOR_HEIGHT; i++)
+        for (i = 0; i < CURSOR_HEIGHT; i++)
 		{
-			if(i < 16*2)
+            if (i < 16*2)
 			{
 				mchunk = *mask;
 				chunk = *data;
-				if((i & 1) == 1)
+                if ((i & 1) == 1)
 				{
 					mask++;
 					data++;
@@ -198,13 +208,13 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
 			}
 			else
 				mchunk = chunk = 0;
-			for(j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=2)
+            for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=2)
 			{
-				for(k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
+                for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
 				{
-					if(mchunk & 0x8000)
+                    if (mchunk & 0x8000)
 					{
-						if(chunk & 0x8000)
+                        if (chunk & 0x8000)
 						{
 							*d++ = 0xff000000; /* Black, fully opaque. */				
 							*d++ = 0xff000000; 
@@ -225,13 +235,13 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
 		}
 		break;
 	case 4:
-		for(i = 0; i < CURSOR_HEIGHT; i++)
+        for (i = 0; i < CURSOR_HEIGHT; i++)
 		{
-			if(i < 16*4)
+            if (i < 16 * 4)
 			{
 				mchunk = *mask;
 				chunk = *data;
-				if((i & 3) == 3)
+                if ((i & 3) == 3)
 				{
 					mask++;
 					data++;
@@ -239,13 +249,13 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
 			}
 			else
 				mchunk = chunk = 0;
-			for(j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=4)
+            for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=4)
 			{
-				for(k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
+                for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
 				{
-					if(mchunk & 0x8000)
+                    if (mchunk & 0x8000)
 					{
-						if(chunk & 0x8000)
+                        if (chunk & 0x8000)
 						{
 							*d++ = 0xff000000; /* Black, fully opaque. */				
 							*d++ = 0xff000000; 
@@ -282,6 +292,7 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
 void radeon_hide_cursor(struct fb_info *info)
 {
 	struct radeonfb_info *rinfo = info->par;
+
 //	DPRINT("radeonfb: RADEONHideCursor\r\n");
 	OUTREGP(CRTC_GEN_CNTL, 0, ~CRTC_CUR_EN);
 	rinfo->cursor_show = 0;
@@ -291,6 +302,7 @@ void radeon_hide_cursor(struct fb_info *info)
 void radeon_show_cursor(struct fb_info *info)
 {
 	struct radeonfb_info *rinfo = info->par;
+
 //	DPRINT("radeonfb: RADEONShowCursor\r\n");
 	OUTREGP(CRTC_GEN_CNTL, CRTC_CUR_EN, ~CRTC_CUR_EN);
 	rinfo->cursor_show = 1;
@@ -303,9 +315,9 @@ long radeon_cursor_init(struct fb_info *info)
 	int size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT;
 	unsigned long fbarea = offscreen_alloc(rinfo->info, size_bytes + 256);

-	dbg("radeonfb: %s: fbarea: %p\r\n", __FUNCTION__, fbarea);
+    dbg("radeonfb: %s: fbarea: %p\r\n", fbarea);

-	if(!fbarea)
+    if (!fbarea)
 		rinfo->cursor_start = 0;
 	else
 	{
--- a/spi/dspi.c
+++ b/spi/dspi.c
@@ -25,7 +25,6 @@
 *      Author: mfro
 */

-#include <stdint.h>
 #include <bas_types.h>
 #include <MCF5475.h>

@@ -36,7 +35,7 @@ struct baudrate
 	int	divider;
 };

-static const int system_clock = 133000000;	/* System clock in Hz */
+static const int system_clock = 132000000;	/* System clock in Hz */

 struct baudrate baudrates[] =
 {
--- a/spi/mmc.c
+++ b/spi/mmc.c
@@ -1,4 +1,3 @@
-#include <stdint.h>
 #include <bas_types.h>
 #include <sd_card.h>
 #include <bas_printf.h>
@@ -466,7 +465,7 @@ DSTATUS disk_initialize(uint8_t drv)
 	{
 		uint8_t buff[16];
 		res = disk_ioctl(0, MMC_GET_CSD, buff);
-		
+
 		if (res == RES_OK)
 		{
 			debug_printf("CSD of card:\r\n");
--- a/sys/BaS.c
+++ b/sys/BaS.c
@@ -21,8 +21,7 @@
 * Copyright 2012        M. Froeschle
 */

-#include <stdint.h>
-#include <stdbool.h>
+#include <bas_types.h>

 #include "MCF5475.h"
 #include "startcf.h"
@@ -52,7 +51,7 @@

 //#define BAS_DEBUG
 #if defined(BAS_DEBUG)
-#define dbg(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif
@@ -109,7 +108,7 @@ uint8_t read_pic_byte(void)
 	waitfor(1000, pic_rxready);

 	/* Return the received byte */
-	return *(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT); // Really 8-bit
+	return * (volatile uint8_t *) (&MCF_PSC3_PSCTB_8BIT); // Really 8-bit
 }

 void pic_init(void)
@@ -132,7 +131,7 @@ void pic_init(void)

 	if (answer[0] != 'O' || answer[1] != 'K' || answer[2] != '!')
 	{
-		dbg("%s: PIC initialization failed. Already initialized?\r\n", __FUNCTION__);
+		dbg("PIC initialization failed. Already initialized?\r\n");
 	}
 	else
 	{
@@ -203,12 +202,12 @@ void acia_init()
 void enable_coldfire_interrupts()
 {
 	xprintf("enable interrupts: ");
-#if MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
 	*FPGA_INTR_CONTRL = 0L;				/* disable all interrupts */
 #endif /* MACHINE_FIREBEE */
 	MCF_EPORT_EPPAR = 0xaaa8;			/* all interrupts on falling edge */

-#if MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
 	/*
 	 * TIN0 on the Coldfire is connected to the FPGA. TIN0 triggers every write
 	 * access to 0xff8201 (vbasehi), i.e. everytime the video base address is written
@@ -231,9 +230,10 @@ void enable_coldfire_interrupts()

 void disable_coldfire_interrupts()
 {
-#ifdef MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
 	*FPGA_INTR_ENABLE = 0;		/* disable all interrupts */
 #endif /* MACHINE_FIREBEE */
+
 	MCF_EPORT_EPIER = 0x0;
 	MCF_EPORT_EPFR = 0x0;
 	MCF_INTC_IMRL = 0xfffffffe;
@@ -243,75 +243,46 @@ void disable_coldfire_interrupts()


 NIF nif1;
-#ifdef MACHINE_M5484LITE
+#if defined(MACHINE_M5484LITE)
 NIF nif2;
 #endif
-static IP_INFO ip_info;
-static ARP_INFO	arp_info;

-
-void network_init(void)
+/*
+ * initialize the interrupt handler tables to dispatch interrupt requests from Coldfire devices
+ */
+void init_isr(void)
 {
-	uint8_t mac[6] = {0x00, 0xcf, 0x54, 0x85, 0xcf, 0x01};	/* this is the original MAC address dbug assigns */
-	uint8_t bc[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; /* this is our broadcast MAC address */
-	IP_ADDR myip = {192, 168, 1, 100};
-	IP_ADDR gateway = {192, 168, 1, 1};
-	IP_ADDR netmask = {255, 255, 255, 0};
-	int vector;
-	int (*handler)(void *, void *);
-
-	handler = fec0_interrupt_handler;
-	vector = 103;
-
 	isr_init();		/* need to call that explicitely, otherwise isr table might be full */

-	if (!isr_register_handler(vector, handler, NULL, (void *) &nif1))
+	/*
+	 * register the FEC interrupt handler
+	 */
+	if (!isr_register_handler(64 + INT_SOURCE_FEC0, fec0_interrupt_handler, NULL, (void *) &nif1))
 	{
-		dbg("%s: unable to register handler for vector %d\r\n", __FUNCTION__, vector);
+		dbg("unable to register isr for FEC0\r\n");
 		return;
 	}

 	/*
 	 * Register the DMA interrupt handler
 	 */
-	handler = dma_interrupt_handler;
-	vector = 112;

-	if (!isr_register_handler(vector, handler, NULL,NULL))
+	if (!isr_register_handler(64 + INT_SOURCE_DMA, dma_interrupt_handler, NULL,NULL))
 	{
-		dbg("%s: Error: Unable to register handler for vector %s\r\n", __FUNCTION__, vector);
+		dbg("Error: Unable to register isr for DMA\r\n");
 		return;
 	}

-	nif_init(&nif1);
-	nif1.mtu = ETH_MTU;
-	nif1.send = fec0_send;
-	fec_eth_setup(0, FEC_MODE_MII, FEC_MII_100BASE_TX, FEC_MII_FULL_DUPLEX, mac);
-	// fec_eth_setup(1, FEC_MODE_MII, FEC_MII_100BASE_TX, FEC_MII_FULL_DUPLEX, mac);
-	memcpy(nif1.hwa, mac, 6);
-	memcpy(nif1.broadcast, bc, 6);
+	dma_irq_enable(5, 3);	/* TODO: need to match the FEC driver's specs in MiNT? */

-	dbg("%s: ethernet address is %02X:%02X:%02X:%02X:%02X:%02X\r\n", __FUNCTION__,
-				nif1.hwa[0], nif1.hwa[1], nif1.hwa[2],
-				nif1.hwa[3], nif1.hwa[4], nif1.hwa[5]);
-
-	timer_init(TIMER_NETWORK, TMR_INTC_LVL, TMR_INTC_PRI);
-
-	arp_init(&arp_info);
-	nif_bind_protocol(&nif1, ETH_FRM_ARP, arp_handler, (void *) &arp_info);
-
-	ip_init(&ip_info, myip, gateway, netmask);
-	nif_bind_protocol(&nif1, ETH_FRM_IP, ip_handler, (void *) &ip_info);
-
-	udp_init();
-
-	dma_irq_enable(6, 6);
-
-	set_ipl(0);
-
-	bootp_request(&nif1, 0);
-
-	fec_eth_stop(0);
+	/*
+	 * register the PIC interrupt handler
+	 */
+	if (isr_register_handler(64 + INT_SOURCE_PSC3, pic_interrupt_handler, NULL, NULL))
+	{
+		dbg("Error: unable to register ISR for PSC3\r\n");
+		return;
+	}
 }

 void BaS(void)
@@ -319,7 +290,7 @@ void BaS(void)
 	uint8_t *src;
 	uint8_t *dst = (uint8_t *) TOS;

-#if MACHINE_FIREBEE	/* LITE board has no pic and (currently) no nvram */
+#if defined(MACHINE_FIREBEE)        /* LITE board has no pic and (currently) no nvram */
 	pic_init();
 	nvram_init();
 #endif /* MACHINE_FIREBEE */
@@ -415,7 +386,7 @@ void BaS(void)
 	 */
 	memset((void *) 0x400, 0, 0x400);

-#ifdef MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
 	/* set Falcon bus control register */
 	/* sets bit 3 and 6. Both are undefined on an original Falcon? */

@@ -434,7 +405,7 @@ void BaS(void)
 	* (uint32_t *) 0x5a4 = FASTRAM_END;	/* ramtop TOS system variable */
 	* (uint32_t *) 0x5a8 = 0x1357bd13;	/* ramvalid TOS system variable */

-#ifdef MACHINE_FIREBEE /* m5484lite has no ACIA and no dip switch... */
+#if defined(MACHINE_FIREBEE) /* m5484lite has no ACIA and no dip switch... */
 	acia_init();
 #endif /* MACHINE_FIREBEE */

@@ -450,9 +421,7 @@ void BaS(void)

 	xprintf("BaS initialization finished, enable interrupts\r\n");
 	enable_coldfire_interrupts();
-
-	//set_ipl(0);
-	network_init();
+	init_isr();

 	xprintf("call EmuTOS\r\n");
 	struct rom_header *os_header = (struct rom_header *) TOS;
--- a/sys/cache.c
+++ b/sys/cache.c
@@ -32,7 +32,7 @@ void cacr_set(uint32_t value)
 	__asm__ __volatile__("movec	%0, cacr\n\t"
 						 : /* output */
 						 : "r" (rt_cacr)
-						 : /* clobbers */);
+						 : "memory" /* clobbers */);
 }

 uint32_t cacr_get(void)
@@ -42,26 +42,43 @@ uint32_t cacr_get(void)
 	return rt_cacr;
 }

+void disable_data_cache(void)
+{
+	flush_and_invalidate_caches();
+	cacr_set((cacr_get() | CF_CACR_DCINVA) & ~CF_CACR_DEC);
+}
+
+void disable_instruction_cache(void)
+{
+	flush_and_invalidate_caches();
+	cacr_set((cacr_get() | CF_CACR_ICINVA) & ~CF_CACR_IEC);
+}
+
+void enable_data_cache(void)
+{
+	cacr_set(cacr_get() & ~CF_CACR_DCINVA);
+}
+
 void flush_and_invalidate_caches(void)
 {
-    __asm__ __volatile__(
-            "	clr.l		d0                  \n\t"
-            "	clr.l		d1                  \n\t"
-            "	move.l		d0,a0               \n\t"
-            "cfa_setloop:                       \n\t"
-            "	cpushl		bc,(a0)				| flush\n\t"
-            "	lea			0x10(a0),a0			| index+1\n\t"
-            "	addq.l		#1,d1				| index+1\n\t"
-            "	cmpi.w		#512,d1				| all sets?\n\t"
-            "	bne.s		cfa_setloop			| no->\n\t"
-            "	clr.l		d1                  \n\t"
-            "	addq.l		#1,d0               \n\t"
-            "	move.l		d0,a0               \n\t"
-            "	cmpi.w		#4,d0				| all ways?\n\t"
-            "	bne.s		cfa_setloop			| no->\n\t"
-            /* input */	:
-            /* output */	:
-            /* clobber */	: "d0", "d1", "a0"
+	__asm__ __volatile__(
+			"	clr.l		d0                  \n\t"
+			"	clr.l		d1                  \n\t"
+			"	move.l		d0,a0               \n\t"
+			"cfa_setloop:                       \n\t"
+			"	cpushl		bc,(a0)				| flush\n\t"
+			"	lea			0x10(a0),a0			| index+1\n\t"
+			"	addq.l		#1,d1				| index+1\n\t"
+			"	cmpi.w		#512,d1				| all sets?\n\t"
+			"	bne.s		cfa_setloop			| no->\n\t"
+			"	clr.l		d1                  \n\t"
+			"	addq.l		#1,d0               \n\t"
+			"	move.l		d0,a0               \n\t"
+			"	cmpi.w		#4,d0				| all ways?\n\t"
+			"	bne.s		cfa_setloop			| no->\n\t"
+			/* input */	:
+			/* output */	:
+			/* clobber */	: "cc", "d0", "d1", "a0"
 	);
 }

@@ -80,36 +97,37 @@ void flush_icache_range(void *address, size_t size)

 	if (start_set > end_set) {
 		/* from the begining to the lowest address */
-		for (set = 0; set <= end_set; set += (0x10 - 3)) {
-            __asm__ __volatile__(
-                        "       cpushl  ic,(%[set])         \n\t"
-                        "       addq.l  #1,%[set]           \n\t"
-                        "       cpushl  ic,(%[set])         \n\t"
-                        "       addq.l  #1,%[set]           \n\t"
-                        "       cpushl  ic,(%[set])         \n\t"
-                        "       addq.l  #1,%[set]           \n\t"
-                        "       cpushl  ic,(%[set])         \n\t"
-                 : /* output parameters  */
-                 : [set] "a" (set)    /* input parameters */
-                 :
-            );
+        for (set = 0; set <= end_set; set += (0x10 - 3))
+        {
+			__asm__ __volatile__(
+						"       cpushl  ic,(%[set])         \n\t"
+						"       addq.l  #1,%[set]           \n\t"
+						"       cpushl  ic,(%[set])         \n\t"
+						"       addq.l  #1,%[set]           \n\t"
+						"       cpushl  ic,(%[set])         \n\t"
+						"       addq.l  #1,%[set]           \n\t"
+						"       cpushl  ic,(%[set])         \n\t"
+				 : /* output parameters  */
+				 : [set] "a" (set)  /* input parameters */
+				 : "cc"             /* clobbered registers */
+			);
 		}
 		/* next loop will finish the cache ie pass the hole */
 		end_set = LAST_ICACHE_ADDR;
 	}
 	for (set = start_set; set <= end_set; set += (0x10 - 3)) {
-        __asm__ __volatile__(
-                    "       cpushl  ic,(%[set])             \n\t"
-                    "       addq.l  #1,%[set]               \n\t"
-                    "       cpushl  ic,(%[set])             \n\t"
-                    "       addq.l  #1,%[set]               \n\t"
-                    "       cpushl  ic,(%[set])             \n\t"
-                    "       addq.l  #1,%[set]               \n\t"
-                    "       cpushl  ic,(%[set])"
-                    : /* output parameters */
-                    : [set] "a" (set)
-                    :
-         );
+		__asm__ __volatile__(
+					"       cpushl  ic,(%[set])             \n\t"
+					"       addq.l  #1,%[set]               \n\t"
+					"       cpushl  ic,(%[set])             \n\t"
+					"       addq.l  #1,%[set]               \n\t"
+					"       cpushl  ic,(%[set])             \n\t"
+					"       addq.l  #1,%[set]               \n\t"
+					"       cpushl  ic,(%[set])"
+					: /* output parameters */
+					: [set] "a" (set)
+					: "cc"
+		 );
 	}
 }

@@ -131,37 +149,91 @@ void flush_dcache_range(void *address, size_t size)

 	if (start_set > end_set) {
 		/* from the begining to the lowest address */
-        for (set = 0; set <= end_set; set += (0x10 - 3))
-        {
-            __asm__ __volatile__(
-                        "       cpushl  dc,(%[set])         \n\t"
-                        "       addq.l  #1,%[set]           \n\t"
-                        "       cpushl  dc,(%[set])         \n\t"
-                        "       addq.l  #1,%[set]           \n\t"
-                        "       cpushl  dc,(%[set])         \n\t"
-                        "       addq.l  #1,%[set]           \n\t"
-                        "       cpushl  dc,(%[set])         \n\t"
-                        : /* output parameters */
-                        : [set] "a" (set)
-                        : /* clobbered registers */
-            );
+		for (set = 0; set <= end_set; set += (0x10 - 3))
+		{
+			__asm__ __volatile__(
+						"       cpushl  dc,(%[set])         \n\t"
+						"       addq.l  #1,%[set]           \n\t"
+						"       cpushl  dc,(%[set])         \n\t"
+						"       addq.l  #1,%[set]           \n\t"
+						"       cpushl  dc,(%[set])         \n\t"
+						"       addq.l  #1,%[set]           \n\t"
+						"       cpushl  dc,(%[set])         \n\t"
+						: /* output parameters */
+						: [set] "a" (set)
+						: "cc" /* clobbered registers */
+			);
 		}
 		/* next loop will finish the cache ie pass the hole */
 		end_set = LAST_DCACHE_ADDR;
 	}
+	for (set = start_set; set <= end_set; set += (0x10 - 3))
+	{
+		__asm__ __volatile__(
+					"       cpushl      dc,(%[set])     \n\t"
+					"       addq.l      #1,%[set]       \n\t"
+					"       cpushl      dc,(%[set])     \n\t"
+					"       addq%.l     #1,%[set]       \n\t"
+					"       cpushl      dc,(%[set])     \n\t"
+					"       addq.l      #1,%[set]       \n\t"
+					"       cpushl      dc,(%[set])     \n\t"
+					: /* output parameters */
+					: [set] "a" (set)
+					: "cc" /* clobbered registers */
+		);
+	}
+}
+
+/*
+ * flush and invalidate a specific region from the both caches. We do not know if the area is cached
+ * at all, we do not know in which of the four ways it is cached, but we know the index where they
+ * would be cached if they are, so we only need to flush and invalidate only a subset of the 512 index
+ * entries, but all four ways.
+ */
+void flush_cache_range(void *address, size_t size)
+{
+    unsigned long set;
+    unsigned long start_set;
+    unsigned long end_set;
+    void *endaddr;
+
+    endaddr = address + size;
+    start_set = (uint32_t) address & _DCACHE_SET_MASK;
+    end_set = (uint32_t) endaddr & _DCACHE_SET_MASK;
+
+    if (start_set > end_set) {
+        /* from the begining to the lowest address */
+        for (set = 0; set <= end_set; set += (0x10 - 3))
+        {
+            __asm__ __volatile__(
+                        "       cpushl  bc,(%[set])         \n\t"
+                        "       addq.l  #1,%[set]           \n\t"
+                        "       cpushl  bc,(%[set])         \n\t"
+                        "       addq.l  #1,%[set]           \n\t"
+                        "       cpushl  bc,(%[set])         \n\t"
+                        "       addq.l  #1,%[set]           \n\t"
+                        "       cpushl  bc,(%[set])         \n\t"
+                        : /* output parameters */
+                        : [set] "a" (set)
+                        : "cc" /* clobbered registers */
+            );
+        }
+        /* next loop will finish the cache ie pass the hole */
+        end_set = LAST_DCACHE_ADDR;
+    }
    for (set = start_set; set <= end_set; set += (0x10 - 3))
    {
        __asm__ __volatile__(
-                    "       cpushl      dc,(%[set])     \n\t"
+                    "       cpushl      bc,(%[set])     \n\t"
                    "       addq.l      #1,%[set]       \n\t"
-                    "       cpushl      dc,(%[set])     \n\t"
+                    "       cpushl      bc,(%[set])     \n\t"
                    "       addq%.l     #1,%[set]       \n\t"
-                    "       cpushl      dc,(%[set])     \n\t"
+                    "       cpushl      bc,(%[set])     \n\t"
                    "       addq.l      #1,%[set]       \n\t"
-                    "       cpushl      dc,(%[set])     \n\t"
+                    "       cpushl      bc,(%[set])     \n\t"
                    : /* output parameters */
                    : [set] "a" (set)
-                    : /* clobbered registers */
+                    : "cc" /* clobbered registers */
        );
-	}
+    }
 }
--- a/sys/driver_mem.c
+++ b/sys/driver_mem.c
@@ -2,7 +2,7 @@
 *	driver_mem.c
 *
 * based from Emutos / BDOS
- * 
+ *
 * Copyright (c) 2001 Lineo, Inc.
 *
 * Authors: Karl T. Braun, Martin Doering, Laurent Vogel
@@ -11,8 +11,7 @@
 * option any later version.
 */

-#include <stdint.h>
-#include <stdbool.h>
+#include <bas_types.h>
 #include "bas_string.h"
 #include "bas_printf.h"
 #include "usb.h"
@@ -28,8 +27,7 @@
 #error "unknown machine!"
 #endif

-//#define DBG_DM
-
+#define DBG_DM
 #ifdef	DBG_DM
 #define	dbg(fmt, args...)	xprintf(fmt, ##args)
 #else
@@ -71,7 +69,7 @@ static MPB pmd;
 static void *xmgetblk(void)
 {
 	int i;
-	
+
 	for (i = 0; i < MAXMD; i++)
 	{
 		if (tab_md[i].m_own == NULL)
@@ -79,7 +77,7 @@ static void *xmgetblk(void)
 			tab_md[i].m_own = (void*)1L;
 			return(&tab_md[i]);
 		}
-	}			   
+	}
 	return NULL;
 }

@@ -97,18 +95,18 @@ static MD *ffit(long amount, MPB *mp)
 	MD *p, *q, *p1;                    /* free list is composed of MD's */
 	int maxflg;
 	long maxval;
-	
+
 	if (amount != -1)
 	{
 		amount += 15;                  /* 16 bytes alignment */
 		amount &= 0xFFFFFFF0;
 	}
-	
+
 	if ((q = mp->mp_rover) == 0)      /* get rotating pointer */
 	{
 		return 0;
 	}
-	
+
 	maxval = 0;
 	maxflg = ((amount == -1) ? true : false) ;
 	p = q->m_link;                   /* start with next MD */
@@ -138,7 +136,7 @@ static MD *ffit(long amount, MPB *mp)
 				{
 					return(NULL);
 				}
-				
+
 				/* init new MD */
 				p1->m_length = p->m_length - amount;
 				p1->m_start = p->m_start + amount;
@@ -147,7 +145,7 @@ static MD *ffit(long amount, MPB *mp)
 				q->m_link = p1;
 			}
 			/* link allocate block into allocated list,
-			    mark owner of block, & adjust rover  */
+				mark owner of block, & adjust rover  */
 			p->m_link = mp->mp_mal;
 			mp->mp_mal = p;
 			mp->mp_rover = (q == (MD *) &mp->mp_mfl ? q->m_link : q);
@@ -157,7 +155,7 @@ static MD *ffit(long amount, MPB *mp)
 			maxval = p->m_length;
 		p = ( q=p )->m_link;
 	} while(q != mp->mp_rover);
-	
+
 	/*
 	 * return either the max, or 0 (error)
 	 */
@@ -179,7 +177,7 @@ static MD *ffit(long amount, MPB *mp)
 static void freeit(MD *m, MPB *mp)
 {
 	MD *p, *q;
-	
+
 	q = 0;
 	for (p = mp->mp_mfl; p ; p = (q = p) -> m_link)
 	{
@@ -189,7 +187,7 @@ static void freeit(MD *m, MPB *mp)
 		}
 	}
 	m->m_link = p;
-	
+
 	if (q)
 	{
 		q->m_link = m;
@@ -198,12 +196,12 @@ static void freeit(MD *m, MPB *mp)
 	{
 		mp->mp_mfl = m;
 	}
-	
+
 	if (!mp->mp_rover)
 	{
 		mp->mp_rover = m;
 	}
-	
+
 	if (p)
 	{
 		if (m->m_start + m->m_length == p->m_start)
@@ -241,7 +239,7 @@ int32_t driver_mem_free(void *addr)
 	MPB *mpb;
 	mpb = &pmd;
 	level = set_ipl(7);
-	
+
 	for(p = *(q = &mpb->mp_mal); p; p = *(q = &p->m_link))
 	{
 		if ((long) addr == p->m_start)
@@ -249,19 +247,19 @@ int32_t driver_mem_free(void *addr)
 			break;
 		}
 	}
-	
+
 	if (!p)
 	{
 		set_ipl(level);
 		return(-1);
 	}
-	
+
 	*q = p->m_link;
 	freeit(p, mpb);
 	set_ipl(level);
-	
+
 	dbg("%s: driver_mem_free(0x%08X)\r\n", __FUNCTION__, addr);
-	
+
 	return(0);
 }

@@ -270,33 +268,33 @@ void *driver_mem_alloc(uint32_t amount)
 	void *ret = NULL;
 	int level;
 	MD *m;
-	
+
 	if (amount == -1L)
 	{
-		return((void *)ffit(-1L, &pmd));
+		return (void *) ffit(-1L, &pmd);
 	}
-	
+
 	if (amount <= 0 )
 	{
 		return(0);
 	}
-	
+
 	if ((amount & 1))
 	{
 		amount++;
 	}
-	
+
 	level = set_ipl(7);
 	m = ffit(amount, &pmd);
-	
+
 	if (m != NULL)
 	{
-		ret = (void *)m->m_start;
+		ret = (void *) m->m_start;
 	}
 	set_ipl(level);
 	dbg("%s: driver_mem_alloc(%d) = 0x%08X\r\n", __FUNCTION__, amount, ret);
-	
-	return(ret);
+
+	return ret;
 }

 static int use_count = 0;
@@ -307,11 +305,11 @@ int driver_mem_init(void)
 	{
 		dbg("%s: initialise driver_mem_buffer[] at %p, size 0x%x\r\n", __FUNCTION__, driver_mem_buffer, DRIVER_MEM_BUFFER_SIZE);
 		memset(driver_mem_buffer, 0, DRIVER_MEM_BUFFER_SIZE);
-	
+
 		pmd.mp_mfl = pmd.mp_rover = &tab_md[0];
 		tab_md[0].m_link = (MD *) NULL;
 		tab_md[0].m_start = ((long) driver_mem_buffer + 15) & ~15;
-		tab_md[0].m_length = DRIVER_MEM_BUFFER_SIZE;	
+		tab_md[0].m_length = DRIVER_MEM_BUFFER_SIZE;
 		tab_md[0].m_own = (void *) 1L;
 		pmd.mp_mal = (MD *) NULL;
 		memset(driver_mem_buffer, 0, tab_md[0].m_length);
@@ -320,7 +318,8 @@ int driver_mem_init(void)
 	}
 	use_count++;
 	dbg("%s: driver_mem now has a use count of %d\r\n", __FUNCTION__, use_count);
-	return(0);
+
+	return 0;
 }

 void driver_mem_release(void)
--- a/sys/exceptions.S
+++ b/sys/exceptions.S
--- a/sys/fault_vectors.c
+++ b/sys/fault_vectors.c
@@ -192,7 +192,11 @@ void setup_vectors(void)
 	__asm__ __volatile__("clr.l		d0\n\t"\
 						 "movec.l	d0,VBR\n\t"\
 						 "nop\n\t"\
-						 "move.l	d0,_rt_vbr" ::: "d0", "memory");
+                         "move.l	d0,_rt_vbr"
+                         :                      /* outputs */
+                         :                      /* inputs */
+                         : "d0", "memory", "cc" /* clobbered registers */
+                        );

 	xprintf("finished.\r\n");
 }
--- a/sys/init_fpga.c
+++ b/sys/init_fpga.c
@@ -27,16 +27,31 @@
 #include "bas_printf.h"
 #include "wait.h"

+// #define FPGA_DEBUG
+#if defined(FPGA_DEBUG)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
+#else
+#define dbg(format, arg...) do { ; } while (0)
+#endif
+
 #define FPGA_STATUS		(1 << 0)
 #define FPGA_CLOCK		(1 << 1)
 #define FPGA_CONFIG		(1 << 2)
 #define FPGA_DATA0		(1 << 3)
 #define FPGA_CONF_DONE	(1 << 5)

-extern uint8_t _FPGA_FLASH_DATA[];
-#define FPGA_FLASH_DATA	&_FPGA_FLASH_DATA[0]
-extern uint8_t _FPGA_FLASH_DATA_SIZE[];
-#define FPGA_FLASH_DATA_SIZE	((uint32_t) &_FPGA_FLASH_DATA_SIZE[0])
+extern uint8_t _FPGA_CONFIG[];
+#define FPGA_FLASH_DATA	&_FPGA_CONFIG[0]
+extern uint8_t _FPGA_CONFIG_SIZE[];
+#define FPGA_FLASH_DATA_SIZE	((uint32_t) &_FPGA_CONFIG_SIZE[0])
+
+/*
+ * flag located in processor SRAM1 that indicates that the FPGA configuration has
+ * been loaded through JTAG. init_fpga() will honour this and not overwrite config.
+ */
+extern bool _FPGA_JTAG_LOADED;
+extern long _FPGA_JTAG_VALID;
+#define VALID_JTAG		0xaffeaffe

 void config_gpio_for_fpga_config(void)
 {
@@ -64,7 +79,7 @@ void config_gpio_for_jtag_config(void)
 						  MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4;	/* bit 4 = LED => output */
 															/* all other bits = input */
 	/*
-	 * unfortunately, the GPIO module cannot trigger interrupts. That means FPGA_CONFIG needs to be polled to detect
+	 * unfortunately, the GPIO module cannot trigger interrupts. That means CONF_DONE needs to be polled to detect
 	 * external FPGA (re)configuration and reset the system in that case. Could be done from the OS as well...
 	 */
 }
@@ -78,7 +93,15 @@ bool init_fpga(void)
 	volatile int32_t time, start, end;
 	int i;

-	xprintf("FPGA load config... ");
+	dbg("FPGA load config\r\n(_FPGA_JTAG_LOADED = %x, _FPGA_JTAG_VALID = %x)...\r\n", _FPGA_JTAG_LOADED, _FPGA_JTAG_VALID);
+	if (_FPGA_JTAG_LOADED == true && _FPGA_JTAG_VALID == VALID_JTAG)
+	{
+		dbg("detected _FPGA_JTAG_LOADED flag. Not overwriting FPGA config.\r\n");
+
+		/* reset the flag so that next boot will load config again from flash */
+		_FPGA_JTAG_LOADED = 0;
+		return true;
+	}
 	start = MCF_SLT0_SCNT;

 	config_gpio_for_fpga_config();
--- a/sys/interrupts.c
+++ b/sys/interrupts.c
@@ -3,6 +3,7 @@
 *
 * Handle interrupts, the levels.
 *
+ *
 * This file is part of BaS_gcc.
 *
 * BaS_gcc is free software: you can redistribute it and/or modify
@@ -22,17 +23,18 @@
 *      Author: Markus Fröschle
 */

-#include <stdint.h>
-#include <stdbool.h>
+#include <bas_types.h>
 #include "MCF5475.h"
 #include "bas_utils.h"
 #include "bas_printf.h"
+#include "bas_string.h"
 #include "exceptions.h"
 #include "interrupts.h"
 #include "bas_printf.h"
 #include "startcf.h"
 #include "cache.h"
 #include "util.h"
+#include "dma.h"

 extern void (*rt_vbr[])(void);
 #define VBR	rt_vbr
@@ -96,41 +98,34 @@ int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority,
 #endif


-typedef struct
+struct isrentry
 {
 	int     vector;
 	int     (*handler)(void *, void *);
 	void    *hdev;
 	void    *harg;
-} ISRENTRY;
-
-ISRENTRY isrtab[MAX_ISR_ENTRY];
+};

+static struct isrentry isrtab[MAX_ISR_ENTRY];      /* list of interrupt service routines */

+/*
+ * clear the table of interrupt service handlers
+ */
 void isr_init(void)
 {
-	int index;
-
-	for (index = 0; index < MAX_ISR_ENTRY; index++)
-	{
-		isrtab[index].vector = 0;
-		isrtab[index].handler = 0;
-		isrtab[index].hdev = 0;
-		isrtab[index].harg = 0;
-	}
+	memset(isrtab, 0, sizeof(isrtab));
 }

-
+/*
+ * This function places an interrupt handler in the ISR table,
+ * thereby registering it so that the low-level handler may call it.
+ *
+ * The two parameters are intended for the first arg to be a
+ * pointer to the device itself, and the second a pointer to a data
+ * structure used by the device driver for that particular device.
+ */
 int isr_register_handler(int vector, int (*handler)(void *, void *), void *hdev, void *harg)
 {
-	/*
-	 * This function places an interrupt handler in the ISR table,
-	 * thereby registering it so that the low-level handler may call it.
-	 *
-	 * The two parameters are intended for the first arg to be a
-	 * pointer to the device itself, and the second a pointer to a data
-	 * structure used by the device driver for that particular device.
-	 */
 	int index;

 	if ((vector == 0) || (handler == NULL))
@@ -175,10 +170,7 @@ void isr_remove_handler(int (*handler)(void *, void *))
 	{
 		if (isrtab[index].handler == handler)
 		{
-			isrtab[index].vector = 0;
-			isrtab[index].handler = 0;
-			isrtab[index].hdev = 0;
-			isrtab[index].harg = 0;
+			memset(&isrtab[index], 0, sizeof(struct isrentry));

 			return;
 		}
@@ -186,13 +178,12 @@ void isr_remove_handler(int (*handler)(void *, void *))
 	dbg("no such handler registered (handler=%p\r\n", handler);
 }

-
+/*
+ * This routine searches the ISR table for an entry that matches
+ * 'vector'.  If one is found, then 'handler' is executed.
+ */
 bool isr_execute_handler(int vector)
 {
-	/*
-	 * This routine searches the ISR table for an entry that matches
-	 * 'vector'.  If one is found, then 'handler' is executed.
-	 */
 	int index;
 	bool retval = false;

@@ -218,19 +209,22 @@ bool isr_execute_handler(int vector)

 /*
 * PIC interrupt handler for Firebee
+ *
+ * Handles PIC requests that come in from PSC3 serial interface. Currently, that
+ * is RTC/NVRAM requests only
 */
-void pic_interrupt_handler(void)
+int pic_interrupt_handler(void *arg1, void *arg2)
 {
 	uint8_t rcv_byte;

 	rcv_byte = MCF_PSC3_PSCRB_8BIT;
 	if (rcv_byte == 2)	// PIC requests RTC data
 	{
-		uint8_t *rtc_reg= (uint8_t *) 0xffff8961;
+		uint8_t *rtc_reg = (uint8_t *) 0xffff8961;
 		uint8_t *rtc_data = (uint8_t *) 0xffff8963;
 		int index = 0;

-		xprintf("PIC interrupt requesting RTC data\r\n");
+		xprintf("PIC interrupt: requesting RTC data\r\n");

 		MCF_PSC3_PSCTB_8BIT = 0x82;		// header byte to PIC
 		do
@@ -239,6 +233,7 @@ void pic_interrupt_handler(void)
 			MCF_PSC3_PSCTB_8BIT = *rtc_data;
 		} while (index++ < 64);
 	}
+	return 1;
 }

 extern int32_t video_sbt;
@@ -410,3 +405,137 @@ bool irq6_interrupt_handler(uint32_t sf1, uint32_t sf2)

 	return handled;
 }
+
+#if defined(MACHINE_FIREBEE)
+#define vbasehi		(* (volatile uint8_t *) 0xffff8201)
+#define vbasemid	(* (volatile uint8_t *) 0xffff8203)
+#define vbaselow	(* (volatile uint8_t *) 0xffff820d)
+
+#define vwrap		(* (volatile uint16_t *) 0xffff8210)
+#define vde			(* (volatile uint16_t *) 0xffff82aa)
+#define vdb			(* (volatile uint16_t *) 0xffff82a8)
+/*
+ * this is the higlevel interrupt service routine for gpt0 timer interrupts.
+ *
+ * It is called from handler_gpt0 in exceptions.S
+ *
+ * The gpt0 timer is not used as a timer, but as interrupt trigger by the FPGA which fires
+ * everytime the video base address high byte (0xffff8201) gets written by user code (i.e.
+ * everytime the video base address is set).
+ * The interrupt service routine checks if that page was already set as a video page (in that
+ * case it does nothing), if not (if we have a newly set page), it sets up an MMU mapping for
+ * that page (effectively rerouting any further access to Falcon video RAM to Firebee FPGA
+ * video RAM starting at 0x60000000) and copies SDRAM contents of that page to the video
+ * RAM page.
+ */
+void gpt0_interrupt_handler(void)
+{
+	uint32_t video_address;
+	uint32_t video_end_address;
+	int page_number;
+	bool already_set;
+	extern uint32_t _STRAM_END;
+
+	dbg("screen base = 0x%x\r\n", vbasehi);
+
+	if (vbasehi < 2)			/* screen base lower than 0x20000? */
+	{
+		goto rearm_trigger;		/* do nothing */
+	}
+	else if (vbasehi >= 0xd0)	/* higher than 0xd00000 (normal Falcon address)? */
+	{
+		video_sbt = MCF_SLT0_SCNT;	/* FIXME: no idea why we need to save the time here */
+	}
+	video_address = (vbasehi << 16) | (vbasemid << 8) | vbaselow;
+
+	page_number = video_address >> 20;				/* calculate a page number */
+	already_set = (video_tlb & (1 << page_number));	/* already in bitset? */
+	video_tlb |= page_number;						/* set it */
+
+	if (! already_set)	/* newly set page, need to copy contents */
+	{
+		flush_and_invalidate_caches();
+		dma_memcpy((uint8_t *) video_address + 0x60000000, (uint8_t *) video_address, 0x100000);
+
+		/*
+		 * create an MMU TLB entry for the new video page
+		 */
+
+		/*
+		 * first search for an existing entry with our address. If none is found,
+		 * the MMU will propose a new one
+		 */
+		MCF_MMU_MMUAR = video_address;
+		MCF_MMU_MMUOR = 0x106;
+		NOP();
+
+		/*
+		 * take this MMU TLB entry and set it to our video address and page mapping
+		 */
+		MCF_MMU_MMUAR = (MCF_MMU_MMUOR >> 16) & 0xffff;	/* set TLB id */
+
+		MCF_MMU_MMUTR = video_address |
+						MCF_MMU_MMUTR_ID(sca_page_ID) |	/* set video page ID */
+						MCF_MMU_MMUTR_SG |				/* shared global */
+						MCF_MMU_MMUTR_V;				/* valid */
+		MCF_MMU_MMUDR = (video_address + 0x60000000) |	/* physical address */
+						MCF_MMU_MMUDR_SZ(0) |			/* 1 MB page size */
+						MCF_MMU_MMUDR_CM(0) |			/* writethrough */
+						MCF_MMU_MMUDR_R |				/* readable */
+						MCF_MMU_MMUDR_W |				/* writeable */
+						MCF_MMU_MMUDR_X;				/* executable */
+		MCF_MMU_MMUOR = 0x10b;							/* update TLB entry */
+	}
+
+	/*
+	 * Calculate the effective screen memory size to see if we need to map another page
+	 * in case the new screen spans more than one single page
+	 */
+	video_end_address = video_address + (vde - vdb) * vwrap;
+	if (video_end_address < _STRAM_END)
+	{
+		page_number = video_end_address >> 20;			/* calculate a page number */
+		already_set = (video_tlb & (1 << page_number));	/* already in bitset? */
+		video_tlb |= page_number;						/* set it */
+
+		if (! already_set)	/* newly set page, need to copy contents */
+		{
+			flush_and_invalidate_caches();
+			dma_memcpy((uint8_t *) video_end_address + 0x60000000, (uint8_t *) video_end_address, 0x100000);
+
+			/*
+			 * create an MMU TLB entry for the new video page
+			 */
+
+			/*
+			 * first search for an existing entry with our address. If none is found,
+			 * the MMU will propose a new one
+			 */
+			MCF_MMU_MMUAR = video_end_address;
+			MCF_MMU_MMUOR = 0x106;
+			NOP();
+
+			/*
+			 * take this MMU TLB entry and set it to our video address and page mapping
+			 */
+			MCF_MMU_MMUAR = (MCF_MMU_MMUOR >> 16) & 0xffff;	/* set TLB id */
+
+			MCF_MMU_MMUTR = video_end_address |
+							MCF_MMU_MMUTR_ID(sca_page_ID) |	/* set video page ID */
+							MCF_MMU_MMUTR_SG |				/* shared global */
+							MCF_MMU_MMUTR_V;				/* valid */
+			MCF_MMU_MMUDR = (video_end_address + 0x60000000) |	/* physical address */
+							MCF_MMU_MMUDR_SZ(0) |			/* 1 MB page size */
+							MCF_MMU_MMUDR_CM(0) |			/* writethrough */
+							MCF_MMU_MMUDR_R |				/* readable */
+							MCF_MMU_MMUDR_W |				/* writeable */
+							MCF_MMU_MMUDR_X;				/* executable */
+			MCF_MMU_MMUOR = 0x10b;							/* update TLB entry */
+		}
+	}
+rearm_trigger:
+	MCF_GPT0_GMS &= ~1;		/* rearm trigger */
+	NOP();
+	MCF_GPT0_GMS |= 1;
+}
+#endif /* MACHINE_FIREBEE */
--- a/sys/mmu.c
+++ b/sys/mmu.c
@@ -62,9 +62,9 @@
 #error "unknown machine!"
 #endif /* MACHINE_FIREBEE */

-//#define DEBUG_MMU
+// #define DEBUG_MMU
 #ifdef DEBUG_MMU
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg);} while(0)
+#define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0)
 #else
 #define dbg(format, arg...) do {;} while (0)
 #endif /* DEBUG_MMU */
@@ -189,8 +189,79 @@ inline uint32_t set_mmubar(uint32_t value)
 	return ret;
 }

+/*
+ * map a page of memory using virt and phys as addresses with the Coldfire MMU.
+ *
+ * Theory of operation: the Coldfire MMU in the Firebee has 64 TLB entries, 32 for data (DTLB), 32 for
+ * instructions (ITLB). Mappings can either be done locked (normal MMU TLB misses will not consider them
+ * for replacement) or unlocked (mappings will reallocate using a LRU scheme when the MMU runs out of
+ * TLB entries). For proper operation, the MMU needs at least two ITLBs and/or four free/allocatable DTLBs
+ * per instruction as a minimum, more for performance. Thus locked pages (that can't be touched by the
+ * LRU algorithm) should be used sparsingly.
+ *
+ *
+ */
+int mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, const struct mmu_map_flags *flags)
+{
+	int size_mask;
+
+	switch (sz)
+	{
+		case MMU_PAGE_SIZE_1M:
+			size_mask = 0xfff00000;
+			break;
+
+		case MMU_PAGE_SIZE_8K:
+			size_mask = 0xffffe000;
+			break;
+
+		case MMU_PAGE_SIZE_4K:
+			size_mask = 0xfffff000;
+			break;
+
+		case MMU_PAGE_SIZE_1K:
+			size_mask = 0xfffff800;
+			break;
+
+		default:
+			dbg("illegal map size %d\r\n", sz);
+			return 0;
+	}
+
+	/*
+	 * add page to TLB
+	 */
+	MCF_MMU_MMUTR = ((int) virt & size_mask) |						/* virtual address */
+		MCF_MMU_MMUTR_ID(flags->page_id) |							/* address space id (ASID) */
+		MCF_MMU_MMUTR_SG |											/* shared global */
+		MCF_MMU_MMUTR_V;											/* valid */
+	NOP();
+
+	MCF_MMU_MMUDR = ((int) phys & size_mask) |						/* physical address */
+		MCF_MMU_MMUDR_SZ(sz) |										/* page size */
+		MCF_MMU_MMUDR_CM(flags->cache_mode) |
+		(flags->access & ACCESS_READ ? MCF_MMU_MMUDR_R : 0) |		/* read access enable */
+		(flags->access & ACCESS_WRITE ? MCF_MMU_MMUDR_W : 0) |		/* write access enable */
+		(flags->access & ACCESS_EXECUTE ? MCF_MMU_MMUDR_X : 0) |		/* execute access enable */
+		(flags->locked ? MCF_MMU_MMUDR_LK : 0);
+	NOP();
+
+	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
+		MCF_MMU_MMUOR_UAA;					/* update allocation address field */
+	NOP();
+
+	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
+		MCF_MMU_MMUOR_ACC |     			/* access TLB */
+		MCF_MMU_MMUOR_UAA;      			/* update allocation address field */
+	dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt, phys);
+
+	return 1;
+}
+
 void mmu_init(void)
 {
+	struct mmu_map_flags flags;
+
 	extern uint8_t _MMUBAR[];
 	uint32_t MMUBAR = (uint32_t) &_MMUBAR[0];
 	extern uint8_t _TOS[];
@@ -206,8 +277,8 @@ void mmu_init(void)
 			ACR_S(ACR_S_ALL) |						/* match addresses in user and supervisor mode */
 			ACR_E(1) |								/* enable ACR */
 #if defined(MACHINE_FIREBEE)
-			ACR_ADMSK(0x3f) |						/* cover 1GB area from 0xc0000000 to 0xffffffff */
-			ACR_BA(0xc0000000));					/* (equals area from 3 to 4 GB */
+			ACR_ADMSK(0x7f) |						/* cover 2GB area from 0x80000000 to 0xffffffff */
+			ACR_BA(0x80000000));					/* (equals area from 3 to 4 GB */
 #elif defined(MACHINE_M5484LITE)
 			ACR_ADMSK(0x7f) |						/* cover 2 GB area from 0x80000000 to 0xffffffff */
 			ACR_BA(0x80000000));
@@ -260,62 +331,28 @@ void mmu_init(void)

 	/* create locked TLB entries */

-	/*
-	 * 0x0000'0000 - 0x000F'FFFF (first MB of physical memory) locked virtual = physical
-	 */
-	MCF_MMU_MMUTR = 0x0 | 					/* virtual address */
-					MCF_MMU_MMUTR_SG |		/* shared global */
-					MCF_MMU_MMUTR_V;		/* valid */
-	MCF_MMU_MMUDR = 0x0 |					/* physical address */
-					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
-					MCF_MMU_MMUDR_CM(0x1) |	/* cacheable, copyback */
-					MCF_MMU_MMUDR_R |		/* read access enable */
-					MCF_MMU_MMUDR_W |		/* write access enable */
-					MCF_MMU_MMUDR_X | 		/* execute access enable */
-					MCF_MMU_MMUDR_LK;		/* lock entry */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
-					MCF_MMU_MMUOR_UAA;		/* update allocation address field */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
-					MCF_MMU_MMUOR_ACC |     /* access TLB */
-					MCF_MMU_MMUOR_UAA;      /* update allocation address field */
+	flags.cache_mode = CACHE_COPYBACK;
+	flags.protection = SV_USER;
+	flags.page_id = 0;
+	flags.access = ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE;
+	flags.locked = true;

+	/* 0x0000_0000 - 0x000F_FFFF (first MB of physical memory) locked virt = phys */
+	mmu_map_page(0x0, 0x0, MMU_PAGE_SIZE_1M, &flags);
+
+#if defined(MACHINE_FIREBEE)
 	/*
 	 * 0x00d0'0000 - 0x00df'ffff (last megabyte of ST RAM = Falcon video memory) locked ID = 6
 	 * mapped to physical address 0x60d0'0000 (FPGA video memory)
 	 * video RAM: read write execute normal write true
 	 */
+	flags.cache_mode = CACHE_WRITETHROUGH;
+    flags.protection = SV_USER;
+	flags.page_id = SCA_PAGE_ID;
+    flags.access = ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE;
+    flags.locked = true;
+	mmu_map_page(0x00d00000, 0x60d00000, MMU_PAGE_SIZE_1M, &flags);

-	MCF_MMU_MMUTR = 0x00d00000 |			/* virtual address */
-#if defined(MACHINE_FIREBEE)
-					MCF_MMU_MMUTR_ID(SCA_PAGE_ID) |
-#endif /* MACHINE_FIREBEE */
-					MCF_MMU_MMUTR_SG |		/* shared global */
-					MCF_MMU_MMUTR_V;		/* valid */
-#if defined(MACHINE_FIREBEE)
-					/* map FPGA video memory for FireBee only */
-	MCF_MMU_MMUDR = 0x60d00000 |			/* physical address */
-#elif defined(MACHINE_M5484LITE)
-	MCF_MMU_MMUDR = 0x00d00000 |			/* physical address */
-#elif defined(MACHINE_M54455)
-	MCF_MMU_MMUDR = 0x60d00000 |			/* FIXME: not determined yet */
-#else
-#error unknown machine!
-#endif /* MACHINE_FIREBEE */
-					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
-					MCF_MMU_MMUDR_CM(0x0) |	/* cachable writethrough */
-					/* caveat: can't be supervisor protected since TOS puts the application stack there! */
-					//MCF_MMU_MMUDR_SP |		/* supervisor protect */
-					MCF_MMU_MMUDR_R |		/* read access enable */
-					MCF_MMU_MMUDR_W |		/* write access enable */
-					MCF_MMU_MMUDR_X |		/* execute access enable */
-					MCF_MMU_MMUDR_LK;		/* lock entry */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
-					MCF_MMU_MMUOR_UAA;		/* update allocation address field */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
-					MCF_MMU_MMUOR_ACC |     /* access TLB */
-					MCF_MMU_MMUOR_UAA;      /* update allocation address field */
-
-#if defined(MACHINE_FIREBEE)
 	video_tlb = 0x2000;						/* set page as video page */
 	video_sbt = 0x0;						/* clear time */
 #endif /* MACHINE_FIREBEE */
@@ -324,95 +361,52 @@ void mmu_init(void)
 	 * Make the TOS (in SDRAM) read-only
 	 * This maps virtual 0x00e0'0000 - 0x00ef'ffff to the same virtual address
 	 */
-	MCF_MMU_MMUTR = TOS |					/* virtual address */
-					MCF_MMU_MMUTR_SG |		/* shared global */
-					MCF_MMU_MMUTR_V;		/* valid */
-	MCF_MMU_MMUDR = TOS |					/* physical address */
-					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
-					MCF_MMU_MMUDR_CM(0x1) |	/* cachable copyback */
-					MCF_MMU_MMUDR_R |		/* read access enable */
-					//MCF_MMU_MMUDR_W |		/* write access enable (FIXME: for now) */
-					MCF_MMU_MMUDR_X |		/* execute access enable */
-					MCF_MMU_MMUDR_LK;		/* lock entry */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
-					MCF_MMU_MMUOR_UAA;		/* update allocation address field */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
-					MCF_MMU_MMUOR_ACC |     /* access TLB */
-					MCF_MMU_MMUOR_UAA;      /* update allocation address field */
+	flags.cache_mode = CACHE_COPYBACK;
+	flags.page_id = 0;
+	flags.access = ACCESS_READ | ACCESS_EXECUTE;
+	mmu_map_page(TOS, TOS, MMU_PAGE_SIZE_1M, &flags);

-#if MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
 	/*
 	 * Map FireBee I/O area (0xfff0'0000 - 0xffff'ffff physical) to the Falcon-compatible I/O
 	 * area (0x00f0'0000 - 0x00ff'ffff virtual) for the FireBee
 	 */
-
-	MCF_MMU_MMUTR = 0x00f00000 |			/* virtual address */
-					MCF_MMU_MMUTR_SG |		/* shared global */
-					MCF_MMU_MMUTR_V;		/* valid */
-	MCF_MMU_MMUDR = 0xfff00000 |			/* physical address */
-					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
-					MCF_MMU_MMUDR_CM(0x2) |	/* nocache precise */
-					MCF_MMU_MMUDR_SP |		/* supervisor protect */
-					MCF_MMU_MMUDR_R |		/* read access enable */
-					MCF_MMU_MMUDR_W |		/* write access enable */
-					MCF_MMU_MMUDR_X |		/* execute access enable */
-					MCF_MMU_MMUDR_LK;		/* lock entry */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
-					MCF_MMU_MMUOR_UAA;		/* update allocation address field */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
-					MCF_MMU_MMUOR_ACC |     /* access TLB */
-					MCF_MMU_MMUOR_UAA;      /* update allocation address field */
+	flags.cache_mode = CACHE_NOCACHE_PRECISE;
+	flags.access = ACCESS_WRITE | ACCESS_READ;
+	mmu_map_page(0x00f00000, 0xfff00000, MMU_PAGE_SIZE_1M, &flags);
 #endif /* MACHINE_FIREBEE */

 	/*
 	 * Map (locked) the second last MB of physical SDRAM (this is where BaS .data and .bss reside) to the same
-	 * virtual address. This is also used when BaS is in RAM
+	 * virtual address. This is also used (completely) when BaS is in RAM
 	 */
-
-	MCF_MMU_MMUTR = (SDRAM_START + SDRAM_SIZE - 0x00200000) |	/* virtual address */
-					MCF_MMU_MMUTR_SG |		/* shared global */
-					MCF_MMU_MMUTR_V;		/* valid */
-	MCF_MMU_MMUDR = (SDRAM_START + SDRAM_SIZE - 0x00200000) |	/* physical address */
-					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
-					MCF_MMU_MMUDR_CM(0x0) |	/* cacheable writethrough */
-					MCF_MMU_MMUDR_SP |		/* supervisor protect */
-					MCF_MMU_MMUDR_R |		/* read access enable */
-					MCF_MMU_MMUDR_W |		/* write access enable */
-					MCF_MMU_MMUDR_X |		/* execute access enable */
-					MCF_MMU_MMUDR_LK;		/* lock entry */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
-					MCF_MMU_MMUOR_UAA;		/* update allocation address field */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
-					MCF_MMU_MMUOR_ACC |     /* access TLB */
-					MCF_MMU_MMUOR_UAA;      /* update allocation address field */
+	flags.cache_mode = CACHE_COPYBACK;
+	flags.access = ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE;
+	mmu_map_page(SDRAM_START + SDRAM_SIZE - 0X00200000, SDRAM_START + SDRAM_SIZE - 0X00200000, MMU_PAGE_SIZE_1M, &flags);

 	/*
 	 * Map (locked) the very last MB of physical SDRAM (this is where the driver buffers reside) to the same
 	 * virtual address. Used uncached for drivers.
 	 */
-
-	MCF_MMU_MMUTR = (SDRAM_START + SDRAM_SIZE - 0x00100000) |	/* virtual address */
-					MCF_MMU_MMUTR_SG |		/* shared global */
-					MCF_MMU_MMUTR_V;		/* valid */
-	MCF_MMU_MMUDR = (SDRAM_START + SDRAM_SIZE - 0x00100000) |	/* physical address */
-					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
-					MCF_MMU_MMUDR_CM(0x2) |	/* nocache precise */
-					MCF_MMU_MMUDR_SP |		/* supervisor protect */
-					MCF_MMU_MMUDR_R |		/* read access enable */
-					MCF_MMU_MMUDR_W |		/* write access enable */
-					//MCF_MMU_MMUDR_X |		/* execute access enable */
-					MCF_MMU_MMUDR_LK;		/* lock entry */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
-					MCF_MMU_MMUOR_UAA;		/* update allocation address field */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
-					MCF_MMU_MMUOR_ACC |     /* access TLB */
-					MCF_MMU_MMUOR_UAA;      /* update allocation address field */
+	flags.cache_mode = CACHE_NOCACHE_PRECISE;
+	flags.access = ACCESS_READ | ACCESS_WRITE;
+	flags.protection = SV_PROTECT;
+	mmu_map_page(SDRAM_START + SDRAM_SIZE - 0x00100000, SDRAM_START + SDRAM_SIZE - 0x00100000, MMU_PAGE_SIZE_1M, &flags);
 }

-void mmutr_miss(uint32_t address)
+static struct mmu_map_flags flags =
 {
-	dbg("MMU TLB MISS at 0x%08x\r\n", address);
-	flush_and_invalidate_caches();
+	.cache_mode = CACHE_COPYBACK,
+	.protection = SV_USER,
+	.page_id = 0,
+	.access = ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE,
+	.locked = false
+};
+
+void mmutr_miss(uint32_t address, uint32_t pc, uint32_t format_status)
+{
+	dbg("MMU TLB MISS accessing 0x%08x\r\nFS = 0x%08x\r\nPC = 0x%08x\r\n", address, format_status, pc);
+	// flush_and_invalidate_caches();

 	switch (address)
 	{
@@ -430,23 +424,9 @@ void mmutr_miss(uint32_t address)

 		default:
 			/* add missed page to TLB */
-			MCF_MMU_MMUTR = (address & 0xfff00000) | /* virtual aligned to 1M */
-							MCF_MMU_MMUTR_SG |		/* shared global */
-							MCF_MMU_MMUTR_V;		/* valid */
-
-			MCF_MMU_MMUDR = (address & 0xfff00000) |	/* physical aligned to 1M */
-							MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
-							MCF_MMU_MMUDR_CM(0x1) |	/* cacheable copyback */
-							MCF_MMU_MMUDR_R |		/* read access enable */
-							MCF_MMU_MMUDR_W |		/* write access enable */
-							MCF_MMU_MMUDR_X;		/* execute access enable */
-
-			MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
-							MCF_MMU_MMUOR_UAA;		/* update allocation address field */
-
-			MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
-							MCF_MMU_MMUOR_ACC |     /* access TLB */
-							MCF_MMU_MMUOR_UAA;      /* update allocation address field */
+			mmu_map_page(address, address, MMU_PAGE_SIZE_1M, &flags);
+			dbg("DTLB: MCF_MMU_MMUOR = %08x\r\n", MCF_MMU_MMUOR);
+			dbg("ITLB: MCF_MMU_MMUOR = %08x\r\n\r\n", MCF_MMU_MMUOR);
 	}
 }

--- a/sys/sysinit.c
+++ b/sys/sysinit.c
@@ -55,6 +55,13 @@
 #include "usb.h"
 #include "video.h"

+// #define DEBUG_SYSINIT
+#ifdef DEBUG_SYSINIT
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
+#else
+#define dbg(format, arg...) do { ; } while (0)
+#endif /* DEBUG_SYSINIT */
+
 #define UNUSED(x) (void)(x)				/* Unused variable         */

 bool fpga_configured = false;			/* for FPGA JTAG configuration */
@@ -244,7 +251,7 @@ void init_serial(void)
 	MCF_PSC0_PSCOPSET = 0x01;
 	MCF_PSC0_PSCCR = 0x05;

-#ifdef MACHINE_FIREBEE	/* PSC3 is not connected to anything on the LITE board */
+#if defined(MACHINE_FIREBEE)	/* PSC3 is not connected to anything on the LITE board */
 	/* PSC3: PIC */
 	MCF_PSC3_PSCSICR = 0;	// UART
 	MCF_PSC3_PSCCSR = 0xDD;
@@ -480,12 +487,123 @@ void wait_pll(void)
 	} while ((* (volatile int16_t *) 0xf0000800 < 0) && MCF_SLT0_SCNT > trgt);
 }

-static volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600;
+
+volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600;
+
+//#define _OLD_CODE_ /* use old PLL initialization code */
+#ifndef _OLD_CODE_
+
+/*
+ * the altpll_reconfig component is connected to the Bus as follows:
+ *
+ * 9 bit data:
+ * 876543210 (this _is_ actually the last part of the address written or read!)
+ * | ||  |
+ * | |+--+- counter_type
+ * +-+----- counter_param
+ *
+ * 9 bit data
+ * 876543210
+ * +-------+- data_in
+ *
+ * counter_type selects which counter should be affected by data_in:
+ * 0000 - N
+ * 0001 - M
+ * 0010 - CP/LF (charge pump/loop filter)
+ * 0011 - VCO (voltage controlled oscillator)
+ * 0100 - C0
+ * 0101 - C1
+ * 0110 - C2
+ * 0111 - C3
+ * 1000 - C4
+ *
+ * counter_param selects which part of the selected counter_type is set/read and how many
+ * bits are used/valid:
+ *
+ * for counter_type N, M, C0-C4:
+ * 000 - high count, 8 bit
+ * 001 - low count, 8 bit
+ * 100 - bypass, 1 bit
+ * 101 - mode (odd/even division), 1 bit
+ *
+ * for counter_type CP/LF:
+ * 101 - charge pump unused, 5 bit
+ * 000 - charge pump current, 3 bit
+ * 100 - loop filter unused, 1 bit
+ * 001 - loop filter resistor, 5 bit
+ * 010 - loop filter capacitance, 2 bit
+ *
+ * for counter_type VCO:
+ * 000 - VCO post scale, 1 bit
+ */
+
+#define PLL_COUNTER_TYPE_N      0
+#define PLL_COUNTER_TYPE_M      1
+#define PLL_COUNTER_TYPE_CPLF   2
+#define PLL_COUNTER_TYPE_VCO    3
+#define PLL_COUNTER_TYPE_C0     4
+#define PLL_COUNTER_TYPE_C1     5
+#define PLL_COUNTER_TYPE_C2     6
+#define PLL_COUNTER_TYPE_C3     7
+#define PLL_COUNTER_TYPE_C4     8
+
+#define PLL_COUNTER_PARAM_HC    0
+#define PLL_COUNTER_PARAM_LC    1
+#define PLL_COUNTER_PARAM_BP    4
+#define PLL_COUNTER_PARAM_MODE  5
+
+#define PLL_COUNTER_PARAM_CP_U  5
+#define PLL_COUNTER_PARAM_CP_C  0
+#define PLL_COUNTER_PARAM_LF_U  4
+#define PLL_COUNTER_PARAM_LF_R  1
+#define PLL_COUNTER_PARAM_LF_C  2
+
+#define PLL_COUNTER_PARAM_VCO_PS    0
+
+void pll_write(int type, int param, int data)
+{
+	wait_pll();
+	* (volatile uint16_t *) (pll_base + ((param << 6) | (type << 2))) = data;
+}
+
+struct pll_init
+{
+	int type;
+	int param;
+	int data;
+};
+
+struct pll_init pll_values[] =
+{
+	{ PLL_COUNTER_TYPE_CPLF, PLL_COUNTER_PARAM_LF_R, 27 },	/* loopfilter R */
+	{ PLL_COUNTER_TYPE_CPLF, PLL_COUNTER_PARAM_LF_C, 1 },	/* charge pump 1 */
+	{ PLL_COUNTER_TYPE_N, PLL_COUNTER_PARAM_HC, 12 },		/* N counter high */
+	{ PLL_COUNTER_TYPE_N, PLL_COUNTER_PARAM_LC, 12 },		/* N counter low */
+	{ PLL_COUNTER_TYPE_C1, PLL_COUNTER_PARAM_BP, 1 },		/* c1 bypass */
+	{ PLL_COUNTER_TYPE_C2, PLL_COUNTER_PARAM_BP, 1 },		/* c2 bypass */
+	{ PLL_COUNTER_TYPE_C3, PLL_COUNTER_PARAM_BP, 1 },		/* c3 bypass */
+	{ PLL_COUNTER_TYPE_C0, PLL_COUNTER_PARAM_HC, 1 },		/* c0 high */
+	{ PLL_COUNTER_TYPE_C0, PLL_COUNTER_PARAM_LC, 1 },		/* c0 low */
+	{ PLL_COUNTER_TYPE_M, PLL_COUNTER_PARAM_MODE, 1 },		/* M odd division */
+	{ PLL_COUNTER_TYPE_M, PLL_COUNTER_PARAM_LC, 1 },		/* M low = 1 */
+	{ PLL_COUNTER_TYPE_M, PLL_COUNTER_PARAM_HC, 145 }		/* M high = 145 = 146 MHz */
+};
+int num_pll_values = sizeof(pll_values) / sizeof(struct pll_init);
+#endif /* _OLD_CODE_ */

 void init_pll(void)
 {
+	int i;
+
 	xprintf("FPGA PLL initialization: ");

+#ifndef _OLD_CODE_
+	for (i = 0; i < num_pll_values; i++)
+	{
+		pll_write(pll_values[i].type, pll_values[i].param, pll_values[i].data);
+	}
+
+#else /* _OLD_CODE_ */
 	wait_pll();
 	* (volatile uint16_t *) (pll_base + 0x48) = 27;	/* loopfilter  r */

@@ -496,7 +614,7 @@ void init_pll(void)
 	* (volatile uint16_t *) (pll_base + 0x00) = 12;		/* N counter high = 12 */

 	wait_pll();
-	* (volatile uint16_t *) (pll_base + 0x40) = 12;		/* N counter low = 12 */
+	 * (volatile uint16_t *) (pll_base + 0x40) = 12;		/* N counter low = 12 */

 	wait_pll();
 	* (volatile uint16_t *) (pll_base + 0x114) = 1;		/* ck1 bypass */
@@ -523,6 +641,7 @@ void init_pll(void)
 	* (volatile uint16_t *) (pll_base + 0x04) = 145;	/* M high = 145 = 146 MHz */

 	wait_pll();
+#endif /* _OLD_CODE_ */

 	* (volatile uint8_t *) 0xf0000800 = 0;				/* set */

@@ -562,7 +681,7 @@ void init_video_ddr(void) {
 	_VRAM = 0000070022;	/* load MR dll on */
 	NOP();

-	* (uint32_t *) 0xf0000400 = 0x01070002; /* fifo on, refresh on, ddrcs und cke on, video dac on */
+	* (uint32_t *) 0xf0000400 = 0x01070002; /* fifo on, refresh on, ddrcs and cke on, video dac on */

 	xprintf("finished\r\n");
 }
@@ -588,41 +707,52 @@ void init_usb(void)
 		if (handle > 0)
 		{
 			uint32_t id = 0;
-			uint32_t class = 0;
+			uint32_t pci_class = 0;

 			id = pci_read_config_longword(handle, PCIIDR);
-			class = pci_read_config_longword(handle, PCIREV);
-
-			if (PCI_CLASS_CODE(class) == PCI_CLASS_SERIAL_USB)
+			pci_class = pci_read_config_longword(handle, PCIREV);
+			dbg("compare class code 0x%x to 0x%x\r\n", PCI_CLASS_CODE(pci_class), PCI_CLASS_SERIAL_USB);
+			if (PCI_CLASS_CODE(pci_class) == PCI_CLASS_SERIAL_USB)
 			{
 				xprintf("serial USB found at bus=0x%x, dev=0x%x, fnc=0x%x (0x%x)\r\n",
 						PCI_BUS_FROM_HANDLE(handle),
 						PCI_DEVICE_FROM_HANDLE(handle),
 						PCI_FUNCTION_FROM_HANDLE(handle),
 						handle);
-				if (PCI_SUBCLASS(class) == PCI_CLASS_SERIAL_USB_EHCI)
+				dbg("compare subclass code 0x%x against 0x%x\r\n", PCI_SUBCLASS(pci_class), PCI_CLASS_SERIAL_USB_EHCI);
+				if (PCI_SUBCLASS(pci_class) == PCI_CLASS_SERIAL_USB_EHCI)
 				{
 					board = ehci_usb_pci_table;
 					while (board->vendor)
 					{
+						dbg("compare vendor id 0x%x against 0x%x\r\n", board->vendor, PCI_VENDOR_ID(id));
+						dbg("compare device id 0x%x against 0x%x\r\n", board->device, PCI_DEVICE_ID(id));
 						if ((board->vendor == PCI_VENDOR_ID(id)) && board->device == PCI_DEVICE_ID(id))
 						{
+#ifdef _NOT_YET_	/* FIXME: usb_init() is broken */
+							dbg("match. trying to init board\r\n");
 							if (usb_init(handle, board) >= 0)
 							{
 								usb_found++;
 							}
+#endif /* _NOT_YET_ */
 						}
 						board++;
 					}
 				}
-				if (PCI_SUBCLASS(class) == PCI_CLASS_SERIAL_USB_OHCI)
+
+				dbg("compare subclass code 0x%x against 0x%x\r\n", PCI_SUBCLASS(pci_class), PCI_CLASS_SERIAL_USB_OHCI);
+				if (PCI_SUBCLASS(pci_class) == PCI_CLASS_SERIAL_USB_OHCI)
 				{
 					board = ohci_usb_pci_table;
+
 					while (board->vendor)
 					{
+						dbg("matched. compare vendor id 0x%x against 0x%x\r\n", board->vendor, PCI_VENDOR_ID(id));
+						dbg("compare device id 0x%x against 0x%x\r\n", board->device, PCI_DEVICE_ID(id));
 						if ((board->vendor == PCI_VENDOR_ID(id)) && board->device == PCI_DEVICE_ID(id))
 						{
-							if (usb_init(handle, board) >= 0)
+							// if (usb_init(handle, board) >= 0)
 								usb_found++;
 						}
 						board++;
@@ -630,6 +760,7 @@ void init_usb(void)
 				}
 			}
 		}
+		dbg("PCI device handle = %x\r\n", handle);
 	} while (handle >= 0);

 	xprintf("finished (found %d USB controller(s))\r\n", usb_found);
@@ -932,8 +1063,6 @@ void clear_bss_segment(void)

 void initialize_hardware(void)
 {
-	bool coldboot = true;
-
 	/* Test for FireTOS switch: DIP switch #5 up */
 #ifdef MACHINE_FIREBEE
 	if (!(DIP_SWITCH & (1 << 6))) {
@@ -977,6 +1106,9 @@ void initialize_hardware(void)
 #endif
 	, MAJOR_VERSION, MINOR_VERSION, __DATE__, __TIME__);

+	extern char *rom_header;
+
+	xprintf("running from %p\r\n\r\n", &rom_header);
 	/*
 	 * Determine cause(s) of Reset
 	 */
@@ -1049,19 +1181,13 @@ void initialize_hardware(void)

 	init_slt();
 	init_fbcs();
-	coldboot = init_ddram();
+	init_ddram();

 	/*
 	 * install (preliminary) exception vectors
 	 */
 	setup_vectors();

-#ifdef _NOT_USED_
-	/* make sure the handlers are called */
-	__asm__ __volatile__("dc.w 0xafff");  /* should trigger a line-A exception */
-#endif /* _NOT_USED_ */
-
-
 	/*
 	 * save the planet (and reduce case heat): disable clocks of unused SOC modules
 	 */
@@ -1095,8 +1221,6 @@ void initialize_hardware(void)
 	}

 #if MACHINE_FIREBEE
-	if (coldboot) /* does not work with BDM */
-		;
 	fpga_configured = init_fpga();

 	init_pll();
@@ -1108,10 +1232,8 @@ void initialize_hardware(void)
 	init_pci();
 	video_init();

-	/* do not try to init USB for now on the Firebee, it hangs the machine */
-#ifndef MACHINE_FIREBEE
-	//init_usb();
-#endif
+	/* initialize USB devices */
+	init_usb();

 #if MACHINE_FIREBEE
 	init_ac97();
--- a/tos/Makefile
+++ b/tos/Makefile
@@ -0,0 +1,11 @@
+.PHONY: tos
+.PHONY: jtagwait
+.PHONY: mcdcook
+tos: jtagwait mcdcook
+
+jtagwait:
+	(cd $@; make)
+
+bascook:
+	(cd $@; make)
+	
--- a/tos/bascook/Makefile
+++ b/tos/bascook/Makefile
@@ -0,0 +1,97 @@
+CROSS=Y
+
+CROSSBINDIR_IS_Y=m68k-atari-mint-
+CROSSBINDIR_IS_N=
+
+CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS))
+
+UNAME := $(shell uname)
+ifeq ($(CROSS), Y)
+ifeq ($(UNAME),Linux)
+PREFIX=m68k-atari-mint
+HATARI=hatari
+else
+PREFIX=m68k-atari-mint
+HATARI=/usr/local/bin/hatari
+endif
+else
+PREFIX=/usr
+endif
+
+DEPEND=depend
+TOPDIR= ../..
+
+BAS_INCLUDE=-I$(TOPDIR)/../BaS_gcc/include
+
+INCLUDE=-I$(TOPDIR)/../libcmini/include $(BAS_INCLUDE) -nostdlib
+LIBS=-lcmini -nostdlib -lgcc
+CC=$(PREFIX)/bin/gcc
+
+CC=$(CROSSBINDIR)gcc
+STRIP=$(CROSSBINDIR)strip
+STACK=$(CROSSBINDIR)stack
+
+APP=bascook.prg
+TEST_APP=$(APP)
+
+CFLAGS=\
+	-Os\
+	-g\
+	-Wl,-Map,mapfile\
+	-Wall
+
+SRCDIR=sources
+
+CSRCS=\
+	$(SRCDIR)/bascook.c
+ASRCS=
+
+COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS)))
+AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS)))
+OBJS=$(COBJS) $(AOBJS)
+
+TRGTDIRS=.
+OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS))
+
+#
+# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output
+#
+$(APP):CFLAGS += -mcpu=5475
+
+all: $(TEST_APP)
+
+#
+# generate pattern rules for multilib object files.
+#
+define CC_TEMPLATE
+$(1)/objs/%.o:$(SRCDIR)/%.c
+	$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
+
+$(1)/objs/%.o:$(SRCDIR)/%.S
+	$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
+
+$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
+$(1)/$(APP): $$($(1)_OBJS)
+	$(CC) $$(CFLAGS) -o $$@ $(TOPDIR)/../libcmini/m5475/startup.o $$($(1)_OBJS) -L$(TOPDIR)/../libcmini/m5475 $(LIBS)
+	$(STRIP) $$@
+endef
+$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
+
+$(DEPEND): $(ASRCS) $(CSRCS)
+	-rm -f $(DEPEND)
+	for d in $(TRGTDIRS);\
+		do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \
+    done
+
+
+clean:
+	@rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS))
+	@rm -f $(DEPEND) mapfile
+
+.PHONY: printvars
+printvars:
+	@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
+
+ifneq (clean,$(MAKECMDGOALS))
+-include $(DEPEND)
+endif
--- a/tos/bascook/sources/bascook.c
+++ b/tos/bascook/sources/bascook.c
@@ -0,0 +1,122 @@
+#include <stdio.h>
+#include <mint/osbind.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "driver_vec.h"
+
+struct driver_table *get_bas_drivers(void)
+{
+	struct driver_table *ret = NULL;
+
+	__asm__ __volatile(
+		"	trap	#0\n\t"
+		"	move.l	d0,%[ret]\n\t"
+		:	[ret] "=m" (ret)	/* output */
+		:						/* no inputs */
+		:						/* clobbered */
+	);
+
+	return ret;
+}
+
+static uint32_t cookieptr(void)
+{
+	return * (uint32_t *) 0x5a0L;
+}
+
+void setcookie(uint32_t cookie, uint32_t value)
+{
+	uint32_t *cookiejar = (uint32_t *) Supexec(cookieptr);
+	int num_slots;
+	int max_slots;
+
+	num_slots = max_slots = 0;
+	do
+	{
+		if (cookiejar[0] == cookie)
+		{
+			cookiejar[1] = value;
+			return;
+		}
+		cookiejar = &(cookiejar[2]);
+		num_slots++;
+	} while (cookiejar[-2]);
+
+	/*
+	 * Here we are at the end of the list and did not find our cookie.
+	 * Let's check if there is any space left and append our value to the
+	 * list if so. If not, we are lost (extending the cookie jar does only
+	 * work from TSRs)
+	 */
+	if (cookiejar[-1])
+		max_slots = cookiejar[-1];
+
+	if (max_slots > num_slots)
+	{
+		 /* relief, there is space left, extend the list */
+		cookiejar[0] = cookiejar[-2];
+		cookiejar[1] = cookiejar[-1];
+		/* add the new element */
+		cookiejar[-2] = cookie;
+		cookiejar[-1] = value;
+	}
+	else
+		printf("cannot set cookie, cookie jar is full!\r\n");
+}
+
+# define COOKIE_DMAC	0x444D4143L /* FireTOS DMA API */
+
+static char *dt_to_str(enum driver_type dt)
+{
+	switch (dt)
+	{
+		case BLOCKDEV_DRIVER: return "generic block device driver";
+		case CHARDEV_DRIVER:  return "generic character device driver";
+		case VIDEO_DRIVER:    return "video/framebuffer driver";
+		case XHDI_DRIVER:     return "XHDI compatible hard disk driver";
+		case MCD_DRIVER:	  return "multichannel DMA driver";
+		case PCI_DRIVER:	  return "PCI interface driver";
+		default:              return "unknown driver type";
+	}
+}
+
+int main(int argc, char *argv[])
+{
+	struct driver_table *dt;
+	void *ssp;
+
+	(void) Cconws("retrieve BaS driver interface\r\n");
+
+	ssp = (void *) Super(0L);
+	dt = get_bas_drivers();
+	if (dt)
+	{
+		struct generic_interface *ifc = &dt->interfaces[0];
+
+		printf("BaS driver table found at %p, BaS version is %d.%d\r\n", dt,
+				dt->bas_version, dt->bas_revision);
+
+		while (ifc->type != END_OF_DRIVERS)
+		{
+			printf("driver \"%s (%s)\" found,\r\n"
+				   "interface type is %d (%s),\r\n"
+				   "version %d.%d\r\n\r\n",
+					ifc->name, ifc->description, ifc->type, dt_to_str(ifc->type),
+					ifc->version, ifc->revision);
+			if (ifc->type == MCD_DRIVER)
+			{
+				setcookie(COOKIE_DMAC, (uint32_t) ifc->interface.dma);
+				printf("\r\nDMAC cookie set to %p\r\n", ifc->interface.dma);
+			}
+			ifc++;
+		}
+	}
+	Super(ssp);
+
+	while (Cconis()) Cconin();	/* eat keys */
+	// printf("press any key to continue\n\r");
+	// while (! Cconis());
+	return 0;
+}
+
--- a/tos/jtagwait/Makefile
+++ b/tos/jtagwait/Makefile
@@ -0,0 +1,103 @@
+CROSS=Y
+
+CROSSBINDIR_IS_Y=m68k-atari-mint-
+CROSSBINDIR_IS_N=
+
+CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS))
+
+UNAME := $(shell uname)
+ifeq ($(CROSS), Y)
+ifeq ($(UNAME),Linux)
+PREFIX=m68k-atari-mint
+HATARI=hatari
+else
+PREFIX=m68k-atari-mint
+HATARI=/usr/local/bin/hatari
+endif
+else
+PREFIX=/usr
+endif
+
+DEPEND=depend
+TOPDIR = ../..
+
+INCLUDE=-I$(TOPDIR)/../libcmini/include -nostdlib
+LIBS=-lcmini -nostdlib -lgcc
+CC=$(PREFIX)/bin/gcc
+
+CC=$(CROSSBINDIR)gcc
+STRIP=$(CROSSBINDIR)strip
+STACK=$(CROSSBINDIR)stack
+
+APP=jtagwait.prg
+TEST_APP=$(APP)
+
+CFLAGS=\
+	-O0\
+	-g\
+	-Wl,-Map,mapfile\
+	-Wl,--defsym -Wl,__MBAR=0xff000000\
+	-Wl,--defsym -Wl,__MMUBAR=0xff040000\
+	-Wl,--defsym -Wl,__FPGA_JTAG_LOADED=0xff101000\
+	-Wl,--defsym -Wl,__FPGA_JTAG_VALID=0xff101004\
+	-Wall
+
+SRCDIR=sources
+INCDIR=include
+INCLUDE+=-I$(INCDIR)
+
+CSRCS=\
+	$(SRCDIR)/jtagwait.c \
+	$(SRCDIR)/bas_printf.c
+
+ASRCS=$(SRCDIR)/printf_helper.S
+
+COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS)))
+AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS)))
+OBJS=$(COBJS) $(AOBJS)
+
+TRGTDIRS=./m5475 ./m5475/mshort
+OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS))
+
+#
+# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output
+#
+m5475/$(APP):CFLAGS += -mcpu=5475
+m5475/mshort/$(APP): CFLAGS += -mcpu=5475 -mshort
+
+all:$(patsubst %,%/$(APP),$(TRGTDIRS))
+#
+# generate pattern rules for multilib object files.
+#
+define CC_TEMPLATE
+$(1)/objs/%.o:$(SRCDIR)/%.c
+	$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
+
+$(1)/objs/%.o:$(SRCDIR)/%.S
+	$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
+
+$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
+$(1)/$(APP): $$($(1)_OBJS)
+	$(CC) $$(CFLAGS) -o $$@ $(TOPDIR)/../libcmini/$(1)/startup.o $$($(1)_OBJS) -L$(TOPDIR)/../libcmini/$(1) $(LIBS)
+	$(STRIP) $$@
+endef
+$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
+
+$(DEPEND): $(ASRCS) $(CSRCS)
+	-rm -f $(DEPEND)
+	for d in $(TRGTDIRS);\
+		do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \
+    done
+
+
+clean:
+	@rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS))
+	@rm -f $(DEPEND) mapfile
+
+.PHONY: printvars
+printvars:
+	@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
+
+ifneq (clean,$(MAKECMDGOALS))
+-include $(DEPEND)
+endif
--- a/tos/jtagwait/include/MCF5475.h
+++ b/tos/jtagwait/include/MCF5475.h
@@ -0,0 +1,67 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_H__
+#define __MCF5475_H__
+
+#include <stdint.h>
+/***
+ * MCF5475 Derivative Memory map definitions from linker command files:
+ * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
+ * linker symbols must be defined in the linker command file.
+ */
+
+typedef uint32_t __attribute__((__may_alias__)) uint32_t_a;	/* a type to avoid gcc's complaints about pointer aliasing */
+
+extern uint8_t _MBAR[];
+extern uint8_t _MMUBAR[];
+extern uint8_t _RAMBAR0[];
+extern uint8_t _RAMBAR0_SIZE[];
+extern uint8_t _RAMBAR1[];
+extern uint8_t _RAMBAR1_SIZE[];
+
+#define MBAR_ADDRESS    (uint32_t)_MBAR
+#define MMUBAR_ADDRESS  (uint32_t)_MMUBAR
+#define RAMBAR0_ADDRESS (uint32_t)_RAMBAR0
+#define RAMBAR0_SIZE    (uint32_t)_RAMBAR0_SIZE
+#define RAMBAR1_ADDRESS (uint32_t)_RAMBAR1
+#define RAMBAR1_SIZE    (uint32_t)_RAMBAR1_SIZE
+
+
+#include "MCF5475_SIU.h"
+#include "MCF5475_MMU.h"
+#include "MCF5475_SDRAMC.h"
+#include "MCF5475_XLB.h"
+#include "MCF5475_CLOCK.h"
+#include "MCF5475_FBCS.h"
+#include "MCF5475_INTC.h"
+#include "MCF5475_GPT.h"
+#include "MCF5475_SLT.h"
+#include "MCF5475_GPIO.h"
+#include "MCF5475_PAD.h"
+#include "MCF5475_PCI.h"
+#include "MCF5475_PCIARB.h"
+#include "MCF5475_EPORT.h"
+#include "MCF5475_CTM.h"
+#include "MCF5475_DMA.h"
+#include "MCF5475_PSC.h"
+#include "MCF5475_DSPI.h"
+#include "MCF5475_I2C.h"
+#include "MCF5475_FEC.h"
+#include "MCF5475_USB.h"
+#include "MCF5475_SRAM.h"
+#include "MCF5475_SEC.h"
+
+#endif /* __MCF5475_H__ */
--- a/tos/jtagwait/include/MCF5475_CLOCK.h
+++ b/tos/jtagwait/include/MCF5475_CLOCK.h
@@ -0,0 +1,47 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_CLOCK_H__
+#define __MCF5475_CLOCK_H__
+
+
+/*********************************************************************
+*
+* Clock Module (CLOCK)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CLOCK_SPCR                       (*(volatile uint32_t*)(&_MBAR[0x300]))
+
+
+/* Bit definitions and macros for MCF_CLOCK_SPCR */
+#define MCF_CLOCK_SPCR_MEMEN                 (0x1)
+#define MCF_CLOCK_SPCR_PCIEN                 (0x2)
+#define MCF_CLOCK_SPCR_FBEN                  (0x4)
+#define MCF_CLOCK_SPCR_CAN0EN                (0x8)
+#define MCF_CLOCK_SPCR_DMAEN                 (0x10)
+#define MCF_CLOCK_SPCR_FEC0EN                (0x20)
+#define MCF_CLOCK_SPCR_FEC1EN                (0x40)
+#define MCF_CLOCK_SPCR_USBEN                 (0x80)
+#define MCF_CLOCK_SPCR_PSCEN                 (0x200)
+#define MCF_CLOCK_SPCR_CAN1EN                (0x800)
+#define MCF_CLOCK_SPCR_CRYENA                (0x1000)
+#define MCF_CLOCK_SPCR_CRYENB                (0x2000)
+#define MCF_CLOCK_SPCR_COREN                 (0x4000)
+#define MCF_CLOCK_SPCR_PLLK                  (0x80000000)
+
+
+#endif /* __MCF5475_CLOCK_H__ */
--- a/tos/jtagwait/include/MCF5475_CTM.h
+++ b/tos/jtagwait/include/MCF5475_CTM.h
@@ -0,0 +1,76 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_CTM_H__
+#define __MCF5475_CTM_H__
+
+
+/*********************************************************************
+*
+* Comm Timer Module (CTM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CTM_CTCR0                        (*(volatile uint32_t*)(&_MBAR[0x7F00]))
+#define MCF_CTM_CTCR1                        (*(volatile uint32_t*)(&_MBAR[0x7F04]))
+#define MCF_CTM_CTCR2                        (*(volatile uint32_t*)(&_MBAR[0x7F08]))
+#define MCF_CTM_CTCR3                        (*(volatile uint32_t*)(&_MBAR[0x7F0C]))
+#define MCF_CTM_CTCR4                        (*(volatile uint32_t*)(&_MBAR[0x7F10]))
+#define MCF_CTM_CTCR5                        (*(volatile uint32_t*)(&_MBAR[0x7F14]))
+#define MCF_CTM_CTCR6                        (*(volatile uint32_t*)(&_MBAR[0x7F18]))
+#define MCF_CTM_CTCR7                        (*(volatile uint32_t*)(&_MBAR[0x7F1C]))
+#define MCF_CTM_CTCRF(x)                     (*(volatile uint32_t*)(&_MBAR[0x7F00 + ((x)*0x4)]))
+#define MCF_CTM_CTCRV(x)                     (*(volatile uint32_t*)(&_MBAR[0x7F10 + ((x-4)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_CTM_CTCRF */
+#define MCF_CTM_CTCRF_CRV(x)                 (((x)&0xFFFF)<<0)
+#define MCF_CTM_CTCRF_S(x)                   (((x)&0xF)<<0x10)
+#define MCF_CTM_CTCRF_S_CLK_1                (0)
+#define MCF_CTM_CTCRF_S_CLK_2                (0x10000)
+#define MCF_CTM_CTCRF_S_CLK_4                (0x20000)
+#define MCF_CTM_CTCRF_S_CLK_8                (0x30000)
+#define MCF_CTM_CTCRF_S_CLK_16               (0x40000)
+#define MCF_CTM_CTCRF_S_CLK_32               (0x50000)
+#define MCF_CTM_CTCRF_S_CLK_64               (0x60000)
+#define MCF_CTM_CTCRF_S_CLK_128              (0x70000)
+#define MCF_CTM_CTCRF_S_CLK_256              (0x80000)
+#define MCF_CTM_CTCRF_S_CLK_EXT              (0x90000)
+#define MCF_CTM_CTCRF_PCT(x)                 (((x)&0x7)<<0x14)
+#define MCF_CTM_CTCRF_PCT_100                (0)
+#define MCF_CTM_CTCRF_PCT_50                 (0x100000)
+#define MCF_CTM_CTCRF_PCT_25                 (0x200000)
+#define MCF_CTM_CTCRF_PCT_12p5               (0x300000)
+#define MCF_CTM_CTCRF_PCT_6p25               (0x400000)
+#define MCF_CTM_CTCRF_PCT_OFF                (0x500000)
+#define MCF_CTM_CTCRF_M                      (0x800000)
+#define MCF_CTM_CTCRF_IM                     (0x1000000)
+#define MCF_CTM_CTCRF_I                      (0x80000000)
+
+/* Bit definitions and macros for MCF_CTM_CTCRV */
+#define MCF_CTM_CTCRV_CRV(x)                 (((x)&0xFFFFFF)<<0)
+#define MCF_CTM_CTCRV_PCT(x)                 (((x)&0x7)<<0x18)
+#define MCF_CTM_CTCRV_PCT_100                (0)
+#define MCF_CTM_CTCRV_PCT_50                 (0x1000000)
+#define MCF_CTM_CTCRV_PCT_25                 (0x2000000)
+#define MCF_CTM_CTCRV_PCT_12p5               (0x3000000)
+#define MCF_CTM_CTCRV_PCT_6p25               (0x4000000)
+#define MCF_CTM_CTCRV_PCT_OFF                (0x5000000)
+#define MCF_CTM_CTCRV_M                      (0x8000000)
+#define MCF_CTM_CTCRV_S                      (0x10000000)
+
+
+#endif /* __MCF5475_CTM_H__ */
--- a/tos/jtagwait/include/MCF5475_DMA.h
+++ b/tos/jtagwait/include/MCF5475_DMA.h
@@ -0,0 +1,234 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_DMA_H__
+#define __MCF5475_DMA_H__
+
+
+/*********************************************************************
+*
+* Multichannel DMA (DMA)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DMA_TASKBAR                      (*(volatile uint32_t*)(&_MBAR[0x8000]))
+#define MCF_DMA_CP                           (*(volatile uint32_t*)(&_MBAR[0x8004]))
+#define MCF_DMA_EP                           (*(volatile uint32_t*)(&_MBAR[0x8008]))
+#define MCF_DMA_VP                           (*(volatile uint32_t*)(&_MBAR[0x800C]))
+#define MCF_DMA_PTD                          (*(volatile uint32_t*)(&_MBAR[0x8010]))
+#define MCF_DMA_DIPR                         (*(volatile uint32_t*)(&_MBAR[0x8014]))
+#define MCF_DMA_DIMR                         (*(volatile uint32_t*)(&_MBAR[0x8018]))
+#define MCF_DMA_TCR0                         (*(volatile uint16_t*)(&_MBAR[0x801C]))
+#define MCF_DMA_TCR1                         (*(volatile uint16_t*)(&_MBAR[0x801E]))
+#define MCF_DMA_TCR2                         (*(volatile uint16_t*)(&_MBAR[0x8020]))
+#define MCF_DMA_TCR3                         (*(volatile uint16_t*)(&_MBAR[0x8022]))
+#define MCF_DMA_TCR4                         (*(volatile uint16_t*)(&_MBAR[0x8024]))
+#define MCF_DMA_TCR5                         (*(volatile uint16_t*)(&_MBAR[0x8026]))
+#define MCF_DMA_TCR6                         (*(volatile uint16_t*)(&_MBAR[0x8028]))
+#define MCF_DMA_TCR7                         (*(volatile uint16_t*)(&_MBAR[0x802A]))
+#define MCF_DMA_TCR8                         (*(volatile uint16_t*)(&_MBAR[0x802C]))
+#define MCF_DMA_TCR9                         (*(volatile uint16_t*)(&_MBAR[0x802E]))
+#define MCF_DMA_TCR10                        (*(volatile uint16_t*)(&_MBAR[0x8030]))
+#define MCF_DMA_TCR11                        (*(volatile uint16_t*)(&_MBAR[0x8032]))
+#define MCF_DMA_TCR12                        (*(volatile uint16_t*)(&_MBAR[0x8034]))
+#define MCF_DMA_TCR13                        (*(volatile uint16_t*)(&_MBAR[0x8036]))
+#define MCF_DMA_TCR14                        (*(volatile uint16_t*)(&_MBAR[0x8038]))
+#define MCF_DMA_TCR15                        (*(volatile uint16_t*)(&_MBAR[0x803A]))
+#define MCF_DMA_PRIOR0                       (*(volatile uint8_t *)(&_MBAR[0x803C]))
+#define MCF_DMA_PRIOR1                       (*(volatile uint8_t *)(&_MBAR[0x803D]))
+#define MCF_DMA_PRIOR2                       (*(volatile uint8_t *)(&_MBAR[0x803E]))
+#define MCF_DMA_PRIOR3                       (*(volatile uint8_t *)(&_MBAR[0x803F]))
+#define MCF_DMA_PRIOR4                       (*(volatile uint8_t *)(&_MBAR[0x8040]))
+#define MCF_DMA_PRIOR5                       (*(volatile uint8_t *)(&_MBAR[0x8041]))
+#define MCF_DMA_PRIOR6                       (*(volatile uint8_t *)(&_MBAR[0x8042]))
+#define MCF_DMA_PRIOR7                       (*(volatile uint8_t *)(&_MBAR[0x8043]))
+#define MCF_DMA_PRIOR8                       (*(volatile uint8_t *)(&_MBAR[0x8044]))
+#define MCF_DMA_PRIOR9                       (*(volatile uint8_t *)(&_MBAR[0x8045]))
+#define MCF_DMA_PRIOR10                      (*(volatile uint8_t *)(&_MBAR[0x8046]))
+#define MCF_DMA_PRIOR11                      (*(volatile uint8_t *)(&_MBAR[0x8047]))
+#define MCF_DMA_PRIOR12                      (*(volatile uint8_t *)(&_MBAR[0x8048]))
+#define MCF_DMA_PRIOR13                      (*(volatile uint8_t *)(&_MBAR[0x8049]))
+#define MCF_DMA_PRIOR14                      (*(volatile uint8_t *)(&_MBAR[0x804A]))
+#define MCF_DMA_PRIOR15                      (*(volatile uint8_t *)(&_MBAR[0x804B]))
+#define MCF_DMA_PRIOR16                      (*(volatile uint8_t *)(&_MBAR[0x804C]))
+#define MCF_DMA_PRIOR17                      (*(volatile uint8_t *)(&_MBAR[0x804D]))
+#define MCF_DMA_PRIOR18                      (*(volatile uint8_t *)(&_MBAR[0x804E]))
+#define MCF_DMA_PRIOR19                      (*(volatile uint8_t *)(&_MBAR[0x804F]))
+#define MCF_DMA_PRIOR20                      (*(volatile uint8_t *)(&_MBAR[0x8050]))
+#define MCF_DMA_PRIOR21                      (*(volatile uint8_t *)(&_MBAR[0x8051]))
+#define MCF_DMA_PRIOR22                      (*(volatile uint8_t *)(&_MBAR[0x8052]))
+#define MCF_DMA_PRIOR23                      (*(volatile uint8_t *)(&_MBAR[0x8053]))
+#define MCF_DMA_PRIOR24                      (*(volatile uint8_t *)(&_MBAR[0x8054]))
+#define MCF_DMA_PRIOR25                      (*(volatile uint8_t *)(&_MBAR[0x8055]))
+#define MCF_DMA_PRIOR26                      (*(volatile uint8_t *)(&_MBAR[0x8056]))
+#define MCF_DMA_PRIOR27                      (*(volatile uint8_t *)(&_MBAR[0x8057]))
+#define MCF_DMA_PRIOR28                      (*(volatile uint8_t *)(&_MBAR[0x8058]))
+#define MCF_DMA_PRIOR29                      (*(volatile uint8_t *)(&_MBAR[0x8059]))
+#define MCF_DMA_PRIOR30                      (*(volatile uint8_t *)(&_MBAR[0x805A]))
+#define MCF_DMA_PRIOR31                      (*(volatile uint8_t *)(&_MBAR[0x805B]))
+#define MCF_DMA_IMCR                         (*(volatile uint32_t*)(&_MBAR[0x805C]))
+#define MCF_DMA_TSKSZ0                       (*(volatile uint32_t*)(&_MBAR[0x8060]))
+#define MCF_DMA_TSKSZ1                       (*(volatile uint32_t*)(&_MBAR[0x8064]))
+#define MCF_DMA_DBGCOMP0                     (*(volatile uint32_t*)(&_MBAR[0x8070]))
+#define MCF_DMA_DBGCOMP2                     (*(volatile uint32_t*)(&_MBAR[0x8074]))
+#define MCF_DMA_DBGCTL                       (*(volatile uint32_t*)(&_MBAR[0x8078]))
+#define MCF_DMA_TCR(x)                       (*(volatile uint16_t*)(&_MBAR[0x801C + ((x)*0x2)]))
+#define MCF_DMA_PRIOR(x)                     (*(volatile uint8_t *)(&_MBAR[0x803C + ((x)*0x1)]))
+
+
+/* Bit definitions and macros for MCF_DMA_TASKBAR */
+#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_CP */
+#define MCF_DMA_CP_DESCRIPTOR_POINTER(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_EP */
+#define MCF_DMA_EP_DESCRIPTOR_POINTER(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_VP */
+#define MCF_DMA_VP_VARIABLE_POINTER(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_PTD */
+#define MCF_DMA_PTD_PCTL0                    (0x1)
+#define MCF_DMA_PTD_PCTL1                    (0x2)
+#define MCF_DMA_PTD_PCTL13                   (0x2000)
+#define MCF_DMA_PTD_PCTL14                   (0x4000)
+#define MCF_DMA_PTD_PCTL15                   (0x8000)
+
+/* Bit definitions and macros for MCF_DMA_DIPR */
+#define MCF_DMA_DIPR_TASK(x)                 (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DIMR */
+#define MCF_DMA_DIMR_TASK(x)                 (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_TCR */
+#define MCF_DMA_TCR_ASTSKNUM(x)              (((x)&0xF)<<0)
+#define MCF_DMA_TCR_HLDINITNUM               (0x20)
+#define MCF_DMA_TCR_HIPRITSKEN               (0x40)
+#define MCF_DMA_TCR_ASTRT                    (0x80)
+#define MCF_DMA_TCR_INITNUM(x)               (((x)&0x1F)<<0x8)
+#define MCF_DMA_TCR_ALWINIT                  (0x2000)
+#define MCF_DMA_TCR_V                        (0x4000)
+#define MCF_DMA_TCR_EN                       (0x8000)
+
+/* Bit definitions and macros for MCF_DMA_PRIOR */
+#define MCF_DMA_PRIOR_PRI(x)                 (((x)&0x7)<<0)
+#define MCF_DMA_PRIOR_HLD                    (0x80)
+
+/* Bit definitions and macros for MCF_DMA_IMCR */
+#define MCF_DMA_IMCR_IMC16(x)	(((x)&0x3)<<0)
+#define MCF_DMA_IMCR_IMC17(x)	(((x)&0x3)<<0x2)
+#define MCF_DMA_IMCR_IMC18(x)	(((x)&0x3)<<0x4)
+#define MCF_DMA_IMCR_IMC19(x)	(((x)&0x3)<<0x6)
+#define MCF_DMA_IMCR_IMC20(x)	(((x)&0x3)<<0x8)
+#define MCF_DMA_IMCR_IMC21(x)	(((x)&0x3)<<0xA)
+#define MCF_DMA_IMCR_IMC22(x)	(((x)&0x3)<<0xC)
+#define MCF_DMA_IMCR_IMC23(x)	(((x)&0x3)<<0xE)
+#define MCF_DMA_IMCR_IMC24(x)	(((x)&0x3)<<0x10)
+#define MCF_DMA_IMCR_IMC25(x)	(((x)&0x3)<<0x12)
+#define MCF_DMA_IMCR_IMC26(x)	(((x)&0x3)<<0x14)
+#define MCF_DMA_IMCR_IMC27(x)	(((x)&0x3)<<0x16)
+#define MCF_DMA_IMCR_IMC28(x)	(((x)&0x3)<<0x18)
+#define MCF_DMA_IMCR_IMC29(x)	(((x)&0x3)<<0x1A)
+#define MCF_DMA_IMCR_IMC30(x)	(((x)&0x3)<<0x1C)
+#define MCF_DMA_IMCR_IMC31(x)	(((x)&0x3)<<0x1E)
+
+
+#define MCF_DMA_IMCR_IMC16_FEC0RX    (0x00000000)
+#define MCF_DMA_IMCR_IMC17_FEC0TX    (0x00000000)
+#define MCF_DMA_IMCR_IMC18_FEC0RX    (0x00000020)
+#define MCF_DMA_IMCR_IMC19_FEC0TX    (0x00000080)
+#define MCF_DMA_IMCR_IMC20_FEC1RX    (0x00000100)
+#define MCF_DMA_IMCR_IMC21_DREQ1     (0x00000000)
+#define MCF_DMA_IMCR_IMC21_FEC1TX    (0x00000400)
+#define MCF_DMA_IMCR_IMC22_FEC0RX    (0x00001000)
+#define MCF_DMA_IMCR_IMC23_FEC0TX    (0x00004000)
+#define MCF_DMA_IMCR_IMC24_CTM0      (0x00010000)
+#define MCF_DMA_IMCR_IMC24_FEC1RX    (0x00020000)
+#define MCF_DMA_IMCR_IMC25_CTM1      (0x00040000)
+#define MCF_DMA_IMCR_IMC25_FEC1TX    (0x00080000)
+#define MCF_DMA_IMCR_IMC26_USBEP4    (0x00000000)
+#define MCF_DMA_IMCR_IMC26_CTM2      (0x00200000)
+#define MCF_DMA_IMCR_IMC27_USBEP5    (0x00000000)
+#define MCF_DMA_IMCR_IMC27_CTM3      (0x00800000)
+#define MCF_DMA_IMCR_IMC28_USBEP6    (0x00000000)
+#define MCF_DMA_IMCR_IMC28_CTM4      (0x01000000)
+#define MCF_DMA_IMCR_IMC28_DREQ1     (0x02000000)
+#define MCF_DMA_IMCR_IMC28_PSC2RX    (0x03000000)
+#define MCF_DMA_IMCR_IMC29_DREQ1     (0x04000000)
+#define MCF_DMA_IMCR_IMC29_CTM5      (0x08000000)
+#define MCF_DMA_IMCR_IMC29_PSC2TX    (0x0C000000)
+#define MCF_DMA_IMCR_IMC30_FEC1RX    (0x00000000)
+#define MCF_DMA_IMCR_IMC30_CTM6      (0x10000000)
+#define MCF_DMA_IMCR_IMC30_PSC3RX    (0x30000000)
+#define MCF_DMA_IMCR_IMC31_FEC1TX    (0x00000000)
+#define MCF_DMA_IMCR_IMC31_CTM7      (0x80000000)
+#define MCF_DMA_IMCR_IMC31_PSC3TX    (0xC0000000)
+
+/* Bit definitions and macros for MCF_DMA_TSKSZ0 */
+#define MCF_DMA_TSKSZ0_DSTSZ7(x)             (((x)&0x3)<<0)
+#define MCF_DMA_TSKSZ0_SRCSZ7(x)             (((x)&0x3)<<0x2)
+#define MCF_DMA_TSKSZ0_DSTSZ6(x)             (((x)&0x3)<<0x4)
+#define MCF_DMA_TSKSZ0_SRCSZ6(x)             (((x)&0x3)<<0x6)
+#define MCF_DMA_TSKSZ0_DSTSZ5(x)             (((x)&0x3)<<0x8)
+#define MCF_DMA_TSKSZ0_SRCSZ5(x)             (((x)&0x3)<<0xA)
+#define MCF_DMA_TSKSZ0_DSTSZ4(x)             (((x)&0x3)<<0xC)
+#define MCF_DMA_TSKSZ0_SRCSZ4(x)             (((x)&0x3)<<0xE)
+#define MCF_DMA_TSKSZ0_DSTSZ3(x)             (((x)&0x3)<<0x10)
+#define MCF_DMA_TSKSZ0_SRCSZ3(x)             (((x)&0x3)<<0x12)
+#define MCF_DMA_TSKSZ0_DSTSZ2(x)             (((x)&0x3)<<0x14)
+#define MCF_DMA_TSKSZ0_SRCSZ2(x)             (((x)&0x3)<<0x16)
+#define MCF_DMA_TSKSZ0_DSTSZ1(x)             (((x)&0x3)<<0x18)
+#define MCF_DMA_TSKSZ0_SRCSZ1(x)             (((x)&0x3)<<0x1A)
+#define MCF_DMA_TSKSZ0_DSTSZ0(x)             (((x)&0x3)<<0x1C)
+#define MCF_DMA_TSKSZ0_SRCSZ0(x)             (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_DMA_TSKSZ1 */
+#define MCF_DMA_TSKSZ1_DSTSZ15(x)            (((x)&0x3)<<0)
+#define MCF_DMA_TSKSZ1_SRCSZ15(x)            (((x)&0x3)<<0x2)
+#define MCF_DMA_TSKSZ1_DSTSZ14(x)            (((x)&0x3)<<0x4)
+#define MCF_DMA_TSKSZ1_SRCSZ14(x)            (((x)&0x3)<<0x6)
+#define MCF_DMA_TSKSZ1_DSTSZ13(x)            (((x)&0x3)<<0x8)
+#define MCF_DMA_TSKSZ1_SRCSZ13(x)            (((x)&0x3)<<0xA)
+#define MCF_DMA_TSKSZ1_DSTSZ12(x)            (((x)&0x3)<<0xC)
+#define MCF_DMA_TSKSZ1_SRCSZ12(x)            (((x)&0x3)<<0xE)
+#define MCF_DMA_TSKSZ1_DSTSZ11(x)            (((x)&0x3)<<0x10)
+#define MCF_DMA_TSKSZ1_SRCSZ11(x)            (((x)&0x3)<<0x12)
+#define MCF_DMA_TSKSZ1_DSTSZ10(x)            (((x)&0x3)<<0x14)
+#define MCF_DMA_TSKSZ1_SRCSZ10(x)            (((x)&0x3)<<0x16)
+#define MCF_DMA_TSKSZ1_DSTSZ9(x)             (((x)&0x3)<<0x18)
+#define MCF_DMA_TSKSZ1_SRCSZ9(x)             (((x)&0x3)<<0x1A)
+#define MCF_DMA_TSKSZ1_DSTSZ8(x)             (((x)&0x3)<<0x1C)
+#define MCF_DMA_TSKSZ1_SRCSZ8(x)             (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */
+#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */
+#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DBGCTL */
+#define MCF_DMA_DBGCTL_I                     (0x2)
+#define MCF_DMA_DBGCTL_E                     (0x4)
+#define MCF_DMA_DBGCTL_AND_OR                (0x80)
+#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x)  (((x)&0x7)<<0x8)
+#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x)  (((x)&0x7)<<0xB)
+#define MCF_DMA_DBGCTL_B                     (0x4000)
+#define MCF_DMA_DBGCTL_AA                    (0x8000)
+#define MCF_DMA_DBGCTL_BLOCK_TASKS(x)        (((x)&0xFFFF)<<0x10)
+
+
+#endif /* __MCF5475_DMA_H__ */
--- a/tos/jtagwait/include/MCF5475_DSPI.h
+++ b/tos/jtagwait/include/MCF5475_DSPI.h
@@ -0,0 +1,150 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_DSPI_H__
+#define __MCF5475_DSPI_H__
+
+
+/*********************************************************************
+*
+* DMA Serial Peripheral Interface (DSPI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DSPI_DMCR                        (*(volatile uint32_t*)(&_MBAR[0x8A00]))
+#define MCF_DSPI_DTCR                        (*(volatile uint32_t*)(&_MBAR[0x8A08]))
+#define MCF_DSPI_DCTAR0                      (*(volatile uint32_t*)(&_MBAR[0x8A0C]))
+#define MCF_DSPI_DCTAR1                      (*(volatile uint32_t*)(&_MBAR[0x8A10]))
+#define MCF_DSPI_DCTAR2                      (*(volatile uint32_t*)(&_MBAR[0x8A14]))
+#define MCF_DSPI_DCTAR3                      (*(volatile uint32_t*)(&_MBAR[0x8A18]))
+#define MCF_DSPI_DCTAR4                      (*(volatile uint32_t*)(&_MBAR[0x8A1C]))
+#define MCF_DSPI_DCTAR5                      (*(volatile uint32_t*)(&_MBAR[0x8A20]))
+#define MCF_DSPI_DCTAR6                      (*(volatile uint32_t*)(&_MBAR[0x8A24]))
+#define MCF_DSPI_DCTAR7                      (*(volatile uint32_t*)(&_MBAR[0x8A28]))
+#define MCF_DSPI_DSR                         (*(volatile uint32_t*)(&_MBAR[0x8A2C]))
+#define MCF_DSPI_DIRSR                       (*(volatile uint32_t*)(&_MBAR[0x8A30]))
+#define MCF_DSPI_DTFR                        (*(volatile uint32_t*)(&_MBAR[0x8A34]))
+#define MCF_DSPI_DRFR                        (*(volatile uint32_t*)(&_MBAR[0x8A38]))
+#define MCF_DSPI_DTFDR0                      (*(volatile uint32_t*)(&_MBAR[0x8A3C]))
+#define MCF_DSPI_DTFDR1                      (*(volatile uint32_t*)(&_MBAR[0x8A40]))
+#define MCF_DSPI_DTFDR2                      (*(volatile uint32_t*)(&_MBAR[0x8A44]))
+#define MCF_DSPI_DTFDR3                      (*(volatile uint32_t*)(&_MBAR[0x8A48]))
+#define MCF_DSPI_DRFDR0                      (*(volatile uint32_t*)(&_MBAR[0x8A7C]))
+#define MCF_DSPI_DRFDR1                      (*(volatile uint32_t*)(&_MBAR[0x8A80]))
+#define MCF_DSPI_DRFDR2                      (*(volatile uint32_t*)(&_MBAR[0x8A84]))
+#define MCF_DSPI_DRFDR3                      (*(volatile uint32_t*)(&_MBAR[0x8A88]))
+#define MCF_DSPI_DCTAR(x)                    (*(volatile uint32_t*)(&_MBAR[0x8A0C + ((x)*0x4)]))
+#define MCF_DSPI_DTFDR(x)                    (*(volatile uint32_t*)(&_MBAR[0x8A3C + ((x)*0x4)]))
+#define MCF_DSPI_DRFDR(x)                    (*(volatile uint32_t*)(&_MBAR[0x8A7C + ((x)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_DSPI_DMCR */
+#define MCF_DSPI_DMCR_HALT                   (0x1)
+#define MCF_DSPI_DMCR_SMPL_PT(x)             (((x)&0x3)<<0x8)
+#define MCF_DSPI_DMCR_SMPL_PT_0CLK           (0)
+#define MCF_DSPI_DMCR_SMPL_PT_1CLK           (0x100)
+#define MCF_DSPI_DMCR_SMPL_PT_2CLK           (0x200)
+#define MCF_DSPI_DMCR_CRXF                   (0x400)
+#define MCF_DSPI_DMCR_CTXF                   (0x800)
+#define MCF_DSPI_DMCR_DRXF                   (0x1000)
+#define MCF_DSPI_DMCR_DTXF                   (0x2000)
+#define MCF_DSPI_DMCR_CSIS0                  (0x10000)
+#define MCF_DSPI_DMCR_CSIS2                  (0x40000)
+#define MCF_DSPI_DMCR_CSIS3                  (0x80000)
+#define MCF_DSPI_DMCR_CSIS5                  (0x200000)
+#define MCF_DSPI_DMCR_ROOE                   (0x1000000)
+#define MCF_DSPI_DMCR_PCSSE                  (0x2000000)
+#define MCF_DSPI_DMCR_MTFE                   (0x4000000)
+#define MCF_DSPI_DMCR_FRZ                    (0x8000000)
+#define MCF_DSPI_DMCR_DCONF(x)               (((x)&0x3)<<0x1C)
+#define MCF_DSPI_DMCR_CSCK                   (0x40000000)
+#define MCF_DSPI_DMCR_MSTR                   (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DTCR */
+#define MCF_DSPI_DTCR_SPI_TCNT(x)            (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_DSPI_DCTAR */
+#define MCF_DSPI_DCTAR_BR(x)                 (((x)&0xF)<<0)
+#define MCF_DSPI_DCTAR_DT(x)                 (((x)&0xF)<<0x4)
+#define MCF_DSPI_DCTAR_ASC(x)                (((x)&0xF)<<0x8)
+#define MCF_DSPI_DCTAR_CSSCK(x)              (((x)&0xF)<<0xC)
+#define MCF_DSPI_DCTAR_PBR(x)                (((x)&0x3)<<0x10)
+#define MCF_DSPI_DCTAR_PBR_1CLK              (0)
+#define MCF_DSPI_DCTAR_PBR_3CLK              (0x10000)
+#define MCF_DSPI_DCTAR_PBR_5CLK              (0x20000)
+#define MCF_DSPI_DCTAR_PBR_7CLK              (0x30000)
+#define MCF_DSPI_DCTAR_PDT(x)                (((x)&0x3)<<0x12)
+#define MCF_DSPI_DCTAR_PDT_1CLK              (0)
+#define MCF_DSPI_DCTAR_PDT_3CLK              (0x40000)
+#define MCF_DSPI_DCTAR_PDT_5CLK              (0x80000)
+#define MCF_DSPI_DCTAR_PDT_7CLK              (0xC0000)
+#define MCF_DSPI_DCTAR_PASC(x)               (((x)&0x3)<<0x14)
+#define MCF_DSPI_DCTAR_PASC_1CLK             (0)
+#define MCF_DSPI_DCTAR_PASC_3CLK             (0x100000)
+#define MCF_DSPI_DCTAR_PASC_5CLK             (0x200000)
+#define MCF_DSPI_DCTAR_PASC_7CLK             (0x300000)
+#define MCF_DSPI_DCTAR_PCSSCK(x)             (((x)&0x3)<<0x16)
+#define MCF_DSPI_DCTAR_LSBFE                 (0x1000000)
+#define MCF_DSPI_DCTAR_CPHA                  (0x2000000)
+#define MCF_DSPI_DCTAR_CPOL                  (0x4000000)
+#define MCF_DSPI_DCTAR_TRSZ(x)               (((x)&0xF)<<0x1B)
+
+/* Bit definitions and macros for MCF_DSPI_DSR */
+#define MCF_DSPI_DSR_RXPTR(x)                (((x)&0xF)<<0)
+#define MCF_DSPI_DSR_RXCTR(x)                (((x)&0xF)<<0x4)
+#define MCF_DSPI_DSR_TXPTR(x)                (((x)&0xF)<<0x8)
+#define MCF_DSPI_DSR_TXCTR(x)                (((x)&0xF)<<0xC)
+#define MCF_DSPI_DSR_RFDF                    (0x20000)
+#define MCF_DSPI_DSR_RFOF                    (0x80000)
+#define MCF_DSPI_DSR_TFFF                    (0x2000000)
+#define MCF_DSPI_DSR_TFUF                    (0x8000000)
+#define MCF_DSPI_DSR_EOQF                    (0x10000000)
+#define MCF_DSPI_DSR_TXRXS                   (0x40000000)
+#define MCF_DSPI_DSR_TCF                     (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DIRSR */
+#define MCF_DSPI_DIRSR_RFDFS                 (0x10000)
+#define MCF_DSPI_DIRSR_RFDFE                 (0x20000)
+#define MCF_DSPI_DIRSR_RFOFE                 (0x80000)
+#define MCF_DSPI_DIRSR_TFFFS                 (0x1000000)
+#define MCF_DSPI_DIRSR_TFFFE                 (0x2000000)
+#define MCF_DSPI_DIRSR_TFUFE                 (0x8000000)
+#define MCF_DSPI_DIRSR_EOQFE                 (0x10000000)
+#define MCF_DSPI_DIRSR_TCFE                  (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DTFR */
+#define MCF_DSPI_DTFR_TXDATA(x)              (((x)&0xFFFF)<<0)
+#define MCF_DSPI_DTFR_CS0                    (0x10000)
+#define MCF_DSPI_DTFR_CS2                    (0x40000)
+#define MCF_DSPI_DTFR_CS3                    (0x80000)
+#define MCF_DSPI_DTFR_CS5                    (0x200000)
+#define MCF_DSPI_DTFR_CTCNT                  (0x4000000)
+#define MCF_DSPI_DTFR_EOQ                    (0x8000000)
+#define MCF_DSPI_DTFR_CTAS(x)                (((x)&0x7)<<0x1C)
+#define MCF_DSPI_DTFR_CONT                   (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DRFR */
+#define MCF_DSPI_DRFR_RXDATA(x)              (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DSPI_DTFDR */
+#define MCF_DSPI_DTFDR_TXDATA(x)             (((x)&0xFFFF)<<0)
+#define MCF_DSPI_DTFDR_TXCMD(x)              (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_DSPI_DRFDR */
+#define MCF_DSPI_DRFDR_RXDATA(x)             (((x)&0xFFFF)<<0)
+
+
+#endif /* __MCF5475_DSPI_H__ */
--- a/tos/jtagwait/include/MCF5475_EPORT.h
+++ b/tos/jtagwait/include/MCF5475_EPORT.h
@@ -0,0 +1,123 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_EPORT_H__
+#define __MCF5475_EPORT_H__
+
+
+/*********************************************************************
+*
+* Edge Port Module (EPORT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_EPORT_EPPAR                      (*(volatile uint16_t*)(&_MBAR[0xF00]))
+#define MCF_EPORT_EPDDR                      (*(volatile uint8_t *)(&_MBAR[0xF04]))
+#define MCF_EPORT_EPIER                      (*(volatile uint8_t *)(&_MBAR[0xF05]))
+#define MCF_EPORT_EPDR                       (*(volatile uint8_t *)(&_MBAR[0xF08]))
+#define MCF_EPORT_EPPDR                      (*(volatile uint8_t *)(&_MBAR[0xF09]))
+#define MCF_EPORT_EPFR                       (*(volatile uint8_t *)(&_MBAR[0xF0C]))
+
+
+
+/* Bit definitions and macros for MCF_EPORT_EPPAR */
+#define MCF_EPORT_EPPAR_EPPA1(x)             (((x)&0x3)<<0x2)
+#define MCF_EPORT_EPPAR_EPPA1_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA1_RISING         (0x4)
+#define MCF_EPORT_EPPAR_EPPA1_FALLING        (0x8)
+#define MCF_EPORT_EPPAR_EPPA1_BOTH           (0xC)
+#define MCF_EPORT_EPPAR_EPPA2(x)             (((x)&0x3)<<0x4)
+#define MCF_EPORT_EPPAR_EPPA2_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA2_RISING         (0x10)
+#define MCF_EPORT_EPPAR_EPPA2_FALLING        (0x20)
+#define MCF_EPORT_EPPAR_EPPA2_BOTH           (0x30)
+#define MCF_EPORT_EPPAR_EPPA3(x)             (((x)&0x3)<<0x6)
+#define MCF_EPORT_EPPAR_EPPA3_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA3_RISING         (0x40)
+#define MCF_EPORT_EPPAR_EPPA3_FALLING        (0x80)
+#define MCF_EPORT_EPPAR_EPPA3_BOTH           (0xC0)
+#define MCF_EPORT_EPPAR_EPPA4(x)             (((x)&0x3)<<0x8)
+#define MCF_EPORT_EPPAR_EPPA4_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA4_RISING         (0x100)
+#define MCF_EPORT_EPPAR_EPPA4_FALLING        (0x200)
+#define MCF_EPORT_EPPAR_EPPA4_BOTH           (0x300)
+#define MCF_EPORT_EPPAR_EPPA5(x)             (((x)&0x3)<<0xA)
+#define MCF_EPORT_EPPAR_EPPA5_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA5_RISING         (0x400)
+#define MCF_EPORT_EPPAR_EPPA5_FALLING        (0x800)
+#define MCF_EPORT_EPPAR_EPPA5_BOTH           (0xC00)
+#define MCF_EPORT_EPPAR_EPPA6(x)             (((x)&0x3)<<0xC)
+#define MCF_EPORT_EPPAR_EPPA6_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA6_RISING         (0x1000)
+#define MCF_EPORT_EPPAR_EPPA6_FALLING        (0x2000)
+#define MCF_EPORT_EPPAR_EPPA6_BOTH           (0x3000)
+#define MCF_EPORT_EPPAR_EPPA7(x)             (((x)&0x3)<<0xE)
+#define MCF_EPORT_EPPAR_EPPA7_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA7_RISING         (0x4000)
+#define MCF_EPORT_EPPAR_EPPA7_FALLING        (0x8000)
+#define MCF_EPORT_EPPAR_EPPA7_BOTH           (0xC000)
+#define MCF_EPORT_EPPAR_LEVEL                (0)
+#define MCF_EPORT_EPPAR_RISING               (0x1)
+#define MCF_EPORT_EPPAR_FALLING              (0x2)
+#define MCF_EPORT_EPPAR_BOTH                 (0x3)
+
+/* Bit definitions and macros for MCF_EPORT_EPDDR */
+#define MCF_EPORT_EPDDR_EPDD1                (0x2)
+#define MCF_EPORT_EPDDR_EPDD2                (0x4)
+#define MCF_EPORT_EPDDR_EPDD3                (0x8)
+#define MCF_EPORT_EPDDR_EPDD4                (0x10)
+#define MCF_EPORT_EPDDR_EPDD5                (0x20)
+#define MCF_EPORT_EPDDR_EPDD6                (0x40)
+#define MCF_EPORT_EPDDR_EPDD7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPIER */
+#define MCF_EPORT_EPIER_EPIE1                (0x2)
+#define MCF_EPORT_EPIER_EPIE2                (0x4)
+#define MCF_EPORT_EPIER_EPIE3                (0x8)
+#define MCF_EPORT_EPIER_EPIE4                (0x10)
+#define MCF_EPORT_EPIER_EPIE5                (0x20)
+#define MCF_EPORT_EPIER_EPIE6                (0x40)
+#define MCF_EPORT_EPIER_EPIE7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPDR */
+#define MCF_EPORT_EPDR_EPD1                  (0x2)
+#define MCF_EPORT_EPDR_EPD2                  (0x4)
+#define MCF_EPORT_EPDR_EPD3                  (0x8)
+#define MCF_EPORT_EPDR_EPD4                  (0x10)
+#define MCF_EPORT_EPDR_EPD5                  (0x20)
+#define MCF_EPORT_EPDR_EPD6                  (0x40)
+#define MCF_EPORT_EPDR_EPD7                  (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPPDR */
+#define MCF_EPORT_EPPDR_EPPD1                (0x2)
+#define MCF_EPORT_EPPDR_EPPD2                (0x4)
+#define MCF_EPORT_EPPDR_EPPD3                (0x8)
+#define MCF_EPORT_EPPDR_EPPD4                (0x10)
+#define MCF_EPORT_EPPDR_EPPD5                (0x20)
+#define MCF_EPORT_EPPDR_EPPD6                (0x40)
+#define MCF_EPORT_EPPDR_EPPD7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPFR */
+#define MCF_EPORT_EPFR_EPF1                  (0x2)
+#define MCF_EPORT_EPFR_EPF2                  (0x4)
+#define MCF_EPORT_EPFR_EPF3                  (0x8)
+#define MCF_EPORT_EPFR_EPF4                  (0x10)
+#define MCF_EPORT_EPFR_EPF5                  (0x20)
+#define MCF_EPORT_EPFR_EPF6                  (0x40)
+#define MCF_EPORT_EPFR_EPF7                  (0x80)
+
+
+#endif /* __MCF5475_EPORT_H__ */
--- a/tos/jtagwait/include/MCF5475_FBCS.h
+++ b/tos/jtagwait/include/MCF5475_FBCS.h
@@ -0,0 +1,100 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_FBCS_H__
+#define __MCF5475_FBCS_H__
+
+
+/*********************************************************************
+*
+* FlexBus Chip Select Module (FBCS)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FBCS0_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x500]))
+#define MCF_FBCS0_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x504]))
+#define MCF_FBCS0_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x508]))
+
+#define MCF_FBCS1_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x50C]))
+#define MCF_FBCS1_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x510]))
+#define MCF_FBCS1_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x514]))
+
+#define MCF_FBCS2_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x518]))
+#define MCF_FBCS2_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x51C]))
+#define MCF_FBCS2_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x520]))
+
+#define MCF_FBCS3_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x524]))
+#define MCF_FBCS3_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x528]))
+#define MCF_FBCS3_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x52C]))
+
+#define MCF_FBCS4_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x530]))
+#define MCF_FBCS4_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x534]))
+#define MCF_FBCS4_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x538]))
+
+#define MCF_FBCS5_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x53C]))
+#define MCF_FBCS5_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x540]))
+#define MCF_FBCS5_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x544]))
+
+#define MCF_FBCS_CSAR(x)                     (*(volatile uint32_t*)(&_MBAR[0x500 + ((x)*0xC)]))
+#define MCF_FBCS_CSMR(x)                     (*(volatile uint32_t*)(&_MBAR[0x504 + ((x)*0xC)]))
+#define MCF_FBCS_CSCR(x)                     (*(volatile uint32_t*)(&_MBAR[0x508 + ((x)*0xC)]))
+
+
+/* Bit definitions and macros for MCF_FBCS_CSAR */
+#define MCF_FBCS_CSAR_BA(x)                  ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for MCF_FBCS_CSMR */
+#define MCF_FBCS_CSMR_V                      (0x1)
+#define MCF_FBCS_CSMR_WP                     (0x100)
+#define MCF_FBCS_CSMR_BAM(x)                 (((x)&0xFFFF)<<0x10)
+#define MCF_FBCS_CSMR_BAM_4G                 (0xFFFF0000)
+#define MCF_FBCS_CSMR_BAM_2G                 (0x7FFF0000)
+#define MCF_FBCS_CSMR_BAM_1G                 (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_1024M              (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_512M               (0x1FFF0000)
+#define MCF_FBCS_CSMR_BAM_256M               (0xFFF0000)
+#define MCF_FBCS_CSMR_BAM_128M               (0x7FF0000)
+#define MCF_FBCS_CSMR_BAM_64M                (0x3FF0000)
+#define MCF_FBCS_CSMR_BAM_32M                (0x1FF0000)
+#define MCF_FBCS_CSMR_BAM_16M                (0xFF0000)
+#define MCF_FBCS_CSMR_BAM_8M                 (0x7F0000)
+#define MCF_FBCS_CSMR_BAM_4M                 (0x3F0000)
+#define MCF_FBCS_CSMR_BAM_2M                 (0x1F0000)
+#define MCF_FBCS_CSMR_BAM_1M                 (0xF0000)
+#define MCF_FBCS_CSMR_BAM_1024K              (0xF0000)
+#define MCF_FBCS_CSMR_BAM_512K               (0x70000)
+#define MCF_FBCS_CSMR_BAM_256K               (0x30000)
+#define MCF_FBCS_CSMR_BAM_128K               (0x10000)
+#define MCF_FBCS_CSMR_BAM_64K                (0)
+
+/* Bit definitions and macros for MCF_FBCS_CSCR */
+#define MCF_FBCS_CSCR_BSTW                   (0x8)
+#define MCF_FBCS_CSCR_BSTR                   (0x10)
+#define MCF_FBCS_CSCR_BEM                    (0x20)
+#define MCF_FBCS_CSCR_PS(x)                  (((x)&0x3)<<0x6)
+#define MCF_FBCS_CSCR_PS_32                  (0)
+#define MCF_FBCS_CSCR_PS_8                   (0x40)
+#define MCF_FBCS_CSCR_PS_16                  (0x80)
+#define MCF_FBCS_CSCR_AA                     (0x100)
+#define MCF_FBCS_CSCR_WS(x)                  (((x)&0x3F)<<0xA)
+#define MCF_FBCS_CSCR_WRAH(x)                (((x)&0x3)<<0x10)
+#define MCF_FBCS_CSCR_RDAH(x)                (((x)&0x3)<<0x12)
+#define MCF_FBCS_CSCR_ASET(x)                (((x)&0x3)<<0x14)
+#define MCF_FBCS_CSCR_SWSEN                  (0x800000)
+#define MCF_FBCS_CSCR_SWS(x)                 (((x)&0x3F)<<0x1A)
+
+
+#endif /* __MCF5475_FBCS_H__ */
--- a/tos/jtagwait/include/MCF5475_FEC.h
+++ b/tos/jtagwait/include/MCF5475_FEC.h
@@ -0,0 +1,680 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_FEC_H__
+#define __MCF5475_FEC_H__
+
+
+/*********************************************************************
+*
+* Fast Ethernet Controller(FEC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FEC0_EIR                         (*(volatile uint32_t*)(&_MBAR[0x9004]))
+#define MCF_FEC0_EIMR                        (*(volatile uint32_t*)(&_MBAR[0x9008]))
+#define MCF_FEC0_ECR                         (*(volatile uint32_t*)(&_MBAR[0x9024]))
+#define MCF_FEC0_MMFR                        (*(volatile uint32_t*)(&_MBAR[0x9040]))
+#define MCF_FEC0_MSCR                        (*(volatile uint32_t*)(&_MBAR[0x9044]))
+#define MCF_FEC0_MIBC                        (*(volatile uint32_t*)(&_MBAR[0x9064]))
+#define MCF_FEC0_RCR                         (*(volatile uint32_t*)(&_MBAR[0x9084]))
+#define MCF_FEC0_RHR                         (*(volatile uint32_t*)(&_MBAR[0x9088]))
+#define MCF_FEC0_TCR                         (*(volatile uint32_t*)(&_MBAR[0x90C4]))
+#define MCF_FEC0_PALR                        (*(volatile uint32_t*)(&_MBAR[0x90E4]))
+#define MCF_FEC0_PAHR                        (*(volatile uint32_t*)(&_MBAR[0x90E8]))
+#define MCF_FEC0_OPD                         (*(volatile uint32_t*)(&_MBAR[0x90EC]))
+#define MCF_FEC0_IAUR                        (*(volatile uint32_t*)(&_MBAR[0x9118]))
+#define MCF_FEC0_IALR                        (*(volatile uint32_t*)(&_MBAR[0x911C]))
+#define MCF_FEC0_GAUR                        (*(volatile uint32_t*)(&_MBAR[0x9120]))
+#define MCF_FEC0_GALR                        (*(volatile uint32_t*)(&_MBAR[0x9124]))
+#define MCF_FEC0_FECTFWR                     (*(volatile uint32_t*)(&_MBAR[0x9144]))
+#define MCF_FEC0_FECRFDR                     (*(volatile uint32_t*)(&_MBAR[0x9184]))
+#define MCF_FEC0_FECRFSR                     (*(volatile uint32_t*)(&_MBAR[0x9188]))
+#define MCF_FEC0_FECRFCR                     (*(volatile uint32_t*)(&_MBAR[0x918C]))
+#define MCF_FEC0_FECRLRFP                    (*(volatile uint32_t*)(&_MBAR[0x9190]))
+#define MCF_FEC0_FECRLWFP                    (*(volatile uint32_t*)(&_MBAR[0x9194]))
+#define MCF_FEC0_FECRFAR                     (*(volatile uint32_t*)(&_MBAR[0x9198]))
+#define MCF_FEC0_FECRFRP                     (*(volatile uint32_t*)(&_MBAR[0x919C]))
+#define MCF_FEC0_FECRFWP                     (*(volatile uint32_t*)(&_MBAR[0x91A0]))
+#define MCF_FEC0_FECTFDR                     (*(volatile uint32_t*)(&_MBAR[0x91A4]))
+#define MCF_FEC0_FECTFSR                     (*(volatile uint32_t*)(&_MBAR[0x91A8]))
+#define MCF_FEC0_FECTFCR                     (*(volatile uint32_t*)(&_MBAR[0x91AC]))
+#define MCF_FEC0_FECTLRFP                    (*(volatile uint32_t*)(&_MBAR[0x91B0]))
+#define MCF_FEC0_FECTLWFP                    (*(volatile uint32_t*)(&_MBAR[0x91B4]))
+#define MCF_FEC0_FECTFAR                     (*(volatile uint32_t*)(&_MBAR[0x91B8]))
+#define MCF_FEC0_FECTFRP                     (*(volatile uint32_t*)(&_MBAR[0x91BC]))
+#define MCF_FEC0_FECTFWP                     (*(volatile uint32_t*)(&_MBAR[0x91C0]))
+#define MCF_FEC0_FECFRST                     (*(volatile uint32_t*)(&_MBAR[0x91C4]))
+#define MCF_FEC0_FECCTCWR                    (*(volatile uint32_t*)(&_MBAR[0x91C8]))
+#define MCF_FEC0_RMON_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9200]))
+#define MCF_FEC0_RMON_T_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9204]))
+#define MCF_FEC0_RMON_T_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9208]))
+#define MCF_FEC0_RMON_T_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x920C]))
+#define MCF_FEC0_RMON_T_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9210]))
+#define MCF_FEC0_RMON_T_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9214]))
+#define MCF_FEC0_RMON_T_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9218]))
+#define MCF_FEC0_RMON_T_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x921C]))
+#define MCF_FEC0_RMON_T_JAB                  (*(volatile uint32_t*)(&_MBAR[0x9220]))
+#define MCF_FEC0_RMON_T_COL                  (*(volatile uint32_t*)(&_MBAR[0x9224]))
+#define MCF_FEC0_RMON_T_P64                  (*(volatile uint32_t*)(&_MBAR[0x9228]))
+#define MCF_FEC0_RMON_T_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x922C]))
+#define MCF_FEC0_RMON_T_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x9230]))
+#define MCF_FEC0_RMON_T_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x9234]))
+#define MCF_FEC0_RMON_T_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x9238]))
+#define MCF_FEC0_RMON_T_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x923C]))
+#define MCF_FEC0_RMON_T_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x9240]))
+#define MCF_FEC0_RMON_T_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x9244]))
+#define MCF_FEC0_IEEE_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9248]))
+#define MCF_FEC0_IEEE_T_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x924C]))
+#define MCF_FEC0_IEEE_T_1COL                 (*(volatile uint32_t*)(&_MBAR[0x9250]))
+#define MCF_FEC0_IEEE_T_MCOL                 (*(volatile uint32_t*)(&_MBAR[0x9254]))
+#define MCF_FEC0_IEEE_T_DEF                  (*(volatile uint32_t*)(&_MBAR[0x9258]))
+#define MCF_FEC0_IEEE_T_LCOL                 (*(volatile uint32_t*)(&_MBAR[0x925C]))
+#define MCF_FEC0_IEEE_T_EXCOL                (*(volatile uint32_t*)(&_MBAR[0x9260]))
+#define MCF_FEC0_IEEE_T_MACERR               (*(volatile uint32_t*)(&_MBAR[0x9264]))
+#define MCF_FEC0_IEEE_T_CSERR                (*(volatile uint32_t*)(&_MBAR[0x9268]))
+#define MCF_FEC0_IEEE_T_SQE                  (*(volatile uint32_t*)(&_MBAR[0x926C]))
+#define MCF_FEC0_IEEE_T_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x9270]))
+#define MCF_FEC0_IEEE_T_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x9274]))
+#define MCF_FEC0_RMON_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9280]))
+#define MCF_FEC0_RMON_R_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9284]))
+#define MCF_FEC0_RMON_R_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9288]))
+#define MCF_FEC0_RMON_R_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x928C]))
+#define MCF_FEC0_RMON_R_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9290]))
+#define MCF_FEC0_RMON_R_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9294]))
+#define MCF_FEC0_RMON_R_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9298]))
+#define MCF_FEC0_RMON_R_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x929C]))
+#define MCF_FEC0_RMON_R_JAB                  (*(volatile uint32_t*)(&_MBAR[0x92A0]))
+#define MCF_FEC0_RMON_R_RESVD_0              (*(volatile uint32_t*)(&_MBAR[0x92A4]))
+#define MCF_FEC0_RMON_R_P64                  (*(volatile uint32_t*)(&_MBAR[0x92A8]))
+#define MCF_FEC0_RMON_R_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x92AC]))
+#define MCF_FEC0_RMON_R_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x92B0]))
+#define MCF_FEC0_RMON_R_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x92B4]))
+#define MCF_FEC0_RMON_R_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x92B8]))
+#define MCF_FEC0_RMON_R_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x92BC]))
+#define MCF_FEC0_RMON_R_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x92C0]))
+#define MCF_FEC0_RMON_R_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x92C4]))
+#define MCF_FEC0_IEEE_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x92C8]))
+#define MCF_FEC0_IEEE_R_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x92CC]))
+#define MCF_FEC0_IEEE_R_CRC                  (*(volatile uint32_t*)(&_MBAR[0x92D0]))
+#define MCF_FEC0_IEEE_R_ALIGN                (*(volatile uint32_t*)(&_MBAR[0x92D4]))
+#define MCF_FEC0_IEEE_R_MACERR               (*(volatile uint32_t*)(&_MBAR[0x92D8]))
+#define MCF_FEC0_IEEE_R_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x92DC]))
+#define MCF_FEC0_IEEE_R_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x92E0]))
+
+#define MCF_FEC1_EIR                         (*(volatile uint32_t*)(&_MBAR[0x9804]))
+#define MCF_FEC1_EIMR                        (*(volatile uint32_t*)(&_MBAR[0x9808]))
+#define MCF_FEC1_ECR                         (*(volatile uint32_t*)(&_MBAR[0x9824]))
+#define MCF_FEC1_MMFR                        (*(volatile uint32_t*)(&_MBAR[0x9840]))
+#define MCF_FEC1_MSCR                        (*(volatile uint32_t*)(&_MBAR[0x9844]))
+#define MCF_FEC1_MIBC                        (*(volatile uint32_t*)(&_MBAR[0x9864]))
+#define MCF_FEC1_RCR                         (*(volatile uint32_t*)(&_MBAR[0x9884]))
+#define MCF_FEC1_RHR                         (*(volatile uint32_t*)(&_MBAR[0x9888]))
+#define MCF_FEC1_TCR                         (*(volatile uint32_t*)(&_MBAR[0x98C4]))
+#define MCF_FEC1_PALR                        (*(volatile uint32_t*)(&_MBAR[0x98E4]))
+#define MCF_FEC1_PAHR                        (*(volatile uint32_t*)(&_MBAR[0x98E8]))
+#define MCF_FEC1_OPD                         (*(volatile uint32_t*)(&_MBAR[0x98EC]))
+#define MCF_FEC1_IAUR                        (*(volatile uint32_t*)(&_MBAR[0x9918]))
+#define MCF_FEC1_IALR                        (*(volatile uint32_t*)(&_MBAR[0x991C]))
+#define MCF_FEC1_GAUR                        (*(volatile uint32_t*)(&_MBAR[0x9920]))
+#define MCF_FEC1_GALR                        (*(volatile uint32_t*)(&_MBAR[0x9924]))
+#define MCF_FEC1_FECTFWR                     (*(volatile uint32_t*)(&_MBAR[0x9944]))
+#define MCF_FEC1_FECRFDR                     (*(volatile uint32_t*)(&_MBAR[0x9984]))
+#define MCF_FEC1_FECRFSR                     (*(volatile uint32_t*)(&_MBAR[0x9988]))
+#define MCF_FEC1_FECRFCR                     (*(volatile uint32_t*)(&_MBAR[0x998C]))
+#define MCF_FEC1_FECRLRFP                    (*(volatile uint32_t*)(&_MBAR[0x9990]))
+#define MCF_FEC1_FECRLWFP                    (*(volatile uint32_t*)(&_MBAR[0x9994]))
+#define MCF_FEC1_FECRFAR                     (*(volatile uint32_t*)(&_MBAR[0x9998]))
+#define MCF_FEC1_FECRFRP                     (*(volatile uint32_t*)(&_MBAR[0x999C]))
+#define MCF_FEC1_FECRFWP                     (*(volatile uint32_t*)(&_MBAR[0x99A0]))
+#define MCF_FEC1_FECTFDR                     (*(volatile uint32_t*)(&_MBAR[0x99A4]))
+#define MCF_FEC1_FECTFSR                     (*(volatile uint32_t*)(&_MBAR[0x99A8]))
+#define MCF_FEC1_FECTFCR                     (*(volatile uint32_t*)(&_MBAR[0x99AC]))
+#define MCF_FEC1_FECTLRFP                    (*(volatile uint32_t*)(&_MBAR[0x99B0]))
+#define MCF_FEC1_FECTLWFP                    (*(volatile uint32_t*)(&_MBAR[0x99B4]))
+#define MCF_FEC1_FECTFAR                     (*(volatile uint32_t*)(&_MBAR[0x99B8]))
+#define MCF_FEC1_FECTFRP                     (*(volatile uint32_t*)(&_MBAR[0x99BC]))
+#define MCF_FEC1_FECTFWP                     (*(volatile uint32_t*)(&_MBAR[0x99C0]))
+#define MCF_FEC1_FECFRST                     (*(volatile uint32_t*)(&_MBAR[0x99C4]))
+#define MCF_FEC1_FECCTCWR                    (*(volatile uint32_t*)(&_MBAR[0x99C8]))
+#define MCF_FEC1_RMON_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9A00]))
+#define MCF_FEC1_RMON_T_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9A04]))
+#define MCF_FEC1_RMON_T_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A08]))
+#define MCF_FEC1_RMON_T_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A0C]))
+#define MCF_FEC1_RMON_T_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9A10]))
+#define MCF_FEC1_RMON_T_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9A14]))
+#define MCF_FEC1_RMON_T_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9A18]))
+#define MCF_FEC1_RMON_T_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x9A1C]))
+#define MCF_FEC1_RMON_T_JAB                  (*(volatile uint32_t*)(&_MBAR[0x9A20]))
+#define MCF_FEC1_RMON_T_COL                  (*(volatile uint32_t*)(&_MBAR[0x9A24]))
+#define MCF_FEC1_RMON_T_P64                  (*(volatile uint32_t*)(&_MBAR[0x9A28]))
+#define MCF_FEC1_RMON_T_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x9A2C]))
+#define MCF_FEC1_RMON_T_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x9A30]))
+#define MCF_FEC1_RMON_T_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x9A34]))
+#define MCF_FEC1_RMON_T_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x9A38]))
+#define MCF_FEC1_RMON_T_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x9A3C]))
+#define MCF_FEC1_RMON_T_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x9A40]))
+#define MCF_FEC1_RMON_T_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x9A44]))
+#define MCF_FEC1_IEEE_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9A48]))
+#define MCF_FEC1_IEEE_T_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x9A4C]))
+#define MCF_FEC1_IEEE_T_1COL                 (*(volatile uint32_t*)(&_MBAR[0x9A50]))
+#define MCF_FEC1_IEEE_T_MCOL                 (*(volatile uint32_t*)(&_MBAR[0x9A54]))
+#define MCF_FEC1_IEEE_T_DEF                  (*(volatile uint32_t*)(&_MBAR[0x9A58]))
+#define MCF_FEC1_IEEE_T_LCOL                 (*(volatile uint32_t*)(&_MBAR[0x9A5C]))
+#define MCF_FEC1_IEEE_T_EXCOL                (*(volatile uint32_t*)(&_MBAR[0x9A60]))
+#define MCF_FEC1_IEEE_T_MACERR               (*(volatile uint32_t*)(&_MBAR[0x9A64]))
+#define MCF_FEC1_IEEE_T_CSERR                (*(volatile uint32_t*)(&_MBAR[0x9A68]))
+#define MCF_FEC1_IEEE_T_SQE                  (*(volatile uint32_t*)(&_MBAR[0x9A6C]))
+#define MCF_FEC1_IEEE_T_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x9A70]))
+#define MCF_FEC1_IEEE_T_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x9A74]))
+#define MCF_FEC1_RMON_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9A80]))
+#define MCF_FEC1_RMON_R_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9A84]))
+#define MCF_FEC1_RMON_R_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A88]))
+#define MCF_FEC1_RMON_R_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A8C]))
+#define MCF_FEC1_RMON_R_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9A90]))
+#define MCF_FEC1_RMON_R_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9A94]))
+#define MCF_FEC1_RMON_R_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9A98]))
+#define MCF_FEC1_RMON_R_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x9A9C]))
+#define MCF_FEC1_RMON_R_JAB                  (*(volatile uint32_t*)(&_MBAR[0x9AA0]))
+#define MCF_FEC1_RMON_R_RESVD_0              (*(volatile uint32_t*)(&_MBAR[0x9AA4]))
+#define MCF_FEC1_RMON_R_P64                  (*(volatile uint32_t*)(&_MBAR[0x9AA8]))
+#define MCF_FEC1_RMON_R_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x9AAC]))
+#define MCF_FEC1_RMON_R_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x9AB0]))
+#define MCF_FEC1_RMON_R_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x9AB4]))
+#define MCF_FEC1_RMON_R_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x9AB8]))
+#define MCF_FEC1_RMON_R_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x9ABC]))
+#define MCF_FEC1_RMON_R_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x9AC0]))
+#define MCF_FEC1_RMON_R_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x9AC4]))
+#define MCF_FEC1_IEEE_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9AC8]))
+#define MCF_FEC1_IEEE_R_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x9ACC]))
+#define MCF_FEC1_IEEE_R_CRC                  (*(volatile uint32_t*)(&_MBAR[0x9AD0]))
+#define MCF_FEC1_IEEE_R_ALIGN                (*(volatile uint32_t*)(&_MBAR[0x9AD4]))
+#define MCF_FEC1_IEEE_R_MACERR               (*(volatile uint32_t*)(&_MBAR[0x9AD8]))
+#define MCF_FEC1_IEEE_R_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x9ADC]))
+#define MCF_FEC1_IEEE_R_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x9AE0]))
+
+#define MCF_FEC_EIR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9004 + ((x)*0x800)]))
+#define MCF_FEC_EIMR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9008 + ((x)*0x800)]))
+#define MCF_FEC_ECR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9024 + ((x)*0x800)]))
+#define MCF_FEC_MMFR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9040 + ((x)*0x800)]))
+#define MCF_FEC_MSCR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9044 + ((x)*0x800)]))
+#define MCF_FEC_MIBC(x)                      (*(volatile uint32_t*)(&_MBAR[0x9064 + ((x)*0x800)]))
+#define MCF_FEC_RCR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9084 + ((x)*0x800)]))
+#define MCF_FEC_RHR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9088 + ((x)*0x800)]))
+#define MCF_FEC_TCR(x)                       (*(volatile uint32_t*)(&_MBAR[0x90C4 + ((x)*0x800)]))
+#define MCF_FEC_PALR(x)                      (*(volatile uint32_t*)(&_MBAR[0x90E4 + ((x)*0x800)]))
+#define MCF_FEC_PAHR(x)                      (*(volatile uint32_t*)(&_MBAR[0x90E8 + ((x)*0x800)]))
+#define MCF_FEC_OPD(x)                       (*(volatile uint32_t*)(&_MBAR[0x90EC + ((x)*0x800)]))
+#define MCF_FEC_IAUR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9118 + ((x)*0x800)]))
+#define MCF_FEC_IALR(x)                      (*(volatile uint32_t*)(&_MBAR[0x911C + ((x)*0x800)]))
+#define MCF_FEC_GAUR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9120 + ((x)*0x800)]))
+#define MCF_FEC_GALR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9124 + ((x)*0x800)]))
+#define MCF_FEC_FECTFWR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9144 + ((x)*0x800)]))
+#define MCF_FEC_FECRFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9184 + ((x)*0x800)]))
+#define MCF_FEC_FECRFSR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9188 + ((x)*0x800)]))
+#define MCF_FEC_FECRFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x918C + ((x)*0x800)]))
+#define MCF_FEC_FECRLRFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x9190 + ((x)*0x800)]))
+#define MCF_FEC_FECRLWFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x9194 + ((x)*0x800)]))
+#define MCF_FEC_FECRFAR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9198 + ((x)*0x800)]))
+#define MCF_FEC_FECRFRP(x)                   (*(volatile uint32_t*)(&_MBAR[0x919C + ((x)*0x800)]))
+#define MCF_FEC_FECRFWP(x)                   (*(volatile uint32_t*)(&_MBAR[0x91A0 + ((x)*0x800)]))
+#define MCF_FEC_FECTFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91A4 + ((x)*0x800)]))
+#define MCF_FEC_FECTFSR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91A8 + ((x)*0x800)]))
+#define MCF_FEC_FECTFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91AC + ((x)*0x800)]))
+#define MCF_FEC_FECTLRFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x91B0 + ((x)*0x800)]))
+#define MCF_FEC_FECTLWFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x91B4 + ((x)*0x800)]))
+#define MCF_FEC_FECTFAR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91B8 + ((x)*0x800)]))
+#define MCF_FEC_FECTFRP(x)                   (*(volatile uint32_t*)(&_MBAR[0x91BC + ((x)*0x800)]))
+#define MCF_FEC_FECTFWP(x)                   (*(volatile uint32_t*)(&_MBAR[0x91C0 + ((x)*0x800)]))
+#define MCF_FEC_FECFRST(x)                   (*(volatile uint32_t*)(&_MBAR[0x91C4 + ((x)*0x800)]))
+#define MCF_FEC_FECCTCWR(x)                  (*(volatile uint32_t*)(&_MBAR[0x91C8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x9200 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_PACKETS(x)            (*(volatile uint32_t*)(&_MBAR[0x9204 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_BC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x9208 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_MC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x920C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_CRC_ALIGN(x)          (*(volatile uint32_t*)(&_MBAR[0x9210 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_UNDERSIZE(x)          (*(volatile uint32_t*)(&_MBAR[0x9214 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_OVERSIZE(x)           (*(volatile uint32_t*)(&_MBAR[0x9218 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_FRAG(x)               (*(volatile uint32_t*)(&_MBAR[0x921C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_JAB(x)                (*(volatile uint32_t*)(&_MBAR[0x9220 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_COL(x)                (*(volatile uint32_t*)(&_MBAR[0x9224 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P64(x)                (*(volatile uint32_t*)(&_MBAR[0x9228 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P65TO127(x)           (*(volatile uint32_t*)(&_MBAR[0x922C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P128TO255(x)          (*(volatile uint32_t*)(&_MBAR[0x9230 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P256TO511(x)          (*(volatile uint32_t*)(&_MBAR[0x9234 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P512TO1023(x)         (*(volatile uint32_t*)(&_MBAR[0x9238 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P1024TO2047(x)        (*(volatile uint32_t*)(&_MBAR[0x923C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P_GTE2048(x)          (*(volatile uint32_t*)(&_MBAR[0x9240 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_OCTETS(x)             (*(volatile uint32_t*)(&_MBAR[0x9244 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x9248 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_FRAME_OK(x)           (*(volatile uint32_t*)(&_MBAR[0x924C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_1COL(x)               (*(volatile uint32_t*)(&_MBAR[0x9250 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_MCOL(x)               (*(volatile uint32_t*)(&_MBAR[0x9254 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_DEF(x)                (*(volatile uint32_t*)(&_MBAR[0x9258 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_LCOL(x)               (*(volatile uint32_t*)(&_MBAR[0x925C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_EXCOL(x)              (*(volatile uint32_t*)(&_MBAR[0x9260 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_MACERR(x)             (*(volatile uint32_t*)(&_MBAR[0x9264 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_CSERR(x)              (*(volatile uint32_t*)(&_MBAR[0x9268 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_SQE(x)                (*(volatile uint32_t*)(&_MBAR[0x926C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_FDXFC(x)              (*(volatile uint32_t*)(&_MBAR[0x9270 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_OCTETS_OK(x)          (*(volatile uint32_t*)(&_MBAR[0x9274 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x9280 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_PACKETS(x)            (*(volatile uint32_t*)(&_MBAR[0x9284 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_BC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x9288 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_MC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x928C + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_CRC_ALIGN(x)          (*(volatile uint32_t*)(&_MBAR[0x9290 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_UNDERSIZE(x)          (*(volatile uint32_t*)(&_MBAR[0x9294 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_OVERSIZE(x)           (*(volatile uint32_t*)(&_MBAR[0x9298 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_FRAG(x)               (*(volatile uint32_t*)(&_MBAR[0x929C + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_JAB(x)                (*(volatile uint32_t*)(&_MBAR[0x92A0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_RESVD_0(x)            (*(volatile uint32_t*)(&_MBAR[0x92A4 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P64(x)                (*(volatile uint32_t*)(&_MBAR[0x92A8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P65TO127(x)           (*(volatile uint32_t*)(&_MBAR[0x92AC + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P128TO255(x)          (*(volatile uint32_t*)(&_MBAR[0x92B0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P256TO511(x)          (*(volatile uint32_t*)(&_MBAR[0x92B4 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P512TO1023(x)         (*(volatile uint32_t*)(&_MBAR[0x92B8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P1024TO2047(x)        (*(volatile uint32_t*)(&_MBAR[0x92BC + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P_GTE2048(x)          (*(volatile uint32_t*)(&_MBAR[0x92C0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_OCTETS(x)             (*(volatile uint32_t*)(&_MBAR[0x92C4 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x92C8 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_FRAME_OK(x)           (*(volatile uint32_t*)(&_MBAR[0x92CC + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_CRC(x)                (*(volatile uint32_t*)(&_MBAR[0x92D0 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_ALIGN(x)              (*(volatile uint32_t*)(&_MBAR[0x92D4 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_MACERR(x)             (*(volatile uint32_t*)(&_MBAR[0x92D8 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_FDXFC(x)              (*(volatile uint32_t*)(&_MBAR[0x92DC + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_OCTETS_OK(x)          (*(volatile uint32_t*)(&_MBAR[0x92E0 + ((x)*0x800)]))
+
+
+/* Bit definitions and macros for MCF_FEC_EIR */
+#define MCF_FEC_EIR_RFERR                    (0x20000)
+#define MCF_FEC_EIR_XFERR                    (0x40000)
+#define MCF_FEC_EIR_XFUN                     (0x80000)
+#define MCF_FEC_EIR_RL                       (0x100000)
+#define MCF_FEC_EIR_LC                       (0x200000)
+#define MCF_FEC_EIR_MII                      (0x800000)
+#define MCF_FEC_EIR_TXF                      (0x8000000)
+#define MCF_FEC_EIR_GRA                      (0x10000000)
+#define MCF_FEC_EIR_BABT                     (0x20000000)
+#define MCF_FEC_EIR_BABR                     (0x40000000)
+#define MCF_FEC_EIR_HBERR                    (0x80000000)
+#define MCF_FEC_EIR_CLEAR_ALL                (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_EIMR */
+#define MCF_FEC_EIMR_RFERR                   (0x20000)
+#define MCF_FEC_EIMR_XFERR                   (0x40000)
+#define MCF_FEC_EIMR_XFUN                    (0x80000)
+#define MCF_FEC_EIMR_RL                      (0x100000)
+#define MCF_FEC_EIMR_LC                      (0x200000)
+#define MCF_FEC_EIMR_MII                     (0x800000)
+#define MCF_FEC_EIMR_TXF                     (0x8000000)
+#define MCF_FEC_EIMR_GRA                     (0x10000000)
+#define MCF_FEC_EIMR_BABT                    (0x20000000)
+#define MCF_FEC_EIMR_BABR                    (0x40000000)
+#define MCF_FEC_EIMR_HBERR                   (0x80000000)
+#define MCF_FEC_EIMR_MASK_ALL                (0)
+#define MCF_FEC_EIMR_UNMASK_ALL              (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_ECR */
+#define MCF_FEC_ECR_RESET                    (0x1)
+#define MCF_FEC_ECR_ETHER_EN                 (0x2)
+
+/* Bit definitions and macros for MCF_FEC_MMFR */
+#define MCF_FEC_MMFR_DATA(x)                 (((x)&0xFFFF)<<0)
+#define MCF_FEC_MMFR_TA(x)                   (((x)&0x3)<<0x10)
+#define MCF_FEC_MMFR_TA_10                   (0x20000)
+#define MCF_FEC_MMFR_RA(x)                   (((x)&0x1F)<<0x12)
+#define MCF_FEC_MMFR_PA(x)                   (((x)&0x1F)<<0x17)
+#define MCF_FEC_MMFR_OP(x)                   (((x)&0x3)<<0x1C)
+#define MCF_FEC_MMFR_OP_READ                 (0x20000000)
+#define MCF_FEC_MMFR_OP_WRITE                (0x10000000)
+#define MCF_FEC_MMFR_ST(x)                   (((x)&0x3)<<0x1E)
+#define MCF_FEC_MMFR_ST_01                   (0x40000000)
+
+/* Bit definitions and macros for MCF_FEC_MSCR */
+#define MCF_FEC_MSCR_MII_SPEED(x)            (((x)&0x3F)<<0x1)
+#define MCF_FEC_MSCR_DIS_PREAMBLE            (0x80)
+#define MCF_FEC_MSCR_MII_SPEED_133           (0x1B<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_120           (0x18<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_66            (0xE<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_60            (0xC<<0x1)
+
+/* Bit definitions and macros for MCF_FEC_MIBC */
+#define MCF_FEC_MIBC_MIB_IDLE                (0x40000000)
+#define MCF_FEC_MIBC_MIB_DISABLE             (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_RCR */
+#define MCF_FEC_RCR_LOOP                     (0x1)
+#define MCF_FEC_RCR_DRT                      (0x2)
+#define MCF_FEC_RCR_MII_MODE                 (0x4)
+#define MCF_FEC_RCR_PROM                     (0x8)
+#define MCF_FEC_RCR_BC_REJ                   (0x10)
+#define MCF_FEC_RCR_FCE                      (0x20)
+#define MCF_FEC_RCR_MAX_FL(x)                (((x)&0x7FF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_RHR */
+#define MCF_FEC_RHR_HASH(x)                  (((x)&0x3F)<<0x18)
+#define MCF_FEC_RHR_MULTCAST                 (0x40000000)
+#define MCF_FEC_RHR_FCE                      (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_TCR */
+#define MCF_FEC_TCR_GTS                      (0x1)
+#define MCF_FEC_TCR_HBC                      (0x2)
+#define MCF_FEC_TCR_FDEN                     (0x4)
+#define MCF_FEC_TCR_TFC_PAUSE                (0x8)
+#define MCF_FEC_TCR_RFC_PAUSE                (0x10)
+
+/* Bit definitions and macros for MCF_FEC_PALR */
+#define MCF_FEC_PALR_PADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_PAHR */
+#define MCF_FEC_PAHR_TYPE(x)                 (((x)&0xFFFF)<<0)
+#define MCF_FEC_PAHR_PADDR2(x)               (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_OPD */
+#define MCF_FEC_OPD_PAUSE_DUR(x)             (((x)&0xFFFF)<<0)
+#define MCF_FEC_OPD_OPCODE(x)                (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_IAUR */
+#define MCF_FEC_IAUR_IADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IALR */
+#define MCF_FEC_IALR_IADDR2(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_GAUR */
+#define MCF_FEC_GAUR_GADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_GALR */
+#define MCF_FEC_GALR_GADDR2(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFWR */
+#define MCF_FEC_FECTFWR_X_WMRK(x)            (((x)&0xF)<<0)
+#define MCF_FEC_FECTFWR_X_WMRK_64            (0)
+#define MCF_FEC_FECTFWR_X_WMRK_128           (0x1)
+#define MCF_FEC_FECTFWR_X_WMRK_192           (0x2)
+#define MCF_FEC_FECTFWR_X_WMRK_256           (0x3)
+#define MCF_FEC_FECTFWR_X_WMRK_320           (0x4)
+#define MCF_FEC_FECTFWR_X_WMRK_384           (0x5)
+#define MCF_FEC_FECTFWR_X_WMRK_448           (0x6)
+#define MCF_FEC_FECTFWR_X_WMRK_512           (0x7)
+#define MCF_FEC_FECTFWR_X_WMRK_576           (0x8)
+#define MCF_FEC_FECTFWR_X_WMRK_640           (0x9)
+#define MCF_FEC_FECTFWR_X_WMRK_704           (0xA)
+#define MCF_FEC_FECTFWR_X_WMRK_768           (0xB)
+#define MCF_FEC_FECTFWR_X_WMRK_832           (0xC)
+#define MCF_FEC_FECTFWR_X_WMRK_896           (0xD)
+#define MCF_FEC_FECTFWR_X_WMRK_960           (0xE)
+#define MCF_FEC_FECTFWR_X_WMRK_1024          (0xF)
+
+/* Bit definitions and macros for MCF_FEC_FECRFDR */
+#define MCF_FEC_FECRFDR_FIFO_DATA(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFSR */
+#define MCF_FEC_FECRFSR_EMT                  (0x10000)
+#define MCF_FEC_FECRFSR_ALARM                (0x20000)
+#define MCF_FEC_FECRFSR_FU                   (0x40000)
+#define MCF_FEC_FECRFSR_FRMRDY               (0x80000)
+#define MCF_FEC_FECRFSR_OF                   (0x100000)
+#define MCF_FEC_FECRFSR_UF                   (0x200000)
+#define MCF_FEC_FECRFSR_RXW                  (0x400000)
+#define MCF_FEC_FECRFSR_FAE                  (0x800000)
+#define MCF_FEC_FECRFSR_FRM(x)               (((x)&0xF)<<0x18)
+#define MCF_FEC_FECRFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_FECRFCR */
+#define MCF_FEC_FECRFCR_COUNTER(x)           (((x)&0xFFFF)<<0)
+#define MCF_FEC_FECRFCR_OF_MSK               (0x80000)
+#define MCF_FEC_FECRFCR_UF_MSK               (0x100000)
+#define MCF_FEC_FECRFCR_RXW_MSK              (0x200000)
+#define MCF_FEC_FECRFCR_FAE_MSK              (0x400000)
+#define MCF_FEC_FECRFCR_IP_MSK               (0x800000)
+#define MCF_FEC_FECRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_FEC_FECRFCR_FRMEN                (0x8000000)
+#define MCF_FEC_FECRFCR_TIMER                (0x10000000)
+
+/* Bit definitions and macros for MCF_FEC_FECRLRFP */
+#define MCF_FEC_FECRLRFP_LRFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRLWFP */
+#define MCF_FEC_FECRLWFP_LWFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFAR */
+#define MCF_FEC_FECRFAR_ALARM(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFRP */
+#define MCF_FEC_FECRFRP_READ(x)              (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFWP */
+#define MCF_FEC_FECRFWP_WRITE(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFDR */
+#define MCF_FEC_FECTFDR_FIFO_DATA(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFSR */
+#define MCF_FEC_FECTFSR_EMT                  (0x10000)
+#define MCF_FEC_FECTFSR_ALARM                (0x20000)
+#define MCF_FEC_FECTFSR_FU                   (0x40000)
+#define MCF_FEC_FECTFSR_FRMRDY               (0x80000)
+#define MCF_FEC_FECTFSR_OF                   (0x100000)
+#define MCF_FEC_FECTFSR_UF                   (0x200000)
+#define MCF_FEC_FECTFSR_FAE                  (0x800000)
+#define MCF_FEC_FECTFSR_FRM(x)               (((x)&0xF)<<0x18)
+#define MCF_FEC_FECTFSR_TXW                  (0x40000000)
+#define MCF_FEC_FECTFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_FECTFCR */
+#define MCF_FEC_FECTFCR_RESERVED             (0x200000)
+#define MCF_FEC_FECTFCR_COUNTER(x)           (((x)&0xFFFF)<<0|0x200000)
+#define MCF_FEC_FECTFCR_TXW_MASK             (0x240000)
+#define MCF_FEC_FECTFCR_OF_MSK               (0x280000)
+#define MCF_FEC_FECTFCR_UF_MSK               (0x300000)
+#define MCF_FEC_FECTFCR_FAE_MSK              (0x600000)
+#define MCF_FEC_FECTFCR_IP_MSK               (0xA00000)
+#define MCF_FEC_FECTFCR_GR(x)                (((x)&0x7)<<0x18|0x200000)
+#define MCF_FEC_FECTFCR_FRMEN                (0x8200000)
+#define MCF_FEC_FECTFCR_TIMER                (0x10200000)
+#define MCF_FEC_FECTFCR_WFR                  (0x20200000)
+#define MCF_FEC_FECTFCR_WCTL                 (0x40200000)
+
+/* Bit definitions and macros for MCF_FEC_FECTLRFP */
+#define MCF_FEC_FECTLRFP_LRFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTLWFP */
+#define MCF_FEC_FECTLWFP_LWFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFAR */
+#define MCF_FEC_FECTFAR_ALARM(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFRP */
+#define MCF_FEC_FECTFRP_READ(x)              (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFWP */
+#define MCF_FEC_FECTFWP_WRITE(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECFRST */
+#define MCF_FEC_FECFRST_RST_CTL              (0x1000000)
+#define MCF_FEC_FECFRST_SW_RST               (0x2000000)
+
+/* Bit definitions and macros for MCF_FEC_FECCTCWR */
+#define MCF_FEC_FECCTCWR_TFCW                (0x1000000)
+#define MCF_FEC_FECCTCWR_CRC                 (0x2000000)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */
+#define MCF_FEC_RMON_T_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */
+#define MCF_FEC_RMON_T_PACKETS_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */
+#define MCF_FEC_RMON_T_BC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */
+#define MCF_FEC_RMON_T_MC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */
+#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */
+#define MCF_FEC_RMON_T_UNDERSIZE_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */
+#define MCF_FEC_RMON_T_OVERSIZE_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */
+#define MCF_FEC_RMON_T_FRAG_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */
+#define MCF_FEC_RMON_T_JAB_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_COL */
+#define MCF_FEC_RMON_T_COL_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */
+#define MCF_FEC_RMON_T_P64_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */
+#define MCF_FEC_RMON_T_P65TO127_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */
+#define MCF_FEC_RMON_T_P128TO255_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */
+#define MCF_FEC_RMON_T_P256TO511_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */
+#define MCF_FEC_RMON_T_P512TO1023_Value(x)   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */
+#define MCF_FEC_RMON_T_P1024TO2047_Value(x)  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */
+#define MCF_FEC_RMON_T_P_GTE2048_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */
+#define MCF_FEC_RMON_T_OCTETS_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */
+#define MCF_FEC_IEEE_T_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */
+#define MCF_FEC_IEEE_T_FRAME_OK_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */
+#define MCF_FEC_IEEE_T_1COL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */
+#define MCF_FEC_IEEE_T_MCOL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */
+#define MCF_FEC_IEEE_T_DEF_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */
+#define MCF_FEC_IEEE_T_LCOL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */
+#define MCF_FEC_IEEE_T_EXCOL_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */
+#define MCF_FEC_IEEE_T_MACERR_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */
+#define MCF_FEC_IEEE_T_CSERR_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */
+#define MCF_FEC_IEEE_T_SQE_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */
+#define MCF_FEC_IEEE_T_FDXFC_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */
+#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */
+#define MCF_FEC_RMON_R_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */
+#define MCF_FEC_RMON_R_PACKETS_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */
+#define MCF_FEC_RMON_R_BC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */
+#define MCF_FEC_RMON_R_MC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */
+#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */
+#define MCF_FEC_RMON_R_UNDERSIZE_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */
+#define MCF_FEC_RMON_R_OVERSIZE_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */
+#define MCF_FEC_RMON_R_FRAG_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */
+#define MCF_FEC_RMON_R_JAB_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */
+#define MCF_FEC_RMON_R_RESVD_0_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */
+#define MCF_FEC_RMON_R_P64_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */
+#define MCF_FEC_RMON_R_P65TO127_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */
+#define MCF_FEC_RMON_R_P128TO255_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */
+#define MCF_FEC_RMON_R_P256TO511_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */
+#define MCF_FEC_RMON_R_P512TO1023_Value(x)   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */
+#define MCF_FEC_RMON_R_P1024TO2047_Value(x)  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */
+#define MCF_FEC_RMON_R_P_GTE2048_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */
+#define MCF_FEC_RMON_R_OCTETS_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */
+#define MCF_FEC_IEEE_R_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */
+#define MCF_FEC_IEEE_R_FRAME_OK_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */
+#define MCF_FEC_IEEE_R_CRC_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */
+#define MCF_FEC_IEEE_R_ALIGN_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */
+#define MCF_FEC_IEEE_R_MACERR_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */
+#define MCF_FEC_IEEE_R_FDXFC_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */
+#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+
+#endif /* __MCF5475_FEC_H__ */
--- a/tos/jtagwait/include/MCF5475_GPIO.h
+++ b/tos/jtagwait/include/MCF5475_GPIO.h
@@ -0,0 +1,543 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_GPIO_H__
+#define __MCF5475_GPIO_H__
+
+
+/*********************************************************************
+*
+* General Purpose I/O (GPIO)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPIO_PODR_FBCTL                  (*(volatile uint8_t *)(&_MBAR[0xA00]))
+#define MCF_GPIO_PDDR_FBCTL                  (*(volatile uint8_t *)(&_MBAR[0xA10]))
+#define MCF_GPIO_PPDSDR_FBCTL                (*(volatile uint8_t *)(&_MBAR[0xA20]))
+#define MCF_GPIO_PCLRR_FBCTL                 (*(volatile uint8_t *)(&_MBAR[0xA30]))
+
+#define MCF_GPIO_PODR_FBCS                   (*(volatile uint8_t *)(&_MBAR[0xA01]))
+#define MCF_GPIO_PDDR_FBCS                   (*(volatile uint8_t *)(&_MBAR[0xA11]))
+#define MCF_GPIO_PPDSDR_FBCS                 (*(volatile uint8_t *)(&_MBAR[0xA21]))
+#define MCF_GPIO_PCLRR_FBCS                  (*(volatile uint8_t *)(&_MBAR[0xA31]))
+
+#define MCF_GPIO_PODR_DMA                    (*(volatile uint8_t *)(&_MBAR[0xA02]))
+#define MCF_GPIO_PDDR_DMA                    (*(volatile uint8_t *)(&_MBAR[0xA12]))
+#define MCF_GPIO_PPDSDR_DMA                  (*(volatile uint8_t *)(&_MBAR[0xA22]))
+#define MCF_GPIO_PCLRR_DMA                   (*(volatile uint8_t *)(&_MBAR[0xA32]))
+
+#define MCF_GPIO_PODR_FEC0H                  (*(volatile uint8_t *)(&_MBAR[0xA04]))
+#define MCF_GPIO_PDDR_FEC0H                  (*(volatile uint8_t *)(&_MBAR[0xA14]))
+#define MCF_GPIO_PPDSDR_FEC0H                (*(volatile uint8_t *)(&_MBAR[0xA24]))
+#define MCF_GPIO_PCLRR_FEC0H                 (*(volatile uint8_t *)(&_MBAR[0xA34]))
+
+#define MCF_GPIO_PODR_FEC0L                  (*(volatile uint8_t *)(&_MBAR[0xA05]))
+#define MCF_GPIO_PDDR_FEC0L                  (*(volatile uint8_t *)(&_MBAR[0xA15]))
+#define MCF_GPIO_PPDSDR_FEC0L                (*(volatile uint8_t *)(&_MBAR[0xA25]))
+#define MCF_GPIO_PCLRR_FEC0L                 (*(volatile uint8_t *)(&_MBAR[0xA35]))
+
+#define MCF_GPIO_PODR_FEC1H                  (*(volatile uint8_t *)(&_MBAR[0xA06]))
+#define MCF_GPIO_PDDR_FEC1H                  (*(volatile uint8_t *)(&_MBAR[0xA16]))
+#define MCF_GPIO_PPDSDR_FEC1H                (*(volatile uint8_t *)(&_MBAR[0xA26]))
+#define MCF_GPIO_PCLRR_FEC1H                 (*(volatile uint8_t *)(&_MBAR[0xA36]))
+
+#define MCF_GPIO_PODR_FEC1L                  (*(volatile uint8_t *)(&_MBAR[0xA07]))
+#define MCF_GPIO_PDDR_FEC1L                  (*(volatile uint8_t *)(&_MBAR[0xA17]))
+#define MCF_GPIO_PPDSDR_FEC1L                (*(volatile uint8_t *)(&_MBAR[0xA27]))
+#define MCF_GPIO_PCLRR_FEC1L                 (*(volatile uint8_t *)(&_MBAR[0xA37]))
+
+#define MCF_GPIO_PODR_FECI2C                 (*(volatile uint8_t *)(&_MBAR[0xA08]))
+#define MCF_GPIO_PDDR_FECI2C                 (*(volatile uint8_t *)(&_MBAR[0xA18]))
+#define MCF_GPIO_PPDSDR_FECI2C               (*(volatile uint8_t *)(&_MBAR[0xA28]))
+#define MCF_GPIO_PCLRR_FECI2C                (*(volatile uint8_t *)(&_MBAR[0xA38]))
+
+#define MCF_GPIO_PODR_PCIBG                  (*(volatile uint8_t *)(&_MBAR[0xA09]))
+#define MCF_GPIO_PDDR_PCIBG                  (*(volatile uint8_t *)(&_MBAR[0xA19]))
+#define MCF_GPIO_PPDSDR_PCIBG                (*(volatile uint8_t *)(&_MBAR[0xA29]))
+#define MCF_GPIO_PCLRR_PCIBG                 (*(volatile uint8_t *)(&_MBAR[0xA39]))
+
+#define MCF_GPIO_PODR_PCIBR                  (*(volatile uint8_t *)(&_MBAR[0xA0A]))
+#define MCF_GPIO_PDDR_PCIBR                  (*(volatile uint8_t *)(&_MBAR[0xA1A]))
+#define MCF_GPIO_PPDSDR_PCIBR                (*(volatile uint8_t *)(&_MBAR[0xA2A]))
+#define MCF_GPIO_PCLRR_PCIBR                 (*(volatile uint8_t *)(&_MBAR[0xA3A]))
+
+#define MCF_GPIO2_PODR_PSC3PSC               (*(volatile uint8_t *)(&_MBAR[0xA0C]))
+#define MCF_GPIO2_PDDR_PSC3PSC               (*(volatile uint8_t *)(&_MBAR[0xA1C]))
+#define MCF_GPIO2_PPDSDR_PSC3PSC             (*(volatile uint8_t *)(&_MBAR[0xA2C]))
+#define MCF_GPIO2_PCLRR_PSC3PSC              (*(volatile uint8_t *)(&_MBAR[0xA3C]))
+
+#define MCF_GPIO0_PODR_PSC1PSC               (*(volatile uint8_t *)(&_MBAR[0xA0D]))
+#define MCF_GPIO0_PDDR_PSC1PSC               (*(volatile uint8_t *)(&_MBAR[0xA1D]))
+#define MCF_GPIO0_PPDSDR_PSC1PSC             (*(volatile uint8_t *)(&_MBAR[0xA2D]))
+#define MCF_GPIO0_PCLRR_PSC1PSC              (*(volatile uint8_t *)(&_MBAR[0xA3D]))
+
+#define MCF_GPIO_PODR_DSPI                   (*(volatile uint8_t *)(&_MBAR[0xA0E]))
+#define MCF_GPIO_PDDR_DSPI                   (*(volatile uint8_t *)(&_MBAR[0xA1E]))
+#define MCF_GPIO_PPDSDR_DSPI                 (*(volatile uint8_t *)(&_MBAR[0xA2E]))
+#define MCF_GPIO_PCLRR_DSPI                  (*(volatile uint8_t *)(&_MBAR[0xA3E]))
+
+
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0      (0x1)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1      (0x2)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2      (0x4)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3      (0x8)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4      (0x10)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5      (0x20)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6      (0x40)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0      (0x1)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1      (0x2)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2      (0x4)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3      (0x8)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4      (0x10)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5      (0x20)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6      (0x40)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0  (0x1)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1  (0x2)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2  (0x4)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3  (0x8)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4  (0x10)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5  (0x20)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6  (0x40)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0    (0x1)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1    (0x2)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2    (0x4)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3    (0x8)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4    (0x10)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5    (0x20)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6    (0x40)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS1        (0x2)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS2        (0x4)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS3        (0x8)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS4        (0x10)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS5        (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1        (0x2)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2        (0x4)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3        (0x8)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4        (0x10)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5        (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1    (0x2)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2    (0x4)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3    (0x8)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4    (0x10)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5    (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1      (0x2)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2      (0x4)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3      (0x8)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4      (0x10)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5      (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
+#define MCF_GPIO_PODR_DMA_PODR_DMA0          (0x1)
+#define MCF_GPIO_PODR_DMA_PODR_DMA1          (0x2)
+#define MCF_GPIO_PODR_DMA_PODR_DMA2          (0x4)
+#define MCF_GPIO_PODR_DMA_PODR_DMA3          (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA0          (0x1)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA1          (0x2)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA2          (0x4)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA3          (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0      (0x1)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1      (0x2)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2      (0x4)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3      (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0        (0x1)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1        (0x2)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2        (0x4)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3        (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0      (0x1)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1      (0x2)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2      (0x4)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3      (0x8)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4      (0x10)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5      (0x20)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6      (0x40)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0      (0x1)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1      (0x2)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2      (0x4)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3      (0x8)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4      (0x10)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5      (0x20)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6      (0x40)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0    (0x1)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1    (0x2)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2    (0x4)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3    (0x8)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4    (0x10)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5    (0x20)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6    (0x40)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0      (0x1)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1      (0x2)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2      (0x4)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3      (0x8)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4      (0x10)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5      (0x20)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6      (0x40)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0      (0x1)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1      (0x2)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2      (0x4)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3      (0x8)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4      (0x10)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5      (0x20)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6      (0x40)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0    (0x1)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1    (0x2)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2    (0x4)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3    (0x8)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4    (0x10)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5    (0x20)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6    (0x40)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0      (0x1)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1      (0x2)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2      (0x4)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3      (0x8)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4      (0x10)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5      (0x20)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6      (0x40)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0      (0x1)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1      (0x2)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2      (0x4)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3      (0x8)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4      (0x10)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5      (0x20)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6      (0x40)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0    (0x1)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1    (0x2)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2    (0x4)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3    (0x8)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4    (0x10)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5    (0x20)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6    (0x40)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0      (0x1)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1      (0x2)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2      (0x4)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3      (0x8)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4      (0x10)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5      (0x20)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6      (0x40)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0      (0x1)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1      (0x2)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2      (0x4)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3      (0x8)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4      (0x10)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5      (0x20)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6      (0x40)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0    (0x1)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1    (0x2)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2    (0x4)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3    (0x8)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4    (0x10)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5    (0x20)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6    (0x40)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0    (0x1)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1    (0x2)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2    (0x4)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3    (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0    (0x1)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1    (0x2)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2    (0x4)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3    (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0  (0x1)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1  (0x2)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2  (0x4)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3  (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0      (0x1)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1      (0x2)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2      (0x4)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3      (0x8)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0      (0x1)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1      (0x2)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2      (0x4)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3      (0x8)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0  (0x1)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1  (0x2)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2  (0x4)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3  (0x8)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4  (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0    (0x1)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1    (0x2)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2    (0x4)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3    (0x8)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4    (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0      (0x1)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1      (0x2)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2      (0x4)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3      (0x8)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0      (0x1)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1      (0x2)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2      (0x4)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3      (0x8)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0  (0x1)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1  (0x2)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2  (0x4)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3  (0x8)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4  (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0    (0x1)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1    (0x2)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2    (0x4)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3    (0x8)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4    (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI0        (0x1)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI1        (0x2)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI2        (0x4)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI3        (0x8)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI4        (0x10)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI5        (0x20)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI6        (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0        (0x1)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1        (0x2)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2        (0x4)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3        (0x8)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4        (0x10)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5        (0x20)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6        (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0    (0x1)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1    (0x2)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2    (0x4)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3    (0x8)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4    (0x10)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5    (0x20)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6    (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0      (0x1)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1      (0x2)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2      (0x4)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3      (0x8)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4      (0x10)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5      (0x20)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6      (0x40)
+
+
+#endif /* __MCF5475_GPIO_H__ */
--- a/tos/jtagwait/include/MCF5475_GPT.h
+++ b/tos/jtagwait/include/MCF5475_GPT.h
@@ -0,0 +1,100 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_GPT_H__
+#define __MCF5475_GPT_H__
+
+
+/*********************************************************************
+*
+* General Purpose Timers (GPT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPT0_GMS                         (*(volatile uint32_t*)(&_MBAR[0x800]))
+#define MCF_GPT0_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x804]))
+#define MCF_GPT0_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x808]))
+#define MCF_GPT0_GSR                         (*(volatile uint32_t*)(&_MBAR[0x80C]))
+
+#define MCF_GPT1_GMS                         (*(volatile uint32_t*)(&_MBAR[0x810]))
+#define MCF_GPT1_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x814]))
+#define MCF_GPT1_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x818]))
+#define MCF_GPT1_GSR                         (*(volatile uint32_t*)(&_MBAR[0x81C]))
+
+#define MCF_GPT2_GMS                         (*(volatile uint32_t*)(&_MBAR[0x820]))
+#define MCF_GPT2_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x824]))
+#define MCF_GPT2_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x828]))
+#define MCF_GPT2_GSR                         (*(volatile uint32_t*)(&_MBAR[0x82C]))
+
+#define MCF_GPT3_GMS                         (*(volatile uint32_t*)(&_MBAR[0x830]))
+#define MCF_GPT3_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x834]))
+#define MCF_GPT3_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x838]))
+#define MCF_GPT3_GSR                         (*(volatile uint32_t*)(&_MBAR[0x83C]))
+
+#define MCF_GPT_GMS(x)                       (*(volatile uint32_t*)(&_MBAR[0x800 + ((x)*0x10)]))
+#define MCF_GPT_GCIR(x)                      (*(volatile uint32_t*)(&_MBAR[0x804 + ((x)*0x10)]))
+#define MCF_GPT_GPWM(x)                      (*(volatile uint32_t*)(&_MBAR[0x808 + ((x)*0x10)]))
+#define MCF_GPT_GSR(x)                       (*(volatile uint32_t*)(&_MBAR[0x80C + ((x)*0x10)]))
+
+
+/* Bit definitions and macros for MCF_GPT_GMS */
+#define MCF_GPT_GMS_TMS(x)                   (((x)&0x7)<<0)
+#define MCF_GPT_GMS_TMS_DISABLE              (0)
+#define MCF_GPT_GMS_TMS_INCAPT               (0x1)
+#define MCF_GPT_GMS_TMS_OUTCAPT              (0x2)
+#define MCF_GPT_GMS_TMS_PWM                  (0x3)
+#define MCF_GPT_GMS_TMS_GPIO                 (0x4)
+#define MCF_GPT_GMS_GPIO(x)                  (((x)&0x3)<<0x4)
+#define MCF_GPT_GMS_GPIO_INPUT               (0)
+#define MCF_GPT_GMS_GPIO_OUTLO               (0x20)
+#define MCF_GPT_GMS_GPIO_OUTHI               (0x30)
+#define MCF_GPT_GMS_IEN                      (0x100)
+#define MCF_GPT_GMS_OD                       (0x200)
+#define MCF_GPT_GMS_SC                       (0x400)
+#define MCF_GPT_GMS_CE                       (0x1000)
+#define MCF_GPT_GMS_WDEN                     (0x8000)
+#define MCF_GPT_GMS_ICT(x)                   (((x)&0x3)<<0x10)
+#define MCF_GPT_GMS_ICT_ANY                  (0)
+#define MCF_GPT_GMS_ICT_RISE                 (0x10000)
+#define MCF_GPT_GMS_ICT_FALL                 (0x20000)
+#define MCF_GPT_GMS_ICT_PULSE                (0x30000)
+#define MCF_GPT_GMS_OCT(x)                   (((x)&0x3)<<0x14)
+#define MCF_GPT_GMS_OCT_FRCLOW               (0)
+#define MCF_GPT_GMS_OCT_PULSEHI              (0x100000)
+#define MCF_GPT_GMS_OCT_PULSELO              (0x200000)
+#define MCF_GPT_GMS_OCT_TOGGLE               (0x300000)
+#define MCF_GPT_GMS_OCPW(x)                  (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_GPT_GCIR */
+#define MCF_GPT_GCIR_CNT(x)                  (((x)&0xFFFF)<<0)
+#define MCF_GPT_GCIR_PRE(x)                  (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_GPT_GPWM */
+#define MCF_GPT_GPWM_LOAD                    (0x1)
+#define MCF_GPT_GPWM_PWMOP                   (0x100)
+#define MCF_GPT_GPWM_WIDTH(x)                (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_GPT_GSR */
+#define MCF_GPT_GSR_CAPT                     (0x1)
+#define MCF_GPT_GSR_COMP                     (0x2)
+#define MCF_GPT_GSR_PWMP                     (0x4)
+#define MCF_GPT_GSR_TEXP                     (0x8)
+#define MCF_GPT_GSR_PIN                      (0x100)
+#define MCF_GPT_GSR_OVF(x)                   (((x)&0x7)<<0xC)
+#define MCF_GPT_GSR_CAPTURE(x)               (((x)&0xFFFF)<<0x10)
+
+
+#endif /* __MCF5475_GPT_H__ */
--- a/tos/jtagwait/include/MCF5475_I2C.h
+++ b/tos/jtagwait/include/MCF5475_I2C.h
@@ -0,0 +1,69 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_I2C_H__
+#define __MCF5475_I2C_H__
+
+
+/*********************************************************************
+*
+* I2C Module (I2C)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_I2C_I2ADR                        (*(volatile uint8_t *)(&_MBAR[0x8F00]))
+#define MCF_I2C_I2FDR                        (*(volatile uint8_t *)(&_MBAR[0x8F04]))
+#define MCF_I2C_I2CR                         (*(volatile uint8_t *)(&_MBAR[0x8F08]))
+#define MCF_I2C_I2SR                         (*(volatile uint8_t *)(&_MBAR[0x8F0C]))
+#define MCF_I2C_I2DR                         (*(volatile uint8_t *)(&_MBAR[0x8F10]))
+#define MCF_I2C_I2ICR                        (*(volatile uint8_t *)(&_MBAR[0x8F20]))
+
+
+
+/* Bit definitions and macros for MCF_I2C_I2ADR */
+#define MCF_I2C_I2ADR_ADR(x)                 (((x)&0x7F)<<0x1)
+
+/* Bit definitions and macros for MCF_I2C_I2FDR */
+#define MCF_I2C_I2FDR_IC(x)                  (((x)&0x3F)<<0)
+
+/* Bit definitions and macros for MCF_I2C_I2CR */
+#define MCF_I2C_I2CR_RSTA                    (0x4)
+#define MCF_I2C_I2CR_TXAK                    (0x8)
+#define MCF_I2C_I2CR_MTX                     (0x10)
+#define MCF_I2C_I2CR_MSTA                    (0x20)
+#define MCF_I2C_I2CR_IIEN                    (0x40)
+#define MCF_I2C_I2CR_IEN                     (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2SR */
+#define MCF_I2C_I2SR_RXAK                    (0x1)
+#define MCF_I2C_I2SR_IIF                     (0x2)
+#define MCF_I2C_I2SR_SRW                     (0x4)
+#define MCF_I2C_I2SR_IAL                     (0x10)
+#define MCF_I2C_I2SR_IBB                     (0x20)
+#define MCF_I2C_I2SR_IAAS                    (0x40)
+#define MCF_I2C_I2SR_ICF                     (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2DR */
+#define MCF_I2C_I2DR_DATA(x)                 (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_I2C_I2ICR */
+#define MCF_I2C_I2ICR_IE                     (0x1)
+#define MCF_I2C_I2ICR_RE                     (0x2)
+#define MCF_I2C_I2ICR_TE                     (0x4)
+#define MCF_I2C_I2ICR_BNBE                   (0x8)
+
+
+#endif /* __MCF5475_I2C_H__ */
--- a/tos/jtagwait/include/MCF5475_INTC.h
+++ b/tos/jtagwait/include/MCF5475_INTC.h
@@ -0,0 +1,331 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_INTC_H__
+#define __MCF5475_INTC_H__
+
+
+/*********************************************************************
+*
+* Interrupt Controller (INTC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_INTC_IPRH                        (*(volatile uint32_t*)(&_MBAR[0x700]))
+#define MCF_INTC_IPRL                        (*(volatile uint32_t*)(&_MBAR[0x704]))
+#define MCF_INTC_IMRH                        (*(volatile uint32_t*)(&_MBAR[0x708]))
+#define MCF_INTC_IMRL                        (*(volatile uint32_t*)(&_MBAR[0x70C]))
+#define MCF_INTC_INTFRCH                     (*(volatile uint32_t*)(&_MBAR[0x710]))
+#define MCF_INTC_INTFRCL                     (*(volatile uint32_t*)(&_MBAR[0x714]))
+#define MCF_INTC_IRLR                        (*(volatile uint8_t *)(&_MBAR[0x718]))
+#define MCF_INTC_IACKLPR                     (*(volatile uint8_t *)(&_MBAR[0x719]))
+#define MCF_INTC_ICR01                       (*(volatile uint8_t *)(&_MBAR[0x741]))
+#define MCF_INTC_ICR02                       (*(volatile uint8_t *)(&_MBAR[0x742]))
+#define MCF_INTC_ICR03                       (*(volatile uint8_t *)(&_MBAR[0x743]))
+#define MCF_INTC_ICR04                       (*(volatile uint8_t *)(&_MBAR[0x744]))
+#define MCF_INTC_ICR05                       (*(volatile uint8_t *)(&_MBAR[0x745]))
+#define MCF_INTC_ICR06                       (*(volatile uint8_t *)(&_MBAR[0x746]))
+#define MCF_INTC_ICR07                       (*(volatile uint8_t *)(&_MBAR[0x747]))
+#define MCF_INTC_ICR08                       (*(volatile uint8_t *)(&_MBAR[0x748]))
+#define MCF_INTC_ICR09                       (*(volatile uint8_t *)(&_MBAR[0x749]))
+#define MCF_INTC_ICR10                       (*(volatile uint8_t *)(&_MBAR[0x74A]))
+#define MCF_INTC_ICR11                       (*(volatile uint8_t *)(&_MBAR[0x74B]))
+#define MCF_INTC_ICR12                       (*(volatile uint8_t *)(&_MBAR[0x74C]))
+#define MCF_INTC_ICR13                       (*(volatile uint8_t *)(&_MBAR[0x74D]))
+#define MCF_INTC_ICR14                       (*(volatile uint8_t *)(&_MBAR[0x74E]))
+#define MCF_INTC_ICR15                       (*(volatile uint8_t *)(&_MBAR[0x74F]))
+#define MCF_INTC_ICR16                       (*(volatile uint8_t *)(&_MBAR[0x750]))
+#define MCF_INTC_ICR17                       (*(volatile uint8_t *)(&_MBAR[0x751]))
+#define MCF_INTC_ICR18                       (*(volatile uint8_t *)(&_MBAR[0x752]))
+#define MCF_INTC_ICR19                       (*(volatile uint8_t *)(&_MBAR[0x753]))
+#define MCF_INTC_ICR20                       (*(volatile uint8_t *)(&_MBAR[0x754]))
+#define MCF_INTC_ICR21                       (*(volatile uint8_t *)(&_MBAR[0x755]))
+#define MCF_INTC_ICR22                       (*(volatile uint8_t *)(&_MBAR[0x756]))
+#define MCF_INTC_ICR23                       (*(volatile uint8_t *)(&_MBAR[0x757]))
+#define MCF_INTC_ICR24                       (*(volatile uint8_t *)(&_MBAR[0x758]))
+#define MCF_INTC_ICR25                       (*(volatile uint8_t *)(&_MBAR[0x759]))
+#define MCF_INTC_ICR26                       (*(volatile uint8_t *)(&_MBAR[0x75A]))
+#define MCF_INTC_ICR27                       (*(volatile uint8_t *)(&_MBAR[0x75B]))
+#define MCF_INTC_ICR28                       (*(volatile uint8_t *)(&_MBAR[0x75C]))
+#define MCF_INTC_ICR29                       (*(volatile uint8_t *)(&_MBAR[0x75D]))
+#define MCF_INTC_ICR30                       (*(volatile uint8_t *)(&_MBAR[0x75E]))
+#define MCF_INTC_ICR31                       (*(volatile uint8_t *)(&_MBAR[0x75F]))
+#define MCF_INTC_ICR32                       (*(volatile uint8_t *)(&_MBAR[0x760]))
+#define MCF_INTC_ICR33                       (*(volatile uint8_t *)(&_MBAR[0x761]))
+#define MCF_INTC_ICR34                       (*(volatile uint8_t *)(&_MBAR[0x762]))
+#define MCF_INTC_ICR35                       (*(volatile uint8_t *)(&_MBAR[0x763]))
+#define MCF_INTC_ICR36                       (*(volatile uint8_t *)(&_MBAR[0x764]))
+#define MCF_INTC_ICR37                       (*(volatile uint8_t *)(&_MBAR[0x765]))
+#define MCF_INTC_ICR38                       (*(volatile uint8_t *)(&_MBAR[0x766]))
+#define MCF_INTC_ICR39                       (*(volatile uint8_t *)(&_MBAR[0x767]))
+#define MCF_INTC_ICR40                       (*(volatile uint8_t *)(&_MBAR[0x768]))
+#define MCF_INTC_ICR41                       (*(volatile uint8_t *)(&_MBAR[0x769]))
+#define MCF_INTC_ICR42                       (*(volatile uint8_t *)(&_MBAR[0x76A]))
+#define MCF_INTC_ICR43                       (*(volatile uint8_t *)(&_MBAR[0x76B]))
+#define MCF_INTC_ICR44                       (*(volatile uint8_t *)(&_MBAR[0x76C]))
+#define MCF_INTC_ICR45                       (*(volatile uint8_t *)(&_MBAR[0x76D]))
+#define MCF_INTC_ICR46                       (*(volatile uint8_t *)(&_MBAR[0x76E]))
+#define MCF_INTC_ICR47                       (*(volatile uint8_t *)(&_MBAR[0x76F]))
+#define MCF_INTC_ICR48                       (*(volatile uint8_t *)(&_MBAR[0x770]))
+#define MCF_INTC_ICR49                       (*(volatile uint8_t *)(&_MBAR[0x771]))
+#define MCF_INTC_ICR50                       (*(volatile uint8_t *)(&_MBAR[0x772]))
+#define MCF_INTC_ICR51                       (*(volatile uint8_t *)(&_MBAR[0x773]))
+#define MCF_INTC_ICR52                       (*(volatile uint8_t *)(&_MBAR[0x774]))
+#define MCF_INTC_ICR53                       (*(volatile uint8_t *)(&_MBAR[0x775]))
+#define MCF_INTC_ICR54                       (*(volatile uint8_t *)(&_MBAR[0x776]))
+#define MCF_INTC_ICR55                       (*(volatile uint8_t *)(&_MBAR[0x777]))
+#define MCF_INTC_ICR56                       (*(volatile uint8_t *)(&_MBAR[0x778]))
+#define MCF_INTC_ICR57                       (*(volatile uint8_t *)(&_MBAR[0x779]))
+#define MCF_INTC_ICR58                       (*(volatile uint8_t *)(&_MBAR[0x77A]))
+#define MCF_INTC_ICR59                       (*(volatile uint8_t *)(&_MBAR[0x77B]))
+#define MCF_INTC_ICR60                       (*(volatile uint8_t *)(&_MBAR[0x77C]))
+#define MCF_INTC_ICR61                       (*(volatile uint8_t *)(&_MBAR[0x77D]))
+#define MCF_INTC_ICR62                       (*(volatile uint8_t *)(&_MBAR[0x77E]))
+#define MCF_INTC_ICR63                       (*(volatile uint8_t *)(&_MBAR[0x77F]))
+#define MCF_INTC_SWIACK                      (*(volatile uint8_t *)(&_MBAR[0x7E0]))
+#define MCF_INTC_L1IACK                      (*(volatile uint8_t *)(&_MBAR[0x7E4]))
+#define MCF_INTC_L2IACK                      (*(volatile uint8_t *)(&_MBAR[0x7E8]))
+#define MCF_INTC_L3IACK                      (*(volatile uint8_t *)(&_MBAR[0x7EC]))
+#define MCF_INTC_L4IACK                      (*(volatile uint8_t *)(&_MBAR[0x7F0]))
+#define MCF_INTC_L5IACK                      (*(volatile uint8_t *)(&_MBAR[0x7F4]))
+#define MCF_INTC_L6IACK                      (*(volatile uint8_t *)(&_MBAR[0x7F8]))
+#define MCF_INTC_L7IACK                      (*(volatile uint8_t *)(&_MBAR[0x7FC]))
+#define MCF_INTC_ICR(x)                      (*(volatile uint8_t *)(&_MBAR[0x741 + ((x-1)*0x1)]))
+#define MCF_INTC_LIACK(x)                    (*(volatile uint8_t *)(&_MBAR[0x7E4 + ((x-1)*0x4)]))
+
+
+
+/* Bit definitions and macros for MCF_INTC_IPRH */
+#define MCF_INTC_IPRH_INT32                  (0x1)
+#define MCF_INTC_IPRH_INT33                  (0x2)
+#define MCF_INTC_IPRH_INT34                  (0x4)
+#define MCF_INTC_IPRH_INT35                  (0x8)
+#define MCF_INTC_IPRH_INT36                  (0x10)
+#define MCF_INTC_IPRH_INT37                  (0x20)
+#define MCF_INTC_IPRH_INT38                  (0x40)
+#define MCF_INTC_IPRH_INT39                  (0x80)
+#define MCF_INTC_IPRH_INT40                  (0x100)
+#define MCF_INTC_IPRH_INT41                  (0x200)
+#define MCF_INTC_IPRH_INT42                  (0x400)
+#define MCF_INTC_IPRH_INT43                  (0x800)
+#define MCF_INTC_IPRH_INT44                  (0x1000)
+#define MCF_INTC_IPRH_INT45                  (0x2000)
+#define MCF_INTC_IPRH_INT46                  (0x4000)
+#define MCF_INTC_IPRH_INT47                  (0x8000)
+#define MCF_INTC_IPRH_INT48                  (0x10000)
+#define MCF_INTC_IPRH_INT49                  (0x20000)
+#define MCF_INTC_IPRH_INT50                  (0x40000)
+#define MCF_INTC_IPRH_INT51                  (0x80000)
+#define MCF_INTC_IPRH_INT52                  (0x100000)
+#define MCF_INTC_IPRH_INT53                  (0x200000)
+#define MCF_INTC_IPRH_INT54                  (0x400000)
+#define MCF_INTC_IPRH_INT55                  (0x800000)
+#define MCF_INTC_IPRH_INT56                  (0x1000000)
+#define MCF_INTC_IPRH_INT57                  (0x2000000)
+#define MCF_INTC_IPRH_INT58                  (0x4000000)
+#define MCF_INTC_IPRH_INT59                  (0x8000000)
+#define MCF_INTC_IPRH_INT60                  (0x10000000)
+#define MCF_INTC_IPRH_INT61                  (0x20000000)
+#define MCF_INTC_IPRH_INT62                  (0x40000000)
+#define MCF_INTC_IPRH_INT63                  (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IPRL */
+#define MCF_INTC_IPRL_INT1                   (0x2)
+#define MCF_INTC_IPRL_INT2                   (0x4)
+#define MCF_INTC_IPRL_INT3                   (0x8)
+#define MCF_INTC_IPRL_INT4                   (0x10)
+#define MCF_INTC_IPRL_INT5                   (0x20)
+#define MCF_INTC_IPRL_INT6                   (0x40)
+#define MCF_INTC_IPRL_INT7                   (0x80)
+#define MCF_INTC_IPRL_INT8                   (0x100)
+#define MCF_INTC_IPRL_INT9                   (0x200)
+#define MCF_INTC_IPRL_INT10                  (0x400)
+#define MCF_INTC_IPRL_INT11                  (0x800)
+#define MCF_INTC_IPRL_INT12                  (0x1000)
+#define MCF_INTC_IPRL_INT13                  (0x2000)
+#define MCF_INTC_IPRL_INT14                  (0x4000)
+#define MCF_INTC_IPRL_INT15                  (0x8000)
+#define MCF_INTC_IPRL_INT16                  (0x10000)
+#define MCF_INTC_IPRL_INT17                  (0x20000)
+#define MCF_INTC_IPRL_INT18                  (0x40000)
+#define MCF_INTC_IPRL_INT19                  (0x80000)
+#define MCF_INTC_IPRL_INT20                  (0x100000)
+#define MCF_INTC_IPRL_INT21                  (0x200000)
+#define MCF_INTC_IPRL_INT22                  (0x400000)
+#define MCF_INTC_IPRL_INT23                  (0x800000)
+#define MCF_INTC_IPRL_INT24                  (0x1000000)
+#define MCF_INTC_IPRL_INT25                  (0x2000000)
+#define MCF_INTC_IPRL_INT26                  (0x4000000)
+#define MCF_INTC_IPRL_INT27                  (0x8000000)
+#define MCF_INTC_IPRL_INT28                  (0x10000000)
+#define MCF_INTC_IPRL_INT29                  (0x20000000)
+#define MCF_INTC_IPRL_INT30                  (0x40000000)
+#define MCF_INTC_IPRL_INT31                  (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRH */
+#define MCF_INTC_IMRH_INT_MASK32             (0x1)
+#define MCF_INTC_IMRH_INT_MASK33             (0x2)
+#define MCF_INTC_IMRH_INT_MASK34             (0x4)
+#define MCF_INTC_IMRH_INT_MASK35             (0x8)
+#define MCF_INTC_IMRH_INT_MASK36             (0x10)
+#define MCF_INTC_IMRH_INT_MASK37             (0x20)
+#define MCF_INTC_IMRH_INT_MASK38             (0x40)
+#define MCF_INTC_IMRH_INT_MASK39             (0x80)
+#define MCF_INTC_IMRH_INT_MASK40             (0x100)
+#define MCF_INTC_IMRH_INT_MASK41             (0x200)
+#define MCF_INTC_IMRH_INT_MASK42             (0x400)
+#define MCF_INTC_IMRH_INT_MASK43             (0x800)
+#define MCF_INTC_IMRH_INT_MASK44             (0x1000)
+#define MCF_INTC_IMRH_INT_MASK45             (0x2000)
+#define MCF_INTC_IMRH_INT_MASK46             (0x4000)
+#define MCF_INTC_IMRH_INT_MASK47             (0x8000)
+#define MCF_INTC_IMRH_INT_MASK48             (0x10000)
+#define MCF_INTC_IMRH_INT_MASK49             (0x20000)
+#define MCF_INTC_IMRH_INT_MASK50             (0x40000)
+#define MCF_INTC_IMRH_INT_MASK51             (0x80000)
+#define MCF_INTC_IMRH_INT_MASK52             (0x100000)
+#define MCF_INTC_IMRH_INT_MASK53             (0x200000)
+#define MCF_INTC_IMRH_INT_MASK54             (0x400000)
+#define MCF_INTC_IMRH_INT_MASK55             (0x800000)
+#define MCF_INTC_IMRH_INT_MASK56             (0x1000000)
+#define MCF_INTC_IMRH_INT_MASK57             (0x2000000)
+#define MCF_INTC_IMRH_INT_MASK58             (0x4000000)
+#define MCF_INTC_IMRH_INT_MASK59             (0x8000000)
+#define MCF_INTC_IMRH_INT_MASK60             (0x10000000)
+#define MCF_INTC_IMRH_INT_MASK61             (0x20000000)
+#define MCF_INTC_IMRH_INT_MASK62             (0x40000000)
+#define MCF_INTC_IMRH_INT_MASK63             (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRL */
+#define MCF_INTC_IMRL_MASKALL                (0x1)
+#define MCF_INTC_IMRL_INT_MASK1              (0x2)
+#define MCF_INTC_IMRL_INT_MASK2              (0x4)
+#define MCF_INTC_IMRL_INT_MASK3              (0x8)
+#define MCF_INTC_IMRL_INT_MASK4              (0x10)
+#define MCF_INTC_IMRL_INT_MASK5              (0x20)
+#define MCF_INTC_IMRL_INT_MASK6              (0x40)
+#define MCF_INTC_IMRL_INT_MASK7              (0x80)
+#define MCF_INTC_IMRL_INT_MASK8              (0x100)
+#define MCF_INTC_IMRL_INT_MASK9              (0x200)
+#define MCF_INTC_IMRL_INT_MASK10             (0x400)
+#define MCF_INTC_IMRL_INT_MASK11             (0x800)
+#define MCF_INTC_IMRL_INT_MASK12             (0x1000)
+#define MCF_INTC_IMRL_INT_MASK13             (0x2000)
+#define MCF_INTC_IMRL_INT_MASK14             (0x4000)
+#define MCF_INTC_IMRL_INT_MASK15             (0x8000)
+#define MCF_INTC_IMRL_INT_MASK16             (0x10000)
+#define MCF_INTC_IMRL_INT_MASK17             (0x20000)
+#define MCF_INTC_IMRL_INT_MASK18             (0x40000)
+#define MCF_INTC_IMRL_INT_MASK19             (0x80000)
+#define MCF_INTC_IMRL_INT_MASK20             (0x100000)
+#define MCF_INTC_IMRL_INT_MASK21             (0x200000)
+#define MCF_INTC_IMRL_INT_MASK22             (0x400000)
+#define MCF_INTC_IMRL_INT_MASK23             (0x800000)
+#define MCF_INTC_IMRL_INT_MASK24             (0x1000000)
+#define MCF_INTC_IMRL_INT_MASK25             (0x2000000)
+#define MCF_INTC_IMRL_INT_MASK26             (0x4000000)
+#define MCF_INTC_IMRL_INT_MASK27             (0x8000000)
+#define MCF_INTC_IMRL_INT_MASK28             (0x10000000)
+#define MCF_INTC_IMRL_INT_MASK29             (0x20000000)
+#define MCF_INTC_IMRL_INT_MASK30             (0x40000000)
+#define MCF_INTC_IMRL_INT_MASK31             (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCH */
+#define MCF_INTC_INTFRCH_INTFRC32            (0x1)
+#define MCF_INTC_INTFRCH_INTFRC33            (0x2)
+#define MCF_INTC_INTFRCH_INTFRC34            (0x4)
+#define MCF_INTC_INTFRCH_INTFRC35            (0x8)
+#define MCF_INTC_INTFRCH_INTFRC36            (0x10)
+#define MCF_INTC_INTFRCH_INTFRC37            (0x20)
+#define MCF_INTC_INTFRCH_INTFRC38            (0x40)
+#define MCF_INTC_INTFRCH_INTFRC39            (0x80)
+#define MCF_INTC_INTFRCH_INTFRC40            (0x100)
+#define MCF_INTC_INTFRCH_INTFRC41            (0x200)
+#define MCF_INTC_INTFRCH_INTFRC42            (0x400)
+#define MCF_INTC_INTFRCH_INTFRC43            (0x800)
+#define MCF_INTC_INTFRCH_INTFRC44            (0x1000)
+#define MCF_INTC_INTFRCH_INTFRC45            (0x2000)
+#define MCF_INTC_INTFRCH_INTFRC46            (0x4000)
+#define MCF_INTC_INTFRCH_INTFRC47            (0x8000)
+#define MCF_INTC_INTFRCH_INTFRC48            (0x10000)
+#define MCF_INTC_INTFRCH_INTFRC49            (0x20000)
+#define MCF_INTC_INTFRCH_INTFRC50            (0x40000)
+#define MCF_INTC_INTFRCH_INTFRC51            (0x80000)
+#define MCF_INTC_INTFRCH_INTFRC52            (0x100000)
+#define MCF_INTC_INTFRCH_INTFRC53            (0x200000)
+#define MCF_INTC_INTFRCH_INTFRC54            (0x400000)
+#define MCF_INTC_INTFRCH_INTFRC55            (0x800000)
+#define MCF_INTC_INTFRCH_INTFRC56            (0x1000000)
+#define MCF_INTC_INTFRCH_INTFRC57            (0x2000000)
+#define MCF_INTC_INTFRCH_INTFRC58            (0x4000000)
+#define MCF_INTC_INTFRCH_INTFRC59            (0x8000000)
+#define MCF_INTC_INTFRCH_INTFRC60            (0x10000000)
+#define MCF_INTC_INTFRCH_INTFRC61            (0x20000000)
+#define MCF_INTC_INTFRCH_INTFRC62            (0x40000000)
+#define MCF_INTC_INTFRCH_INTFRC63            (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCL */
+#define MCF_INTC_INTFRCL_INTFRC1             (0x2)
+#define MCF_INTC_INTFRCL_INTFRC2             (0x4)
+#define MCF_INTC_INTFRCL_INTFRC3             (0x8)
+#define MCF_INTC_INTFRCL_INTFRC4             (0x10)
+#define MCF_INTC_INTFRCL_INTFRC5             (0x20)
+#define MCF_INTC_INTFRCL_INTFRC6             (0x40)
+#define MCF_INTC_INTFRCL_INTFRC7             (0x80)
+#define MCF_INTC_INTFRCL_INTFRC8             (0x100)
+#define MCF_INTC_INTFRCL_INTFRC9             (0x200)
+#define MCF_INTC_INTFRCL_INTFRC10            (0x400)
+#define MCF_INTC_INTFRCL_INTFRC11            (0x800)
+#define MCF_INTC_INTFRCL_INTFRC12            (0x1000)
+#define MCF_INTC_INTFRCL_INTFRC13            (0x2000)
+#define MCF_INTC_INTFRCL_INTFRC14            (0x4000)
+#define MCF_INTC_INTFRCL_INTFRC15            (0x8000)
+#define MCF_INTC_INTFRCL_INTFRC16            (0x10000)
+#define MCF_INTC_INTFRCL_INTFRC17            (0x20000)
+#define MCF_INTC_INTFRCL_INTFRC18            (0x40000)
+#define MCF_INTC_INTFRCL_INTFRC19            (0x80000)
+#define MCF_INTC_INTFRCL_INTFRC20            (0x100000)
+#define MCF_INTC_INTFRCL_INTFRC21            (0x200000)
+#define MCF_INTC_INTFRCL_INTFRC22            (0x400000)
+#define MCF_INTC_INTFRCL_INTFRC23            (0x800000)
+#define MCF_INTC_INTFRCL_INTFRC24            (0x1000000)
+#define MCF_INTC_INTFRCL_INTFRC25            (0x2000000)
+#define MCF_INTC_INTFRCL_INTFRC26            (0x4000000)
+#define MCF_INTC_INTFRCL_INTFRC27            (0x8000000)
+#define MCF_INTC_INTFRCL_INTFRC28            (0x10000000)
+#define MCF_INTC_INTFRCL_INTFRC29            (0x20000000)
+#define MCF_INTC_INTFRCL_INTFRC30            (0x40000000)
+#define MCF_INTC_INTFRCL_INTFRC31            (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IRLR */
+#define MCF_INTC_IRLR_IRQ(x)                 (((x)&0x7F)<<0x1)
+
+/* Bit definitions and macros for MCF_INTC_IACKLPR */
+#define MCF_INTC_IACKLPR_PRI(x)              (((x)&0xF)<<0)
+#define MCF_INTC_IACKLPR_LEVEL(x)            (((x)&0x7)<<0x4)
+
+/* Bit definitions and macros for MCF_INTC_ICR */
+#define MCF_INTC_ICR_IP(x)                   (((x)&0x7)<<0)
+#define MCF_INTC_ICR_IL(x)                   (((x)&0x7)<<0x3)
+
+/* Bit definitions and macros for MCF_INTC_SWIACK */
+#define MCF_INTC_SWIACK_VECTOR(x)            (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_INTC_LIACK */
+#define MCF_INTC_LIACK_VECTOR(x)             (((x)&0xFF)<<0)
+
+
+#endif /* __MCF5475_INTC_H__ */
--- a/tos/jtagwait/include/MCF5475_MMU.h
+++ b/tos/jtagwait/include/MCF5475_MMU.h
@@ -0,0 +1,79 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_MMU_H__
+#define __MCF5475_MMU_H__
+
+
+/*********************************************************************
+*
+* Memory Management Unit (MMU)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+
+/* note the uint32_t_a - this is to avoid gcc warnings about pointer aliasing */
+#define MCF_MMU_MMUCR                        (*(volatile uint32_t_a*)(&_MMUBAR[0]))
+#define MCF_MMU_MMUOR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x4]))
+#define MCF_MMU_MMUSR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x8]))
+#define MCF_MMU_MMUAR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x10]))
+#define MCF_MMU_MMUTR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x14]))
+#define MCF_MMU_MMUDR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x18]))
+
+
+/* Bit definitions and macros for MCF_MMU_MMUCR */
+#define MCF_MMU_MMUCR_EN                     (0x1)
+#define MCF_MMU_MMUCR_ASM                    (0x2)
+
+/* Bit definitions and macros for MCF_MMU_MMUOR */
+#define MCF_MMU_MMUOR_UAA                    (0x1)
+#define MCF_MMU_MMUOR_ACC                    (0x2)
+#define MCF_MMU_MMUOR_RW                     (0x4)
+#define MCF_MMU_MMUOR_ADR                    (0x8)
+#define MCF_MMU_MMUOR_ITLB                   (0x10)
+#define MCF_MMU_MMUOR_CAS                    (0x20)
+#define MCF_MMU_MMUOR_CNL                    (0x40)
+#define MCF_MMU_MMUOR_CA                     (0x80)
+#define MCF_MMU_MMUOR_STLB                   (0x100)
+#define MCF_MMU_MMUOR_AA(x)                  (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_MMU_MMUSR */
+#define MCF_MMU_MMUSR_HIT                    (0x2)
+#define MCF_MMU_MMUSR_WF                     (0x8)
+#define MCF_MMU_MMUSR_RF                     (0x10)
+#define MCF_MMU_MMUSR_SPF                    (0x20)
+
+/* Bit definitions and macros for MCF_MMU_MMUAR */
+#define MCF_MMU_MMUAR_FA(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_MMU_MMUTR */
+#define MCF_MMU_MMUTR_V                      (0x1)
+#define MCF_MMU_MMUTR_SG                     (0x2)
+#define MCF_MMU_MMUTR_ID(x)                  (((x)&0xFF)<<0x2)
+#define MCF_MMU_MMUTR_VA(x)                  (((x)&0x3FFFFF)<<0xA)
+
+/* Bit definitions and macros for MCF_MMU_MMUDR */
+#define MCF_MMU_MMUDR_LK                     (0x2)
+#define MCF_MMU_MMUDR_X                      (0x4)
+#define MCF_MMU_MMUDR_W                      (0x8)
+#define MCF_MMU_MMUDR_R                      (0x10)
+#define MCF_MMU_MMUDR_SP                     (0x20)
+#define MCF_MMU_MMUDR_CM(x)                  (((x)&0x3)<<0x6)
+#define MCF_MMU_MMUDR_SZ(x)                  (((x)&0x3)<<0x8)
+#define MCF_MMU_MMUDR_PA(x)                  (((x)&0x3FFFFF)<<0xA)
+
+
+#endif /* __MCF5475_MMU_H__ */
--- a/tos/jtagwait/include/MCF5475_PAD.h
+++ b/tos/jtagwait/include/MCF5475_PAD.h
@@ -0,0 +1,233 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PAD_H__
+#define __MCF5475_PAD_H__
+
+
+/*********************************************************************
+*
+* Common GPIO
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PAD_PAR_FBCTL                    (*(volatile uint16_t*)(&_MBAR[0xA40]))
+#define MCF_PAD_PAR_FBCS                     (*(volatile uint8_t *)(&_MBAR[0xA42]))
+#define MCF_PAD_PAR_DMA                      (*(volatile uint8_t *)(&_MBAR[0xA43]))
+#define MCF_PAD_PAR_FECI2CIRQ                (*(volatile uint16_t*)(&_MBAR[0xA44]))
+#define MCF_PAD_PAR_PCIBG                    (*(volatile uint16_t*)(&_MBAR[0xA48]))
+#define MCF_PAD_PAR_PCIBR                    (*(volatile uint16_t*)(&_MBAR[0xA4A]))
+#define MCF_PAD_PAR_PSC3                     (*(volatile uint8_t *)(&_MBAR[0xA4C]))
+#define MCF_PAD_PAR_PSC2                     (*(volatile uint8_t *)(&_MBAR[0xA4D]))
+#define MCF_PAD_PAR_PSC1                     (*(volatile uint8_t *)(&_MBAR[0xA4E]))
+#define MCF_PAD_PAR_PSC0                     (*(volatile uint8_t *)(&_MBAR[0xA4F]))
+#define MCF_PAD_PAR_DSPI                     (*(volatile uint16_t*)(&_MBAR[0xA50]))
+#define MCF_PAD_PAR_TIMER                    (*(volatile uint8_t *)(&_MBAR[0xA52]))
+
+
+/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */
+#define MCF_PAD_PAR_FBCTL_PAR_ALE(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_GPIO       (0)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_TBST       (0x2)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_ALE        (0x3)
+#define MCF_PAD_PAR_FBCTL_PAR_TA             (0x4)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_GPIO       (0)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_TBST       (0x20)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_RW         (0x30)
+#define MCF_PAD_PAR_FBCTL_PAR_OE             (0x40)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE0           (0x100)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE1           (0x400)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE2           (0x1000)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE3           (0x4000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_FBCS */
+#define MCF_PAD_PAR_FBCS_PAR_CS1             (0x2)
+#define MCF_PAD_PAR_FBCS_PAR_CS2             (0x4)
+#define MCF_PAD_PAR_FBCS_PAR_CS3             (0x8)
+#define MCF_PAD_PAR_FBCS_PAR_CS4             (0x10)
+#define MCF_PAD_PAR_FBCS_PAR_CS5             (0x20)
+
+/* Bit definitions and macros for MCF_PAD_PAR_DMA */
+#define MCF_PAD_PAR_DMA_PAR_DREQ0(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_TIN0       (0x2)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0      (0x3)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1(x)         (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_IRQ1       (0x4)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_TIN1       (0x8)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1      (0xC)
+#define MCF_PAD_PAR_DMA_PAR_DACK0(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_TOUT0      (0x20)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_DACK0      (0x30)
+#define MCF_PAD_PAR_DMA_PAR_DACK1(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_TOUT1      (0x80)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_DACK1      (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_FECI2CIRQ */
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5       (0x1)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6       (0x2)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_SCL        (0x4)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_SDA        (0x8)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC(x)   (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_SCL  (0x80)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC (0xC0)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO(x)  (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x200)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO (0x300)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII      (0x400)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E17        (0x800)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC      (0x1000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO     (0x2000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII      (0x4000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E07        (0x8000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PCIBG */
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0(x)      (((x)&0x3)<<0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_TOUT0   (0x2)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0  (0x3)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1(x)      (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_TOUT1   (0x8)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1  (0xC)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2(x)      (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_TOUT2   (0x20)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2  (0x30)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3(x)      (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_TOUT3   (0x80)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3  (0xC0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4(x)      (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST    (0x200)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4  (0x300)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PCIBR */
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0(x)      (((x)&0x3)<<0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_TIN0    (0x2)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0  (0x3)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1(x)      (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_TIN1    (0x8)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1  (0xC)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2(x)      (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_TIN2    (0x20)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2  (0x30)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3(x)      (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_TIN3    (0x80)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3  (0xC0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4(x)      (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4    (0x200)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4  (0x300)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC3 */
+#define MCF_PAD_PAR_PSC3_PAR_TXD3            (0x4)
+#define MCF_PAD_PAR_PSC3_PAR_RXD3            (0x8)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_GPIO       (0)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_RTS        (0x30)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_GPIO       (0)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC2 */
+#define MCF_PAD_PAR_PSC2_PAR_TXD2            (0x4)
+#define MCF_PAD_PAR_PSC2_PAR_RXD2            (0x8)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_GPIO       (0)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_RTS        (0x30)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_GPIO       (0)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC1 */
+#define MCF_PAD_PAR_PSC1_PAR_TXD1            (0x4)
+#define MCF_PAD_PAR_PSC1_PAR_RXD1            (0x8)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_GPIO       (0)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_RTS        (0x30)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_GPIO       (0)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC0 */
+#define MCF_PAD_PAR_PSC0_PAR_TXD0            (0x4)
+#define MCF_PAD_PAR_PSC0_PAR_RXD0            (0x8)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_GPIO       (0)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_RTS        (0x30)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_GPIO       (0)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_DSPI */
+#define MCF_PAD_PAR_DSPI_PAR_SOUT(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_GPIO       (0)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_TXD        (0x2)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT       (0x3)
+#define MCF_PAD_PAR_DSPI_PAR_SIN(x)          (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_RXD         (0x8)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_SIN         (0xC)
+#define MCF_PAD_PAR_DSPI_PAR_SCK(x)          (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_BCLK        (0x10)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_CTS         (0x20)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_SCK         (0x30)
+#define MCF_PAD_PAR_DSPI_PAR_CS0(x)          (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_FSYNC       (0x40)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_RTS         (0x80)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0     (0xC0)
+#define MCF_PAD_PAR_DSPI_PAR_CS2(x)          (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_TOUT2       (0x200)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2     (0x300)
+#define MCF_PAD_PAR_DSPI_PAR_CS3(x)          (((x)&0x3)<<0xA)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_TOUT3       (0x800)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3     (0xC00)
+#define MCF_PAD_PAR_DSPI_PAR_CS5             (0x1000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_TIMER */
+#define MCF_PAD_PAR_TIMER_PAR_TOUT2          (0x1)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2(x)        (((x)&0x3)<<0x1)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2      (0x4)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2_TIN2      (0x6)
+#define MCF_PAD_PAR_TIMER_PAR_TOUT3          (0x8)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3(x)        (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3      (0x20)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3_TIN3      (0x30)
+
+
+#endif /* __MCF5475_PAD_H__ */
--- a/tos/jtagwait/include/MCF5475_PCI.h
+++ b/tos/jtagwait/include/MCF5475_PCI.h
@@ -0,0 +1,376 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PCI_H__
+#define __MCF5475_PCI_H__
+
+
+/*********************************************************************
+*
+* PCI Bus Controller (PCI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PCI_PCIIDR                       (*(volatile uint32_t*)(&_MBAR[0xB00]))
+#define MCF_PCI_PCISCR                       (*(volatile uint32_t*)(&_MBAR[0xB04]))
+#define MCF_PCI_PCICCRIR                     (*(volatile uint32_t*)(&_MBAR[0xB08]))
+#define MCF_PCI_PCICR1                       (*(volatile uint32_t*)(&_MBAR[0xB0C]))
+#define MCF_PCI_PCIBAR0                      (*(volatile uint32_t*)(&_MBAR[0xB10]))
+#define MCF_PCI_PCIBAR1                      (*(volatile uint32_t*)(&_MBAR[0xB14]))
+#define MCF_PCI_PCICCPR                      (*(volatile uint32_t*)(&_MBAR[0xB28]))
+#define MCF_PCI_PCISID                       (*(volatile uint32_t*)(&_MBAR[0xB2C]))
+#define MCF_PCI_PCICR2                       (*(volatile uint32_t*)(&_MBAR[0xB3C]))
+#define MCF_PCI_PCIGSCR                      (*(volatile uint32_t*)(&_MBAR[0xB60]))
+#define MCF_PCI_PCITBATR0                    (*(volatile uint32_t*)(&_MBAR[0xB64]))
+#define MCF_PCI_PCITBATR1                    (*(volatile uint32_t*)(&_MBAR[0xB68]))
+#define MCF_PCI_PCITCR                       (*(volatile uint32_t*)(&_MBAR[0xB6C]))
+#define MCF_PCI_PCIIW0BTAR                   (*(volatile uint32_t*)(&_MBAR[0xB70]))
+#define MCF_PCI_PCIIW1BTAR                   (*(volatile uint32_t*)(&_MBAR[0xB74]))
+#define MCF_PCI_PCIIW2BTAR                   (*(volatile uint32_t*)(&_MBAR[0xB78]))
+#define MCF_PCI_PCIIWCR                      (*(volatile uint32_t*)(&_MBAR[0xB80]))
+#define MCF_PCI_PCIICR                       (*(volatile uint32_t*)(&_MBAR[0xB84]))
+#define MCF_PCI_PCIISR                       (*(volatile uint32_t*)(&_MBAR[0xB88]))
+#define MCF_PCI_PCICAR                       (*(volatile uint32_t*)(&_MBAR[0xBF8]))
+#define MCF_PCI_PCITPSR                      (*(volatile uint32_t*)(&_MBAR[0x8400]))
+#define MCF_PCI_PCITSAR                      (*(volatile uint32_t*)(&_MBAR[0x8404]))
+#define MCF_PCI_PCITTCR                      (*(volatile uint32_t*)(&_MBAR[0x8408]))
+#define MCF_PCI_PCITER                       (*(volatile uint32_t*)(&_MBAR[0x840C]))
+#define MCF_PCI_PCITNAR                      (*(volatile uint32_t*)(&_MBAR[0x8410]))
+#define MCF_PCI_PCITLWR                      (*(volatile uint32_t*)(&_MBAR[0x8414]))
+#define MCF_PCI_PCITDCR                      (*(volatile uint32_t*)(&_MBAR[0x8418]))
+#define MCF_PCI_PCITSR                       (*(volatile uint32_t*)(&_MBAR[0x841C]))
+#define MCF_PCI_PCITFDR                      (*(volatile uint32_t*)(&_MBAR[0x8440]))
+#define MCF_PCI_PCITFSR                      (*(volatile uint32_t*)(&_MBAR[0x8444]))
+#define MCF_PCI_PCITFCR                      (*(volatile uint32_t*)(&_MBAR[0x8448]))
+#define MCF_PCI_PCITFAR                      (*(volatile uint32_t*)(&_MBAR[0x844C]))
+#define MCF_PCI_PCITFRPR                     (*(volatile uint32_t*)(&_MBAR[0x8450]))
+#define MCF_PCI_PCITFWPR                     (*(volatile uint32_t*)(&_MBAR[0x8454]))
+#define MCF_PCI_PCIRPSR                      (*(volatile uint32_t*)(&_MBAR[0x8480]))
+#define MCF_PCI_PCIRSAR                      (*(volatile uint32_t*)(&_MBAR[0x8484]))
+#define MCF_PCI_PCIRTCR                      (*(volatile uint32_t*)(&_MBAR[0x8488]))
+#define MCF_PCI_PCIRER                       (*(volatile uint32_t*)(&_MBAR[0x848C]))
+#define MCF_PCI_PCIRNAR                      (*(volatile uint32_t*)(&_MBAR[0x8490]))
+#define MCF_PCI_PCIRDCR                      (*(volatile uint32_t*)(&_MBAR[0x8498]))
+#define MCF_PCI_PCIRSR                       (*(volatile uint32_t*)(&_MBAR[0x849C]))
+#define MCF_PCI_PCIRFDR                      (*(volatile uint32_t*)(&_MBAR[0x84C0]))
+#define MCF_PCI_PCIRFSR                      (*(volatile uint32_t*)(&_MBAR[0x84C4]))
+#define MCF_PCI_PCIRFCR                      (*(volatile uint32_t*)(&_MBAR[0x84C8]))
+#define MCF_PCI_PCIRFAR                      (*(volatile uint32_t*)(&_MBAR[0x84CC]))
+#define MCF_PCI_PCIRFRPR                     (*(volatile uint32_t*)(&_MBAR[0x84D0]))
+#define MCF_PCI_PCIRFWPR                     (*(volatile uint32_t*)(&_MBAR[0x84D4]))
+
+
+/* Bit definitions and macros for MCF_PCI_PCIIDR */
+#define MCF_PCI_PCIIDR_VENDORID(x)           (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCIIDR_DEVICEID(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCISCR */
+#define MCF_PCI_PCISCR_IO                    (0x1)
+#define MCF_PCI_PCISCR_M                     (0x2)
+#define MCF_PCI_PCISCR_B                     (0x4)
+#define MCF_PCI_PCISCR_SP                    (0x8)
+#define MCF_PCI_PCISCR_MW                    (0x10)
+#define MCF_PCI_PCISCR_V                     (0x20)
+#define MCF_PCI_PCISCR_PER                   (0x40)
+#define MCF_PCI_PCISCR_ST                    (0x80)
+#define MCF_PCI_PCISCR_S                     (0x100)
+#define MCF_PCI_PCISCR_F                     (0x200)
+#define MCF_PCI_PCISCR_C                     (0x100000)
+#define MCF_PCI_PCISCR_66M                   (0x200000)
+#define MCF_PCI_PCISCR_R                     (0x400000)
+#define MCF_PCI_PCISCR_FC                    (0x800000)
+#define MCF_PCI_PCISCR_DP                    (0x1000000)
+#define MCF_PCI_PCISCR_DT(x)                 (((x)&0x3)<<0x19)
+#define MCF_PCI_PCISCR_TS                    (0x8000000)
+#define MCF_PCI_PCISCR_TR                    (0x10000000)
+#define MCF_PCI_PCISCR_MA                    (0x20000000)
+#define MCF_PCI_PCISCR_SE                    (0x40000000)
+#define MCF_PCI_PCISCR_PE                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCICCRIR */
+#define MCF_PCI_PCICCRIR_REVISIONID(x)       (((x)&0xFF)<<0)
+#define MCF_PCI_PCICCRIR_CLASSCODE(x)        (((x)&0xFFFFFF)<<0x8)
+
+/* Bit definitions and macros for MCF_PCI_PCICR1 */
+#define MCF_PCI_PCICR1_CACHELINESIZE(x)      (((x)&0xFF)<<0)
+#define MCF_PCI_PCICR1_LATTIMER(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCICR1_HEADERTYPE(x)         (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICR1_BIST(x)               (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIBAR0 */
+#define MCF_PCI_PCIBAR0_IOM                  (0x1)
+#define MCF_PCI_PCIBAR0_RANGE(x)             (((x)&0x3)<<0x1)
+#define MCF_PCI_PCIBAR0_PREF                 (0x8)
+#define MCF_PCI_PCIBAR0_BAR0(x)              (((x)&0x3FFF)<<0x12)
+
+/* Bit definitions and macros for MCF_PCI_PCIBAR1 */
+#define MCF_PCI_PCIBAR1_IOM                  (0x1)
+#define MCF_PCI_PCIBAR1_RANGE(x)             (((x)&0x3)<<0x1)
+#define MCF_PCI_PCIBAR1_PREF                 (0x8)
+#define MCF_PCI_PCIBAR1_BAR1(x)              (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_PCI_PCICCPR */
+#define MCF_PCI_PCICCPR_PCICCP(x)            (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCISID */
+#define MCF_PCI_PCISID_VENDORID(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCICR2 */
+#define MCF_PCI_PCICR2_INTLINE(x)            (((x)&0xFF)<<0)
+#define MCF_PCI_PCICR2_INTPIN(x)             (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCICR2_MINGNT(x)             (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICR2_MAXLAT(x)             (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIGSCR */
+#define MCF_PCI_PCIGSCR_PR                   (0x1)
+#define MCF_PCI_PCIGSCR_SEE                  (0x1000)
+#define MCF_PCI_PCIGSCR_PEE                  (0x2000)
+#define MCF_PCI_PCIGSCR_CLKINRESERVED(x)     (((x)&0x7)<<0x10)
+#define MCF_PCI_PCIGSCR_XLB2CLKIN(x)         (((x)&0x7)<<0x18)
+#define MCF_PCI_PCIGSCR_SE                   (0x10000000)
+#define MCF_PCI_PCIGSCR_PE                   (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITBATR0 */
+#define MCF_PCI_PCITBATR0_EN                 (0x1)
+#define MCF_PCI_PCITBATR0_BAT0(x)            (((x)&0x3FFF)<<0x12)
+
+/* Bit definitions and macros for MCF_PCI_PCITBATR1 */
+#define MCF_PCI_PCITBATR1_EN                 (0x1)
+#define MCF_PCI_PCITBATR1_BAT1(x)            (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_PCI_PCITCR */
+#define MCF_PCI_PCITCR_P                     (0x10000)
+#define MCF_PCI_PCITCR_LD                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */
+#define MCF_PCI_PCIIW0BTAR_WTA0(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW0BTAR_WAM0(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW0BTAR_WBA0(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */
+#define MCF_PCI_PCIIW1BTAR_WTA1(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW1BTAR_WAM1(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW1BTAR_WBA1(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */
+#define MCF_PCI_PCIIW2BTAR_WTA2(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW2BTAR_WAM2(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW2BTAR_WBA2(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIWCR */
+#define MCF_PCI_PCIIWCR_WINCTRL2_E           (0x100)
+#define MCF_PCI_PCIIWCR_WINCTRL2_PRC(x)      (((x)&0x3)<<0x9)
+#define MCF_PCI_PCIIWCR_WINCTRL2_IOM         (0x800)
+#define MCF_PCI_PCIIWCR_WINCTRL1_E           (0x10000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_PRC(x)      (((x)&0x3)<<0x11)
+#define MCF_PCI_PCIIWCR_WINCTRL1_IOM         (0x80000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_E           (0x1000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_PRC(x)      (((x)&0x3)<<0x19)
+#define MCF_PCI_PCIIWCR_WINCTRL0_IOM         (0x8000000)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD     (0x100)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE   (0x300)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL    (0x500)
+#define MCF_PCI_PCIIWCR_WINCTRL2_IO          (0x900)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD     (0x10000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE   (0x30000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL    (0x50000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_IO          (0x90000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD     (0x1000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE   (0x3000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL    (0x5000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_IO          (0x9000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIICR */
+#define MCF_PCI_PCIICR_MAXRETRY(x)           (((x)&0xFF)<<0)
+#define MCF_PCI_PCIICR_TAE                   (0x1000000)
+#define MCF_PCI_PCIICR_IAE                   (0x2000000)
+#define MCF_PCI_PCIICR_REE                   (0x4000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIISR */
+#define MCF_PCI_PCIISR_TA                    (0x1000000)
+#define MCF_PCI_PCIISR_IA                    (0x2000000)
+#define MCF_PCI_PCIISR_RE                    (0x4000000)
+
+/* Bit definitions and macros for MCF_PCI_PCICAR */
+#define MCF_PCI_PCICAR_DWORD(x)              (((x)&0x3F)<<0x2)
+#define MCF_PCI_PCICAR_FUNCNUM(x)            (((x)&0x7)<<0x8)
+#define MCF_PCI_PCICAR_DEVNUM(x)             (((x)&0x1F)<<0xB)
+#define MCF_PCI_PCICAR_BUSNUM(x)             (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICAR_E                     (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITPSR */
+#define MCF_PCI_PCITPSR_PKTSIZE(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCITSAR */
+#define MCF_PCI_PCITSAR_STARTADD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITTCR */
+#define MCF_PCI_PCITTCR_DI                   (0x1)
+#define MCF_PCI_PCITTCR_W                    (0x10)
+#define MCF_PCI_PCITTCR_MAXBEATS(x)          (((x)&0x7)<<0x8)
+#define MCF_PCI_PCITTCR_MAXRETRY(x)          (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCITTCR_PCICMD(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCITER */
+#define MCF_PCI_PCITER_NE                    (0x10000)
+#define MCF_PCI_PCITER_IAE                   (0x20000)
+#define MCF_PCI_PCITER_TAE                   (0x40000)
+#define MCF_PCI_PCITER_RE                    (0x80000)
+#define MCF_PCI_PCITER_SE                    (0x100000)
+#define MCF_PCI_PCITER_FEE                   (0x200000)
+#define MCF_PCI_PCITER_ME                    (0x1000000)
+#define MCF_PCI_PCITER_BE                    (0x8000000)
+#define MCF_PCI_PCITER_CM                    (0x10000000)
+#define MCF_PCI_PCITER_RF                    (0x40000000)
+#define MCF_PCI_PCITER_RC                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITNAR */
+#define MCF_PCI_PCITNAR_NEXTADDRESS(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITLWR */
+#define MCF_PCI_PCITLWR_LASTWORD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITDCR */
+#define MCF_PCI_PCITDCR_PKTSDONE(x)          (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCITDCR_BYTESDONE(x)         (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCITSR */
+#define MCF_PCI_PCITSR_IA                    (0x10000)
+#define MCF_PCI_PCITSR_TA                    (0x20000)
+#define MCF_PCI_PCITSR_RE                    (0x40000)
+#define MCF_PCI_PCITSR_SE                    (0x80000)
+#define MCF_PCI_PCITSR_FE                    (0x100000)
+#define MCF_PCI_PCITSR_BE1                   (0x200000)
+#define MCF_PCI_PCITSR_BE2                   (0x400000)
+#define MCF_PCI_PCITSR_BE3                   (0x800000)
+#define MCF_PCI_PCITSR_NT                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFDR */
+#define MCF_PCI_PCITFDR_FIFODATAWORD(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFSR */
+#define MCF_PCI_PCITFSR_EMPTY                (0x10000)
+#define MCF_PCI_PCITFSR_ALARM                (0x20000)
+#define MCF_PCI_PCITFSR_FULL                 (0x40000)
+#define MCF_PCI_PCITFSR_FR                   (0x80000)
+#define MCF_PCI_PCITFSR_OF                   (0x100000)
+#define MCF_PCI_PCITFSR_UF                   (0x200000)
+#define MCF_PCI_PCITFSR_RXW                  (0x400000)
+#define MCF_PCI_PCITFSR_FAE                  (0x800000)
+#define MCF_PCI_PCITFSR_TXW                  (0x40000000)
+#define MCF_PCI_PCITFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFCR */
+#define MCF_PCI_PCITFCR_TXW_MASK             (0x40000)
+#define MCF_PCI_PCITFCR_OF_MASK              (0x80000)
+#define MCF_PCI_PCITFCR_UF_MASK              (0x100000)
+#define MCF_PCI_PCITFCR_RXW_MASK             (0x200000)
+#define MCF_PCI_PCITFCR_FAE_MASK             (0x400000)
+#define MCF_PCI_PCITFCR_IP_MASK              (0x800000)
+#define MCF_PCI_PCITFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PCI_PCITFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFAR */
+#define MCF_PCI_PCITFAR_ALARM(x)             (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFRPR */
+#define MCF_PCI_PCITFRPR_READPTR(x)          (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFWPR */
+#define MCF_PCI_PCITFWPR_WRITEPTR(x)         (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRPSR */
+#define MCF_PCI_PCIRPSR_PKTSIZE(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCIRSAR */
+#define MCF_PCI_PCIRSAR_STARTADD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRTCR */
+#define MCF_PCI_PCIRTCR_DI                   (0x1)
+#define MCF_PCI_PCIRTCR_W                    (0x10)
+#define MCF_PCI_PCIRTCR_MAXBEATS(x)          (((x)&0x7)<<0x8)
+#define MCF_PCI_PCIRTCR_FB                   (0x1000)
+#define MCF_PCI_PCIRTCR_MAXRETRY(x)          (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIRTCR_PCICMD(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIRER */
+#define MCF_PCI_PCIRER_NE                    (0x10000)
+#define MCF_PCI_PCIRER_IAE                   (0x20000)
+#define MCF_PCI_PCIRER_TAE                   (0x40000)
+#define MCF_PCI_PCIRER_RE                    (0x80000)
+#define MCF_PCI_PCIRER_SE                    (0x100000)
+#define MCF_PCI_PCIRER_FEE                   (0x200000)
+#define MCF_PCI_PCIRER_ME                    (0x1000000)
+#define MCF_PCI_PCIRER_BE                    (0x8000000)
+#define MCF_PCI_PCIRER_CM                    (0x10000000)
+#define MCF_PCI_PCIRER_FE                    (0x20000000)
+#define MCF_PCI_PCIRER_RF                    (0x40000000)
+#define MCF_PCI_PCIRER_RC                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRNAR */
+#define MCF_PCI_PCIRNAR_NEXTADDRESS(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRDCR */
+#define MCF_PCI_PCIRDCR_PKTSDONE(x)          (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCIRDCR_BYTESDONE(x)         (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCIRSR */
+#define MCF_PCI_PCIRSR_IA                    (0x10000)
+#define MCF_PCI_PCIRSR_TA                    (0x20000)
+#define MCF_PCI_PCIRSR_RE                    (0x40000)
+#define MCF_PCI_PCIRSR_SE                    (0x80000)
+#define MCF_PCI_PCIRSR_FE                    (0x100000)
+#define MCF_PCI_PCIRSR_BE1                   (0x200000)
+#define MCF_PCI_PCIRSR_BE2                   (0x400000)
+#define MCF_PCI_PCIRSR_BE3                   (0x800000)
+#define MCF_PCI_PCIRSR_NT                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFDR */
+#define MCF_PCI_PCIRFDR_FIFODATAWORD(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFSR */
+#define MCF_PCI_PCIRFSR_EMPTY                (0x10000)
+#define MCF_PCI_PCIRFSR_ALARM                (0x20000)
+#define MCF_PCI_PCIRFSR_FULL                 (0x40000)
+#define MCF_PCI_PCIRFSR_FR                   (0x80000)
+#define MCF_PCI_PCIRFSR_OF                   (0x100000)
+#define MCF_PCI_PCIRFSR_UF                   (0x200000)
+#define MCF_PCI_PCIRFSR_RXW                  (0x400000)
+#define MCF_PCI_PCIRFSR_FAE                  (0x800000)
+#define MCF_PCI_PCIRFSR_TXW                  (0x40000000)
+#define MCF_PCI_PCIRFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFCR */
+#define MCF_PCI_PCIRFCR_TXW_MASK             (0x40000)
+#define MCF_PCI_PCIRFCR_OF_MASK              (0x80000)
+#define MCF_PCI_PCIRFCR_UF_MASK              (0x100000)
+#define MCF_PCI_PCIRFCR_RXW_MASK             (0x200000)
+#define MCF_PCI_PCIRFCR_FAE_MASK             (0x400000)
+#define MCF_PCI_PCIRFCR_IP_MASK              (0x800000)
+#define MCF_PCI_PCIRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PCI_PCIRFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFAR */
+#define MCF_PCI_PCIRFAR_ALARM(x)             (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFRPR */
+#define MCF_PCI_PCIRFRPR_READPTR(x)          (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFWPR */
+#define MCF_PCI_PCIRFWPR_WRITEPTR(x)         (((x)&0x7F)<<0)
+
+
+#endif /* __MCF5475_PCI_H__ */
--- a/tos/jtagwait/include/MCF5475_PCIARB.h
+++ b/tos/jtagwait/include/MCF5475_PCIARB.h
@@ -0,0 +1,43 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PCIARB_H__
+#define __MCF5475_PCIARB_H__
+
+
+/*********************************************************************
+*
+* PCI Bus Arbiter Module (PCIARB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PCIARB_PACR                      (*(volatile uint32_t*)(&_MBAR[0xC00]))
+#define MCF_PCIARB_PASR                      (*(volatile uint32_t*)(&_MBAR[0xC04]))
+
+
+/* Bit definitions and macros for MCF_PCIARB_PACR */
+#define MCF_PCIARB_PACR_INTMPRI              (0x1)
+#define MCF_PCIARB_PACR_EXTMPRI(x)           (((x)&0x1F)<<0x1)
+#define MCF_PCIARB_PACR_INTMINTEN            (0x10000)
+#define MCF_PCIARB_PACR_EXTMINTEN(x)         (((x)&0x1F)<<0x11)
+#define MCF_PCIARB_PACR_DS                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCIARB_PASR */
+#define MCF_PCIARB_PASR_ITLMBK               (0x10000)
+#define MCF_PCIARB_PASR_EXTMBK(x)            (((x)&0x1F)<<0x11)
+
+
+#endif /* __MCF5475_PCIARB_H__ */
--- a/tos/jtagwait/include/MCF5475_PSC.h
+++ b/tos/jtagwait/include/MCF5475_PSC.h
@@ -0,0 +1,527 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PSC_H__
+#define __MCF5475_PSC_H__
+
+
+/*********************************************************************
+*
+* Programmable Serial Controller (PSC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PSC0_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8600]))
+#define MCF_PSC0_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8600]))
+#define MCF_PSC0_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8604]))
+#define MCF_PSC0_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8604]))
+#define MCF_PSC0_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8608]))
+#define MCF_PSC0_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8610]))
+#define MCF_PSC0_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8610]))
+#define MCF_PSC0_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8614]))
+#define MCF_PSC0_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8614]))
+#define MCF_PSC0_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8618]))
+#define MCF_PSC0_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x861C]))
+#define MCF_PSC0_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8634]))
+#define MCF_PSC0_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8638]))
+#define MCF_PSC0_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x863C]))
+#define MCF_PSC0_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8640]))
+#define MCF_PSC0_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8644]))
+#define MCF_PSC0_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8648]))
+#define MCF_PSC0_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x864C]))
+#define MCF_PSC0_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8650]))
+#define MCF_PSC0_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8654]))
+#define MCF_PSC0_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8658]))
+#define MCF_PSC0_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x865C]))
+#define MCF_PSC0_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8660]))
+#define MCF_PSC0_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8664]))
+#define MCF_PSC0_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8668]))
+#define MCF_PSC0_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x866E]))
+#define MCF_PSC0_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8672]))
+#define MCF_PSC0_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8676]))
+#define MCF_PSC0_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x867A]))
+#define MCF_PSC0_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x867E]))
+#define MCF_PSC0_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8680]))
+#define MCF_PSC0_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8684]))
+#define MCF_PSC0_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8688]))
+#define MCF_PSC0_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x868E]))
+#define MCF_PSC0_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8692]))
+#define MCF_PSC0_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8696]))
+#define MCF_PSC0_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x869A]))
+#define MCF_PSC0_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x869E]))
+
+#define MCF_PSC1_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8700]))
+#define MCF_PSC1_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8700]))
+#define MCF_PSC1_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8704]))
+#define MCF_PSC1_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8704]))
+#define MCF_PSC1_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8708]))
+#define MCF_PSC1_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8710]))
+#define MCF_PSC1_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8710]))
+#define MCF_PSC1_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8714]))
+#define MCF_PSC1_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8714]))
+#define MCF_PSC1_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8718]))
+#define MCF_PSC1_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x871C]))
+#define MCF_PSC1_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8734]))
+#define MCF_PSC1_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8738]))
+#define MCF_PSC1_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x873C]))
+#define MCF_PSC1_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8740]))
+#define MCF_PSC1_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8744]))
+#define MCF_PSC1_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8748]))
+#define MCF_PSC1_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x874C]))
+#define MCF_PSC1_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8750]))
+#define MCF_PSC1_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8754]))
+#define MCF_PSC1_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8758]))
+#define MCF_PSC1_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x875C]))
+#define MCF_PSC1_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8760]))
+#define MCF_PSC1_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8764]))
+#define MCF_PSC1_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8768]))
+#define MCF_PSC1_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x876E]))
+#define MCF_PSC1_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8772]))
+#define MCF_PSC1_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8776]))
+#define MCF_PSC1_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x877A]))
+#define MCF_PSC1_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x877E]))
+#define MCF_PSC1_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8780]))
+#define MCF_PSC1_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8784]))
+#define MCF_PSC1_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8788]))
+#define MCF_PSC1_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x878E]))
+#define MCF_PSC1_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8792]))
+#define MCF_PSC1_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8796]))
+#define MCF_PSC1_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x879A]))
+#define MCF_PSC1_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x879E]))
+
+#define MCF_PSC2_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8800]))
+#define MCF_PSC2_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8800]))
+#define MCF_PSC2_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8804]))
+#define MCF_PSC2_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8804]))
+#define MCF_PSC2_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8808]))
+#define MCF_PSC2_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8810]))
+#define MCF_PSC2_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8810]))
+#define MCF_PSC2_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8814]))
+#define MCF_PSC2_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8814]))
+#define MCF_PSC2_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8818]))
+#define MCF_PSC2_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x881C]))
+#define MCF_PSC2_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8834]))
+#define MCF_PSC2_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8838]))
+#define MCF_PSC2_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x883C]))
+#define MCF_PSC2_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8840]))
+#define MCF_PSC2_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8844]))
+#define MCF_PSC2_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8848]))
+#define MCF_PSC2_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x884C]))
+#define MCF_PSC2_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8850]))
+#define MCF_PSC2_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8854]))
+#define MCF_PSC2_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8858]))
+#define MCF_PSC2_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x885C]))
+#define MCF_PSC2_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8860]))
+#define MCF_PSC2_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8864]))
+#define MCF_PSC2_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8868]))
+#define MCF_PSC2_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x886E]))
+#define MCF_PSC2_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8872]))
+#define MCF_PSC2_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8876]))
+#define MCF_PSC2_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x887A]))
+#define MCF_PSC2_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x887E]))
+#define MCF_PSC2_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8880]))
+#define MCF_PSC2_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8884]))
+#define MCF_PSC2_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8888]))
+#define MCF_PSC2_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x888E]))
+#define MCF_PSC2_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8892]))
+#define MCF_PSC2_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8896]))
+#define MCF_PSC2_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x889A]))
+#define MCF_PSC2_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x889E]))
+
+#define MCF_PSC3_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8900]))
+#define MCF_PSC3_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8900]))
+#define MCF_PSC3_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8904]))
+#define MCF_PSC3_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8904]))
+#define MCF_PSC3_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8908]))
+#define MCF_PSC3_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8910]))
+#define MCF_PSC3_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8910]))
+#define MCF_PSC3_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8914]))
+#define MCF_PSC3_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8914]))
+#define MCF_PSC3_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8918]))
+#define MCF_PSC3_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x891C]))
+#define MCF_PSC3_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8934]))
+#define MCF_PSC3_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8938]))
+#define MCF_PSC3_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x893C]))
+#define MCF_PSC3_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8940]))
+#define MCF_PSC3_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8944]))
+#define MCF_PSC3_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8948]))
+#define MCF_PSC3_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x894C]))
+#define MCF_PSC3_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8950]))
+#define MCF_PSC3_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8954]))
+#define MCF_PSC3_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8958]))
+#define MCF_PSC3_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x895C]))
+#define MCF_PSC3_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8960]))
+#define MCF_PSC3_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8964]))
+#define MCF_PSC3_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8968]))
+#define MCF_PSC3_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x896E]))
+#define MCF_PSC3_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8972]))
+#define MCF_PSC3_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8976]))
+#define MCF_PSC3_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x897A]))
+#define MCF_PSC3_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x897E]))
+#define MCF_PSC3_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8980]))
+#define MCF_PSC3_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8984]))
+#define MCF_PSC3_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8988]))
+#define MCF_PSC3_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x898E]))
+#define MCF_PSC3_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8992]))
+#define MCF_PSC3_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8996]))
+#define MCF_PSC3_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x899A]))
+#define MCF_PSC3_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x899E]))
+
+#define MCF_PSC_PSCMR(x)                     (*(volatile uint8_t *)(&_MBAR[0x8600 + ((x)*0x100)]))
+#define MCF_PSC_PSCCSR(x)                    (*(volatile uint8_t *)(&_MBAR[0x8604 + ((x)*0x100)]))
+#define MCF_PSC_PSCSR(x)                     (*(volatile uint16_t*)(&_MBAR[0x8604 + ((x)*0x100)]))
+#define MCF_PSC_PSCCR(x)                     (*(volatile uint8_t *)(&_MBAR[0x8608 + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_8BIT(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_8BIT(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_16BIT(x)               (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_16BIT(x)               (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_AC97(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_AC97(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCIPCR(x)                   (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)]))
+#define MCF_PSC_PSCACR(x)                    (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)]))
+#define MCF_PSC_PSCIMR(x)                    (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)]))
+#define MCF_PSC_PSCISR(x)                    (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)]))
+#define MCF_PSC_PSCCTUR(x)                   (*(volatile uint8_t *)(&_MBAR[0x8618 + ((x)*0x100)]))
+#define MCF_PSC_PSCCTLR(x)                   (*(volatile uint8_t *)(&_MBAR[0x861C + ((x)*0x100)]))
+#define MCF_PSC_PSCIP(x)                     (*(volatile uint8_t *)(&_MBAR[0x8634 + ((x)*0x100)]))
+#define MCF_PSC_PSCOPSET(x)                  (*(volatile uint8_t *)(&_MBAR[0x8638 + ((x)*0x100)]))
+#define MCF_PSC_PSCOPRESET(x)                (*(volatile uint8_t *)(&_MBAR[0x863C + ((x)*0x100)]))
+#define MCF_PSC_PSCSICR(x)                   (*(volatile uint8_t *)(&_MBAR[0x8640 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRCR1(x)                  (*(volatile uint8_t *)(&_MBAR[0x8644 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRCR2(x)                  (*(volatile uint8_t *)(&_MBAR[0x8648 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRSDR(x)                  (*(volatile uint8_t *)(&_MBAR[0x864C + ((x)*0x100)]))
+#define MCF_PSC_PSCIRMDR(x)                  (*(volatile uint8_t *)(&_MBAR[0x8650 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRFDR(x)                  (*(volatile uint8_t *)(&_MBAR[0x8654 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFCNT(x)                  (*(volatile uint16_t*)(&_MBAR[0x8658 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFCNT(x)                  (*(volatile uint16_t*)(&_MBAR[0x865C + ((x)*0x100)]))
+#define MCF_PSC_PSCRFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8660 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFSR(x)                   (*(volatile uint16_t*)(&_MBAR[0x8664 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8668 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFAR(x)                   (*(volatile uint16_t*)(&_MBAR[0x866E + ((x)*0x100)]))
+#define MCF_PSC_PSCRFRP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8672 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFWP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8676 + ((x)*0x100)]))
+#define MCF_PSC_PSCRLRFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x867A + ((x)*0x100)]))
+#define MCF_PSC_PSCRLWFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x867E + ((x)*0x100)]))
+#define MCF_PSC_PSCTFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8680 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFSR(x)                   (*(volatile uint16_t*)(&_MBAR[0x8684 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8688 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFAR(x)                   (*(volatile uint16_t*)(&_MBAR[0x868E + ((x)*0x100)]))
+#define MCF_PSC_PSCTFRP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8692 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFWP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8696 + ((x)*0x100)]))
+#define MCF_PSC_PSCTLRFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x869A + ((x)*0x100)]))
+#define MCF_PSC_PSCTLWFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x869E + ((x)*0x100)]))
+
+/* Bit definitions and macros for MCF_PSC_PSCMR */
+#define MCF_PSC_PSCMR_SB(x)                  (((x)&0xF)<<0)
+#define MCF_PSC_PSCMR_TXCTS                  (0x10)
+#define MCF_PSC_PSCMR_TXRTS                  (0x20)
+#define MCF_PSC_PSCMR_CM(x)                  (((x)&0x3)<<0x6)
+#define MCF_PSC_PSCMR_CM_NORMAL              (0)
+#define MCF_PSC_PSCMR_CM_ECHO                (0x40)
+#define MCF_PSC_PSCMR_CM_LOCAL_LOOP          (0x80)
+#define MCF_PSC_PSCMR_CM_REMOTE_LOOP         (0xC0)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_1         (0x7)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_15        (0x8)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_2         (0xF)
+#define MCF_PSC_PSCMR_PM_MULTI_ADDR          (0x1C)
+#define MCF_PSC_PSCMR_PM_MULTI_DATA          (0x18)
+#define MCF_PSC_PSCMR_PM_NONE                (0x10)
+#define MCF_PSC_PSCMR_PM_FORCE_HI            (0xC)
+#define MCF_PSC_PSCMR_PM_FORCE_LO            (0x8)
+#define MCF_PSC_PSCMR_PM_ODD                 (0x4)
+#define MCF_PSC_PSCMR_PM_EVEN                (0)
+#define MCF_PSC_PSCMR_BC(x)                  (((x)&0x3)<<0)
+#define MCF_PSC_PSCMR_BC_5                   (0)
+#define MCF_PSC_PSCMR_BC_6                   (0x1)
+#define MCF_PSC_PSCMR_BC_7                   (0x2)
+#define MCF_PSC_PSCMR_BC_8                   (0x3)
+#define MCF_PSC_PSCMR_PT                     (0x4)
+#define MCF_PSC_PSCMR_PM(x)                  (((x)&0x3)<<0x3)
+#define MCF_PSC_PSCMR_ERR                    (0x20)
+#define MCF_PSC_PSCMR_RXIRQ_FU               (0x40)
+#define MCF_PSC_PSCMR_RXRTS                  (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCCSR */
+#define MCF_PSC_PSCCSR_TCSEL(x)              (((x)&0xF)<<0)
+#define MCF_PSC_PSCCSR_RCSEL(x)              (((x)&0xF)<<0x4)
+#define MCF_PSC_PSCCSR_TCSEL_SYS_CLK         (0x0D)
+#define MCF_PSC_PSCCSR_TCSEL_CTM16           (0x0E)
+#define MCF_PSC_PSCCSR_TCSEL_CTM             (0x0F)
+#define MCF_PSC_PSCCSR_RCSEL_SYS_CLK         (0xD0)
+#define MCF_PSC_PSCCSR_RCSEL_CTM16           (0xE0)
+#define MCF_PSC_PSCCSR_RCSEL_CTM             (0xF0)
+
+/* Bit definitions and macros for MCF_PSC_PSCSR */
+#define MCF_PSC_PSCSR_ERR                    (0x40)
+#define MCF_PSC_PSCSR_CDE_DEOF               (0x80)
+#define MCF_PSC_PSCSR_RXRDY                  (0x100)
+#define MCF_PSC_PSCSR_FU                     (0x200)
+#define MCF_PSC_PSCSR_TXRDY                  (0x400)
+#define MCF_PSC_PSCSR_TXEMP_URERR            (0x800)
+#define MCF_PSC_PSCSR_OE                     (0x1000)
+#define MCF_PSC_PSCSR_PE_CRCERR              (0x2000)
+#define MCF_PSC_PSCSR_FE_PHYERR              (0x4000)
+#define MCF_PSC_PSCSR_RB_NEOF                (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCCR */
+#define MCF_PSC_PSCCR_RXC(x)                 (((x)&0x3)<<0)
+#define MCF_PSC_PSCCR_RX_ENABLED             (0x1)
+#define MCF_PSC_PSCCR_RX_DISABLED            (0x2)
+#define MCF_PSC_PSCCR_TXC(x)                 (((x)&0x3)<<0x2)
+#define MCF_PSC_PSCCR_TX_ENABLED             (0x4)
+#define MCF_PSC_PSCCR_TX_DISABLED            (0x8)
+#define MCF_PSC_PSCCR_MISC(x)                (((x)&0x7)<<0x4)
+#define MCF_PSC_PSCCR_NONE                   (0)
+#define MCF_PSC_PSCCR_RESET_MR               (0x10)
+#define MCF_PSC_PSCCR_RESET_RX               (0x20)
+#define MCF_PSC_PSCCR_RESET_TX               (0x30)
+#define MCF_PSC_PSCCR_RESET_ERROR            (0x40)
+#define MCF_PSC_PSCCR_RESET_BKCHGINT         (0x50)
+#define MCF_PSC_PSCCR_START_BREAK            (0x60)
+#define MCF_PSC_PSCCR_STOP_BREAK             (0x70)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_8BIT */
+#define MCF_PSC_PSCRB_8BIT_RB3(x)            (((x)&0xFF)<<0)
+#define MCF_PSC_PSCRB_8BIT_RB2(x)            (((x)&0xFF)<<0x8)
+#define MCF_PSC_PSCRB_8BIT_RB1(x)            (((x)&0xFF)<<0x10)
+#define MCF_PSC_PSCRB_8BIT_RB0(x)            (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_8BIT */
+#define MCF_PSC_PSCTB_8BIT_TB3(x)            (((x)&0xFF)<<0)
+#define MCF_PSC_PSCTB_8BIT_TB2(x)            (((x)&0xFF)<<0x8)
+#define MCF_PSC_PSCTB_8BIT_TB1(x)            (((x)&0xFF)<<0x10)
+#define MCF_PSC_PSCTB_8BIT_TB0(x)            (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_16BIT */
+#define MCF_PSC_PSCRB_16BIT_RB1(x)           (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCRB_16BIT_RB0(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_16BIT */
+#define MCF_PSC_PSCTB_16BIT_TB1(x)           (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCTB_16BIT_TB0(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_AC97 */
+#define MCF_PSC_PSCRB_AC97_SOF               (0x800)
+#define MCF_PSC_PSCRB_AC97_RB(x)             (((x)&0xFFFFF)<<0xC)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_AC97 */
+#define MCF_PSC_PSCTB_AC97_TB(x)             (((x)&0xFFFFF)<<0xC)
+
+/* Bit definitions and macros for MCF_PSC_PSCIPCR */
+#define MCF_PSC_PSCIPCR_RESERVED             (0xC)
+#define MCF_PSC_PSCIPCR_CTS                  (0xD)
+#define MCF_PSC_PSCIPCR_D_CTS                (0x1C)
+#define MCF_PSC_PSCIPCR_SYNC                 (0x8C)
+
+/* Bit definitions and macros for MCF_PSC_PSCACR */
+#define MCF_PSC_PSCACR_IEC0                  (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCIMR */
+#define MCF_PSC_PSCIMR_ERR                   (0x40)
+#define MCF_PSC_PSCIMR_DEOF                  (0x80)
+#define MCF_PSC_PSCIMR_TXRDY                 (0x100)
+#define MCF_PSC_PSCIMR_RXRDY_FU              (0x200)
+#define MCF_PSC_PSCIMR_DB                    (0x400)
+#define MCF_PSC_PSCIMR_IPC                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCISR */
+#define MCF_PSC_PSCISR_ERR                   (0x40)
+#define MCF_PSC_PSCISR_DEOF                  (0x80)
+#define MCF_PSC_PSCISR_TXRDY                 (0x100)
+#define MCF_PSC_PSCISR_RXRDY_FU              (0x200)
+#define MCF_PSC_PSCISR_DB                    (0x400)
+#define MCF_PSC_PSCISR_IPC                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCCTUR */
+#define MCF_PSC_PSCCTUR_CT(x)                (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCCTLR */
+#define MCF_PSC_PSCCTLR_CT(x)                (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCIP */
+#define MCF_PSC_PSCIP_CTS                    (0x1)
+#define MCF_PSC_PSCIP_TGL                    (0x40)
+#define MCF_PSC_PSCIP_LPWR_B                 (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCOPSET */
+#define MCF_PSC_PSCOPSET_RTS                 (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCOPRESET */
+#define MCF_PSC_PSCOPRESET_RTS               (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCSICR */
+#define MCF_PSC_PSCSICR_SIM(x)               (((x)&0x7)<<0)
+#define MCF_PSC_PSCSICR_SIM_UART             (0)
+#define MCF_PSC_PSCSICR_SIM_MODEM8           (0x1)
+#define MCF_PSC_PSCSICR_SIM_MODEM16          (0x2)
+#define MCF_PSC_PSCSICR_SIM_AC97             (0x3)
+#define MCF_PSC_PSCSICR_SIM_SIR              (0x4)
+#define MCF_PSC_PSCSICR_SIM_MIR              (0x5)
+#define MCF_PSC_PSCSICR_SIM_FIR              (0x6)
+#define MCF_PSC_PSCSICR_SHDIR                (0x10)
+#define MCF_PSC_PSCSICR_DTS1                 (0x20)
+#define MCF_PSC_PSCSICR_AWR                  (0x40)
+#define MCF_PSC_PSCSICR_ACRB                 (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRCR1 */
+#define MCF_PSC_PSCIRCR1_SPUL                (0x1)
+#define MCF_PSC_PSCIRCR1_SIPEN               (0x2)
+#define MCF_PSC_PSCIRCR1_FD                  (0x4)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRCR2 */
+#define MCF_PSC_PSCIRCR2_NXTEOF              (0x1)
+#define MCF_PSC_PSCIRCR2_ABORT               (0x2)
+#define MCF_PSC_PSCIRCR2_SIPREQ              (0x4)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRSDR */
+#define MCF_PSC_PSCIRSDR_IRSTIM(x)           (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRMDR */
+#define MCF_PSC_PSCIRMDR_M_FDIV(x)           (((x)&0x7F)<<0)
+#define MCF_PSC_PSCIRMDR_FREQ                (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRFDR */
+#define MCF_PSC_PSCIRFDR_F_FDIV(x)           (((x)&0xF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFCNT */
+#define MCF_PSC_PSCRFCNT_CNT(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFCNT */
+#define MCF_PSC_PSCTFCNT_CNT(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFDR */
+#define MCF_PSC_PSCRFDR_DATA(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFSR */
+#define MCF_PSC_PSCRFSR_EMT                  (0x1)
+#define MCF_PSC_PSCRFSR_ALARM                (0x2)
+#define MCF_PSC_PSCRFSR_FU                   (0x4)
+#define MCF_PSC_PSCRFSR_FRMRDY               (0x8)
+#define MCF_PSC_PSCRFSR_OF                   (0x10)
+#define MCF_PSC_PSCRFSR_UF                   (0x20)
+#define MCF_PSC_PSCRFSR_RXW                  (0x40)
+#define MCF_PSC_PSCRFSR_FAE                  (0x80)
+#define MCF_PSC_PSCRFSR_FRM(x)               (((x)&0xF)<<0x8)
+#define MCF_PSC_PSCRFSR_FRM_BYTE0            (0x800)
+#define MCF_PSC_PSCRFSR_FRM_BYTE1            (0x400)
+#define MCF_PSC_PSCRFSR_FRM_BYTE2            (0x200)
+#define MCF_PSC_PSCRFSR_FRM_BYTE3            (0x100)
+#define MCF_PSC_PSCRFSR_TAG(x)               (((x)&0x3)<<0xC)
+#define MCF_PSC_PSCRFSR_TXW                  (0x4000)
+#define MCF_PSC_PSCRFSR_IP                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFCR */
+#define MCF_PSC_PSCRFCR_CNTR(x)              (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCRFCR_TXW_MSK              (0x40000)
+#define MCF_PSC_PSCRFCR_OF_MSK               (0x80000)
+#define MCF_PSC_PSCRFCR_UF_MSK               (0x100000)
+#define MCF_PSC_PSCRFCR_RXW_MSK              (0x200000)
+#define MCF_PSC_PSCRFCR_FAE_MSK              (0x400000)
+#define MCF_PSC_PSCRFCR_IP_MSK               (0x800000)
+#define MCF_PSC_PSCRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PSC_PSCRFCR_FRMEN                (0x8000000)
+#define MCF_PSC_PSCRFCR_TIMER                (0x10000000)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFAR */
+#define MCF_PSC_PSCRFAR_ALARM(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFRP */
+#define MCF_PSC_PSCRFRP_READ(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFWP */
+#define MCF_PSC_PSCRFWP_WRITE(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRLRFP */
+#define MCF_PSC_PSCRLRFP_LRFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRLWFP */
+#define MCF_PSC_PSCRLWFP_LWFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFDR */
+#define MCF_PSC_PSCTFDR_DATA(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFSR */
+#define MCF_PSC_PSCTFSR_EMT                  (0x1)
+#define MCF_PSC_PSCTFSR_ALARM                (0x2)
+#define MCF_PSC_PSCTFSR_FU                   (0x4)
+#define MCF_PSC_PSCTFSR_FRMRDY               (0x8)
+#define MCF_PSC_PSCTFSR_OF                   (0x10)
+#define MCF_PSC_PSCTFSR_UF                   (0x20)
+#define MCF_PSC_PSCTFSR_RXW                  (0x40)
+#define MCF_PSC_PSCTFSR_FAE                  (0x80)
+#define MCF_PSC_PSCTFSR_FRM(x)               (((x)&0xF)<<0x8)
+#define MCF_PSC_PSCTFSR_FRM_BYTE0            (0x800)
+#define MCF_PSC_PSCTFSR_FRM_BYTE1            (0x400)
+#define MCF_PSC_PSCTFSR_FRM_BYTE2            (0x200)
+#define MCF_PSC_PSCTFSR_FRM_BYTE3            (0x100)
+#define MCF_PSC_PSCTFSR_TAG(x)               (((x)&0x3)<<0xC)
+#define MCF_PSC_PSCTFSR_TXW                  (0x4000)
+#define MCF_PSC_PSCTFSR_IP                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFCR */
+#define MCF_PSC_PSCTFCR_CNTR(x)              (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCTFCR_TXW_MSK              (0x40000)
+#define MCF_PSC_PSCTFCR_OF_MSK               (0x80000)
+#define MCF_PSC_PSCTFCR_UF_MSK               (0x100000)
+#define MCF_PSC_PSCTFCR_RXW_MSK              (0x200000)
+#define MCF_PSC_PSCTFCR_FAE_MSK              (0x400000)
+#define MCF_PSC_PSCTFCR_IP_MSK               (0x800000)
+#define MCF_PSC_PSCTFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PSC_PSCTFCR_FRMEN                (0x8000000)
+#define MCF_PSC_PSCTFCR_TIMER                (0x10000000)
+#define MCF_PSC_PSCTFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFAR */
+#define MCF_PSC_PSCTFAR_ALARM(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFRP */
+#define MCF_PSC_PSCTFRP_READ(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFWP */
+#define MCF_PSC_PSCTFWP_WRITE(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTLRFP */
+#define MCF_PSC_PSCTLRFP_LRFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTLWFP */
+#define MCF_PSC_PSCTLWFP_LWFP(x)             (((x)&0x1FF)<<0)
+
+
+#endif /* __MCF5475_PSC_H__ */
--- a/tos/jtagwait/include/MCF5475_SDRAMC.h
+++ b/tos/jtagwait/include/MCF5475_SDRAMC.h
@@ -0,0 +1,106 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SDRAMC_H__
+#define __MCF5475_SDRAMC_H__
+
+
+/*********************************************************************
+*
+* Synchronous DRAM Controller (SDRAMC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SDRAMC_SDRAMDS                   (*(volatile uint32_t*)(&_MBAR[0x4]))
+#define MCF_SDRAMC_CS0CFG                    (*(volatile uint32_t*)(&_MBAR[0x20]))
+#define MCF_SDRAMC_CS1CFG                    (*(volatile uint32_t*)(&_MBAR[0x24]))
+#define MCF_SDRAMC_CS2CFG                    (*(volatile uint32_t*)(&_MBAR[0x28]))
+#define MCF_SDRAMC_CS3CFG                    (*(volatile uint32_t*)(&_MBAR[0x2C]))
+#define MCF_SDRAMC_SDMR                      (*(volatile uint32_t*)(&_MBAR[0x100]))
+#define MCF_SDRAMC_SDCR                      (*(volatile uint32_t*)(&_MBAR[0x104]))
+#define MCF_SDRAMC_SDCFG1                    (*(volatile uint32_t*)(&_MBAR[0x108]))
+#define MCF_SDRAMC_SDCFG2                    (*(volatile uint32_t*)(&_MBAR[0x10C]))
+#define MCF_SDRAMC_CSCFG(x)                  (*(volatile uint32_t*)(&_MBAR[0x20 + ((x)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */
+#define MCF_SDRAMC_SDRAMDS_SB_D(x)           (((x)&0x3)<<0)
+#define MCF_SDRAMC_SDRAMDS_SB_S(x)           (((x)&0x3)<<0x2)
+#define MCF_SDRAMC_SDRAMDS_SB_A(x)           (((x)&0x3)<<0x4)
+#define MCF_SDRAMC_SDRAMDS_SB_C(x)           (((x)&0x3)<<0x6)
+#define MCF_SDRAMC_SDRAMDS_SB_E(x)           (((x)&0x3)<<0x8)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA        (0)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA        (0x1)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA         (0x2)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE        (0x3)
+
+/* Bit definitions and macros for MCF_SDRAMC_CSCFG */
+#define MCF_SDRAMC_CSCFG_CSSZ(x)             (((x)&0x1F)<<0)
+#define MCF_SDRAMC_CSCFG_CSSZ_DISABLED       (0)
+#define MCF_SDRAMC_CSCFG_CSSZ_1MBYTE         (0x13)
+#define MCF_SDRAMC_CSCFG_CSSZ_2MBYTE         (0x14)
+#define MCF_SDRAMC_CSCFG_CSSZ_4MBYTE         (0x15)
+#define MCF_SDRAMC_CSCFG_CSSZ_8MBYTE         (0x16)
+#define MCF_SDRAMC_CSCFG_CSSZ_16MBYTE        (0x17)
+#define MCF_SDRAMC_CSCFG_CSSZ_32MBYTE        (0x18)
+#define MCF_SDRAMC_CSCFG_CSSZ_64MBYTE        (0x19)
+#define MCF_SDRAMC_CSCFG_CSSZ_128MBYTE       (0x1A)
+#define MCF_SDRAMC_CSCFG_CSSZ_256MBYTE       (0x1B)
+#define MCF_SDRAMC_CSCFG_CSSZ_512MBYTE       (0x1C)
+#define MCF_SDRAMC_CSCFG_CSSZ_1GBYTE         (0x1D)
+#define MCF_SDRAMC_CSCFG_CSSZ_2GBYTE         (0x1E)
+#define MCF_SDRAMC_CSCFG_CSSZ_4GBYTE         (0x1F)
+#define MCF_SDRAMC_CSCFG_CSBA(x)             (((x)&0xFFF)<<0x14)
+#define MCF_SDRAMC_CSCFG_BA(x)               ((x)&0xFFF00000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDMR */
+#define MCF_SDRAMC_SDMR_CMD                  (0x10000)
+#define MCF_SDRAMC_SDMR_AD(x)                (((x)&0xFFF)<<0x12)
+#define MCF_SDRAMC_SDMR_BNKAD(x)             (((x)&0x3)<<0x1E)
+#define MCF_SDRAMC_SDMR_BK_LMR               (0)
+#define MCF_SDRAMC_SDMR_BK_LEMR              (0x40000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCR */
+#define MCF_SDRAMC_SDCR_IPALL                (0x2)
+#define MCF_SDRAMC_SDCR_IREF                 (0x4)
+#define MCF_SDRAMC_SDCR_BUFF                 (0x10)
+#define MCF_SDRAMC_SDCR_DQS_OE(x)            (((x)&0xF)<<0x8)
+#define MCF_SDRAMC_SDCR_RCNT(x)              (((x)&0x3F)<<0x10)
+#define MCF_SDRAMC_SDCR_DRIVE                (0x400000)
+#define MCF_SDRAMC_SDCR_AP                   (0x800000)
+#define MCF_SDRAMC_SDCR_MUX(x)               (((x)&0x3)<<0x18)
+#define MCF_SDRAMC_SDCR_REF                  (0x10000000)
+#define MCF_SDRAMC_SDCR_DDR                  (0x20000000)
+#define MCF_SDRAMC_SDCR_CKE                  (0x40000000)
+#define MCF_SDRAMC_SDCR_MODE_EN              (0x80000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
+#define MCF_SDRAMC_SDCFG1_WTLAT(x)           (((x)&0x7)<<0x4)
+#define MCF_SDRAMC_SDCFG1_REF2ACT(x)         (((x)&0xF)<<0x8)
+#define MCF_SDRAMC_SDCFG1_PRE2ACT(x)         (((x)&0x7)<<0xC)
+#define MCF_SDRAMC_SDCFG1_ACT2RW(x)          (((x)&0x7)<<0x10)
+#define MCF_SDRAMC_SDCFG1_RDLAT(x)           (((x)&0xF)<<0x14)
+#define MCF_SDRAMC_SDCFG1_SWT2RD(x)          (((x)&0x7)<<0x18)
+#define MCF_SDRAMC_SDCFG1_SRD2RW(x)          (((x)&0xF)<<0x1C)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
+#define MCF_SDRAMC_SDCFG2_BL(x)              (((x)&0xF)<<0x10)
+#define MCF_SDRAMC_SDCFG2_BRD2WT(x)          (((x)&0xF)<<0x14)
+#define MCF_SDRAMC_SDCFG2_BWT2RW(x)          (((x)&0xF)<<0x18)
+#define MCF_SDRAMC_SDCFG2_BRD2PRE(x)         (((x)&0xF)<<0x1C)
+
+
+#endif /* __MCF5475_SDRAMC_H__ */
--- a/tos/jtagwait/include/MCF5475_SEC.h
+++ b/tos/jtagwait/include/MCF5475_SEC.h
@@ -0,0 +1,398 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SEC_H__
+#define __MCF5475_SEC_H__
+
+
+/*********************************************************************
+*
+* Integrated Security Engine (SEC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SEC_EUACRH                       (*(volatile uint32_t*)(&_MBAR[0x21000]))
+#define MCF_SEC_EUACRL                       (*(volatile uint32_t*)(&_MBAR[0x21004]))
+#define MCF_SEC_SIMRH                        (*(volatile uint32_t*)(&_MBAR[0x21008]))
+#define MCF_SEC_SIMRL                        (*(volatile uint32_t*)(&_MBAR[0x2100C]))
+#define MCF_SEC_SISRH                        (*(volatile uint32_t*)(&_MBAR[0x21010]))
+#define MCF_SEC_SISRL                        (*(volatile uint32_t*)(&_MBAR[0x21014]))
+#define MCF_SEC_SICRH                        (*(volatile uint32_t*)(&_MBAR[0x21018]))
+#define MCF_SEC_SICRL                        (*(volatile uint32_t*)(&_MBAR[0x2101C]))
+#define MCF_SEC_SIDR                         (*(volatile uint32_t*)(&_MBAR[0x21020]))
+#define MCF_SEC_EUASRH                       (*(volatile uint32_t*)(&_MBAR[0x21028]))
+#define MCF_SEC_EUASRL                       (*(volatile uint32_t*)(&_MBAR[0x2102C]))
+#define MCF_SEC_SMCR                         (*(volatile uint32_t*)(&_MBAR[0x21030]))
+#define MCF_SEC_MEAR                         (*(volatile uint32_t*)(&_MBAR[0x21038]))
+#define MCF_SEC_CCCR0                        (*(volatile uint32_t*)(&_MBAR[0x2200C]))
+#define MCF_SEC_CCPSRH0                      (*(volatile uint32_t*)(&_MBAR[0x22010]))
+#define MCF_SEC_CCPSRL0                      (*(volatile uint32_t*)(&_MBAR[0x22014]))
+#define MCF_SEC_CDPR0                        (*(volatile uint32_t*)(&_MBAR[0x22044]))
+#define MCF_SEC_FR0                          (*(volatile uint32_t*)(&_MBAR[0x2204C]))
+#define MCF_SEC_CCCR1                        (*(volatile uint32_t*)(&_MBAR[0x2300C]))
+#define MCF_SEC_CCPSRH1                      (*(volatile uint32_t*)(&_MBAR[0x23010]))
+#define MCF_SEC_CCPSRL1                      (*(volatile uint32_t*)(&_MBAR[0x23014]))
+#define MCF_SEC_CDPR1                        (*(volatile uint32_t*)(&_MBAR[0x23044]))
+#define MCF_SEC_FR1                          (*(volatile uint32_t*)(&_MBAR[0x2304C]))
+#define MCF_SEC_AFRCR                        (*(volatile uint32_t*)(&_MBAR[0x28018]))
+#define MCF_SEC_AFSR                         (*(volatile uint32_t*)(&_MBAR[0x28028]))
+#define MCF_SEC_AFISR                        (*(volatile uint32_t*)(&_MBAR[0x28030]))
+#define MCF_SEC_AFIMR                        (*(volatile uint32_t*)(&_MBAR[0x28038]))
+#define MCF_SEC_DRCR                         (*(volatile uint32_t*)(&_MBAR[0x2A018]))
+#define MCF_SEC_DSR                          (*(volatile uint32_t*)(&_MBAR[0x2A028]))
+#define MCF_SEC_DISR                         (*(volatile uint32_t*)(&_MBAR[0x2A030]))
+#define MCF_SEC_DIMR                         (*(volatile uint32_t*)(&_MBAR[0x2A038]))
+#define MCF_SEC_MDRCR                        (*(volatile uint32_t*)(&_MBAR[0x2C018]))
+#define MCF_SEC_MDSR                         (*(volatile uint32_t*)(&_MBAR[0x2C028]))
+#define MCF_SEC_MDISR                        (*(volatile uint32_t*)(&_MBAR[0x2C030]))
+#define MCF_SEC_MDIMR                        (*(volatile uint32_t*)(&_MBAR[0x2C038]))
+#define MCF_SEC_RNGRCR                       (*(volatile uint32_t*)(&_MBAR[0x2E018]))
+#define MCF_SEC_RNGSR                        (*(volatile uint32_t*)(&_MBAR[0x2E028]))
+#define MCF_SEC_RNGISR                       (*(volatile uint32_t*)(&_MBAR[0x2E030]))
+#define MCF_SEC_RNGIMR                       (*(volatile uint32_t*)(&_MBAR[0x2E038]))
+#define MCF_SEC_AESRCR                       (*(volatile uint32_t*)(&_MBAR[0x32018]))
+#define MCF_SEC_AESSR                        (*(volatile uint32_t*)(&_MBAR[0x32028]))
+#define MCF_SEC_AESISR                       (*(volatile uint32_t*)(&_MBAR[0x32030]))
+#define MCF_SEC_AESIMR                       (*(volatile uint32_t*)(&_MBAR[0x32038]))
+#define MCF_SEC_CCCRn(x)                     (*(volatile uint32_t*)(&_MBAR[0x2200C + ((x)*0x1000)]))
+#define MCF_SEC_CCPSRHn(x)                   (*(volatile uint32_t*)(&_MBAR[0x22010 + ((x)*0x1000)]))
+#define MCF_SEC_CCPSRLn(x)                   (*(volatile uint32_t*)(&_MBAR[0x22014 + ((x)*0x1000)]))
+#define MCF_SEC_CDPRn(x)                     (*(volatile uint32_t*)(&_MBAR[0x22044 + ((x)*0x1000)]))
+#define MCF_SEC_FRn(x)                       (*(volatile uint32_t*)(&_MBAR[0x2204C + ((x)*0x1000)]))
+
+
+/* Bit definitions and macros for MCF_SEC_EUACRH */
+#define MCF_SEC_EUACRH_AFEU(x)               (((x)&0xF)<<0)
+#define MCF_SEC_EUACRH_AFFEU_NOASSIGN        (0)
+#define MCF_SEC_EUACRH_AFFEU_CHA0            (0x1)
+#define MCF_SEC_EUACRH_AFFEU_CHA1            (0x2)
+#define MCF_SEC_EUACRH_MDEU(x)               (((x)&0xF)<<0x8)
+#define MCF_SEC_EUACRH_MDEU_NOASSIGN         (0)
+#define MCF_SEC_EUACRH_MDEU_CHA0             (0x100)
+#define MCF_SEC_EUACRH_MDEU_CHA1             (0x200)
+#define MCF_SEC_EUACRH_RNG(x)                (((x)&0xF)<<0x18)
+#define MCF_SEC_EUACRH_RNG_NOASSIGN          (0)
+#define MCF_SEC_EUACRH_RNG_CHA0              (0x1000000)
+#define MCF_SEC_EUACRH_RNG_CHA1              (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_EUACRL */
+#define MCF_SEC_EUACRL_AESU(x)               (((x)&0xF)<<0x10)
+#define MCF_SEC_EUACRL_AESU_NOASSIGN         (0)
+#define MCF_SEC_EUACRL_AESU_CHA0             (0x10000)
+#define MCF_SEC_EUACRL_AESU_CHA1             (0x20000)
+#define MCF_SEC_EUACRL_DEU(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_SIMRH */
+#define MCF_SEC_SIMRH_AERR                   (0x8000000)
+#define MCF_SEC_SIMRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SIMRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SIMRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SIMRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SIMRL */
+#define MCF_SEC_SIMRL_TEA                    (0x40)
+#define MCF_SEC_SIMRL_DEU_DN                 (0x100)
+#define MCF_SEC_SIMRL_DEU_ERR                (0x200)
+#define MCF_SEC_SIMRL_AESU_DN                (0x1000)
+#define MCF_SEC_SIMRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SIMRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SIMRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SIMRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SIMRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SIMRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SIMRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SISRH */
+#define MCF_SEC_SISRH_AERR                   (0x8000000)
+#define MCF_SEC_SISRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SISRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SISRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SISRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SISRL */
+#define MCF_SEC_SISRL_TEA                    (0x40)
+#define MCF_SEC_SISRL_DEU_DN                 (0x100)
+#define MCF_SEC_SISRL_DEU_ERR                (0x200)
+#define MCF_SEC_SISRL_AESU_DN                (0x1000)
+#define MCF_SEC_SISRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SISRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SISRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SISRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SISRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SISRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SISRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SICRH */
+#define MCF_SEC_SICRH_AERR                   (0x8000000)
+#define MCF_SEC_SICRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SICRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SICRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SICRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SICRL */
+#define MCF_SEC_SICRL_TEA                    (0x40)
+#define MCF_SEC_SICRL_DEU_DN                 (0x100)
+#define MCF_SEC_SICRL_DEU_ERR                (0x200)
+#define MCF_SEC_SICRL_AESU_DN                (0x1000)
+#define MCF_SEC_SICRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SICRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SICRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SICRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SICRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SICRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SICRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SIDR */
+#define MCF_SEC_SIDR_VERSION(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_EUASRH */
+#define MCF_SEC_EUASRH_AFEU(x)               (((x)&0xF)<<0)
+#define MCF_SEC_EUASRH_MDEU(x)               (((x)&0xF)<<0x8)
+#define MCF_SEC_EUASRH_RNG(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_EUASRL */
+#define MCF_SEC_EUASRL_AESU(x)               (((x)&0xF)<<0x10)
+#define MCF_SEC_EUASRL_DEU(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_SMCR */
+#define MCF_SEC_SMCR_CURR_CHAN(x)            (((x)&0xF)<<0x4)
+#define MCF_SEC_SMCR_CURR_CHAN_1             (0x10)
+#define MCF_SEC_SMCR_CURR_CHAN_2             (0x20)
+#define MCF_SEC_SMCR_SWR                     (0x1000000)
+
+/* Bit definitions and macros for MCF_SEC_MEAR */
+#define MCF_SEC_MEAR_ADDRESS(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_CCCRn */
+#define MCF_SEC_CCCRn_RST                    (0x1)
+#define MCF_SEC_CCCRn_CDIE                   (0x2)
+#define MCF_SEC_CCCRn_NT                     (0x4)
+#define MCF_SEC_CCCRn_NE                     (0x8)
+#define MCF_SEC_CCCRn_WE                     (0x10)
+#define MCF_SEC_CCCRn_BURST_SIZE(x)          (((x)&0x7)<<0x8)
+#define MCF_SEC_CCCRn_BURST_SIZE_2           (0)
+#define MCF_SEC_CCCRn_BURST_SIZE_8           (0x100)
+#define MCF_SEC_CCCRn_BURST_SIZE_16          (0x200)
+#define MCF_SEC_CCCRn_BURST_SIZE_24          (0x300)
+#define MCF_SEC_CCCRn_BURST_SIZE_32          (0x400)
+#define MCF_SEC_CCCRn_BURST_SIZE_40          (0x500)
+#define MCF_SEC_CCCRn_BURST_SIZE_48          (0x600)
+#define MCF_SEC_CCCRn_BURST_SIZE_56          (0x700)
+
+/* Bit definitions and macros for MCF_SEC_CCPSRHn */
+#define MCF_SEC_CCPSRHn_STATE(x)             (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_CCPSRLn */
+#define MCF_SEC_CCPSRLn_PAIR_PTR(x)          (((x)&0xFF)<<0)
+#define MCF_SEC_CCPSRLn_EUERR                (0x100)
+#define MCF_SEC_CCPSRLn_SERR                 (0x200)
+#define MCF_SEC_CCPSRLn_DERR                 (0x400)
+#define MCF_SEC_CCPSRLn_PERR                 (0x1000)
+#define MCF_SEC_CCPSRLn_TEA                  (0x2000)
+#define MCF_SEC_CCPSRLn_SD                   (0x10000)
+#define MCF_SEC_CCPSRLn_PD                   (0x20000)
+#define MCF_SEC_CCPSRLn_SRD                  (0x40000)
+#define MCF_SEC_CCPSRLn_PRD                  (0x80000)
+#define MCF_SEC_CCPSRLn_SG                   (0x100000)
+#define MCF_SEC_CCPSRLn_PG                   (0x200000)
+#define MCF_SEC_CCPSRLn_SR                   (0x400000)
+#define MCF_SEC_CCPSRLn_PR                   (0x800000)
+#define MCF_SEC_CCPSRLn_MO                   (0x1000000)
+#define MCF_SEC_CCPSRLn_MI                   (0x2000000)
+#define MCF_SEC_CCPSRLn_STAT                 (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_CDPRn */
+#define MCF_SEC_CDPRn_CDP(x)                 (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_FRn */
+#define MCF_SEC_FRn_FETCH_ADDR(x)            (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_AFRCR */
+#define MCF_SEC_AFRCR_SR                     (0x1000000)
+#define MCF_SEC_AFRCR_MI                     (0x2000000)
+#define MCF_SEC_AFRCR_RI                     (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_AFSR */
+#define MCF_SEC_AFSR_RD                      (0x1000000)
+#define MCF_SEC_AFSR_ID                      (0x2000000)
+#define MCF_SEC_AFSR_IE                      (0x4000000)
+#define MCF_SEC_AFSR_OFR                     (0x8000000)
+#define MCF_SEC_AFSR_IFW                     (0x10000000)
+#define MCF_SEC_AFSR_HALT                    (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_AFISR */
+#define MCF_SEC_AFISR_DSE                    (0x10000)
+#define MCF_SEC_AFISR_KSE                    (0x20000)
+#define MCF_SEC_AFISR_CE                     (0x40000)
+#define MCF_SEC_AFISR_ERE                    (0x80000)
+#define MCF_SEC_AFISR_IE                     (0x100000)
+#define MCF_SEC_AFISR_OFU                    (0x2000000)
+#define MCF_SEC_AFISR_IFO                    (0x4000000)
+#define MCF_SEC_AFISR_IFE                    (0x10000000)
+#define MCF_SEC_AFISR_OFE                    (0x20000000)
+#define MCF_SEC_AFISR_AE                     (0x40000000)
+#define MCF_SEC_AFISR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AFIMR */
+#define MCF_SEC_AFIMR_DSE                    (0x10000)
+#define MCF_SEC_AFIMR_KSE                    (0x20000)
+#define MCF_SEC_AFIMR_CE                     (0x40000)
+#define MCF_SEC_AFIMR_ERE                    (0x80000)
+#define MCF_SEC_AFIMR_IE                     (0x100000)
+#define MCF_SEC_AFIMR_OFU                    (0x2000000)
+#define MCF_SEC_AFIMR_IFO                    (0x4000000)
+#define MCF_SEC_AFIMR_IFE                    (0x10000000)
+#define MCF_SEC_AFIMR_OFE                    (0x20000000)
+#define MCF_SEC_AFIMR_AE                     (0x40000000)
+#define MCF_SEC_AFIMR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_DRCR */
+#define MCF_SEC_DRCR_SR                      (0x1000000)
+#define MCF_SEC_DRCR_MI                      (0x2000000)
+#define MCF_SEC_DRCR_RI                      (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_DSR */
+#define MCF_SEC_DSR_RD                       (0x1000000)
+#define MCF_SEC_DSR_ID                       (0x2000000)
+#define MCF_SEC_DSR_IE                       (0x4000000)
+#define MCF_SEC_DSR_OFR                      (0x8000000)
+#define MCF_SEC_DSR_IFW                      (0x10000000)
+#define MCF_SEC_DSR_HALT                     (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_DISR */
+#define MCF_SEC_DISR_DSE                     (0x10000)
+#define MCF_SEC_DISR_KSE                     (0x20000)
+#define MCF_SEC_DISR_CE                      (0x40000)
+#define MCF_SEC_DISR_ERE                     (0x80000)
+#define MCF_SEC_DISR_IE                      (0x100000)
+#define MCF_SEC_DISR_KPE                     (0x200000)
+#define MCF_SEC_DISR_OFU                     (0x2000000)
+#define MCF_SEC_DISR_IFO                     (0x4000000)
+#define MCF_SEC_DISR_IFE                     (0x10000000)
+#define MCF_SEC_DISR_OFE                     (0x20000000)
+#define MCF_SEC_DISR_AE                      (0x40000000)
+#define MCF_SEC_DISR_ME                      (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_DIMR */
+#define MCF_SEC_DIMR_DSE                     (0x10000)
+#define MCF_SEC_DIMR_KSE                     (0x20000)
+#define MCF_SEC_DIMR_CE                      (0x40000)
+#define MCF_SEC_DIMR_ERE                     (0x80000)
+#define MCF_SEC_DIMR_IE                      (0x100000)
+#define MCF_SEC_DIMR_KPE                     (0x200000)
+#define MCF_SEC_DIMR_OFU                     (0x2000000)
+#define MCF_SEC_DIMR_IFO                     (0x4000000)
+#define MCF_SEC_DIMR_IFE                     (0x10000000)
+#define MCF_SEC_DIMR_OFE                     (0x20000000)
+#define MCF_SEC_DIMR_AE                      (0x40000000)
+#define MCF_SEC_DIMR_ME                      (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_MDRCR */
+#define MCF_SEC_MDRCR_SR                     (0x1000000)
+#define MCF_SEC_MDRCR_MI                     (0x2000000)
+#define MCF_SEC_MDRCR_RI                     (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_MDSR */
+#define MCF_SEC_MDSR_RD                      (0x1000000)
+#define MCF_SEC_MDSR_ID                      (0x2000000)
+#define MCF_SEC_MDSR_IE                      (0x4000000)
+#define MCF_SEC_MDSR_IFW                     (0x10000000)
+#define MCF_SEC_MDSR_HALT                    (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_MDISR */
+#define MCF_SEC_MDISR_DSE                    (0x10000)
+#define MCF_SEC_MDISR_KSE                    (0x20000)
+#define MCF_SEC_MDISR_CE                     (0x40000)
+#define MCF_SEC_MDISR_ERE                    (0x80000)
+#define MCF_SEC_MDISR_IE                     (0x100000)
+#define MCF_SEC_MDISR_IFO                    (0x4000000)
+#define MCF_SEC_MDISR_AE                     (0x40000000)
+#define MCF_SEC_MDISR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_MDIMR */
+#define MCF_SEC_MDIMR_DSE                    (0x10000)
+#define MCF_SEC_MDIMR_KSE                    (0x20000)
+#define MCF_SEC_MDIMR_CE                     (0x40000)
+#define MCF_SEC_MDIMR_ERE                    (0x80000)
+#define MCF_SEC_MDIMR_IE                     (0x100000)
+#define MCF_SEC_MDIMR_IFO                    (0x4000000)
+#define MCF_SEC_MDIMR_AE                     (0x40000000)
+#define MCF_SEC_MDIMR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGRCR */
+#define MCF_SEC_RNGRCR_SR                    (0x1000000)
+#define MCF_SEC_RNGRCR_MI                    (0x2000000)
+#define MCF_SEC_RNGRCR_RI                    (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGSR */
+#define MCF_SEC_RNGSR_RD                     (0x1000000)
+#define MCF_SEC_RNGSR_IE                     (0x4000000)
+#define MCF_SEC_RNGSR_OFR                    (0x8000000)
+#define MCF_SEC_RNGSR_HALT                   (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGISR */
+#define MCF_SEC_RNGISR_IE                    (0x100000)
+#define MCF_SEC_RNGISR_OFU                   (0x2000000)
+#define MCF_SEC_RNGISR_AE                    (0x40000000)
+#define MCF_SEC_RNGISR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGIMR */
+#define MCF_SEC_RNGIMR_IE                    (0x100000)
+#define MCF_SEC_RNGIMR_OFU                   (0x2000000)
+#define MCF_SEC_RNGIMR_AE                    (0x40000000)
+#define MCF_SEC_RNGIMR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AESRCR */
+#define MCF_SEC_AESRCR_SR                    (0x1000000)
+#define MCF_SEC_AESRCR_MI                    (0x2000000)
+#define MCF_SEC_AESRCR_RI                    (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_AESSR */
+#define MCF_SEC_AESSR_RD                     (0x1000000)
+#define MCF_SEC_AESSR_ID                     (0x2000000)
+#define MCF_SEC_AESSR_IE                     (0x4000000)
+#define MCF_SEC_AESSR_OFR                    (0x8000000)
+#define MCF_SEC_AESSR_IFW                    (0x10000000)
+#define MCF_SEC_AESSR_HALT                   (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_AESISR */
+#define MCF_SEC_AESISR_DSE                   (0x10000)
+#define MCF_SEC_AESISR_KSE                   (0x20000)
+#define MCF_SEC_AESISR_CE                    (0x40000)
+#define MCF_SEC_AESISR_ERE                   (0x80000)
+#define MCF_SEC_AESISR_IE                    (0x100000)
+#define MCF_SEC_AESISR_OFU                   (0x2000000)
+#define MCF_SEC_AESISR_IFO                   (0x4000000)
+#define MCF_SEC_AESISR_IFE                   (0x10000000)
+#define MCF_SEC_AESISR_OFE                   (0x20000000)
+#define MCF_SEC_AESISR_AE                    (0x40000000)
+#define MCF_SEC_AESISR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AESIMR */
+#define MCF_SEC_AESIMR_DSE                   (0x10000)
+#define MCF_SEC_AESIMR_KSE                   (0x20000)
+#define MCF_SEC_AESIMR_CE                    (0x40000)
+#define MCF_SEC_AESIMR_ERE                   (0x80000)
+#define MCF_SEC_AESIMR_IE                    (0x100000)
+#define MCF_SEC_AESIMR_OFU                   (0x2000000)
+#define MCF_SEC_AESIMR_IFO                   (0x4000000)
+#define MCF_SEC_AESIMR_IFE                   (0x10000000)
+#define MCF_SEC_AESIMR_OFE                   (0x20000000)
+#define MCF_SEC_AESIMR_AE                    (0x40000000)
+#define MCF_SEC_AESIMR_ME                    (0x80000000)
+
+
+#endif /* __MCF5475_SEC_H__ */
--- a/tos/jtagwait/include/MCF5475_SIU.h
+++ b/tos/jtagwait/include/MCF5475_SIU.h
@@ -0,0 +1,67 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SIU_H__
+#define __MCF5475_SIU_H__
+
+
+/*********************************************************************
+*
+* System Integration Unit (SIU)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SIU_SBCR                         (*(volatile uint32_t*)(&_MBAR[0x10]))
+#define MCF_SIU_SECSACR                      (*(volatile uint32_t*)(&_MBAR[0x38]))
+#define MCF_SIU_RSR                          (*(volatile uint32_t*)(&_MBAR[0x44]))
+#define MCF_SIU_JTAGID                       (*(volatile uint32_t*)(&_MBAR[0x50]))
+
+
+/* Bit definitions and macros for MCF_SIU_SBCR */
+#define MCF_SIU_SBCR_PIN2DSPI                (0x8000000)
+#define MCF_SIU_SBCR_DMA2CPU                 (0x10000000)
+#define MCF_SIU_SBCR_CPU2DMA                 (0x20000000)
+#define MCF_SIU_SBCR_PIN2DMA                 (0x40000000)
+#define MCF_SIU_SBCR_PIN2CPU                 (0x80000000)
+
+/* Bit definitions and macros for MCF_SIU_SECSACR */
+#define MCF_SIU_SECSACR_SEQEN                (0x1)
+
+/* Bit definitions and macros for MCF_SIU_RSR */
+#define MCF_SIU_RSR_RST                      (0x1)
+#define MCF_SIU_RSR_RSTWD                    (0x2)
+#define MCF_SIU_RSR_RSTJTG                   (0x8)
+
+/* Bit definitions and macros for MCF_SIU_JTAGID */
+#define MCF_SIU_JTAGID_JTAGID(x)             (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SIU_JTAGID */
+#define MCF_SIU_JTAGID_REV          (0xF0000000)
+#define MCF_SIU_JTAGID_PROCESSOR    (0x0FFFFFFF)
+#define MCF_SIU_JTAGID_MCF5485      (0x0800C01D)
+#define MCF_SIU_JTAGID_MCF5484      (0x0800D01D)
+#define MCF_SIU_JTAGID_MCF5483      (0x0800E01D)
+#define MCF_SIU_JTAGID_MCF5482      (0x0800F01D)
+#define MCF_SIU_JTAGID_MCF5481      (0x0801001D)
+#define MCF_SIU_JTAGID_MCF5480      (0x0801101D)
+#define MCF_SIU_JTAGID_MCF5475      (0x0801201D)
+#define MCF_SIU_JTAGID_MCF5474      (0x0801301D)
+#define MCF_SIU_JTAGID_MCF5473      (0x0801401D)
+#define MCF_SIU_JTAGID_MCF5472      (0x0801501D)
+#define MCF_SIU_JTAGID_MCF5471      (0x0801601D)
+#define MCF_SIU_JTAGID_MCF5470      (0x0801701D)
+
+#endif /* __MCF5475_SIU_H__ */
--- a/tos/jtagwait/include/MCF5475_SLT.h
+++ b/tos/jtagwait/include/MCF5475_SLT.h
@@ -0,0 +1,59 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SLT_H__
+#define __MCF5475_SLT_H__
+
+
+/*********************************************************************
+*
+* Slice Timers (SLT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SLT0_STCNT                       (*(volatile uint32_t*)(&_MBAR[0x900]))
+#define MCF_SLT0_SCR                         (*(volatile uint32_t*)(&_MBAR[0x904]))
+#define MCF_SLT0_SCNT                        (*(volatile uint32_t*)(&_MBAR[0x908]))
+#define MCF_SLT0_SSR                         (*(volatile uint32_t*)(&_MBAR[0x90C]))
+
+#define MCF_SLT1_STCNT                       (*(volatile uint32_t*)(&_MBAR[0x910]))
+#define MCF_SLT1_SCR                         (*(volatile uint32_t*)(&_MBAR[0x914]))
+#define MCF_SLT1_SCNT                        (*(volatile uint32_t*)(&_MBAR[0x918]))
+#define MCF_SLT1_SSR                         (*(volatile uint32_t*)(&_MBAR[0x91C]))
+
+#define MCF_SLT_STCNT(x)                     (*(volatile uint32_t*)(&_MBAR[0x900 + ((x)*0x10)]))
+#define MCF_SLT_SCR(x)                       (*(volatile uint32_t*)(&_MBAR[0x904 + ((x)*0x10)]))
+#define MCF_SLT_SCNT(x)                      (*(volatile int32_t*)(&_MBAR[0x908 + ((x)*0x10)]))
+#define MCF_SLT_SSR(x)                       (*(volatile uint32_t*)(&_MBAR[0x90C + ((x)*0x10)]))
+
+
+/* Bit definitions and macros for MCF_SLT_STCNT */
+#define MCF_SLT_STCNT_TC(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SLT_SCR */
+#define MCF_SLT_SCR_TEN                      (0x1000000)
+#define MCF_SLT_SCR_IEN                      (0x2000000)
+#define MCF_SLT_SCR_RUN                      (0x4000000)
+
+/* Bit definitions and macros for MCF_SLT_SCNT */
+#define MCF_SLT_SCNT_CNT(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SLT_SSR */
+#define MCF_SLT_SSR_ST                       (0x1000000)
+#define MCF_SLT_SSR_BE                       (0x2000000)
+
+
+#endif /* __MCF5475_SLT_H__ */
--- a/tos/jtagwait/include/MCF5475_SRAM.h
+++ b/tos/jtagwait/include/MCF5475_SRAM.h
@@ -0,0 +1,62 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SRAM_H__
+#define __MCF5475_SRAM_H__
+
+
+/*********************************************************************
+*
+* System SRAM Module (SRAM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SRAM_SSCR                        (*(volatile uint32_t*)(&__MBAR[0x1FFC0]))
+#define MCF_SRAM_TCCR                        (*(volatile uint32_t*)(&__MBAR[0x1FFC4]))
+#define MCF_SRAM_TCCRDR                      (*(volatile uint32_t*)(&__MBAR[0x1FFC8]))
+#define MCF_SRAM_TCCRDW                      (*(volatile uint32_t*)(&__MBAR[0x1FFCC]))
+#define MCF_SRAM_TCCRSEC                     (*(volatile uint32_t*)(&__MBAR[0x1FFD0]))
+
+
+/* Bit definitions and macros for MCF_SRAM_SSCR */
+#define MCF_SRAM_SSCR_INLV                   (0x10000)
+
+/* Bit definitions and macros for MCF_SRAM_TCCR */
+#define MCF_SRAM_TCCR_BANK0_TC(x)            (((x)&0xF)<<0)
+#define MCF_SRAM_TCCR_BANK1_TC(x)            (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCR_BANK2_TC(x)            (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCR_BANK3_TC(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SRAM_TCCRDR */
+#define MCF_SRAM_TCCRDR_BANK0_TC(x)          (((x)&0xF)<<0)
+#define MCF_SRAM_TCCRDR_BANK1_TC(x)          (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCRDR_BANK2_TC(x)          (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCRDR_BANK3_TC(x)          (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SRAM_TCCRDW */
+#define MCF_SRAM_TCCRDW_BANK0_TC(x)          (((x)&0xF)<<0)
+#define MCF_SRAM_TCCRDW_BANK1_TC(x)          (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCRDW_BANK2_TC(x)          (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCRDW_BANK3_TC(x)          (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SRAM_TCCRSEC */
+#define MCF_SRAM_TCCRSEC_BANK0_TC(x)         (((x)&0xF)<<0)
+#define MCF_SRAM_TCCRSEC_BANK1_TC(x)         (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCRSEC_BANK2_TC(x)         (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCRSEC_BANK3_TC(x)         (((x)&0xF)<<0x18)
+
+
+#endif /* __MCF5475_SRAM_H__ */
--- a/tos/jtagwait/include/MCF5475_USB.h
+++ b/tos/jtagwait/include/MCF5475_USB.h
@@ -0,0 +1,554 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_USB_H__
+#define __MCF5475_USB_H__
+
+
+/*********************************************************************
+*
+* Universal Serial Bus Interface (USB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_USB_USBAISR                      (*(volatile uint8_t *)(&__MBAR[0xB000]))
+#define MCF_USB_USBAIMR                      (*(volatile uint8_t *)(&__MBAR[0xB001]))
+#define MCF_USB_EPINFO                       (*(volatile uint8_t *)(&__MBAR[0xB003]))
+#define MCF_USB_CFGR                         (*(volatile uint8_t *)(&__MBAR[0xB004]))
+#define MCF_USB_CFGAR                        (*(volatile uint8_t *)(&__MBAR[0xB005]))
+#define MCF_USB_SPEEDR                       (*(volatile uint8_t *)(&__MBAR[0xB006]))
+#define MCF_USB_FRMNUMR                      (*(volatile uint16_t*)(&__MBAR[0xB00E]))
+#define MCF_USB_EPTNR                        (*(volatile uint16_t*)(&__MBAR[0xB010]))
+#define MCF_USB_IFUR                         (*(volatile uint16_t*)(&__MBAR[0xB014]))
+#define MCF_USB_IFR0                         (*(volatile uint16_t*)(&__MBAR[0xB040]))
+#define MCF_USB_IFR1                         (*(volatile uint16_t*)(&__MBAR[0xB042]))
+#define MCF_USB_IFR2                         (*(volatile uint16_t*)(&__MBAR[0xB044]))
+#define MCF_USB_IFR3                         (*(volatile uint16_t*)(&__MBAR[0xB046]))
+#define MCF_USB_IFR4                         (*(volatile uint16_t*)(&__MBAR[0xB048]))
+#define MCF_USB_IFR5                         (*(volatile uint16_t*)(&__MBAR[0xB04A]))
+#define MCF_USB_IFR6                         (*(volatile uint16_t*)(&__MBAR[0xB04C]))
+#define MCF_USB_IFR7                         (*(volatile uint16_t*)(&__MBAR[0xB04E]))
+#define MCF_USB_IFR8                         (*(volatile uint16_t*)(&__MBAR[0xB050]))
+#define MCF_USB_IFR9                         (*(volatile uint16_t*)(&__MBAR[0xB052]))
+#define MCF_USB_IFR10                        (*(volatile uint16_t*)(&__MBAR[0xB054]))
+#define MCF_USB_IFR11                        (*(volatile uint16_t*)(&__MBAR[0xB056]))
+#define MCF_USB_IFR12                        (*(volatile uint16_t*)(&__MBAR[0xB058]))
+#define MCF_USB_IFR13                        (*(volatile uint16_t*)(&__MBAR[0xB05A]))
+#define MCF_USB_IFR14                        (*(volatile uint16_t*)(&__MBAR[0xB05C]))
+#define MCF_USB_IFR15                        (*(volatile uint16_t*)(&__MBAR[0xB05E]))
+#define MCF_USB_IFR16                        (*(volatile uint16_t*)(&__MBAR[0xB060]))
+#define MCF_USB_IFR17                        (*(volatile uint16_t*)(&__MBAR[0xB062]))
+#define MCF_USB_IFR18                        (*(volatile uint16_t*)(&__MBAR[0xB064]))
+#define MCF_USB_IFR19                        (*(volatile uint16_t*)(&__MBAR[0xB066]))
+#define MCF_USB_IFR20                        (*(volatile uint16_t*)(&__MBAR[0xB068]))
+#define MCF_USB_IFR21                        (*(volatile uint16_t*)(&__MBAR[0xB06A]))
+#define MCF_USB_IFR22                        (*(volatile uint16_t*)(&__MBAR[0xB06C]))
+#define MCF_USB_IFR23                        (*(volatile uint16_t*)(&__MBAR[0xB06E]))
+#define MCF_USB_IFR24                        (*(volatile uint16_t*)(&__MBAR[0xB070]))
+#define MCF_USB_IFR25                        (*(volatile uint16_t*)(&__MBAR[0xB072]))
+#define MCF_USB_IFR26                        (*(volatile uint16_t*)(&__MBAR[0xB074]))
+#define MCF_USB_IFR27                        (*(volatile uint16_t*)(&__MBAR[0xB076]))
+#define MCF_USB_IFR28                        (*(volatile uint16_t*)(&__MBAR[0xB078]))
+#define MCF_USB_IFR29                        (*(volatile uint16_t*)(&__MBAR[0xB07A]))
+#define MCF_USB_IFR30                        (*(volatile uint16_t*)(&__MBAR[0xB07C]))
+#define MCF_USB_IFR31                        (*(volatile uint16_t*)(&__MBAR[0xB07E]))
+#define MCF_USB_PPCNT                        (*(volatile uint16_t*)(&__MBAR[0xB080]))
+#define MCF_USB_DPCNT                        (*(volatile uint16_t*)(&__MBAR[0xB082]))
+#define MCF_USB_CRCECNT                      (*(volatile uint16_t*)(&__MBAR[0xB084]))
+#define MCF_USB_BSECNT                       (*(volatile uint16_t*)(&__MBAR[0xB086]))
+#define MCF_USB_PIDECNT                      (*(volatile uint16_t*)(&__MBAR[0xB088]))
+#define MCF_USB_FRMECNT                      (*(volatile uint16_t*)(&__MBAR[0xB08A]))
+#define MCF_USB_TXPCNT                       (*(volatile uint16_t*)(&__MBAR[0xB08C]))
+#define MCF_USB_CNTOVR                       (*(volatile uint8_t *)(&__MBAR[0xB08E]))
+#define MCF_USB_EP0ACR                       (*(volatile uint8_t *)(&__MBAR[0xB101]))
+#define MCF_USB_EP0MPSR                      (*(volatile uint16_t*)(&__MBAR[0xB102]))
+#define MCF_USB_EP0IFR                       (*(volatile uint8_t *)(&__MBAR[0xB104]))
+#define MCF_USB_EP0SR                        (*(volatile uint8_t *)(&__MBAR[0xB105]))
+#define MCF_USB_BMRTR                        (*(volatile uint8_t *)(&__MBAR[0xB106]))
+#define MCF_USB_BRTR                         (*(volatile uint8_t *)(&__MBAR[0xB107]))
+#define MCF_USB_WVALUER                      (*(volatile uint16_t*)(&__MBAR[0xB108]))
+#define MCF_USB_WINDEXR                      (*(volatile uint16_t*)(&__MBAR[0xB10A]))
+#define MCF_USB_WLENGTHR                     (*(volatile uint16_t*)(&__MBAR[0xB10C]))
+#define MCF_USB_EP1OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB131]))
+#define MCF_USB_EP1OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB132]))
+#define MCF_USB_EP1OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB134]))
+#define MCF_USB_EP1OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB135]))
+#define MCF_USB_EP1OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB13E]))
+#define MCF_USB_EP1INACR                     (*(volatile uint8_t *)(&__MBAR[0xB149]))
+#define MCF_USB_EP1INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB14A]))
+#define MCF_USB_EP1INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB14C]))
+#define MCF_USB_EP1INSR                      (*(volatile uint8_t *)(&__MBAR[0xB14D]))
+#define MCF_USB_EP1INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB156]))
+#define MCF_USB_EP2OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB161]))
+#define MCF_USB_EP2OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB162]))
+#define MCF_USB_EP2OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB164]))
+#define MCF_USB_EP2OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB165]))
+#define MCF_USB_EP2OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB16E]))
+#define MCF_USB_EP2INACR                     (*(volatile uint8_t *)(&__MBAR[0xB179]))
+#define MCF_USB_EP2INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB17A]))
+#define MCF_USB_EP2INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB17C]))
+#define MCF_USB_EP2INSR                      (*(volatile uint8_t *)(&__MBAR[0xB17D]))
+#define MCF_USB_EP2INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB186]))
+#define MCF_USB_EP3OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB191]))
+#define MCF_USB_EP3OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB192]))
+#define MCF_USB_EP3OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB194]))
+#define MCF_USB_EP3OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB195]))
+#define MCF_USB_EP3OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB19E]))
+#define MCF_USB_EP3INACR                     (*(volatile uint8_t *)(&__MBAR[0xB1A9]))
+#define MCF_USB_EP3INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB1AA]))
+#define MCF_USB_EP3INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB1AC]))
+#define MCF_USB_EP3INSR                      (*(volatile uint8_t *)(&__MBAR[0xB1AD]))
+#define MCF_USB_EP3INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB1B6]))
+#define MCF_USB_EP4OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB1C1]))
+#define MCF_USB_EP4OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB1C2]))
+#define MCF_USB_EP4OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB1C4]))
+#define MCF_USB_EP4OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB1C5]))
+#define MCF_USB_EP4OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB1CE]))
+#define MCF_USB_EP4INACR                     (*(volatile uint8_t *)(&__MBAR[0xB1D9]))
+#define MCF_USB_EP4INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB1DA]))
+#define MCF_USB_EP4INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB1DC]))
+#define MCF_USB_EP4INSR                      (*(volatile uint8_t *)(&__MBAR[0xB1DD]))
+#define MCF_USB_EP4INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB1E6]))
+#define MCF_USB_EP5OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB1F1]))
+#define MCF_USB_EP5OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB1F2]))
+#define MCF_USB_EP5OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB1F4]))
+#define MCF_USB_EP5OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB1F5]))
+#define MCF_USB_EP5OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB1FE]))
+#define MCF_USB_EP5INACR                     (*(volatile uint8_t *)(&__MBAR[0xB209]))
+#define MCF_USB_EP5INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB20A]))
+#define MCF_USB_EP5INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB20C]))
+#define MCF_USB_EP5INSR                      (*(volatile uint8_t *)(&__MBAR[0xB20D]))
+#define MCF_USB_EP5INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB216]))
+#define MCF_USB_EP6OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB221]))
+#define MCF_USB_EP6OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB222]))
+#define MCF_USB_EP6OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB224]))
+#define MCF_USB_EP6OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB225]))
+#define MCF_USB_EP6OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB22E]))
+#define MCF_USB_EP6INACR                     (*(volatile uint8_t *)(&__MBAR[0xB239]))
+#define MCF_USB_EP6INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB23A]))
+#define MCF_USB_EP6INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB23C]))
+#define MCF_USB_EP6INSR                      (*(volatile uint8_t *)(&__MBAR[0xB23D]))
+#define MCF_USB_EP6INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB246]))
+#define MCF_USB_USBSR                        (*(volatile uint32_t*)(&__MBAR[0xB400]))
+#define MCF_USB_USBCR                        (*(volatile uint32_t*)(&__MBAR[0xB404]))
+#define MCF_USB_DRAMCR                       (*(volatile uint32_t*)(&__MBAR[0xB408]))
+#define MCF_USB_DRAMDR                       (*(volatile uint32_t*)(&__MBAR[0xB40C]))
+#define MCF_USB_USBISR                       (*(volatile uint32_t*)(&__MBAR[0xB410]))
+#define MCF_USB_USBIMR                       (*(volatile uint32_t*)(&__MBAR[0xB414]))
+#define MCF_USB_EP0STAT                      (*(volatile uint32_t*)(&__MBAR[0xB440]))
+#define MCF_USB_EP0ISR                       (*(volatile uint32_t*)(&__MBAR[0xB444]))
+#define MCF_USB_EP0IMR                       (*(volatile uint32_t*)(&__MBAR[0xB448]))
+#define MCF_USB_EP0FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB44C]))
+#define MCF_USB_EP0FDR                       (*(volatile uint32_t*)(&__MBAR[0xB450]))
+#define MCF_USB_EP0FSR                       (*(volatile uint32_t*)(&__MBAR[0xB454]))
+#define MCF_USB_EP0FCR                       (*(volatile uint32_t*)(&__MBAR[0xB458]))
+#define MCF_USB_EP0FAR                       (*(volatile uint32_t*)(&__MBAR[0xB45C]))
+#define MCF_USB_EP0FRP                       (*(volatile uint32_t*)(&__MBAR[0xB460]))
+#define MCF_USB_EP0FWP                       (*(volatile uint32_t*)(&__MBAR[0xB464]))
+#define MCF_USB_EP0LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB468]))
+#define MCF_USB_EP0LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB46C]))
+#define MCF_USB_EP1STAT                      (*(volatile uint32_t*)(&__MBAR[0xB470]))
+#define MCF_USB_EP1ISR                       (*(volatile uint32_t*)(&__MBAR[0xB474]))
+#define MCF_USB_EP1IMR                       (*(volatile uint32_t*)(&__MBAR[0xB478]))
+#define MCF_USB_EP1FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB47C]))
+#define MCF_USB_EP1FDR                       (*(volatile uint32_t*)(&__MBAR[0xB480]))
+#define MCF_USB_EP1FSR                       (*(volatile uint32_t*)(&__MBAR[0xB484]))
+#define MCF_USB_EP1FCR                       (*(volatile uint32_t*)(&__MBAR[0xB488]))
+#define MCF_USB_EP1FAR                       (*(volatile uint32_t*)(&__MBAR[0xB48C]))
+#define MCF_USB_EP1FRP                       (*(volatile uint32_t*)(&__MBAR[0xB490]))
+#define MCF_USB_EP1FWP                       (*(volatile uint32_t*)(&__MBAR[0xB494]))
+#define MCF_USB_EP1LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB498]))
+#define MCF_USB_EP1LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB49C]))
+#define MCF_USB_EP2STAT                      (*(volatile uint32_t*)(&__MBAR[0xB4A0]))
+#define MCF_USB_EP2ISR                       (*(volatile uint32_t*)(&__MBAR[0xB4A4]))
+#define MCF_USB_EP2IMR                       (*(volatile uint32_t*)(&__MBAR[0xB4A8]))
+#define MCF_USB_EP2FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB4AC]))
+#define MCF_USB_EP2FDR                       (*(volatile uint32_t*)(&__MBAR[0xB4B0]))
+#define MCF_USB_EP2FSR                       (*(volatile uint32_t*)(&__MBAR[0xB4B4]))
+#define MCF_USB_EP2FCR                       (*(volatile uint32_t*)(&__MBAR[0xB4B8]))
+#define MCF_USB_EP2FAR                       (*(volatile uint32_t*)(&__MBAR[0xB4BC]))
+#define MCF_USB_EP2FRP                       (*(volatile uint32_t*)(&__MBAR[0xB4C0]))
+#define MCF_USB_EP2FWP                       (*(volatile uint32_t*)(&__MBAR[0xB4C4]))
+#define MCF_USB_EP2LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB4C8]))
+#define MCF_USB_EP2LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB4CC]))
+#define MCF_USB_EP3STAT                      (*(volatile uint32_t*)(&__MBAR[0xB4D0]))
+#define MCF_USB_EP3ISR                       (*(volatile uint32_t*)(&__MBAR[0xB4D4]))
+#define MCF_USB_EP3IMR                       (*(volatile uint32_t*)(&__MBAR[0xB4D8]))
+#define MCF_USB_EP3FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB4DC]))
+#define MCF_USB_EP3FDR                       (*(volatile uint32_t*)(&__MBAR[0xB4E0]))
+#define MCF_USB_EP3FSR                       (*(volatile uint32_t*)(&__MBAR[0xB4E4]))
+#define MCF_USB_EP3FCR                       (*(volatile uint32_t*)(&__MBAR[0xB4E8]))
+#define MCF_USB_EP3FAR                       (*(volatile uint32_t*)(&__MBAR[0xB4EC]))
+#define MCF_USB_EP3FRP                       (*(volatile uint32_t*)(&__MBAR[0xB4F0]))
+#define MCF_USB_EP3FWP                       (*(volatile uint32_t*)(&__MBAR[0xB4F4]))
+#define MCF_USB_EP3LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB4F8]))
+#define MCF_USB_EP3LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB4FC]))
+#define MCF_USB_EP4STAT                      (*(volatile uint32_t*)(&__MBAR[0xB500]))
+#define MCF_USB_EP4ISR                       (*(volatile uint32_t*)(&__MBAR[0xB504]))
+#define MCF_USB_EP4IMR                       (*(volatile uint32_t*)(&__MBAR[0xB508]))
+#define MCF_USB_EP4FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB50C]))
+#define MCF_USB_EP4FDR                       (*(volatile uint32_t*)(&__MBAR[0xB510]))
+#define MCF_USB_EP4FSR                       (*(volatile uint32_t*)(&__MBAR[0xB514]))
+#define MCF_USB_EP4FCR                       (*(volatile uint32_t*)(&__MBAR[0xB518]))
+#define MCF_USB_EP4FAR                       (*(volatile uint32_t*)(&__MBAR[0xB51C]))
+#define MCF_USB_EP4FRP                       (*(volatile uint32_t*)(&__MBAR[0xB520]))
+#define MCF_USB_EP4FWP                       (*(volatile uint32_t*)(&__MBAR[0xB524]))
+#define MCF_USB_EP4LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB528]))
+#define MCF_USB_EP4LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB52C]))
+#define MCF_USB_EP5STAT                      (*(volatile uint32_t*)(&__MBAR[0xB530]))
+#define MCF_USB_EP5ISR                       (*(volatile uint32_t*)(&__MBAR[0xB534]))
+#define MCF_USB_EP5IMR                       (*(volatile uint32_t*)(&__MBAR[0xB538]))
+#define MCF_USB_EP5FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB53C]))
+#define MCF_USB_EP5FDR                       (*(volatile uint32_t*)(&__MBAR[0xB540]))
+#define MCF_USB_EP5FSR                       (*(volatile uint32_t*)(&__MBAR[0xB544]))
+#define MCF_USB_EP5FCR                       (*(volatile uint32_t*)(&__MBAR[0xB548]))
+#define MCF_USB_EP5FAR                       (*(volatile uint32_t*)(&__MBAR[0xB54C]))
+#define MCF_USB_EP5FRP                       (*(volatile uint32_t*)(&__MBAR[0xB550]))
+#define MCF_USB_EP5FWP                       (*(volatile uint32_t*)(&__MBAR[0xB554]))
+#define MCF_USB_EP5LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB558]))
+#define MCF_USB_EP5LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB55C]))
+#define MCF_USB_EP6STAT                      (*(volatile uint32_t*)(&__MBAR[0xB560]))
+#define MCF_USB_EP6ISR                       (*(volatile uint32_t*)(&__MBAR[0xB564]))
+#define MCF_USB_EP6IMR                       (*(volatile uint32_t*)(&__MBAR[0xB568]))
+#define MCF_USB_EP6FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB56C]))
+#define MCF_USB_EP6FDR                       (*(volatile uint32_t*)(&__MBAR[0xB570]))
+#define MCF_USB_EP6FSR                       (*(volatile uint32_t*)(&__MBAR[0xB574]))
+#define MCF_USB_EP6FCR                       (*(volatile uint32_t*)(&__MBAR[0xB578]))
+#define MCF_USB_EP6FAR                       (*(volatile uint32_t*)(&__MBAR[0xB57C]))
+#define MCF_USB_EP6FRP                       (*(volatile uint32_t*)(&__MBAR[0xB580]))
+#define MCF_USB_EP6FWP                       (*(volatile uint32_t*)(&__MBAR[0xB584]))
+#define MCF_USB_EP6LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB588]))
+#define MCF_USB_EP6LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB58C]))
+#define MCF_USB_IFR(x)                       (*(volatile uint16_t*)(&__MBAR[0xB040 + ((x)*0x2)]))
+#define MCF_USB_EPOUTACR(x)                  (*(volatile uint8_t *)(&__MBAR[0xB131 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTMPSR(x)                 (*(volatile uint16_t*)(&__MBAR[0xB132 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTIFR(x)                  (*(volatile uint8_t *)(&__MBAR[0xB134 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTSR(x)                   (*(volatile uint8_t *)(&__MBAR[0xB135 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTSFR(x)                  (*(volatile uint16_t*)(&__MBAR[0xB13E + ((x-1)*0x30)]))
+#define MCF_USB_EPINACR(x)                   (*(volatile uint8_t *)(&__MBAR[0xB149 + ((x-1)*0x30)]))
+#define MCF_USB_EPINMPSR(x)                  (*(volatile uint16_t*)(&__MBAR[0xB14A + ((x-1)*0x30)]))
+#define MCF_USB_EPINIFR(x)                   (*(volatile uint8_t *)(&__MBAR[0xB14C + ((x-1)*0x30)]))
+#define MCF_USB_EPINSR(x)                    (*(volatile uint8_t *)(&__MBAR[0xB14D + ((x-1)*0x30)]))
+#define MCF_USB_EPINSFR(x)                   (*(volatile uint16_t*)(&__MBAR[0xB156 + ((x-1)*0x30)]))
+#define MCF_USB_EPSTAT(x)                    (*(volatile uint32_t*)(&__MBAR[0xB440 + ((x)*0x30)]))
+#define MCF_USB_EPISR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB444 + ((x)*0x30)]))
+#define MCF_USB_EPIMR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB448 + ((x)*0x30)]))
+#define MCF_USB_EPFRCFGR(x)                  (*(volatile uint32_t*)(&__MBAR[0xB44C + ((x)*0x30)]))
+#define MCF_USB_EPFDR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB450 + ((x)*0x30)]))
+#define MCF_USB_EPFSR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB454 + ((x)*0x30)]))
+#define MCF_USB_EPFCR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB458 + ((x)*0x30)]))
+#define MCF_USB_EPFAR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB45C + ((x)*0x30)]))
+#define MCF_USB_EPFRP(x)                     (*(volatile uint32_t*)(&__MBAR[0xB460 + ((x)*0x30)]))
+#define MCF_USB_EPFWP(x)                     (*(volatile uint32_t*)(&__MBAR[0xB464 + ((x)*0x30)]))
+#define MCF_USB_EPLRFP(x)                    (*(volatile uint32_t*)(&__MBAR[0xB468 + ((x)*0x30)]))
+#define MCF_USB_EPLWFP(x)                    (*(volatile uint32_t*)(&__MBAR[0xB46C + ((x)*0x30)]))
+
+
+/* Bit definitions and macros for MCF_USB_USBAISR */
+#define MCF_USB_USBAISR_SETUP                (0x1)
+#define MCF_USB_USBAISR_IN                   (0x2)
+#define MCF_USB_USBAISR_OUT                  (0x4)
+#define MCF_USB_USBAISR_EPHALT               (0x8)
+#define MCF_USB_USBAISR_TRANSERR             (0x10)
+#define MCF_USB_USBAISR_ACK                  (0x20)
+#define MCF_USB_USBAISR_CTROVFL              (0x40)
+#define MCF_USB_USBAISR_EPSTALL              (0x80)
+
+/* Bit definitions and macros for MCF_USB_USBAIMR */
+#define MCF_USB_USBAIMR_SETUPEN              (0x1)
+#define MCF_USB_USBAIMR_INEN                 (0x2)
+#define MCF_USB_USBAIMR_OUTEN                (0x4)
+#define MCF_USB_USBAIMR_EPHALTEN             (0x8)
+#define MCF_USB_USBAIMR_TRANSERREN           (0x10)
+#define MCF_USB_USBAIMR_ACKEN                (0x20)
+#define MCF_USB_USBAIMR_CTROVFLEN            (0x40)
+#define MCF_USB_USBAIMR_EPSTALLEN            (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPINFO */
+#define MCF_USB_EPINFO_EPDIR                 (0x1)
+#define MCF_USB_EPINFO_EPNUM(x)              (((x)&0x7)<<0x1)
+
+/* Bit definitions and macros for MCF_USB_CFGR */
+#define MCF_USB_CFGR_Configuration_Value(x)  (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_CFGAR */
+#define MCF_USB_CFGAR_RESERVED               (0xA0)
+#define MCF_USB_CFGAR_RMTWKEUP               (0xE0)
+
+/* Bit definitions and macros for MCF_USB_SPEEDR */
+#define MCF_USB_SPEEDR_SPEED(x)              (((x)&0x3)<<0)
+
+/* Bit definitions and macros for MCF_USB_FRMNUMR */
+#define MCF_USB_FRMNUMR_FRMNUM(x)            (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPTNR */
+#define MCF_USB_EPTNR_EP1T(x)                (((x)&0x3)<<0)
+#define MCF_USB_EPTNR_EP2T(x)                (((x)&0x3)<<0x2)
+#define MCF_USB_EPTNR_EP3T(x)                (((x)&0x3)<<0x4)
+#define MCF_USB_EPTNR_EP4T(x)                (((x)&0x3)<<0x6)
+#define MCF_USB_EPTNR_EP5T(x)                (((x)&0x3)<<0x8)
+#define MCF_USB_EPTNR_EP6T(x)                (((x)&0x3)<<0xA)
+#define MCF_USB_EPTNR_EPnT1                  (0)
+#define MCF_USB_EPTNR_EPnT2                  (0x1)
+#define MCF_USB_EPTNR_EPnT3                  (0x2)
+
+/* Bit definitions and macros for MCF_USB_IFUR */
+#define MCF_USB_IFUR_ALTSET(x)               (((x)&0xFF)<<0)
+#define MCF_USB_IFUR_IFNUM(x)                (((x)&0xFF)<<0x8)
+
+/* Bit definitions and macros for MCF_USB_IFR */
+#define MCF_USB_IFR_ALTSET(x)                (((x)&0xFF)<<0)
+#define MCF_USB_IFR_IFNUM(x)                 (((x)&0xFF)<<0x8)
+
+/* Bit definitions and macros for MCF_USB_PPCNT */
+#define MCF_USB_PPCNT_PPCNT(x)               (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_DPCNT */
+#define MCF_USB_DPCNT_DPCNT(x)               (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_CRCECNT */
+#define MCF_USB_CRCECNT_CRCECNT(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_BSECNT */
+#define MCF_USB_BSECNT_BSECNT(x)             (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_PIDECNT */
+#define MCF_USB_PIDECNT_PIDECNT(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_FRMECNT */
+#define MCF_USB_FRMECNT_FRMECNT(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_TXPCNT */
+#define MCF_USB_TXPCNT_TXPCNT(x)             (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_CNTOVR */
+#define MCF_USB_CNTOVR_PPCNT                 (0x1)
+#define MCF_USB_CNTOVR_DPCNT                 (0x2)
+#define MCF_USB_CNTOVR_CRCECNT               (0x4)
+#define MCF_USB_CNTOVR_BSECNT                (0x8)
+#define MCF_USB_CNTOVR_PIDECNT               (0x10)
+#define MCF_USB_CNTOVR_FRMECNT               (0x20)
+#define MCF_USB_CNTOVR_TXPCNT                (0x40)
+
+/* Bit definitions and macros for MCF_USB_EP0ACR */
+#define MCF_USB_EP0ACR_TTYPE(x)              (((x)&0x3)<<0)
+#define MCF_USB_EP0ACR_TTYPE_CTRL            (0)
+#define MCF_USB_EP0ACR_TTYPE_ISOC            (0x1)
+#define MCF_USB_EP0ACR_TTYPE_BULK            (0x2)
+#define MCF_USB_EP0ACR_TTYPE_INT             (0x3)
+
+/* Bit definitions and macros for MCF_USB_EP0MPSR */
+#define MCF_USB_EP0MPSR_MAXPKTSZ(x)          (((x)&0x7FF)<<0)
+#define MCF_USB_EP0MPSR_ADDTRANS(x)          (((x)&0x3)<<0xB)
+
+/* Bit definitions and macros for MCF_USB_EP0IFR */
+#define MCF_USB_EP0IFR_IFNUM(x)              (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EP0SR */
+#define MCF_USB_EP0SR_HALT                   (0x1)
+#define MCF_USB_EP0SR_ACTIVE                 (0x2)
+#define MCF_USB_EP0SR_PSTALL                 (0x4)
+#define MCF_USB_EP0SR_CCOMP                  (0x8)
+#define MCF_USB_EP0SR_TXZERO                 (0x20)
+#define MCF_USB_EP0SR_INT                    (0x80)
+
+/* Bit definitions and macros for MCF_USB_BMRTR */
+#define MCF_USB_BMRTR_REC(x)                 (((x)&0x1F)<<0)
+#define MCF_USB_BMRTR_REC_DEVICE             (0)
+#define MCF_USB_BMRTR_REC_INTERFACE          (0x1)
+#define MCF_USB_BMRTR_REC_ENDPOINT           (0x2)
+#define MCF_USB_BMRTR_REC_OTHER              (0x3)
+#define MCF_USB_BMRTR_TYPE(x)                (((x)&0x3)<<0x5)
+#define MCF_USB_BMRTR_TYPE_STANDARD          (0)
+#define MCF_USB_BMRTR_TYPE_CLASS             (0x20)
+#define MCF_USB_BMRTR_TYPE_VENDOR            (0x40)
+#define MCF_USB_BMRTR_DIR                    (0x80)
+
+/* Bit definitions and macros for MCF_USB_BRTR */
+#define MCF_USB_BRTR_BREQ(x)                 (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_WVALUER */
+#define MCF_USB_WVALUER_WVALUE(x)            (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_WINDEXR */
+#define MCF_USB_WINDEXR_WINDEX(x)            (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_WLENGTHR */
+#define MCF_USB_WLENGTHR_WLENGTH(x)          (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPOUTACR */
+#define MCF_USB_EPOUTACR_TTYPE(x)            (((x)&0x3)<<0)
+#define MCF_USB_EPOUTACR_TTYPE_ISOC          (0x1)
+#define MCF_USB_EPOUTACR_TTYPE_BULK          (0x2)
+#define MCF_USB_EPOUTACR_TTYPE_INT           (0x3)
+
+/* Bit definitions and macros for MCF_USB_EPOUTMPSR */
+#define MCF_USB_EPOUTMPSR_MAXPKTSZ(x)        (((x)&0x7FF)<<0)
+#define MCF_USB_EPOUTMPSR_ADDTRANS(x)        (((x)&0x3)<<0xB)
+
+/* Bit definitions and macros for MCF_USB_EPOUTIFR */
+#define MCF_USB_EPOUTIFR_IFNUM(x)            (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPOUTSR */
+#define MCF_USB_EPOUTSR_HALT                 (0x1)
+#define MCF_USB_EPOUTSR_ACTIVE               (0x2)
+#define MCF_USB_EPOUTSR_PSTALL               (0x4)
+#define MCF_USB_EPOUTSR_CCOMP                (0x8)
+#define MCF_USB_EPOUTSR_TXZERO               (0x20)
+#define MCF_USB_EPOUTSR_INT                  (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPOUTSFR */
+#define MCF_USB_EPOUTSFR_FRMNUM(x)           (((x)&0x7FF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPINACR */
+#define MCF_USB_EPINACR_TTYPE(x)             (((x)&0x3)<<0)
+#define MCF_USB_EPINACR_TTYPE_ISOC           (0x1)
+#define MCF_USB_EPINACR_TTYPE_BULK           (0x2)
+#define MCF_USB_EPINACR_TTYPE_INT            (0x3)
+
+/* Bit definitions and macros for MCF_USB_EPINMPSR */
+#define MCF_USB_EPINMPSR_MAXPKTSZ(x)         (((x)&0x7FF)<<0)
+#define MCF_USB_EPINMPSR_ADDTRANS(x)         (((x)&0x3)<<0xB)
+
+/* Bit definitions and macros for MCF_USB_EPINIFR */
+#define MCF_USB_EPINIFR_IFNUM(x)             (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPINSR */
+#define MCF_USB_EPINSR_HALT                  (0x1)
+#define MCF_USB_EPINSR_ACTIVE                (0x2)
+#define MCF_USB_EPINSR_PSTALL                (0x4)
+#define MCF_USB_EPINSR_CCOMP                 (0x8)
+#define MCF_USB_EPINSR_TXZERO                (0x20)
+#define MCF_USB_EPINSR_INT                   (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPINSFR */
+#define MCF_USB_EPINSFR_FRMNUM(x)            (((x)&0x7FF)<<0)
+
+/* Bit definitions and macros for MCF_USB_USBSR */
+#define MCF_USB_USBSR_ISOERREP(x)            (((x)&0xF)<<0)
+#define MCF_USB_USBSR_SUSP                   (0x80)
+
+/* Bit definitions and macros for MCF_USB_USBCR */
+#define MCF_USB_USBCR_RESUME                 (0x1)
+#define MCF_USB_USBCR_APPLOCK                (0x2)
+#define MCF_USB_USBCR_RST                    (0x4)
+#define MCF_USB_USBCR_RAMEN                  (0x8)
+#define MCF_USB_USBCR_RAMSPLIT               (0x20)
+
+/* Bit definitions and macros for MCF_USB_DRAMCR */
+#define MCF_USB_DRAMCR_DADR(x)               (((x)&0x3FF)<<0)
+#define MCF_USB_DRAMCR_DSIZE(x)              (((x)&0x7FF)<<0x10)
+#define MCF_USB_DRAMCR_BSY                   (0x40000000)
+#define MCF_USB_DRAMCR_START                 (0x80000000)
+
+/* Bit definitions and macros for MCF_USB_DRAMDR */
+#define MCF_USB_DRAMDR_DDAT(x)               (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_USBISR */
+#define MCF_USB_USBISR_ISOERR                (0x1)
+#define MCF_USB_USBISR_FTUNLCK               (0x2)
+#define MCF_USB_USBISR_SUSP                  (0x4)
+#define MCF_USB_USBISR_RES                   (0x8)
+#define MCF_USB_USBISR_UPDSOF                (0x10)
+#define MCF_USB_USBISR_RSTSTOP               (0x20)
+#define MCF_USB_USBISR_SOF                   (0x40)
+#define MCF_USB_USBISR_MSOF                  (0x80)
+
+/* Bit definitions and macros for MCF_USB_USBIMR */
+#define MCF_USB_USBIMR_ISOERR                (0x1)
+#define MCF_USB_USBIMR_FTUNLCK               (0x2)
+#define MCF_USB_USBIMR_SUSP                  (0x4)
+#define MCF_USB_USBIMR_RES                   (0x8)
+#define MCF_USB_USBIMR_UPDSOF                (0x10)
+#define MCF_USB_USBIMR_RSTSTOP               (0x20)
+#define MCF_USB_USBIMR_SOF                   (0x40)
+#define MCF_USB_USBIMR_MSOF                  (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPSTAT */
+#define MCF_USB_EPSTAT_RST                   (0x1)
+#define MCF_USB_EPSTAT_FLUSH                 (0x2)
+#define MCF_USB_EPSTAT_DIR                   (0x80)
+#define MCF_USB_EPSTAT_BYTECNT(x)            (((x)&0xFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_USB_EPISR */
+#define MCF_USB_EPISR_EOF                    (0x1)
+#define MCF_USB_EPISR_EOT                    (0x4)
+#define MCF_USB_EPISR_FIFOLO                 (0x10)
+#define MCF_USB_EPISR_FIFOHI                 (0x20)
+#define MCF_USB_EPISR_ERR                    (0x40)
+#define MCF_USB_EPISR_EMT                    (0x80)
+#define MCF_USB_EPISR_FU                     (0x100)
+
+/* Bit definitions and macros for MCF_USB_EPIMR */
+#define MCF_USB_EPIMR_EOF                    (0x1)
+#define MCF_USB_EPIMR_EOT                    (0x4)
+#define MCF_USB_EPIMR_FIFOLO                 (0x10)
+#define MCF_USB_EPIMR_FIFOHI                 (0x20)
+#define MCF_USB_EPIMR_ERR                    (0x40)
+#define MCF_USB_EPIMR_EMT                    (0x80)
+#define MCF_USB_EPIMR_FU                     (0x100)
+
+/* Bit definitions and macros for MCF_USB_EPFRCFGR */
+#define MCF_USB_EPFRCFGR_DEPTH(x)            (((x)&0x1FFF)<<0)
+#define MCF_USB_EPFRCFGR_BASE(x)             (((x)&0xFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_USB_EPFDR */
+#define MCF_USB_EPFDR_RX_TXDATA(x)           (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPFSR */
+#define MCF_USB_EPFSR_EMT                    (0x10000)
+#define MCF_USB_EPFSR_ALRM                   (0x20000)
+#define MCF_USB_EPFSR_FU                     (0x40000)
+#define MCF_USB_EPFSR_FR                     (0x80000)
+#define MCF_USB_EPFSR_OF                     (0x100000)
+#define MCF_USB_EPFSR_UF                     (0x200000)
+#define MCF_USB_EPFSR_RXW                    (0x400000)
+#define MCF_USB_EPFSR_FAE                    (0x800000)
+#define MCF_USB_EPFSR_FRM(x)                 (((x)&0xF)<<0x18)
+#define MCF_USB_EPFSR_TXW                    (0x40000000)
+#define MCF_USB_EPFSR_IP                     (0x80000000)
+
+/* Bit definitions and macros for MCF_USB_EPFCR */
+#define MCF_USB_EPFCR_COUNTER(x)             (((x)&0xFFFF)<<0)
+#define MCF_USB_EPFCR_TXWMSK                 (0x40000)
+#define MCF_USB_EPFCR_OFMSK                  (0x80000)
+#define MCF_USB_EPFCR_UFMSK                  (0x100000)
+#define MCF_USB_EPFCR_RXWMSK                 (0x200000)
+#define MCF_USB_EPFCR_FAEMSK                 (0x400000)
+#define MCF_USB_EPFCR_IPMSK                  (0x800000)
+#define MCF_USB_EPFCR_GR(x)                  (((x)&0x7)<<0x18)
+#define MCF_USB_EPFCR_FRM                    (0x8000000)
+#define MCF_USB_EPFCR_TMR                    (0x10000000)
+#define MCF_USB_EPFCR_WFR                    (0x20000000)
+#define MCF_USB_EPFCR_SHAD                   (0x80000000)
+
+/* Bit definitions and macros for MCF_USB_EPFAR */
+#define MCF_USB_EPFAR_ALRMP(x)               (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPFRP */
+#define MCF_USB_EPFRP_RP(x)                  (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPFWP */
+#define MCF_USB_EPFWP_WP(x)                  (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPLRFP */
+#define MCF_USB_EPLRFP_LRFP(x)               (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPLWFP */
+#define MCF_USB_EPLWFP_LWFP(x)               (((x)&0xFFF)<<0)
+
+
+#endif /* __MCF5475_USB_H__ */
--- a/tos/jtagwait/include/MCF5475_XLB.h
+++ b/tos/jtagwait/include/MCF5475_XLB.h
@@ -0,0 +1,101 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_XLB_H__
+#define __MCF5475_XLB_H__
+
+
+/*********************************************************************
+*
+* XL Bus Arbiter (XLB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_XLB_XARB_CFG                     (*(volatile uint32_t*)(&_MBAR[0x240]))
+#define MCF_XLB_XARB_VER                     (*(volatile uint32_t*)(&_MBAR[0x244]))
+#define MCF_XLB_XARB_SR                      (*(volatile uint32_t*)(&_MBAR[0x248]))
+#define MCF_XLB_XARB_IMR                     (*(volatile uint32_t*)(&_MBAR[0x24C]))
+#define MCF_XLB_XARB_ADRCAP                  (*(volatile uint32_t*)(&_MBAR[0x250]))
+#define MCF_XLB_XARB_SIGCAP                  (*(volatile uint32_t*)(&_MBAR[0x254]))
+#define MCF_XLB_XARB_ADRTO                   (*(volatile uint32_t*)(&_MBAR[0x258]))
+#define MCF_XLB_XARB_DATTO                   (*(volatile uint32_t*)(&_MBAR[0x25C]))
+#define MCF_XLB_XARB_BUSTO                   (*(volatile uint32_t*)(&_MBAR[0x260]))
+#define MCF_XLB_XARB_PRIEN                   (*(volatile uint32_t*)(&_MBAR[0x264]))
+#define MCF_XLB_XARB_PRI                     (*(volatile uint32_t*)(&_MBAR[0x268]))
+
+
+/* Bit definitions and macros for MCF_XLB_XARB_CFG */
+#define MCF_XLB_XARB_CFG_AT                  (0x2)
+#define MCF_XLB_XARB_CFG_DT                  (0x4)
+#define MCF_XLB_XARB_CFG_BA                  (0x8)
+#define MCF_XLB_XARB_CFG_PM(x)               (((x)&0x3)<<0x5)
+#define MCF_XLB_XARB_CFG_SP(x)               (((x)&0x7)<<0x8)
+#define MCF_XLB_XARB_CFG_PLDIS               (0x80000000)
+
+/* Bit definitions and macros for MCF_XLB_XARB_VER */
+#define MCF_XLB_XARB_VER_VER(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_SR */
+#define MCF_XLB_XARB_SR_AT                   (0x1)
+#define MCF_XLB_XARB_SR_DT                   (0x2)
+#define MCF_XLB_XARB_SR_BA                   (0x4)
+#define MCF_XLB_XARB_SR_TTM                  (0x8)
+#define MCF_XLB_XARB_SR_ECW                  (0x10)
+#define MCF_XLB_XARB_SR_TTR                  (0x20)
+#define MCF_XLB_XARB_SR_TTA                  (0x40)
+#define MCF_XLB_XARB_SR_MM                   (0x80)
+#define MCF_XLB_XARB_SR_SEA                  (0x100)
+
+/* Bit definitions and macros for MCF_XLB_XARB_IMR */
+#define MCF_XLB_XARB_IMR_ATE                 (0x1)
+#define MCF_XLB_XARB_IMR_DTE                 (0x2)
+#define MCF_XLB_XARB_IMR_BAE                 (0x4)
+#define MCF_XLB_XARB_IMR_TTME                (0x8)
+#define MCF_XLB_XARB_IMR_ECWE                (0x10)
+#define MCF_XLB_XARB_IMR_TTRE                (0x20)
+#define MCF_XLB_XARB_IMR_TTAE                (0x40)
+#define MCF_XLB_XARB_IMR_MME                 (0x80)
+#define MCF_XLB_XARB_IMR_SEAE                (0x100)
+
+/* Bit definitions and macros for MCF_XLB_XARB_ADRCAP */
+#define MCF_XLB_XARB_ADRCAP_ADRCAP(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_SIGCAP */
+#define MCF_XLB_XARB_SIGCAP_TT(x)            (((x)&0x1F)<<0)
+#define MCF_XLB_XARB_SIGCAP_TBST             (0x20)
+#define MCF_XLB_XARB_SIGCAP_TSIZ(x)          (((x)&0x7)<<0x7)
+
+/* Bit definitions and macros for MCF_XLB_XARB_ADRTO */
+#define MCF_XLB_XARB_ADRTO_ADRTO(x)          (((x)&0xFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_DATTO */
+#define MCF_XLB_XARB_DATTO_DATTO(x)          (((x)&0xFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_BUSTO */
+#define MCF_XLB_XARB_BUSTO_BUSTO(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_PRIEN */
+#define MCF_XLB_XARB_PRIEN_M0                (0x1)
+#define MCF_XLB_XARB_PRIEN_M2                (0x4)
+#define MCF_XLB_XARB_PRIEN_M3                (0x8)
+
+/* Bit definitions and macros for MCF_XLB_XARB_PRI */
+#define MCF_XLB_XARB_PRI_M0P(x)              (((x)&0x7)<<0)
+#define MCF_XLB_XARB_PRI_M2P(x)              (((x)&0x7)<<0x8)
+#define MCF_XLB_XARB_PRI_M3P(x)              (((x)&0x7)<<0xC)
+
+
+#endif /* __MCF5475_XLB_H__ */
--- a/tos/jtagwait/include/bas_printf.h
+++ b/tos/jtagwait/include/bas_printf.h
@@ -0,0 +1,35 @@
+/*
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef _BAS_PRINTF_H_
+#define _BAS_PRINTF_H_
+#include <stdarg.h>
+#include <stddef.h>
+
+extern void xvsnprintf(char *str, size_t size, const char *fmt, va_list va);
+extern void xvprintf(const char *fmt, va_list va);
+extern void xprintf(const char *fmt, ...);
+extern void xsnprintf(char *str, size_t size, const char *fmt, ...);
+extern void xputchar(int c);
+extern int sprintf(char *str, const char *format, ...);
+
+
+extern void display_progress(void);
+extern void hexdump(uint8_t buffer[], int size);
+#endif /* _BAS_PRINTF_H_ */
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Markus Fröschle	c0d21a104f	consistantly use bas_types.h instead of standard headers	2014-09-25 06:24:55 +00:00
Markus Fröschle	4fc208c67d	updated comments	2014-09-25 05:54:26 +00:00
Markus Fröschle	8949a8456e	added function to flush only a portion of the caches	2014-09-24 16:02:20 +00:00
Markus Fröschle	37037b1e4c	now flashes BaS again	2014-09-21 13:30:55 +00:00
Markus Fröschle	e0f6d035a9	Screen address change now handled entirely in C (handler_gpt0/	2014-09-19 17:41:00 +00:00
Markus Fröschle	8bdb21c73f	updated comments	2014-09-19 06:02:16 +00:00
Markus Fröschle	b8df5c654f	replace "a7" with "sp" for consistancy	2014-09-19 04:59:21 +00:00
Markus Fröschle	77f641a959	fixed and completed comments	2014-09-18 20:13:54 +00:00
Markus Fröschle	02ab73f2cc	fixed a few MMU quirks	2014-09-17 05:28:16 +00:00
Markus Fröschle	01141f4251	check for supervisor protection fault and issue a bus error	2014-09-07 19:29:11 +00:00
Markus Fröschle	85798de684	rewritten mmu_map_page() and put into production	2014-09-07 19:01:19 +00:00
Markus Fröschle	fd8992cec5	removed warnings with some ugly casts...	2014-09-07 17:12:44 +00:00
Markus Fröschle	baa68901b8	moved more functionality from exceptions.S to interrupts.c. Added debug printouts to MMU page fault handler	2014-09-07 10:57:58 +00:00
Markus Fröschle	4c154978c9	modified to always update build date/time	2014-09-07 07:02:26 +00:00
Markus Fröschle	4b9a5bdbcd	minor changes	2014-09-07 06:55:37 +00:00
Markus Fröschle	9aac73896f	moved PSC3 interrupt handler to BaS dispatcher	2014-09-07 06:55:00 +00:00
Markus Fröschle	ebd8bd8e47	disabled USB init for now	2014-09-07 06:53:40 +00:00
Markus Fröschle	d147ef2625	moved IRQ service handler for PSC3 interrupt to the BaS ISR dispatcher	2014-09-07 06:53:01 +00:00
Markus Fröschle	1791a1bfaa	removed BaS network stuff and introduced a function to initialize BaS' ISR dispatcher	2014-09-07 06:50:23 +00:00
Markus Fröschle	0ced2c74f9	refactored	2014-09-06 21:29:55 +00:00
Markus Fröschle	d29c41022f	fixed a bug with LINK instruction not saving address register	2014-09-06 19:27:11 +00:00
Markus Fröschle	e6d81d461a	temporarily disabled interrupts to make debug printouts readable	2014-09-06 18:45:21 +00:00
Markus Fröschle	d4167ad98a	lowered DMA interrupt level	2014-09-06 18:43:03 +00:00
Markus Fröschle	5950f3651b	set interrupt and level to same values MiNT driver expects	2014-09-06 18:40:36 +00:00
Markus Fröschle	646768185b	disabled debug printouts	2014-09-06 18:39:42 +00:00
Markus Fröschle	5fae525781	disabled (unnecessary?) cache flush	2014-09-06 18:37:13 +00:00
Markus Fröschle	14186c8651	disabled USB initialization for now	2014-09-06 18:35:51 +00:00
Markus Fröschle	18fb66344d	reformatted	2014-09-06 18:35:06 +00:00
Markus Fröschle	ed13b05209	disabled USB debug printouts	2014-09-06 18:34:35 +00:00
Markus Fröschle	adc375f99a	disabled USB debug printouts	2014-09-06 18:33:46 +00:00
Markus Fröschle	81960712f7	disabled USB debug printouts	2014-09-06 18:33:00 +00:00
Markus Fröschle	e98a3aed3a	reformatted	2014-09-05 05:55:03 +00:00
Markus Fröschle	609d805c07	beautified formatting and fixed some (minor) typos	2014-09-03 06:16:55 +00:00
Markus Fröschle	c453b2e180	fixed a few typos	2014-09-02 19:58:19 +00:00
Markus Fröschle	7921199e9b	refactored, reformatted, added missing clobber registers to __asm__ statements	2014-09-02 13:51:00 +00:00
Markus Fröschle	56cbd17373	refactored USB driver code, enabled debug printouts everywhere	2014-09-01 19:22:26 +00:00
Markus Fröschle	3cac91e754	fixed some compiler warnings	2014-09-01 14:23:33 +00:00
Markus Fröschle	f2aae64892	more generalization of the dbg() diagnostic message prints	2014-09-01 07:20:22 +00:00
Markus Fröschle	df57613c13	added debug statements. Apparently, the code is trying to initialize the hub as mouse (which obviously can't work).	2014-09-01 06:41:07 +00:00
Markus Fröschle	1f02b270f7	(re)enabled debugging statements	2014-09-01 06:26:19 +00:00
Markus Fröschle	f170349879	(re)enabled USB bus scan. It takes an eternity to finish, but finally returns. Hub found, but no mouse yet.	2014-09-01 06:19:45 +00:00
Markus Fröschle	8c5ea67b00	added debugging statements for PCI enumeration	2014-09-01 05:37:43 +00:00
Markus Fröschle	1e74148353	fixed wrong intermediate Makefile which was forgotten to change after the rename	2014-08-31 12:35:54 +00:00
Markus Fröschle	986ed13f07	renamed tos/mcdcook to tos/bascook	2014-08-31 11:42:32 +00:00
Markus Fröschle	d422f8926e	renamed to bascook	2014-08-31 11:40:55 +00:00
Markus Fröschle	9da962b98a	renamed	2014-08-31 11:39:41 +00:00
Markus Fröschle	1590804dfa	removed unused files. Modifed MCDCOOK build process to use BaS_gcc includes (no need to sync includes anymore)	2014-08-31 11:36:59 +00:00
Markus Fröschle	47b25119ba	added missing files	2014-08-10 18:23:55 +00:00
Markus Fröschle	5c0ec291d8	fixed dbg() printout macro	2014-08-10 18:22:59 +00:00
Markus Fröschle	8a887fae45	added additional functions for cache handling	2014-08-10 18:21:49 +00:00
Markus Fröschle	4d79841c12	fixed warning regarding incompatible pointers	2014-08-10 18:20:15 +00:00
Markus Fröschle	699ae1917b	made stack location symbolic	2014-08-10 17:19:10 +00:00
Markus Fröschle	6befb6fc46	modified jtagwait to allow to set reset start address when renamed to .TTP	2014-08-10 14:39:06 +00:00
Markus Fröschle	2560f26f99	added missing check for _FPGA_JTAG_VALID	2014-08-09 13:56:28 +00:00
Markus Fröschle	2c870a639d	added missing files forgot on last commit	2014-08-09 13:10:13 +00:00
Markus Fröschle	d842254b36	support for JTAGWAIT.PRG (configure FPGA from JTAG port) implemented	2014-08-09 13:07:28 +00:00
Markus Fröschle	6dbe795815	simplified PLL initialization	2014-08-08 19:52:07 +00:00
Markus Fröschle	bd14381192	simplified pll initialization	2014-08-08 16:13:14 +00:00
Markus Fröschle	1e471ec8cd	bumped version for release	2014-08-06 06:23:30 +00:00
Markus Fröschle	e3e202a7cc	added tos programs that are used to interface to BaS_gcc from TOS. These programs are currently not build by default (need to call make in their respective directory for now). They expect to find a libcmini copy on the same directory level than you have your BaS_gcc folder.	2014-08-02 08:25:07 +00:00
David Gálvez	8b8206cf97	Add format specifier to fix debug messages format	2014-07-13 15:18:23 +00:00
David Gálvez	77d134150a	Make PCI memory space uncachable	2014-07-10 16:46:21 +00:00
David Gálvez	8d62eb705f	Merge pci_BaS_gcc branch to trunk	2014-07-10 15:45:45 +00:00
Markus Fröschle	68aac6bf71	fixed formatting	2014-06-23 18:23:44 +00:00
Markus Fröschle	067b31c31d	fixed formatting	2014-06-23 05:46:13 +00:00
Markus Fröschle	53644425ea	fixed compiler warnings	2014-06-23 05:37:51 +00:00
Markus Fröschle	2ba3d52843	fixed a few compiler warnings	2014-06-23 05:32:49 +00:00
Markus Fröschle	7fd0c0c663	modified init_fpga() to honour JTAG configuration. Does not work currently and needs support from the TOS side (program not finished yet)	2014-06-22 16:00:49 +00:00
Markus Fröschle	ae44abc952	added Doxyfile for doxygen documentation	2014-06-21 19:53:54 +00:00
Markus Fröschle	1dc12f4b05	added BaS includes	2014-06-21 19:52:23 +00:00
Markus Fröschle	49e3eb31e4	added ST fonts	2014-06-21 19:48:22 +00:00
David Gálvez	73f75895bc	Add driver interface for PCI	2014-05-21 08:40:50 +00:00
David Gálvez	f0d0af7add	Create new branch for PCI development	2014-05-21 07:38:47 +00:00
Markus Fröschle	a23abf0b5d	corresponds to the equivalent file release. Contains networking code for EmuTOS, PCI bus scan and card configuration. X86emu included but deactivated.	2014-01-06 19:50:52 +00:00