for ITLB misses, map following page also since sometimes (prefetch?) the

fault PC reported by the access error exceptions seems to be off a few
instructions.

.gdbinit

@@ -1,7 +1,9 @@
 #set disassemble-next-line on
 define tr
-	#target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3
-	target remote | m68k-bdm-gdbserver pipe /dev/tblcf3
+	#!killall m68k-bdm-gdbserver
+	target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3
+	#target remote localhost:1234
+	#target remote | m68k-bdm-gdbserver pipe /dev/tblcf3
 	#target dbug /dev/ttyS0
 	#monitor bdm-reset
 end

BaS_gcc.config

@@ -0,0 +1 @@
+// ADD PREDEFINED MACROS HERE!

BaS_gcc.creator

@@ -0,0 +1 @@
+[General]

BaS_gcc.files

@@ -0,0 +1,271 @@
+dma/dma.c
+dma/MCD_dmaApi.c
+dma/MCD_tasks.c
+dma/MCD_tasksInit.c
+exe/basflash.c
+exe/basflash_start.c
+firebee/bas.elf
+firebee/bas.lk
+firebee/bas.map
+firebee/bas.s19
+firebee/basflash.elf
+firebee/basflash.map
+firebee/basflash.s19
+firebee/bashflash.lk
+firebee/depend
+firebee/libbas.a
+firebee/ram.elf
+firebee/ram.lk
+firebee/ram.map
+firebee/ram.s19
+flash/flash.c
+flash/s19reader.c
+fs/cc932.c
+fs/cc936.c
+fs/cc949.c
+fs/cc950.c
+fs/ccsbcs.c
+fs/ff.c
+fs/unicode.c
+if/driver_vec.c
+include/acia.h
+include/am79c874.h
+include/arp.h
+include/ati_ids.h
+include/bas_printf.h
+include/bas_string.h
+include/bas_types.h
+include/bas_utils.h
+include/bcm5222.h
+include/bootp.h
+include/cache.h
+include/diskio.h
+include/dma.h
+include/driver_mem.h
+include/driver_vec.h
+include/edid.h
+include/ehci.h
+include/eth.h
+include/exceptions.h
+include/fb.h
+include/fec.h
+include/fecbd.h
+include/ff.h
+include/ffconf.h
+include/firebee.h
+include/i2c-algo-bit.h
+include/i2c.h
+include/icmp.h
+include/ikbd.h
+include/interrupts.h
+include/ip.h
+include/m54455.h
+include/m5484l.h
+include/MCD_dma.h
+include/mcd_initiators.h
+include/MCD_progCheck.h
+include/MCD_tasksInit.h
+include/MCF5475.h
+include/MCF5475_CLOCK.h
+include/MCF5475_CTM.h
+include/MCF5475_DMA.h
+include/MCF5475_DSPI.h
+include/MCF5475_EPORT.h
+include/MCF5475_FBCS.h
+include/MCF5475_FEC.h
+include/MCF5475_GPIO.h
+include/MCF5475_GPT.h
+include/MCF5475_I2C.h
+include/MCF5475_INTC.h
+include/MCF5475_MMU.h
+include/MCF5475_PAD.h
+include/MCF5475_PCI.h
+include/MCF5475_PCIARB.h
+include/MCF5475_PSC.h
+include/MCF5475_SDRAMC.h
+include/MCF5475_SEC.h
+include/MCF5475_SIU.h
+include/MCF5475_SLT.h
+include/MCF5475_SRAM.h
+include/MCF5475_USB.h
+include/MCF5475_XLB.h
+include/mmu.h
+include/mod_devicetable.h
+include/nbuf.h
+include/net.h
+include/net_timer.h
+include/nif.h
+include/ohci.h
+include/part.h
+include/pci.h
+include/pci_ids.h
+include/queue.h
+include/radeon_reg.h
+include/radeonfb.h
+include/s19reader.h
+include/screen.h
+include/sd_card.h
+include/startcf.h
+include/sysinit.h
+include/tftp.h
+include/udp.h
+include/usb.h
+include/usb_defs.h
+include/user_io.h
+include/util.h
+include/version.h
+include/videl.h
+include/video.h
+include/wait.h
+include/x86debug.h
+include/x86decode.h
+include/x86emu.h
+include/x86emui.h
+include/x86fpu.h
+include/x86fpu_regs.h
+include/x86ops.h
+include/x86pcibios.h
+include/x86prim_asm.h
+include/x86prim_ops.h
+include/x86regs.h
+include/xhdi_sd.h
+kbd/ikbd.c
+m54455/bas.elf
+m54455/bas.lk
+m54455/bas.map
+m54455/bas.s19
+m54455/basflash.elf
+m54455/basflash.map
+m54455/basflash.s19
+m54455/bashflash.lk
+m54455/depend
+m54455/libbas.a
+m54455/ram.elf
+m54455/ram.lk
+m54455/ram.map
+m54455/ram.s19
+m5484lite/bas.elf
+m5484lite/bas.lk
+m5484lite/bas.map
+m5484lite/bas.s19
+m5484lite/basflash.elf
+m5484lite/basflash.map
+m5484lite/basflash.s19
+m5484lite/bashflash.lk
+m5484lite/depend
+m5484lite/libbas.a
+m5484lite/ram.elf
+m5484lite/ram.lk
+m5484lite/ram.map
+m5484lite/ram.s19
+net/am79c874.c
+net/arp.c
+net/bcm5222.c
+net/bootp.c
+net/fec.c
+net/fecbd.c
+net/ip.c
+net/nbuf.c
+net/net_timer.c
+net/nif.c
+net/queue.c
+net/tftp.c
+net/udp.c
+nutil/s19header
+nutil/s19header.c
+pci/ehci-hcd.c
+pci/ohci-hcd.c
+pci/pci.c
+radeon/radeon_accel.c
+radeon/radeon_base.c
+radeon/radeon_cursor.c
+radeon/radeon_monitor.c
+spi/dspi.c
+spi/mmc.c
+spi/sd_card.c
+sys/BaS.c
+sys/cache.c
+sys/driver_mem.c
+sys/exceptions.S
+sys/fault_vectors.c
+sys/init_fpga.c
+sys/interrupts.c
+sys/mmu.c
+sys/startcf.S
+sys/sysinit.c
+usb/usb.c
+usb/usb_mouse.c
+util/bas_printf.c
+util/bas_string.c
+util/printf_helper.S
+util/wait.c
+video/fbmem.c
+video/fbmodedb.c
+video/fbmon.c
+video/fnt_st_8x16.c
+video/offscreen.c
+video/vdi_fill.c
+video/videl.c
+video/video.c
+x86emu/x86biosemu.c
+x86emu/x86debug.c
+x86emu/x86decode.c
+x86emu/x86fpu.c
+x86emu/x86ops.c
+x86emu/x86ops2.c
+x86emu/x86pcibios.c
+x86emu/x86prim_ops.c
+x86emu/x86sys.c
+xhdi/xhdi_interface.c
+xhdi/xhdi_sd.c
+xhdi/xhdi_vec.S
+bas.lk.in
+bas_firebee.bdm
+bas_m5484.bdm
+basflash.lk.in
+check.bdm
+COPYING
+COPYING.LESSER
+dump.bdm
+mcf5474.gdb
+Makefile
+tos/jtagwait/Makefile
+tos/jtagwait/sources/jtagwait.c
+tos/jtagwait/include/driver_vec.h
+tos/bascook/Makefile
+tos/mcdcook/sources/bascook.c
+tos/jtagwait/include/bas_printf.h
+tos/jtagwait/include/bas_string.h
+tos/jtagwait/include/MCF5475_CLOCK.h
+tos/jtagwait/include/MCF5475_CTM.h
+tos/jtagwait/include/MCF5475_DMA.h
+tos/jtagwait/include/MCF5475_DSPI.h
+tos/jtagwait/include/MCF5475_EPORT.h
+tos/jtagwait/include/MCF5475_FBCS.h
+tos/jtagwait/include/MCF5475_FEC.h
+tos/jtagwait/include/MCF5475_GPIO.h
+tos/jtagwait/include/MCF5475_GPT.h
+tos/jtagwait/include/MCF5475_I2C.h
+tos/jtagwait/include/MCF5475_INTC.h
+tos/jtagwait/include/MCF5475_MMU.h
+tos/jtagwait/include/MCF5475_PAD.h
+tos/jtagwait/include/MCF5475_PCI.h
+tos/jtagwait/include/MCF5475_PCIARB.h
+tos/jtagwait/include/MCF5475_PSC.h
+tos/jtagwait/include/MCF5475_SDRAMC.h
+tos/jtagwait/include/MCF5475_SEC.h
+tos/jtagwait/include/MCF5475_SIU.h
+tos/jtagwait/include/MCF5475_SLT.h
+tos/jtagwait/include/MCF5475_SRAM.h
+tos/jtagwait/include/MCF5475_USB.h
+tos/jtagwait/include/MCF5475_XLB.h
+tos/jtagwait/include/MCF5475.h
+tos/jtagwait/include/driver_vec.h
+tos/jtagwait/sources/bas_printf.c
+tos/jtagwait/sources/bas_string.c
+tos/jtagwait/sources/printf_helper.S
+tos/bascook/Makefile
+tos/bascook/sources/bascook.c
+tos/Makefile
+usb/usb_hub.c
+include/usb_hub.h

BaS_gcc.includes

@@ -0,0 +1,2 @@
+include
+/usr/m68k-elf/include

Makefile

@@ -15,7 +15,7 @@ ifeq (Y,$(COMPILE_ELF))
 TCPREFIX=m68k-elf-
 EXE=elf
 FORMAT=elf32-m68k
-else 
+else
 TCPREFIX=m68k-atari-mint-
 EXE=s19
 FORMAT=srec
@@ -32,20 +32,21 @@ NATIVECC=gcc
 INCLUDE=-Iinclude
 CFLAGS=-mcpu=5474 \
 		-Wall \
-		-Os \
+		-g3 \
 		-fomit-frame-pointer \
 		-ffreestanding \
 		-fleading-underscore \
 		-Wa,--register-prefix-optional
 CFLAGS_OPTIMIZED = -mcpu=5474 \
 		-Wall \
+		-g3 \
 		-O2 \
 		-fomit-frame-pointer \
 		-ffreestanding \
 		-fleading-underscore \
 		-Wa,--register-prefix-optional
 
-TRGTDIRS= ./firebee ./m5484lite
+TRGTDIRS= ./firebee ./m5484lite ./m54455
 OBJDIRS=$(patsubst %, %/objs,$(TRGTDIRS))
 TOOLDIR=util
 
@@ -94,6 +95,7 @@ CSRCS= \
 	usb.c \
 	ohci-hcd.c \
 	ehci-hcd.c \
+	usb_hub.c \
 	usb_mouse.c \
 	ikbd.c \
 	\
@@ -123,6 +125,7 @@ CSRCS= \
 	radeon_accel.c \
 	radeon_cursor.c \
 	radeon_monitor.c \
+	fnt_st_8x16.c \
 	\
 	x86decode.c \
 	x86sys.c \
@@ -135,14 +138,14 @@ CSRCS= \
 	x86pcibios.c \
 	\
 	basflash.c \
-	basflash_start.c 
+	basflash_start.c
 
 
 ASRCS= \
 	startcf.S \
-	printf_helper.S \
 	exceptions.S \
-	xhdi_vec.S
+	xhdi_vec.S \
+	pci_wrappers.S
 
 SRCS=$(ASRCS) $(CSRCS)
 COBJS=$(patsubst %.c,%.o,$(CSRCS))
@@ -153,12 +156,18 @@ LIBBAS=libbas.a
 
 LIBS=$(patsubst %,%/$(LIBBAS),$(TRGTDIRS))
 
-all: fls ram bfl lib
+all: ver fls ram bfl lib tos
 fls: $(patsubst %,%/$(FLASH_EXEC),$(TRGTDIRS))
 ram: $(patsubst %,%/$(RAM_EXEC),$(TRGTDIRS))
 bfl: $(patsubst %,%/$(BASFLASH_EXEC),$(TRGTDIRS))
 lib: $(LIBS)
 
+.PHONY: ver
+ver:
+	touch include/version.h
+.PHONY: tos
+tos:
+	(cd tos; make)
 
 .PHONY: clean
 clean:
@@ -170,32 +179,35 @@ clean:
 
 # flags for targets
 m5484lite/bas.$(EXE): MACHINE=MACHINE_M5484LITE
+m54455/bas.$(EXE): MACHINE=MACHINE_M54455
 firebee/bas.$(EXE): MACHINE=MACHINE_FIREBEE
 m5484lite/ram.$(EXE): MACHINE=MACHINE_M5484LITE
+m54455/ram.$(EXE): MACHINE=MACHINE_M54455
 firebee/ram.$(EXE): MACHINE=MACHINE_FIREBEE
 m5484lite/basflash.$(EXE): MACHINE=MACHINE_M5484LITE
+m54455/basflash.$(EXE): MACHINE=MACHINE_M54455
 firebee/basflash.$(EXE): MACHINE=MACHINE_FIREBEE
 
 #
 # generate pattern rules for different object files
 #
 define CC_TEMPLATE
-ifeq (firebee,$(1))
-	MACHINE=MACHINE_FIREBEE
-else
-	MACHINE=MACHINE_M5484LITE
-endif
+#ifeq (firebee,$(1))
+	#MACHINE=MACHINE_FIREBEE
+#else
+	#MACHINE=MACHINE_M5484LITE
+#endif
 
 # always optimize x86 emulator objects
-$(1)/objs/x86decode.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
-$(1)/objs/x86sys.o:		CFLAGS=$(CFLAGS_OPTIMIZED)
-$(1)/objs/x86debug.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
-$(1)/objs/x86prim_ops.o:CFLAGS=$(CFLAGS_OPTIMIZED)
-$(1)/objs/x86ops.o:		CFLAGS=$(CFLAGS_OPTIMIZED)
-$(1)/objs/x86ops2.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
-$(1)/objs/x86fpu.o:		CFLAGS=$(CFLAGS_OPTIMIZED)
-$(1)/objs/x86biosemu.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
-$(1)/objs/x86pcibios.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
+#$(1)/objs/x86decode.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
+#$(1)/objs/x86sys.o:		CFLAGS=$(CFLAGS_OPTIMIZED)
+#$(1)/objs/x86debug.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
+#$(1)/objs/x86prim_ops.o:CFLAGS=$(CFLAGS_OPTIMIZED)
+#$(1)/objs/x86ops.o:		CFLAGS=$(CFLAGS_OPTIMIZED)
+#$(1)/objs/x86ops2.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
+#$(1)/objs/x86fpu.o:		CFLAGS=$(CFLAGS_OPTIMIZED)
+#$(1)/objs/x86biosemu.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
+#$(1)/objs/x86pcibios.o:	CFLAGS=$(CFLAGS_OPTIMIZED)
 
 $(1)/objs/%.o:%.c
 	$(CC) $$(CFLAGS) -D$$(MACHINE) $(INCLUDE) -c $$< -o $$@
@@ -257,7 +269,7 @@ endif
 $(1)_MAPFILE_RAM=$(1)/$$(basename $$(RAM_EXEC)).map
 $(1)/$$(RAM_EXEC): $(1)/$(LIBBAS) $(LDCSRC)
 	$(CPP) $(INCLUDE) -DCOMPILE_RAM -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCSRC) -o $(1)/$$(LDRFILE)
-	$(LD) --oformat $$(FORMAT) -Map $$($(1)_MAPFILE_RAM) --cref -T $(1)/$$(LDRFILE) -o $$@
+	$(LD) -g --oformat $$(FORMAT) -Map $$($(1)_MAPFILE_RAM) --cref -T $(1)/$$(LDRFILE) -o $$@
 ifeq ($(COMPILE_ELF),Y)
 	$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
 else
@@ -280,21 +292,21 @@ $(foreach DIR,$(TRGTDIRS),$(eval $(call EX_TEMPLATE,$(DIR))))
 
 indent: $(CSRCS)
 	indent $<
-	
+
 .PHONY: tags
 tags:
 	ctags $(patsubst %,%/*,$(VPATH))
-	
+
 .PHONY: printvars
 printvars:
 	@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
 ifeq (MACHINE_M5484LITE,$$(MACHINE))
 	MNAME=m5484lite
 else ifeq (MACHINE_FIREBEE,$(MACHINE))
-   	MNAME=firebee
+	MNAME=firebee
 endif
 
 tools:
-	$(NATIVECC) $(INCLUDE) -c $(TOOLDIR)/s19header.c -o $(TOOLDIR)/s19header.o 
+	$(NATIVECC) $(INCLUDE) -c $(TOOLDIR)/s19header.c -o $(TOOLDIR)/s19header.o
 	$(NATIVECC) -o $(TOOLDIR)/s19header $(TOOLDIR)/s19header.o
 

bas.lk.in

@@ -1,9 +1,11 @@
-#ifdef MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
 #include "firebee.h"
-#endif /* MACHINE_FIREBEE */
-
-#ifdef MACHINE_M5484LITE
+#elif defined(MACHINE_M5484LITE)
 #include "m5484l.h"
+#elif defined(MACHINE_M54455)
+#include "m54455.h"
+#else
+#error "unknown machine!"
 #endif /* MACHINE_M5484LITE */
 
 /* make bas_rom access flags rx if compiling to RAM */
@@ -21,7 +23,7 @@ MEMORY
 	*/
    bas_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00200000, LENGTH = 0x00100000
    /*
-    * driver_ram is an uncached, reserved memory area for drivers (e.g. USB) that need this type of memory
+	* driver_ram is an uncached, reserved memory area for drivers (e.g. USB) that need this type of memory
 	*/
    driver_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00100000, LENGTH = 0x00100000
 }
@@ -42,12 +44,14 @@ SECTIONS
 		OBJDIR/exceptions.o(.text)
 		OBJDIR/driver_vec.o(.text)
 		OBJDIR/interrupts.o(.text)
-		OBJDIR/mmu.o(.text)		
-		
+		OBJDIR/mmu.o(.text)
+
 		OBJDIR/BaS.o(.text)
 		OBJDIR/pci.o(.text)
+		OBJDIR/pci_wrappers.o(.text)
 		OBJDIR/usb.o(.text)
 		OBJDIR/driver_mem.o(.text)
+		OBJDIR/usb_hub.o(.text)
 		OBJDIR/usb_mouse.o(.text)
 		OBJDIR/ohci-hcd.o(.text)
 		OBJDIR/ehci-hcd.o(.text)
@@ -74,7 +78,6 @@ SECTIONS
 		OBJDIR/s19reader.o(.text)
 		OBJDIR/bas_printf.o(.text)
 		OBJDIR/bas_string.o(.text)
-		OBJDIR/printf_helper.o(.text)
 		OBJDIR/cache.o(.text)
 		OBJDIR/dma.o(.text)
 		OBJDIR/MCD_dmaApi.o(.text)
@@ -106,7 +109,7 @@ SECTIONS
 		OBJDIR/xhdi_sd.o(.text)
 		OBJDIR/xhdi_interface.o(.text)
 		OBJDIR/xhdi_vec.o(.text)
-		
+
 #ifdef COMPILE_RAM
 		/*
 		 * if we compile to RAM anyway, there is no need to copy anything
@@ -116,7 +119,7 @@ SECTIONS
 		*(.data)
 		__BAS_DATA_END = .;
 		__BAS_BSS_START = .;
-		*(.bss)	
+		*(.bss)
 		__BAS_BSS_END = .;
 #endif /* COMPILE_RAM */
 
@@ -138,7 +141,7 @@ SECTIONS
 		*(.data)
 		__BAS_DATA_END = .;
 		__BAS_BSS_START = .;
-		*(.bss)	
+		*(.bss)
 		__BAS_BSS_END = .;
 
 		. = ALIGN(16);
@@ -151,16 +154,16 @@ SECTIONS
 		_driver_mem_buffer = .;
 		//. = . + DRIVER_MEM_BUFFER_SIZE;
 	} > driver_ram
-	
+
 	/*
 	 * Global memory map
 	 */
 
 	/* SDRAM Initialization */
- 	___SDRAM                = SDRAM_START;
- 	___SDRAM_SIZE           = SDRAM_SIZE;
+	___SDRAM                = SDRAM_START;
+	___SDRAM_SIZE           = SDRAM_SIZE;
 	_SDRAM_VECTOR_TABLE		= ___SDRAM;
-	
+
 	/* ST-RAM */
 	__STRAM                 = ___SDRAM;
 	__STRAM_END             = __TOS;
@@ -171,16 +174,17 @@ SECTIONS
 	/* FastRAM */
 	__FASTRAM               = 0x10000000;
 	__TARGET_ADDRESS		= TARGET_ADDRESS;
-	
+
 #if TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS
 	__FASTRAM_END           = __BAS_IN_RAM;
 #else
 	__FASTRAM_END			= TARGET_ADDRESS;
 #endif
+	__FASTRAM_SIZE			= __FASTRAM_END - __FASTRAM;
 
 	/* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */
 	___BOOT_FLASH           = BOOTFLASH_BASE_ADDRESS;
- 	___BOOT_FLASH_SIZE      = BOOTFLASH_SIZE;
+	___BOOT_FLASH_SIZE      = BOOTFLASH_SIZE;
 
 #if TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS
 	/* BaS */
@@ -200,35 +204,41 @@ SECTIONS
 	__EMUTOS_SIZE           = 0x00100000;
 
 	/* where FPGA data lives in flash */
-	__FPGA_FLASH_DATA 		= 0xe0700000;
-	__FPGA_FLASH_DATA_SIZE 	= 0x100000;
+	__FPGA_CONFIG 		= 0xe0700000;
+	__FPGA_CONFIG_SIZE 	= 0x100000;
 
 	/* VIDEO RAM BASIS */
 	__VRAM                  = 0x60000000;
 
 	/* Memory mapped registers */
- 	__MBAR                  = 0xFF000000;
-	
+	__MBAR                  = 0xFF000000;
+
 	/* 32KB on-chip System SRAM */
- 	__SYS_SRAM              = __MBAR + 0x10000;
+	__SYS_SRAM              = __MBAR + 0x10000;
 	__SYS_SRAM_SIZE         = 0x00008000;
 
 	/* MMU memory mapped registers */
- 	__MMUBAR                = 0xFF040000;
+	__MMUBAR                = 0xFF040000;
 
 	/*
-	 * 4KB on-chip Core SRAM0: -> exception table 
+	 * 4KB on-chip Core SRAM0: -> exception table
 	 */
- 	__RAMBAR0               = 0xFF100000;
- 	__RAMBAR0_SIZE          = 0x00001000;
+	__RAMBAR0               = 0xFF100000;
+	__RAMBAR0_SIZE          = 0x00001000;
 
 	/* 4KB on-chip Core SRAM1 */
- 	__RAMBAR1               = 0xFF101000;
- 	__RAMBAR1_SIZE          = 0x00001000;
- 	__SUP_SP                = __RAMBAR0 + __RAMBAR0_SIZE - 4;
+	__RAMBAR1               = 0xFF101000;
+	__RAMBAR1_SIZE          = 0x00001000;
+	__SUP_SP                = __RAMBAR1 + __RAMBAR1_SIZE - 4;
 
+	/*
+	 * this flag (if 1) indicates that FPGA configuration has been loaded through JTAG
+	 * and shouldn't be overwritten on boot
+	 */
+	__FPGA_JTAG_LOADED		= __RAMBAR1;
+	__FPGA_JTAG_VALID		= __RAMBAR1 + 4;
 	/* system variables */
-	
+
 	/* RAMBAR0 0 to 0x7FF -> exception vectors */
 	_rt_mod    = __RAMBAR0 + 0x800;
 	_rt_ssp    = __RAMBAR0 + 0x804;

dma/MCD_dmaApi.c

@@ -66,12 +66,12 @@ MCD_bufDesc *MCD_relocBuffDesc;
  */
 #define DBG_CTL_COMP1_TASK  (0x00002000) /* have comparator 1 look for a task # */
 #define DBG_CTL_ENABLE      (DBG_CTL_AUTO_ARM    | \
-                             DBG_CTL_BREAK       | \
-                             DBG_CTL_INT_BREAK   | \
-                             DBG_CTL_COMP1_TASK)
+							 DBG_CTL_BREAK       | \
+							 DBG_CTL_INT_BREAK   | \
+							 DBG_CTL_COMP1_TASK)
 #define DBG_CTL_DISABLE     (DBG_CTL_AUTO_ARM    | \
-                             DBG_CTL_INT_BREAK   | \
-                             DBG_CTL_COMP1_TASK)
+							 DBG_CTL_INT_BREAK   | \
+							 DBG_CTL_COMP1_TASK)
 #define DBG_KILL_ALL_STAT   (0xFFFFFFFF)
 
 /*
@@ -247,10 +247,10 @@ int MCD_initDma(dmaRegs *dmaBarAddr, void *taskTableDest, uint32_t flags)
 			entryPtr[i].TDTend = (uint32_t) taskDescTabsOffset - 4;
 		}
 #ifdef MCD_INCLUDE_EU /* Tack single DMA BDs onto end of code so API controls
-                         where they are since DMA might write to them */
+						 where they are since DMA might write to them */
 		MCD_relocBuffDesc = (MCD_bufDesc*)(entryPtr[NUMOFVARIANTS - 1].TDTend + 4);
-#else /* DMA does not touch them so they can be wherever and we don't need to 
-         waste SRAM on them */
+#else /* DMA does not touch them so they can be wherever and we don't need to
+		 waste SRAM on them */
 		MCD_relocBuffDesc = MCD_singleBufDescs;
 #endif
 	}
@@ -352,7 +352,7 @@ int MCD_dmaStatus(int channel)
  * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
  */
 
-int __attribute__((flatten)) MCD_startDma(int channel, /* the channel on which to run the DMA */
+int MCD_startDma(int channel, /* the channel on which to run the DMA */
 		int8_t *srcAddr, /* the address to move data from, or physical buffer-descriptor address */
 		int16_t srcIncr, /* the amount to increment the source address per transfer */
 		int8_t *destAddr, /* the address to move data to */
@@ -582,7 +582,7 @@ int __attribute__((flatten)) MCD_startDma(int channel, /* the channel on which t
  * Notes:
  *  MCD_XferProgrQuery() upon completing or after aborting a DMA, or
  *  while the DMA is in progress, this function returns the first
- *  DMA-destination address not (or not yet) used in the DMA. When 
+ *  DMA-destination address not (or not yet) used in the DMA. When
  *  encountering a non-ready buffer descriptor, the information for
  *  the last completed descriptor is returned.
  *
@@ -850,7 +850,7 @@ int MCD_continDma(int channel)
  * this means that bits 14 and 0 must enable debug functions before
  * bits 1 and 2, respectively, have any effect.
  *
- * NOTE: It's extremely important to not pause more than one DMA channel 
+ * NOTE: It's extremely important to not pause more than one DMA channel
  *  at a time.
  ********************************************************************/
 

dma/dma.c

@@ -29,15 +29,19 @@
 #include "cache.h"
 #include "exceptions.h"
 
-#if MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
 #include "firebee.h"
-#elif MACHINE_M5484LITE
+#elif defined(MACHINE_M5484LITE)
 #include "m5484l.h"
+#elif defined(MACHINE_M54455)
+#include "m54455.h"
+#else
+#error "unknown machine!"
 #endif /* MACHINE_FIREBEE */
 
-//#define DBG_DMA
+#define DBG_DMA
 #ifdef DBG_DMA
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_DMA */
@@ -54,13 +58,13 @@ struct dma_channel
 static char used_reqs[32] =
 {
 	DMA_ALWAYS,  DMA_DSPI_RXFIFO, DMA_DSPI_TXFIFO, DMA_DREQ0,
-    DMA_PSC0_RX, DMA_PSC0_TX, DMA_USB_EP0,  DMA_USB_EP1,
-    DMA_USB_EP2,  DMA_USB_EP3,  DMA_PCI_TX,  DMA_PCI_RX,
-    DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX,  DMA_I2C_TX,
-    0,           0,           0,           0,
-    0,           0,           0,           0,
-    0,           0,           0,           0,
-    0,           0,           0,           0
+	DMA_PSC0_RX, DMA_PSC0_TX, DMA_USB_EP0,  DMA_USB_EP1,
+	DMA_USB_EP2,  DMA_USB_EP3,  DMA_PCI_TX,  DMA_PCI_RX,
+	DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX,  DMA_I2C_TX,
+	0,           0,           0,           0,
+	0,           0,           0,           0,
+	0,           0,           0,           0,
+	0,           0,           0,           0
 };
 
 static struct dma_channel dma_channel[NCHANNELS] =
@@ -71,7 +75,6 @@ static struct dma_channel dma_channel[NCHANNELS] =
 	{-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL},
 };
 
-/********************************************************************/
 /*
  * Enable all DMA interrupts
  *
@@ -85,7 +88,7 @@ void dma_irq_enable(uint8_t lvl, uint8_t pri)
 	MCF_INTC_ICR48 = 0
 		| MCF_INTC_ICR_IP(pri)
 		| MCF_INTC_ICR_IL(lvl);
-	dbg("%s:DMA irq assigned level %d, priority %d\r\n", __FUNCTION__, lvl, pri);
+	dbg("DMA irq assigned level %d, priority %d\r\n", lvl, pri);
 
 	/* Unmask all task interrupts */
 	MCF_DMA_DIMR = 0;
@@ -96,11 +99,9 @@ void dma_irq_enable(uint8_t lvl, uint8_t pri)
 	/* Unmask the DMA interrupt in the interrupt controller */
 	MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK48;
 
-	dbg("%s: DMA task interrupts unmasked, pending interrupts cleared, interrupt controller active\r\n",
-		__FUNCTION__);
+	dbg("DMA task interrupts unmasked, pending interrupts cleared, interrupt controller active\r\n");
 }
 
-/********************************************************************/
 /*
  * Disable all DMA interrupts
  */
@@ -115,7 +116,7 @@ void dma_irq_disable(void)
 	/* Mask the DMA interrupt in the interrupt controller */
 	MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK48;
 
-	dbg("%s: DMA interrupts masked and disabled\r\n", __FUNCTION__);
+	dbg("DMA interrupts masked and disabled\r\n");
 }
 
 int dma_set_initiator(int initiator)
@@ -173,7 +174,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot found\r\n", __FUNCTION__);
+				dbg("no free slot found\r\n");
 
 				return 1;
 			}
@@ -192,7 +193,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");
 
 				return 1;
 			}
@@ -206,7 +207,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");
 
 				return 1;
 			}
@@ -220,8 +221,8 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
-				
+				dbg("no free slot\r\n");
+
 				return 1;
 			}
 			break;
@@ -234,7 +235,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");
 
 				return 1;
 			}
@@ -248,7 +249,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");
 
 				return 1;
 			}
@@ -262,7 +263,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");
 
 				return 1;
 			}
@@ -276,7 +277,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");
 
 				return 1;
 			}
@@ -290,7 +291,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");
 
 				return 1;
 			}
@@ -304,7 +305,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");
 
 				return 1;
 			}
@@ -318,7 +319,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");
 
 				return 1;
 			}
@@ -332,7 +333,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");
 
 				return 1;
 			}
@@ -355,7 +356,7 @@ int dma_set_initiator(int initiator)
 				used_reqs[28] = DMA_PSC2_RX;            }
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");
 
 				return 1;
 			}
@@ -369,7 +370,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");
 
 				return 1;
 			}
@@ -383,7 +384,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");
 
 				return 1;
 			}
@@ -397,7 +398,7 @@ int dma_set_initiator(int initiator)
 			}
 			else /* No empty slots */
 			{
-				dbg("%s: no free slot\r\n", __FUNCTION__);
+				dbg("no free slot\r\n");
 
 				return 1;
 			}
@@ -405,7 +406,7 @@ int dma_set_initiator(int initiator)
 
 		default:
 			{
-				dbg("%s: don't know what to do\r\n", __FUNCTION__);
+				dbg("don't know what to do\r\n");
 
 				return 1;
 			}
@@ -432,7 +433,7 @@ uint32_t dma_get_initiator(int requestor)
 		if (used_reqs[i] == requestor)
 			return i;
 	}
-	dbg("%s: no initiator found for requestor %d\r\n", __FUNCTION__, requestor);
+	dbg("no initiator found for requestor %d\r\n", requestor);
 
 	return 0;
 }
@@ -455,7 +456,7 @@ void dma_free_initiator(int requestor)
 			break;
 		}
 	}
-	dbg("%s: DMA requestor %d freed\r\n", __FUNCTION__, requestor);
+	dbg("DMA requestor %d freed\r\n", requestor);
 }
 
 /*
@@ -472,7 +473,7 @@ int dma_set_channel(int requestor, void (*handler)(void))
 	int i;
 
 	/* Check to see if this requestor is already assigned to a channel */
-	dbg("%s: check if requestor %d is already assigned to a channel\r\n", __FUNCTION__, requestor);
+	dbg("check if requestor %d is already assigned to a channel\r\n", requestor);
 	if ((i = dma_get_channel(requestor)) != -1)
 		return i;
 
@@ -482,11 +483,11 @@ int dma_set_channel(int requestor, void (*handler)(void))
 		{
 			dma_channel[i].req = requestor;
 			dma_channel[i].handler = handler;
-			dbg("%s: assigned channel %d to requestor %d\r\n", __FUNCTION__, i, requestor);
+			dbg("assigned channel %d to requestor %d\r\n", i, requestor);
 			return i;
 		}
 	}
-	dbg("%s: no free DMA channel found for requestor %d\r\n", __FUNCTION__, requestor);
+	dbg("no free DMA channel found for requestor %d\r\n", requestor);
 
 	/* All channels taken */
 	return -1;
@@ -498,7 +499,7 @@ void dma_clear_channel(int channel)
 	{
 		dma_channel[channel].req = -1;
 		dma_channel[channel].handler = NULL;
-		dbg("%s: cleared DMA channel %d\r\n", __FUNCTION__, channel);
+		dbg("cleared DMA channel %d\r\n", channel);
 	}
 }
 
@@ -521,12 +522,12 @@ int dma_get_channel(int requestor)
 		if (dma_channel[i].req == requestor)
 			return i;
 	}
-	dbg("%s: no channel occupied by requestor %d\r\n", __FUNCTION__, requestor);
+	dbg("no channel occupied by requestor %d\r\n", requestor);
 	return -1;
 }
 
 /*
- * Remove the channel being initiated by the given requestor from 
+ * Remove the channel being initiated by the given requestor from
  * the active list
  *
  * Parameters:
@@ -547,17 +548,18 @@ void dma_free_channel(int requestor)
 	}
 }
 
-/* 
- * This is the catch-all interrupt handler for the mult-channel DMA 
+/*
+ * This is the catch-all interrupt handler for the mult-channel DMA
  */
 int dma_interrupt_handler(void *arg1, void *arg2)
 {
 	int i, interrupts;
+	uint32_t ipl;
 
-	(void) set_ipl(7);
+	ipl = set_ipl(7);		/* do not disturb */
 
-	/* 
-	 * Determine which interrupt(s) triggered by AND'ing the 
+	/*
+	 * Determine which interrupt(s) triggered by AND'ing the
 	 * pending interrupts with those that aren't masked.
 	 */
 	interrupts = MCF_DMA_DIPR & ~MCF_DMA_DIMR;
@@ -565,7 +567,7 @@ int dma_interrupt_handler(void *arg1, void *arg2)
 	/* Make sure we are here for a reason */
 	if (interrupts == 0)
 	{
-		dbg("%s: not DMA interrupt! Spurious?\r\n", __FUNCTION__);
+		dbg("not DMA interrupt! Spurious?\r\n");
 		return 0;
 	}
 
@@ -579,12 +581,14 @@ int dma_interrupt_handler(void *arg1, void *arg2)
 			/* If there is a handler, call it */
 			if (dma_channel[i].handler != NULL)
 			{
-				dbg("%s: call handler for DMA channel %d (%p)\r\n", __FUNCTION__, i, dma_channel[i].handler);
+				dbg("call handler for DMA channel %d (%p)\r\n", i, dma_channel[i].handler);
 				dma_channel[i].handler();
 			}
 		}
 	}
 
+	set_ipl(ipl);
+
 	return 1;	/* handled */
 }
 /********************************************************************/
@@ -592,15 +596,19 @@ int dma_interrupt_handler(void *arg1, void *arg2)
 void *dma_memcpy(void *dst, void *src, size_t n)
 {
 	int ret;
-	volatile int32_t time;
-	volatile int32_t start;
-	volatile int32_t end;
+
+#ifdef DBG_DMA
+	int32_t time;
+	int32_t start;
+	int32_t end;
 
 	start = MCF_SLT0_SCNT;
+#endif /* DBG_DMA */
+
 	ret = MCD_startDma(1, src, 4, dst, 4, n, 4, DMA_ALWAYS, 0, MCD_SINGLE_DMA, 0);
 	if (ret == MCD_OK)
 	{
-		dbg("%s: DMA on channel 1 successfully started\r\n", __FUNCTION__);
+		dbg("DMA on channel 1 successfully started\r\n");
 	}
 
 	do
@@ -640,9 +648,11 @@ void *dma_memcpy(void *dst, void *src, size_t n)
 #endif
 	} while (ret != MCD_DONE);
 
+#ifdef DBG_DMA
 	end = MCF_SLT0_SCNT;
 	time = (start - end) / (SYSCLK / 1000) / 1000;
-	dbg("%s: took %d ms (%f Mbytes/second)\r\n", __FUNCTION__, time, n / (float) time / 1000.0);
+#endif /* DBG_DMA */
+	dbg("took %d ms (%f Mbytes/second)\r\n", time, n / (float) time / 1000.0);
 
 	return dst;
 }
@@ -651,11 +661,11 @@ int dma_init(void)
 {
 	int res;
 
-	dbg("%s: MCD DMA API initialization: ", __FUNCTION__);
+	dbg("MCD DMA API initialization: ");
 	res = MCD_initDma((dmaRegs *) &_MBAR[0x8000], SYS_SRAM, MCD_RELOC_TASKS | MCD_COMM_PREFETCH_EN);
 	if (res != MCD_OK)
 	{
-		dbg("%s: DMA API initialization failed (0x%x)\r\n", __FUNCTION__, res);
+		dbg("DMA API initialization failed (0x%x)\r\n", res);
 		return 0;
 	}
 

exe/basflash.c

@@ -21,10 +21,9 @@
  *      Author: Markus Fröschle
  */
 
-#include <stdint.h>
-#include <stdbool.h>
-#include "bas_string.h"
+#include <bas_types.h>
 #include "bas_printf.h"
+#include "bas_string.h"
 #include "diskio.h"
 #include "ff.h"
 #include "s19reader.h"
@@ -220,190 +219,190 @@ static const int num_flash_areas = sizeof(flash_areas) / sizeof(struct romram);
  */
 void amd_flash_sector_erase(int n)
 {
-    volatile AMD_FLASH_CELL status;
+	volatile AMD_FLASH_CELL status;
 
-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);
 
-    do
-        status = pFlash[SADDR(n)];
-    while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));
+	do
+		status = pFlash[SADDR(n)];
+	while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));
 
-    /*
-     * Place device in read mode
-     */
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+	/*
+	 * Place device in read mode
+	 */
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
 }
 
 int amd_flash_erase(void *start, int bytes, void (*putchar)(int))
 {
-    int i, ebytes = 0;
+	int i, ebytes = 0;
 
-    if (bytes == 0)
-        return 0;
+	if (bytes == 0)
+		return 0;
 
-    for (i = 0; i < AMD_FLASH_SECTORS; i++)
-    {
-        if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
-            start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
-        {
-            break;
-        }
-    }
+	for (i = 0; i < AMD_FLASH_SECTORS; i++)
+	{
+		if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
+			start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
+		{
+			break;
+		}
+	}
 
-    while (ebytes < bytes)
-    {
-        if (putchar != NULL)
-        {
-            putchar('.');
-        }
-        amd_flash_sector_erase(i);
-        ebytes += SSIZE(i);
-        i++;
-    }
+	while (ebytes < bytes)
+	{
+		if (putchar != NULL)
+		{
+			putchar('.');
+		}
+		amd_flash_sector_erase(i);
+		ebytes += SSIZE(i);
+		i++;
+	}
 
-    if (putchar != NULL)
-    {
-        putchar(10);    /* LF */
-        putchar(13);    /* CR */
-    }
+	if (putchar != NULL)
+	{
+		putchar(10);    /* LF */
+		putchar(13);    /* CR */
+	}
 
-    return ebytes;
+	return ebytes;
 }
 
 void amd_flash_program_cell(AMD_FLASH_CELL *dst, AMD_FLASH_CELL data)
 {
-    volatile AMD_FLASH_CELL status;
-    int retry;
+	volatile AMD_FLASH_CELL status;
+	int retry;
 
-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
-    *dst = data;
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
+	*dst = data;
 
-    /*
-     * Wait for program operation to finish
-     *  (Data# Polling Algorithm)
-     */
-    retry = 0;
-    while (1)
-    {
-        status = *dst;
-        if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
-            (data & AMD_FLASH_CMD_DATA(0x80)))
-        {
-            break;
-        }
-        if (status & AMD_FLASH_CMD_DATA(0x20))
-        {
-            status = *dst;
-            if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
-                (data & AMD_FLASH_CMD_DATA(0x80)))
-            {
-                break;
-            }
-            if (++retry > 1024)
-            {
-                break;
-            }
-        }
-    }
+	/*
+	 * Wait for program operation to finish
+	 *  (Data# Polling Algorithm)
+	 */
+	retry = 0;
+	while (1)
+	{
+		status = *dst;
+		if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
+			(data & AMD_FLASH_CMD_DATA(0x80)))
+		{
+			break;
+		}
+		if (status & AMD_FLASH_CMD_DATA(0x20))
+		{
+			status = *dst;
+			if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
+				(data & AMD_FLASH_CMD_DATA(0x80)))
+			{
+				break;
+			}
+			if (++retry > 1024)
+			{
+				break;
+			}
+		}
+	}
 }
 
 
 int amd_flash_program(void *dest, void *source, int bytes, int erase, void (*func)(void), void (*putchar)(int))
 {
-    AMD_FLASH_CELL *src, *dst;
-    int hashi=1,hashj=0;
-    char hash[5];
+	AMD_FLASH_CELL *src, *dst;
+	int hashi=1,hashj=0;
+	char hash[5];
 
-    hash[0]=8;  /* Backspace */
-    hash[1]=124;/* "|" */
-    hash[2]=47; /* "/" */
-    hash[3]=45; /* "-" */
-    hash[4]=92; /* "\" */
+	hash[0]=8;  /* Backspace */
+	hash[1]=124;/* "|" */
+	hash[2]=47; /* "/" */
+	hash[3]=45; /* "-" */
+	hash[4]=92; /* "\" */
 
-    src = (AMD_FLASH_CELL *)source;
-    dst = (AMD_FLASH_CELL *)dest;
+	src = (AMD_FLASH_CELL *)source;
+	dst = (AMD_FLASH_CELL *)dest;
 
-    /*
-     * Place device in read mode
-     */
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+	/*
+	 * Place device in read mode
+	 */
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
 
-    /*
-     * Erase device if necessary
-     */
-    if (erase)
-    {
-        amd_flash_erase(dest, bytes, putchar);
-    }
+	/*
+	 * Erase device if necessary
+	 */
+	if (erase)
+	{
+		amd_flash_erase(dest, bytes, putchar);
+	}
 
-    /*
-     * Program device
-     */
-    while (bytes > 0)
-    {
-        amd_flash_program_cell(dst,*src);
+	/*
+	 * Program device
+	 */
+	while (bytes > 0)
+	{
+		amd_flash_program_cell(dst,*src);
 
-        /* Verify Write */
-        if (*dst == *src)
-        {
-            bytes -= AMD_FLASH_CELL_BYTES;
-            *dst++, *src++;
+		/* Verify Write */
+		if (*dst == *src)
+		{
+			bytes -= AMD_FLASH_CELL_BYTES;
+			*dst++, *src++;
 
-            if ((putchar != NULL))
-            {
-                /* Hash marks to indicate progress */
-                if (hashj == 0x1000)
-                {
-                    hashj = -1;
-                    putchar(hash[0]);
-                    putchar(hash[hashi]);
+			if ((putchar != NULL))
+			{
+				/* Hash marks to indicate progress */
+				if (hashj == 0x1000)
+				{
+					hashj = -1;
+					putchar(hash[0]);
+					putchar(hash[hashi]);
 
-                    hashi++;
-                    if (hashi == 5)
-                    {
-                        hashi=1;
-                    }
+					hashi++;
+					if (hashi == 5)
+					{
+						hashi=1;
+					}
 
-                }
-                hashj++;
-            }
-        }
-        else
-            break;
-    }
+				}
+				hashj++;
+			}
+		}
+		else
+			break;
+	}
 
-    /*
-     * Place device in read mode
-     */
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+	/*
+	 * Place device in read mode
+	 */
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
 
-    if (putchar != NULL)
-    {
-        putchar(hash[0]);
-    }
+	if (putchar != NULL)
+	{
+		putchar(hash[0]);
+	}
 
-    /*
-     * If a function was passed in, call it now
-     */
-    if ((func != NULL))
-    {
-        func();
-    }
+	/*
+	 * If a function was passed in, call it now
+	 */
+	if ((func != NULL))
+	{
+		func();
+	}
 
-    return ((int)src - (int)source);
+	return ((int)src - (int)source);
 }
 
 /*
@@ -635,7 +634,7 @@ void basflash(void)
 						if (strlen(fileinfo.fname) >= 4
 								&& strncmp(
 										&fileinfo.fname[strlen(fileinfo.fname)
-										                - 4], srec_ext, 4) == 0) /* we have a .S19 file */
+														- 4], srec_ext, 4) == 0) /* we have a .S19 file */
 						{
 							/*
 							 * build path + filename

exe/basflash_start.c

@@ -21,7 +21,7 @@
  *      Author: Markus Fröschle
  */
 
-#include <stdint.h>
+#include <bas_types.h>
 
 static uint32_t ownstack[4096];
 static uint32_t *stackptr = &ownstack[4095];

flash/flash.c

@@ -1,4 +1,3 @@
-#include <stdint.h>
 #include <stddef.h>
 #include "bas_types.h"
 
@@ -192,191 +191,191 @@ static const int num_flash_areas = sizeof(flash_areas) / sizeof(struct romram);
  */
 void amd_flash_sector_erase(int n)
 {
-    volatile AMD_FLASH_CELL status;
+	volatile AMD_FLASH_CELL status;
 
-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);
 
-    do
-        status = pFlash[SADDR(n)];
-    while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));
+	do
+		status = pFlash[SADDR(n)];
+	while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));
 
-    /*
-     * Place device in read mode
-     */
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+	/*
+	 * Place device in read mode
+	 */
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
 }
 
 int amd_flash_erase(void *start, int bytes, void (*putchar)(int))
 {
-    int i, ebytes = 0;
+	int i, ebytes = 0;
 
-    if (bytes == 0)
-        return 0;
+	if (bytes == 0)
+		return 0;
 
-    for (i = 0; i < AMD_FLASH_SECTORS; i++)
-    {
-        if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
-            start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
-        {
-            break;
-        }
-    }
+	for (i = 0; i < AMD_FLASH_SECTORS; i++)
+	{
+		if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
+			start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
+		{
+			break;
+		}
+	}
 
-    while (ebytes < bytes)
-    {
-        if (putchar != NULL)
-        {
-            putchar('.');
-        }
-        amd_flash_sector_erase(i);
-        ebytes += SSIZE(i);
-        i++;
-    }
+	while (ebytes < bytes)
+	{
+		if (putchar != NULL)
+		{
+			putchar('.');
+		}
+		amd_flash_sector_erase(i);
+		ebytes += SSIZE(i);
+		i++;
+	}
 
-    if (putchar != NULL)
-    {
-        putchar(10);    /* LF */
-        putchar(13);    /* CR */
-    }
+	if (putchar != NULL)
+	{
+		putchar(10);    /* LF */
+		putchar(13);    /* CR */
+	}
 
-    return ebytes;
+	return ebytes;
 }
 
 void amd_flash_program_cell(AMD_FLASH_CELL *dst, AMD_FLASH_CELL data)
 {
-    volatile AMD_FLASH_CELL status;
-    int retry;
+	volatile AMD_FLASH_CELL status;
+	int retry;
 
-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
-    *dst = data;
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
+	*dst = data;
 
-    /*
-     * Wait for program operation to finish
-     *  (Data# Polling Algorithm)
-     */
-    retry = 0;
-    while (1)
-    {
-        status = *dst;
-        if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
-            (data & AMD_FLASH_CMD_DATA(0x80)))
-        {
-            break;
-        }
-        if (status & AMD_FLASH_CMD_DATA(0x20))
-        {
-            status = *dst;
-            if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
-                (data & AMD_FLASH_CMD_DATA(0x80)))
-            {
-                break;
-            }
-            if (++retry > 1024)
-            {
-                break;
-            }
-        }
-    }
+	/*
+	 * Wait for program operation to finish
+	 *  (Data# Polling Algorithm)
+	 */
+	retry = 0;
+	while (1)
+	{
+		status = *dst;
+		if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
+			(data & AMD_FLASH_CMD_DATA(0x80)))
+		{
+			break;
+		}
+		if (status & AMD_FLASH_CMD_DATA(0x20))
+		{
+			status = *dst;
+			if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
+				(data & AMD_FLASH_CMD_DATA(0x80)))
+			{
+				break;
+			}
+			if (++retry > 1024)
+			{
+				break;
+			}
+		}
+	}
 }
 
 
 int amd_flash_program(void *dest, void *source, int bytes, int erase, void (*func)(void), void (*putchar)(int))
 {
-    AMD_FLASH_CELL *src;
+	AMD_FLASH_CELL *src;
 	AMD_FLASH_CELL *dst;
-    int hashi = 1;
+	int hashi = 1;
 	int hashj = 0;
-    char hash[5];
+	char hash[5];
 
-    hash[0] = 8;  /* Backspace */
-    hash[1] = 124;/* "|" */
-    hash[2] = 47; /* "/" */
-    hash[3] = 45; /* "-" */
-    hash[4] = 92; /* "\" */
+	hash[0] = 8;  /* Backspace */
+	hash[1] = 124;/* "|" */
+	hash[2] = 47; /* "/" */
+	hash[3] = 45; /* "-" */
+	hash[4] = 92; /* "\" */
 
-    src = (AMD_FLASH_CELL *)source;
-    dst = (AMD_FLASH_CELL *)dest;
+	src = (AMD_FLASH_CELL *)source;
+	dst = (AMD_FLASH_CELL *)dest;
 
-    /*
-     * Place device in read mode
-     */
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+	/*
+	 * Place device in read mode
+	 */
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
 
-    /*
-     * Erase device if necessary
-     */
-    if (erase)
-    {
-        amd_flash_erase(dest, bytes, putchar);
-    }
+	/*
+	 * Erase device if necessary
+	 */
+	if (erase)
+	{
+		amd_flash_erase(dest, bytes, putchar);
+	}
 
-    /*
-     * Program device
-     */
-    while (bytes > 0)
-    {
-        amd_flash_program_cell(dst, *src);
+	/*
+	 * Program device
+	 */
+	while (bytes > 0)
+	{
+		amd_flash_program_cell(dst, *src);
 
-        /* Verify Write */
-        if (*dst == *src)
-        {
-            bytes -= AMD_FLASH_CELL_BYTES;
-            *dst++, *src++;
+		/* Verify Write */
+		if (*dst == *src)
+		{
+			bytes -= AMD_FLASH_CELL_BYTES;
+			*dst++, *src++;
 
-            if ((putchar != NULL))
-            {
-                /* Hash marks to indicate progress */
-                if (hashj == 0x1000)
-                {
-                    hashj = -1;
-                    putchar(hash[0]);
-                    putchar(hash[hashi]);
+			if ((putchar != NULL))
+			{
+				/* Hash marks to indicate progress */
+				if (hashj == 0x1000)
+				{
+					hashj = -1;
+					putchar(hash[0]);
+					putchar(hash[hashi]);
 
-                    hashi++;
-                    if (hashi == 5)
-                    {
-                        hashi = 1;
-                    }
+					hashi++;
+					if (hashi == 5)
+					{
+						hashi = 1;
+					}
 
-                }
-                hashj++;
-            }
-        }
-        else
-            break;
-    }
+				}
+				hashj++;
+			}
+		}
+		else
+			break;
+	}
 
-    /*
-     * Place device in read mode
-     */
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
-    pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
+	/*
+	 * Place device in read mode
+	 */
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
+	pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
 
-    if (putchar != NULL)
-    {
-        putchar(hash[0]);
-    }
+	if (putchar != NULL)
+	{
+		putchar(hash[0]);
+	}
 
-    /*
-     * If a function was passed in, call it now
-     */
-    if ((func != NULL))
-    {
-        func();
-    }
+	/*
+	 * If a function was passed in, call it now
+	 */
+	if ((func != NULL))
+	{
+		func();
+	}
 
-    return ((int)src - (int)source);
+	return ((int)src - (int)source);
 }
 

flash/s19reader.c

@@ -23,8 +23,7 @@
  * Copyright 2012        M. Froeschle
  */
 
-#include <stdint.h>
-#include <stdbool.h>
+#include <bas_types.h>
 
 #include "bas_printf.h"
 #include "bas_string.h"
@@ -340,6 +339,17 @@ static err_t verify(uint8_t *dst, uint8_t *src, uint32_t length)
 	return OK;
 }
 
+/*
+ * needed to avoid missing type cast warning below
+ */
+static inline err_t srec_memcpy(uint8_t *dst, uint8_t *src, size_t n)
+{
+	err_t e = OK;
+
+	memcpy((void *) dst, (void *) src, n);
+	return e;
+}
+
 void srec_execute(char *flasher_filename)
 {
 	DRESULT res;
@@ -372,7 +382,7 @@ void srec_execute(char *flasher_filename)
 				{
 					/* next pass: copy data to destination */
 					xprintf("OK.\r\ncopy/flash data: ");
-					err = read_srecords(flasher_filename, &start_address, &length, memcpy);
+					err = read_srecords(flasher_filename, &start_address, &length, srec_memcpy);
 					if (err == OK)
 					{
 						/* next pass: verify data */

flash_scripts/flash_firebee_bas.bdm

@@ -1,71 +1,53 @@
-#!/usr/local/bin/bdmctrl 
+#!/usr/local/bin/bdmctrl -D2
 #
 # firebee board initialization for bdmctrl 
 #
 open $1
 reset
-sleep 10
+sleep 1
 
 wait
 
-# Turn on MBAR at 0xFF00_0000
-write-ctrl 0x0C0F 0xFF000000
-
-# set VBR
-write-ctrl 0x0801 0x00000000
-
-#
-# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
-write 0xFF000500 0xE0000000 4
-write 0xFF000508 0x00001180 4
-write 0xFF000504 0x007F0001 4
-
-# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
-write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
-write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
-write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
-write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
-write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
-write 0xFF000108 0x73622830 4 # SDCFG1
-write 0xFF00010C 0x46770000 4 # SDCFG2
-
-write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
-write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
-write 0xFF000100 0x048D0000 4 # SDMR (write to LMR)
-sleep 100
-write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
-write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
-write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
-write 0xFF000100 0x008D0000 4 # SDMR (write to LMR)
-write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
-sleep 10
-
-
 # use system sdram as flashlib scratch area.
 # TODO: plugin flashing seems to work o.k. now for smaller binaries, while it doesn't for larger ones (EmuTOS) yet.
 # This seems to be related to large flash buffers and PC-relative adressing of the plugin
-flash-plugin 0x1000 0xf000 flash29.plugin
+#flash-plugin 0x1000 0xf000 flash29-5475.plugin
 # notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
-flash 0xE0000000
+flash 0xe0000000
 
 # Erase flash from 0xE0000000 to 0xE00FFFFF (reserved space for BaS)
 #
 # Caution: sector offset numbers need to be the ones from the x16 address range
 # column and they vary in size - needs to be exactly as in the data sheet (p. 9)
 #
-# contrary to documentation, it seems we need to erase-wait after each sector
 
-erase 0xE0000000 0
-erase 0xE0000000 1
-erase 0xE0000000 2
-erase 0xE0000000 3
-erase 0xE0000000 4
-erase 0xE0000000 5
-erase 0xE0000000 7
-erase 0xE0000000 8
-erase 0xE0000000 9
-erase 0xE0000000 10
-erase-wait 0xE0000000
+erase 0xe0000000 0
+erase 0xe0000000 0x1000
+erase 0xe0000000 0x2000
+erase 0xe0000000 0x3000
+erase 0xe0000000 0x4000
+erase 0xe0000000 0x5000
+erase 0xe0000000 0x6000
+erase 0xe0000000 0x7000
+erase 0xe0000000 0x8000
+erase 0xe0000000 0x10000
+erase 0xe0000000 0x18000
+erase 0xe0000000 0x20000
+erase 0xe0000000 0x28000
+erase 0xe0000000 0x30000
+erase 0xe0000000 0x38000
+erase 0xe0000000 0x40000
+erase 0xe0000000 0x48000
+erase 0xe0000000 0x50000
+erase 0xe0000000 0x58000
+erase 0xe0000000 0x60000
+erase 0xe0000000 0x70000
+erase 0xe0000000 0x78000
+
+erase-wait 0xe0000000
+# should now have erased from 0xe0000000 to 0xe00fffff
+
+dump-mem 0xe0010000 0x20 b
 
 load -v ../firebee/bas.elf
 wait

fs/ccsbcs.c

@@ -26,7 +26,7 @@
 */
 
 #include <ff.h>
-#include <stdint.h>
+#include <bas_types.h>
 
 #if _CODE_PAGE == 437
 #define _TBLDEF 1

fs/ff.c

@@ -95,7 +95,7 @@
 /                   Changed option name _FS_SHARE to _FS_LOCK.
 /---------------------------------------------------------------------------*/
 
-#include <stdint.h>
+#include <bas_types.h>
 #include <ff.h>			/* FatFs configurations and declarations */
 #include <diskio.h>		/* Declarations of low level disk I/O functions */
 
@@ -356,11 +356,11 @@ typedef struct {
 uint32_t get_fattime (void)
 {
    return     ((uint32_t)(2012 - 1980) << 25)   /* Year = 2012 */
-         | ((uint32_t)1 << 21)            /* Month = 1 */
-         | ((uint32_t)1 << 16)            /* Day_m = 1*/
-         | ((uint32_t)0 << 11)            /* Hour = 0 */
-         | ((uint32_t)0 << 5)          /* Min = 0 */
-         | ((uint32_t)0 >> 1);            /* Sec = 0 */
+		 | ((uint32_t)1 << 21)            /* Month = 1 */
+		 | ((uint32_t)1 << 16)            /* Day_m = 1*/
+		 | ((uint32_t)0 << 11)            /* Hour = 0 */
+		 | ((uint32_t)0 << 5)          /* Min = 0 */
+		 | ((uint32_t)0 >> 1);            /* Sec = 0 */
 }
 
 /* Character code support macros */
@@ -970,7 +970,7 @@ FRESULT remove_chain (
 #if _USE_ERASE
 			if (ecl + 1 == nxt) {	/* Is next cluster contiguous? */
 				ecl = nxt;
-			} else {				/* End of contiguous clusters */ 
+			} else {				/* End of contiguous clusters */
 				rt[0] = clust2sect(fs, scl);					/* Start sector */
 				rt[1] = clust2sect(fs, ecl) + fs->csize - 1;	/* End sector */
 				disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, rt);		/* Erase the block */
@@ -2190,7 +2190,7 @@ FRESULT chk_mounted (	/* FR_OK(0): successful, !=0: any error occurred */
 
 	/* Get fsinfo if available */
 	if (fmt == FS_FAT32) {
-	 	fs->fsi_flag = 0;
+		fs->fsi_flag = 0;
 		fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo);
 		if (disk_read(fs->drv, fs->win, fs->fsi_sector, 1) == RES_OK &&
 			LD_WORD(fs->win+BS_55AA) == 0xAA55 &&
@@ -2721,7 +2721,7 @@ FRESULT f_close (
 		FATFS *fs = fp->fs;;
 		res = validate(fp);
 		if (res == FR_OK) {
-			res = dec_lock(fp->lockid);	
+			res = dec_lock(fp->lockid);
 			unlock_fs(fs, FR_OK);
 		}
 #else
@@ -2820,7 +2820,7 @@ FRESULT f_getcwd (
 				res = dir_read(&dj);
 				if (res != FR_OK) break;
 				if (ccl == ld_clust(dj.fs, dj.dir)) break;	/* Found the entry */
-				res = dir_next(&dj, 0);	
+				res = dir_next(&dj, 0);
 			} while (res == FR_OK);
 			if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
 			if (res != FR_OK) break;

if/driver_vec.c

@@ -23,18 +23,18 @@
  *      Author: Markus Fröschle
  */
 
-#include <stdint.h>
-#include <stddef.h>
+#include <bas_types.h>
 #include "version.h"
 #include "xhdi_sd.h"
 #include "dma.h"
 #include "driver_vec.h"
 #include "driver_mem.h"
+#include "pci.h"
 
 /*
  * driver interface struct for the SD card BaS driver
  */
-static struct xhdi_driver_interface xhdi_call_interface = 
+static struct xhdi_driver_interface xhdi_call_interface =
 {
 	xhdi_call
 };
@@ -47,27 +47,81 @@ static struct xhdi_driver_interface xhdi_call_interface =
 static struct dma_driver_interface dma_interface =
 {
 	.version = 0x0101,
-	.magic = 'DMAC',
-	.dma_set_initiator = &dma_set_initiator,
+	.magic = 0x444d4143, 						/* 'DMAC' */
+	.dma_set_initiator = dma_set_initiator,
 	.dma_get_initiator = dma_get_initiator,
 	.dma_free_initiator = dma_free_initiator,
 	.dma_set_channel = dma_set_channel,
 	.dma_get_channel = dma_get_channel,
 	.dma_free_channel = dma_free_channel,
 	.dma_clear_channel = dma_clear_channel,
-	.MCD_startDma = MCD_startDma,
-	.MCD_dmaStatus = MCD_dmaStatus,
-	.MCD_XferProgrQuery = MCD_XferProgrQuery,
-	.MCD_killDma = MCD_killDma,
-	.MCD_continDma = MCD_continDma,
-	.MCD_pauseDma = MCD_pauseDma,
-	.MCD_resumeDma = MCD_resumeDma,
-	.MCD_csumQuery = MCD_csumQuery,
+	.MCD_startDma = (int (*)(long, int8_t *, unsigned int, int8_t *, unsigned int,
+					unsigned int, unsigned int, unsigned int, int,
+					unsigned int, unsigned int)) MCD_startDma,
+	.MCD_dmaStatus = (int32_t (*)(int32_t)) MCD_dmaStatus,
+	.MCD_XferProgrQuery = (int32_t (*)(int32_t, MCD_XferProg *)) MCD_XferProgrQuery,
+	.MCD_killDma = (int32_t (*)(int32_t)) MCD_killDma,
+	.MCD_continDma = (int32_t (*)(int32_t)) MCD_continDma,
+	.MCD_pauseDma = (int32_t (*)(int32_t)) MCD_pauseDma,
+	.MCD_resumeDma = (int32_t (*)(int32_t)) MCD_resumeDma,
+	.MCD_csumQuery = (int32_t (*)(int32_t, uint32_t *)) MCD_csumQuery,
 	.dma_malloc = driver_mem_alloc,
 	.dma_free = driver_mem_free
 };
 
-extern const struct fb_info *info_fb;
+extern struct fb_info *info_fb;
+
+/*
+ * driver interface struct for the PCI_BIOS BaS driver
+ */
+static struct pci_bios_interface pci_interface =
+{
+	.subjar = 0,
+	.version = 0x00010000,
+	.find_pci_device = wrapper_find_pci_device,
+	.find_pci_classcode = wrapper_find_pci_classcode,
+	.read_config_byte = wrapper_read_config_byte,
+	.read_config_word = wrapper_read_config_word,
+	.read_config_longword = wrapper_read_config_longword,
+	.fast_read_config_byte = wrapper_fast_read_config_byte,
+	.fast_read_config_word = wrapper_fast_read_config_word,
+	.fast_read_config_longword = wrapper_fast_read_config_longword,
+	.write_config_byte = wrapper_write_config_byte,
+	.write_config_word = wrapper_write_config_word,
+	.write_config_longword = wrapper_write_config_longword,
+	.hook_interrupt = wrapper_hook_interrupt,
+	.unhook_interrupt = wrapper_unhook_interrupt,
+	.special_cycle = wrapper_special_cycle,
+	.get_routing = wrapper_get_routing,
+	.set_interrupt = wrapper_set_interrupt,
+	.get_resource = wrapper_get_resource,
+	.get_card_used = wrapper_get_card_used,
+	.set_card_used = wrapper_set_card_used,
+	.read_mem_byte = wrapper_read_mem_byte,
+	.read_mem_word = wrapper_read_mem_word,
+	.read_mem_longword = wrapper_read_mem_longword,
+	.fast_read_mem_byte = wrapper_fast_read_mem_byte,
+	.fast_read_mem_word = wrapper_fast_read_mem_word,
+	.fast_read_mem_longword = wrapper_fast_read_mem_longword,
+	.write_mem_byte = wrapper_write_mem_byte,
+	.write_mem_word = wrapper_write_mem_word,
+	.write_mem_longword = wrapper_write_mem_longword,
+	.read_io_byte = wrapper_read_io_byte,
+	.read_io_word = wrapper_read_io_word,
+	.read_io_longword = wrapper_read_io_longword,
+	.fast_read_io_byte = wrapper_fast_read_io_byte,
+	.fast_read_io_word = wrapper_fast_read_io_word,
+	.fast_read_io_longword = wrapper_fast_read_io_longword,
+	.write_io_byte = wrapper_write_io_byte,
+	.write_io_word = wrapper_write_io_word,
+	.write_io_longword = wrapper_write_io_longword,
+	.get_machine_id = wrapper_get_machine_id,
+	.get_pagesize = wrapper_get_pagesize,
+	.virt_to_bus = wrapper_virt_to_bus,
+	.bus_to_virt = wrapper_bus_to_virt,
+	.virt_to_phys = wrapper_virt_to_phys,
+	.phys_to_virt = wrapper_phys_to_virt,
+};
 
 /*
  * driver interface struct for the BaS framebuffer video driver
@@ -87,7 +141,7 @@ static struct generic_interface interfaces[] =
 		.description = "BaS SD Card driver",
 		.version = 0,
 		.revision = 1,
-		.interface.xhdi = &xhdi_call_interface 
+		.interface.xhdi = &xhdi_call_interface
 	},
 	{
 		.type = MCD_DRIVER,
@@ -105,7 +159,14 @@ static struct generic_interface interfaces[] =
 		.revision = 1,
 		.interface.fb = &framebuffer_interface,
 	},
-
+	{
+		.type = PCI_DRIVER,
+		.name = "PCI",
+		.description = "BaS PCI_BIOS driver",
+		.version = 0,
+		.revision = 1,
+		.interface.pci = &pci_interface,
+	},
 	/* insert new drivers here */
 
 	{
@@ -121,7 +182,7 @@ static struct driver_table bas_drivers =
 	.bas_version = MAJOR_VERSION,
 	.bas_revision = MINOR_VERSION,
 	.remove_handler = NULL,
-	.interfaces = { interfaces }
+	.interfaces = interfaces
 };
 
 void __attribute__((interrupt)) get_bas_drivers(void)

include/MCF5475.h

@@ -16,7 +16,7 @@
 #ifndef __MCF5475_H__
 #define __MCF5475_H__
 
-#include <stdint.h>
+#include <bas_types.h>
 /***
  * MCF5475 Derivative Memory map definitions from linker command files:
  * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE

include/MCF5475_MMU.h

@@ -62,7 +62,7 @@
 /* Bit definitions and macros for MCF_MMU_MMUTR */
 #define MCF_MMU_MMUTR_V                      (0x1)
 #define MCF_MMU_MMUTR_SG                     (0x2)
-#define MCF_MMU_MMUTR_ID(x)                  (((x)&0xFF)<<0x2)
+#define MCF_MMU_MMUTR_ID(x)                  (((x) & 0xFF) << 0x2)
 #define MCF_MMU_MMUTR_VA(x)                  (((x)&0x3FFFFF)<<0xA)
 
 /* Bit definitions and macros for MCF_MMU_MMUDR */
@@ -71,9 +71,9 @@
 #define MCF_MMU_MMUDR_W                      (0x8)
 #define MCF_MMU_MMUDR_R                      (0x10)
 #define MCF_MMU_MMUDR_SP                     (0x20)
-#define MCF_MMU_MMUDR_CM(x)                  (((x)&0x3)<<0x6)
-#define MCF_MMU_MMUDR_SZ(x)                  (((x)&0x3)<<0x8)
-#define MCF_MMU_MMUDR_PA(x)                  (((x)&0x3FFFFF)<<0xA)
+#define MCF_MMU_MMUDR_CM(x)                  (((x) & 0x3) << 0x6)
+#define MCF_MMU_MMUDR_SZ(x)                  (((x) & 0x3) << 0x8)
+#define MCF_MMU_MMUDR_PA(x)                  (((x) & 0x3FFFFF) << 0xA)
 
 
 #endif /* __MCF5475_MMU_H__ */

include/bas_string.h

@@ -35,6 +35,7 @@ extern char *strncat(char *dst, const char *src, size_t max);
 extern int atoi(const char *c);
 extern void *memcpy(void *dst, const void *src, size_t n);
 extern void *memset(void *s, int c, size_t n);
+extern int memcmp(const void *s1, const void *s2, size_t max);
 extern void bzero(void *s, size_t n);
 
 #define isdigit(c)	(((c) >= '0') && ((c) <= '9'))

include/bas_types.h

@@ -30,5 +30,6 @@
 
 #include <stdint.h>
 #include <stdbool.h>
+#include <stddef.h>		/* for sizeof() etc. */
 
 #endif /* BAS_TYPES_H_ */

include/cache.h

@@ -25,8 +25,7 @@
  *
  */
 
-#include <stdint.h>
-#include <stddef.h>
+#include <bas_types.h>
 
 /*
  * CACR Cache Control Register
@@ -54,11 +53,7 @@
 #define CF_CACR_ICINVA      (0x00000100) /* Instr Cache Invalidate All       */
 #define CF_CACR_IDSP        (0x00000080) /* Ins default supervisor-protect   */
 #define CF_CACR_EUSP        (0x00000020) /* Switch stacks in user mode       */
-
-#define _DCACHE_SET_MASK ((DCACHE_SIZE/64-1)<<CACHE_WAYS)
-#define _ICACHE_SET_MASK ((ICACHE_SIZE/64-1)<<CACHE_WAYS)
-#define LAST_DCACHE_ADDR _DCACHE_SET_MASK
-#define LAST_ICACHE_ADDR _ICACHE_SET_MASK
+#define CF_CACR_DF          (0x00000010) /* Disable FPU                      */
 
 #define ICACHE_SIZE 0x8000              /* instruction - 32k */
 #define DCACHE_SIZE 0x8000              /* data - 32k */
@@ -67,6 +62,10 @@
 #define CACHE_SETS 0x0200               /* 512 sets */
 #define CACHE_WAYS 0x0004               /* 4 way */
 
+#define _DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS)
+#define _ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS)
+#define LAST_DCACHE_ADDR _DCACHE_SET_MASK
+#define LAST_ICACHE_ADDR _ICACHE_SET_MASK
 
 #define CACHE_DISABLE_MODE      (CF_CACR_DCINVA+        \
 									CF_CACR_BCINVA+        \
@@ -83,7 +82,7 @@ extern uint32_t cacr_get(void);
 extern void cacr_set(uint32_t);
 extern void flush_icache_range(void *address, size_t size);
 extern void flush_dcache_range(void *address, size_t size);
-
+extern void flush_cache_range(void *address, size_t size);
 
 
 #endif /* _CACHE_H_ */

include/diskio.h

@@ -12,7 +12,7 @@ extern "C" {
 #define _USE_WRITE	1	/* 1: Enable disk_write function */
 #define _USE_IOCTL	1	/* 1: Enable disk_ioctl fucntion */
 
-#include <stdint.h>
+#include <bas_types.h>
 
 
 /* Status of Disk Functions */

include/dma.h

@@ -26,8 +26,8 @@
 #include "MCD_dma.h"
 #include "bas_string.h"
 
-#define DMA_INTC_LVL        6
-#define DMA_INTC_PRI        0
+#define DMA_INTC_LVL        5
+#define DMA_INTC_PRI        3
 
 
 void *dma_memcpy(void *dst, void *src, size_t n);

include/driver_vec.h

@@ -27,15 +27,17 @@
 
 #include "xhdi_sd.h"
 #include "MCD_dma.h"
+#include "pci.h"
 
 enum driver_type
 {
-	END_OF_DRIVERS,		/* marks end of driver list */
 	BLOCKDEV_DRIVER,
 	CHARDEV_DRIVER,
-	VIDEO_DRIVER,
 	XHDI_DRIVER,
 	MCD_DRIVER,
+	VIDEO_DRIVER,
+	PCI_DRIVER,
+	END_OF_DRIVERS,		/* marks end of driver list */
 };
 
 struct generic_driver_interface
@@ -50,17 +52,17 @@ struct dma_driver_interface
 {
 	int32_t version;
 	int32_t magic;
-	int32_t (*dma_set_initiator)(int32_t initiator);
-	uint32_t (*dma_get_initiator)(int32_t requestor);
-	void (*dma_free_initiator)(int32_t requestor);
-	int32_t (*dma_set_channel)(int32_t requestor, void (*handler)(void));
-	int32_t (*dma_get_channel)(int32_t requestor);
-	void (*dma_free_channel)(int32_t requestor);
-	void (*dma_clear_channel)(int32_t channel);
-	int32_t (*MCD_startDma)(long channel,
-						int8_t *srcAddr, uint32_t srcIncr, int8_t *destAddr, uint32_t destIncr,
-						uint32_t dmaSize, uint32_t xferSize, uint32_t initiator, int32_t priority,
-						uint32_t flags, uint32_t funcDesc);
+	int (*dma_set_initiator)(int initiator);
+	uint32_t (*dma_get_initiator)(int requestor);
+	void (*dma_free_initiator)(int requestor);
+	int (*dma_set_channel)(int requestor, void (*handler)(void));
+	int (*dma_get_channel)(int requestor);
+	void (*dma_free_channel)(int requestor);
+	void (*dma_clear_channel)(int channel);
+	int (*MCD_startDma)(long channel,
+						int8_t *srcAddr, unsigned int srcIncr, int8_t *destAddr, unsigned int destIncr,
+						unsigned int dmaSize, unsigned int xferSize, unsigned int initiator, int priority,
+						unsigned int flags, unsigned int funcDesc);
 	int32_t (*MCD_dmaStatus)(int32_t channel);
 	int32_t (*MCD_XferProgrQuery)(int32_t channel, MCD_XferProg *progRep);
 	int32_t (*MCD_killDma)(int32_t channel);
@@ -71,7 +73,7 @@ struct dma_driver_interface
 	void *(*dma_malloc)(uint32_t amount);
 	int32_t (*dma_free)(void *addr);
 };
-	
+
 struct xhdi_driver_interface
 {
 	uint32_t (*xhdivec)();
@@ -85,10 +87,10 @@ struct xhdi_driver_interface
  */
 struct fb_bitfield
 {
-    unsigned long offset;           /* beginning of bitfield    */
-    unsigned long length;           /* length of bitfield       */
-    unsigned long msb_right;        /* != 0 : Most significant bit is */
-				                    /* right */
+	unsigned long offset;           /* beginning of bitfield    */
+	unsigned long length;           /* length of bitfield       */
+	unsigned long msb_right;        /* != 0 : Most significant bit is */
+									/* right */
 };
 
 /*
@@ -96,107 +98,107 @@ struct fb_bitfield
  */
 struct fb_var_screeninfo
 {
-    unsigned long xres;             /* visible resolution       */
-    unsigned long yres;
-    unsigned long xres_virtual;     /* virtual resolution       */
-    unsigned long yres_virtual;
-    unsigned long xoffset;          /* offset from virtual to visible */
-    unsigned long yoffset;          /* resolution           */
+	unsigned long xres;             /* visible resolution       */
+	unsigned long yres;
+	unsigned long xres_virtual;     /* virtual resolution       */
+	unsigned long yres_virtual;
+	unsigned long xoffset;          /* offset from virtual to visible */
+	unsigned long yoffset;          /* resolution           */
 
-    unsigned long bits_per_pixel;   /* guess what           */
-    unsigned long grayscale;        /* != 0 Graylevels instead of colors */
+	unsigned long bits_per_pixel;   /* guess what           */
+	unsigned long grayscale;        /* != 0 Graylevels instead of colors */
 
-    struct fb_bitfield red;         /* bitfield in fb mem if true color, */
-    struct fb_bitfield green;       /* else only length is significant */
-    struct fb_bitfield blue;
-    struct fb_bitfield transp;      /* transparency         */
+	struct fb_bitfield red;         /* bitfield in fb mem if true color, */
+	struct fb_bitfield green;       /* else only length is significant */
+	struct fb_bitfield blue;
+	struct fb_bitfield transp;      /* transparency         */
 
-    unsigned long nonstd;           /* != 0 Non standard pixel format */
+	unsigned long nonstd;           /* != 0 Non standard pixel format */
 
-    unsigned long activate;         /* see FB_ACTIVATE_*        */
+	unsigned long activate;         /* see FB_ACTIVATE_*        */
 
-    unsigned long height;           /* height of picture in mm    */
-    unsigned long width;            /* width of picture in mm     */
+	unsigned long height;           /* height of picture in mm    */
+	unsigned long width;            /* width of picture in mm     */
 
-    unsigned long accel_flags;      /* (OBSOLETE) see fb_info.flags */
+	unsigned long accel_flags;      /* (OBSOLETE) see fb_info.flags */
 
-    /* Timing: All values in pixclocks, except pixclock (of course) */
-    unsigned long pixclock;         /* pixel clock in ps (pico seconds) */
-    unsigned long left_margin;      /* time from sync to picture    */
-    unsigned long right_margin;     /* time from picture to sync    */
-    unsigned long upper_margin;     /* time from sync to picture    */
-    unsigned long lower_margin;
-    unsigned long hsync_len;        /* length of horizontal sync    */
-    unsigned long vsync_len;        /* length of vertical sync  */
-    unsigned long sync;             /* see FB_SYNC_*        */
-    unsigned long vmode;            /* see FB_VMODE_*       */
-    unsigned long rotate;           /* angle we rotate counter clockwise */
-    unsigned long refresh;
-    unsigned long reserved[4];      /* Reserved for future compatibility */
+	/* Timing: All values in pixclocks, except pixclock (of course) */
+	unsigned long pixclock;         /* pixel clock in ps (pico seconds) */
+	unsigned long left_margin;      /* time from sync to picture    */
+	unsigned long right_margin;     /* time from picture to sync    */
+	unsigned long upper_margin;     /* time from sync to picture    */
+	unsigned long lower_margin;
+	unsigned long hsync_len;        /* length of horizontal sync    */
+	unsigned long vsync_len;        /* length of vertical sync  */
+	unsigned long sync;             /* see FB_SYNC_*        */
+	unsigned long vmode;            /* see FB_VMODE_*       */
+	unsigned long rotate;           /* angle we rotate counter clockwise */
+	unsigned long refresh;
+	unsigned long reserved[4];      /* Reserved for future compatibility */
 };
 
 struct fb_fix_screeninfo
 {
-    char id[16];                    /* identification string eg "TT Builtin" */
-    unsigned long smem_start;       /* Start of frame buffer mem */
-                                    /* (physical address) */
-    unsigned long smem_len;         /* Length of frame buffer mem */
-    unsigned long type;             /* see FB_TYPE_*        */
-    unsigned long type_aux;         /* Interleave for interleaved Planes */
-    unsigned long visual;           /* see FB_VISUAL_*      */
-    unsigned short xpanstep;        /* zero if no hardware panning  */
-    unsigned short ypanstep;        /* zero if no hardware panning  */
-    unsigned short ywrapstep;       /* zero if no hardware ywrap    */
-    unsigned long line_length;      /* length of a line in bytes    */
-    unsigned long mmio_start;       /* Start of Memory Mapped I/O   */
-                                    /* (physical address) */
-    unsigned long mmio_len;         /* Length of Memory Mapped I/O  */
-    unsigned long accel;            /* Indicate to driver which */
-                                    /*  specific chip/card we have  */
-    unsigned short reserved[3];     /* Reserved for future compatibility */
+	char id[16];                    /* identification string eg "TT Builtin" */
+	unsigned long smem_start;       /* Start of frame buffer mem */
+									/* (physical address) */
+	unsigned long smem_len;         /* Length of frame buffer mem */
+	unsigned long type;             /* see FB_TYPE_*        */
+	unsigned long type_aux;         /* Interleave for interleaved Planes */
+	unsigned long visual;           /* see FB_VISUAL_*      */
+	unsigned short xpanstep;        /* zero if no hardware panning  */
+	unsigned short ypanstep;        /* zero if no hardware panning  */
+	unsigned short ywrapstep;       /* zero if no hardware ywrap    */
+	unsigned long line_length;      /* length of a line in bytes    */
+	unsigned long mmio_start;       /* Start of Memory Mapped I/O   */
+									/* (physical address) */
+	unsigned long mmio_len;         /* Length of Memory Mapped I/O  */
+	unsigned long accel;            /* Indicate to driver which */
+									/*  specific chip/card we have  */
+	unsigned short reserved[3];     /* Reserved for future compatibility */
 };
 
 struct fb_chroma
 {
-    unsigned long redx; /* in fraction of 1024 */
-    unsigned long greenx;
-    unsigned long bluex;
-    unsigned long whitex;
-    unsigned long redy;
-    unsigned long greeny;
-    unsigned long bluey;
-    unsigned long whitey;
+	unsigned long redx; /* in fraction of 1024 */
+	unsigned long greenx;
+	unsigned long bluex;
+	unsigned long whitex;
+	unsigned long redy;
+	unsigned long greeny;
+	unsigned long bluey;
+	unsigned long whitey;
 };
 
 struct fb_monspecs
 {
-    struct fb_chroma chroma;
-    struct fb_videomode *modedb;    /* mode database */
-    unsigned char  manufacturer[4]; /* Manufacturer */
-    unsigned char  monitor[14];     /* Monitor String */
-    unsigned char  serial_no[14];   /* Serial Number */
-    unsigned char  ascii[14];       /* ? */
-    unsigned long modedb_len;       /* mode database length */
-    unsigned long model;            /* Monitor Model */
-    unsigned long serial;           /* Serial Number - Integer */
-    unsigned long year;             /* Year manufactured */
-    unsigned long week;             /* Week Manufactured */
-    unsigned long hfmin;            /* hfreq lower limit (Hz) */
-    unsigned long hfmax;            /* hfreq upper limit (Hz) */
-    unsigned long dclkmin;          /* pixelclock lower limit (Hz) */
-    unsigned long dclkmax;          /* pixelclock upper limit (Hz) */
-    unsigned short input;           /* display type - see FB_DISP_* */
-    unsigned short dpms;            /* DPMS support - see FB_DPMS_ */
-    unsigned short signal;          /* Signal Type - see FB_SIGNAL_* */
-    unsigned short vfmin;           /* vfreq lower limit (Hz) */
-    unsigned short vfmax;           /* vfreq upper limit (Hz) */
-    unsigned short gamma;           /* Gamma - in fractions of 100 */
-    unsigned short gtf  : 1;        /* supports GTF */
-    unsigned short misc;            /* Misc flags - see FB_MISC_* */
-    unsigned char  version;         /* EDID version... */
-    unsigned char  revision;        /* ...and revision */
-    unsigned char  max_x;           /* Maximum horizontal size (cm) */
-    unsigned char  max_y;           /* Maximum vertical size (cm) */
+	struct fb_chroma chroma;
+	struct fb_videomode *modedb;    /* mode database */
+	unsigned char  manufacturer[4]; /* Manufacturer */
+	unsigned char  monitor[14];     /* Monitor String */
+	unsigned char  serial_no[14];   /* Serial Number */
+	unsigned char  ascii[14];       /* ? */
+	unsigned long modedb_len;       /* mode database length */
+	unsigned long model;            /* Monitor Model */
+	unsigned long serial;           /* Serial Number - Integer */
+	unsigned long year;             /* Year manufactured */
+	unsigned long week;             /* Week Manufactured */
+	unsigned long hfmin;            /* hfreq lower limit (Hz) */
+	unsigned long hfmax;            /* hfreq upper limit (Hz) */
+	unsigned long dclkmin;          /* pixelclock lower limit (Hz) */
+	unsigned long dclkmax;          /* pixelclock upper limit (Hz) */
+	unsigned short input;           /* display type - see FB_DISP_* */
+	unsigned short dpms;            /* DPMS support - see FB_DPMS_ */
+	unsigned short signal;          /* Signal Type - see FB_SIGNAL_* */
+	unsigned short vfmin;           /* vfreq lower limit (Hz) */
+	unsigned short vfmax;           /* vfreq upper limit (Hz) */
+	unsigned short gamma;           /* Gamma - in fractions of 100 */
+	unsigned short gtf  : 1;        /* supports GTF */
+	unsigned short misc;            /* Misc flags - see FB_MISC_* */
+	unsigned char  version;         /* EDID version... */
+	unsigned char  revision;        /* ...and revision */
+	unsigned char  max_x;           /* Maximum horizontal size (cm) */
+	unsigned char  max_y;           /* Maximum vertical size (cm) */
 };
 
 struct framebuffer_driver_interface
@@ -204,12 +206,66 @@ struct framebuffer_driver_interface
 	struct fb_info **framebuffer_info;	/* pointer to an fb_info struct (defined in include/fb.h) */
 };
 
+struct pci_bios_interface {
+	uint32_t subjar;
+	uint32_t version;
+	/* Although we declare this functions as standard gcc functions (cdecl),
+	 * they expect paramenters inside registers (fastcall) unsupported by gcc m68k.
+	 * Caller will take care of parameters passing convention.
+	 */
+	int32_t (*find_pci_device)	(uint32_t id, uint16_t index);
+	int32_t (*find_pci_classcode)	(uint32_t class, uint16_t index);
+	int32_t (*read_config_byte)	(int32_t handle, uint16_t reg, uint8_t *address);
+	int32_t (*read_config_word)	(int32_t handle, uint16_t reg, uint16_t *address);
+	int32_t (*read_config_longword)	(int32_t handle, uint16_t reg, uint32_t *address);
+	uint8_t (*fast_read_config_byte)	(int32_t handle, uint16_t reg);
+	uint16_t (*fast_read_config_word)	(int32_t handle, uint16_t reg);
+	uint32_t (*fast_read_config_longword)	(int32_t handle, uint16_t reg);
+	int32_t (*write_config_byte)	(int32_t handle, uint16_t reg, uint16_t val);
+	int32_t (*write_config_word)	(int32_t handle, uint16_t reg, uint16_t val);
+	int32_t (*write_config_longword)	(int32_t handle, uint16_t reg, uint32_t val);
+	int32_t (*hook_interrupt)	(int32_t handle, uint32_t *routine, uint32_t *parameter);
+	int32_t (*unhook_interrupt)	(int32_t handle);
+	int32_t (*special_cycle)	(uint16_t bus, uint32_t data);
+	int32_t (*get_routing)	(int32_t handle);
+	int32_t (*set_interrupt)	(int32_t handle);
+	int32_t (*get_resource)	(int32_t handle);
+	int32_t (*get_card_used)	(int32_t handle, uint32_t *address);
+	int32_t (*set_card_used)	(int32_t handle, uint32_t *callback);
+	int32_t (*read_mem_byte)	(int32_t handle, uint32_t offset, uint8_t *address);
+	int32_t (*read_mem_word)	(int32_t handle, uint32_t offset, uint16_t *address);
+	int32_t (*read_mem_longword)	(int32_t handle, uint32_t offset, uint32_t *address);
+	uint8_t (*fast_read_mem_byte)	(int32_t handle, uint32_t offset);
+	uint16_t (*fast_read_mem_word)	(int32_t handle, uint32_t offset);
+	uint32_t (*fast_read_mem_longword)	(int32_t handle, uint32_t offset);
+	int32_t (*write_mem_byte)	(int32_t handle, uint32_t offset, uint16_t val);
+	int32_t (*write_mem_word)	(int32_t handle, uint32_t offset, uint16_t val);
+	int32_t (*write_mem_longword)	(int32_t handle, uint32_t offset, uint32_t val);
+	int32_t (*read_io_byte)	(int32_t handle, uint32_t offset, uint8_t *address);
+	int32_t (*read_io_word)	(int32_t handle, uint32_t offset, uint16_t *address);
+	int32_t (*read_io_longword)	(int32_t handle, uint32_t offset, uint32_t *address);
+	uint8_t (*fast_read_io_byte)	(int32_t handle, uint32_t offset);
+	uint16_t (*fast_read_io_word)	(int32_t handle, uint32_t offset);
+	uint32_t (*fast_read_io_longword)	(int32_t handle, uint32_t offset);
+	int32_t (*write_io_byte)	(int32_t handle, uint32_t offset, uint16_t val);
+	int32_t (*write_io_word)	(int32_t handle, uint32_t offset, uint16_t val);
+	int32_t (*write_io_longword)	(int32_t handle, uint32_t offset, uint32_t val);
+	int32_t (*get_machine_id)	(void);
+	int32_t (*get_pagesize)	(void);
+	int32_t (*virt_to_bus)	(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+	int32_t (*bus_to_virt)	(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+	int32_t (*virt_to_phys)	(uint32_t address, PCI_CONV_ADR *pointer);
+	int32_t (*phys_to_virt)	(uint32_t address, PCI_CONV_ADR *pointer);
+//	int32_t reserved[2];
+};
+
 union interface
 {
 	struct generic_driver_interface *gdi;
 	struct xhdi_driver_interface *xhdi;
 	struct dma_driver_interface *dma;
 	struct framebuffer_driver_interface *fb;
+	struct pci_bios_interface *pci;
 };
 
 struct generic_interface
@@ -227,7 +283,7 @@ struct driver_table
 	uint32_t bas_version;
 	uint32_t bas_revision;
 	uint32_t (*remove_handler)();			/* calling this will disable the BaS' hook into trap #0 */
-	struct generic_interface *interfaces[];
+	struct generic_interface *interfaces;
 };
 
 

include/ehci.h

@@ -51,7 +51,7 @@ struct ehci_hccr {
 #define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
 #define HC_VERSION(p)		(((p) >> 16) & 0xffff)
 	uint32_t cr_hcsparams;
-#define HCS_PPC(p)		((p) & (1 << 4))
+#define HCS_PPC(p)			((p) & (1 << 4))
 #define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
 #define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
 	uint32_t cr_hccparams;
@@ -70,20 +70,20 @@ struct ehci_hcor {
 #define CMD_RUN		(1 << 0)		/* start/stop HC */
 	uint32_t or_usbsts;
 #define	STD_ASS		(1 << 15)
-#define STS_PSSTAT (1 << 14)
-#define STS_RECL  ( 1 << 13)
+#define STS_PSSTAT	(1 << 14)
+#define STS_RECL	(1 << 13)
 #define STS_HALT	(1 << 12)
-#define STS_IAA (1 << 5)
-#define STS_HSE (1 << 4)
-#define STS_FLR (1 << 3)
-#define STS_PCD (1 << 2)
+#define STS_IAA		(1 << 5)
+#define STS_HSE		(1 << 4)
+#define STS_FLR		(1 << 3)
+#define STS_PCD		(1 << 2)
 #define STS_USBERRINT (1 << 1)
-#define STS_USBINT (1 << 0)
+#define STS_USBINT	(1 << 0)
 	uint32_t or_usbintr;
-#define INTR_IAAE (1 << 5)
-#define INTR_HSEE (1 << 4)
-#define INTR_FLRE (1 << 3)
-#define INTR_PCDE (1 << 2)
+#define INTR_IAAE	(1 << 5)
+#define INTR_HSEE	(1 << 4)
+#define INTR_FLRE	(1 << 3)
+#define INTR_PCDE	(1 << 2)
 #define INTR_USBERRINTE (1 << 1)
 #define INTR_USBINTE (1 << 0)
 	uint32_t or_frindex;
@@ -97,14 +97,15 @@ struct ehci_hcor {
 	uint32_t or_systune;
 } __attribute__ ((packed));
 
-#define USBMODE		0x68		/* USB Device mode */
+#define USBMODE		0x68			/* USB Device mode */
 #define USBMODE_SDIS	(1 << 3)	/* Stream disable */
-#define USBMODE_BE	(1 << 2)	/* BE/LE endiannes select */
+#define USBMODE_BE	(1 << 2)		/* BE/LE endiannes select */
 #define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
 #define USBMODE_CM_IDLE	(0 << 0)	/* idle state */
 
 /* Interface descriptor */
-struct usb_linux_interface_descriptor {
+struct usb_linux_interface_descriptor
+{
 	unsigned char	bLength;
 	unsigned char	bDescriptorType;
 	unsigned char	bInterfaceNumber;
@@ -117,7 +118,8 @@ struct usb_linux_interface_descriptor {
 } __attribute__ ((packed));
 
 /* Configuration descriptor information.. */
-struct usb_linux_config_descriptor {
+struct usb_linux_config_descriptor
+{
 	unsigned char	bLength;
 	unsigned char	bDescriptorType;
 	unsigned short	wTotalLength;
@@ -129,11 +131,11 @@ struct usb_linux_config_descriptor {
 } __attribute__ ((packed));
 
 #if defined CONFIG_EHCI_DESC_BIG_ENDIAN
-#define	ehci_readl(x)		(*((volatile u32 *)(x)))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = ((volatile u32)b))
+#define	ehci_readl(x)		(*((volatile uint32_t *)(x)))
+#define ehci_writel(a, b)	(*((volatile uint32_t *)(a)) = ((volatile uint32_t) b))
 #else
-#define ehci_readl(x)		swpl((*((volatile u32 *)(x))))
-#define ehci_writel(a, b)	(*((volatile u32 *)(a)) = swpl(((volatile u32)b)))
+#define ehci_readl(x)		swpl((*((volatile uint32_t *)(x))))
+#define ehci_writel(a, b)	(*((volatile uint32_t *)(a)) = swpl(((volatile uint32_t) b)))
 #endif
 
 #if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
@@ -147,18 +149,18 @@ struct usb_linux_config_descriptor {
 #define EHCI_PS_WKOC_E		(1 << 22)	/* RW wake on over current */
 #define EHCI_PS_WKDSCNNT_E	(1 << 21)	/* RW wake on disconnect */
 #define EHCI_PS_WKCNNT_E	(1 << 20)	/* RW wake on connect */
-#define EHCI_PS_PO		(1 << 13)	/* RW port owner */
-#define EHCI_PS_PP		(1 << 12)	/* RW,RO port power */
-#define EHCI_PS_LS		(3 << 10)	/* RO line status */
-#define EHCI_PS_PR		(1 << 8)	/* RW port reset */
-#define EHCI_PS_SUSP	(1 << 7)	/* RW suspend */
-#define EHCI_PS_FPR		(1 << 6)	/* RW force port resume */
-#define EHCI_PS_OCC		(1 << 5)	/* RWC over current change */
-#define EHCI_PS_OCA		(1 << 4)	/* RO over current active */
-#define EHCI_PS_PEC		(1 << 3)	/* RWC port enable change */
-#define EHCI_PS_PE		(1 << 2)	/* RW port enable */
-#define EHCI_PS_CSC		(1 << 1)	/* RWC connect status change */
-#define EHCI_PS_CS		(1 << 0)	/* RO connect status */
+#define EHCI_PS_PO			(1 << 13)	/* RW port owner */
+#define EHCI_PS_PP			(1 << 12)	/* RW,RO port power */
+#define EHCI_PS_LS			(3 << 10)	/* RO line status */
+#define EHCI_PS_PR			(1 << 8)	/* RW port reset */
+#define EHCI_PS_SUSP		(1 << 7)	/* RW suspend */
+#define EHCI_PS_FPR			(1 << 6)	/* RW force port resume */
+#define EHCI_PS_OCC			(1 << 5)	/* RWC over current change */
+#define EHCI_PS_OCA			(1 << 4)	/* RO over current active */
+#define EHCI_PS_PEC			(1 << 3)	/* RWC port enable change */
+#define EHCI_PS_PE			(1 << 2)	/* RW port enable */
+#define EHCI_PS_CSC			(1 << 1)	/* RWC connect status change */
+#define EHCI_PS_CS			(1 << 0)	/* RO connect status */
 #define EHCI_PS_CLEAR		(EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
 
 #define EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == (1 << 10))
@@ -174,7 +176,8 @@ struct usb_linux_config_descriptor {
  */
 
 /* Queue Element Transfer Descriptor (qTD). */
-struct qTD {
+struct qTD
+{
 	uint32_t qt_next;
 #define	QT_NEXT_TERMINATE	1
 	uint32_t qt_altnext;
@@ -183,7 +186,8 @@ struct qTD {
 };
 
 /* Queue Head (QH). */
-struct QH {
+struct QH
+{
 	uint32_t qh_link;
 #define	QH_LINK_TERMINATE	1
 #define	QH_LINK_TYPE_ITD	0

include/exceptions.h

@@ -1,7 +1,7 @@
 #ifndef _EXCEPTIONS_H_
 #define _EXCEPTIONS_H_
 
-#include <stdint.h>
+#include <bas_types.h>
 
 static inline uint32_t set_ipl(uint32_t ipl)
 {
@@ -19,7 +19,7 @@ static inline uint32_t set_ipl(uint32_t ipl)
 		"		lsr.l	#8,%[ret]\r\n"			/* shift them to position */
 		: [ret] "=&d" (ret)		/* output */
 		: [ipl] "d" (ipl)		/* input */
-		: "d0"	/* clobber */
+		: "cc", "d0"	/* clobber */
 	);
 
 	return ret;

include/fb.h

@@ -528,7 +528,6 @@ struct fb_videomode {
 extern const struct fb_videomode vesa_modes[];
 
 /* timer */
-extern void udelay(long usec);
 #ifdef COLDFIRE
 #ifdef MCF5445X
 #define US_TO_TIMER(a) (a)
@@ -541,6 +540,7 @@ extern void udelay(long usec);
 #define US_TO_TIMER(a) (((a)*256)/5000)
 #define TIMER_TO_US(a) (((a)*5000)/256)
 #endif
+
 extern void start_timeout(void);
 extern int end_timeout(long msec);
 extern void mdelay(long msec);

include/ff.h

@@ -21,7 +21,7 @@
 extern "C" {
 #endif
 
-#include <stdint.h>
+#include <bas_types.h>
 #include <ffconf.h>		/* FatFs configuration options */
 
 #if _FATFS != _FFCONF

include/firebee.h

@@ -27,7 +27,7 @@
  *      Author: Markus Fröschle
  */
 
-#define SYSCLK			132000
+#define SYSCLK			132000		/* NOTE: 132 _is_ correct. 133 _is_ wrong. Do not change! */
 
 #define BOOTFLASH_BASE_ADDRESS		0xE0000000
 #define BOOTFLASH_SIZE				0x800000		/* FireBee has 8 MByte Flash */

include/font.h

@@ -0,0 +1,98 @@
+/*
+ * font.h - font specific definitions
+ *
+ * Copyright (c) 2001 Lineo, Inc.
+ * Copyright (c) 2004 by Authors:
+ *
+ * Authors:
+ *  MAD     Martin Doering
+ *
+ * This file is distributed under the GPL, version 2 or at your
+ * option any later version.  See doc/license.txt for details.
+ */
+
+#ifndef FONT_H
+#define FONT_H
+
+#include <stdint.h>
+
+/* font header flags */
+
+#define F_DEFAULT 1     /* this is the default font (face and size) */
+#define F_HORZ_OFF  2   /* there are left and right offset tables */
+#define F_STDFORM  4    /* is the font in standard format */
+#define F_MONOSPACE 8   /* is the font monospaced */
+
+/* font style bits */
+
+#define F_THICKEN 1
+#define F_LIGHT 2
+#define F_SKEW  4
+#define F_UNDER 8
+#define F_OUTLINE 16
+#define F_SHADOW        32
+
+/* font specific linea variables */
+
+extern const uint16_t *v_fnt_ad;   /* address of current monospace font */
+extern const uint16_t *v_off_ad;   /* address of font offset table */
+extern uint16_t v_fnt_nd;          /* ascii code of last cell in font */
+extern uint16_t v_fnt_st;          /* ascii code of first cell in font */
+extern uint16_t v_fnt_wr;          /* font cell wrap */
+
+/* character cell specific linea variables */
+
+extern uint16_t    v_cel_ht;       /* cell height (width is 8) */
+extern uint16_t    v_cel_mx;       /* needed by MiNT: columns on the screen minus 1 */
+extern uint16_t    v_cel_my;       /* needed by MiNT: rows on the screen minus 1 */
+extern uint16_t    v_cel_wr;       /* needed by MiNT: length (in int8_ts) of a line of characters */
+
+/*
+ * font_ring is a struct of four pointers, each of which points to
+ * a list of font headers linked together to form a string.
+ */
+
+extern struct font_head *font_ring[4];  /* Ring of available fonts */
+extern int16_t font_count;                 /* all three fonts and NULL */
+
+/* the font header descibes a font */
+
+struct font_head {
+    int16_t font_id;
+    int16_t point;
+    int8_t name[32];
+    uint16_t first_ade;
+    uint16_t last_ade;
+    uint16_t top;
+    uint16_t ascent;
+    uint16_t half;
+    uint16_t descent;
+    uint16_t bottom;
+    uint16_t max_char_width;
+    uint16_t max_cell_width;
+    uint16_t left_offset;          /* amount character slants left when skewed */
+    uint16_t right_offset;         /* amount character slants right */
+    uint16_t thicken;              /* number of pixels to smear */
+    uint16_t ul_size;              /* size of the underline */
+    uint16_t lighten;              /* mask to and with to lighten  */
+    uint16_t skew;                 /* mask for skewing */
+    uint16_t flags;
+
+    const uint8_t *hor_table;     /* horizontal offsets */
+    const uint16_t *off_table;     /* character offsets  */
+    const uint16_t *dat_table;     /* character definitions */
+    uint16_t form_width;
+    uint16_t form_height;
+
+    struct font_head *next_font;/* pointer to next font */
+    uint16_t font_seg;
+};
+
+
+
+/* prototypes */
+
+void font_init(void);           /* initialize BIOS font ring */
+void font_set_default(void);    /* choose the default font */
+
+#endif /* FONT_H */

include/interrupts.h

@@ -80,19 +80,19 @@
 
 
 #define FEC0_INTC_LVL	5			/* interrupt level for FEC0 */
-#define FEC0_INTC_PRI	7			/* interrupt priority for FEC0 */
+#define FEC0_INTC_PRI	1			/* interrupt priority for FEC0 */
 
 #define FEC1_INTC_LVL	5			/* interrupt level for FEC1 */
-#define FEC1_INTC_PRI	7			/* interrupt priority for FEC1 */
+#define FEC1_INTC_PRI	0			/* interrupt priority for FEC1 */
 
 #define FEC_INTC_LVL(x)		((x == 0) ? FEC0_INTC_LVL : FEC1_INTC_LVL)
 #define FEC_INTC_PRI(x)		((x == 0) ? FEC0_INTC_PRI : FEC1_INTC_PRI)
 
 #define FEC0RX_DMA_PRI      5
-#define FEC1RX_DMA_PRI      5
+#define FEC1RX_DMA_PRI      3
 #define FECRX_DMA_PRI(x)    ((x == 0) ? FEC0RX_DMA_PRI : FEC1RX_DMA_PRI)
 #define FEC0TX_DMA_PRI      6
-#define FEC1TX_DMA_PRI      6
+#define FEC1TX_DMA_PRI      4
 #define FECTX_DMA_PRI(x)    ((x == 0) ? FEC0TX_DMA_PRI : FEC1TX_DMA_PRI)
 
 extern int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority, uint8_t intr, void (*handler)(void));
@@ -101,7 +101,8 @@ extern int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t pri
 #define ISR_USER_ISR 	0x02
 
 extern void isr_init(void);
-extern int isr_register_handler(int type, int vector, int (*handler)(void *, void *), void *hdev, void *harg);
-extern void isr_remove_handler(int type ,int (*handler)(void *, void *));
+extern int isr_register_handler(int vector, int (*handler)(void *, void *), void *hdev, void *harg);
+extern void isr_remove_handler(int (*handler)(void *, void *));
 extern bool isr_execute_handler(int vector);
+extern int pic_interrupt_handler(void *arg1, void *arg2);
 #endif /* _INTERRUPTS_H_ */

include/ip.h

@@ -9,7 +9,6 @@
 #ifndef _IP_H
 #define _IP_H
 
-/********************************************************************/
 
 /* 32-bit IP Addresses */
 typedef uint8_t IP_ADDR[4];
@@ -57,7 +56,6 @@ typedef struct
 #define IP_HDR_OFFSET   ETH_HDR_LEN
 #define IP_HDR_SIZE     20  /* no options */
 
-/********************************************************************/
 
 typedef struct
 {
@@ -71,7 +69,6 @@ typedef struct
 	unsigned int    err;
 } IP_INFO;
 
-/********************************************************************/
 
 extern void ip_handler(NIF *nif, NBUF *nbf);
 uint16_t ip_chksum(uint16_t *data, int num);

include/m54455.h

@@ -0,0 +1,49 @@
+#ifndef _M54455_H_
+#define _M54455_H_
+
+/*
+ * m54455.h
+ *
+ * preprocessor definitions for the M54455 Freescale machine. This file should contain nothing but preprocessor
+ * definition that evaluate to numbers. It is intended for use in C sources as well as in linker control
+ * files, so care must be taken to not break the syntax of either one.
+ * 
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 26.02.2013
+ *      Author: Markus Fröschle
+ */
+
+#define SYSCLK			133000
+
+#define BOOTFLASH_BASE_ADDRESS		0xe0000000
+#define BOOTFLASH_SIZE				0x800000
+#define BOOTFLASH_BAM				(BOOTFLASH_SIZE - 1)
+
+#define SDRAM_START					0x00000000	/* start at address 0 */
+#define SDRAM_SIZE					0x8000000
+
+#ifdef COMPILE_RAM
+#define TARGET_ADDRESS	(SDRAM_START + SDRAM_SIZE - 0x200000)
+#else
+#define TARGET_ADDRESS	BOOTFLASH_BASE_ADDRESS
+#endif /* COMPILE_RAM */
+
+#define DRIVER_MEM_BUFFER_SIZE	0x100000
+
+#define EMUTOS_BASE_ADDRESS 	0xe0100000
+
+#endif /* _M54455_H_ */

include/mmu.h

@@ -24,9 +24,67 @@
 #ifndef _MMU_H_
 #define _MMU_H_
 
+#include <stddef.h>
 #include "bas_types.h"
 
-#define SCA_PAGE_ID		6	/* indicates video memory page */
+/*
+ * ACR register handling macros
+ */
+#define ACR_BA(x)                   ((x) & 0xffff0000)
+#define ACR_ADMSK(x)                (((x) & 0xffff) << 16)
+#define ACR_E(x)                    (((x) & 1) << 15)
+
+#define ACR_S(x)                    (((x) & 3) << 13)
+#define ACR_S_USERMODE              0
+#define ACR_S_SUPERVISOR_MODE       1
+#define ACR_S_ALL                   2
+
+#define ACR_ADDRESS_MASK_MODE(x)	(((x) & 1) << 10)
+
+#define ACR_CACHE_MODE(x)			(((x) & 3) << 5)
+#define ACR_SUPERVISOR_PROTECT(x)	(((x) & 1) << 3)
+#define ACR_WRITE_PROTECT(x)		(((x) & 1) << 2)
+
+
+/*
+ * MMU register handling macros
+ */
+
+#define SCA_PAGE_ID			6		/* indicates video memory page */
+#define DEFAULT_PAGE_SIZE	0x2000	/* use 8k pages for MiNT compatibility */
+/*
+ * MMU page sizes
+ */
+
+enum mmu_page_size
+{
+    MMU_PAGE_SIZE_1M	= 0,
+    MMU_PAGE_SIZE_4K	= 1,
+    MMU_PAGE_SIZE_8K	= 2,
+    MMU_PAGE_SIZE_1K	= 3
+};
+
+/*
+ * cache modes
+ */
+enum mmu_cache_modes
+{
+    CACHE_WRITETHROUGH      = 0,
+    CACHE_COPYBACK          = 1,
+    CACHE_NOCACHE_PRECISE   = 2,
+    CACHE_NOCACHE_IMPRECISE = 3
+};
+
+
+/*
+ * page flags
+ */
+#define SV_PROTECT				1
+#define SV_USER					0
+
+#define ACCESS_READ		(1 << 0)
+#define	ACCESS_WRITE	(1 << 1)
+#define ACCESS_EXECUTE	(1 << 2)
 
 /*
  * global variables from linker script
@@ -34,7 +92,8 @@
 extern long video_tlb;
 extern long video_sbt;
 
+extern void mmu_enable(void);
 extern void mmu_init(void);
-extern void mmutr_miss(uint32_t addresss);
+extern int mmu_map_8k_page(uint32_t adr, uint8_t asid);
 
 #endif /* _MMU_H_ */

include/nbuf.h

@@ -10,7 +10,6 @@
 
 #include "bas_types.h"
 
-/********************************************************************/
 /*
  * Include the Queue structure definitions
  */

include/net_timer.h

@@ -8,9 +8,7 @@
 #ifndef _TIMER_H_
 #define _TIMER_H_
 
-#include <stdint.h>
-#include <stdbool.h>
-#include <stddef.h>
+#include <bas_types.h>
 
 typedef struct
 {

include/ohci.h

@@ -9,7 +9,8 @@
  
 #define USB_OHCI_MAX_ROOT_PORTS	4
 
-static int cc_to_error[16] = {
+static int cc_to_error[16] =
+{
 
 /* mapping of the OHCI CC status to error codes */
 	/* No  Error  */	       0,
@@ -30,8 +31,9 @@ static int cc_to_error[16] = {
 	/* Not Access */	       -1
 };
 
-#ifdef DEBUG
-static const char *cc_to_string[16] = {
+#ifdef DEBUG_OHCI
+static const char *cc_to_string[16] =
+{
 	"No Error",
 	"CRC: Last data packet from endpoint contained a CRC error.",
 	"BITSTUFFING:\r\nLast data packet from endpoint contained a bit stuffing violation",
@@ -62,7 +64,7 @@ static const char *cc_to_string[16] = {
 	"NOT ACCESSED:\r\nThis code is set by software before the TD is placed\r\n" \
 		     "on a list to be processed by the HC.(2)",
 };
-#endif /* DEBUG */
+#endif /* DEBUG_OHCI */
 
 /* ED States */
 
@@ -73,7 +75,8 @@ static const char *cc_to_string[16] = {
 #define ED_URB_DEL	0x08
 
 /* usb_ohci_ed */
-struct ed {
+struct ed
+{
 	uint32_t hwINFO;
 	uint32_t hwTailP;
 	uint32_t hwHeadP;
@@ -134,7 +137,8 @@ typedef struct ed ed_t;
 
 #define MAXPSW 1
 
-struct td {
+struct td
+{
 	uint32_t hwINFO;
 	uint32_t hwCBP;		/* Current Buffer Pointer */
 	uint32_t hwNextTD;		/* Next TD Pointer */
@@ -162,7 +166,8 @@ typedef struct td td_t;
  */
 
 #define NUM_INTS 32	/* part of the OHCI standard */
-struct ohci_hcca {
+struct ohci_hcca
+{
 	uint32_t	int_table[NUM_INTS];	/* Interrupt ED table */
 #if defined(CONFIG_MPC5200)
 	uint16_t	pad1;			/* set to 0 on each frame_no change */
@@ -180,7 +185,8 @@ struct ohci_hcca {
  * region.  This is Memory Mapped I/O.	You must use the readl() and
  * writel() macros defined in asm/io.h to access these!!
  */
-struct ohci_regs {
+struct ohci_regs
+{
 	/* control and status registers */
 	uint32_t	revision;
 	uint32_t	control;
@@ -203,7 +209,8 @@ struct ohci_regs {
 	uint32_t	periodicstart;
 	uint32_t	lsthresh;
 	/* Root hub ports */
-	struct	ohci_roothub_regs {
+    struct	ohci_roothub_regs
+    {
 		uint32_t	a;
 		uint32_t	b;
 		uint32_t	status;
@@ -263,7 +270,8 @@ struct ohci_regs {
 
 
 /* Virtual Root HUB */
-struct virt_root_hub {
+struct virt_root_hub
+{
 	int devnum; /* Address of Root Hub endpoint */
 	void *dev;  /* was urb */
 	void *int_addr;
@@ -383,7 +391,8 @@ typedef struct
 
 #define NUM_EDS 8		/* num of preallocated endpoint descriptors */
 
-struct ohci_device {
+struct ohci_device
+{
 	ed_t	ed[NUM_EDS];
 	int ed_cnt;
 };
@@ -395,7 +404,8 @@ struct ohci_device {
  * a subset of what the full implementation needs. (Linus)
  */
 
-typedef struct ohci {
+typedef struct ohci
+{
 	/* ------- common part -------- */
 	long handle;              /* PCI BIOS */
 	const struct pci_device_id *ent;
@@ -443,7 +453,6 @@ static int ep_link(ohci_t * ohci, ed_t * ed);
 static int ep_unlink(ohci_t * ohci, ed_t * ed);
 static ed_t * ep_add_ed(ohci_t * ohci, struct usb_device * usb_dev, uint32_t pipe, int interval, int load);
 
-/*-------------------------------------------------------------------------*/
 
 /* we need more TDs than EDs */
 #define NUM_TD 64

include/part.h

@@ -26,7 +26,8 @@
 typedef unsigned long long uint64_t;
 typedef unsigned long lbaint_t;
 
-typedef struct block_dev_desc {
+typedef struct block_dev_desc
+{
 	int		if_type;	/* type of the interface */
 	int		dev;		/* device number */
 	unsigned char	part_type;	/* partition type */

include/pci.h

@@ -21,7 +21,7 @@
  *      Author: Markus Fröschle
  */
 
-#include <stdint.h>
+#include <bas_types.h>
 #include "util.h" 	/* for swpX() */
 
 #define	 PCI_MEMORY_OFFSET	(0x80000000)
@@ -44,13 +44,13 @@
 #define PCIHTR                0x0E   /* PCI Header Type Register            */
 #define PCIBISTR              0x0F   /* PCI Build-In Self Test Register     */
 #define PCIBAR0               0x10   /* PCI Base Address Register for Memory
-                                        Accesses to Local, Runtime, and DMA */
+										Accesses to Local, Runtime, and DMA */
 #define PCIBAR1               0x14   /* PCI Base Address Register for I/O
-                                        Accesses to Local, Runtime, and DMA */
+										Accesses to Local, Runtime, and DMA */
 #define PCIBAR2               0x18   /* PCI Base Address Register for Memory
-                                        Accesses to Local Address Space 0   */
+										Accesses to Local Address Space 0   */
 #define PCIBAR3               0x1C   /* PCI Base Address Register for Memory
-                                        Accesses to Local Address Space 1   */ 
+										Accesses to Local Address Space 1   */
 #define PCIBAR4               0x20   /* PCI Base Address Register, reserved */
 #define PCIBAR5               0x24   /* PCI Base Address Register, reserved */
 #define PCICIS                0x28   /* PCI Cardbus CIS Pointer, not support*/
@@ -64,7 +64,7 @@
 #define PCIMLR                0x3F   /* PCI Max_Lat Register                */
 #define PMCAPID               0x40   /* Power Management Capability ID      */
 #define PMNEXT                0x41   /* Power Management Next Capability
-                                        Pointer                             */
+										Pointer                             */
 #define PMC                   0x42   /* Power Management Capabilities       */
 #define PMCSR                 0x44   /* Power Management Control/Status     */
 #define PMCSR_BSE             0x46   /* PMCSR Bridge Support Extensions     */
@@ -74,7 +74,7 @@
 #define HS_CSR                0x4A   /* Hot Swap Control/Status             */
 #define PVPDCNTL              0x4C   /* PCI Vital Product Data Control      */
 #define PVPD_NEXT             0x4D   /* PCI Vital Product Data Next
-                                        Capability Pointer                  */
+										Capability Pointer                  */
 #define PVPDAD                0x4E   /* PCI Vital Product Data Address      */
 #define PVPDATA               0x50   /* PCI VPD Data                        */
 
@@ -125,18 +125,18 @@
 
 struct pci_rd          /* structure of resource descriptor    */
 {
-    unsigned short next;               /* length of the following structure   */
-    unsigned short flags;              /* type of resource and misc. flags    */
-    unsigned long start;               /* start-address of resource           */
-    unsigned long length;              /* length of resource                  */
-    unsigned long offset;              /* offset PCI to phys. CPU Address     */
-    unsigned long dmaoffset;           /* offset for DMA-transfers            */
+	unsigned short next;               /* length of the following structure   */
+	unsigned short flags;              /* type of resource and misc. flags    */
+	unsigned long start;               /* start-address of resource           */
+	unsigned long length;              /* length of resource                  */
+	unsigned long offset;              /* offset PCI to phys. CPU Address     */
+	unsigned long dmaoffset;           /* offset for DMA-transfers            */
 } __attribute__ ((packed));
 
 typedef struct                       /* structure of address conversion     */
 {
-    unsigned long adr;                 /* calculated address (CPU<->PCI)      */
-    unsigned long len;                 /* length of memory range              */
+	unsigned long adr;                 /* calculated address (CPU<->PCI)      */
+	unsigned long len;                 /* length of memory range              */
 } PCI_CONV_ADR;
 
 /******************************************************************************/
@@ -191,8 +191,8 @@ typedef struct                       /* structure of address conversion     */
 #define PCI_COMMAND(i)		(((i) >> 16) & 0xffff)
 
 /* register 0x08 macros */
-#define PCI_CLASS_CODE(i)	((swpl((i)) & 0xff000000) >> 24)
-#define PCI_SUBCLASS(i)		((swpl((i)) & 0x00ff0000) >> 16)
+#define PCI_CLASS_CODE(i)	((swpl((i)) & 0xffff0000) >> 16)
+#define PCI_SUBCLASS(i)		((swpl((i)) & 0xffffff00) >> 8)
 #define PCI_PROG_IF(i)		((swpl((i)) & 0x0000ff00) >> 8)
 #define PCI_REVISION_ID(i)	((swpl((i)) & 0x000000ff))
 
@@ -243,14 +243,98 @@ extern int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t va
 extern int32_t pci_write_config_word(int32_t handle, int offset, uint16_t value);
 extern int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value);
 
-extern struct pci_rd *pci_get_resource(int32_t handle);
 extern int32_t pci_hook_interrupt(int32_t handle, void *interrupt_handler, void *parameter);
 extern int32_t pci_unhook_interrupt(int32_t handle);
 
+extern struct pci_rd *pci_get_resource(int32_t handle);
+
+/*
+ * Not implemented PCI_BIOS functions
+ */
+extern uint8_t pci_fast_read_config_byte(int32_t handle, uint16_t reg);
+extern uint16_t pci_fast_read_config_word(int32_t handle, uint16_t reg);
+extern uint32_t pci_fast_read_config_longword(int32_t handle, uint16_t reg);
+extern int32_t pci_special_cycle(uint16_t bus, uint32_t data);
+extern int32_t pci_get_routing(int32_t handle);
+extern int32_t pci_set_interrupt(int32_t handle);
+extern int32_t pci_get_card_used(int32_t handle, uint32_t *address);
+extern int32_t pci_set_card_used(int32_t handle, uint32_t *callback);
+extern int32_t pci_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address);
+extern int32_t pci_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address);
+extern int32_t pci_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address);
+extern uint8_t pci_fast_read_mem_byte(int32_t handle, uint32_t offset);
+extern uint16_t pci_fast_read_mem_word(int32_t handle, uint32_t offset);
+extern uint32_t pci_fast_read_mem_longword(int32_t handle, uint32_t offset);
+extern int32_t pci_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t pci_write_mem_word(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t pci_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val);
+extern int32_t pci_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address);
+extern int32_t pci_read_io_word(int32_t handle, uint32_t offset, uint16_t *address);
+extern int32_t pci_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address);
+extern uint8_t pci_fast_read_io_byte(int32_t handle, uint32_t offset);
+extern uint16_t pci_fast_read_io_word(int32_t handle, uint32_t offset);
+extern uint32_t pci_fast_read_io_longword(int32_t handle, uint32_t offset);
+extern int32_t pci_write_io_byte(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t pci_write_io_word(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t pci_write_io_longword(int32_t handle, uint32_t offset, uint32_t val);
+extern int32_t pci_get_machine_id(void);
+extern int32_t pci_get_pagesize(void);
+extern int32_t pci_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+extern int32_t pci_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+extern int32_t pci_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
+extern int32_t pci_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
+
+/*
+ * prototypes for PCI wrapper routines
+ */
+extern int32_t wrapper_find_pci_device(uint32_t id, uint16_t index);
+extern int32_t wrapper_find_pci_classcode(uint32_t class, uint16_t index);
+extern int32_t wrapper_read_config_byte(int32_t handle, uint16_t reg, uint8_t *address);
+extern int32_t wrapper_read_config_word(int32_t handle, uint16_t reg, uint16_t *address);
+extern int32_t wrapper_read_config_longword(int32_t handle, uint16_t reg, uint32_t *address);
+extern uint8_t wrapper_fast_read_config_byte(int32_t handle, uint16_t reg);
+extern uint16_t wrapper_fast_read_config_word(int32_t handle, uint16_t reg);
+extern uint32_t wrapper_fast_read_config_longword(int32_t handle, uint16_t reg);
+extern int32_t wrapper_write_config_byte(int32_t handle, uint16_t reg, uint16_t val);
+extern int32_t wrapper_write_config_word(int32_t handle, uint16_t reg, uint16_t val);
+extern int32_t wrapper_write_config_longword(int32_t handle, uint16_t reg, uint32_t val);
+extern int32_t wrapper_hook_interrupt(int32_t handle, uint32_t *routine, uint32_t *parameter);
+extern int32_t wrapper_unhook_interrupt(int32_t handle);
+extern int32_t wrapper_special_cycle(uint16_t bus, uint32_t data);
+extern int32_t wrapper_get_routing(int32_t handle);
+extern int32_t wrapper_set_interrupt(int32_t handle);
+extern int32_t wrapper_get_resource(int32_t handle);
+extern int32_t wrapper_get_card_used(int32_t handle, uint32_t *address);
+extern int32_t wrapper_set_card_used(int32_t handle, uint32_t *callback);
+extern int32_t wrapper_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address);
+extern int32_t wrapper_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address);
+extern int32_t wrapper_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address);
+extern uint8_t wrapper_fast_read_mem_byte(int32_t handle, uint32_t offset);
+extern uint16_t wrapper_fast_read_mem_word(int32_t handle, uint32_t offset);
+extern uint32_t wrapper_fast_read_mem_longword(int32_t handle, uint32_t offset);
+extern int32_t wrapper_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t wrapper_write_mem_word(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t wrapper_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val);
+extern int32_t wrapper_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address);
+extern int32_t wrapper_read_io_word(int32_t handle, uint32_t offset, uint16_t *address);
+extern int32_t wrapper_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address);
+extern uint8_t wrapper_fast_read_io_byte(int32_t handle, uint32_t offset);
+extern uint16_t wrapper_fast_read_io_word(int32_t handle, uint32_t offset);
+extern uint32_t wrapper_fast_read_io_longword(int32_t handle, uint32_t offset);
+extern int32_t wrapper_write_io_byte(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t wrapper_write_io_word(int32_t handle, uint32_t offset, uint16_t val);
+extern int32_t wrapper_write_io_longword(int32_t handle, uint32_t offset, uint32_t val);
+extern int32_t wrapper_get_machine_id(void);
+extern int32_t wrapper_get_pagesize(void);
+extern int32_t wrapper_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+extern int32_t wrapper_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+extern int32_t wrapper_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
+extern int32_t wrapper_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
+
 #define PCI_MK_CONF_ADDR(bus, device, function)	(MCF_PCI_PCICAR_E | \
 												((bus) << 16) | \
 												((device << 8) | \
-												(function)) 
+												(function))
 
 #define PCI_HANDLE(bus, slot, function)	(0 | ((bus & 0xff) << 10 | (slot & 0x1f) << 3 | (function & 7)))
 #define PCI_BUS_FROM_HANDLE(h)				(((h) & 0xff00) >> 10)

include/queue.h

@@ -8,8 +8,6 @@
 #ifndef _QUEUE_H_
 #define _QUEUE_H_
 
-/********************************************************************/
-
 /* 
  * Individual queue node
  */

include/radeonfb.h

@@ -10,7 +10,9 @@
 #include "i2c-algo-bit.h"
 #include "util.h"			/* for swpX() */
 #include "wait.h"
+
 //#include "radeon_theatre.h"
+
 #include "radeon_reg.h"
 
 /* Buffer are aligned on 4096 byte boundaries */

include/sd_card.h

@@ -31,7 +31,7 @@
 #define _SD_CARD_H_
 
 #include <MCF5475.h>
-#include <stdint.h>
+#include <bas_types.h>
 
 extern void sd_card_init(void);
 

include/sysinit.h

@@ -28,13 +28,17 @@
 #ifndef __SYSINIT_H__
 #define __SYSINIT_H__
 
+#include <stdbool.h>
+
 /* function(s) from init_fpga.c */
-extern void init_fpga(void);
+extern bool init_fpga(void);
 extern void init_usb(void);
 
 /* fault_vectors */
 extern void setup_vectors(void);
 
+extern bool fpga_configured;
+
 #endif /* __SYSINIT_H__ */
 
 

include/usb.h

@@ -26,7 +26,6 @@
 #ifndef _USB_H_
 #define _USB_H_
 
-//#include <stdlib.h>
 #include <bas_string.h>
 #include "driver_mem.h"
 #include "pci.h"
@@ -37,14 +36,6 @@
 
 extern long *tab_funcs_pci;
 
-#define in8(addr)		Fast_read_mem_byte(usb_handle,addr)
-#define in16r(addr)		Fast_read_mem_word(usb_handle,addr)
-#define in32r(addr)		Fast_read_mem_longword(usb_handle,addr)
-#define out8(addr,val)	Write_mem_byte(usb_handle,addr,val)
-#define out16r(addr,val)	Write_mem_word(usb_handle,addr,val)
-#define out32r(addr,val)	Write_mem_longword(usb_handle,addr,val)
-
-
 #define __u8 uint8_t
 #define __u16 uint16_t
 #define __u32 uint32_t
@@ -74,15 +65,19 @@ extern int sprintD(char *s, const char *fmt, ...);
 
 #define USB_CNTL_TIMEOUT 100 /* 100ms timeout */
 
+#define USB_BUFSIZ	512
+
 /* String descriptor */
-struct usb_string_descriptor {
+struct usb_string_descriptor
+{
 	uint8_t	bLength;
 	uint8_t	bDescriptorType;
 	uint16_t	wData[1];
 } __attribute__ ((packed));
 
 /* device request (setup) */
-struct devrequest {
+struct devrequest
+{
 	uint8_t	requesttype;
 	uint8_t	request;
 	uint16_t	value;
@@ -91,13 +86,15 @@ struct devrequest {
 } __attribute__ ((packed));
 
 /* All standard descriptors have these 2 fields in common */
-struct usb_descriptor_header {
+struct usb_descriptor_header
+{
 	uint8_t	bLength;
 	uint8_t	bDescriptorType;
 } __attribute__ ((packed));
 
 /* Device descriptor */
-struct usb_device_descriptor {
+struct usb_device_descriptor
+{
 	uint8_t	bLength;
 	uint8_t	bDescriptorType;
 	uint16_t	bcdUSB;
@@ -115,7 +112,8 @@ struct usb_device_descriptor {
 } __attribute__ ((packed));
 
 /* Endpoint descriptor */
-struct usb_endpoint_descriptor {
+struct usb_endpoint_descriptor
+{
 	uint8_t	bLength;
 	uint8_t	bDescriptorType;
 	uint8_t	bEndpointAddress;
@@ -127,7 +125,8 @@ struct usb_endpoint_descriptor {
 } __attribute__ ((packed)) __attribute__ ((aligned(2)));
 
 /* Interface descriptor */
-struct usb_interface_descriptor {
+struct usb_interface_descriptor
+{
 	uint8_t	bLength;
 	uint8_t	bDescriptorType;
 	uint8_t	bInterfaceNumber;
@@ -147,7 +146,8 @@ struct usb_interface_descriptor {
 
 
 /* Configuration descriptor information.. */
-struct usb_config_descriptor {
+struct usb_config_descriptor
+{
 	uint8_t	bLength;
 	uint8_t	bDescriptorType;
 	uint16_t	wTotalLength;
@@ -161,7 +161,8 @@ struct usb_config_descriptor {
 	struct usb_interface_descriptor if_desc[USB_MAXINTERFACES];
 } __attribute__ ((packed));
 
-enum {
+enum
+{
 	/* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */
 	PACKET_SIZE_8   = 0,
 	PACKET_SIZE_16  = 1,
@@ -169,7 +170,8 @@ enum {
 	PACKET_SIZE_64  = 3,
 };
 
-struct usb_device {
+struct usb_device
+{
 	int	devnum;			/* Device number on USB bus */
 	int	speed;			/* full/low/high */
 	char mf[32];			/* manufacturer */
@@ -229,67 +231,62 @@ typedef struct
  * this is how the lowlevel part communicate with the outer world
  */
 
-int ohci_usb_lowlevel_init(int32_t handle, const struct pci_device_id *ent, void **priv);
-int ohci_usb_lowlevel_stop(void *priv);
-int ohci_submit_bulk_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len);
-int ohci_submit_control_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, struct devrequest *setup);
-int ohci_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
-void ohci_usb_enable_interrupt(int enable);
+extern int ohci_usb_lowlevel_init(int32_t handle, const struct pci_device_id *ent, void **priv);
+extern int ohci_usb_lowlevel_stop(void *priv);
+extern int ohci_submit_bulk_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len);
+extern int ohci_submit_control_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, struct devrequest *setup);
+extern int ohci_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
+extern void ohci_usb_enable_interrupt(int enable);
 
-int ehci_usb_lowlevel_init(long handle, const struct pci_device_id *ent, void **priv);
-int ehci_usb_lowlevel_stop(void *priv);
-int ehci_submit_bulk_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len);
-int ehci_submit_control_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, struct devrequest *setup);
-int ehci_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
-void ehci_usb_enable_interrupt(int enable);
+extern int ehci_usb_lowlevel_init(long handle, const struct pci_device_id *ent, void **priv);
+extern int ehci_usb_lowlevel_stop(void *priv);
+extern int ehci_submit_bulk_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len);
+extern int ehci_submit_control_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, struct devrequest *setup);
+extern int ehci_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
+extern void ehci_usb_enable_interrupt(int enable);
 
-void usb_enable_interrupt(int enable);
+extern void usb_enable_interrupt(int enable);
+
+extern int usb_new_device(struct usb_device *dev);
+extern struct usb_device *usb_alloc_new_device(int bus_index, void *priv);
+extern void usb_disconnect(struct usb_device **pdev);
 
 #define USB_MAX_STOR_DEV 5
-block_dev_desc_t *usb_stor_get_dev(int index);
-int usb_stor_scan(void);
-int usb_stor_info(void);
-int usb_stor_register(struct usb_device *dev);
-int usb_stor_deregister(struct usb_device *dev);
 
-int drv_usb_kbd_init(void);
-int usb_kbd_register(struct usb_device *dev);
-int usb_kbd_deregister(struct usb_device *dev);
+extern block_dev_desc_t *usb_stor_get_dev(int index);
+extern int usb_stor_scan(void);
+extern int usb_stor_info(void);
+extern int usb_stor_register(struct usb_device *dev);
+extern int usb_stor_deregister(struct usb_device *dev);
 
-int drv_usb_mouse_init(void);
-int usb_mouse_register(struct usb_device *dev);
-int usb_mouse_deregister(struct usb_device *dev);
+extern int drv_usb_kbd_init(void);
+extern int usb_kbd_register(struct usb_device *dev);
+extern int usb_kbd_deregister(struct usb_device *dev);
 
-extern char usb_error_str[256];
-
-/* memory */
-void *usb_malloc(long amount);
-int usb_free(void *addr);
-int usb_mem_init(void);
-void usb_mem_stop(void);
+extern int drv_usb_mouse_init(void);
+extern int usb_mouse_register(struct usb_device *dev);
+extern int usb_mouse_deregister(struct usb_device *dev);
 
 /* routines */
-USB_COOKIE *usb_get_cookie(long id);
-void usb_error_msg(const char *const fmt, ... );
-int usb_init(int32_t handle, const struct pci_device_id *ent); /* initialize the USB Controller */
-int usb_stop(void); /* stop the USB Controller */
+extern int usb_init(int32_t handle, const struct pci_device_id *ent); /* initialize the USB Controller */
+extern int usb_stop(void); /* stop the USB Controller */
 
-int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol);
-int usb_set_idle(struct usb_device *dev, int ifnum, int duration, int report_id);
-struct usb_device *usb_get_dev_index(int index, int bus);
-int usb_control_msg(struct usb_device *dev, unsigned int pipe, uint8_t request, uint8_t requesttype, uint16_t value, 
- uint16_t index, void *data, uint16_t size, int timeout);
-int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, void *data, int len, int *actual_length, int timeout);
-int usb_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
-void usb_disable_asynch(int disable);
-int usb_maxpacket(struct usb_device *dev, uint32_t pipe);
-void wait_ms(uint32_t ms);
-int usb_get_configuration_no(struct usb_device *dev, uint8_t *buffer, int cfgno);
-int usb_get_report(struct usb_device *dev, int ifnum, uint8_t type, uint8_t id, void *buf, int size);
-int usb_get_class_descriptor(struct usb_device *dev, int ifnum, uint8_t type, uint8_t id, void *buf, int size);
-int usb_clear_halt(struct usb_device *dev, int pipe);
-int usb_string(struct usb_device *dev, int index, char *buf, size_t size);
-int usb_set_interface(struct usb_device *dev, int interface, int alternate);
+extern int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol);
+extern int usb_set_idle(struct usb_device *dev, int ifnum, int duration, int report_id);
+extern struct usb_device *usb_get_dev_index(int index, int bus);
+extern int usb_control_msg(struct usb_device *dev, unsigned int pipe, uint8_t request, uint8_t requesttype,
+						   uint16_t value, uint16_t index, void *data, uint16_t size, int timeout);
+extern int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, void *data, int len, int *actual_length, int timeout);
+extern int usb_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
+extern void usb_disable_asynch(int disable);
+extern int usb_maxpacket(struct usb_device *dev, uint32_t pipe);
+
+extern int usb_get_configuration_no(struct usb_device *dev, uint8_t *buffer, int cfgno);
+extern int usb_get_report(struct usb_device *dev, int ifnum, uint8_t type, uint8_t id, void *buf, int size);
+extern int usb_get_class_descriptor(struct usb_device *dev, int ifnum, uint8_t type, uint8_t id, void *buf, int size);
+extern int usb_clear_halt(struct usb_device *dev, int pipe);
+extern int usb_string(struct usb_device *dev, int index, char *buf, size_t size);
+extern int usb_set_interface(struct usb_device *dev, int interface, int alternate);
 
 /*
  * Calling this entity a "pipe" is glorifying it. A USB pipe
@@ -391,19 +388,22 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate);
 /*************************************************************************
  * Hub Stuff
  */
-struct usb_port_status {
+struct usb_port_status
+{
 	uint16_t wPortStatus;
 	uint16_t wPortChange;
 } __attribute__ ((packed));
 
-struct usb_hub_status {
+struct usb_hub_status
+{
 	uint16_t wHubStatus;
 	uint16_t wHubChange;
 } __attribute__ ((packed));
 
 
 /* Hub descriptor */
-struct usb_hub_descriptor {
+struct usb_hub_descriptor
+{
 	uint8_t  bLength;
 	uint8_t  bDescriptorType;
 	uint8_t  bNbrPorts;
@@ -417,7 +417,8 @@ struct usb_hub_descriptor {
 } __attribute__ ((packed));
 
 
-struct usb_hub_device {
+struct usb_hub_device
+{
 	struct usb_device *pusb_dev;
 	struct usb_hub_descriptor desc;
 };

include/usb_hub.h

@@ -0,0 +1,10 @@
+#ifndef USB_HUB_H
+#define USB_HUB_H
+
+extern int bus_index;
+
+extern void usb_hub_reset(int bus_index);
+extern int usb_hub_probe(struct usb_device *dev, int ifnum);
+extern int hub_port_reset(struct usb_device *dev, int port, unsigned short *portstat);
+
+#endif // USB_HUB_H

include/util.h

@@ -25,7 +25,7 @@
 #ifndef UTIL_H_
 #define UTIL_H_
 
-#include <stdint.h>
+#include <bas_types.h>
 
 #define NOP() __asm__ __volatile__("nop\n\t" : : : "memory")
 
@@ -59,7 +59,7 @@ static inline uint32_t swpl(uint32_t l)
 	register uint32_t result asm("d0");
 
 	__asm__ __volatile__
-	(						
+	(
 		"lea		%[input],a0\n\t"				\
 		"mvz.b	3(a0),%[output]\n\t"			\
 		"lsl.l	#8,%[output]\n\t"				\
@@ -74,7 +74,7 @@ static inline uint32_t swpl(uint32_t l)
 	);
 	return result;
 }
-	
+
 
 /*
  * WORD swpw2(ULONG val);
@@ -85,17 +85,17 @@ static inline uint32_t swpl(uint32_t l)
 #define swpw2(a)                          \
   __extension__                           \
   ({unsigned long _tmp;                   \
-    __asm__ __volatile__                  \
-    ("move.b  (%1),%0\n\t"                \
-     "move.b  1(%1),(%1)\n\t"             \
-     "move.b  %0,1(%1)\n\t"               \
-     "move.b  2(%1),%0\n\t"               \
-     "move.b  3(%1),2(%1)\n\t"            \
-     "move.b  %0,3(%1)"                   \
-    : "=d"(_tmp)     /* outputs */        \
-    : "a"(&a)        /* inputs  */        \
-    : "cc", "memory" /* clobbered */      \
-    );                                    \
+	__asm__ __volatile__                  \
+	("move.b  (%1),%0\n\t"                \
+	 "move.b  1(%1),(%1)\n\t"             \
+	 "move.b  %0,1(%1)\n\t"               \
+	 "move.b  2(%1),%0\n\t"               \
+	 "move.b  3(%1),2(%1)\n\t"            \
+	 "move.b  %0,3(%1)"                   \
+	: "=d"(_tmp)     /* outputs */        \
+	: "a"(&a)        /* inputs  */        \
+	: "cc", "memory" /* clobbered */      \
+	);                                    \
   })
 
 /*
@@ -144,10 +144,10 @@ __extension__                             \
 #define regsafe_call(addr)                         \
 __extension__                                      \
 ({__asm__ volatile ("lea     -60(sp),sp\n\t"       \
-                    "movem.l d0-d7/a0-a6,(sp)");   \
-  ((void (*)(void))addr)();                        \
+					"movem.l d0-d7/a0-a6,(sp)");   \
+  ((void (*) (void)) addr)();                      \
   __asm__ volatile ("movem.l (sp),d0-d7/a0-a6\n\t" \
-                    "lea     60(sp),sp");          \
+					"lea     60(sp),sp");          \
 })
 
 

include/version.h

@@ -29,7 +29,7 @@
  */
 
 #define MAJOR_VERSION	0
-#define MINOR_VERSION	83
+#define MINOR_VERSION	86
 
 
 #endif /* VERSION_H_ */

include/video.h

@@ -1,9 +1,7 @@
 #ifndef _VIDEO_H_
 #define _VIDEO_H_
 
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
+#include <bas_types.h>
 #include "bas_printf.h"
 
 extern void video_init(void);

include/wait.h

@@ -29,55 +29,28 @@
 
 #include <bas_types.h>
 
-#if MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
 #include "firebee.h"
-#elif MACHINE_M5484LITE
+#elif defined(MACHINE_M5484LITE)
 #include "m5484l.h"
+#elif defined(MACHINE_M54455)
+#include "m54455.h"
+#else
+#error "unknown machine"
 #endif /* MACHINE_FIREBEE */
 
 #include "MCF5475.h"
 
 typedef bool (*checker_func)(void);
 
-extern __inline__ void wait(uint32_t) __attribute__((always_inline));
-extern __inline__ bool waitfor(uint32_t us, checker_func condition) __attribute__((always_inline));
-
-extern __inline__ uint32_t get_timer(void)
+extern void wait(uint32_t);
+inline static void udelay(long us)
 {
-	return MCF_SLT_SCNT(0);
-}
-/*
- * wait for the specified number of us on slice timer 0. Replaces the original routines that had
- * the number of useconds to wait for hardcoded in their name.
- */
-extern __inline__ void wait(uint32_t us)
-{
-	int32_t target = MCF_SLT_SCNT(0) - (us * (SYSCLK / 1000));
-
-	while (MCF_SLT_SCNT(0) - target > 0);
+    wait((uint32_t) us);
 }
 
-/*
- * same as above, but with milliseconds wait time
- */
-extern __inline__ void wait_ms(uint32_t ms)
-{
-	wait(ms * 1000);
-}
-/*
- * the same as above, with a checker function which gets called while
- * busy waiting and allows for an early return if it returns true
- */
-extern __inline__ bool waitfor(uint32_t us, checker_func condition)
-{
-	int32_t target = MCF_SLT_SCNT(0) - (us * (SYSCLK / 1000));
-	bool res;
+extern bool waitfor(uint32_t us, checker_func condition);
+extern uint32_t get_timer(void);
+extern void wait_ms(uint32_t ms);
 
-	do
-	{
-		if ((res = (*condition)()))
-			return res;
-	} while (MCF_SLT_SCNT(0) - target > 0);
-	return false;
-}
 #endif /* _WAIT_H_ */

include/x86debug.h

@@ -37,7 +37,7 @@
 ****************************************************************************/
 /* $XFree86: xc/extras/x86emu/src/x86emu/x86emu/debug.h,v 1.4 2000/11/21 23:10:27 tsi Exp $ */
 
-#include <stdint.h>
+#include <bas_types.h>
 #include "bas_printf.h"
 
 /*
@@ -135,7 +135,7 @@
 
 #define SAVE_IP_CS(x,y)                               			\
 	if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \
-              | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \
+			  | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \
 		M.x86.saved_cs = x;                          			\
 		M.x86.saved_ip = y;                          			\
 	}

kbd/ikbd.c

@@ -18,7 +18,7 @@
 
  */
 
-#include <stdint.h>
+#include <bas_types.h>
 #include "bas_printf.h"
 #include "bas_string.h"
 
@@ -40,276 +40,300 @@ static unsigned char tx_queue[QUEUE_LEN];
 static unsigned char wptr = 0, rptr = 0;
 
 // structure to keep track of ikbd state
-static struct {
-  unsigned char cmd;
-  unsigned char state;
-  unsigned char expect;
+static struct
+{
+	unsigned char cmd;
+	unsigned char state;
+	unsigned char expect;
 
-  // joystick state
-  unsigned char joystick[2];
+	// joystick state
+	unsigned char joystick[2];
 
-  // mouse state
-  unsigned short mouse_pos_x, mouse_pos_y;
-  unsigned char mouse_buttons;
+	// mouse state
+	unsigned short mouse_pos_x, mouse_pos_y;
+	unsigned char mouse_buttons;
 } ikbd;
 
 // #define IKBD_DEBUG
 
-void ikbd_init() {
-  // reset ikbd state
-  memset(&ikbd, 0, sizeof(ikbd));
-  ikbd.state = IKBD_DEFAULT;
+void ikbd_init()
+{
+	// reset ikbd state
+	memset(&ikbd, 0, sizeof(ikbd));
+	ikbd.state = IKBD_DEFAULT;
 }
 
-static void enqueue(unsigned char b) {
-  if(((wptr + 1)&(QUEUE_LEN-1)) == rptr) {
-    xprintf("IKBD: !!!!!!! tx queue overflow !!!!!!!!!\n");
-    return;
-  }
+static void enqueue(unsigned char b)
+{
+	if (((wptr + 1)&(QUEUE_LEN-1)) == rptr)
+	{
+		xprintf("IKBD: !!!!!!! tx queue overflow !!!!!!!!!\n");
+		return;
+	}
 
-  tx_queue[wptr] = b;
-  wptr = (wptr+1)&(QUEUE_LEN-1);
+	tx_queue[wptr] = b;
+	wptr = (wptr + 1) & (QUEUE_LEN - 1);
 }
 
 // convert internal joystick format into atari ikbd format
-static unsigned char joystick_map2ikbd(unsigned in) {
-  unsigned char out = 0;
+static unsigned char joystick_map2ikbd(unsigned in)
+{
+	unsigned char out = 0;
 
-  if(in & JOY_UP)    out |= 0x01;
-  if(in & JOY_DOWN)  out |= 0x02;
-  if(in & JOY_LEFT)  out |= 0x04;
-  if(in & JOY_RIGHT) out |= 0x08;
-  if(in & JOY_BTN1)  out |= 0x80;
+	if (in & JOY_UP)    out |= 0x01;
+	if (in & JOY_DOWN)  out |= 0x02;
+	if (in & JOY_LEFT)  out |= 0x04;
+	if (in & JOY_RIGHT) out |= 0x08;
+	if (in & JOY_BTN1)  out |= 0x80;
 
-  return out;
+	return out;
 }
 
 // process inout from atari core into ikbd
-void ikbd_handle_input(unsigned char cmd) {
-  // expecting a second byte for command
-  if(ikbd.expect) {
-    ikbd.expect--;
+void ikbd_handle_input(unsigned char cmd)
+{
+	// expecting a second byte for command
+	if (ikbd.expect)
+	{
+		ikbd.expect--;
 
-    // last byte of command received
-    if(!ikbd.expect) {
-      switch(ikbd.cmd) {
-      case 0x07: // set mouse button action
-        xprintf("IKBD: mouse button action = %x\n", cmd);
+		// last byte of command received
+		if (!ikbd.expect)
+		{
+			switch(ikbd.cmd)
+			{
+				case 0x07: // set mouse button action
+					xprintf("IKBD: mouse button action = %x\n", cmd);
 
-        // bit 2: Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75)
-        if(cmd & 0x04) ikbd.state |=  IKBD_STATE_MOUSE_BUTTON_AS_KEY;
-        else           ikbd.state &= ~IKBD_STATE_MOUSE_BUTTON_AS_KEY;
+					// bit 2: Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75)
+					if(cmd & 0x04) ikbd.state |=  IKBD_STATE_MOUSE_BUTTON_AS_KEY;
+					else           ikbd.state &= ~IKBD_STATE_MOUSE_BUTTON_AS_KEY;
 
-        break;
+					break;
 
-      case 0x80: // ibkd reset
-        // reply "everything is ok"
-        enqueue(0xf0);
-        break;
+				case 0x80: // ibkd reset
+					// reply "everything is ok"
+					enqueue(0xf0);
+					break;
 
-      default:
-        break;
-      }
-    }
+				default:
+					break;
+			}
+		}
 
-    return;
-  }
+		return;
+	}
 
-  ikbd.cmd = cmd;
+	ikbd.cmd = cmd;
 
-  switch(cmd) {
-  case 0x07:
-    xprintf("IKBD: Set mouse button action");
-    ikbd.expect = 1;
-    break;
+	switch(cmd)
+	{
+		case 0x07:
+			xprintf("IKBD: Set mouse button action");
+			ikbd.expect = 1;
+			break;
 
-  case 0x08:
-    xprintf("IKBD: Set relative mouse positioning");
-    ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED;
-    ikbd.state &= ~IKBD_STATE_MOUSE_ABSOLUTE;
-    break;
+		case 0x08:
+			xprintf("IKBD: Set relative mouse positioning");
+			ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED;
+			ikbd.state &= ~IKBD_STATE_MOUSE_ABSOLUTE;
+			break;
 
-  case 0x09:
-    xprintf("IKBD: Set absolute mouse positioning");
-    ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED;
-    ikbd.state |=  IKBD_STATE_MOUSE_ABSOLUTE;
-    ikbd.expect = 4;
-    break;
+		case 0x09:
+			xprintf("IKBD: Set absolute mouse positioning");
+			ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED;
+			ikbd.state |=  IKBD_STATE_MOUSE_ABSOLUTE;
+			ikbd.expect = 4;
+			break;
 
-  case 0x0b:
-    xprintf("IKBD: Set Mouse threshold");
-    ikbd.expect = 2;
-    break;
+		case 0x0b:
+			xprintf("IKBD: Set Mouse threshold");
+			ikbd.expect = 2;
+			break;
 
-  case 0x0f:
-    xprintf("IKBD: Set Y at bottom");
-    ikbd.state |= IKBD_STATE_MOUSE_Y_BOTTOM;
-    break;
+		case 0x0f:
+			xprintf("IKBD: Set Y at bottom");
+			ikbd.state |= IKBD_STATE_MOUSE_Y_BOTTOM;
+			break;
 
-  case 0x10:
-    xprintf("IKBD: Set Y at top");
-    ikbd.state &= ~IKBD_STATE_MOUSE_Y_BOTTOM;
-    break;
+		case 0x10:
+			xprintf("IKBD: Set Y at top");
+			ikbd.state &= ~IKBD_STATE_MOUSE_Y_BOTTOM;
+			break;
 
-  case 0x12:
-    xprintf("IKBD: Disable mouse");
-    ikbd.state |= IKBD_STATE_MOUSE_DISABLED;
-    break;
+		case 0x12:
+			xprintf("IKBD: Disable mouse");
+			ikbd.state |= IKBD_STATE_MOUSE_DISABLED;
+			break;
 
-  case 0x14:
-    xprintf("IKBD: Set Joystick event reporting");
-    ikbd.state |= IKBD_STATE_JOYSTICK_EVENT_REPORTING;
-    break;
+		case 0x14:
+			xprintf("IKBD: Set Joystick event reporting");
+			ikbd.state |= IKBD_STATE_JOYSTICK_EVENT_REPORTING;
+			break;
 
-  case 0x15:
-    xprintf("IKBD: Set Joystick interrogation mode");
-    ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING;
-    break;
+		case 0x15:
+			xprintf("IKBD: Set Joystick interrogation mode");
+			ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING;
+			break;
 
-  case 0x16: // interrogate joystick
-    // send reply
-    enqueue(0xfd);
-    enqueue(joystick_map2ikbd(ikbd.joystick[0]));
-    enqueue(joystick_map2ikbd(ikbd.joystick[1]));
-    break;
+		case 0x16: // interrogate joystick
+			// send reply
+			enqueue(0xfd);
+			enqueue(joystick_map2ikbd(ikbd.joystick[0]));
+			enqueue(joystick_map2ikbd(ikbd.joystick[1]));
+			break;
 
-  case 0x1a:
-    xprintf("IKBD: Disable joysticks");
-    ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING;
-    break;
+		case 0x1a:
+			xprintf("IKBD: Disable joysticks");
+			ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING;
+			break;
 
-  case 0x1c:
-    xprintf("IKBD: Interrogate time of day");
+		case 0x1c:
+			xprintf("IKBD: Interrogate time of day");
 
-    enqueue(0xfc);
-    enqueue(0x13);  // year bcd
-    enqueue(0x03);  // month bcd
-    enqueue(0x07);  // day bcd
-    enqueue(0x20);  // hour bcd
-    enqueue(0x58);  // minute bcd
-    enqueue(0x00);  // second bcd
-    break;
-   
+			enqueue(0xfc);
+			enqueue(0x13);  // year bcd
+			enqueue(0x03);  // month bcd
+			enqueue(0x07);  // day bcd
+			enqueue(0x20);  // hour bcd
+			enqueue(0x58);  // minute bcd
+			enqueue(0x00);  // second bcd
+			break;
 
-  case 0x80:
-    xprintf("IKBD: Reset");
-    ikbd.expect = 1;
-    ikbd.state = IKBD_DEFAULT;
-    break;
 
-  default:
-    xprintf("IKBD: unknown command: %x\n", cmd);
-    break;
-  }
+		case 0x80:
+			xprintf("IKBD: Reset");
+			ikbd.expect = 1;
+			ikbd.state = IKBD_DEFAULT;
+			break;
+
+		default:
+			xprintf("IKBD: unknown command: %x\n", cmd);
+			break;
+	}
 }
 
 void ikbd_poll(void) {
-  static int mtimer = 0;
-  if(CheckTimer(mtimer)) {
-    mtimer = GetTimer(10);
-   
-    // check for incoming ikbd data
-    EnableIO();
-    SPI(UIO_IKBD_IN);
-   
-    while(SPI(0))
-      ikbd_handle_input(SPI(0));
-   
-    DisableIO();
-  }
+	static int mtimer = 0;
+	if (CheckTimer(mtimer))
+	{
+		mtimer = GetTimer(10);
 
-  // send data from queue if present
-  if(rptr == wptr) return;
-   
-  // transmit data from queue
-  EnableIO();
-  SPI(UIO_IKBD_OUT);
-  SPI(tx_queue[rptr]);
-  DisableIO();
- 
-  rptr = (rptr+1)&(QUEUE_LEN-1);  
+		// check for incoming ikbd data
+		EnableIO();
+		SPI(UIO_IKBD_IN);
+
+		while(SPI(0))
+			ikbd_handle_input(SPI(0));
+
+		DisableIO();
+	}
+
+	// send data from queue if present
+	if(rptr == wptr) return;
+
+	// transmit data from queue
+	EnableIO();
+	SPI(UIO_IKBD_OUT);
+	SPI(tx_queue[rptr]);
+	DisableIO();
+
+	rptr = (rptr + 1) & (QUEUE_LEN - 1);
 }
 
-void ikbd_joystick(unsigned char joystick, unsigned char map) {
-  // todo: suppress events for joystick 0 as long as mouse
-  // is enabled?
- 
-  if(ikbd.state & IKBD_STATE_JOYSTICK_EVENT_REPORTING) {
+void ikbd_joystick(unsigned char joystick, unsigned char map)
+{
+	// todo: suppress events for joystick 0 as long as mouse
+	// is enabled?
+
+	if (ikbd.state & IKBD_STATE_JOYSTICK_EVENT_REPORTING)
+	{
 #ifdef IKBD_DEBUG
-    xprintf("IKBD: joy %d %x\n", joystick, map);
+		xprintf("IKBD: joy %d %x\n", joystick, map);
 #endif
 
-    // only report joystick data for joystick 0 if the mouse is disabled
-    if((ikbd.state & IKBD_STATE_MOUSE_DISABLED) || (joystick == 1)) {    
-      enqueue(0xfe + joystick);
-      enqueue(joystick_map2ikbd(map));
-    }
-   
-    if(!(ikbd.state & IKBD_STATE_MOUSE_DISABLED)) {
-      // the fire button also generates a mouse event if
-      // mouse reporting is enabled
-      if((map & JOY_BTN1) != (ikbd.joystick[joystick] & JOY_BTN1)) {
-        // generate mouse event (ikbd_joystick_buttons is evaluated inside
-        // user_io_mouse)
-        ikbd.joystick[joystick] = map;
-        ikbd_mouse(0, 0, 0);
-      }
-    }
-  }
+		// only report joystick data for joystick 0 if the mouse is disabled
+		if ((ikbd.state & IKBD_STATE_MOUSE_DISABLED) || (joystick == 1))
+		{
+			enqueue(0xfe + joystick);
+			enqueue(joystick_map2ikbd(map));
+		}
+
+		if (!(ikbd.state & IKBD_STATE_MOUSE_DISABLED))
+		{
+			// the fire button also generates a mouse event if
+			// mouse reporting is enabled
+			if ((map & JOY_BTN1) != (ikbd.joystick[joystick] & JOY_BTN1))
+			{
+				// generate mouse event (ikbd_joystick_buttons is evaluated inside
+				// user_io_mouse)
+				ikbd.joystick[joystick] = map;
+				ikbd_mouse(0, 0, 0);
+			}
+		}
+	}
 #ifdef IKBD_DEBUG
-  else
-    xprintf("IKBD: no monitor, drop joy %d %x\n", joystick, map);
+	else
+		xprintf("IKBD: no monitor, drop joy %d %x\n", joystick, map);
 #endif
- 
-  // save state of joystick for interrogation mode
-  ikbd.joystick[joystick] = map;
+
+	// save state of joystick for interrogation mode
+	ikbd.joystick[joystick] = map;
 }
 
-void ikbd_keyboard(unsigned char code) {
+void ikbd_keyboard(unsigned char code)
+{
 #ifdef IKBD_DEBUG
-  xprintf("IKBD: send keycode %x%s\n", code&0x7f, (code&0x80)?" BREAK":"");
+	xprintf("IKBD: send keycode %x%s\n", code&0x7f, (code&0x80)?" BREAK":"");
 #endif
-  enqueue(code);
+	enqueue(code);
 }
 
-void ikbd_mouse(uint8_t b, int8_t x, int8_t y) {
-  if(ikbd.state & IKBD_STATE_MOUSE_DISABLED)
-    return;
+void ikbd_mouse(uint8_t b, int8_t x, int8_t y)
+{
+	if (ikbd.state & IKBD_STATE_MOUSE_DISABLED)
+		return;
+
+	// joystick and mouse buttons are wired together in
+	// atari st
+	b |= (ikbd.joystick[0] & JOY_BTN1)?1:0;
+	b |= (ikbd.joystick[1] & JOY_BTN1)?2:0;
+
+	static unsigned char b_old = 0;
+	// monitor state of two mouse buttons
+	if (b != b_old)
+	{
+		// check if mouse buttons are supposed to be treated like keys
+		if (ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY)
+		{
+			// Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75)
+
+			// handle left mouse button
+			if((b ^ b_old) & 1) ikbd_keyboard(0x74 | ((b&1)?0x00:0x80));
+			// handle right mouse button
+			if((b ^ b_old) & 2) ikbd_keyboard(0x75 | ((b&2)?0x00:0x80));
+		}
+		b_old = b;
+	}
 
-  // joystick and mouse buttons are wired together in
-  // atari st
-  b |= (ikbd.joystick[0] & JOY_BTN1)?1:0;
-  b |= (ikbd.joystick[1] & JOY_BTN1)?2:0;
- 
-  static unsigned char b_old = 0;
-  // monitor state of two mouse buttons
-  if(b != b_old) {
-    // check if mouse buttons are supposed to be treated like keys
-    if(ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY) {
-      // Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75)
-     
-      // handle left mouse button
-      if((b ^ b_old) & 1) ikbd_keyboard(0x74 | ((b&1)?0x00:0x80));
-      // handle right mouse button
-      if((b ^ b_old) & 2) ikbd_keyboard(0x75 | ((b&2)?0x00:0x80));
-    }
-    b_old = b;
-  }
- 
 #if 0
-  if(ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY) {
-    b = 0;
-    // if mouse position is 0/0 quit here
-    if(!x && !y) return;
-  }
+	if(ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY)
+	{
+		b = 0;
+		// if mouse position is 0/0 quit here
+		if(!x && !y) return;
+	}
 #endif
 
-  if(ikbd.state & IKBD_STATE_MOUSE_ABSOLUTE) {
-  } else {
-    // atari has mouse button bits swapped
-    enqueue(0xf8|((b&1)?2:0)|((b&2)?1:0));
-    enqueue(x);
-    enqueue((ikbd.state & IKBD_STATE_MOUSE_Y_BOTTOM)?-y:y);
-  }
+	if (ikbd.state & IKBD_STATE_MOUSE_ABSOLUTE)
+	{
+	}
+	else
+	{
+		// atari has mouse button bits swapped
+		enqueue(0xf8|((b&1)?2:0)|((b&2)?1:0));
+		enqueue(x);
+		enqueue((ikbd.state & IKBD_STATE_MOUSE_Y_BOTTOM)?-y:y);
+	}
 }
 

mcf5474.gdb

@@ -5,7 +5,7 @@
 define addresses
 set $vbr   = 0x00000000
 #monitor bdm-ctl-set 0x0801 0x00000000
- 
+
 set $mbar  = 0xFF000000
 #monitor bdm-ctl-set 0x0C0F 0xFF000000
 
@@ -22,30 +22,30 @@ end
 
 define setup-dram
 # Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
-set *((long *) 0xFF000500) = 0xE0000000		
-set *((long *) 0xFF000508) = 0x00041180		
-set *((long *) 0xFF000504) = 0x007F0001		
+set *((long *) 0xFF000500) = 0xE0000000
+set *((long *) 0xFF000508) = 0x00041180
+set *((long *) 0xFF000504) = 0x007F0001
 
 # set *((long *) 0xFF00050C) = 0xFFF00000		# ATARI I/O address
 
 # SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
-set *((long *) 0xFF000004) = 0x000002AA		
-set *((long *) 0xFF000020) = 0x0000001A		
-set *((long *) 0xFF000024) = 0x0800001A		
-set *((long *) 0xFF000028) = 0x1000001A		
-set *((long *) 0xFF00002C) = 0x1800001A		
-set *((long *) 0xFF000108) = 0x73622830		
-set *((long *) 0xFF00010C) = 0x46770000		
+set *((long *) 0xFF000004) = 0x000002AA
+set *((long *) 0xFF000020) = 0x0000001A
+set *((long *) 0xFF000024) = 0x0800001A
+set *((long *) 0xFF000028) = 0x1000001A
+set *((long *) 0xFF00002C) = 0x1800001A
+set *((long *) 0xFF000108) = 0x73622830
+set *((long *) 0xFF00010C) = 0x46770000
 
 
-set *((long *) 0xFF000104) = 0xE10D0002		
-set *((long *) 0xFF000100) = 0x40010000		
-set *((long *) 0xFF000100) = 0x048D0000		
-set *((long *) 0xFF000104) = 0xE10D0002		
-set *((long *) 0xFF000104) = 0xE10D0004		
-set *((long *) 0xFF000104) = 0xE10D0004		
-set *((long *) 0xFF000100) = 0x008D0000		
-set *((long *) 0xFF000104) = 0x710D0F00		
+set *((long *) 0xFF000104) = 0xE10D0002
+set *((long *) 0xFF000100) = 0x40010000
+set *((long *) 0xFF000100) = 0x048D0000
+set *((long *) 0xFF000104) = 0xE10D0002
+set *((long *) 0xFF000104) = 0xE10D0004
+set *((long *) 0xFF000104) = 0xE10D0004
+set *((long *) 0xFF000100) = 0x008D0000
+set *((long *) 0xFF000104) = 0x710D0F00
 end
 
 define cu
@@ -61,6 +61,11 @@ define ib
 	setup-dram
 end
 
+define run
+	continue
+end
+
 tr
 ib
-load
+add-symbol-file ../emutos/emutos2.img 0xe00000
+load firebee/ram.elf

net/am79c874.c

@@ -13,8 +13,10 @@
 #include "firebee.h"
 #elif defined(MACHINE_M5484LITE)
 #include "m5484l.h"
+#elif defined(MACHINE_M54455)
+#include "m54455.h"
 #else
-#error "unknown machine"
+#error "unknown machine!"
 #endif
 
 //#define DBG_AM79
@@ -24,7 +26,7 @@
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_AM79 */
 
-/********************************************************************/
+
 /* Initialize the AM79C874 PHY
  *
  * This function sets up the Auto-Negotiate Advertisement register
@@ -63,6 +65,7 @@ int am79c874_init(uint8_t fec_ch, uint8_t phy_addr, uint8_t speed, uint8_t duple
 		if (!(settings & MII_AM79C874_CR_RESET))
 			break;
 	}
+
 	if (timeout >= FEC_MII_TIMEOUT)
 	{
 		dbg("%s: PHY reset failed\r\n", __FUNCTION__);
@@ -88,11 +91,14 @@ int am79c874_init(uint8_t fec_ch, uint8_t phy_addr, uint8_t speed, uint8_t duple
 
 	if (timeout >= FEC_MII_TIMEOUT)
 	{
-		dbg("%s: PHY Set the default mode\r\n", __FUNCTION__);
+		dbg("%s: Auto-negotiation failed (timeout). Set default mode (100Mbps, full duplex)\r\n", __FUNCTION__);
 
 		/* Set the default mode (Full duplex, 100 Mbps) */
 		if (!fec_mii_write(fec_ch, phy_addr, MII_AM79C874_CR, MII_AM79C874_CR_100MB | MII_AM79C874_CR_DPLX))
+		{
+			dbg("%s: forced setting 100Mbps/full failed.\r\n", __FUNCTION__);
 			return 0;
+		}
 	}
 
 #ifdef DBG_AM79

net/arp.c

@@ -11,9 +11,9 @@
 #include <stdbool.h>
 #include <stddef.h>
 
-#define DBG_ARP
+//#define DBG_ARP
 #ifdef DBG_ARP
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_ARP */
@@ -22,459 +22,469 @@
 
 static uint8_t *arp_find_pair(ARP_INFO *arptab, uint16_t protocol, uint8_t *hwa, uint8_t *pa)
 {
-	/*
-	 * This function searches through the ARP table for the
-	 * specified <protocol,hwa> or <protocol,pa> address pair.
-	 * If it is found, then a a pointer to the non-specified
-	 * address is returned.  Otherwise NULL is returned.
-	 * If you pass in <protocol,pa> then you get <hwa> out.
-	 * If you pass in <protocol,hwa> then you get <pa> out.
-	 */
-	int slot, i, match = false;
-	uint8_t *rvalue;
+    /*
+     * This function searches through the ARP table for the
+     * specified <protocol,hwa> or <protocol,pa> address pair.
+     * If it is found, then a a pointer to the non-specified
+     * address is returned.  Otherwise NULL is returned.
+     * If you pass in <protocol,pa> then you get <hwa> out.
+     * If you pass in <protocol,hwa> then you get <pa> out.
+     */
+    int slot, i, match = false;
+    uint8_t *rvalue;
 
-	if (((hwa == 0) && (pa == 0)) || (arptab == 0))
-		return NULL;
+    if (((hwa == 0) && (pa == 0)) || (arptab == 0))
+        return NULL;
 
-	rvalue = NULL;
+    rvalue = NULL;
 
-	/* 
-	 * Check each protocol address for a match 
-	 */
-	for (slot = 0; slot < arptab->tab_size; slot++)
-	{
-		if ((arptab->table[slot].longevity != ARP_ENTRY_EMPTY) &&
-				(arptab->table[slot].protocol == protocol))
-		{
-			match = true;
-			if (hwa != 0)
-			{
-				/* 
-				 * Check the Hardware Address field 
-				 */
-				rvalue = &arptab->table[slot].pa[0];
-				for (i = 0; i < arptab->table[slot].hwa_size; i++)
-				{
-					if (arptab->table[slot].hwa[i] != hwa[i])
-					{
-						match = false;
-						break;
-					}
-				}
-			}
-			else
-			{
-				/* 
-				 * Check the Protocol Address field 
-				 */
-				rvalue = &arptab->table[slot].hwa[0];
-				for (i = 0; i < arptab->table[slot].pa_size; i++)
-				{
-					if (arptab->table[slot].pa[i] != pa[i])
-					{
-						match = false;
-						break;
-					}
-				}
-			}
-			if (match)
-			{
-				break;
-			}
-		}
-	}
+    /*
+     * Check each protocol address for a match
+     */
+    for (slot = 0; slot < arptab->tab_size; slot++)
+    {
+        if ((arptab->table[slot].longevity != ARP_ENTRY_EMPTY) &&
+                (arptab->table[slot].protocol == protocol))
+        {
+            match = true;
+            if (hwa != 0)
+            {
+                /*
+                 * Check the Hardware Address field
+                 */
+                rvalue = &arptab->table[slot].pa[0];
+                for (i = 0; i < arptab->table[slot].hwa_size; i++)
+                {
+                    if (arptab->table[slot].hwa[i] != hwa[i])
+                    {
+                        match = false;
+                        break;
+                    }
+                }
+            }
+            else
+            {
+                /*
+                 * Check the Protocol Address field
+                 */
+                rvalue = &arptab->table[slot].hwa[0];
+                for (i = 0; i < arptab->table[slot].pa_size; i++)
+                {
+                    if (arptab->table[slot].pa[i] != pa[i])
+                    {
+                        match = false;
+                        break;
+                    }
+                }
+            }
+            if (match)
+            {
+                break;
+            }
+        }
+    }
 
-	if (match)
-		return rvalue;
-	else
-		return NULL;
+    if (match)
+        return rvalue;
+    else
+        return NULL;
 }
 
 void arp_merge(ARP_INFO *arptab, uint16_t protocol, int hwa_size, uint8_t *hwa,
-		int pa_size, uint8_t *pa, int longevity)
+        int pa_size, uint8_t *pa, int longevity)
 {
-	/*
-	 * This function merges an entry into the ARP table.  If
-	 * either piece is NULL, the function exits, otherwise
-	 * the entry is merged or added, provided there is space.
-	 */
-	int i, slot;
-	uint8_t *ta;
+    /*
+     * This function merges an entry into the ARP table.  If
+     * either piece is NULL, the function exits, otherwise
+     * the entry is merged or added, provided there is space.
+     */
+    int i, slot;
+    uint8_t *ta;
 
-	if ((hwa == NULL) || (pa == NULL) || (arptab == NULL) ||
-			((longevity != ARP_ENTRY_TEMP) &&
-			 (longevity != ARP_ENTRY_PERM)))
-	{
-		return;
-	}
+    if ((hwa == NULL) || (pa == NULL) || (arptab == NULL) ||
+            ((longevity != ARP_ENTRY_TEMP) &&
+             (longevity != ARP_ENTRY_PERM)))
+    {
+        return;
+    }
 
-	/* First search ARP table for existing entry */
-	if ((ta = arp_find_pair(arptab,protocol,NULL,pa)) != 0)
-	{
-		/* Update hardware address */
-		for (i = 0; i < hwa_size; i++)
-			ta[i] = hwa[i];
-		return;
-	}
+    /* First search ARP table for existing entry */
+    if ((ta = arp_find_pair(arptab,protocol,NULL,pa)) != 0)
+    {
+        /* Update hardware address */
+        for (i = 0; i < hwa_size; i++)
+            ta[i] = hwa[i];
+        return;
+    }
 
-	/* Next try to find an empty slot */
-	slot = -1;
-	for (i = 0; i < MAX_ARP_ENTRY; i++)
-	{
-		if (arptab->table[i].longevity == ARP_ENTRY_EMPTY)
-		{
-			slot = i;
-			break;
-		}
-	}
+    /* Next try to find an empty slot */
+    slot = -1;
+    for (i = 0; i < MAX_ARP_ENTRY; i++)
+    {
+        if (arptab->table[i].longevity == ARP_ENTRY_EMPTY)
+        {
+            slot = i;
+            break;
+        }
+    }
 
-	/* if no empty slot was found, pick a temp slot */
-	if (slot == -1)
-	{
-		for (i = 0; i < MAX_ARP_ENTRY; i++)
-		{
-			if (arptab->table[i].longevity == ARP_ENTRY_TEMP)
-			{
-				slot = i;
-				break;
-			}
-		}
-	}
+    /* if no empty slot was found, pick a temp slot */
+    if (slot == -1)
+    {
+        for (i = 0; i < MAX_ARP_ENTRY; i++)
+        {
+            if (arptab->table[i].longevity == ARP_ENTRY_TEMP)
+            {
+                slot = i;
+                break;
+            }
+        }
+    }
 
-	/* if after all this, still no slot found, add in last slot */
-	if (slot == -1)
-		slot = (MAX_ARP_ENTRY - 1);
+    /* if after all this, still no slot found, add in last slot */
+    if (slot == -1)
+        slot = (MAX_ARP_ENTRY - 1);
 
-	/* add the entry into the slot */
-	arptab->table[slot].protocol = protocol;
+    /* add the entry into the slot */
+    arptab->table[slot].protocol = protocol;
 
-	arptab->table[slot].hwa_size = (uint8_t) hwa_size;
-	for (i = 0; i < hwa_size; i++)
-		arptab->table[slot].hwa[i] = hwa[i];
+    arptab->table[slot].hwa_size = (uint8_t) hwa_size;
+    for (i = 0; i < hwa_size; i++)
+        arptab->table[slot].hwa[i] = hwa[i];
 
-	arptab->table[slot].pa_size = (uint8_t) pa_size;
-	for (i = 0; i < pa_size; i++)
-		arptab->table[slot].pa[i] = pa[i];
+    arptab->table[slot].pa_size = (uint8_t) pa_size;
+    for (i = 0; i < pa_size; i++)
+        arptab->table[slot].pa[i] = pa[i];
 
-	arptab->table[slot].longevity = longevity;
+    arptab->table[slot].longevity = longevity;
 }
 
 
 void arp_remove(ARP_INFO *arptab, uint16_t protocol, uint8_t *hwa, uint8_t *pa)
 {
-	/*
-	 * This function removes an entry from the ARP table.  The
-	 * ARP table is searched according to the non-NULL address
-	 * that is provided.
-	 */
-	int slot, i, match;
+    /*
+     * This function removes an entry from the ARP table.  The
+     * ARP table is searched according to the non-NULL address
+     * that is provided.
+     */
+    int slot, i, match;
 
-	if (((hwa == 0) && (pa == 0)) || (arptab == 0))
-		return;
+    if (((hwa == 0) && (pa == 0)) || (arptab == 0))
+        return;
 
-	/* check each hardware adress for a match */
-	for (slot = 0; slot < arptab->tab_size; slot++)
-	{
-		if ((arptab->table[slot].longevity != ARP_ENTRY_EMPTY) &&
-				(arptab->table[slot].protocol == protocol))
-		{
-			match = true;
-			if (hwa != 0)
-			{
-				/* Check Hardware Address field */
-				for (i = 0; i < arptab->table[slot].hwa_size; i++)
-				{
-					if (arptab->table[slot].hwa[i] != hwa[i])
-					{
-						match = false;
-						break;
-					}
-				}
-			}
-			else
-			{
-				/* Check Protocol Address field */
-				for (i = 0; i < arptab->table[slot].pa_size; i++)
-				{
-					if (arptab->table[slot].pa[i] != pa[i])
-					{
-						match = false;
-						break;
-					}
-				}
-			}
-			if (match)
-			{
-				for (i = 0; i < arptab->table[slot].hwa_size; i++)
-					arptab->table[slot].hwa[i] = 0;
-				for (i = 0; i < arptab->table[slot].pa_size; i++)
-					arptab->table[slot].pa[i] = 0;
-				arptab->table[slot].longevity = ARP_ENTRY_EMPTY;
-				break;
-			}
-		}
-	}
+    /* check each hardware adress for a match */
+    for (slot = 0; slot < arptab->tab_size; slot++)
+    {
+        if ((arptab->table[slot].longevity != ARP_ENTRY_EMPTY) &&
+                (arptab->table[slot].protocol == protocol))
+        {
+            match = true;
+            if (hwa != 0)
+            {
+                /* Check Hardware Address field */
+                for (i = 0; i < arptab->table[slot].hwa_size; i++)
+                {
+                    if (arptab->table[slot].hwa[i] != hwa[i])
+                    {
+                        match = false;
+                        break;
+                    }
+                }
+            }
+            else
+            {
+                /* Check Protocol Address field */
+                for (i = 0; i < arptab->table[slot].pa_size; i++)
+                {
+                    if (arptab->table[slot].pa[i] != pa[i])
+                    {
+                        match = false;
+                        break;
+                    }
+                }
+            }
+            if (match)
+            {
+                for (i = 0; i < arptab->table[slot].hwa_size; i++)
+                    arptab->table[slot].hwa[i] = 0;
+                for (i = 0; i < arptab->table[slot].pa_size; i++)
+                    arptab->table[slot].pa[i] = 0;
+                arptab->table[slot].longevity = ARP_ENTRY_EMPTY;
+                break;
+            }
+        }
+    }
 }
 
 void arp_request(NIF *nif, uint8_t *pa)
 {
-	/*
-	 * This function broadcasts an ARP request for the protocol
-	 * address "pa"
-	 */
-	uint8_t *addr;
-	NBUF *pNbuf;
-	arp_frame_hdr *arpframe;
-	int i, result;
+    /*
+     * This function broadcasts an ARP request for the protocol
+     * address "pa"
+     */
+    uint8_t *addr;
+    NBUF *pNbuf;
+    arp_frame_hdr *arpframe;
+    int i, result;
 
+    pNbuf = nbuf_alloc();
+    if (pNbuf == NULL)
+    {
+        dbg("could not allocate Tx buffer\n");
+        return;
+    }
 
-	dbg("%s\r\n", __FUNCTION__);
+    arpframe = (arp_frame_hdr *)&pNbuf->data[ARP_HDR_OFFSET];
 
-	pNbuf = nbuf_alloc();
-	if (pNbuf == NULL)
-	{
-		dbg("%s: arp_request couldn't allocate Tx buffer\n", __FUNCTION__);
-		return;
-	}
+    /* Build the ARP request packet */
+    arpframe->ar_hrd = ETHERNET;
+    arpframe->ar_pro = ETH_FRM_IP;
+    arpframe->ar_hln = 6;
+    arpframe->ar_pln = 4;
+    arpframe->opcode = ARP_REQUEST;
 
-	arpframe = (arp_frame_hdr *)&pNbuf->data[ARP_HDR_OFFSET];
+    addr = &nif->hwa[0];
+    for (i = 0; i < 6; i++)
+        arpframe->ar_sha[i] = addr[i];
 
-	/* Build the ARP request packet */
-	arpframe->ar_hrd = ETHERNET;
-	arpframe->ar_pro = ETH_FRM_IP;
-	arpframe->ar_hln = 6;
-	arpframe->ar_pln = 4;
-	arpframe->opcode = ARP_REQUEST;
+    addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
+    for (i = 0; i < 4; i++)
+        arpframe->ar_spa[i] = addr[i];
 
-	addr = &nif->hwa[0];
-	for (i = 0; i < 6; i++)
-		arpframe->ar_sha[i] = addr[i];
+    for (i = 0; i < 6; i++)
+        arpframe->ar_tha[i] = 0x00;
 
-	addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
-	for (i = 0; i < 4; i++)
-		arpframe->ar_spa[i] = addr[i];
+    for (i = 0; i < 4; i++)
+        arpframe->ar_tpa[i] = pa[i];
 
-	for (i = 0; i < 6; i++)
-		arpframe->ar_tha[i] = 0x00;
+    pNbuf->length = ARP_HDR_LEN;
 
-	for (i = 0; i < 4; i++)
-		arpframe->ar_tpa[i] = pa[i];
+    /* Send the ARP request */
+    dbg("sending ARP request\r\n");
+    result = nif->send(nif, nif->broadcast, nif->hwa, ETH_FRM_ARP, pNbuf);
 
-	pNbuf->length = ARP_HDR_LEN;
-
-	/* Send the ARP request */
-	dbg("%s: sending ARP request\r\n", __FUNCTION__);
-	result = nif->send(nif, nif->broadcast, nif->hwa, ETH_FRM_ARP, pNbuf);
-
-	if (result == 0)
-		nbuf_free(pNbuf);
+    if (result == 0)
+        nbuf_free(pNbuf);
 }
 
 static int arp_resolve_pa(NIF *nif, uint16_t protocol, uint8_t *pa, uint8_t **ha)
 {
-	/*
-	 * This function accepts a pointer to a protocol address and
-	 * searches the ARP table for a hardware address match.  If no
-	 * no match found, false is returned.
-	 */
-	ARP_INFO *arptab;
+    /*
+     * This function accepts a pointer to a protocol address and
+     * searches the ARP table for a hardware address match.  If no
+     * no match found, false is returned.
+     */
+    ARP_INFO *arptab;
 
-	if ((pa == NULL) || (nif == NULL) || (protocol == 0))
-		return 0;
+    if ((pa == NULL) || (nif == NULL) || (protocol == 0))
+        return 0;
 
-	arptab = nif_get_protocol_info (nif,ETH_FRM_ARP);
-	*ha = arp_find_pair(arptab,protocol,0,pa);
+    arptab = nif_get_protocol_info (nif,ETH_FRM_ARP);
+    *ha = arp_find_pair(arptab,protocol,0,pa);
 
-	if (*ha == NULL)
-		return 0;
-	else
-		return 1;
+    if (*ha == NULL)
+        return 0;
+    else
+        return 1;
 }
 
 uint8_t *arp_resolve(NIF *nif, uint16_t protocol, uint8_t *pa)
 {
-	int i;
-	uint8_t *hwa;
+    int i;
+    uint8_t *hwa;
 
-	/* 
-	 * Check to see if the necessary MAC-to-IP translation information
-	 * is in table already 
-	 */
-	if (arp_resolve_pa(nif, protocol, pa, &hwa))
-		return hwa;
+    /*
+     * Check to see if the necessary MAC-to-IP translation information
+     * is in table already
+     */
+    if (arp_resolve_pa(nif, protocol, pa, &hwa))
+        return hwa;
 
-	/* 
-	 * Ok, it's not, so we need to try to obtain it by broadcasting
-	 * an ARP request.  Hopefully the desired host is listening and
-	 * will respond with it's MAC address
-	 */
-	for (i = 0; i < 3; i++)
-	{
-		arp_request(nif, pa);
+    /*
+     * Ok, it's not, so we need to try to obtain it by broadcasting
+     * an ARP request.  Hopefully the desired host is listening and
+     * will respond with it's MAC address
+     */
+    for (i = 0; i < 3; i++)
+    {
+        arp_request(nif, pa);
 
-		timer_set_secs(TIMER_NETWORK, ARP_TIMEOUT);
-		while (timer_get_reference(TIMER_NETWORK))
-		{
-			dbg("%s: try to resolve %d.%d.%d.%d\r\n", __FUNCTION__,
-				pa[0], pa[1], pa[2], pa[3], pa[4]);
-			if (arp_resolve_pa(nif, protocol, pa, &hwa))
-			{
-				dbg("%s: resolved to %02x:%02x:%02x:%02x:%02x:%02x.\r\n", __FUNCTION__,
-					hwa[0], hwa[1], hwa[2], hwa[3], hwa[4], hwa[5], hwa[6]);
-					
-				return hwa;
-			}
-		}
-	}
+        timer_set_secs(TIMER_NETWORK, ARP_TIMEOUT);
+        while (timer_get_reference(TIMER_NETWORK))
+        {
+            dbg("try to resolve %d.%d.%d.%d\r\n",
+                pa[0], pa[1], pa[2], pa[3], pa[4]);
+            if (arp_resolve_pa(nif, protocol, pa, &hwa))
+            {
+                dbg("resolved to %02x:%02x:%02x:%02x:%02x:%02x.\r\n",
+                    hwa[0], hwa[1], hwa[2], hwa[3], hwa[4], hwa[5], hwa[6]);
 
-	return NULL;
+                return hwa;
+            }
+        }
+    }
+
+    return NULL;
 }
 
 void arp_init(ARP_INFO *arptab)
 {
-	int slot, i;
+    int slot, i;
 
-	arptab->tab_size = MAX_ARP_ENTRY;
-	for (slot = 0; slot < arptab->tab_size; slot++)
-	{
-		for (i = 0; i < MAX_HWA_SIZE; i++)
-			arptab->table[slot].hwa[i] = 0;
-		for (i = 0; i < MAX_PA_SIZE; i++)
-			arptab->table[slot].pa[i] = 0;
-		arptab->table[slot].longevity = ARP_ENTRY_EMPTY;
-		arptab->table[slot].hwa_size = 0;
-		arptab->table[slot].pa_size = 0;
-	}
+    arptab->tab_size = MAX_ARP_ENTRY;
+    for (slot = 0; slot < arptab->tab_size; slot++)
+    {
+        for (i = 0; i < MAX_HWA_SIZE; i++)
+            arptab->table[slot].hwa[i] = 0;
+        for (i = 0; i < MAX_PA_SIZE; i++)
+            arptab->table[slot].pa[i] = 0;
+        arptab->table[slot].longevity = ARP_ENTRY_EMPTY;
+        arptab->table[slot].hwa_size = 0;
+        arptab->table[slot].pa_size = 0;
+    }
 }
 
 void arp_handler(NIF *nif, NBUF *pNbuf)
 {
-	/* 
-	 * ARP protocol handler 
-	 */
-	uint8_t *addr;
-	ARP_INFO *arptab;
-	int longevity;
-	arp_frame_hdr *rx_arpframe, *tx_arpframe;
+    /*
+     * ARP protocol handler
+     */
+    uint8_t *addr;
+    ARP_INFO *arptab;
+    int longevity;
+    arp_frame_hdr *rx_arpframe, *tx_arpframe;
 
-	arptab = nif_get_protocol_info(nif, ETH_FRM_ARP);
-	rx_arpframe = (arp_frame_hdr *) &pNbuf->data[pNbuf->offset];
+    arptab = nif_get_protocol_info(nif, ETH_FRM_ARP);
+    rx_arpframe = (arp_frame_hdr *) &pNbuf->data[pNbuf->offset];
 
-	/* 
-	 * Check for an appropriate ARP packet 
-	 */
-	if ((pNbuf->length < ARP_HDR_LEN)       ||  
-			(rx_arpframe->ar_hrd != ETHERNET)   ||
-			(rx_arpframe->ar_hln != 6)          ||
-			(rx_arpframe->ar_pro != ETH_FRM_IP) ||
-			(rx_arpframe->ar_pln != 4))
-	{
-		nbuf_free(pNbuf);
-		return;
-	}
+    /*
+     * Check for an appropriate ARP packet
+     */
+    if ((pNbuf->length < ARP_HDR_LEN)       ||
+            (rx_arpframe->ar_hrd != ETHERNET)   ||
+            (rx_arpframe->ar_hln != 6)          ||
+            (rx_arpframe->ar_pro != ETH_FRM_IP) ||
+            (rx_arpframe->ar_pln != 4))
+    {
+        dbg("received packet is not an ARP packet, discard it\r\n");
+        nbuf_free(pNbuf);
+        return;
+    }
 
-	/* 
-	 * Check to see if it was addressed to me - if it was, keep this
-	 * ARP entry in the table permanently; if not, mark it so that it
-	 * can be displaced later if necessary
-	 */
-	addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
-	if ((rx_arpframe->ar_tpa[0] == addr[0]) &&
-			(rx_arpframe->ar_tpa[1] == addr[1]) &&
-			(rx_arpframe->ar_tpa[2] == addr[2]) &&
-			(rx_arpframe->ar_tpa[3] == addr[3]) )
-	{
-		longevity = ARP_ENTRY_PERM;
-	}
-	else 
-		longevity = ARP_ENTRY_TEMP;
+    /*
+     * Check to see if it was addressed to me - if it was, keep this
+     * ARP entry in the table permanently; if not, mark it so that it
+     * can be displaced later if necessary
+     */
+    addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
+    if ((rx_arpframe->ar_tpa[0] == addr[0]) &&
+            (rx_arpframe->ar_tpa[1] == addr[1]) &&
+            (rx_arpframe->ar_tpa[2] == addr[2]) &&
+            (rx_arpframe->ar_tpa[3] == addr[3]) )
+    {
+        dbg("received ARP packet is a permanent one, store it\r\n");
+        longevity = ARP_ENTRY_PERM;
+    }
+    else
+    {
+        dbg("received ARP packet was not addressed to us, keep only temporarily\r\n");
+        longevity = ARP_ENTRY_TEMP;
+    }
 
-	/* 
-	 * Add ARP info into the table
-	 */
-	arp_merge(arptab,
-			rx_arpframe->ar_pro,
-			rx_arpframe->ar_hln,
-			&rx_arpframe->ar_sha[0],
-			rx_arpframe->ar_pln,
-			&rx_arpframe->ar_spa[0],
-			longevity
-			);
+    /*
+     * Add ARP info into the table
+     */
+    arp_merge(arptab,
+            rx_arpframe->ar_pro,
+            rx_arpframe->ar_hln,
+            &rx_arpframe->ar_sha[0],
+            rx_arpframe->ar_pln,
+            &rx_arpframe->ar_spa[0],
+            longevity
+            );
 
-	switch (rx_arpframe->opcode)
-	{
-		case ARP_REQUEST:
-			/* 
-			 * Check to see if request is directed to me
-			 */
-			if ((rx_arpframe->ar_tpa[0] == addr[0]) &&
-					(rx_arpframe->ar_tpa[1] == addr[1]) &&
-					(rx_arpframe->ar_tpa[2] == addr[2]) &&
-					(rx_arpframe->ar_tpa[3] == addr[3]) )
-			{
-				/*
-				 * Reuse the current network buffer to assemble an ARP reply
-				 */
-				tx_arpframe = (arp_frame_hdr *)&pNbuf->data[ARP_HDR_OFFSET];
+    switch (rx_arpframe->opcode)
+    {
+        case ARP_REQUEST:
+            /*
+             * Check to see if request is directed to me
+             */
+            if ((rx_arpframe->ar_tpa[0] == addr[0]) &&
+                    (rx_arpframe->ar_tpa[1] == addr[1]) &&
+                    (rx_arpframe->ar_tpa[2] == addr[2]) &&
+                    (rx_arpframe->ar_tpa[3] == addr[3]) )
+            {
+                dbg("received arp request directed to us, replying\r\n");
+                /*
+                 * Reuse the current network buffer to assemble an ARP reply
+                 */
+                tx_arpframe = (arp_frame_hdr *)&pNbuf->data[ARP_HDR_OFFSET];
 
-				/*
-				 * Build new ARP frame from the received data
-				 */
-				tx_arpframe->ar_hrd = ETHERNET;
-				tx_arpframe->ar_pro = ETH_FRM_IP;
-				tx_arpframe->ar_hln = 6;
-				tx_arpframe->ar_pln = 4;
-				tx_arpframe->opcode = ARP_REPLY;
-				tx_arpframe->ar_tha[0] = rx_arpframe->ar_sha[0];
-				tx_arpframe->ar_tha[1] = rx_arpframe->ar_sha[1];
-				tx_arpframe->ar_tha[2] = rx_arpframe->ar_sha[2];
-				tx_arpframe->ar_tha[3] = rx_arpframe->ar_sha[3];
-				tx_arpframe->ar_tha[4] = rx_arpframe->ar_sha[4];
-				tx_arpframe->ar_tha[5] = rx_arpframe->ar_sha[5];
-				tx_arpframe->ar_tpa[0] = rx_arpframe->ar_spa[0];
-				tx_arpframe->ar_tpa[1] = rx_arpframe->ar_spa[1];
-				tx_arpframe->ar_tpa[2] = rx_arpframe->ar_spa[2];
-				tx_arpframe->ar_tpa[3] = rx_arpframe->ar_spa[3];
+                /*
+                 * Build new ARP frame from the received data
+                 */
+                tx_arpframe->ar_hrd = ETHERNET;
+                tx_arpframe->ar_pro = ETH_FRM_IP;
+                tx_arpframe->ar_hln = 6;
+                tx_arpframe->ar_pln = 4;
+                tx_arpframe->opcode = ARP_REPLY;
+                tx_arpframe->ar_tha[0] = rx_arpframe->ar_sha[0];
+                tx_arpframe->ar_tha[1] = rx_arpframe->ar_sha[1];
+                tx_arpframe->ar_tha[2] = rx_arpframe->ar_sha[2];
+                tx_arpframe->ar_tha[3] = rx_arpframe->ar_sha[3];
+                tx_arpframe->ar_tha[4] = rx_arpframe->ar_sha[4];
+                tx_arpframe->ar_tha[5] = rx_arpframe->ar_sha[5];
+                tx_arpframe->ar_tpa[0] = rx_arpframe->ar_spa[0];
+                tx_arpframe->ar_tpa[1] = rx_arpframe->ar_spa[1];
+                tx_arpframe->ar_tpa[2] = rx_arpframe->ar_spa[2];
+                tx_arpframe->ar_tpa[3] = rx_arpframe->ar_spa[3];
 
-				/* 
-				 * Now copy in the new information 
-				 */
-				addr = &nif->hwa[0];
-				tx_arpframe->ar_sha[0] = addr[0];
-				tx_arpframe->ar_sha[1] = addr[1];
-				tx_arpframe->ar_sha[2] = addr[2];
-				tx_arpframe->ar_sha[3] = addr[3];
-				tx_arpframe->ar_sha[4] = addr[4];
-				tx_arpframe->ar_sha[5] = addr[5];
+                /*
+                 * Now copy in the new information
+                 */
+                addr = &nif->hwa[0];
+                tx_arpframe->ar_sha[0] = addr[0];
+                tx_arpframe->ar_sha[1] = addr[1];
+                tx_arpframe->ar_sha[2] = addr[2];
+                tx_arpframe->ar_sha[3] = addr[3];
+                tx_arpframe->ar_sha[4] = addr[4];
+                tx_arpframe->ar_sha[5] = addr[5];
 
-				addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
-				tx_arpframe->ar_spa[0] = addr[0];
-				tx_arpframe->ar_spa[1] = addr[1];
-				tx_arpframe->ar_spa[2] = addr[2];
-				tx_arpframe->ar_spa[3] = addr[3];
+                addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
+                tx_arpframe->ar_spa[0] = addr[0];
+                tx_arpframe->ar_spa[1] = addr[1];
+                tx_arpframe->ar_spa[2] = addr[2];
+                tx_arpframe->ar_spa[3] = addr[3];
 
-				/* 
-				 * Save the length of my packet in the buffer structure 
-				 */
-				pNbuf->length = ARP_HDR_LEN;
+                /*
+                 * Save the length of my packet in the buffer structure
+                 */
+                pNbuf->length = ARP_HDR_LEN;
 
-				nif->send(nif, 
-						&tx_arpframe->ar_tha[0], 
-						&tx_arpframe->ar_sha[0], 
-						ETH_FRM_ARP, 
-						pNbuf);
-			}
-			else 
-				nbuf_free(pNbuf);
-			break;
-		case ARP_REPLY:
-			/*
-			 * The ARP Reply case is already taken care of
-			 */
-		default:
-			nbuf_free(pNbuf);
-			break;
-	}
+                nif->send(nif,
+                        &tx_arpframe->ar_tha[0],
+                        &tx_arpframe->ar_sha[0],
+                        ETH_FRM_ARP,
+                        pNbuf);
+            }
+            else
+            {
+                dbg("ARP request not addressed to us, discarding\r\n");
+                nbuf_free(pNbuf);
+            }
+            break;
 
-	return;
+        case ARP_REPLY:
+            /*
+             * The ARP Reply case is already taken care of
+             */
+
+            /* missing break is intentional */
+
+        default:
+            nbuf_free(pNbuf);
+            break;
+    }
+
+    return;
 }

net/bcm5222.c

@@ -18,13 +18,15 @@
 #include "firebee.h"
 #elif defined(MACHINE_M5484LITE)
 #include "m5484l.h"
+#elif defined(MACHINE_M54455)
+#include "m54455.h"
 #else
 #error "Unknown machine!"
 #endif
 
 #define DBG_BCM
 #ifdef DBG_BCM
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_BCM */
@@ -53,7 +55,7 @@ int bcm5222_init(uint8_t fec_ch, uint8_t phy_addr, uint8_t speed, uint8_t duplex
 
 	/* Initialize the MII interface */
 	fec_mii_init(fec_ch, SYSCLK / 1000);
-	dbg("%s: PHY reset\r\n", __FUNCTION__);
+    dbg("PHY reset\r\n");
 
 	/* Reset the PHY */
 	if (!fec_mii_write(fec_ch, phy_addr, BCM5222_CTRL, BCM5222_CTRL_RESET | BCM5222_CTRL_ANE))
@@ -69,7 +71,7 @@ int bcm5222_init(uint8_t fec_ch, uint8_t phy_addr, uint8_t speed, uint8_t duplex
 	if(timeout >= FEC_MII_TIMEOUT)
 		return 0;
 
-	dbg("%s: PHY reset OK\r\n", __FUNCTION__);
+    dbg("PHY reset OK\r\n");
 
 	settings = (BCM5222_AN_ADV_NEXT_PAGE | BCM5222_AN_ADV_PAUSE);
 
@@ -87,13 +89,13 @@ int bcm5222_init(uint8_t fec_ch, uint8_t phy_addr, uint8_t speed, uint8_t duplex
 	if (!fec_mii_write(fec_ch, phy_addr, BCM5222_AN_ADV, settings))
 		return 0;
 
-	dbg("%s: PHY Enable Auto-Negotiation\r\n", __FUNCTION__);
+    dbg("PHY Enable Auto-Negotiation\r\n");
 
 	/* Enable Auto-Negotiation */
 	if (!fec_mii_write(fec_ch, phy_addr, BCM5222_CTRL, (BCM5222_CTRL_ANE | BCM5222_CTRL_RESTART_AN)))
 		return 0;
 
-	dbg("%s: PHY Wait for auto-negotiation to complete\r\n", __FUNCTION__);
+    dbg("PHY Wait for auto-negotiation to complete\r\n");
 
 	/* Wait for auto-negotiation to complete */
 	for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
@@ -106,7 +108,7 @@ int bcm5222_init(uint8_t fec_ch, uint8_t phy_addr, uint8_t speed, uint8_t duplex
 
 	if (timeout < FEC_MII_TIMEOUT)
 	{
-		dbg("%s: PHY auto-negociation complete\r\n", __FUNCTION__);
+        dbg("PHY auto-negociation complete\r\n");
 
 		/* Read Auxiliary Control/Status Register */
 		if (!fec_mii_read(fec_ch, phy_addr, BCM5222_ACSR, &settings))
@@ -114,7 +116,7 @@ int bcm5222_init(uint8_t fec_ch, uint8_t phy_addr, uint8_t speed, uint8_t duplex
 	}
 	else
 	{
-		dbg("%s: auto negotiation failed, PHY Set the default mode\r\n", __FUNCTION__);
+        dbg("auto negotiation failed, PHY Set the default mode\r\n");
 
 		/* Set the default mode (Full duplex, 100 Mbps) */
 		if (!fec_mii_write(fec_ch, phy_addr, BCM5222_ACSR, settings = (BCM5222_ACSR_100BTX | BCM5222_ACSR_FDX)))
@@ -127,17 +129,17 @@ int bcm5222_init(uint8_t fec_ch, uint8_t phy_addr, uint8_t speed, uint8_t duplex
 	else
 		fec_duplex(fec_ch, FEC_MII_HALF_DUPLEX);
 
-	dbg("%s: PHY Mode: ", __FUNCTION__);
+    dbg("PHY Mode: ");
 
 	if (settings & BCM5222_ACSR_100BTX)
-		dbg("%s: 100Mbps\r\n", __FUNCTION__);
+        dbg("100Mbps\r\n");
 	else
-		dbg("%s: 10Mbps\r\n", __FUNCTION__);
+        dbg("10Mbps\r\n");
 
 	if (settings & BCM5222_ACSR_FDX)
-		dbg("%s: Full-duplex\r\n", __FUNCTION__);
+        dbg("Full-duplex\r\n");
 	else
-		dbg("%s: Half-duplex\r\n", __FUNCTION__);
+        dbg("Half-duplex\r\n");
 
 	return 1;
 }

net/bootp.c

@@ -13,7 +13,7 @@
 
 #define DBG_BOOTP
 #ifdef DBG_BOOTP
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_BOOTP */
@@ -94,12 +94,14 @@ void bootp_handler(NIF *nif, NBUF *nbuf)
 	struct bootp_packet *rx_p;
 	udp_frame_hdr *udpframe;
 
-	dbg("%s\n", __FUNCTION__);
+    dbg("\r\n");
 
 	rx_p = (struct bootp_packet *) &nbuf->data[nbuf->offset];
 	udpframe = (udp_frame_hdr *) &nbuf->data[nbuf->offset - UDP_HDR_SIZE];
 
-	/* check packet if it is valid and if it is really intended for us */
+    /*
+     * check packet if it is valid and if it is really intended for us
+     */
 
 	if (rx_p->type == BOOTP_TYPE_BOOTREPLY && rx_p->xid == XID)
 	{
@@ -109,6 +111,7 @@ void bootp_handler(NIF *nif, NBUF *nbuf)
 	}
 	else
 	{
+        dbg("received invalid bootp reply\r\n");
 		/* not valid */
 		return;
 	}

net/fec.c

@@ -17,21 +17,24 @@
 #include "bas_string.h"
 #include "bas_printf.h"
 #include "util.h"
+#include "wait.h"
 #include "am79c874.h"
-#include "bcm5222.h"
+//#include "bcm5222.h"
 #include <stdbool.h>
 
 #if defined(MACHINE_FIREBEE)
 #include "firebee.h"
 #elif defined(MACHINE_M5484LITE)
 #include "m5484l.h"
+#elif defined(MACHINE_M54455)
+#include "m54455.h"
 #else
 #error Unknown machine!
 #endif
 
-//#define DBG_FEC
+// #define DBG_FEC
 #ifdef DBG_FEC
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_FEC */
@@ -91,11 +94,12 @@ int fec_mii_write(uint8_t ch, uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
 	 */
 	for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
 	{
+		wait(1);
 		if (MCF_FEC_EIR(ch) & MCF_FEC_EIR_MII)
 			break;
 	}
 
-	if(timeout == FEC_MII_TIMEOUT)
+	if (timeout == FEC_MII_TIMEOUT)
 		return 0;
 
 	/*
@@ -156,11 +160,12 @@ int fec_mii_read(uint8_t ch, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
 	 */
 	for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++)
 	{
+		wait(1);
 		if (MCF_FEC_EIR(ch) & MCF_FEC_EIR_MII)
 			break;
 	}
 
-	if(timeout == FEC_MII_TIMEOUT)
+	if (timeout == FEC_MII_TIMEOUT)
 		return 0;
 
 	/*
@@ -232,33 +237,33 @@ void fec_log_init(uint8_t ch)
  */
 void fec_log_dump(uint8_t ch)
 {
-	dbg("%s: \r\n   FEC%d Log\r\n", __FUNCTION__, ch);
-	dbg("%s:   ---------------\r\n", __FUNCTION__);
-	dbg("%s: Total: %4d\r\n", __FUNCTION__, fec_log[ch].total);
-	dbg("%s: hberr: %4d\r\n", __FUNCTION__, fec_log[ch].hberr);
-	dbg("%s: babr:  %4d\r\n", __FUNCTION__, fec_log[ch].babr);
-	dbg("%s: babt:  %4d\r\n", __FUNCTION__, fec_log[ch].babt);
-	dbg("%s: gra:   %4d\r\n", __FUNCTION__, fec_log[ch].gra);
-	dbg("%s: txf:   %4d\r\n", __FUNCTION__, fec_log[ch].txf);
-	dbg("%s: mii:   %4d\r\n", __FUNCTION__, fec_log[ch].mii);
-	dbg("%s: lc:    %4d\r\n", __FUNCTION__, fec_log[ch].lc);
-	dbg("%s: rl:    %4d\r\n", __FUNCTION__, fec_log[ch].rl);
-	dbg("%s: xfun:  %4d\r\n", __FUNCTION__, fec_log[ch].xfun);
-	dbg("%s: xferr: %4d\r\n", __FUNCTION__, fec_log[ch].xferr);
-	dbg("%s: rferr: %4d\r\n", __FUNCTION__, fec_log[ch].rferr);
-	dbg("%s: dtxf:  %4d\r\n", __FUNCTION__, fec_log[ch].dtxf);
-	dbg("%s: drxf:  %4d\r\n", __FUNCTION__, fec_log[ch].drxf);
-	dbg("%s: \r\nRFSW:\r\n", __FUNCTION__);
-	dbg("%s: inv:   %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_inv);
-	dbg("%s: m:     %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_m);
-	dbg("%s: bc:    %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_bc);
-	dbg("%s: mc:    %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_mc);
-	dbg("%s: lg:    %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_lg);
-	dbg("%s: no:    %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_no);
-	dbg("%s: cr:    %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_cr);
-	dbg("%s: ov:    %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_ov);
-	dbg("%s: tr:    %4d\r\n", __FUNCTION__, fec_log[ch].rfsw_tr);
-	dbg("%s: ---------------\r\n\r\n", __FUNCTION__);
+	dbg("\r\n   FEC%d Log\r\n", __FUNCTION__, ch);
+	dbg("   ---------------\r\n", __FUNCTION__);
+	dbg(" Total: %4d\r\n", fec_log[ch].total);
+	dbg(" hberr: %4d\r\n", fec_log[ch].hberr);
+	dbg(" babr:  %4d\r\n", fec_log[ch].babr);
+	dbg(" babt:  %4d\r\n", fec_log[ch].babt);
+	dbg(" gra:   %4d\r\n", fec_log[ch].gra);
+	dbg(" txf:   %4d\r\n", fec_log[ch].txf);
+	dbg(" mii:   %4d\r\n", fec_log[ch].mii);
+	dbg(" lc:    %4d\r\n", fec_log[ch].lc);
+	dbg(" rl:    %4d\r\n", fec_log[ch].rl);
+	dbg(" xfun:  %4d\r\n", fec_log[ch].xfun);
+	dbg(" xferr: %4d\r\n", fec_log[ch].xferr);
+	dbg(" rferr: %4d\r\n", fec_log[ch].rferr);
+	dbg(" dtxf:  %4d\r\n", fec_log[ch].dtxf);
+	dbg(" drxf:  %4d\r\n", fec_log[ch].drxf);
+	dbg(" \r\nRFSW:\r\n");
+	dbg(" inv:   %4d\r\n", fec_log[ch].rfsw_inv);
+	dbg(" m:     %4d\r\n", fec_log[ch].rfsw_m);
+	dbg(" bc:    %4d\r\n", fec_log[ch].rfsw_bc);
+	dbg(" mc:    %4d\r\n", fec_log[ch].rfsw_mc);
+	dbg(" lg:    %4d\r\n", fec_log[ch].rfsw_lg);
+	dbg(" no:    %4d\r\n", fec_log[ch].rfsw_no);
+	dbg(" cr:    %4d\r\n", fec_log[ch].rfsw_cr);
+	dbg(" ov:    %4d\r\n", fec_log[ch].rfsw_ov);
+	dbg(" tr:    %4d\r\n", fec_log[ch].rfsw_tr);
+	dbg(" ---------------\r\n\r\n");
 }
 
 /*
@@ -481,9 +486,7 @@ void fec_init(uint8_t ch, uint8_t mode, const uint8_t *pa)
 	 */
 	MCF_FEC_RCR(ch) = 0
 		| MCF_FEC_RCR_MAX_FL(ETH_MAX_FRM)
-//#ifdef FEC_PROMISCUOUS
 		| MCF_FEC_RCR_PROM
-//#endif
 		| MCF_FEC_RCR_FCE;
 
 	if (mode == FEC_MODE_MII)
@@ -535,19 +538,26 @@ void fec_rx_start(uint8_t ch, int8_t *rxbd)
 {
 	uint32_t initiator;
 	int channel;
+#ifdef DBG_FEC
 	int res;
+#endif
 
 	/*
 	 * Make the initiator assignment
 	 */
-	res = dma_set_initiator(DMA_FEC_RX(ch));
-	dbg("%s: dma_set_initiator(DMA_FEC_RX(%d)): %d\r\n", __FUNCTION__, ch, res);
+#if defined(DBG_FEC)
+    res =
+#else
+    (void)
+#endif
+    dma_set_initiator(DMA_FEC_RX(ch));
+	dbg("dma_set_initiator(DMA_FEC_RX(%d)): %d\r\n", ch, res);
 
 	/*
 	 * Grab the initiator number
 	 */
 	initiator = dma_get_initiator(DMA_FEC_RX(ch));
-	dbg("%s: dma_get_initiator(DMA_FEC_RX(%d)) = %d\r\n", __FUNCTION__, ch, initiator);
+	dbg("dma_get_initiator(DMA_FEC_RX(%d)) = %d\r\n", ch, initiator);
 
 	/*
 	 * Determine the DMA channel running the task for the
@@ -555,7 +565,7 @@ void fec_rx_start(uint8_t ch, int8_t *rxbd)
 	 */
 	channel = dma_set_channel(DMA_FEC_RX(ch),
 			(ch == 0) ? fec0_rx_frame : fec1_rx_frame);
-	dbg("%s: DMA channel for FEC%1d: %d\r\n", __FUNCTION__, ch, channel);
+	dbg("DMA channel for FEC%1d: %d\r\n", ch, channel);
 
 	/*
 	 * Start the Rx DMA task
@@ -569,18 +579,18 @@ void fec_rx_start(uint8_t ch, int8_t *rxbd)
 			0,
 			initiator,
 			FECRX_DMA_PRI(ch),
-			0 
-			| MCD_FECRX_DMA   
+			0
+			| MCD_FECRX_DMA
 			| MCD_INTERRUPT
-			| MCD_TT_FLAGS_CW 
+			| MCD_TT_FLAGS_CW
 			| MCD_TT_FLAGS_RL
 			| MCD_TT_FLAGS_SP
 			,
-			0 
+			0
 			| MCD_NO_CSUM
 			| MCD_NO_BYTE_SWAP
 			);
-	dbg("%s: Rx DMA task for FEC%1d started\r\n", __FUNCTION__, ch);
+	dbg("Rx DMA task for FEC%1d started\r\n", ch);
 }
 
 /*
@@ -604,13 +614,13 @@ void fec_rx_continue(uint8_t ch)
 	 */
 	channel = dma_get_channel(DMA_FEC_RX(ch));
 
-	dbg("%s: RX DMA channel for FEC%1d is %d\r\n", __FUNCTION__, ch, channel);
+	dbg("RX DMA channel for FEC%1d is %d\r\n", ch, channel);
 
 	/*
 	 * Continue/restart the DMA task
 	 */
 	MCD_continDma(channel);
-	dbg("%s: RX dma on channel %d continued\r\n", __FUNCTION__, channel);
+	dbg("RX dma on channel %d continued\r\n", channel);
 }
 
 /*
@@ -639,9 +649,9 @@ void fec_rx_stop (uint8_t ch)
 	/* Kill the FEC Rx DMA task */
 	MCD_killDma(channel);
 
-	/* 
-	 * Free up the FEC requestor from the software maintained 
-	 * initiator list 
+	/*
+	 * Free up the FEC requestor from the software maintained
+	 * initiator list
 	 */
 	dma_free_initiator(DMA_FEC_RX(ch));
 
@@ -653,7 +663,7 @@ void fec_rx_stop (uint8_t ch)
 }
 
 /*
- * Receive Frame interrupt handler - this handler is called by the 
+ * Receive Frame interrupt handler - this handler is called by the
  * DMA interrupt handler indicating that a packet was successfully
  * transferred out of the Rx FIFO.
  *
@@ -668,7 +678,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
 	NBUF *cur_nbuf, *new_nbuf;
 	int keep;
 
-	dbg("%s: started\r\n", __FUNCTION__);
+	dbg("started\r\n");
 
 	while ((pRxBD = fecbd_rx_alloc(ch)) != NULL)
 	{
@@ -681,7 +691,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
 		 *  - No undefined bits should be set
 		 *  - The upper 5 bits of the length should be cleared
 		 */
-		if (!(pRxBD->status & RX_BD_L) || (pRxBD->status & 0x0608) 
+		if (!(pRxBD->status & RX_BD_L) || (pRxBD->status & 0x0608)
 				|| (pRxBD->length & 0xF800))
 		{
 			keep = false;
@@ -713,8 +723,8 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
 
 		if (keep)
 		{
-			/* 
-			 * Pull the network buffer off the Rx ring queue 
+			/*
+			 * Pull the network buffer off the Rx ring queue
 			 */
 			cur_nbuf = nbuf_remove(NBUF_RX_RING);
 
@@ -730,7 +740,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
 			new_nbuf = nbuf_alloc();
 			if (new_nbuf == NULL)
 			{
-				dbg("%s: nbuf_alloc() failed\n", __FUNCTION__);
+				dbg("nbuf_alloc() failed\n");
 
 				/*
 				 * Can't allocate a new network buffer, so we
@@ -764,7 +774,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
 
 
 			/*
-			 * Let the DMA know that there is a new Rx BD (in case the 
+			 * Let the DMA know that there is a new Rx BD (in case the
 			 * ring was full and the DMA was waiting for an empty one)
 			 */
 			fec_rx_continue(ch);
@@ -775,7 +785,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
 			eth_hdr = (ETH_HDR *) cur_nbuf->data;
 
 			/*
-			 * Pass the received packet up the network stack if the 
+			 * Pass the received packet up the network stack if the
 			 * protocol is supported in our network interface (NIF)
 			 */
 			if (nif_protocol_exist(nif, eth_hdr->type))
@@ -786,12 +796,12 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
 			else
 			{
 				nbuf_free(cur_nbuf);
-				dbg("%s: got unsupported packet %d, trashed it\r\n", __FUNCTION__, eth_hdr->type);
+				dbg("got unsupported packet %d, trashed it\r\n", eth_hdr->type);
 			}
 		}
-		else 
+		else
 		{
-			/* 
+			/*
 			 * This frame isn't a keeper
 			 * Reset the status and length, but don't need to get another
 			 * buffer since we are trashing the data in the current one
@@ -801,7 +811,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
 			pRxBD->status |= RX_BD_E;
 
 			/*
-			 * Move the current buffer from the beginning to the end of the 
+			 * Move the current buffer from the beginning to the end of the
 			 * Rx ring queue
 			 */
 			cur_nbuf = nbuf_remove(NBUF_RX_RING);
@@ -841,22 +851,28 @@ void fec_tx_start(uint8_t ch, int8_t *txbd)
 {
 	uint32_t initiator;
 	int channel;
-	int result;
 	void fec0_tx_frame(void);
 	void fec1_tx_frame(void);
+#ifdef DBG_FEC
 	int res;
+#endif
 
 	/*
 	 * Make the initiator assignment
 	 */
-	res = dma_set_initiator(DMA_FEC_TX(ch));
-	dbg("%s: dma_set_initiator(%d) = %d\r\n", __FUNCTION__, ch, res);
+#ifdef DBG_FEC
+    res =
+#else
+    (void)
+#endif
+    dma_set_initiator(DMA_FEC_TX(ch));
+	dbg("dma_set_initiator(%d) = %d\r\n", ch, res);
 
 	/*
 	 * Grab the initiator number
 	 */
 	initiator = dma_get_initiator(DMA_FEC_TX(ch));
-	dbg("%s: dma_get_initiator(%d) = %d\r\n", __FUNCTION__, ch, initiator);
+	dbg("dma_get_initiator(%d) = %d\r\n", ch, initiator);
 
 
 	/*
@@ -865,7 +881,7 @@ void fec_tx_start(uint8_t ch, int8_t *txbd)
 	 */
 	channel = dma_set_channel(DMA_FEC_TX(ch),
 			(ch == 0) ? fec0_tx_frame : fec1_tx_frame);
-	dbg("%s: dma_set_channel(%d, ...) = %d\r\n", __FUNCTION__, ch, channel);
+	dbg("dma_set_channel(%d, ...) = %d\r\n", ch, channel);
 
 	/*
 	 * Start the Tx DMA task
@@ -879,18 +895,18 @@ void fec_tx_start(uint8_t ch, int8_t *txbd)
 			0,
 			initiator,
 			FECTX_DMA_PRI(ch),
-			0 
-			| MCD_FECTX_DMA   
+			0
+			| MCD_FECTX_DMA
 			| MCD_INTERRUPT
-			| MCD_TT_FLAGS_CW 
+			| MCD_TT_FLAGS_CW
 			| MCD_TT_FLAGS_RL
 			| MCD_TT_FLAGS_SP
 			,
-			0 
+			0
 			| MCD_NO_CSUM
 			| MCD_NO_BYTE_SWAP
 			);
-	dbg("%s: DMA tx task started\r\n", __FUNCTION__);
+	dbg("DMA tx task started\r\n");
 }
 
 /*
@@ -913,14 +929,13 @@ void fec_tx_continue(uint8_t ch)
 	 * selected FEC
 	 */
 	channel = dma_get_channel(DMA_FEC_TX(ch));
-	dbg("%s: dma_get_channel(DMA_FEC_TX(%d)) = %d\r\n",
-			__FUNCTION__, ch, channel);
+	dbg("dma_get_channel(DMA_FEC_TX(%d)) = %d\r\n", ch, channel);
 
 	/*
 	 * Continue/restart the DMA task
 	 */
 	MCD_continDma(channel);
-	dbg("%s: DMA TX task continue\r\n", __FUNCTION__);
+	dbg("DMA TX task continue\r\n");
 }
 
 /*
@@ -967,9 +982,9 @@ void fec_tx_stop(uint8_t ch)
 	/* Kill the FEC Tx DMA task */
 	MCD_killDma(channel);
 
-	/* 
-	 * Free up the FEC requestor from the software maintained 
-	 * initiator list 
+	/*
+	 * Free up the FEC requestor from the software maintained
+	 * initiator list
 	 */
 	dma_free_initiator(DMA_FEC_TX(ch));
 
@@ -981,7 +996,7 @@ void fec_tx_stop(uint8_t ch)
 }
 
 /*
- * Trasmit Frame interrupt handler - this handler is called by the 
+ * Trasmit Frame interrupt handler - this handler is called by the
  * DMA interrupt handler indicating that a packet was successfully
  * transferred to the Tx FIFO.
  *
@@ -994,7 +1009,7 @@ void fec_tx_frame(uint8_t ch)
 	NBUF *pNbuf;
 	bool is_empty = true;
 
-	dbg("%s:\r\n", __FUNCTION__);
+	dbg("\r\n");
 	while ((pTxBD = fecbd_tx_free(ch)) != NULL)
 	{
 		fec_log[ch].dtxf++;
@@ -1008,7 +1023,7 @@ void fec_tx_frame(uint8_t ch)
 		 * Free up the network buffer that was just transmitted
 		 */
 		nbuf_free(pNbuf);
-		dbg("%s: free buffer %p from TX ring\r\n", __FUNCTION__, pNbuf);
+		dbg("free buffer %p from TX ring\r\n", pNbuf);
 
 		/*
 		 * Re-initialize the Tx BD
@@ -1017,9 +1032,9 @@ void fec_tx_frame(uint8_t ch)
 		pTxBD->length = 0;
 		is_empty = false;
 
-	}    
+	}
 	if (is_empty)
-		dbg("%s: transmit queue was empty!\r\n", __FUNCTION__);
+		dbg("transmit queue was empty!\r\n");
 }
 
 void fec0_tx_frame(void)
@@ -1032,7 +1047,6 @@ void fec1_tx_frame(void)
 	fec_tx_frame(1);
 }
 
-/********************************************************************/
 /*
  * Send a packet out the selected FEC
  *
@@ -1042,7 +1056,7 @@ void fec1_tx_frame(void)
  *  dst     Destination MAC Address
  *  src     Source MAC Address
  *  type    Ethernet Frame Type
- *  length  Number of bytes to be transmitted (doesn't include type, 
+ *  length  Number of bytes to be transmitted (doesn't include type,
  *          src, or dest byte count)
  *  pkt     Pointer packet network buffer
  *
@@ -1057,14 +1071,14 @@ int fec_send(uint8_t ch, NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NB
 	/* Check the length */
 	if ((nbuf->length + ETH_HDR_LEN) > ETH_MTU)
 	{
-		dbg("%s: nbuf->length (%d) + ETH_HDR_LEN (%d) exceeds ETH_MTU (%d)\r\n", 
-				__FUNCTION__, nbuf->length, ETH_HDR_LEN, ETH_MTU);
+		dbg("nbuf->length (%d) + ETH_HDR_LEN (%d) exceeds ETH_MTU (%d)\r\n",
+				nbuf->length, ETH_HDR_LEN, ETH_MTU);
 		return 0;
 	}
 
-	/* 
-	 * Copy the destination address, source address, and Ethernet 
-	 * type into the packet 
+	/*
+	 * Copy the destination address, source address, and Ethernet
+	 * type into the packet
 	 */
 	memcpy(&nbuf->data[0],  dst,   6);
 	memcpy(&nbuf->data[6],  src,   6);
@@ -1080,7 +1094,7 @@ int fec_send(uint8_t ch, NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NB
 	 */
 	nbuf_add(NBUF_TX_RING, nbuf);
 
-	/* 
+	/*
 	 * Setup the buffer descriptor for transmission
 	 */
 	pTxBD->data = nbuf->data;
@@ -1106,7 +1120,6 @@ int fec1_send(NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NBUF *nbuf)
 	return fec_send(1, nif, dst, src, type, nbuf);
 }
 
-/********************************************************************/
 /*
  * Enable interrupts on the selected FEC
  *
@@ -1143,7 +1156,7 @@ void fec_irq_enable(uint8_t ch, uint8_t lvl, uint8_t pri)
 		MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK38;
 }
 
-/********************************************************************/
+
 /*
  * Disable interrupts on the selected FEC
  *
@@ -1167,7 +1180,6 @@ void fec_irq_disable(uint8_t ch)
 		MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK38;
 }
 
-/********************************************************************/
 /*
  * FEC interrupt handler
  * All interrupts are multiplexed into a single vector for each
@@ -1190,7 +1202,7 @@ static void fec_irq_handler(uint8_t ch)
 	event = eir & MCF_FEC_EIMR(ch);
 
 	if (event != eir)
-		dbg("%s: pending but not enabled: 0x%08x\r\n", __FUNCTION__, (event ^ eir));
+		dbg("pending but not enabled: 0x%08x\r\n", (event ^ eir));
 
 	/*
 	 * Clear the event(s) in the EIR immediately
@@ -1201,8 +1213,8 @@ static void fec_irq_handler(uint8_t ch)
 	{
 		fec_log[ch].total++;
 		fec_log[ch].rferr++;
-		dbg("%s: RFERR\r\n", __FUNCTION__);
-		dbg("%s: FECRFSR%d = 0x%08x\r\n", __FUNCTION__, ch, MCF_FEC_FECRFSR(ch));
+		dbg("RFERR\r\n");
+		dbg("FECRFSR%d = 0x%08x\r\n", ch, MCF_FEC_FECRFSR(ch));
 		//fec_eth_stop(ch);
 	}
 
@@ -1210,14 +1222,14 @@ static void fec_irq_handler(uint8_t ch)
 	{
 		fec_log[ch].total++;
 		fec_log[ch].xferr++;
-		dbg("%s: XFERR\r\n", __FUNCTION__);
+		dbg("XFERR\r\n");
 	}
 
 	if (event & MCF_FEC_EIR_XFUN)
 	{
 		fec_log[ch].total++;
 		fec_log[ch].xfun++;
-		dbg("%s: XFUN\r\n", __FUNCTION__);
+		dbg("XFUN\r\n");
 		//fec_eth_stop(ch);
 	}
 
@@ -1225,54 +1237,54 @@ static void fec_irq_handler(uint8_t ch)
 	{
 		fec_log[ch].total++;
 		fec_log[ch].rl++;
-		dbg("%s: RL\r\n", __FUNCTION__);
+		dbg("RL\r\n");
 	}
 
 	if (event & MCF_FEC_EIR_LC)
 	{
 		fec_log[ch].total++;
 		fec_log[ch].lc++;
-		dbg("%s: LC\r\n", __FUNCTION__);
+		dbg("LC\r\n");
 	}
 
 	if (event & MCF_FEC_EIR_MII)
 	{
 		fec_log[ch].mii++;
-		dbg("%s: MII\r\n", __FUNCTION__);
+		dbg("MII\r\n");
 	}
 
 	if (event & MCF_FEC_EIR_TXF)
 	{
 		fec_log[ch].txf++;
-		dbg("%s: TXF\r\n", __FUNCTION__);
+		dbg("TXF\r\n");
 		fec_log_dump(0);
 	}
 
 	if (event & MCF_FEC_EIR_GRA)
 	{
 		fec_log[ch].gra++;
-		dbg("%s: GRA\r\n", __FUNCTION__);
+		dbg("GRA\r\n");
 	}
 
 	if (event & MCF_FEC_EIR_BABT)
 	{
 		fec_log[ch].total++;
 		fec_log[ch].babt++;
-		dbg("%s: BABT\r\n", __FUNCTION__);
+		dbg("BABT\r\n");
 	}
 
 	if (event & MCF_FEC_EIR_BABR)
 	{
 		fec_log[ch].total++;
 		fec_log[ch].babr++;
-		dbg("%s: BABR\r\n", __FUNCTION__);
+		dbg("BABR\r\n");
 	}
 
 	if (event & MCF_FEC_EIR_HBERR)
 	{
 		fec_log[ch].total++;
 		fec_log[ch].hberr++;
-		dbg("%s: HBERR\r\n", __FUNCTION__);
+		dbg("HBERR\r\n");
 	}
 }
 
@@ -1282,7 +1294,7 @@ static void fec_irq_handler(uint8_t ch)
  */
 int fec0_interrupt_handler(void* arg1, void* arg2)
 {
-	(void) arg1;
+    (void) arg1;    /* not used */
 	(void) arg2;
 
 	fec_irq_handler(0);
@@ -1292,7 +1304,7 @@ int fec0_interrupt_handler(void* arg1, void* arg2)
 
 int fec1_interrupt_handler(void* arg1, void* arg2)
 {
-	(void) arg1;
+    (void) arg1;    /* not used */
 	(void) arg2;
 
 	fec_irq_handler(1);
@@ -1300,7 +1312,6 @@ int fec1_interrupt_handler(void* arg1, void* arg2)
 	return 1;
 }
 
-/********************************************************************/
 /*
  * Configure the selected Ethernet port and enable all operations
  *
@@ -1342,9 +1353,9 @@ void fec_eth_setup(uint8_t ch, uint8_t trcvr, uint8_t speed, uint8_t duplex, con
 		 */
 #if defined(MACHINE_FIREBEE)
 		if (am79c874_init(0, 0, speed, duplex))
-			dbg("%s: PHY init completed\r\n", __FUNCTION__);
+			dbg("PHY init completed\r\n");
 		else
-			dbg("%s: PHY init failed\r\n", __FUNCTION__);
+			dbg("PHY init failed\r\n");
 #elif defined(MACHINE_M548X)
 		bcm_5222_init(0, 0, speed, duplex);
 #else
@@ -1369,7 +1380,6 @@ void fec_eth_setup(uint8_t ch, uint8_t trcvr, uint8_t speed, uint8_t duplex, con
 	MCF_FEC_ECR(ch) |= MCF_FEC_ECR_ETHER_EN;
 }
 
-/********************************************************************/
 /*
  * Reset the selected Ethernet port
  *
@@ -1381,7 +1391,7 @@ void fec_eth_reset(uint8_t ch)
 	// To do
 }
 
-/********************************************************************/
+
 /*
  * Stop the selected Ethernet port
  *
@@ -1397,7 +1407,7 @@ void fec_eth_stop(uint8_t ch)
 	 */
 	level = set_ipl(7);
 
-	dbg("%s: fec %d stopped\r\n", __FUNCTION__, ch);
+	dbg("fec %d stopped\r\n", ch);
 	/*
 	 * Gracefully disable the receiver and transmitter
 	 */
@@ -1419,12 +1429,12 @@ void fec_eth_stop(uint8_t ch)
 	fec_log_dump(ch);
 #endif
 
-	/* 
+	/*
 	 * Flush the network buffers
 	 */
 	nbuf_flush();
 
-	/* 
+	/*
 	 * Restore interrupt level
 	 */
 	set_ipl(level);

net/fecbd.c

@@ -11,7 +11,7 @@
 #include "bas_printf.h"
 #include <stddef.h>
 
-//#define DBG_FECBD
+#define DBG_FECBD
 #ifdef DBG_FECBD
 #define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
 #else
@@ -31,14 +31,14 @@
  * 
  */
 
-FECBD unaligned_bds[(2 * NRXBD) + (2 * NTXBD) + 1];
+static FECBD unaligned_bds[(2 * NRXBD) + (2 * NTXBD) + 1];
 
 /*
  * These pointers are used to reference into the chunck of data set 
  * aside for buffer descriptors
  */
-FECBD *RxBD;
-FECBD *TxBD;
+static FECBD *RxBD;
+static FECBD *TxBD;
 
 /*
  * Macros to easier access to the BD ring
@@ -65,7 +65,7 @@ void fecbd_init(uint8_t ch)
 	NBUF *nbuf;
 	int i;
 
-	dbg("%s:\r\n", __FUNCTION__);
+    dbg("\r\n");
 
 	/* 
 	 * Align Buffer Descriptors to 4-byte boundary 
@@ -73,7 +73,7 @@ void fecbd_init(uint8_t ch)
 	RxBD = (FECBD *)(((int) unaligned_bds + 3) & 0xFFFFFFFC);
 	TxBD = (FECBD *)((int) RxBD + (sizeof(FECBD) * 2 * NRXBD));
 
-	dbg("%s: initialise RX buffer descriptor ring\r\n", __FUNCTION__);
+    dbg("initialise RX buffer descriptor ring\r\n");
 
 	/* 
 	 * Initialize the Rx Buffer Descriptor ring 
@@ -84,7 +84,7 @@ void fecbd_init(uint8_t ch)
 		nbuf = nbuf_alloc();
 		if (nbuf == NULL)
 		{
-			dbg("%s: could not allocate network buffer\r\n", __FUNCTION__);
+            dbg("could not allocate network buffer\r\n");
 			return;
 		}
 
@@ -102,7 +102,7 @@ void fecbd_init(uint8_t ch)
 	 */
 	RxBD(ch, i - 1).status |= RX_BD_W;
 
-	dbg("%s: initialise TX buffer descriptor ring\r\n", __FUNCTION__);
+    dbg("initialise TX buffer descriptor ring\r\n");
 
 	/* 
 	 * Initialize the Tx Buffer Descriptor ring 

net/ip.c

@@ -6,14 +6,15 @@
  *
  * Modifications:
  */
+#include <bas_types.h>
 #include "net.h"
-#include <stdint.h>
-#include <stddef.h>
+#include "bas_printf.h"
+#include "bas_string.h"
 
 
-//#define IP_DEBUG
+#define IP_DEBUG
 #if defined(IP_DEBUG)
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif
@@ -42,7 +43,7 @@ uint8_t *ip_get_myip(IP_INFO *info)
 	{
 		return (uint8_t *) &info->myip[0];
 	}
-	dbg("%s: info is NULL!\n\t", __FUNCTION__);
+	dbg("info is NULL!\n\t");
 	return 0;
 }
 
@@ -72,9 +73,9 @@ uint8_t *ip_resolve_route(NIF *nif, IP_ADDR_P destip)
 
 	info = nif_get_protocol_info(nif, ETH_FRM_IP);
 
-	if (memcmp(destip, bc) == 0)
+	if (memcmp(destip, bc, 4) == 0)
 	{
-		dbg("%s: destip is broadcast address, no gateway needed\r\n", __FUNCTION__);
+		dbg("destip is broadcast address, no gateway needed\r\n");
 		return destip;
 	}
 
@@ -168,7 +169,7 @@ int ip_send(NIF *nif, uint8_t *dest, uint8_t *src, uint8_t protocol, NBUF *pNbuf
 		route = ip_resolve_route(nif, dest);
 		if (route == NULL)
 		{
-			dbg("%s: Unable to locate %d.%d.%d.%d\r\n", __FUNCTION__,
+			dbg("Unable to locate %d.%d.%d.%d\r\n",
 					dest[0], dest[1], dest[2], dest[3]);
 			return 0;
 		}
@@ -176,9 +177,9 @@ int ip_send(NIF *nif, uint8_t *dest, uint8_t *src, uint8_t protocol, NBUF *pNbuf
 	else
 	{
 		route = bc;
-		dbg("%s: route = broadcast\r\n", __FUNCTION__);
-		dbg("%s: nif = %p\r\n", __FUNCTION__, nif);
-		dbg("%s: nif->send = %p\r\n", __FUNCTION__, nif->send);
+		dbg("route = broadcast\r\n");
+		dbg("nif = %p\r\n", nif);
+		dbg("nif->send = %p\r\n", nif->send);
 	}
 
 	return nif->send(nif, route, &nif->hwa[0], ETH_FRM_IP, pNbuf);
@@ -280,7 +281,7 @@ void ip_handler(NIF *nif, NBUF *pNbuf)
 	 */
 	ip_frame_hdr *ipframe;
 
-	dbg("%s: packet received\r\n", __FUNCTION__);
+	dbg("packet received\r\n");
 
 	ipframe = (ip_frame_hdr *) &pNbuf->data[pNbuf->offset];
 
@@ -289,6 +290,8 @@ void ip_handler(NIF *nif, NBUF *pNbuf)
 	 */
 	if (!validate_ip_hdr(nif, ipframe))
 	{
+		dbg("not a valid IP packet!\r\n");
+
 		nbuf_free(pNbuf);
 		return;
 	}
@@ -308,6 +311,8 @@ void ip_handler(NIF *nif, NBUF *pNbuf)
 			udp_handler(nif,pNbuf);
 			break;
 		default:
+			dbg("no protocol handler registered for protocol %d\r\n",
+					__FUNCTION__, IP_PROTOCOL(ipframe));
 			nbuf_free(pNbuf);
 			break;
 	}

net/nbuf.c

@@ -2,7 +2,7 @@
  * File:    nbuf.c
  * Purpose: Implementation of network buffer scheme.
  *
- * Notes:   
+ * Notes:
  */
 #include "queue.h"
 #include "net.h"
@@ -12,9 +12,9 @@
 #include "bas_printf.h"
 
 
-//#define DBG_NBUF
+#define DBG_NBUF
 #if defined(DBG_NBUF)
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_NBUF */
@@ -42,13 +42,13 @@ int nbuf_init(void)
 	int i;
 	NBUF *nbuf;
 
-	for (i=0; i<NBUF_MAXQ; ++i)
+	for (i = 0; i < NBUF_MAXQ; ++i)
 	{
 		/* Initialize all the queues */
 		queue_init(&nbuf_queue[i]);
 	}
 
-	dbg("%s: Creating %d net buffers of %d bytes\r\n", __FUNCTION__, NBUF_MAX, NBUF_SZ);
+	dbg("Creating %d net buffers of %d bytes\r\n", NBUF_MAX, NBUF_SZ);
 
 	for (i = 0; i < NBUF_MAX; ++i)
 	{
@@ -76,18 +76,19 @@ int nbuf_init(void)
 		queue_add(&nbuf_queue[NBUF_FREE], (QNODE *)nbuf);
 	}
 
-	dbg("%s: NBUF allocation complete\r\n", __FUNCTION__);
+	dbg("NBUF allocation complete\r\n");
 
 	return 0;
 }
 
-/* 
+/*
  * Return all the allocated memory to the heap
  */
 void nbuf_flush(void)
 {
 	NBUF *nbuf;
-	int i, level = set_ipl(7);
+	int i;
+	int level = set_ipl(7);
 	int n = 0;
 
 	for (i = 0; i < NBUF_MAX; ++i)
@@ -104,7 +105,7 @@ void nbuf_flush(void)
 	set_ipl(level);
 }
 
-/* 
+/*
  * Allocate a network buffer from the free list
  *
  * Return Value:
@@ -171,12 +172,13 @@ void nbuf_add(int q, NBUF *nbuf)
 }
 
 /*
- * Put all the network buffers back into the free list 
+ * Put all the network buffers back into the free list
  */
 void nbuf_reset(void)
 {
 	NBUF *nbuf;
-	int i, level = set_ipl(7);
+	int i;
+	int level = set_ipl(7);
 
 	for (i = 1; i < NBUF_MAXQ; ++i)
 	{
@@ -193,7 +195,9 @@ void nbuf_debug_dump(void)
 {
 #ifdef DBG_NBUF
 	NBUF *nbuf;
-	int i, j, level;
+	int i;
+	int j;
+	int level;
 
 	level = set_ipl(7);
 
@@ -204,6 +208,7 @@ void nbuf_debug_dump(void)
 		dbg("--------------------------------------\r\n");
 		j = 0;
 		nbuf = (NBUF *) queue_peek(&nbuf_queue[i]);
+
 		while (nbuf != NULL)
 		{
 			dbg("%d\t0x%08x\t0x%04x\t0x%04x\r\n", j++, nbuf->data,

net/net_timer.c

@@ -5,16 +5,15 @@
  *
  * Notes:
  */
+
 #include "net_timer.h"
-#include <stdint.h>
-#include <stdbool.h>
 #include "bas_printf.h"
 #include "MCF5475.h"
 #include "interrupts.h"
 
 //#define DBG_TMR
 #ifdef DBG_TMR
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_TMR */
@@ -24,6 +23,8 @@
 #include "firebee.h"
 #elif defined(MACHINE_M5484LITE)
 #include "m5484l.h"
+#elif defined(MACHINE_M54455)
+#include "m54455.h"
 #else
 #error unknown machine!
 #endif
@@ -41,12 +42,12 @@ int timer_default_isr(void *not_used, NET_TIMER *t)
 {
 	(void) not_used;
 
-	/* 
-	 * Clear the pending event 
+	/*
+	 * Clear the pending event
 	 */
 	MCF_GPT_GMS(t->ch) = 0;
 
-	dbg("%s: timer isr called for timer channel %d\r\n", __FUNCTION__);
+	dbg("timer isr called for timer channel %d\r\n");
 
 	/*
 	 * Clear the reference - the desired seconds have expired
@@ -88,8 +89,8 @@ bool timer_set_secs(uint8_t ch, uint32_t secs)
 	 */
 	MCF_GPT_GMS(ch) = 0;
 
-	/* 
-	 * Get the timeout in seconds 
+	/*
+	 * Get the timeout in seconds
 	 */
 	timeout = (uint16_t)(secs * net_timer[ch].cnt);
 
@@ -117,22 +118,21 @@ bool timer_set_secs(uint8_t ch, uint32_t secs)
 }
 
 uint32_t timer_get_reference(uint8_t ch)
-{   
+{
 	return (uint32_t) net_timer[ch].reference;
 }
 
 bool timer_init(uint8_t ch, uint8_t lvl, uint8_t pri)
 {
-	/* 
+	/*
 	 * Initialize the timer to expire after one second
-	 * 
+	 *
 	 * This routine should only be called by the project (board) specific
 	 * initialization code.
 	 */
 	if (!((ch <= 3) && (lvl <= 7) && (lvl >= 1) && (pri <= 7)))
 	{
-		dbg("%s: illegal parameters (ch=%d, lvl=%d, pri=%d)\r\n", __FUNCTION__,
-				ch, lvl, pri);
+		dbg("illegal parameters (ch=%d, lvl=%d, pri=%d)\r\n", ch, lvl, pri);
 
 		return false;
 	}
@@ -142,7 +142,7 @@ bool timer_init(uint8_t ch, uint8_t lvl, uint8_t pri)
 	 */
 	MCF_GPT_GMS(ch) = 0;
 
-	/* 
+	/*
 	 * Save off the channel, and interrupt lvl/pri information
 	 */
 	net_timer[ch].ch = ch;
@@ -152,17 +152,16 @@ bool timer_init(uint8_t ch, uint8_t lvl, uint8_t pri)
 	/*
 	 * Register the timer interrupt handler
 	 */
-	if (!isr_register_handler(ISR_DBUG_ISR, 
-				TIMER_VECTOR(ch), 
+	if (!isr_register_handler(TIMER_VECTOR(ch),
 				(int (*)(void *,void *)) timer_default_isr,
-				NULL, 
+				NULL,
 				(void *) &net_timer[ch])
 	   )
 	{
-		dbg("%s: could not register timer interrupt handler\r\n", __FUNCTION__);
+		dbg("could not register timer interrupt handler\r\n");
 		return false;
 	}
-	dbg("%s: timer handler registered\r\n", __FUNCTION__);
+	dbg("timer handler registered\r\n", __FUNCTION__);
 
 	/*
 	 * Calculate the require CNT value to get a 1 second timeout
@@ -172,9 +171,9 @@ bool timer_init(uint8_t ch, uint8_t lvl, uint8_t pri)
 	 * CNT = Clk Freq / PRE
 	 *
 	 * The system clock frequency is defined as SYSTEM_CLOCK and
-	 * is given in MHz. We need to multiple it by 1000000 to get the 
-	 * true value.  If we assume PRE to be the maximum of 0xFFFF, 
-	 * then the CNT value needed to achieve a 1 second timeout is 
+	 * is given in MHz. We need to multiple it by 1000000 to get the
+	 * true value.  If we assume PRE to be the maximum of 0xFFFF,
+	 * then the CNT value needed to achieve a 1 second timeout is
 	 * given by:
 	 *
 	 * CNT = SYSTEM_CLOCK * (1000000/0xFFFF)
@@ -182,10 +181,10 @@ bool timer_init(uint8_t ch, uint8_t lvl, uint8_t pri)
 	net_timer[ch].pre = 0xFFFF;
 	net_timer[ch].cnt = (uint16_t) ((SYSCLK / 1000) * (1000000 / 0xFFFF));
 
-	/* 
-	 * Save off the appropriate mode select register value 
+	/*
+	 * Save off the appropriate mode select register value
 	 */
-	net_timer[ch].gms = (0 
+	net_timer[ch].gms = (0
 			| MCF_GPT_GMS_TMS_GPIO
 			| MCF_GPT_GMS_IEN
 			| MCF_GPT_GMS_SC

net/nif.c

@@ -11,12 +11,9 @@
 #include "bas_types.h"
 #include "bas_printf.h"
 
-#include <stdint.h>
-#include <stdbool.h>
-
 #define DBG_NIF
 #ifdef DBG_NIF
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_NIF */
@@ -56,13 +53,13 @@ void nif_protocol_handler(NIF *nif, uint16_t protocol, NBUF *pNbuf)
 	{
 		if (nif->protocol[index].protocol == protocol)
 		{
-			dbg("%s: call protocol handler for protocol %d at %p\r\n", __FUNCTION__, protocol,
+			dbg("call protocol handler for protocol %d at %p\r\n", protocol,
 						nif->protocol[index].handler);
 			nif->protocol[index].handler(nif,pNbuf);
 			return;
 		}
 	}
-	dbg("%s: no protocol handler found for protocol %d\r\n", __FUNCTION__, protocol);
+	dbg("no protocol handler found for protocol %d\r\n", protocol);
 }
 
 void *nif_get_protocol_info(NIF *nif, uint16_t protocol)
@@ -87,12 +84,12 @@ int nif_bind_protocol(NIF *nif, uint16_t protocol, void (*handler)(NIF *,NBUF *)
 {
 	/*
 	 * This function registers 'protocol' as a supported
-	 * protocol in 'nif'.  
+	 * protocol in 'nif'.
 	 */
 	if (nif->num_protocol < (MAX_SUP_PROTO - 1))
 	{
 		nif->protocol[nif->num_protocol].protocol = protocol;
-		nif->protocol[nif->num_protocol].handler = (void(*)(NIF*,NBUF*))handler;
+		nif->protocol[nif->num_protocol].handler = (void(*)(NIF *, NBUF *)) handler;
 		nif->protocol[nif->num_protocol].info = info;
 		++nif->num_protocol;
 

net/tftp.c

@@ -9,10 +9,7 @@
  *
  */
 
-#include <stdint.h>
-#include <stdbool.h>
-#include <stddef.h>
-
+#include "bas_types.h"
 #include "bas_printf.h"
 #include "bas_string.h"
 #include "net.h"
@@ -103,7 +100,7 @@ static int tftp_ack(uint16_t blocknum)
 		nbuf_free(pNbuf);
 
 	return result;
-} 
+}
 
 static int tftp_error(uint16_t error_code, uint16_t server_port)
 {
@@ -172,7 +169,7 @@ void tftp_handler(NIF *nif, NBUF *pNbuf)
 					cnt = 0;
 				}
 				else
-				{   
+				{
 					/* Check the server's transfer ID */
 					if (tcxn.server_port != UDP_SOURCE(udpframe))
 					{
@@ -274,10 +271,10 @@ void tftp_handler(NIF *nif, NBUF *pNbuf)
 
 void tftp_end(int success)
 {
-	/* 
-	 * Following a successful transfer the caller should pass in 
-	 * true, there should have been no ERROR packets received, and 
-	 * the connection should have been marked as closed by the 
+	/*
+	 * Following a successful transfer the caller should pass in
+	 * true, there should have been no ERROR packets received, and
+	 * the connection should have been marked as closed by the
 	 * tftp_in_char() routine.
 	 */
 	if (success && !tcxn.error && (tcxn.open == false))
@@ -411,10 +408,10 @@ int tftp_write(NIF *nif, char *fn, IP_ADDR_P server, uint32_t begin, uint32_t en
 		/* Attempt to send the packet */
 		for (i = 0; i < 3; ++i)
 		{
-			result = udp_send(tcxn.nif, 
-					tcxn.server_ip, 
-					tcxn.my_port, 
-					tcxn.server_port, 
+			result = udp_send(tcxn.nif,
+					tcxn.server_ip,
+					tcxn.my_port,
+					tcxn.server_port,
 					pNbuf);
 
 			if (result == 1)
@@ -552,8 +549,8 @@ int tftp_in_char(void)
 
 	if (tcxn.next_char != NULL)
 	{
-		/* 
-		 * A buffer is already being worked on - grab next 
+		/*
+		 * A buffer is already being worked on - grab next
 		 * byte from it
 		 */
 		retval = *tcxn.next_char++;
@@ -561,7 +558,7 @@ int tftp_in_char(void)
 		{
 			/* The buffer is depleted; add it back to the free queue */
 			pNbuf = (NBUF *)queue_remove(&tcxn.queue);
-			
+
 			nbuf_free(pNbuf);
 			tcxn.next_char = NULL;
 		}

net/udp.c

@@ -14,7 +14,7 @@
 
 //#define DBG_UDP
 #if defined(DBG_UDP)
-#define dbg(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_UDP */
@@ -39,6 +39,7 @@ void udp_init(void)
 	for (index = 0; index < UDP_MAX_PORTS; ++index)
 	{
 		udp_port_table[index].port = 0;
+		udp_port_table[index].handler = 0;
 	}
 
 	udp_port = DEFAULT_UDP_PORT;    /* next free port */
@@ -88,7 +89,7 @@ static void *udp_port_handler(uint16_t port)
 	{
 		if (udp_port_table[index].port == port)
 		{
-			return (void *)udp_port_table[index].handler;
+			return (void *) udp_port_table[index].handler;
 		}
 	}
 	return NULL;
@@ -111,12 +112,12 @@ int udp_send(NIF *nif, uint8_t *dest, int sport, int dport, NBUF *pNbuf)
 
 	if (nif == NULL)
 	{
-		dbg("%s: nif is NULL\r\n", __FUNCTION__);
+        dbg("nif is NULL\r\n");
 		return 0;
 	}
 
 	/*
-	 * This function takes data and creates a UDP frame and
+	 * This function takes data, creates a UDP frame from it and
 	 * passes it onto the IP layer
 	 */
 	udp_frame_hdr *udpframe;
@@ -140,7 +141,7 @@ int udp_send(NIF *nif, uint8_t *dest, int sport, int dport, NBUF *pNbuf)
 
 	myip = ip_get_myip(nif_get_protocol_info(nif, ETH_FRM_IP));
 
-	dbg("%s: sent UDP request to %d.%d.%d.%d from %d.%d.%d.%d\r\n", __FUNCTION__,
+    dbg("sent UDP request to %d.%d.%d.%d from %d.%d.%d.%d\r\n",
 			dest[0], dest[1], dest[2], dest[3],
 			myip[0], myip[1], myip[2], myip[3]);
 
@@ -158,7 +159,7 @@ void udp_handler(NIF *nif, NBUF *pNbuf)
 
 	udpframe = (udp_frame_hdr *) &pNbuf->data[pNbuf->offset];
 
-	dbg("%s: packet received\r\n", __FUNCTION__);
+    dbg("packet received\r\n",);
 
 	/*
 	 * Adjust the length and valid data offset of the packet we are
@@ -175,7 +176,7 @@ void udp_handler(NIF *nif, NBUF *pNbuf)
 		handler(nif, pNbuf);
 	else
 	{
-		dbg("%s: received UDP packet for non-supported port\n", __FUNCTION__);
+        dbg("received UDP packet for non-supported port\n");
 		nbuf_free(pNbuf);
 	}
 

pci/ehci-hcd.c

@@ -31,8 +31,8 @@
 
 //extern xQueueHandle queue_poll_hub;
 
-#undef DEBUG
-#undef SHOW_INFO
+//#undef DEBUG
+//#undef SHOW_INFO
 
 static char ehci_inited;
 static int rootdev;
@@ -112,7 +112,7 @@ static struct descriptor rom_descriptor = {
 #define ehci_is_TDI()	(0)
 #endif
 
-struct pci_device_id ehci_usb_pci_table[] = 
+struct pci_device_id ehci_usb_pci_table[] =
 {
 	{
 		PCI_VENDOR_ID_NEC,
@@ -208,7 +208,7 @@ static void cache_qh(struct QH *qh, int flush)
 		qh = (struct QH *)(swpl(qh->qh_link) + gehci.dma_offset);
 	}
 	qh = qh_addr(qh);
-	
+
 	/* Save first qTD pointer, needed for invalidating pass on this QH */
 	if (flush)
 	{
@@ -278,7 +278,7 @@ static int ehci_reset(void)
 	if ((gehci.ent->vendor == PCI_VENDOR_ID_NEC) && (gehci.ent->device == PCI_DEVICE_ID_NEC_USB_2))
 	{
 		debug("ehci_reset set 48MHz clock\r\n");
-	 	pci_write_config_longword(gehci.handle, 0xE4, 0x20); // oscillator
+		pci_write_config_longword(gehci.handle, 0xE4, 0x20); // oscillator
 	}
 	cmd = ehci_readl(&gehci.hcor->or_usbcmd);
 	debug("%s cmd: 0x%08x\r\n", __FUNCTION__, cmd);
@@ -291,7 +291,7 @@ static int ehci_reset(void)
 		err("EHCI fail to reset");
 		goto out;
 	}
-	
+
 	if (ehci_is_TDI())
 	{
 		reg_ptr = (uint32_t *)((u8 *)gehci.hcor + USBMODE);
@@ -553,7 +553,7 @@ static int ehci_submit_async(struct usb_device *dev, uint32_t pipe, void *buffer
 	{
 		dev->act_len = 0;
 		debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\r\n",
-		 	dev->devnum, ehci_readl(&gehci.hcor->or_usbsts),
+			dev->devnum, ehci_readl(&gehci.hcor->or_usbsts),
 			ehci_readl(&gehci.hcor->or_portsc[0]), ehci_readl(&gehci.hcor->or_portsc[1]));
 	}
 	return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
@@ -693,7 +693,7 @@ static int ehci_submit_root(struct usb_device *dev, uint32_t pipe, void *buffer,
 
 		case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
 			memset(tmpbuf, 0, 4);
-			reg = ehci_readl(status_reg);	
+			reg = ehci_readl(status_reg);
 
 			if ((reg & EHCI_PS_PR) && (portreset & (1 << swpw(req->index))))
 			{
@@ -705,7 +705,7 @@ static int ehci_submit_root(struct usb_device *dev, uint32_t pipe, void *buffer,
 				if (!ret)
 				{
 					tmpbuf[0] |= USB_PORT_STAT_RESET;
-          			reg = ehci_readl(status_reg);
+					reg = ehci_readl(status_reg);
 				}
 				else
 					err("port(%d) reset error", swpw(req->index) - 1);
@@ -739,7 +739,7 @@ static int ehci_submit_root(struct usb_device *dev, uint32_t pipe, void *buffer,
 				}
 			}
 			else
-				tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;    	
+				tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
 
 			if (reg & EHCI_PS_CSC)
 				tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
@@ -886,7 +886,7 @@ static int hc_interrupt(struct ehci *ehci)
 			}
 			i--;
 		}
-	} 
+	}
 	ehci_writel(&ehci->hcor->or_usbsts, status);
 
 	return(1); /* interrupt was from this card */
@@ -950,7 +950,7 @@ int ehci_usb_lowlevel_init(long handle, const struct pci_device_id *ent, void **
 		gehci.ent = ent;
 	}
 	else if (!gehci.handle) /* for restart USB cmd */
-		return(-1);	
+		return(-1);
 
 	gehci.qh_list_unaligned = (struct QH *)driver_mem_alloc(sizeof(struct QH) + 32);
 	if (gehci.qh_list_unaligned == NULL)
@@ -983,7 +983,7 @@ int ehci_usb_lowlevel_init(long handle, const struct pci_device_id *ent, void **
 			return(-1);
 		}
 		gehci.td[i] = (struct qTD *)(((uint32_t)gehci.td_unaligned[i] + 31) & ~31);
-		memset(gehci.td[i], 0, sizeof(struct qTD));	
+		memset(gehci.td[i], 0, sizeof(struct qTD));
 	}
 
 	gehci.descriptor = (struct descriptor *)driver_mem_alloc(sizeof(struct descriptor));
@@ -1118,7 +1118,7 @@ int ehci_usb_lowlevel_stop(void *priv)
 	ehci_writel(&gehci.hcor->or_configflag, 0);
 
 	/* unblock posted write */
-	cmd = ehci_readl(&gehci.hcor->or_usbcmd);		
+	cmd = ehci_readl(&gehci.hcor->or_usbcmd);
 	ehci_reset();
 	hc_free_buffers(&gehci);
 	ehci_inited = 0;

pci/pci.c

@@ -26,7 +26,7 @@
 
 #include <MCF5475.h>
 #include "pci.h"
-#include "stdint.h"
+#include "bas_types.h"
 #include "bas_printf.h"
 #include "bas_string.h"
 #include "util.h"
@@ -35,7 +35,7 @@
 
 //#define DEBUG_PCI
 #ifdef DEBUG_PCI
-#define dbg(format, arg...) do { xprintf("DEBUG: " format "", ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DEBUG_PCI */
@@ -76,7 +76,7 @@ static int num_pci_classes = sizeof(pci_classes) / sizeof(struct pci_class);
 #define NUM_CARDS		10
 #define NUM_RESOURCES	7
 /* holds the handle of a card at position = array index */
-static int32_t handles[NUM_CARDS];	
+static int32_t handles[NUM_CARDS];
 
 /* holds the interrupt handler addresses (see pci_hook_interrupt() and pci_unhook_interrupt()) of the PCI cards */
 struct pci_interrupt
@@ -89,7 +89,7 @@ struct pci_interrupt
 static struct pci_interrupt interrupts[MAX_INTERRUPTS];
 
 /* holds the card's resource descriptors; filled in pci_device_config() */
-static struct pci_rd resource_descriptors[NUM_CARDS][NUM_RESOURCES]; 
+static struct pci_rd resource_descriptors[NUM_CARDS][NUM_RESOURCES];
 
 
 __attribute__((aligned(16))) void chip_errata_135(void)
@@ -147,13 +147,20 @@ __attribute__((interrupt)) void pci_interrupt(void)
 	dbg("PCI interrupt\r\n");
 }
 
+/*
+ * Although this pragma stuff should work according to the GCC docs, it doesn't seem to
+ * with m68k-atari-mint-gcc. At least not currently.
+ * I nevertheless keep it here for future reference
+ */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wunused-function"
 static int32_t pci_get_interrupt_cause(int32_t *handles)
 {
 	int32_t handle;
 
 	while ((handle = *handles++) != -1)
 	{
-		uint32_t csr = swpl(pci_read_config_longword(handle, PCICSR)); 
+		uint32_t csr = swpl(pci_read_config_longword(handle, PCICSR));
 
 		if ((csr & (1 << 3)) && (csr & !(csr & (1 << 10))))
 		{
@@ -162,7 +169,7 @@ static int32_t pci_get_interrupt_cause(int32_t *handles)
 			return handle;
 		}
 	}
-	dbg("%s: no interrupt cause found\r\n", __FUNCTION__);
+	dbg("%s: no interrupt cause found\r\n");
 	return -1;
 }
 
@@ -170,6 +177,7 @@ static int32_t pci_call_interrupt_chain(int32_t handle, int32_t data)
 {
 	return data;	/* unmodified - means: not handled */
 }
+#pragma GCC diagnostic pop
 
 #ifdef MACHINE_M5484LITE
 /*
@@ -179,7 +187,7 @@ static int32_t pci_call_interrupt_chain(int32_t handle, int32_t data)
 void irq5_handler(void)
 {
 	int32_t handle;
-	int32_t value;
+	int32_t value = 0;
 	int32_t newvalue;
 
 	MCF_EPORT_EPFR |= (1 << 5);		/* clear interrupt from edge port */
@@ -189,7 +197,7 @@ void irq5_handler(void)
 		newvalue = pci_call_interrupt_chain(handle, value);
 		if (newvalue == value)
 		{
-			dbg("%s: interrupt not handled!\r\n", __FUNCTION__);
+			dbg("%s: interrupt not handled!\r\n");
 		}
 	}
 }
@@ -201,7 +209,7 @@ void irq5_handler(void)
 void irq7_handler(void)
 {
 	int32_t handle;
-	int32_t value;
+	int32_t value = 0;
 	int32_t newvalue;
 
 	MCF_EPORT_EPFR |= (1 << 7);
@@ -211,7 +219,7 @@ void irq7_handler(void)
 		newvalue = pci_call_interrupt_chain(handle, value);
 		if (newvalue == value)
 		{
-			dbg("%s: interrupt not handled!\r\n", __FUNCTION__);
+			dbg("%s: interrupt not handled!\r\n");
 		}
 	}
 }
@@ -266,7 +274,7 @@ uint32_t pci_read_config_longword(int32_t handle, int offset)
 			MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) |	/* device number, devices 0 - 9 are reserved */
 			MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |	/* function number */
 			MCF_PCI_PCICAR_DWORD(offset / 4);
-	
+
 	__asm__ __volatile__("nop" ::: "memory");				/* this is what the Linux BSP does */
 
 	pci_config_wait();
@@ -292,7 +300,7 @@ uint16_t pci_read_config_word(int32_t handle, int offset)
 			MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) |
 			MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |
 			MCF_PCI_PCICAR_DWORD(offset / 4);
-	
+
 	__asm__ __volatile("nop" ::: "memory");			/* this is what Linux BSP does */
 
 	value = * (volatile uint16_t *) PCI_IO_OFFSET + (offset & 2);
@@ -315,7 +323,7 @@ uint8_t pci_read_config_byte(int32_t handle, int offset)
 		MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) |		/* device number, devices 0 - 9 are reserved */
 		MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |	/* function number */
 		MCF_PCI_PCICAR_DWORD(offset / 4);
-	
+
 	__asm__ __volatile__("nop" ::: "memory");
 
 	value = * (volatile uint8_t *) (PCI_IO_OFFSET + (offset & 3));
@@ -366,11 +374,11 @@ int32_t pci_write_config_word(int32_t handle, int offset, uint16_t value)
 			MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) |
 			MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |
 			MCF_PCI_PCICAR_DWORD(offset / 4);
-	
+
 	__asm__ __volatile__("tpf" ::: "memory");
 
 	* (volatile uint16_t *) (PCI_IO_OFFSET + (offset & 2)) = value;
-	
+
 	__asm__ __volatile__("tpf" ::: "memory");
 
 	/* finish configuration space access cycle */
@@ -391,7 +399,7 @@ int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value)
 			MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) |
 			MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |
 			MCF_PCI_PCICAR_DWORD(offset / 4);
-	
+
 	__asm__ __volatile__("tpf" ::: "memory");
 
 	* (volatile uint8_t *) (PCI_IO_OFFSET + (offset & 3)) = value;
@@ -440,7 +448,7 @@ int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index)
 	uint16_t n = 0;
 	int32_t handle;
 
-	for (bus = 0; bus < 2; bus++)
+	for (bus = 0; bus < 1; bus++)
 	{
 		for (device = 10; device < 31; device++)
 		{
@@ -476,7 +484,7 @@ int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index)
 						value = pci_read_config_longword(handle, PCIIDR);
 						if (value != 0xFFFFFFFF)	/* device found */
 						{
-							if (vendor_id == 0xffff || 
+							if (vendor_id == 0xffff ||
 								(PCI_VENDOR_ID(value) == vendor_id && PCI_DEVICE_ID(value) == device_id))
 							{
 								if (n == index)
@@ -519,11 +527,11 @@ int32_t pci_find_classcode(uint32_t classcode, int index)
 			handle = PCI_HANDLE(bus, device, 0);
 
 			value = pci_read_config_longword(handle, PCIIDR);
-			
+
 			if (value != 0xffffffff)	/* device found */
 			{
 				value = pci_read_config_longword(handle, PCICCR);
-			
+
 				if ((classcode & (1 << 26) ? ((PCI_CLASS_CODE(value) == (classcode & 0xff))) : true) &&
 					(classcode & (1 << 25) ? ((PCI_SUBCLASS(value) == ((classcode & 0xff00) >> 8))) : true) &&
 					(classcode & (1 << 24) ? ((PCI_PROG_IF(value) == ((classcode & 0xff0000) >> 16))) : true))
@@ -536,10 +544,10 @@ int32_t pci_find_classcode(uint32_t classcode, int index)
 				}
 
 				/*
-			 	* there is a device at this position, but not the one we are looking for.
-			 	* Check to see if it is a multi-function device. We need to look "behind" it
-			 	* for the other functions in that case.
-			 	*/
+				* there is a device at this position, but not the one we are looking for.
+				* Check to see if it is a multi-function device. We need to look "behind" it
+				* for the other functions in that case.
+				*/
 				if ((htr = pci_read_config_byte(handle, PCIHTR)) & 0x80)
 				{
 					/* yes, this is a multi-function device, look for more functions */
@@ -587,7 +595,168 @@ int32_t pci_unhook_interrupt(int32_t handle)
 	return PCI_SUCCESSFUL;
 }
 
+/*
+ * Not implemented PCI_BIOS functions
+ */
 
+uint8_t pci_fast_read_config_byte(int32_t handle, uint16_t reg)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+uint16_t pci_fast_read_config_word(int32_t handle, uint16_t reg)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+uint32_t pci_fast_read_config_longword(int32_t handle, uint16_t reg)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_special_cycle(uint16_t bus, uint32_t data)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_get_routing(int32_t handle)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_set_interrupt(int32_t handle)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_get_card_used(int32_t handle, uint32_t *address)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_set_card_used(int32_t handle, uint32_t *callback)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+uint8_t pci_fast_read_mem_byte(int32_t handle, uint32_t offset)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+uint16_t pci_fast_read_mem_word(int32_t handle, uint32_t offset)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+uint32_t pci_fast_read_mem_longword(int32_t handle, uint32_t offset)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_write_mem_word(int32_t handle, uint32_t offset, uint16_t val)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_read_io_word(int32_t handle, uint32_t offset, uint16_t *address)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+uint8_t pci_fast_read_io_byte(int32_t handle, uint32_t offset)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+uint16_t pci_fast_read_io_word(int32_t handle, uint32_t offset)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+uint32_t pci_fast_read_io_longword(int32_t handle, uint32_t offset)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_write_io_byte(int32_t handle, uint32_t offset, uint16_t val)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_write_io_word(int32_t handle, uint32_t offset, uint16_t val)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_write_io_longword(int32_t handle, uint32_t offset, uint32_t val)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_get_machine_id(void)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_get_pagesize(void)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+int32_t pci_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
+
+int32_t pci_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer)
+{
+	return PCI_FUNC_NOT_SUPPORTED;
+}
 
 /*
  * pci_device_config()
@@ -607,6 +776,12 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
 	static uint32_t io_address = PCI_IO_OFFSET;
 	uint16_t cr;
 
+	/*
+	 * should make compiler happy (these are used only in debug builds)
+	 */
+	(void) value;
+	(void) il;
+
 	/* determine pci handle from bus, device + function number */
 	handle = PCI_HANDLE(bus, device, function);
 
@@ -622,7 +797,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
 	/*
 	 * disable device
 	 */
-	
+
 	cr = swpw(pci_read_config_word(handle, PCICSR));
 	cr &= ~3;	/* disable device response to address */
 	pci_write_config_word(handle, PCICSR, swpw(cr));
@@ -647,9 +822,9 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
 			/*
 			 * resource descriptor for this device
 			 */
-			struct pci_rd *rd = &descriptors[barnum]; 
+			struct pci_rd *rd = &descriptors[barnum];
 
-			dbg("%s: address = %08x\r\n", __FUNCTION__, address);
+			dbg("%s: address = %08x\r\n", address);
 			if (IS_PCI_MEM_BAR(address))
 			{
 				/* adjust base address to card's alignment requirements */
@@ -664,7 +839,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
 
 				/* read it back, just to be sure */
 				value = swpl(pci_read_config_longword(handle, PCIBAR0 + i)) & ~1;
-				
+
 				dbg("set PCIBAR%d on device 0x%02x to 0x%08x\r\n",
 						i / 4, handle, value);
 
@@ -673,7 +848,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
 				rd->flags = 0 | FLG_32BIT | FLG_16BIT | FLG_8BIT | 2; /* little endian, lane swapped */
 				rd->start = address;
 				rd->length = size;
-				rd->offset = 0; 
+				rd->offset = 0;
 				rd->dmaoffset = 0;
 
 				/* adjust memory adress for next turn */
@@ -708,7 +883,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
 				cr |= 1;
 
 				barnum++;
-			}		
+			}
 		}
 	}
 
@@ -728,7 +903,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
 	address = swpl(pci_read_config_longword(handle, PCIERBAR));
 	if (address & 1)
 	{
-		struct pci_rd *rd = &descriptors[barnum]; 
+		struct pci_rd *rd = &descriptors[barnum];
 		int size = ~(address & ~0x7ff);
 
 		/* expansion ROM active and mapped */
@@ -738,10 +913,10 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
 
 		/* write it to PCIERBAR and enable ROM */
 		pci_write_config_longword(handle, PCIERBAR, swpl(address | 1));
-		dbg("%s: set PCIERBAR on device 0x%02x to 0x%08x\r\n", __FUNCTION__, handle, address | 1);
+		dbg("%s: set PCIERBAR on device 0x%02x to 0x%08x\r\n", handle, address | 1);
 
 		/* read value back just to be sure */
-		dbg("%s: PCIERBAR = %p\r\n", __FUNCTION__, swpl(pci_read_config_longword(handle, PCIERBAR)));
+		dbg("%s: PCIERBAR = %p\r\n", swpl(pci_read_config_longword(handle, PCIERBAR)));
 
 
 		rd->next = sizeof(struct pci_rd);
@@ -762,11 +937,11 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
 	/* check if device requests an interrupt */
 	il = pci_read_config_byte(handle, PCIIPR);
 	dbg("device requests interrupts on interrupt pin %d\r\n", il);
-			
+
 	/* if so, register interrupts */
-	
+
 	/* TODO: register interrupts here */
-	
+
 	/*
 	 * enable device memory or I/O access
 	 */
@@ -874,7 +1049,7 @@ void init_xlbus_arbiter(void)
 	{
 		MCF_XLB_XARB_CFG = MCF_XLB_XARB_CFG_BA |
 			MCF_XLB_XARB_CFG_DT |
-			MCF_XLB_XARB_CFG_AT; 
+			MCF_XLB_XARB_CFG_AT;
 	}
 
 	MCF_XLB_XARB_ADRTO = 0x1fffff;
@@ -888,7 +1063,7 @@ void init_xlbus_arbiter(void)
 	 * M2 = Multichannel DMA
 	 * M3 = PCI target interface
 	 */
-	
+
 	MCF_XLB_XARB_PRIEN = MCF_XLB_XARB_PRIEN_M0 |	/* activate programmed priority for Coldfire core */
 					MCF_XLB_XARB_PRIEN_M2 |			/* activate programmed priority for Multichannel DMA */
 					MCF_XLB_XARB_PRIEN_M3;			/* activate programmed priority for PCI target interface */
@@ -920,9 +1095,9 @@ void init_pci(void)
 	 * setup the PCI arbiter
 	 */
 	MCF_PCIARB_PACR = MCF_PCIARB_PACR_INTMPRI	/* internal master priority: high */
-       | MCF_PCIARB_PACR_EXTMPRI(0xf)			/* external master priority: high */
-       | MCF_PCIARB_PACR_INTMINTEN				/* enable "internal master broken" interrupt */
-       | MCF_PCIARB_PACR_EXTMINTEN(0x0f);		/* enable "external master broken" interrupt */
+	   | MCF_PCIARB_PACR_EXTMPRI(0xf)			/* external master priority: high */
+	   | MCF_PCIARB_PACR_INTMINTEN				/* enable "internal master broken" interrupt */
+	   | MCF_PCIARB_PACR_EXTMINTEN(0x0f);		/* enable "external master broken" interrupt */
 
 #ifdef _NOT_USED_	/* since this is already done in sysinit.c */
 #if MACHINE_FIREBEE
@@ -939,7 +1114,7 @@ void init_pci(void)
 		MCF_PCI_PCISCR_M |		/* mem access enable */
 		MCF_PCI_PCISCR_MA |		/* clear master abort error */
 		MCF_PCI_PCISCR_MW;		/* memory write and invalidate enabled */
-		
+
 
 	/* Setup burst parameters */
 	MCF_PCI_PCICR1 = MCF_PCI_PCICR1_CACHELINESIZE(8) |
@@ -956,14 +1131,14 @@ void init_pci(void)
 		MCF_PCI_PCIICR_IAE; 				/* initiator abort enable */
 #endif /* NOT_USED */
 	MCF_PCI_PCIICR = 0;						/* this is what Linux does */
-	
+
 	MCF_PCI_PCIGSCR |= MCF_PCI_PCIGSCR_SEE;	/* system error interrupt enable */
 
 	/* Configure Initiator Windows */
 
 	/* initiator window 0 base / translation adress register */
 	MCF_PCI_PCIIW0BTAR = (PCI_MEMORY_OFFSET | (((PCI_MEMORY_SIZE - 1) >> 8) & 0xffff0000))
-						  | ((PCI_MEMORY_OFFSET >> 16) & 0xff00); 
+						  | ((PCI_MEMORY_OFFSET >> 16) & 0xff00);
 
 	dbg("PCIIW0BTAR=0x%08x\r\n", MCF_PCI_PCIIW0BTAR);
 
@@ -1055,4 +1230,4 @@ void pci_print_device_config(int32_t handle)
 }
 #endif /* DEBUG_PCI */
 
-	
+

pci/pci_wrappers.S

@@ -0,0 +1,469 @@
+/*
+ * pci.S
+ *
+ * Purpose:		PCI configuration for the Coldfire builtin PCI bridge.
+ *
+ * Notes:
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 08.05.2014
+ *      Author: David Galvez
+ */
+
+.global _wrapper_find_pci_device
+.global _wrapper_find_pci_classcode
+
+.global _wrapper_read_config_longword
+.global _wrapper_read_config_word
+.global _wrapper_read_config_byte
+
+.global _wrapper_fast_read_config_byte
+.global _wrapper_fast_read_config_word
+.global _wrapper_fast_read_config_longword
+
+.global _wrapper_write_config_longword
+.global _wrapper_write_config_word
+.global _wrapper_write_config_byte
+
+.global _wrapper_get_resource
+.global _wrapper_hook_interrupt
+.global _wrapper_unhook_interrupt
+
+.global _wrapper_special_cycle
+.global _wrapper_get_routing
+.global _wrapper_set_interrupt
+.global _wrapper_get_resource
+.global _wrapper_get_card_used
+.global _wrapper_set_card_used
+
+.global _wrapper_read_mem_byte
+.global _wrapper_read_mem_word
+.global _wrapper_read_mem_longword
+
+.global _wrapper_fast_read_mem_byte
+.global _wrapper_fast_read_mem_word
+.global _wrapper_fast_read_mem_longword
+
+.global _wrapper_write_mem_byte
+.global _wrapper_write_mem_word
+.global _wrapper_write_mem_longword
+
+.global _wrapper_read_io_byte
+.global _wrapper_read_io_word
+.global _wrapper_read_io_longword
+
+.global _wrapper_fast_read_io_byte
+.global _wrapper_fast_read_io_word
+.global _wrapper_fast_read_io_longword
+
+.global _wrapper_write_io_byte
+.global _wrapper_write_io_word
+.global _wrapper_write_io_longword
+
+.global _wrapper_get_machine_id
+.global _wrapper_get_pagesize
+
+.global _wrapper_virt_to_bus
+.global _wrapper_bus_to_virt
+.global _wrapper_virt_to_phys
+.global _wrapper_phys_to_virt
+
+
+_wrapper_find_pci_device:
+	move.l D1,-(SP)			// index
+	move.l D0,-(SP)			// Vendor ID
+	move.l #16,D1
+	lsr.l D1,D0
+	move.l D0,-(SP)			// Device ID
+	jsr _pci_find_device
+	add.l #12,SP
+	rts
+
+_wrapper_find_pci_classcode:
+	move.l D1,-(SP)			// index
+	move.l D0,-(SP)			// ID
+	jsr _pci_find_classcode
+	addq.l #8,SP
+	rts
+
+_wrapper_read_config_byte:
+	move.l A0,-(SP)			// pointer to space for read data
+	move.l D1,-(SP)			// PCI register
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_config_byte
+	move.l 8(SP),A0			// PCI_BIOS expects value in memory
+	move.l D0,(A0)
+	add.l #12,SP
+	move.l #0,D0
+	rts
+
+_wrapper_read_config_word:
+	move.l A0,-(SP)			// pointer to space for read data
+	move.l D1,-(SP)			// PCI register
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_config_word
+	move.l 8(SP),A0			// little to big endian
+	move.l D0,(A0)
+	mvz.b 1(A0),D0
+	lsl.l #8,D0
+	move.b (A0),D0
+	move.l D0,(A0)			// PCI_BIOS expects value in memory, not in D0
+	add.l #12,SP
+	move.l #0,D0
+	rts
+
+_wrapper_read_config_longword:
+	move.l A0,-(SP)			// pointer to space for read data
+	move.l D1,-(SP)			// PCI register
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_config_longword
+	move.l 8(SP),A0			// little to big endian
+	move.l D0,(A0)
+	mvz.b 3(A0),D0
+	lsl.l #8,D0
+	move.b 2(A0),D0
+	lsl.l #8,D0
+	move.b 1(A0),D0
+	lsl.l #8,D0
+	move.b (A0),D0
+	move.l D0,(A0)			// PCI_BIOS expects value in memory, not in D0
+	add.l #12,SP
+	move.l #0,D0
+	rts
+
+/* Not implemented */
+_wrapper_fast_read_config_byte:
+	move.l D1,-(SP)			// PCI register
+	move.l D0,-(SP)			// handle
+	jsr _pci_fast_read_config_byte
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_fast_read_config_word:
+	move.l D1,-(SP)			// PCI register
+	move.l D0,-(SP)			// handle
+	jsr _pci_fast_read_config_word
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_fast_read_config_longword:
+	move.l D1,-(SP)			// PCI register
+	move.l D0,-(SP)			// handle
+	jsr _pci_fast_read_config_longword
+	addq.l #8,SP
+	rts
+
+_wrapper_write_config_byte:
+	move.l D2,-(SP)			// data to write
+	move.l D1,-(SP)			// PCI register
+	move.l D0,-(SP)			// handle
+	jsr _pci_write_config_byte
+	add.l #12,SP
+	rts
+
+_wrapper_write_config_word:
+	move.l D0,-(SP)			// make data little endian
+	moveq #0,D1
+	move.w D2,D1
+	lsr.l #8,D1
+	asl.l #8,D2
+	or.l D1,D2
+	move.l (SP)+,D0
+	move.l D2,-(SP)			// data to write
+	move.l D1,-(SP)			// PCI register
+	move.l D0,-(SP)			// handle
+	jsr _pci_write_config_word
+	add.l #12,SP
+	rts
+
+_wrapper_write_config_longword:
+	move.l D0,-(SP)
+	move.l D2,D0			// make data little endian
+	lsr.l #8,D0
+	asl.l #8,D2
+	and.l #0x00FF00FF,D0
+	and.l #0xFF00FF00,D2
+	or.l D0,D2
+	swap D2
+	move.l (SP)+,D0
+	move.l D2,-(SP)			// data to write
+	move.l D1,-(SP)			// PCI register
+	move.l D0,-(SP)			// handle
+	jsr _pci_write_config_longword
+	add.l #12,SP
+	rts
+
+_wrapper_hook_interrupt:
+	move.l A1,-(SP)			// parameter for interrupt handler
+	move.l A0,-(SP)			// pointer to interrupt handler
+	move.l D0,-(SP)			// handle
+	jsr _pci_hook_interrupt
+	add.l #12,SP
+	rts
+
+_wrapper_unhook_interrupt:
+	move.l D0,-(SP)			// handle
+	jsr _pci_unhook_interrupt
+	addq.l #4,SP
+	rts
+
+/* Not implemented */
+_wrapper_special_cycle:
+	move.l D1,-(SP)			// special cycle data
+	move.l D0,-(SP)			// bus number
+	jsr _pci_special_cycle
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_get_routing:
+	move.l D0,-(SP)			// handle
+	jsr _pci_get_routing
+	addq.l #4,SP
+	rts
+
+/* Not implemented */
+_wrapper_set_interrupt:
+	move.l D1,-(SP)			// mode
+	move.l D0,-(SP)			// handle
+	jsr _pci_set_interrupt
+	addq.l #8,SP
+	rts
+
+_wrapper_get_resource:
+	move.l D0,-(SP)			// handle
+	jsr _pci_get_resource
+	addq.l #4,SP
+	rts
+
+/* Not implemented */
+_wrapper_get_card_used:
+	move.l D1,-(SP)			// address
+	move.l D0,-(SP)			// handle
+	jsr _pci_get_card_used
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_set_card_used:
+	move.l A0,-(SP)			// callback
+	move.l D0,-(SP)			// handle
+	jsr _pci_set_card_used
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_read_mem_byte:
+	move.l A0,-(SP)			// pointer to data in memory
+	move.l D1,-(SP)			// address to access (in PCI memory address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_mem_byte
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_read_mem_word:
+	move.l A0,-(SP)			// pointer to data in memory
+	move.l D1,-(SP)			// address to access (in PCI memory address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_mem_word
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_read_mem_longword:
+	move.l A0,-(SP)			// pointer to data in memory
+	move.l D1,-(SP)			// address to access (in PCI memory address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_mem_longword
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_fast_read_mem_byte:
+	move.l D1,-(SP)			// address to access (in PCI memory address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_mem_byte
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_fast_read_mem_word:
+	move.l D1,-(SP)			// address to access (in PCI memory address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_mem_word
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_fast_read_mem_longword:
+	move.l D1,-(SP)			// address to access (in PCI memory address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_mem_longword
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_write_mem_byte:
+	move.l D2,-(SP)			// data to write
+	move.l D1,-(SP)			// address to access (in PCI memory address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_write_mem_byte
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_write_mem_word:
+	move.l D2,-(SP)			// data to write
+	move.l D1,-(SP)			// address to access (in PCI memory address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_write_mem_word
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_write_mem_longword:
+	move.l D2,-(SP)			// data to write
+	move.l D1,-(SP)			// address to access (in PCI memory address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_write_mem_longword
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_read_io_byte:
+	move.l A0,-(SP)			// pointer to data in memory
+	move.l D1,-(SP)			// address to access (in PCI I/O address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_io_byte
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_read_io_word:
+	move.l A0,-(SP)			// pointer to data in memory
+	move.l D1,-(SP)			// address to access (in PCI I/O address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_io_word
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_read_io_longword:
+	move.l A0,-(SP)			// pointer to data in memory
+	move.l D1,-(SP)			// address to access (in PCI I/O address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_io_longword
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_fast_read_io_byte:
+	move.l D1,-(SP)			// address to access (in PCI I/O address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_io_byte
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_fast_read_io_word:
+	move.l D1,-(SP)			// address to access (in PCI I/O address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_io_word
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_fast_read_io_longword:
+	move.l D1,-(SP)			// address to access (in PCI I/O address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_read_io_longword
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_write_io_byte:
+	move.l D2,-(SP)			// data to write
+	move.l D1,-(SP)			// address to access (in PCI I/O address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_write_io_byte
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_write_io_word:
+	move.l D2,-(SP)			// data to write
+	move.l D1,-(SP)			// address to access (in PCI I/O address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_write_io_word
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_write_io_longword:
+	move.l D2,-(SP)			// data to write
+	move.l D1,-(SP)			// address to access (in PCI I/O address space)
+	move.l D0,-(SP)			// handle
+	jsr _pci_write_io_longword
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_get_machine_id:
+	jsr _pci_get_machine_id
+	rts
+
+/* Not implemented */
+_wrapper_get_pagesize:
+	jsr _pci_get_pagesize
+	rts
+
+/* Not implemented */
+_wrapper_virt_to_bus:
+	move.l A0,-(SP)			// ptr
+	move.l D1,-(SP)			// address in virtual CPU space
+	move.l D0,-(SP)			// handle
+	jsr _pci_virt_to_bus
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_bus_to_virt:
+	move.l A0,-(SP)			// ptr
+	move.l D1,-(SP)			// PCI bus address
+	move.l D0,-(SP)			// handle
+	jsr _pci_bus_to_virt
+	add.l #12,SP
+	rts
+
+/* Not implemented */
+_wrapper_virt_to_phys:
+	move.l A0,-(SP)			// ptr
+	move.l D0,-(SP)			// address in virtual CPU space
+	jsr _pci_virt_to_phys
+	addq.l #8,SP
+	rts
+
+/* Not implemented */
+_wrapper_phys_to_virt:
+	move.l A0,-(SP)			// ptr
+	move.l D0,-(SP)			// physical CPU address 
+	jsr _pci_phys_to_virt
+	addq.l #8,SP
+	rts

radeon/radeon_base.c

@@ -74,7 +74,15 @@ extern void run_bios(struct radeonfb_info *rinfo);
 #define MIN_MAPPED_VRAM	(1024*768*4)
 
 #define CHIP_DEF(id, family, flags)					\
-	{ PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
+{													\
+	PCI_VENDOR_ID_ATI, 								\
+	id,												\
+	PCI_ANY_ID,										\
+	PCI_ANY_ID,										\
+	0,												\
+	0,												\
+	(flags) | (CHIP_FAMILY_##family)				\
+}
 
 struct pci_device_id radeonfb_pci_table[] = 
 {
@@ -231,7 +239,7 @@ extern struct fb_info *info_fb;
 #define rinfo ((struct radeonfb_info *) info_fb->par)
 static uint32_t inreg(uint32_t addr)
 {
-	return(INREG(addr));
+	return INREG(addr);
 }
 
 static void outreg(uint32_t addr, uint32_t val)
@@ -332,12 +340,10 @@ static int round_div(int num, int den)
 	return(num + (den / 2)) / den;
 }
 
-#ifndef MCF5445X
 static uint32_t read_vline_crnt(struct radeonfb_info *rinfo)
 {
 	return((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3FF);
 }
-#endif
 
 static int radeon_map_ROM(struct radeonfb_info *rinfo)
 {
@@ -510,10 +516,12 @@ static int radeon_probe_pll_params(struct radeonfb_info *rinfo)
 
 	hz = US_TO_TIMER(1000000.0) / (double)(stop_tv - start_tv);
 	dbg("%s:hz %d\r\n", __FUNCTION__, (int32_t) hz);
+
 	hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
 	vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
 	dbg("%s:hTotal=%d\r\n", __FUNCTION__, hTotal);
 	dbg("%s:vTotal=%d\r\n", __FUNCTION__, vTotal);
+
 	vclk = (double) hTotal * (double) vTotal * hz;
 	dbg("%s:vclk=%d\r\n", __FUNCTION__, (int) vclk);
 
@@ -525,41 +533,52 @@ static int radeon_probe_pll_params(struct radeonfb_info *rinfo)
 			num = 2 * n;
 			denom = 2 * m;
 			break;
+
 		case 2:
 			n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
 			m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
 			num = 2 * n;
 			denom = 2 * m;
 			break;
+
 		case 0:
 		default:
 			num = 1;
 			denom = 1;
 			break;
 	}
+
 	ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
 	radeon_pll_errata_after_index(rinfo);
+
 	n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
 	m = (INPLL(PPLL_REF_DIV) & 0x3ff);
+
 	num *= n;
 	denom *= m;
+
 	switch((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7)
 	{
 		case 1:
 			denom *= 2;
 			break;
+
 		case 2:
 			denom *= 4;
 			break;
+			
 		case 3:
 			denom *= 8;
 			break;
+
 		case 4:
 			denom *= 3;
 			break;
+
 		case 6:
 			denom *= 6;   
 			break;
+
 		case 7:
 			denom *= 12;
 			break;
@@ -567,6 +586,7 @@ static int radeon_probe_pll_params(struct radeonfb_info *rinfo)
 	vclk *= (double) denom;
 	vclk /= (double) (1000 * num);
 	xtal = (int32_t) vclk;
+
 	if ((xtal > 26900) && (xtal < 27100))
 		xtal = 2700;   /* 27 MHz */
 	else if ((xtal > 14200) && (xtal < 14400))
@@ -578,6 +598,7 @@ static int radeon_probe_pll_params(struct radeonfb_info *rinfo)
 		dbg("%s: xtal calculation failed: %d\r\n", __FUNCTION__, xtal);
 		return -1; /* error */
 	}
+
 	tmp = INPLL(M_SPLL_REF_FB_DIV);
 	ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
 
@@ -619,6 +640,7 @@ static void radeon_get_pllinfo(struct radeonfb_info *rinfo)
 			rinfo->pll.sclk = 23000;
 			rinfo->pll.ref_clk = 2700;
 			break;
+
 		case PCI_DEVICE_ID_ATI_RADEON_QL:
 		case PCI_DEVICE_ID_ATI_RADEON_QN:
 		case PCI_DEVICE_ID_ATI_RADEON_QO:
@@ -630,6 +652,7 @@ static void radeon_get_pllinfo(struct radeonfb_info *rinfo)
 			rinfo->pll.sclk = 27500;
 			rinfo->pll.ref_clk = 2700;
 			break;
+
 		case PCI_DEVICE_ID_ATI_RADEON_Id:
 		case PCI_DEVICE_ID_ATI_RADEON_Ie:
 		case PCI_DEVICE_ID_ATI_RADEON_If:
@@ -640,6 +663,7 @@ static void radeon_get_pllinfo(struct radeonfb_info *rinfo)
 			rinfo->pll.sclk = 25000;
 			rinfo->pll.ref_clk = 2700;
 			break;
+
 		case PCI_DEVICE_ID_ATI_RADEON_ND:
 		case PCI_DEVICE_ID_ATI_RADEON_NE:
 		case PCI_DEVICE_ID_ATI_RADEON_NF:
@@ -650,6 +674,7 @@ static void radeon_get_pllinfo(struct radeonfb_info *rinfo)
 			rinfo->pll.sclk = 27000;
 			rinfo->pll.ref_clk = 2700;
 			break;
+
 		case PCI_DEVICE_ID_ATI_RADEON_QD:
 		case PCI_DEVICE_ID_ATI_RADEON_QE:
 		case PCI_DEVICE_ID_ATI_RADEON_QF:
@@ -690,10 +715,12 @@ static void radeon_get_pllinfo(struct radeonfb_info *rinfo)
 		dbg("%s: Retreived PLL infos from registers\r\n", __FUNCTION__);
 		goto found;
 	}
+
 	/*
 	 * Fall back to already-set defaults...
 	 */
 	dbg("%s: Used default PLL infos\r\n", __FUNCTION__);
+
 found:
 	/*
 	 * Some methods fail to retreive SCLK and MCLK values, we apply default
@@ -707,13 +734,15 @@ found:
 
 	dbg("%s: Reference=%d MHz (RefDiv=0x%x) Memory=%d MHz\r\n", __FUNCTION__,
 			rinfo->pll.ref_clk / 100, rinfo->pll.ref_div, rinfo->pll.mclk / 100);
-	dbg("%s: System=%d MHz PLL min %d, max %d\r\n", __FUNCTION__, rinfo->pll.sclk / 100, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
+	dbg("%s: System=%d MHz PLL min %d, max %d\r\n", __FUNCTION__,
+			rinfo->pll.sclk / 100, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
 }
 
 static int var_to_depth(const struct fb_var_screeninfo *var)
 {
 	if (var->bits_per_pixel != 16)
 		return var->bits_per_pixel;
+
 	return(var->green.length == 5) ? 15 : 16;
 }
 
@@ -723,6 +752,7 @@ int radeonfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 	struct fb_var_screeninfo v;
 	int nom, den;
 	uint32_t pitch;
+
 	dbg("%s:\r\n", __FUNCTION__);
 
 	/* clocks over 135 MHz have heat isues with DVI on RV100 */
@@ -742,9 +772,11 @@ int radeonfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 		case 0 ... 8:
 			v.bits_per_pixel = 8;
 			break;
+
 		case 9 ... 16:
 			v.bits_per_pixel = 16;
 			break;
+
 #if 0 /* Doesn't seem to work */
 		case 17 ... 24:
 			v.bits_per_pixel = 24;
@@ -753,6 +785,7 @@ int radeonfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 		case 25 ... 32:
 			v.bits_per_pixel = 32;
 			break;
+
 		default:
 			return -1; //-EINVAL;
 	}
@@ -765,6 +798,7 @@ int radeonfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 			v.red.length = v.green.length = v.blue.length = 8;
 			v.transp.offset = v.transp.length = 0;
 			break;
+
 		case 15:
 			nom = 2;
 			den = 1;
@@ -774,6 +808,7 @@ int radeonfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 			v.red.length = v.green.length = v.blue.length = 5;
 			v.transp.offset = v.transp.length = 0;
 			break;
+
 		case 16:
 			nom = 2;
 			den = 1;
@@ -785,6 +820,7 @@ int radeonfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 			v.blue.length = 5;
 			v.transp.offset = v.transp.length = 0;
 			break;                          
+
 		case 24:
 			nom = 4;
 			den = 1;
@@ -794,6 +830,7 @@ int radeonfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 			v.red.length = v.blue.length = v.green.length = 8;
 			v.transp.offset = v.transp.length = 0;
 			break;
+
 		case 32:
 			nom = 4;
 			den = 1;
@@ -804,6 +841,7 @@ int radeonfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 			v.transp.offset = 24;
 			v.transp.length = 8;
 			break;
+
     default:
 			dbg("radeonfb: mode %d x %d x %d rejected, color depth invalid\r\n ",
 					var->xres, var->yres, var->bits_per_pixel);
@@ -814,6 +852,7 @@ int radeonfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 		v.yres_virtual = v.yres;
 	if (v.xres_virtual < v.xres)
 		v.xres_virtual = v.xres;
+
 	/*
 	 * XXX I'm adjusting xres_virtual to the pitch, that may help XFree
 	 * with some panels, though I don't quite like this solution
@@ -848,6 +887,7 @@ int radeonfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 	dbg("%s: using mode %d x %d \r\n", __FUNCTION__, v.xres, v.yres);
 
 	memcpy(var, &v, sizeof(v));
+
 	return 0;
 }
 
@@ -857,16 +897,20 @@ int radeonfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 //	DPRINT("radeonfb: radeonfb_pan_display\r\n");
 	if ((var->xoffset + var->xres) > var->xres_virtual)
 		return -1; //-EINVAL;
+
 	if (((var->yoffset * var->xres_virtual) + var->xoffset) >=
 	 (rinfo->mapped_vram - (var->yres * var->xres * (var->bits_per_pixel / 8))))
 		return -1; //-EINVAL;
+
 	if (rinfo->asleep)
 		return 0;
+
 	radeon_wait_for_fifo(rinfo, 2);
 	rinfo->fb_offset = ((var->yoffset * var->xres_virtual + var->xoffset) * var->bits_per_pixel / 8) & ~7;
 	rinfo->dst_pitch_offset = (rinfo->pitch << 22) | ((rinfo->fb_local_base + rinfo->fb_offset) >> 10);
 	OUTREG(CRTC_OFFSET, rinfo->fb_offset);
-  return 0;
+
+	return 0;
 }
 
 short mirror;
@@ -876,6 +920,7 @@ int radeonfb_ioctl(unsigned int cmd, unsigned long arg, struct fb_info *info)
 	struct radeonfb_info *rinfo = info->par;
 	uint32_t tmp;
 	uint32_t value = 0;
+
 	switch(cmd)
 	{
 		/*
@@ -899,6 +944,7 @@ int radeonfb_ioctl(unsigned int cmd, unsigned long arg, struct fb_info *info)
 				tmp &= ~(LVDS_ON | LVDS_BLON);
 			}
 			OUTREG(LVDS_GEN_CNTL, tmp);
+
 			if (value & 0x02)
 			{
 				tmp = INREG(CRTC_EXT_CNTL);
@@ -913,6 +959,7 @@ int radeonfb_ioctl(unsigned int cmd, unsigned long arg, struct fb_info *info)
 			}
 			OUTREG(CRTC_EXT_CNTL, tmp);
 			return 0;
+
 		case FBIO_RADEON_GET_MIRROR:
 			if (!rinfo->is_mobility)
 				return -1; //-EINVAL;
@@ -923,6 +970,7 @@ int radeonfb_ioctl(unsigned int cmd, unsigned long arg, struct fb_info *info)
 			if (CRTC_CRT_ON & tmp)
 				value |= 0x02;
 			return 0;
+
 		default:
 			return -1; //-EINVAL;
 	}
@@ -937,24 +985,30 @@ int32_t radeon_screen_blank(struct radeonfb_info *rinfo, int32_t blank, int32_t
 
 	if (rinfo->lock_blank)
 		return 0;
+
 	dbg("radeonfb: radeon_screen_blank\r\n");
 	radeon_engine_idle();
 	val = INREG(CRTC_EXT_CNTL);
 	val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS | CRTC_VSYNC_DIS);
+
 	switch(blank)
 	{
 		case FB_BLANK_VSYNC_SUSPEND:
 			val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
 			break;
+
 		case FB_BLANK_HSYNC_SUSPEND:
 			val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
 			break;
+
 		case FB_BLANK_POWERDOWN:
 			val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS | CRTC_HSYNC_DIS);
 			break;
+
 		case FB_BLANK_NORMAL:
 			val |= CRTC_DISPLAY_DIS;
 			break;
+
 		case FB_BLANK_UNBLANK:
 		default:
 			unblank = 1;
@@ -974,6 +1028,7 @@ int32_t radeon_screen_blank(struct radeonfb_info *rinfo, int32_t blank, int32_t
 				OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
 			}
 			break;
+
 		case MT_LCD:
 			rinfo->lvds_timer = 0;
 			val = INREG(LVDS_GEN_CNTL);
@@ -1007,15 +1062,19 @@ int32_t radeon_screen_blank(struct radeonfb_info *rinfo, int32_t blank, int32_t
 				/* We don't do a full switch-off on a simple mode switch */
 				if (mode_switch || blank == FB_BLANK_NORMAL)
 					break;
+
 				/* Asic bug, when turning off LVDS_ON, we have to make sure
 				 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
 				 */
 				tmp_pix_clks = INPLL(PIXCLKS_CNTL);
 				if (rinfo->is_mobility || rinfo->is_IGP)
 					OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
+
 				val &= ~(LVDS_BL_MOD_EN);
 				OUTREG(LVDS_GEN_CNTL, val);
+
 				wait(100);
+
 				val &= ~(LVDS_ON | LVDS_EN);
 				OUTREG(LVDS_GEN_CNTL, val);
 				val &= ~LVDS_DIGON;
@@ -1023,6 +1082,7 @@ int32_t radeon_screen_blank(struct radeonfb_info *rinfo, int32_t blank, int32_t
 				rinfo->lvds_timer = (int32_t)rinfo->panel_info.pwr_delay;
 				rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
 				rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
+
 				if (rinfo->is_mobility || rinfo->is_IGP)
 					OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
 			}
@@ -1039,8 +1099,10 @@ int32_t radeon_screen_blank(struct radeonfb_info *rinfo, int32_t blank, int32_t
 int radeonfb_blank(int blank, struct fb_info *info)
 {
 	struct radeonfb_info *rinfo = info->par;
+
 	if (rinfo->asleep)
 		return 0;
+
 	return radeon_screen_blank(rinfo, blank, 0);
 }
 
@@ -1049,14 +1111,18 @@ static int radeon_setcolreg(unsigned regno, unsigned red, unsigned green,
 {
 	struct radeonfb_info *rinfo = info->par;
 	uint32_t pindex;
+
 	if (regno > 255)
 		return 1;
+
 	red >>= 8;
 	green >>= 8;
 	blue >>= 8;
+
 	rinfo->palette[regno].red = red;
 	rinfo->palette[regno].green = green;
 	rinfo->palette[regno].blue = blue;
+
 	/* default */
 	pindex = regno;
 	if (!rinfo->asleep)
@@ -1069,7 +1135,9 @@ static int radeon_setcolreg(unsigned regno, unsigned red, unsigned green,
 				return 1;
 			if (rinfo->depth == 15 && regno > 31)
 				return 1;
-			/* For 565, the green component is mixed one order
+
+			/*
+			 * For 565, the green component is mixed one order
 			 * below
 			 */
 			if (rinfo->depth == 16)
@@ -1095,6 +1163,7 @@ int radeonfb_setcolreg(unsigned regno, unsigned red, unsigned green,
 	struct radeonfb_info *rinfo = info->par;
 	uint32_t dac_cntl2, vclk_cntl = 0;
 	int rc;
+
 	if (!rinfo->asleep)
 	{
 		if (rinfo->is_mobility)
@@ -1102,6 +1171,7 @@ int radeonfb_setcolreg(unsigned regno, unsigned red, unsigned green,
 			vclk_cntl = INPLL(VCLK_ECP_CNTL);
 			OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
 		}
+
 		/* Make sure we are on first palette */
 		if (rinfo->has_CRTC2)
 		{
@@ -1113,6 +1183,7 @@ int radeonfb_setcolreg(unsigned regno, unsigned red, unsigned green,
 	rc = radeon_setcolreg(regno, red, green, blue, transp, info);
 	if (!rinfo->asleep && rinfo->is_mobility)
 		OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
+
 	return rc;
 }
 
@@ -1129,6 +1200,7 @@ static void radeon_save_state(struct radeonfb_info *rinfo, struct radeon_regs *s
 	save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
 	save->crtc_pitch = INREG(CRTC_PITCH);
 	save->surface_cntl = INREG(SURFACE_CNTL);
+
 	/* FP regs */
 	save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
 	save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
@@ -1143,6 +1215,7 @@ static void radeon_save_state(struct radeonfb_info *rinfo, struct radeon_regs *s
 	save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
 	save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
 	/* PLL regs */
+
 	save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
 	radeon_pll_errata_after_index(rinfo);
 	save->ppll_div_3 = INPLL(PPLL_DIV_3);
@@ -1152,8 +1225,10 @@ static void radeon_save_state(struct radeonfb_info *rinfo, struct radeon_regs *s
 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
 {
 	int i;
+
 	dbg("radeonfb: radeon_write_pll_regs\r\n");
 	radeon_wait_for_fifo(rinfo, 20);
+
 #if 0
 	/* Workaround from XFree */
 	if (rinfo->is_mobility)
@@ -1180,22 +1255,27 @@ static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_reg
 		}
 	}
 #endif
+
 	/* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
 	OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
+
 	/* Reset PPLL & enable atomic update */
 	OUTPLLP(PPLL_CNTL, PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
 	 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
+
 	/* Switch to selected PPLL divider */
 	OUTREGP(CLOCK_CNTL_INDEX,	mode->clk_cntl_index & PPLL_DIV_SEL_MASK, ~PPLL_DIV_SEL_MASK);
 	radeon_pll_errata_after_index(rinfo);
 	radeon_pll_errata_after_data(rinfo);
+
 	/* Set PPLL ref. div */
 	if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_RS300
 	 || rinfo->family == CHIP_FAMILY_R350 || rinfo->family == CHIP_FAMILY_RV350)
 	{
 		if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK)
 		{
-			/* When restoring console mode, use saved PPLL_REF_DIV
+			/*
+			 * When restoring console mode, use saved PPLL_REF_DIV
 			 * setting.
 			 */
 			OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
@@ -1216,17 +1296,22 @@ static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_reg
 	/* Write update */
 	while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
 	OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
+
 	/* Wait read update complete */
 	/* FIXME: Certain revisions of R300 can't recover here.  Not sure of
 	   the cause yet, but this workaround will mask the problem for now.
 	   Other chips usually will pass at the very first test, so the
 	   workaround shouldn't have any effect on them. */
-	for(i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++);
+
+	for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++);
 	OUTPLL(HTOTAL_CNTL, 0);
+
 	/* Clear reset & atomic update */
 	OUTPLLP(PPLL_CNTL, 0, ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
+
 	/* We may want some locking ... oh well */
 	radeon_msleep(5);
+
 	/* Switch back VCLK source to PPLL */
 	OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
 }
@@ -1248,6 +1333,7 @@ static void radeon_timer_func(void)
 
 #ifdef FIXME_LATER
 	static int32_t start_timer;
+
 	/* delayed LVDS panel power up/down */
 	if (rinfo->lvds_timer)
 	{
@@ -1263,10 +1349,11 @@ static void radeon_timer_func(void)
 	}
 	else
 		start_timer = 0;
-#endif
+#endif /* FIXME_LATER */
 
 	if (rinfo->RenderCallback != NULL)
 		rinfo->RenderCallback(rinfo);
+
 	if ((info->screen_mono != NULL) && info->update_mono)
 	{
 		int32_t foreground = 255, background = 0;
@@ -1275,21 +1362,25 @@ static void radeon_timer_func(void)
 		int dst_x = 0;
 		int w = (int)info->var.xres_virtual;
 		int h = (int)info->var.yres_virtual;
+
 //		info->fbops->SetClippingRectangle(info,0,0,w-1,h-1);
 		src_buf = (uint8_t*)((int32_t)src_buf & ~3);
 		dst_x -= (int32_t)skipleft;
 		w += (int32_t)skipleft;
 		info->fbops->SetupForScanlineCPUToScreenColorExpandFill(info,(int)foreground,(int)background,3,0xffffffff);
 		info->fbops->SubsequentScanlineCPUToScreenColorExpandFill(info,(int)dst_x,0,w,h,skipleft);
+
 		while (--h >= 0)
 		{
 			info->fbops->SubsequentScanline(info, (unsigned long *) src_buf);
 			src_buf += (info->var.xres_virtual >> 3);
 		}
+
 //		info->fbops->DisableClipping(info);
 		if (info->update_mono > 0)
 			info->update_mono = 0;
 	}
+
 	if ((info->var.xres_virtual != info->var.xres)
 	 || (info->var.yres_virtual != info->var.yres))
 	{
@@ -1310,6 +1401,7 @@ static void radeon_timer_func(void)
 			x -= 8;
 			chg = 1;
 		}
+
 		if (((y + info->var.yres) < info->var.yres_virtual) && (rinfo->cursor_y >= (info->var.yres - 8)))
 		{
 			y += 8;
@@ -1329,7 +1421,9 @@ static void radeon_timer_func(void)
 			disp = rinfo->cursor_show;
 			if (disp)
 				info->fbops->HideCursor(info);
+
 			fb_pan_display(info,&var);
+
 			if (disp)
 				info->fbops->ShowCursor(info);
 		}
@@ -1345,14 +1439,19 @@ void radeon_write_mode(struct radeonfb_info *rinfo, struct radeon_regs *mode, in
 {
 	int i;
 	int primary_mon = PRIMARY_MONITOR(rinfo);
+
 	dbg("radeonfb: radeon_write_mode\r\n");
+
 	if (!regs_only)
 		radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
+
 	radeon_wait_for_fifo(rinfo, 31);
-	for(i=0; i<10; i++)
+
+	for (i = 0; i < 10; i++)
 		OUTREG(common_regs[i].reg, common_regs[i].val);
+
 	/* Apply surface registers */
-	for(i=0; i<8; i++)
+	for (i = 0; i < 8; i++)
 	{
 		OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
 		OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
@@ -1380,9 +1479,11 @@ void radeon_write_mode(struct radeonfb_info *rinfo, struct radeon_regs *mode, in
 	else
 #endif
 		OUTREG(CRTC_OFFSET_CNTL, 0);
+
 	OUTREG(CRTC_PITCH, mode->crtc_pitch);
 	OUTREG(SURFACE_CNTL, mode->surface_cntl);
 	radeon_write_pll_regs(rinfo, mode);
+
 	if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
 	{
 		radeon_wait_for_fifo(rinfo, 10);
@@ -1396,6 +1497,7 @@ void radeon_write_mode(struct radeonfb_info *rinfo, struct radeon_regs *mode, in
 		OUTREG(TMDS_CRC, mode->tmds_crc);
 		OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
 	}
+
 	if (!regs_only)
 		radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
 	radeon_wait_for_fifo(rinfo, 2);
@@ -1407,11 +1509,13 @@ void radeon_write_mode(struct radeonfb_info *rinfo, struct radeon_regs *mode, in
  */
 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs, uint32_t freq)
 {
-	static const struct {
+	static const struct
+	{
 		int divider;
 		int bitvalue;
 	} *post_div,
-	post_divs[] = {
+	post_divs[] =
+	{
 		{ 1,  0 },
 		{ 2,  1 },
 		{ 4,  2 },
@@ -1424,6 +1528,7 @@ static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs
 	};
 	int fb_div, pll_output_freq = 0;
 	int uses_dvo = 0;
+
 	/* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
 	 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
 	 * recent than an r(v)100...
@@ -1443,9 +1548,11 @@ static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs
 		uint32_t fp2_gen_cntl = INREG(FP2_GEN_CNTL);
 		uint32_t disp_output_cntl;
 		int source;
+
 		/* FP2 path not enabled */
 		if ((fp2_gen_cntl & FP2_ON) == 0)
 			break;
+
 		/* Not all chip revs have the same format for this register,
 		 * extract the source selection
 		 */
@@ -1464,9 +1571,11 @@ static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs
 		}
 		else
 			source = (fp2_gen_cntl >> 13) & 0x1;
+
 		/* sourced from CRTC2 -> exit */
 		if (source == 1)
 			break;
+
 		/* so we end up on CRTC1, let's set uses_dvo to 1 now */
 		uses_dvo = 1;
 		break;
@@ -1476,27 +1585,32 @@ static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs
 #endif
 	if (freq > rinfo->pll.ppll_max)
 		freq = rinfo->pll.ppll_max;
-	if (freq*12 < rinfo->pll.ppll_min)
+	if (freq * 12 < rinfo->pll.ppll_min)
 		freq = rinfo->pll.ppll_min / 12;
-	for(post_div = &post_divs[0]; post_div->divider; ++post_div)
+	for (post_div = &post_divs[0]; post_div->divider; ++post_div)
 	{
 		pll_output_freq = post_div->divider * freq;
-		/* If we output to the DVO port (external TMDS), we don't allow an
+
+		/*
+		 * If we output to the DVO port (external TMDS), we don't allow an
 		 * odd PLL divider as those aren't supported on this path
 		 */
 		if (uses_dvo && (post_div->divider & 1))
 			continue;
+
 		if (pll_output_freq >= rinfo->pll.ppll_min  &&
 		    pll_output_freq <= rinfo->pll.ppll_max)
 			break;
 	}
+
 	/* If we fall through the bottom, try the "default value"
 	   given by the terminal post_div->bitvalue */
-	if ( !post_div->divider )
+	if (!post_div->divider)
 	{
 		post_div = &post_divs[post_div->bitvalue];
 		pll_output_freq = post_div->divider * freq;
 	}
+
 	/* If we fall through the bottom, try the "default value"
 	   given by the terminal post_div->bitvalue */
 	if ( !post_div->divider )
@@ -1535,6 +1649,7 @@ int radeonfb_set_par(struct fb_info *info)
 	newmode = (struct radeon_regs *) driver_mem_alloc(sizeof(struct radeon_regs));
 	if (!newmode)
 		return -1; //-ENOMEM;
+
 	/* We always want engine to be idle on a mode switch, even
 	 * if we won't actually change the mode
 	 */
@@ -1582,24 +1697,29 @@ int radeonfb_set_par(struct fb_info *info)
 			newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
 		}
 	}
+
 	dotClock = 1000000000 / pixClock;
 	freq = dotClock / 10; /* x100 */
 	hsync_wid = (hSyncEnd - hSyncStart) / 8;
+
 	if (hsync_wid == 0)
 		hsync_wid = 1;
 	else if (hsync_wid > 0x3f)	/* max */
 		hsync_wid = 0x3f;
+
 	if (mode->vmode & FB_VMODE_DOUBLE)
 	{
 		vSyncStart <<= 1;
 		vSyncEnd <<= 1;
 		vTotal <<= 1;
 	}
+
 	vsync_wid = vSyncEnd - vSyncStart;
 	if (vsync_wid == 0)
 		vsync_wid = 1;
 	else if (vsync_wid > 0x1f)	/* max */
 		vsync_wid = 0x1f;
+
 	// FIXME: this doesn't seem to be used anywhere hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
 	// FIXME: this doesn't seem to be used anywhere vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
 	// FIXME: this doesn't seem to be used anywhere cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
@@ -1624,6 +1744,7 @@ int radeonfb_set_par(struct fb_info *info)
 	/* Clear auto-center etc... */
 	newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
 	newmode->crtc_more_cntl &= 0xfffffff0;
+
 	if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
 	{
 		newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
@@ -1633,13 +1754,16 @@ int radeonfb_set_par(struct fb_info *info)
 	}
 	else
 		newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON;
+
 	newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN;
 	newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) | (((mode->xres / 8) - 1) << 16));
 	newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) | (hsync_wid << 16) | (h_sync_pol << 23));
+
 	if (mode->vmode & FB_VMODE_DOUBLE)
 		newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) | (((mode->yres << 1) - 1) << 16);
 	else
 		newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) | ((mode->yres - 1) << 16);
+
 	newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) | (vsync_wid << 16) | (v_sync_pol << 23));
 	/* We first calculate the engine pitch */
 	rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f) & ~(0x3f)) >> 6;
@@ -1653,6 +1777,7 @@ int radeonfb_set_par(struct fb_info *info)
 	 * swapper as well, so we leave it unset now.
 	 */
 	newmode->surface_cntl = 0;
+
 	if (rinfo->big_endian)
 	{
 		/* Setup swapping on both apertures, though we currently
@@ -1674,12 +1799,13 @@ int radeonfb_set_par(struct fb_info *info)
 	}
 
 	/* Clear surface registers */
-	for(i = 0; i < 8; i++)
+	for (i = 0; i < 8; i++)
 	{
 		newmode->surf_lower_bound[i] = 0;
 		newmode->surf_upper_bound[i] = 0x1f;
 		newmode->surf_info[i] = 0;
 	}
+
 	rinfo->bpp = mode->bits_per_pixel;
 	rinfo->depth = depth;
 
@@ -1724,6 +1850,7 @@ int radeonfb_set_par(struct fb_info *info)
 		 & ~(FP_SEL_CRTC2 | FP_RMX_HVSYNC_CONTROL_EN | FP_DFP_SYNC_SEL | FP_CRT_SYNC_SEL
 		  | FP_CRTC_LOCK_8DOT | FP_USE_SHADOW_EN | FP_CRTC_USE_SHADOW_VEND | FP_CRT_SYNC_ALT));
 		newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR | FP_CRTC_DONT_SHADOW_HEND | FP_PANEL_FORMAT);
+
 		if (IS_R300_VARIANT(rinfo) || (rinfo->family == CHIP_FAMILY_R200))
 		{
 			newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
@@ -1734,10 +1861,12 @@ int radeonfb_set_par(struct fb_info *info)
 		}
 		else
 			newmode->fp_gen_cntl |= FP_SEL_CRTC1;
+
 		newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
 		newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
 		newmode->tmds_crc = rinfo->init_state.tmds_crc;
 		newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
+
 		if (primary_mon == MT_LCD)
 		{
 			newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
@@ -1755,11 +1884,13 @@ int radeonfb_set_par(struct fb_info *info)
 				newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
 			newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
 		}
+
 		newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) | (((mode->xres / 8) - 1) << 16));
 		newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) | ((mode->yres - 1) << 16);
 		newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) | (hsync_wid << 16) | (h_sync_pol << 23));
 		newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) | (vsync_wid << 16) | (v_sync_pol  << 23));
 	}
+
 	/* do it! */
 	if (!rinfo->asleep)
 	{
@@ -1778,10 +1909,12 @@ int radeonfb_set_par(struct fb_info *info)
 		/* (re)initialize the engine */
 		radeon_engine_init(rinfo);
 	}
+
 	/* Update fix */
 	info->fix.line_length = rinfo->pitch*64;
 	info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
 	driver_mem_free(newmode);
+
 	return 0;
 }
 

radeon/radeon_cursor.c

@@ -44,11 +44,13 @@
  *
  */
 
+#include "bas_types.h"
+#include "bas_printf.h"
 #include "radeonfb.h"
 
 #define DBG_RADEON
 #ifdef DBG_RADEON
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DBG_RADEON */
@@ -66,20 +68,20 @@
 #define CURSOR_SWAPPING_DECL_MMIO
 #define CURSOR_SWAPPING_DECL	    unsigned long  __surface_cntl=0;
 #define CURSOR_SWAPPING_START() \
-	if(rinfo->big_endian) \
+    if (rinfo->big_endian) \
     OUTREG(SURFACE_CNTL, \
 	   ((__surface_cntl = INREG(SURFACE_CNTL)) | \
 	    NONSURF_AP0_SWP_32BPP) & \
 	   ~NONSURF_AP0_SWP_16BPP);
 #define CURSOR_SWAPPING_END() \
-	if(rinfo->big_endian) \
+    if (rinfo->big_endian) \
 	(OUTREG(SURFACE_CNTL, __surface_cntl));
 
 /* Set cursor foreground and background colors */
 void radeon_set_cursor_colors(struct fb_info *info, int bg, int fg)
 {
 	struct radeonfb_info *rinfo = info->par;
-	unsigned long *pixels = (unsigned long *)((unsigned long) rinfo->fb_base+rinfo->cursor_start);
+    unsigned long *pixels = (unsigned long *)((unsigned long) rinfo->fb_base + rinfo->cursor_start);
 	int pixel, i;
 	CURSOR_SWAPPING_DECL_MMIO
 	CURSOR_SWAPPING_DECL
@@ -88,15 +90,17 @@ void radeon_set_cursor_colors(struct fb_info *info, int bg, int fg)
 	fg |= 0xff000000;
 	bg |= 0xff000000;
 	/* Don't recolour the image if we don't have to. */
-	if(fg == rinfo->cursor_fg && bg == rinfo->cursor_bg)
+    if (fg == rinfo->cursor_fg && bg == rinfo->cursor_bg)
 		return;
 	CURSOR_SWAPPING_START();
-	/* Note: We assume that the pixels are either fully opaque or fully
+
+    /*
+     * Note: We assume that the pixels are either fully opaque or fully
 	 * transparent, so we won't premultiply them, and we can just
 	 * check for non-zero pixel values; those are either fg or bg
 	 */
-	for(i = 0; i < CURSOR_WIDTH * CURSOR_HEIGHT; i++, pixels++)
-		if((pixel = *pixels))
+    for (i = 0; i < CURSOR_WIDTH * CURSOR_HEIGHT; i++, pixels++)
+        if ((pixel = *pixels))
 			*pixels = (pixel == rinfo->cursor_fg) ? fg : bg;
 	CURSOR_SWAPPING_END();
 	rinfo->cursor_fg = fg;
@@ -112,27 +116,30 @@ void radeon_set_cursor_position(struct fb_info *info, int x, int y)
 	struct fb_var_screeninfo *mode = &info->var;
 	int xorigin = 0;
 	int yorigin = 0;
-	if(mode->vmode & FB_VMODE_DOUBLE)
+    if (mode->vmode & FB_VMODE_DOUBLE)
 		y <<= 1;
-	if(x < 0)
+    if (x < 0)
 		xorigin = 1 - x;
-	if(y < 0)
+    if (y < 0)
 	  yorigin = 1 - y;
+
 //	DPRINTVALHEX("radeonfb: RADEONSetCursorPosition: cursor_start ",rinfo->cursor_start);
 //	DPRINTVAL(" x ",x);
 //	DPRINTVAL(" y ",y);
 //	DPRINT("\r\n");
+
 	OUTREG(CUR_HORZ_VERT_OFF, (CUR_LOCK  | (xorigin << 16) | yorigin));
 	OUTREG(CUR_HORZ_VERT_POSN, (CUR_LOCK | ((xorigin ? 0 : x) << 16) | (yorigin ? 0 : y)));
 	OUTREG(CUR_OFFSET, rinfo->cursor_start + yorigin * 256);
 	rinfo->cursor_x = (unsigned long)x;
-	if(mode->vmode & FB_VMODE_DOUBLE)
-		rinfo->cursor_y = (unsigned long)y >> 1;
+    if (mode->vmode & FB_VMODE_DOUBLE)
+        rinfo->cursor_y = (unsigned long) y >> 1;
 	else
-		rinfo->cursor_y = (unsigned long)y;
+        rinfo->cursor_y = (unsigned long) y;
 }
 
-/* Copy cursor image from `image' to video memory.  RADEONSetCursorPosition
+/*
+ * Copy cursor image from `image' to video memory.  RADEONSetCursorPosition
  * will be called after this, so we can ignore xorigin and yorigin.
  */
 void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsigned short *data, int zoom)
@@ -143,11 +150,14 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
 	unsigned short chunk, mchunk;
 	unsigned long i, j, k;
 	CURSOR_SWAPPING_DECL
+
 //	DPRINTVALHEX("radeonfb: RADEONLoadCursorImage: cursor_start ",rinfo->cursor_start);
-//	DPRINT("\r\n");	
+//	DPRINT("\r\n");
+
 	save = INREG(CRTC_GEN_CNTL) & ~(unsigned long) (3 << 20);
 	save |= (unsigned long) (2 << 20);
 	OUTREG(CRTC_GEN_CNTL, save & (unsigned long)~CRTC_CUR_EN);
+
 	/*
 	 * Convert the bitmap to ARGB32.
 	 */
@@ -157,22 +167,22 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
 	{
 	case 1:
 	default:
-		for(i = 0; i < CURSOR_HEIGHT; i++)
+        for (i = 0; i < CURSOR_HEIGHT; i++)
 		{
-			if(i < 16)
+            if (i < 16)
 			{
 				mchunk = *mask++;
 				chunk = *data++;
 			}
 			else
 				mchunk = chunk = 0;
-			for(j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j++)
+            for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j++)
 			{
-				for(k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
+                for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
 				{
-					if(mchunk & 0x8000)
+                    if (mchunk & 0x8000)
 					{
-						if(chunk & 0x8000)
+                        if (chunk & 0x8000)
 							*d++ = 0xff000000; /* Black, fully opaque. */				
 						else
 							*d++ = 0xffffffff; /* White, fully opaque. */
@@ -184,13 +194,13 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
 		}
 		break;
 	case 2:
-		for(i = 0; i < CURSOR_HEIGHT; i++)
+        for (i = 0; i < CURSOR_HEIGHT; i++)
 		{
-			if(i < 16*2)
+            if (i < 16*2)
 			{
 				mchunk = *mask;
 				chunk = *data;
-				if((i & 1) == 1)
+                if ((i & 1) == 1)
 				{
 					mask++;
 					data++;
@@ -198,13 +208,13 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
 			}
 			else
 				mchunk = chunk = 0;
-			for(j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=2)
+            for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=2)
 			{
-				for(k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
+                for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
 				{
-					if(mchunk & 0x8000)
+                    if (mchunk & 0x8000)
 					{
-						if(chunk & 0x8000)
+                        if (chunk & 0x8000)
 						{
 							*d++ = 0xff000000; /* Black, fully opaque. */				
 							*d++ = 0xff000000; 
@@ -225,13 +235,13 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
 		}
 		break;
 	case 4:
-		for(i = 0; i < CURSOR_HEIGHT; i++)
+        for (i = 0; i < CURSOR_HEIGHT; i++)
 		{
-			if(i < 16*4)
+            if (i < 16 * 4)
 			{
 				mchunk = *mask;
 				chunk = *data;
-				if((i & 3) == 3)
+                if ((i & 3) == 3)
 				{
 					mask++;
 					data++;
@@ -239,13 +249,13 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
 			}
 			else
 				mchunk = chunk = 0;
-			for(j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=4)
+            for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=4)
 			{
-				for(k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
+                for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
 				{
-					if(mchunk & 0x8000)
+                    if (mchunk & 0x8000)
 					{
-						if(chunk & 0x8000)
+                        if (chunk & 0x8000)
 						{
 							*d++ = 0xff000000; /* Black, fully opaque. */				
 							*d++ = 0xff000000; 
@@ -282,6 +292,7 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
 void radeon_hide_cursor(struct fb_info *info)
 {
 	struct radeonfb_info *rinfo = info->par;
+
 //	DPRINT("radeonfb: RADEONHideCursor\r\n");
 	OUTREGP(CRTC_GEN_CNTL, 0, ~CRTC_CUR_EN);
 	rinfo->cursor_show = 0;
@@ -291,6 +302,7 @@ void radeon_hide_cursor(struct fb_info *info)
 void radeon_show_cursor(struct fb_info *info)
 {
 	struct radeonfb_info *rinfo = info->par;
+
 //	DPRINT("radeonfb: RADEONShowCursor\r\n");
 	OUTREGP(CRTC_GEN_CNTL, CRTC_CUR_EN, ~CRTC_CUR_EN);
 	rinfo->cursor_show = 1;
@@ -303,9 +315,9 @@ long radeon_cursor_init(struct fb_info *info)
 	int size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT;
 	unsigned long fbarea = offscreen_alloc(rinfo->info, size_bytes + 256);
 
-	dbg("radeonfb: %s: fbarea: %p\r\n", __FUNCTION__, fbarea);
+    dbg("radeonfb: %s: fbarea: %p\r\n", fbarea);
 
-	if(!fbarea)
+    if (!fbarea)
 		rinfo->cursor_start = 0;
 	else
 	{

spi/dspi.c

@@ -25,7 +25,6 @@
  *      Author: mfro
  */
 
-#include <stdint.h>
 #include <bas_types.h>
 #include <MCF5475.h>
 
@@ -36,7 +35,7 @@ struct baudrate
 	int	divider;
 };
 
-static const int system_clock = 133000000;	/* System clock in Hz */
+static const int system_clock = 132000000;	/* System clock in Hz */
 
 struct baudrate baudrates[] =
 {

spi/mmc.c

@@ -1,4 +1,3 @@
-#include <stdint.h>
 #include <bas_types.h>
 #include <sd_card.h>
 #include <bas_printf.h>
@@ -466,7 +465,7 @@ DSTATUS disk_initialize(uint8_t drv)
 	{
 		uint8_t buff[16];
 		res = disk_ioctl(0, MMC_GET_CSD, buff);
-		
+
 		if (res == RES_OK)
 		{
 			debug_printf("CSD of card:\r\n");

sys/BaS.c

@@ -21,8 +21,7 @@
  * Copyright 2012        M. Froeschle
  */
 
-#include <stdint.h>
-#include <stdbool.h>
+#include <bas_types.h>
 
 #include "MCF5475.h"
 #include "startcf.h"
@@ -48,10 +47,11 @@
 #include "bootp.h"
 #include "interrupts.h"
 #include "exceptions.h"
+#include "net_timer.h"
 
 //#define BAS_DEBUG
 #if defined(BAS_DEBUG)
-#define dbg(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif
@@ -76,10 +76,10 @@ extern uint8_t _EMUTOS_SIZE[];
  */
 static inline bool pic_txready(void)
 {
-	if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_TXRDY)
-		return true;
+    if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_TXRDY)
+        return true;
 
-	return false;
+    return false;
 }
 
 /*
@@ -87,16 +87,16 @@ static inline bool pic_txready(void)
  */
 static inline bool pic_rxready(void)
 {
-	if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_RXRDY)
-		return true;
+    if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_RXRDY)
+        return true;
 
-	return false;
+    return false;
 }
 
 void write_pic_byte(uint8_t value)
 {
     /* Wait until the transmitter is ready or 1000us are passed */
-	waitfor(1000, pic_txready);
+    waitfor(1000, pic_txready);
 
     /* Transmit the byte */
     *(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT) = value; // Really 8-bit
@@ -105,66 +105,66 @@ void write_pic_byte(uint8_t value)
 uint8_t read_pic_byte(void)
 {
     /* Wait until a byte has been received or 1000us are passed */
-	waitfor(1000, pic_rxready);
+    waitfor(1000, pic_rxready);
 
     /* Return the received byte */
-    return *(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT); // Really 8-bit
+    return * (volatile uint8_t *) (&MCF_PSC3_PSCTB_8BIT); // Really 8-bit
 }
 
 void pic_init(void)
 {
-	char answer[4] = "OLD";
+    char answer[4] = "OLD";
 
-	xprintf("initialize the PIC: ");
+    xprintf("initialize the PIC: ");
 
-	/* Send the PIC initialization string */
-	write_pic_byte('A');
-	write_pic_byte('C');
-	write_pic_byte('P');
-	write_pic_byte('F');
+    /* Send the PIC initialization string */
+    write_pic_byte('A');
+    write_pic_byte('C');
+    write_pic_byte('P');
+    write_pic_byte('F');
 
-	/* Read the 3-char answer string. Should be "OK!". */
-	answer[0] = read_pic_byte();
-	answer[1] = read_pic_byte();
-	answer[2] = read_pic_byte();
-	answer[3] = '\0';
+    /* Read the 3-char answer string. Should be "OK!". */
+    answer[0] = read_pic_byte();
+    answer[1] = read_pic_byte();
+    answer[2] = read_pic_byte();
+    answer[3] = '\0';
 
-	if (answer[0] != 'O' || answer[1] != 'K' || answer[2] != '!')
-	{
-		dbg("%s: PIC initialization failed. Already initialized?\r\n", __FUNCTION__);
-	}
-	else
-	{
-		xprintf("%s\r\n", answer);
-	}
+    if (answer[0] != 'O' || answer[1] != 'K' || answer[2] != '!')
+    {
+        dbg("PIC initialization failed. Already initialized?\r\n");
+    }
+    else
+    {
+        xprintf("%s\r\n", answer);
+    }
 }
 
 void nvram_init(void)
 {
-	int i;
+    int i;
 
-	xprintf("Restore the NVRAM data: ");
+    xprintf("Restore the NVRAM data: ");
 
-	/* Request for NVRAM backup data */
-	write_pic_byte(0x01);
+    /* Request for NVRAM backup data */
+    write_pic_byte(0x01);
 
-	/* Check answer type */
-	if (read_pic_byte() != 0x81)
-	{
-		// FIXME: PIC protocol error
-		xprintf("FAILED\r\n");
-		return;
-	}
+    /* Check answer type */
+    if (read_pic_byte() != 0x81)
+    {
+        // FIXME: PIC protocol error
+        xprintf("FAILED\r\n");
+        return;
+    }
 
-	/* Restore the NVRAM backup to the FPGA */
-	for (i = 0; i < 64; i++)
-	{
-		uint8_t data = read_pic_byte();
-		*(volatile uint8_t*)0xffff8961 = i;
-		*(volatile uint8_t*)0xffff8963 = data;
-	}
+    /* Restore the NVRAM backup to the FPGA */
+    for (i = 0; i < 64; i++)
+    {
+        uint8_t data = read_pic_byte();
+        *(volatile uint8_t*)0xffff8961 = i;
+        *(volatile uint8_t*)0xffff8963 = data;
+    }
 
-	xprintf("finished\r\n");
+    xprintf("finished\r\n");
 }
 
 #define KBD_ACIA_CONTROL		((uint8_t *) 0xfffffc00)
@@ -174,24 +174,24 @@ void nvram_init(void)
 
 void acia_init()
 {
-	xprintf("init ACIA: ");
-	/* init ACIA */
-	* KBD_ACIA_CONTROL = 3;		/* master reset */
-	NOP();
+    xprintf("init ACIA: ");
+    /* init ACIA */
+    * KBD_ACIA_CONTROL = 3;		/* master reset */
+    NOP();
 
-	* MIDI_ACIA_CONTROL = 3;	/* master reset */
-	NOP();
+    * MIDI_ACIA_CONTROL = 3;	/* master reset */
+    NOP();
 
-	* KBD_ACIA_CONTROL = 0x96;	/* clock div = 64, 8N1, RTS low, TX int disable, RX int enable */
-	NOP();
+    * KBD_ACIA_CONTROL = 0x96;	/* clock div = 64, 8N1, RTS low, TX int disable, RX int enable */
+    NOP();
 
-	* MFP_INTR_IN_SERVICE_A = -1;
-	NOP();
+    * MFP_INTR_IN_SERVICE_A = -1;
+    NOP();
 
-	* MFP_INTR_IN_SERVICE_B = -1;
-	NOP();
+    * MFP_INTR_IN_SERVICE_B = -1;
+    NOP();
 
-	xprintf("finished\r\n");
+    xprintf("finished\r\n");
 }
 
 /* ACP interrupt controller */
@@ -201,189 +201,163 @@ void acia_init()
 
 void enable_coldfire_interrupts()
 {
-	xprintf("enable interrupts: ");
-#if MACHINE_FIREBEE
-	*FPGA_INTR_CONTRL = 0L;				/* disable all interrupts */
+    xprintf("enable interrupts: ");
+#if defined(MACHINE_FIREBEE)
+    *FPGA_INTR_CONTRL = 0L;				/* disable all interrupts */
 #endif /* MACHINE_FIREBEE */
-	MCF_EPORT_EPPAR = 0xaaa8;			/* all interrupts on falling edge */
+    MCF_EPORT_EPPAR = 0xaaa8;			/* all interrupts on falling edge */
 
-#if MACHINE_FIREBEE
-	/*
-	 * TIN0 on the Coldfire is connected to the FPGA. TIN0 triggers every write
-	 * access to 0xff8201 (vbasehi), i.e. everytime the video base address is written
-	 */
-	MCF_GPT0_GMS = MCF_GPT_GMS_ICT(1) |	/* timer 0 on, video change capture on rising edge */
-			MCF_GPT_GMS_IEN |
-			MCF_GPT_GMS_TMS(1);
-										/* route GPT0 interrupt on interrupt controller */
-	MCF_INTC_ICR62 = 0x3f;				/* interrupt level 7, interrupt priority 7 */
+#if defined(MACHINE_FIREBEE)
+    /*
+     * TIN0 on the Coldfire is connected to the FPGA. TIN0 triggers every write
+     * access to 0xff8201 (vbasehi), i.e. everytime the video base address is written
+     */
+    MCF_GPT0_GMS = MCF_GPT_GMS_ICT(1) |	/* timer 0 on, video change capture on rising edge */
+            MCF_GPT_GMS_IEN |
+            MCF_GPT_GMS_TMS(1);
+                                        /* route GPT0 interrupt on interrupt controller */
+    MCF_INTC_ICR62 = 0x3f;				/* interrupt level 7, interrupt priority 7 */
 
-	*FPGA_INTR_ENABLE  = 0xfe;	/* enable int 1-7 */
-	MCF_EPORT_EPIER = 0xfe;				/* int 1-7 on */
-	MCF_EPORT_EPFR = 0xff;				/* clear all pending interrupts */
-	MCF_INTC_IMRL = 0xffffff00;			/* int 1-7 on */
-	MCF_INTC_IMRH = 0xbffffffe;			/* psc3 and timer 0 int on */
+    *FPGA_INTR_ENABLE  = 0xfe;	/* enable int 1-7 */
+    MCF_EPORT_EPIER = 0xfe;				/* int 1-7 on */
+    MCF_EPORT_EPFR = 0xff;				/* clear all pending interrupts */
+    MCF_INTC_IMRL = 0xffffff00;			/* int 1-7 on */
+    MCF_INTC_IMRH = 0xbffffffe;			/* psc3 and timer 0 int on */
 #endif
 
-	xprintf("finished\r\n");
+    xprintf("finished\r\n");
 }
 
 void disable_coldfire_interrupts()
 {
-#ifdef MACHINE_FIREBEE
-	*FPGA_INTR_ENABLE = 0;		/* disable all interrupts */
+#if defined(MACHINE_FIREBEE)
+    *FPGA_INTR_ENABLE = 0;		/* disable all interrupts */
 #endif /* MACHINE_FIREBEE */
-	MCF_EPORT_EPIER = 0x0;
-	MCF_EPORT_EPFR = 0x0;
-	MCF_INTC_IMRL = 0xfffffffe;
-	MCF_INTC_IMRH = 0xffffffff;
+
+    MCF_EPORT_EPIER = 0x0;
+    MCF_EPORT_EPFR = 0x0;
+    MCF_INTC_IMRL = 0xfffffffe;
+    MCF_INTC_IMRH = 0xffffffff;
 }
 
 
 
 NIF nif1;
-#ifdef MACHINE_M5484LITE
+#if defined(MACHINE_M5484LITE)
 NIF nif2;
 #endif
-static IP_INFO ip_info;
-static ARP_INFO	arp_info;
 
-
-void network_init(void)
+/*
+ * initialize the interrupt handler tables to dispatch interrupt requests from Coldfire devices
+ */
+void init_isr(void)
 {
-	uint8_t mac[6] = {0x00, 0xcf, 0x54, 0x12, 0x34, 0x56};
-	uint8_t bc[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; /* this is our broadcast MAC address */
-	IP_ADDR myip = {192, 168, 1, 100};
-	IP_ADDR gateway = {192, 168, 1, 1};
-	IP_ADDR netmask = {255, 255, 255, 0};
-	int vector;
-	int (*handler)(void *, void *);
+    isr_init();		/* need to call that explicitely, otherwise isr table might be full */
 
-	handler = fec0_interrupt_handler;
-	vector = 103;
-
-	isr_init();		/* need to call that explicitely, otherwise isr table might be full */
-
-	if (!isr_register_handler(ISR_DBUG_ISR, vector, handler, NULL, (void *) &nif1))
-	{
-		dbg("%s: unable to register handler for vector %d\r\n", __FUNCTION__, vector);
-		return;
-	}
+    /*
+     * register the FEC interrupt handler
+     */
+    if (!isr_register_handler(64 + INT_SOURCE_FEC0, fec0_interrupt_handler, NULL, (void *) &nif1))
+    {
+        dbg("unable to register isr for FEC0\r\n");
+        return;
+    }
 
     /*
      * Register the DMA interrupt handler
      */
-    handler = dma_interrupt_handler;
-    vector = 112;
 
-    if (!isr_register_handler(ISR_DBUG_ISR, vector, handler, NULL,NULL))
-	{
-		dbg("%s: Error: Unable to register handler for vector %s\r\n", __FUNCTION__, vector);
-		return;
-	}
+    if (!isr_register_handler(64 + INT_SOURCE_DMA, dma_interrupt_handler, NULL,NULL))
+    {
+        dbg("Error: Unable to register isr for DMA\r\n");
+        return;
+    }
 
-	nif_init(&nif1);
-	nif1.mtu = ETH_MTU;
-	nif1.send = fec0_send;
-	fec_eth_setup(0, FEC_MODE_MII, FEC_MII_100BASE_TX, FEC_MII_FULL_DUPLEX, mac);
-	// fec_eth_setup(1, FEC_MODE_MII, FEC_MII_100BASE_TX, FEC_MII_FULL_DUPLEX, mac);
-	memcpy(nif1.hwa, mac, 6);
-	memcpy(nif1.broadcast, bc, 6);
+    dma_irq_enable(5, 3);	/* TODO: need to match the FEC driver's specs in MiNT? */
 
-	dbg("%s: ethernet address is %02X:%02X:%02X:%02X:%02X:%02X\r\n", __FUNCTION__, 
-				nif1.hwa[0], nif1.hwa[1], nif1.hwa[2],
-				nif1.hwa[3], nif1.hwa[4], nif1.hwa[5]);
-	
-	timer_init(TIMER_NETWORK, TMR_INTC_LVL, TMR_INTC_PRI);
-
-	arp_init(&arp_info);
-	nif_bind_protocol(&nif1, ETH_FRM_ARP, arp_handler, (void *) &arp_info);
-
-	ip_init(&ip_info, myip, gateway, netmask);
-	nif_bind_protocol(&nif1, ETH_FRM_IP, ip_handler, (void *) &ip_info);
-
-	udp_init();
-
-	dma_irq_enable(6, 6);
-
-	set_ipl(0);
-
-	bootp_request(&nif1, 0);
-
-	fec_eth_stop(0);
+    /*
+     * register the PIC interrupt handler
+     */
+    if (isr_register_handler(64 + INT_SOURCE_PSC3, pic_interrupt_handler, NULL, NULL))
+    {
+        dbg("Error: unable to register ISR for PSC3\r\n");
+        return;
+    }
 }
 
 void BaS(void)
 {
-	uint8_t *src;
-	uint8_t *dst = (uint8_t *) TOS;
+    uint8_t *src;
+    uint8_t *dst = (uint8_t *) TOS;
 
-#if MACHINE_FIREBEE	/* LITE board has no pic and (currently) no nvram */
-	pic_init();
-	nvram_init();
+#if defined(MACHINE_FIREBEE)        /* LITE board has no pic and (currently) no nvram */
+    pic_init();
+    nvram_init();
 #endif /* MACHINE_FIREBEE */
 
-	xprintf("copy EmuTOS: ");
+    xprintf("copy EmuTOS: ");
 
-	/* copy EMUTOS */
-	src = (uint8_t *) EMUTOS;
-	dma_memcpy(dst, src, EMUTOS_SIZE);
-	xprintf("finished\r\n");
+    /* copy EMUTOS */
+    src = (uint8_t *) EMUTOS;
+    dma_memcpy(dst, src, EMUTOS_SIZE);
+    xprintf("finished\r\n");
 
-	xprintf("initialize MMU: ");
-	mmu_init();
-	xprintf("finished\r\n");
+    xprintf("initialize MMU: ");
+    mmu_init();
+    xprintf("finished\r\n");
 
-	xprintf("initialize exception vector table: ");
-	vec_init();
-	xprintf("finished\r\n");
+    xprintf("enable MMU: ");
 
-	xprintf("flush caches: ");
-	flush_and_invalidate_caches();
-	xprintf("finished\r\n");
-	xprintf("enable MMU: ");
-	MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN;			/* MMU on */
-	NOP();										/* force pipeline sync */
-	xprintf("finished\r\n");
-	
-	#ifdef MACHINE_FIREBEE
-	xprintf("IDE reset: ");
-	/* IDE reset */
-	* (volatile uint8_t *) (0xffff8802 - 2) = 14;
-	* (volatile uint8_t *) (0xffff8802 - 0) = 0x80;
-	wait(1);
-	
-	* (volatile uint8_t *) (0xffff8802 - 0) = 0;
-	
-	xprintf("finished\r\n");
-	xprintf("enable video: ");
-	/*
-	 * video setup (25MHz)
-	 */
-	* (volatile uint32_t *) (0xf0000410 + 0) = 0x032002ba;	/* horizontal 640x480 */
-	* (volatile uint32_t *) (0xf0000410 + 4) = 0x020c020a;	/* vertical 640x480 */
-	* (volatile uint32_t *) (0xf0000410 + 8) = 0x0190015d;	/* horizontal 320x240 */
-	* (volatile uint32_t *) (0xf0000410 + 12) = 0x020C020A;	/* vertical 320x230 */
+    mmu_enable();										/* force pipeline sync */
+
+    xprintf("finished\r\n");
+
+    xprintf("initialize exception vector table: ");
+    vec_init();
+    xprintf("finished\r\n");
+
+    xprintf("flush caches: ");
+    flush_and_invalidate_caches();
+    xprintf("finished\r\n");
+
+#ifdef MACHINE_FIREBEE
+    xprintf("IDE reset: ");
+    /* IDE reset */
+    * (volatile uint8_t *) (0xffff8802 - 2) = 14;
+    * (volatile uint8_t *) (0xffff8802 - 0) = 0x80;
+    wait(1);
+
+    * (volatile uint8_t *) (0xffff8802 - 0) = 0;
+
+    xprintf("finished\r\n");
+    xprintf("enable video: ");
+    /*
+     * video setup (25MHz)
+     */
+    * (volatile uint32_t *) (0xf0000410 + 0) = 0x032002ba;	/* horizontal 640x480 */
+    * (volatile uint32_t *) (0xf0000410 + 4) = 0x020c020a;	/* vertical 640x480 */
+    * (volatile uint32_t *) (0xf0000410 + 8) = 0x0190015d;	/* horizontal 320x240 */
+    * (volatile uint32_t *) (0xf0000410 + 12) = 0x020C020A;	/* vertical 320x230 */
 
 #ifdef _NOT_USED_
 //  32MHz
-	* (volatile uint32_t *) (0xf0000410 + 0) = 0x037002ba;	/* horizontal 640x480 */
-	* (volatile uint32_t *) (0xf0000410 + 4) = 0x020d020a;	/* vertical 640x480 */
-	* (volatile uint32_t *) (0xf0000410 + 8) = 0x02a001e0;	/* horizontal 320x240 */
-	* (volatile uint32_t *) (0xf0000410 + 12) = 0x05a00160;	/* vertical 320x230 */
+    * (volatile uint32_t *) (0xf0000410 + 0) = 0x037002ba;	/* horizontal 640x480 */
+    * (volatile uint32_t *) (0xf0000410 + 4) = 0x020d020a;	/* vertical 640x480 */
+    * (volatile uint32_t *) (0xf0000410 + 8) = 0x02a001e0;	/* horizontal 320x240 */
+    * (volatile uint32_t *) (0xf0000410 + 12) = 0x05a00160;	/* vertical 320x230 */
 #endif /* _NOT_USED_ */
 
-	/* fifo on, refresh on, ddrcs and cke on, video dac on */
-	* (volatile uint32_t *) (0xf0000410 - 0x20) = 0x01070002;
+    /* fifo on, refresh on, ddrcs and cke on, video dac on */
+    * (volatile uint32_t *) (0xf0000410 - 0x20) = 0x01070002;
 
-	xprintf("finished\r\n");
+    xprintf("finished\r\n");
 
-	enable_coldfire_interrupts();
+    enable_coldfire_interrupts();
 
 #ifdef _NOT_USED_
-	screen_init();
+    screen_init();
 
-	    /* experimental */
+        /* experimental */
     {
         int i;
         uint32_t *scradr = 0xd00000;
@@ -394,65 +368,64 @@ void BaS(void)
 
             for (p = scradr; p < scradr + 1024 * 150L; p++)
             {
-				*p = 0xffffffff;
-		    }
+                *p = 0xffffffff;
+            }
 
-			for (p = scradr; p < scradr + 1024 * 150L; p++)
-		    {
-				*p = 0x0;
-			}
-		}
-	}
+            for (p = scradr; p < scradr + 1024 * 150L; p++)
+            {
+                *p = 0x0;
+            }
+        }
+    }
 #endif /* _NOT_USED_ */
 
 #endif /* MACHINE_FIREBEE */
 
-	sd_card_init();
+    sd_card_init();
 
-	/*
-	 * memory setup
-	 */
-	memset((void *) 0x400, 0, 0x400);
+    /*
+     * memory setup
+     */
+    memset((void *) 0x400, 0, 0x400);
 
-#ifdef MACHINE_FIREBEE
-	/* set Falcon bus control register */
-	/* sets bit 3 and 6. Both are undefined on an original Falcon? */
+#if defined(MACHINE_FIREBEE)
+    /* set Falcon bus control register */
+    /* sets bit 3 and 6. Both are undefined on an original Falcon? */
 
-	* (volatile uint8_t *) 0xffff8007 = 0x48;
+    * (volatile uint8_t *) 0xffff8007 = 0x48;
 #endif /* MACHINE_FIREBEE */
 
-	/* ST RAM */
+    /* ST RAM */
 
-	* (uint32_t *) 0x42e = STRAM_END;	/* phystop TOS system variable */
-	* (uint32_t *) 0x420 = 0x752019f3;	/* memvalid TOS system variable */
-	* (uint32_t *) 0x43a = 0x237698aa;	/* memval2 TOS system variable */
-	* (uint32_t *) 0x51a = 0x5555aaaa;	/* memval3 TOS system variable */
+    * (uint32_t *) 0x42e = STRAM_END;	/* phystop TOS system variable */
+    * (uint32_t *) 0x420 = 0x752019f3;	/* memvalid TOS system variable */
+    * (uint32_t *) 0x43a = 0x237698aa;	/* memval2 TOS system variable */
+    * (uint32_t *) 0x51a = 0x5555aaaa;	/* memval3 TOS system variable */
 
-	/* TT-RAM */
+    /* TT-RAM */
 
-	* (uint32_t *) 0x5a4 = FASTRAM_END;	/* ramtop TOS system variable */
-	* (uint32_t *) 0x5a8 = 0x1357bd13;	/* ramvalid TOS system variable */
+    * (uint32_t *) 0x5a4 = FASTRAM_END;	/* ramtop TOS system variable */
+    * (uint32_t *) 0x5a8 = 0x1357bd13;	/* ramvalid TOS system variable */
 
-#ifdef MACHINE_FIREBEE /* m5484lite has no ACIA and no dip switch... */
-	acia_init();
+#if defined(MACHINE_FIREBEE) /* m5484lite has no ACIA and no dip switch... */
+    acia_init();
 #endif /* MACHINE_FIREBEE */
 
-	srec_execute("BASFLASH.S19");
+    srec_execute("BASFLASH.S19");
 
-	/* Jump into the OS */
-	typedef void void_func(void);
-	typedef struct {
-		void *initial_sp;
-		void_func *initial_pc;
-	} ROM_HEADER;
+    /* Jump into the OS */
+    typedef void void_func(void);
+    struct rom_header
+    {
+        void *initial_sp;
+        void_func *initial_pc;
+    };
 
-	xprintf("BaS initialization finished, enable interrupts\r\n");
-	enable_coldfire_interrupts();
+    xprintf("BaS initialization finished, enable interrupts\r\n");
+    enable_coldfire_interrupts();
+    init_isr();
 
-	//set_ipl(0);
-	network_init();
-
-	xprintf("call EmuTOS\r\n");
-	ROM_HEADER* os_header = (ROM_HEADER*)TOS;
-	os_header->initial_pc();
+    xprintf("call EmuTOS\r\n");
+    struct rom_header *os_header = (struct rom_header *) TOS;
+    os_header->initial_pc();
 }

sys/cache.c

@@ -32,7 +32,7 @@ void cacr_set(uint32_t value)
 	__asm__ __volatile__("movec	%0, cacr\n\t"
 						 : /* output */
 						 : "r" (rt_cacr)
-						 : /* clobbers */);
+						 : "memory" /* clobbers */);
 }
 
 uint32_t cacr_get(void)
@@ -42,26 +42,43 @@ uint32_t cacr_get(void)
 	return rt_cacr;
 }
 
+void disable_data_cache(void)
+{
+	flush_and_invalidate_caches();
+	cacr_set((cacr_get() | CF_CACR_DCINVA) & ~CF_CACR_DEC);
+}
+
+void disable_instruction_cache(void)
+{
+	flush_and_invalidate_caches();
+	cacr_set((cacr_get() | CF_CACR_ICINVA) & ~CF_CACR_IEC);
+}
+
+void enable_data_cache(void)
+{
+	cacr_set(cacr_get() & ~CF_CACR_DCINVA);
+}
+
 void flush_and_invalidate_caches(void)
 {
-	__asm__ (
-	"	clr.l		d0\n\t"
-	"	clr.l		d1\n\t"
-	"	move.l		d0,a0\n\t"
-	"cfa_setloop:\n\t"
-	"	cpushl		bc,(a0)				| flush\n\t"
-	"	lea			0x10(a0),a0			| index+1\n\t"
-	"	addq.l		#1,d1				| index+1\n\t"
-	"	cmpi.w		#512,d1				| all sets?\n\t"
-	"	bne.s		cfa_setloop			| no->\n\t"
-	"	clr.l		d1\n\t"
-	"	addq.l		#1,d0\n\t"
-	"	move.l		d0,a0\n\t"
-	"	cmpi.w		#4,d0				| all ways?\n\t"
-	"	bne.s		cfa_setloop			| no->\n\t"
-	/* input */	:
-	/* output */	:
-	/* clobber */	: "d0", "d1", "a0"
+	__asm__ __volatile__(
+			"	clr.l		d0                  \n\t"
+			"	clr.l		d1                  \n\t"
+			"	move.l		d0,a0               \n\t"
+			"cfa_setloop:                       \n\t"
+			"	cpushl		bc,(a0)				| flush\n\t"
+			"	lea			0x10(a0),a0			| index+1\n\t"
+			"	addq.l		#1,d1				| index+1\n\t"
+			"	cmpi.w		#512,d1				| all sets?\n\t"
+			"	bne.s		cfa_setloop			| no->\n\t"
+			"	clr.l		d1                  \n\t"
+			"	addq.l		#1,d0               \n\t"
+			"	move.l		d0,a0               \n\t"
+			"	cmpi.w		#4,d0				| all ways?\n\t"
+			"	bne.s		cfa_setloop			| no->\n\t"
+			/* input */	:
+			/* output */	:
+			/* clobber */	: "cc", "d0", "d1", "a0"
 	);
 }
 
@@ -78,28 +95,41 @@ void flush_icache_range(void *address, size_t size)
 	start_set = (uint32_t) address & _ICACHE_SET_MASK;
 	end_set = (uint32_t) endaddr & _ICACHE_SET_MASK;
 
-	if (start_set > end_set) {
+	if (start_set > end_set)
+	{
 		/* from the begining to the lowest address */
-		for (set = 0; set <= end_set; set += (0x10 - 3)) {
-			asm volatile("cpushl ic,(%0)\n\t"
-						"addq.l #1,%0\n\t"
-						"cpushl ic,(%0)\n\t"
-						"addq.l #1,%0\n\t"
-						"cpushl ic,(%0)\n\t"
-						"addq.l #1,%0\n\t"
-						"cpushl ic,(%0)" : "=a" (set) : "a" (set));
+        for (set = 0; set <= end_set; set += (0x10 - 3))
+        {
+			__asm__ __volatile__(
+						"       cpushl  ic,(%[set])         \n\t"
+						"       addq.l  #1,%[set]           \n\t"
+						"       cpushl  ic,(%[set])         \n\t"
+						"       addq.l  #1,%[set]           \n\t"
+						"       cpushl  ic,(%[set])         \n\t"
+						"       addq.l  #1,%[set]           \n\t"
+						"       cpushl  ic,(%[set])         \n\t"
+				 : /* output parameters  */
+				 : [set] "a" (set)  /* input parameters */
+				 : "cc"             /* clobbered registers */
+			);
 		}
 		/* next loop will finish the cache ie pass the hole */
 		end_set = LAST_ICACHE_ADDR;
 	}
-	for (set = start_set; set <= end_set; set += (0x10 - 3)) {
-		asm volatile("cpushl ic,(%0)\n\t"
-					"addq.l #1,%0\n\t"
-					"cpushl ic,(%0)\n\t"
-					"addq%.l #1,%0\n\t"
-					"cpushl ic,(%0)\n\t"
-					"addq.l #1,%0\n\t"
-					"cpushl ic,(%0)" : "=a" (set) : "a" (set));
+	for (set = start_set; set <= end_set; set += (0x10 - 3))
+	{
+		__asm__ __volatile__(
+					"       cpushl  ic,(%[set])             \n\t"
+					"       addq.l  #1,%[set]               \n\t"
+					"       cpushl  ic,(%[set])             \n\t"
+					"       addq.l  #1,%[set]               \n\t"
+					"       cpushl  ic,(%[set])             \n\t"
+					"       addq.l  #1,%[set]               \n\t"
+					"       cpushl  ic,(%[set])"
+					: /* output parameters */
+					: [set] "a" (set)
+					: "cc"
+		 );
 	}
 }
 
@@ -121,25 +151,91 @@ void flush_dcache_range(void *address, size_t size)
 
 	if (start_set > end_set) {
 		/* from the begining to the lowest address */
-		for (set = 0; set <= end_set; set += (0x10 - 3)) {
-			asm volatile("cpushl dc,(%0)\n\t"
-						"addq.l #1,%0\n\t"
-						"cpushl dc,(%0)\n\t"
-						"addq.l #1,%0\n\t"
-						"cpushl dc,(%0)\n\t"
-						"addq.l #1,%0\n\t"
-						"cpushl dc,(%0)" : "=a" (set) : "a" (set));
+		for (set = 0; set <= end_set; set += (0x10 - 3))
+		{
+			__asm__ __volatile__(
+						"       cpushl  dc,(%[set])         \n\t"
+						"       addq.l  #1,%[set]           \n\t"
+						"       cpushl  dc,(%[set])         \n\t"
+						"       addq.l  #1,%[set]           \n\t"
+						"       cpushl  dc,(%[set])         \n\t"
+						"       addq.l  #1,%[set]           \n\t"
+						"       cpushl  dc,(%[set])         \n\t"
+						: /* output parameters */
+						: [set] "a" (set)
+						: "cc" /* clobbered registers */
+			);
 		}
 		/* next loop will finish the cache ie pass the hole */
 		end_set = LAST_DCACHE_ADDR;
 	}
-	for (set = start_set; set <= end_set; set += (0x10 - 3)) {
-		asm volatile("cpushl dc,(%0)\n\t"
-					"addq.l #1,%0\n\t"
-					"cpushl dc,(%0)\n\t"
-					"addq%.l #1,%0\n\t"
-					"cpushl dc,(%0)\n\t"
-					"addq.l #1,%0\n\t"
-					"cpushl dc,(%0)" : "=a" (set) : "a" (set));
+	for (set = start_set; set <= end_set; set += (0x10 - 3))
+	{
+		__asm__ __volatile__(
+					"       cpushl      dc,(%[set])     \n\t"
+					"       addq.l      #1,%[set]       \n\t"
+					"       cpushl      dc,(%[set])     \n\t"
+					"       addq%.l     #1,%[set]       \n\t"
+					"       cpushl      dc,(%[set])     \n\t"
+					"       addq.l      #1,%[set]       \n\t"
+					"       cpushl      dc,(%[set])     \n\t"
+					: /* output parameters */
+					: [set] "a" (set)
+					: "cc" /* clobbered registers */
+		);
 	}
 }
+
+/*
+ * flush and invalidate a specific region from the both caches. We do not know if the area is cached
+ * at all, we do not know in which of the four ways it is cached, but we know the index where they
+ * would be cached if they are, so we only need to flush and invalidate only a subset of the 512 index
+ * entries, but all four ways.
+ */
+void flush_cache_range(void *address, size_t size)
+{
+    unsigned long set;
+    unsigned long start_set;
+    unsigned long end_set;
+    void *endaddr;
+
+    endaddr = address + size;
+    start_set = (uint32_t) address & _DCACHE_SET_MASK;
+    end_set = (uint32_t) endaddr & _DCACHE_SET_MASK;
+
+    if (start_set > end_set) {
+        /* from the begining to the lowest address */
+        for (set = 0; set <= end_set; set += (0x10 - 3))
+        {
+            __asm__ __volatile__(
+                        "       cpushl  bc,(%[set])         \n\t"
+                        "       addq.l  #1,%[set]           \n\t"
+                        "       cpushl  bc,(%[set])         \n\t"
+                        "       addq.l  #1,%[set]           \n\t"
+                        "       cpushl  bc,(%[set])         \n\t"
+                        "       addq.l  #1,%[set]           \n\t"
+                        "       cpushl  bc,(%[set])         \n\t"
+                        : /* output parameters */
+                        : [set] "a" (set)
+                        : "cc" /* clobbered registers */
+            );
+        }
+        /* next loop will finish the cache ie pass the hole */
+        end_set = LAST_DCACHE_ADDR;
+    }
+    for (set = start_set; set <= end_set; set += (0x10 - 3))
+    {
+        __asm__ __volatile__(
+                    "       cpushl      bc,(%[set])     \n\t"
+                    "       addq.l      #1,%[set]       \n\t"
+                    "       cpushl      bc,(%[set])     \n\t"
+                    "       addq%.l     #1,%[set]       \n\t"
+                    "       cpushl      bc,(%[set])     \n\t"
+                    "       addq.l      #1,%[set]       \n\t"
+                    "       cpushl      bc,(%[set])     \n\t"
+                    : /* output parameters */
+                    : [set] "a" (set)
+                    : "cc" /* clobbered registers */
+        );
+    }
+}

sys/driver_mem.c

@@ -2,7 +2,7 @@
  *	driver_mem.c
  *
  * based from Emutos / BDOS
- * 
+ *
  * Copyright (c) 2001 Lineo, Inc.
  *
  * Authors: Karl T. Braun, Martin Doering, Laurent Vogel
@@ -11,21 +11,23 @@
  * option any later version.
  */
 
-#include <stdint.h>
-#include <stdbool.h>
+#include <bas_types.h>
 #include "bas_string.h"
 #include "bas_printf.h"
 #include "usb.h"
 #include "exceptions.h"		/* set_ipl() */
 
-#if MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
 #include "firebee.h"
-#elif MACHINE_M5484LITE
+#elif defined(MACHINE_M5484LITE)
 #include "m5484l.h"
+#elif defined(MACHINE_M54455)
+#include "m54455.h"
+#else
+#error "unknown machine!"
 #endif
 
-//#define DBG_DM
-
+#define DBG_DM
 #ifdef	DBG_DM
 #define	dbg(fmt, args...)	xprintf(fmt, ##args)
 #else
@@ -67,7 +69,7 @@ static MPB pmd;
 static void *xmgetblk(void)
 {
 	int i;
-	
+
 	for (i = 0; i < MAXMD; i++)
 	{
 		if (tab_md[i].m_own == NULL)
@@ -75,7 +77,7 @@ static void *xmgetblk(void)
 			tab_md[i].m_own = (void*)1L;
 			return(&tab_md[i]);
 		}
-	}			   
+	}
 	return NULL;
 }
 
@@ -93,18 +95,18 @@ static MD *ffit(long amount, MPB *mp)
 	MD *p, *q, *p1;                    /* free list is composed of MD's */
 	int maxflg;
 	long maxval;
-	
+
 	if (amount != -1)
 	{
 		amount += 15;                  /* 16 bytes alignment */
 		amount &= 0xFFFFFFF0;
 	}
-	
+
 	if ((q = mp->mp_rover) == 0)      /* get rotating pointer */
 	{
 		return 0;
 	}
-	
+
 	maxval = 0;
 	maxflg = ((amount == -1) ? true : false) ;
 	p = q->m_link;                   /* start with next MD */
@@ -134,7 +136,7 @@ static MD *ffit(long amount, MPB *mp)
 				{
 					return(NULL);
 				}
-				
+
 				/* init new MD */
 				p1->m_length = p->m_length - amount;
 				p1->m_start = p->m_start + amount;
@@ -143,7 +145,7 @@ static MD *ffit(long amount, MPB *mp)
 				q->m_link = p1;
 			}
 			/* link allocate block into allocated list,
-			    mark owner of block, & adjust rover  */
+				mark owner of block, & adjust rover  */
 			p->m_link = mp->mp_mal;
 			mp->mp_mal = p;
 			mp->mp_rover = (q == (MD *) &mp->mp_mfl ? q->m_link : q);
@@ -153,7 +155,7 @@ static MD *ffit(long amount, MPB *mp)
 			maxval = p->m_length;
 		p = ( q=p )->m_link;
 	} while(q != mp->mp_rover);
-	
+
 	/*
 	 * return either the max, or 0 (error)
 	 */
@@ -175,7 +177,7 @@ static MD *ffit(long amount, MPB *mp)
 static void freeit(MD *m, MPB *mp)
 {
 	MD *p, *q;
-	
+
 	q = 0;
 	for (p = mp->mp_mfl; p ; p = (q = p) -> m_link)
 	{
@@ -185,7 +187,7 @@ static void freeit(MD *m, MPB *mp)
 		}
 	}
 	m->m_link = p;
-	
+
 	if (q)
 	{
 		q->m_link = m;
@@ -194,12 +196,12 @@ static void freeit(MD *m, MPB *mp)
 	{
 		mp->mp_mfl = m;
 	}
-	
+
 	if (!mp->mp_rover)
 	{
 		mp->mp_rover = m;
 	}
-	
+
 	if (p)
 	{
 		if (m->m_start + m->m_length == p->m_start)
@@ -237,7 +239,7 @@ int32_t driver_mem_free(void *addr)
 	MPB *mpb;
 	mpb = &pmd;
 	level = set_ipl(7);
-	
+
 	for(p = *(q = &mpb->mp_mal); p; p = *(q = &p->m_link))
 	{
 		if ((long) addr == p->m_start)
@@ -245,19 +247,19 @@ int32_t driver_mem_free(void *addr)
 			break;
 		}
 	}
-	
+
 	if (!p)
 	{
 		set_ipl(level);
 		return(-1);
 	}
-	
+
 	*q = p->m_link;
 	freeit(p, mpb);
 	set_ipl(level);
-	
+
 	dbg("%s: driver_mem_free(0x%08X)\r\n", __FUNCTION__, addr);
-	
+
 	return(0);
 }
 
@@ -266,33 +268,33 @@ void *driver_mem_alloc(uint32_t amount)
 	void *ret = NULL;
 	int level;
 	MD *m;
-	
+
 	if (amount == -1L)
 	{
-		return((void *)ffit(-1L, &pmd));
+		return (void *) ffit(-1L, &pmd);
 	}
-	
+
 	if (amount <= 0 )
 	{
 		return(0);
 	}
-	
+
 	if ((amount & 1))
 	{
 		amount++;
 	}
-	
+
 	level = set_ipl(7);
 	m = ffit(amount, &pmd);
-	
+
 	if (m != NULL)
 	{
-		ret = (void *)m->m_start;
+		ret = (void *) m->m_start;
 	}
 	set_ipl(level);
 	dbg("%s: driver_mem_alloc(%d) = 0x%08X\r\n", __FUNCTION__, amount, ret);
-	
-	return(ret);
+
+	return ret;
 }
 
 static int use_count = 0;
@@ -303,11 +305,11 @@ int driver_mem_init(void)
 	{
 		dbg("%s: initialise driver_mem_buffer[] at %p, size 0x%x\r\n", __FUNCTION__, driver_mem_buffer, DRIVER_MEM_BUFFER_SIZE);
 		memset(driver_mem_buffer, 0, DRIVER_MEM_BUFFER_SIZE);
-	
+
 		pmd.mp_mfl = pmd.mp_rover = &tab_md[0];
 		tab_md[0].m_link = (MD *) NULL;
 		tab_md[0].m_start = ((long) driver_mem_buffer + 15) & ~15;
-		tab_md[0].m_length = DRIVER_MEM_BUFFER_SIZE;	
+		tab_md[0].m_length = DRIVER_MEM_BUFFER_SIZE;
 		tab_md[0].m_own = (void *) 1L;
 		pmd.mp_mal = (MD *) NULL;
 		memset(driver_mem_buffer, 0, tab_md[0].m_length);
@@ -316,7 +318,8 @@ int driver_mem_init(void)
 	}
 	use_count++;
 	dbg("%s: driver_mem now has a use count of %d\r\n", __FUNCTION__, use_count);
-	return(0);
+
+	return 0;
 }
 
 void driver_mem_release(void)

sys/fault_vectors.c

@@ -192,7 +192,11 @@ void setup_vectors(void)
 	__asm__ __volatile__("clr.l		d0\n\t"\
 						 "movec.l	d0,VBR\n\t"\
 						 "nop\n\t"\
-						 "move.l	d0,_rt_vbr" ::: "d0", "memory");
+                         "move.l	d0,_rt_vbr"
+                         :                      /* outputs */
+                         :                      /* inputs */
+                         : "d0", "memory", "cc" /* clobbered registers */
+                        );
 
 	xprintf("finished.\r\n");
 }

sys/init_fpga.c

@@ -27,70 +27,84 @@
 #include "bas_printf.h"
 #include "wait.h"
 
+// #define FPGA_DEBUG
+#if defined(FPGA_DEBUG)
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
+#else
+#define dbg(format, arg...) do { ; } while (0)
+#endif
+
 #define FPGA_STATUS		(1 << 0)
 #define FPGA_CLOCK		(1 << 1)
 #define FPGA_CONFIG		(1 << 2)
 #define FPGA_DATA0		(1 << 3)
 #define FPGA_CONF_DONE	(1 << 5)
 
-extern uint8_t _FPGA_FLASH_DATA[];
-#define FPGA_FLASH_DATA	&_FPGA_FLASH_DATA[0]
-extern uint8_t _FPGA_FLASH_DATA_SIZE[];
-#define FPGA_FLASH_DATA_SIZE	((uint32_t) &_FPGA_FLASH_DATA_SIZE[0])
+extern uint8_t _FPGA_CONFIG[];
+#define FPGA_FLASH_DATA	&_FPGA_CONFIG[0]
+extern uint8_t _FPGA_CONFIG_SIZE[];
+#define FPGA_FLASH_DATA_SIZE	((uint32_t) &_FPGA_CONFIG_SIZE[0])
 
+/*
+ * flag located in processor SRAM1 that indicates that the FPGA configuration has
+ * been loaded through JTAG. init_fpga() will honour this and not overwrite config.
+ */
+extern bool _FPGA_JTAG_LOADED;
+extern long _FPGA_JTAG_VALID;
+#define VALID_JTAG		0xaffeaffe
 
-#ifdef _NOT_USED_
-void test_longword(void)
+void config_gpio_for_fpga_config(void)
 {
-	uint32_t *fpga_data = (uint32_t *) FPGA_FLASH_DATA;
-	const uint32_t *fpga_flash_data_end = (uint32_t *) FPGA_FLASH_DATA + FPGA_FLASH_DATA_SIZE;
-	do
-	{
-		uint32_t value = *fpga_data++;
-		xprintf("LONGWORDS: addr=%p, value=%08x\r", fpga_data, value);
-	} while (fpga_data < fpga_flash_data_end);
-	xprintf("finished. \r\n");
+#if defined(MACHINE_FIREBEE)
+	/*
+	 * Configure GPIO FEC1L port directions (needed to load FPGA configuration)
+	 */
+	MCF_GPIO_PDDR_FEC1L = 0 |								/* bit 7 = input */
+						  0	|								/* bit 6 = input */
+						  0 | 								/* bit 5 = input */
+						  MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 |	/* bit 4 = LED => output */
+						  MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 |	/* bit 3 = PRG_DQ0 => output */
+						  MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 |	/* bit 2 = FPGA_CONFIG => output */
+						  MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 |	/* bit 1 = PRG_CLK (FPGA) => output */
+						  0;								/* bit 0 => input */
+#endif /* MACHINE_FIREBEE */
 }
 
-void test_word(void)
+void config_gpio_for_jtag_config(void)
 {
-	uint16_t *fpga_data = (uint16_t *) FPGA_FLASH_DATA;
-	const uint16_t *fpga_flash_data_end = (uint16_t *) FPGA_FLASH_DATA + FPGA_FLASH_DATA_SIZE;
-
-	do
-	{
-		uint16_t value = *fpga_data++;
-		xprintf("WORDS: addr=%p, value=%04x\r", fpga_data, value);
-	} while (fpga_data < fpga_flash_data_end);
-	xprintf("finished. \r\n");
+	/*
+	 * configure FEC1L port directions to enable external JTAG configuration download to FPGA
+	 */
+	MCF_GPIO_PDDR_FEC1L = 0 |
+						  MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4;	/* bit 4 = LED => output */
+															/* all other bits = input */
+	/*
+	 * unfortunately, the GPIO module cannot trigger interrupts. That means CONF_DONE needs to be polled to detect
+	 * external FPGA (re)configuration and reset the system in that case. Could be done from the OS as well...
+	 */
 }
 
-void test_byte(void)
-{
-	uint8_t *fpga_data = (uint8_t *) FPGA_FLASH_DATA;
-	const uint8_t *fpga_flash_data_end = (uint8_t *) FPGA_FLASH_DATA + FPGA_FLASH_DATA_SIZE;
-
-	do
-	{
-		uint8_t value = *fpga_data++;
-		xprintf("LONGWORDS: addr=%p, value=%08x\r", fpga_data, value);
-	} while (fpga_data < fpga_flash_data_end);
-	xprintf("finished. \r\n");
-}
-#endif /* _NOT_USED_ */
-
 /*
  * load FPGA
  */
-void init_fpga(void)
+bool init_fpga(void)
 {
 	uint8_t *fpga_data;
 	volatile int32_t time, start, end;
 	int i;
 
-	xprintf("FPGA load config... ");
-	start = MCF_SLT0_SCNT; 
+	dbg("FPGA load config\r\n(_FPGA_JTAG_LOADED = %x, _FPGA_JTAG_VALID = %x)...\r\n", _FPGA_JTAG_LOADED, _FPGA_JTAG_VALID);
+	if (_FPGA_JTAG_LOADED == true && _FPGA_JTAG_VALID == VALID_JTAG)
+	{
+		dbg("detected _FPGA_JTAG_LOADED flag. Not overwriting FPGA config.\r\n");
 
+		/* reset the flag so that next boot will load config again from flash */
+		_FPGA_JTAG_LOADED = 0;
+		return true;
+	}
+	start = MCF_SLT0_SCNT;
+
+	config_gpio_for_fpga_config();
 	MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;		/* FPGA clock => low */
 
 	/* pulling FPGA_CONFIG to low resets the FPGA */
@@ -109,7 +123,7 @@ void init_fpga(void)
 	 * configuration cycle consists of 3 stages<65>reset, configuration, and initialization.
 	 * While nCONFIG is low, the device is in reset. When the device comes out of reset,
 	 * nCONFIG must be at a logic high level in order for the device to release the open-drain
- 	 * nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA
+	 * nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA
 	 * is ready to receive configuration data. Before and during configuration, all user I/O pins
 	 * are tri-stated. Stratix series, Arria series, and Cyclone series have weak pull-up resistors
 	 * on the I/O pins which are on, before and during configuration.
@@ -159,11 +173,12 @@ void init_fpga(void)
 #endif /* _NOT_USED_ */
 		end = MCF_SLT0_SCNT;
 		time = (start - end) / (SYSCLK / 1000) / 1000;
-		
+
 		xprintf("finished (took %f seconds).\r\n", time / 1000.0);
+		config_gpio_for_jtag_config();
+		return true;
 	}
-	else
-	{
-		xprintf("FAILED!\r\n");
-	}
+	xprintf("FAILED!\r\n");
+	config_gpio_for_jtag_config();
+	return false;
 }

sys/interrupts.c

@@ -3,6 +3,7 @@
  *
  * Handle interrupts, the levels.
  *
+ *
  * This file is part of BaS_gcc.
  *
  * BaS_gcc is free software: you can redistribute it and/or modify
@@ -22,21 +23,25 @@
  *      Author: Markus Fröschle
  */
 
-#include <stdint.h>
-#include <stdbool.h>
+#include <bas_types.h>
 #include "MCF5475.h"
 #include "bas_utils.h"
 #include "bas_printf.h"
+#include "bas_string.h"
 #include "exceptions.h"
 #include "interrupts.h"
 #include "bas_printf.h"
+#include "startcf.h"
+#include "cache.h"
+#include "util.h"
+#include "dma.h"
 
 extern void (*rt_vbr[])(void);
 #define VBR	rt_vbr
 
 #define IRQ_DEBUG
 #if defined(IRQ_DEBUG)
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
+#define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif
@@ -47,178 +52,388 @@ extern void (*rt_vbr[])(void);
  */
 int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority, uint8_t intr, void (*handler)(void))
 {
-	int ipl;
-	int i;
-	volatile uint8_t *ICR = &MCF_INTC_ICR01 - 1;
-	uint8_t lp;
+    int ipl;
+    int i;
+    volatile uint8_t *ICR = &MCF_INTC_ICR01 - 1;
+    uint8_t lp;
 
-	source &= 63;
-	priority &= 7;
+    source &= 63;
+    priority &= 7;
 
-	if (source < 1 || source > 63)
-	{
-		dbg("%s: interrupt source %d not defined\r\n", __FUNCTION__, source);
-		return -1;
-	}
+    if (source < 1 || source > 63)
+    {
+        dbg("interrupt source %d not defined\r\n", source);
+        return -1;
+    }
 
-	lp = MCF_INTC_ICR_IL(level) | MCF_INTC_ICR_IP(priority);
+    lp = MCF_INTC_ICR_IL(level) | MCF_INTC_ICR_IP(priority);
 
-	/* check if this combination is already set somewhere */
-	for (i = 1; i < 64; i++)
-	{
-		if (ICR[i] == lp)
-		{
-			dbg("%s: level %d and priority %d already used for interrupt source %d!\r\n", __FUNCTION__,
-					level, priority, i);
-			return -1;
-		}
-	}
+    /* check if this combination is already set somewhere */
+    for (i = 1; i < 64; i++)
+    {
+        if (ICR[i] == lp)
+        {
+            dbg("level %d and priority %d already used for interrupt source %d!\r\n",
+                    level, priority, i);
+            return -1;
+        }
+    }
 
-	/* disable interrupts */
-	ipl = set_ipl(7);
+    /* disable interrupts */
+    ipl = set_ipl(7);
 
-	VBR[64 + source] = handler;	/* first 64 vectors are system exceptions */
+    VBR[64 + source] = handler;	/* first 64 vectors are system exceptions */
 
-	/* set level and priority in interrupt controller */
-	ICR[source] = lp;
+    /* set level and priority in interrupt controller */
+    ICR[source] = lp;
 
-	/* set interrupt mask to where it was before */
-	set_ipl(ipl);
+    /* set interrupt mask to where it was before */
+    set_ipl(ipl);
 
-	return 0;
+    return 0;
 }
 
-#ifndef UIF_MAX_ISR_ENTRY
-#define UIF_MAX_ISR_ENTRY   (20)
+#ifndef MAX_ISR_ENTRY
+#define MAX_ISR_ENTRY   (20)
 #endif
 
 
-typedef struct
+struct isrentry
 {
-	int     vector;
-	int     type;
-	int     (*handler)(void *, void *);
-	void    *hdev;
-	void    *harg;
-} ISRENTRY;
-
-ISRENTRY isrtab[UIF_MAX_ISR_ENTRY];
+    int     vector;
+    int     (*handler)(void *, void *);
+    void    *hdev;
+    void    *harg;
+};
 
+static struct isrentry isrtab[MAX_ISR_ENTRY];      /* list of interrupt service routines */
 
+/*
+ * clear the table of interrupt service handlers
+ */
 void isr_init(void)
 {
-	int index;
-
-	for (index = 0; index < UIF_MAX_ISR_ENTRY; index++)
-	{
-		isrtab[index].vector = 0;
-		isrtab[index].type = 0;
-		isrtab[index].handler = 0;
-		isrtab[index].hdev = 0;
-		isrtab[index].harg = 0;
-	}
+    memset(isrtab, 0, sizeof(isrtab));
 }
 
-
-int isr_register_handler(int type, int vector, 
-		int (*handler)(void *, void *), void *hdev, void *harg)
+/*
+ * This function places an interrupt handler in the ISR table,
+ * thereby registering it so that the low-level handler may call it.
+ *
+ * The two parameters are intended for the first arg to be a
+ * pointer to the device itself, and the second a pointer to a data
+ * structure used by the device driver for that particular device.
+ */
+int isr_register_handler(int vector, int (*handler)(void *, void *), void *hdev, void *harg)
 {
-	/*
-	 * This function places an interrupt handler in the ISR table,
-	 * thereby registering it so that the low-level handler may call it.
-	 *
-	 * The two parameters are intended for the first arg to be a 
-	 * pointer to the device itself, and the second a pointer to a data 
-	 * structure used by the device driver for that particular device.
-	 */
-	int index;
+    int index;
 
-	if ((vector == 0) || 
-			((type != ISR_DBUG_ISR) && (type != ISR_USER_ISR)) ||
-			(handler == NULL))
-	{
-		dbg("%s: illegal type, vector or handler!\r\n", __FUNCTION__);
-		return false;
-	}
+    if ((vector == 0) || (handler == NULL))
+    {
+        dbg("illegal vector or handler!\r\n");
+        return false;
+    }
 
-	for (index = 0; index < UIF_MAX_ISR_ENTRY; index++)
-	{
-		if ((isrtab[index].vector == vector) &&
-				(isrtab[index].type == type))
-		{
-			/* only one entry of each type per vector */
-			dbg("%s: already set handler with this type and vector (%d, %d)\r\n", __FUNCTION__, type, vector);
-			return false;
-		}
+    for (index = 0; index < MAX_ISR_ENTRY; index++)
+    {
+        if (isrtab[index].vector == vector)
+        {
+            /* one cross each, only! */
+            dbg("already set handler with this vector (%d, %d)\r\n", vector);
+            return false;
+        }
 
-		if (isrtab[index].vector == 0)
-		{
-			isrtab[index].vector = vector;
-			isrtab[index].type = type;
-			isrtab[index].handler = handler;
-			isrtab[index].hdev = hdev;
-			isrtab[index].harg = harg;
+        if (isrtab[index].vector == 0)
+        {
+            isrtab[index].vector = vector;
+            isrtab[index].handler = handler;
+            isrtab[index].hdev = hdev;
+            isrtab[index].harg = harg;
 
-			return true;
-		}
-	}
-	dbg("%s: no available slots to register handler for vector %d\n\r", __FUNCTION__, vector);
+            return true;
+        }
+    }
+    dbg("no available slots to register handler for vector %d\n\r", vector);
 
-	return false;   /* no available slots */
+    return false;   /* no available slots */
 }
 
-void isr_remove_handler(int type, int (*handler)(void *, void *))
+void isr_remove_handler(int (*handler)(void *, void *))
 {
-	/*
-	 * This routine removes from the ISR table all
-	 * entries that matches 'type' and 'handler'.
-	 */
-	int index;
+    /*
+     * This routine removes from the ISR table all
+     * entries that matches 'handler'.
+     */
+    int index;
 
-	for (index = 0; index < UIF_MAX_ISR_ENTRY; index++)
-	{
-		if ((isrtab[index].handler == handler) && 
-				(isrtab[index].type == type))
-		{
-			isrtab[index].vector = 0;
-			isrtab[index].type = 0;
-			isrtab[index].handler = 0;
-			isrtab[index].hdev = 0;
-			isrtab[index].harg = 0;
+    for (index = 0; index < MAX_ISR_ENTRY; index++)
+    {
+        if (isrtab[index].handler == handler)
+        {
+            memset(&isrtab[index], 0, sizeof(struct isrentry));
 
-			return;
-		}
-	}
-	dbg("%s: no such handler registered (type=%d, handler=%p\r\n", __FUNCTION__, type, handler);
+            return;
+        }
+    }
+    dbg("no such handler registered (handler=%p\r\n", handler);
 }
 
-
+/*
+ * This routine searches the ISR table for an entry that matches
+ * 'vector'.  If one is found, then 'handler' is executed.
+ */
 bool isr_execute_handler(int vector)
 {
-	/*
-	 * This routine searches the ISR table for an entry that matches
-	 * 'vector'.  If one is found, then 'handler' is executed.
-	 */
-	int index;
-	bool retval = false;
+    int index;
+    bool retval = false;
 
-	/*
-	 * First locate a BaS Interrupt Service Routine handler.
-	 */
-	for (index = 0; index < UIF_MAX_ISR_ENTRY; index++)
-	{
-		if ((isrtab[index].vector == vector) &&
-				(isrtab[index].type == ISR_DBUG_ISR))
-		{
-			retval = true;
-		
-			if (isrtab[index].handler(isrtab[index].hdev, isrtab[index].harg))
-			{
-				return retval;
-			}
-		}
-	}
-	dbg("%s: no BaS isr handler for vector %d found\r\n", __FUNCTION__, vector);
-	return retval;
+    /*
+     * locate a BaS Interrupt Service Routine handler.
+     */
+    for (index = 0; index < MAX_ISR_ENTRY; index++)
+    {
+        if (isrtab[index].vector == vector)
+        {
+            retval = true;
+
+            if (isrtab[index].handler(isrtab[index].hdev, isrtab[index].harg))
+            {
+                return retval;
+            }
+        }
+    }
+    dbg("no BaS isr handler for vector %d found\r\n", vector);
+
+    return retval;
 }
 
+/*
+ * PIC interrupt handler for Firebee
+ *
+ * Handles PIC requests that come in from PSC3 serial interface. Currently, that
+ * is RTC/NVRAM requests only
+ */
+int pic_interrupt_handler(void *arg1, void *arg2)
+{
+    uint8_t rcv_byte;
+
+    rcv_byte = MCF_PSC3_PSCRB_8BIT;
+    if (rcv_byte == 2)	// PIC requests RTC data
+    {
+        uint8_t *rtc_reg = (uint8_t *) 0xffff8961;
+        uint8_t *rtc_data = (uint8_t *) 0xffff8963;
+        int index = 0;
+
+        xprintf("PIC interrupt: requesting RTC data\r\n");
+
+        MCF_PSC3_PSCTB_8BIT = 0x82;		// header byte to PIC
+        do
+        {
+            *rtc_reg = 0;
+            MCF_PSC3_PSCTB_8BIT = *rtc_data;
+        } while (index++ < 64);
+    }
+    return 1;
+}
+
+extern int32_t video_sbt;
+extern int32_t video_tlb;
+
+void video_addr_timeout(void)
+{
+    uint32_t addr = 0x0L;
+    uint32_t *src;
+    uint32_t *dst;
+    uint32_t asid;
+
+    dbg("video address timeout\r\n");
+    flush_and_invalidate_caches();
+
+    do
+    {
+        uint32_t tlb;
+        uint32_t page_attr;
+
+        /*
+         * search tlb entry id for addr (if not available, the MMU
+         * will provide a new one based on its LRU algorithm)
+         */
+        MCF_MMU_MMUAR = addr;
+        MCF_MMU_MMUOR =
+                MCF_MMU_MMUOR_STLB |
+                MCF_MMU_MMUOR_RW |
+                MCF_MMU_MMUOR_ACC;
+        NOP();
+        tlb = (MCF_MMU_MMUOR >> 16) & 0xffff;
+
+        /*
+         * retrieve tlb entry with the found TLB entry id
+         */
+        MCF_MMU_MMUAR = tlb;
+        MCF_MMU_MMUOR =
+                MCF_MMU_MMUOR_STLB |
+                MCF_MMU_MMUOR_ADR |
+                MCF_MMU_MMUOR_RW |
+                MCF_MMU_MMUOR_ACC;
+        NOP();
+
+        asid = (MCF_MMU_MMUTR >> 2) & 0x1fff;	/* fetch ASID of page */;
+        if (asid != sca_page_ID)                /* check if screen area */
+        {
+            addr += 0x100000;
+            continue;                           /* next page */
+        }
+
+        /* modify found TLB entry */
+        if (addr == 0x0)
+        {
+            page_attr =
+                MCF_MMU_MMUDR_LK |
+                MCF_MMU_MMUDR_SZ(0) |
+                MCF_MMU_MMUDR_CM(0) |
+                MCF_MMU_MMUDR_R |
+                MCF_MMU_MMUDR_W |
+                MCF_MMU_MMUDR_X;
+        }
+        else
+        {
+            page_attr =
+                MCF_MMU_MMUTR_SG |
+                MCF_MMU_MMUTR_V;
+        }
+
+
+        MCF_MMU_MMUTR = addr;
+        MCF_MMU_MMUDR = page_attr;
+        MCF_MMU_MMUOR =
+                MCF_MMU_MMUOR_STLB |
+                MCF_MMU_MMUOR_ADR |
+                MCF_MMU_MMUOR_ACC |
+                MCF_MMU_MMUOR_UAA;
+        NOP();
+
+        dst = (uint32_t *) 0x60000000 + addr;
+        src = (uint32_t *) addr;
+        while (dst < (uint32_t *) 0x60000000 + addr + 0x10000)
+        {
+            *dst++ = *src++;
+            *dst++ = *src++;
+            *dst++ = *src++;
+            *dst++ = *src++;
+        }
+
+
+
+        addr += 0x100000;
+    } while (addr < 0xd00000);
+    video_tlb = 0x2000;
+    video_sbt = 0;
+}
+
+
+/*
+ * blink the Firebee's LED to show we are still alive
+ */
+void blink_led(void)
+{
+    static uint16_t blinker = 0;
+
+    if ((blinker++ & 0x80) > 0)
+    {
+        MCF_GPIO_PODR_FEC1L |= (1 << 4);    /* LED off */
+    }
+    else
+    {
+        MCF_GPIO_PODR_FEC1L &= ~(1 << 4);   /* LED on */
+    }
+}
+
+/*
+ * Atari MFP interrupt registers.
+ *
+ * TODO: should go into a header file
+ */
+
+#define FALCON_MFP_IERA     *((volatile uint8_t *) 0xfffffa07)
+#define FALCON_MFP_IERB     *((volatile uint8_t *) 0xfffffa09)
+#define FALCON_MFP_IPRA     *((volatile uint8_t *) 0xfffffa0b)
+#define FALCON_MFP_IPRB     *((volatile uint8_t *) 0xfffffa0d)
+#define FALCON_MFP_IMRA     *((volatile uint8_t *) 0xfffffa13)
+#define FALCON_MFP_IMRB     *((volatile uint8_t *) 0xfffffa15)
+
+bool irq6_acsi_dma_interrupt(void)
+{
+    dbg("ACSI DMA interrupt\r\n");
+
+    /*
+     * TODO: implement handler
+     */
+
+    return false;
+}
+
+bool irq6_interrupt_handler(uint32_t sf1, uint32_t sf2)
+{
+    bool handled = false;
+
+    MCF_EPORT_EPFR |= (1 << 6);	/* clear int6 from edge port */
+
+    if (video_sbt != 0 && (video_sbt - 0x70000000) > MCF_SLT0_SCNT)
+    {
+        video_addr_timeout();
+        handled = true;
+    }
+
+    /*
+     * check if ACSI DMA interrupt
+     */
+
+    if (FALCON_MFP_IERA & (1 << 7))
+    {
+        /* ACSI interrupt is enabled */
+        if (FALCON_MFP_IPRA & (1 << 7))
+        {
+            irq6_acsi_dma_interrupt();
+            handled = true;
+        }
+    }
+
+    if (FALCON_MFP_IPRA || FALCON_MFP_IPRB)
+    {
+        blink_led();
+    }
+
+    return handled;
+}
+
+#if defined(MACHINE_FIREBEE)
+#define vbasehi		(* (volatile uint8_t *) 0xffff8201)
+#define vbasemid	(* (volatile uint8_t *) 0xffff8203)
+#define vbaselow	(* (volatile uint8_t *) 0xffff820d)
+
+#define vwrap		(* (volatile uint16_t *) 0xffff8210)
+#define vde			(* (volatile uint16_t *) 0xffff82aa)
+#define vdb			(* (volatile uint16_t *) 0xffff82a8)
+/*
+ * this is the higlevel interrupt service routine for gpt0 timer interrupts.
+ *
+ * It is called from handler_gpt0 in exceptions.S
+ *
+ * The gpt0 timer is not used as a timer, but as interrupt trigger by the FPGA which fires
+ * everytime the video base address high byte (0xffff8201) gets written by user code (i.e.
+ * everytime the video base address is set).
+ * The interrupt service routine checks if that page was already set as a video page (in that
+ * case it does nothing), if not (if we have a newly set page), it sets up an MMU mapping for
+ * that page (effectively rerouting any further access to Falcon video RAM to Firebee FPGA
+ * video RAM starting at 0x60000000) and copies SDRAM contents of that page to the video
+ * RAM page.
+ */
+void gpt0_interrupt_handler(void)
+{
+    dbg("screen base = 0x%x\r\n", vbasehi);
+
+    MCF_GPT0_GMS &= ~1;		/* rearm trigger */
+    NOP();
+    MCF_GPT0_GMS |= 1;
+}
+#endif /* MACHINE_FIREBEE */

sys/mmu.c

@@ -1,5 +1,6 @@
 #include "mmu.h"
 #include "acia.h"
+#include "exceptions.h"
 
 /*
  * mmu.c
@@ -56,16 +57,20 @@
 #include "firebee.h"
 #elif defined(MACHINE_M5484LITE)
 #include "m5484l.h"
+#elif defined(MACHINE_M54455)
+#include "m54455.h"
 #else
 #error "unknown machine!"
 #endif /* MACHINE_FIREBEE */
 
-//#define DEBUG_MMU
-#ifdef DEBUG_MMU
-#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg);} while(0)
+//#define DBG_MMU
+#ifdef DBG_MMU
+#define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0)
 #else
 #define dbg(format, arg...) do {;} while (0)
-#endif /* DEBUG_MMU */
+#endif /* DBG_MMU */
+#define err(format, arg...) do { xprintf("ERROR (%s()): " format, __FUNCTION__, ##arg); xprintf("system halted\r\n"); } while(0); while(1)
+
 
 /*
  * set ASID register
@@ -73,40 +78,40 @@
  */
 inline uint32_t set_asid(uint32_t value)
 {
-	extern long rt_asid;
-	uint32_t ret = rt_asid;
+    extern long rt_asid;
+    uint32_t ret = rt_asid;
 
-	__asm__ __volatile__(
-		"movec		%[value],ASID\n\t"
-		: /* no output */
-		: [value] "r" (value)
-		: 
-	);
+    __asm__ __volatile__(
+        "movec		%[value],ASID\n\t"
+        : /* no output */
+        : [value] "r" (value)
+        : "memory"
+    );
 
-	rt_asid = value;
+    rt_asid = value;
 
-	return ret;
+    return ret;
 }
 
-							
+
 /*
  * set ACRx register
  * saves new value to rt_acrx and returns former value
  */
 inline uint32_t set_acr0(uint32_t value)
 {
-	extern uint32_t rt_acr0;
-	uint32_t ret = rt_acr0;
-	
-	__asm__ __volatile__(
-		"movec		%[value],ACR0\n\t"
-		: /* not output */
-		: [value] "r" (value)
-		:
-	);
-	rt_acr0 = value;
+    extern uint32_t rt_acr0;
+    uint32_t ret = rt_acr0;
 
-	return ret;
+    __asm__ __volatile__(
+        "movec		%[value],ACR0\n\t"
+        : /* not output */
+        : [value] "r" (value)
+        : "memory"
+    );
+    rt_acr0 = value;
+
+    return ret;
 }
 
 /*
@@ -115,18 +120,18 @@ inline uint32_t set_acr0(uint32_t value)
  */
 inline uint32_t set_acr1(uint32_t value)
 {
-	extern uint32_t rt_acr1;
-	uint32_t ret = rt_acr1;
-	
-	__asm__ __volatile__(
-		"movec		%[value],ACR1\n\t"
-		: /* not output */
-		: [value] "r" (value)
-		:
-	);
-	rt_acr1 = value;
+    extern uint32_t rt_acr1;
+    uint32_t ret = rt_acr1;
 
-	return ret;
+    __asm__ __volatile__(
+        "movec		%[value],ACR1\n\t"
+        : /* not output */
+        : [value] "r" (value)
+        : "memory"
+    );
+    rt_acr1 = value;
+
+    return ret;
 }
 
 
@@ -136,18 +141,18 @@ inline uint32_t set_acr1(uint32_t value)
  */
 inline uint32_t set_acr2(uint32_t value)
 {
-	extern uint32_t rt_acr2;
-	uint32_t ret = rt_acr2;
-	
-	__asm__ __volatile__(
-		"movec		%[value],ACR2\n\t"
-		: /* not output */
-		: [value] "r" (value)
-		:
-	);
-	rt_acr2 = value;
+    extern uint32_t rt_acr2;
+    uint32_t ret = rt_acr2;
 
-	return ret;
+    __asm__ __volatile__(
+        "movec		%[value],ACR2\n\t"
+        : /* not output */
+        : [value] "r" (value)
+        : "memory"
+    );
+    rt_acr2 = value;
+
+    return ret;
 }
 
 /*
@@ -156,283 +161,558 @@ inline uint32_t set_acr2(uint32_t value)
  */
 inline uint32_t set_acr3(uint32_t value)
 {
-	extern uint32_t rt_acr3;
-	uint32_t ret = rt_acr3;
-	
-	__asm__ __volatile__(
-		"movec		%[value],ACR3\n\t"
-		: /* not output */
-		: [value] "r" (value)
-		:
-	);
-	rt_acr3 = value;
+    extern uint32_t rt_acr3;
+    uint32_t ret = rt_acr3;
 
-	return ret;
+    __asm__ __volatile__(
+        "movec		%[value],ACR3\n\t"
+        : /* not output */
+        : [value] "r" (value)
+        : "memory"
+    );
+    rt_acr3 = value;
+
+    return ret;
 }
 
 inline uint32_t set_mmubar(uint32_t value)
 {
-	extern uint32_t rt_mmubar;
-	uint32_t ret = rt_mmubar;
+    extern uint32_t rt_mmubar;
+    uint32_t ret = rt_mmubar;
 
-	__asm__ __volatile__(
-		"movec		%[value],MMUBAR\n\t"
-		: /* no output */
-		: [value] "r" (value)
-		: /* no clobber */
-	);
-	rt_mmubar = value;
-	NOP();
+    __asm__ __volatile__(
+        "movec		%[value],MMUBAR\n\t"
+        : /* no output */
+        : [value] "r" (value)
+        : "memory"
+    );
+    rt_mmubar = value;
+    NOP();
 
-	return ret;
+    return ret;
+}
+
+/*
+ * translation table for virtual address ranges. Holds the physical_offset (which must be added to a virtual
+ * address to get its physical counterpart) for memory ranges.
+ */
+struct virt_to_phys
+{
+    uint32_t start_address;
+    uint32_t length;
+    uint32_t physical_offset;
+};
+
+static struct virt_to_phys translation[] =
+{
+    /* virtual  , length    , offset    */
+    { 0x00000000, 0x00e00000, 0x60000000 },     /* map first 14 MByte to first 14 Mb of video ram */
+    { 0x00e00000, 0x00100000, 0x00000000 },     /* map TOS to SDRAM */
+    { 0x00f00000, 0x00100000, 0xff000000 },     /* map Falcon I/O area to FPGA */
+    { 0x01000000, 0x1f000000, 0x00000000 },     /* map rest of ram virt = phys */
+};
+static int num_translations = sizeof(translation) / sizeof(struct virt_to_phys);
+
+static inline uint32_t lookup_phys(uint32_t virt)
+{
+    int i;
+
+    for (i = 0; i < num_translations; i++)
+    {
+        if (virt >= translation[i].start_address && virt < translation[i].start_address + translation[i].length)
+        {
+            return virt + translation[i].physical_offset;
+        }
+    }
+    err("virtual address 0x%lx not found in translation table!\r\n", virt);
+    return -1;
+}
+
+struct page_descriptor
+{
+    uint8_t cache_mode          : 2;
+    uint8_t supervisor_protect  : 1;
+    uint8_t read                : 1;
+    uint8_t write               : 1;
+    uint8_t execute             : 1;
+    uint8_t global              : 1;
+    uint8_t locked              : 1;
+};
+
+static struct page_descriptor pages[65536];   /* 512 Mb RAM */
+
+/*
+ * map a page of memory using virt addresses with the Coldfire MMU.
+ *
+ * Theory of operation: the Coldfire MMU in the Firebee has 64 TLB entries, 32 for data (DTLB), 32 for
+ * instructions (ITLB). Mappings can either be done locked (normal MMU TLB misses will not consider them
+ * for replacement) or unlocked (mappings will reallocate using a LRU scheme when the MMU runs out of
+ * TLB entries). For proper operation, the MMU needs at least two ITLBs and/or four free/allocatable DTLBs
+ * per instruction as a minimum, more for performance. Thus locked pages (that can't be touched by the
+ * LRU algorithm) should be used sparsingly.
+ *
+ *
+ */
+int mmu_map_8k_page(uint32_t virt, uint8_t asid)
+{
+    const uint32_t size_mask = 0xffffe000;                      /* 8k pagesize */
+    int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE;	/* index into page_descriptor array */
+    struct page_descriptor *page = &pages[page_index];          /* attributes of page to map */
+
+    uint32_t phys = lookup_phys(virt);                          /* virtual to physical translation of page */
+
+    if (phys == -1)
+        return 0;
+
+#ifdef DBG_MMU
+    register int sp asm("sp");
+    dbg("page_descriptor: 0x%02x, ssp = 0x%08x\r\n", * (uint8_t *) page, sp);
+#endif /* DBG_MMU */
+    /*
+     * add page to TLB
+     */
+    MCF_MMU_MMUTR = (virt & 0xfffffc00) |                           /* virtual address */
+        MCF_MMU_MMUTR_ID(asid) |        							/* address space id (ASID) */
+        (page->global ? MCF_MMU_MMUTR_SG : 0) |						/* shared global */
+        MCF_MMU_MMUTR_V;											/* valid */
+
+    MCF_MMU_MMUDR = (phys & 0xfffffc00) |                 			/* physical address */
+        MCF_MMU_MMUDR_SZ(MMU_PAGE_SIZE_8K) |						/* page size */
+        MCF_MMU_MMUDR_CM(page->cache_mode) |                        /* cache mode */
+        (page->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) |         /* supervisor protect */
+        (page->read ? MCF_MMU_MMUDR_R : 0) |                    	/* read access enable */
+        (page->write ? MCF_MMU_MMUDR_W : 0) |                       /* write access enable */
+        (page->execute ? MCF_MMU_MMUDR_X : 0) |                     /* execute access enable */
+        (page->locked ? MCF_MMU_MMUDR_LK : 0);
+
+    MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
+        MCF_MMU_MMUOR_ACC |     			/* access TLB */
+        MCF_MMU_MMUOR_UAA;      			/* update allocation address field */
+    dbg("ITLB: MCF_MMU_MMUOR = %08x\r\n", MCF_MMU_MMUOR);
+
+    MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
+        MCF_MMU_MMUOR_UAA;					/* update allocation address field */
+
+    dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt & size_mask, phys & size_mask);
+
+    dbg("DTLB: MCF_MMU_MMUOR = %08x\r\n", MCF_MMU_MMUOR);
+
+    return 1;
+}
+
+int mmu_map_8k_instruction_page(uint32_t virt, uint8_t asid)
+{
+    const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1);       /* 8k pagesize */
+    int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE;	/* index into page_descriptor array */
+    struct page_descriptor *page = &pages[page_index];          /* attributes of page to map */
+    int ipl;
+    uint32_t phys = lookup_phys(virt);                          /* virtual to physical translation of page */
+
+    if (phys == -1)
+        return 0;
+
+#ifdef DBG_MMU
+    register int sp asm("sp");
+    dbg("page_descriptor: 0x%02x, ssp = 0x%08x\r\n", * (uint8_t *) page, sp);
+#endif /* DBG_MMU */
+
+    /*
+     * add page to TLB
+     */
+
+    ipl = set_ipl(7);                                               /* do not disturb */
+
+    MCF_MMU_MMUAR = (virt & size_mask);
+
+    MCF_MMU_MMUTR = (virt & size_mask) |                            /* virtual address */
+        MCF_MMU_MMUTR_ID(asid) |        							/* address space id (ASID) */
+        (page->global ? MCF_MMU_MMUTR_SG : 0) |						/* shared global */
+        MCF_MMU_MMUTR_V;											/* valid */
+
+    __asm__ __volatile("" : : : "memory");                          /* MMU commands must be exactly in sequence */
+
+    MCF_MMU_MMUDR = (phys & size_mask) |                 			/* physical address */
+        MCF_MMU_MMUDR_SZ(MMU_PAGE_SIZE_8K) |						/* page size */
+        MCF_MMU_MMUDR_CM(page->cache_mode) |                        /* cache mode */
+        (page->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) |         /* supervisor protect */
+        (page->read ? MCF_MMU_MMUDR_R : 0) |                    	/* read access enable */
+        (page->write ? MCF_MMU_MMUDR_W : 0) |                       /* write access enable */
+        (page->execute ? MCF_MMU_MMUDR_X : 0) |                     /* execute access enable */
+        (page->locked ? MCF_MMU_MMUDR_LK : 0);
+
+    __asm__ __volatile("" : : : "memory");                          /* MMU commands must be exactly in sequence */
+
+    MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
+        MCF_MMU_MMUOR_ACC |     			/* access TLB */
+        MCF_MMU_MMUOR_UAA;      			/* update allocation address field */
+
+    __asm__ __volatile("" : : : "memory");                          /* MMU commands must be exactly in sequence */
+
+    set_ipl(ipl);
+
+    dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt & size_mask, phys & size_mask);
+
+    dbg("ITLB: MCF_MMU_MMUOR = %08x\r\n", MCF_MMU_MMUOR);
+    return 1;
+}
+
+int mmu_map_8k_data_page(uint32_t virt, uint8_t asid)
+{
+    uint16_t ipl;
+    const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1);       /* 8k pagesize */
+    int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE;	/* index into page_descriptor array */
+    struct page_descriptor *page = &pages[page_index];          /* attributes of page to map */
+
+    uint32_t phys = lookup_phys(virt);                          /* virtual to physical translation of page */
+
+    if (phys == -1)
+        return 0;
+
+#ifdef DBG_MMU
+    register int sp asm("sp");
+    dbg("page_descriptor: 0x%02x, ssp = 0x%08x\r\n", * (uint8_t *) page, sp);
+#endif /* DBG_MMU */
+
+    /*
+     * add page to TLB
+     */
+
+    ipl = set_ipl(7);                                               /* do not disturb */
+
+    MCF_MMU_MMUTR = (virt & size_mask) |                            /* virtual address */
+        MCF_MMU_MMUTR_ID(asid) |        							/* address space id (ASID) */
+        (page->global ? MCF_MMU_MMUTR_SG : 0) |						/* shared global */
+        MCF_MMU_MMUTR_V;											/* valid */
+
+    MCF_MMU_MMUDR = (phys & size_mask) |                 			/* physical address */
+        MCF_MMU_MMUDR_SZ(MMU_PAGE_SIZE_8K) |						/* page size */
+        MCF_MMU_MMUDR_CM(page->cache_mode) |                        /* cache mode */
+        (page->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) |         /* supervisor protect */
+        (page->read ? MCF_MMU_MMUDR_R : 0) |                    	/* read access enable */
+        (page->write ? MCF_MMU_MMUDR_W : 0) |                       /* write access enable */
+        (page->execute ? MCF_MMU_MMUDR_X : 0) |                     /* execute access enable */
+        (page->locked ? MCF_MMU_MMUDR_LK : 0);
+
+    MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
+        MCF_MMU_MMUOR_UAA;					/* update allocation address field */
+
+    set_ipl(ipl);
+    dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt & size_mask, phys & size_mask);
+
+    dbg("DTLB: MCF_MMU_MMUOR = %08x\r\n", MCF_MMU_MMUOR);
+
+    return 1;
+}
+
+/*
+ * map a page of memory using virt and phys as addresses with the Coldfire MMU.
+ *
+ * Theory of operation: the Coldfire MMU in the Firebee has 64 TLB entries, 32 for data (DTLB), 32 for
+ * instructions (ITLB). Mappings can either be done locked (normal MMU TLB misses will not consider them
+ * for replacement) or unlocked (mappings will reallocate using a LRU scheme when the MMU runs out of
+ * TLB entries). For proper operation, the MMU needs at least two ITLBs and/or four free/allocatable DTLBs
+ * per instruction as a minimum, more for performance. Thus locked pages (that can't be touched by the
+ * LRU algorithm) should be used sparsingly.
+ *
+ *
+ */
+int mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct page_descriptor *flags)
+{
+    int size_mask;
+    int ipl;
+
+    switch (sz)
+    {
+        case MMU_PAGE_SIZE_1M:
+            size_mask = ~ (0x00010000 - 1);
+            break;
+
+        case MMU_PAGE_SIZE_8K:
+            size_mask = ~ (0x2000 - 1);
+            break;
+
+        case MMU_PAGE_SIZE_4K:
+            size_mask = ~ (0x1000 - 1);
+            break;
+
+        case MMU_PAGE_SIZE_1K:
+            size_mask = ~ (0x400 - 1);
+            break;
+
+        default:
+            err("illegal map size %d\r\n", sz);
+    }
+
+    /*
+     * add page to TLB
+     */
+
+    ipl = set_ipl(7);
+
+    MCF_MMU_MMUTR = ((uint32_t) virt & size_mask) |					/* virtual address */
+        MCF_MMU_MMUTR_ID(page_id) |                                 /* address space id (ASID) */
+        (flags->global ? MCF_MMU_MMUTR_SG : 0) |					/* shared global */
+        MCF_MMU_MMUTR_V;											/* valid */
+    NOP();
+
+    MCF_MMU_MMUDR = ((uint32_t) phys & size_mask) |					/* physical address */
+        MCF_MMU_MMUDR_SZ(sz) |										/* page size */
+        MCF_MMU_MMUDR_CM(flags->cache_mode) |
+        (flags->read ? MCF_MMU_MMUDR_R : 0) |                       /* read access enable */
+        (flags->write ? MCF_MMU_MMUDR_W : 0) |                      /* write access enable */
+        (flags->execute ? MCF_MMU_MMUDR_X : 0) |                    /* execute access enable */
+        (flags->locked ? MCF_MMU_MMUDR_LK : 0);
+    NOP();
+
+    MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
+        MCF_MMU_MMUOR_UAA;					/* update allocation address field */
+    NOP();
+
+    MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
+        MCF_MMU_MMUOR_ACC |     			/* access TLB */
+        MCF_MMU_MMUOR_UAA;      			/* update allocation address field */
+
+    set_ipl(ipl);
+
+    dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt, phys);
+
+    return 1;
 }
 
 void mmu_init(void)
 {
-	extern uint8_t _MMUBAR[];
-	uint32_t MMUBAR = (uint32_t) &_MMUBAR[0];
-	extern uint8_t _TOS[];
-	uint32_t TOS = (uint32_t) &_TOS[0];
-	
-	set_asid(0);			/* do not use address extension (ASID provides virtual 48 bit addresses */
+    extern uint8_t _MMUBAR[];
+    uint32_t MMUBAR = (uint32_t) &_MMUBAR[0];
+    struct page_descriptor flags;
+    int i;
 
-	/* set data access attributes in ACR0 and ACR1 */
-	set_acr0(ACR_W(0) |								/* read and write accesses permitted */
-			ACR_SP(0) |								/* supervisor and user mode access permitted */
-			ACR_CM(ACR_CM_CACHE_INH_PRECISE) |		/* cache inhibit, precise */
-			ACR_AMM(0) |							/* control region > 16 MB */
-			ACR_S(ACR_S_ALL) |						/* match addresses in user and supervisor mode */
-			ACR_E(1) |								/* enable ACR */
-#if MACHINE_FIREBEE
-			ACR_ADMSK(0x3f) |						/* cover 1GB area from 0xc0000000 to 0xffffffff */
-			ACR_BA(0xc0000000));					/* (equals area from 3 to 4 GB */
-#elif MACHINE_M5484LITE
-			ACR_ADMSK(0x7f) |						/* cover 2 GB area from 0x80000000 to 0xffffffff */
-			ACR_BA(0x80000000));
-#endif /* MACHINE_FIREBEE */
-	
-	// set_acr1(0x601fc000);
-	set_acr1(ACR_W(0) |
-			ACR_SP(0) |
-			ACR_CM(0) |
-#if MACHINE_FIREBEE
-			ACR_CM(ACR_CM_CACHEABLE_WT) |			/* video RAM on the Firebee */
-#elif MACHINE_M5484LITE
-			ACR_CM(ACR_CM_CACHE_INH_PRECISE) |		/* Compact Flash on the M548xLITE */
-#endif /* MACHINE_FIREBEE */
-			ACR_AMM(0) |
-			ACR_S(ACR_S_ALL) |
-			ACR_E(1) |
-			ACR_ADMSK(0x1f) |
-			ACR_BA(0x60000000));
-	
-	/* set instruction access attributes in ACR2 and ACR3 */
+    /*
+     * clear all MMU TLB entries first
+     */
+    MCF_MMU_MMUOR = MCF_MMU_MMUOR_CA;       /* clears _all_ TLBs (including locked ones) */
+    NOP();
 
-	//set_acr2(0xe007c400);
-	set_acr2(ACR_W(0) |
-			ACR_SP(0) |
-			ACR_CM(0) |
-			ACR_CM(ACR_CM_CACHEABLE_WT) |
-			ACR_AMM(1) |
-			ACR_S(ACR_S_ALL) |
-			ACR_E(1) |
-			ACR_ADMSK(0x7) |
-			ACR_BA(0xe0000000));
+    /*
+     * prelaminary initialization of page descriptor 0 (root) table
+     */
+    for (i = 0; i < sizeof(pages) / sizeof(struct page_descriptor); i++)
+    {
+        uint32_t addr = i * DEFAULT_PAGE_SIZE;
 
-	/* disable ACR3 */
-	set_acr3(0x0);
+        if (addr >= 0x00f00000 && addr < 0x00ffffff)
+        {
+            pages[i].cache_mode = CACHE_NOCACHE_PRECISE;
+            pages[i].execute = 0;
+            pages[i].read = 1;
+            pages[i].write = 1;
+            pages[i].execute = 0;
+            pages[i].global = 1;
+            pages[i].supervisor_protect = 1;
+        }
+        else if (addr >= 0x0 && addr < 0x00e00000)      /* ST-RAM, potential video memory */
+        {
+            pages[i].cache_mode = CACHE_WRITETHROUGH;
+            pages[i].execute = 1;
+            pages[i].supervisor_protect = 0;
+            pages[i].read = 1;
+            pages[i].write = 1;
+            pages[i].execute = 1;
+            pages[i].global = 1;
+        }
+        else if (addr >= 0x00e00000 && addr < 0x00f00000)      /* EmuTOS */
+        {
+            pages[i].cache_mode = CACHE_COPYBACK;
+            pages[i].execute = 1;
+            pages[i].supervisor_protect = 1;
+            pages[i].read = 1;
+            pages[i].write = 0;
+            pages[i].execute = 1;
+            pages[i].global = 1;
+        }
+        else
+        {
+            pages[i].cache_mode = CACHE_COPYBACK;
+            pages[i].execute = 1;
+            pages[i].read = 1;
+            pages[i].write = 1;
+            pages[i].supervisor_protect = 0;
+            pages[i].global = 1;
+        }
+        pages[i].locked = 0;				/* not locked */
+        pages[0].supervisor_protect = 0;    /* protect system vectors */
+    }
 
-	set_mmubar(MMUBAR + 1);		/* set and enable MMUBAR */
+    set_asid(0);			/* do not use address extension (ASID provides virtual 48 bit addresses) yet */
 
-	/* clear all MMU TLB entries */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_CA;
 
-	/* create locked TLB entries */
-
-	/*
-	 * 0x0000'0000 - 0x000F'FFFF (first MB of physical memory) locked virtual = physical
-	 */
-	MCF_MMU_MMUTR = 0x0 | 					/* virtual address */
-					MCF_MMU_MMUTR_SG |		/* shared global */
-					MCF_MMU_MMUTR_V;		/* valid */
-	MCF_MMU_MMUDR = 0x0 |					/* physical address */
-					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
-					MCF_MMU_MMUDR_CM(0x1) |	/* cacheable, copyback */
-					MCF_MMU_MMUDR_R |		/* read access enable */
-					MCF_MMU_MMUDR_W |		/* write access enable */
-					MCF_MMU_MMUDR_X | 		/* execute access enable */
-					MCF_MMU_MMUDR_LK;		/* lock entry */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
-					MCF_MMU_MMUOR_UAA;		/* update allocation address field */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
-					MCF_MMU_MMUOR_ACC |     /* access TLB */
-					MCF_MMU_MMUOR_UAA;      /* update allocation address field */
-
-	/*
-	 * 0x00d0'0000 - 0x00df'ffff (last megabyte of ST RAM = Falcon video memory) locked ID = 6
-	 * mapped to physical address 0x60d0'0000 (FPGA video memory)
-	 * video RAM: read write execute normal write true
-	 */
-	
-	MCF_MMU_MMUTR = 0x00d00000 |			/* virtual address */
+    /* set data access attributes in ACR0 and ACR1 */
+    set_acr0(ACR_W(0) |								/* read and write accesses permitted */
+            ACR_SP(0) |								/* supervisor and user mode access permitted */
+            ACR_CM(ACR_CM_CACHE_INH_PRECISE) |		/* cache inhibit, precise (i/o area!) */
+            ACR_AMM(0) |							/* control region > 16 MB */
+            ACR_S(ACR_S_ALL) |						/* match addresses in user and supervisor mode */
+            ACR_E(1) |								/* enable ACR */
 #if defined(MACHINE_FIREBEE)
-					MCF_MMU_MMUTR_ID(SCA_PAGE_ID) |
-#endif /* MACHINE_FIREBEE */
-					MCF_MMU_MMUTR_SG |		/* shared global */
-					MCF_MMU_MMUTR_V;		/* valid */
-#if defined(MACHINE_FIREBEE)
-					/* map FPGA video memory for FireBee only */
-	MCF_MMU_MMUDR = 0x60d00000 |			/* physical address */
+            ACR_ADMSK(0x7f) |						/* cover 2GB area from 0x80000000 to 0xffffffff */
+            ACR_BA(0x80000000));					/* (equals area from 3 to 4 GB */
 #elif defined(MACHINE_M5484LITE)
-	MCF_MMU_MMUDR = 0x00d00000 |			/* physical address */
+            ACR_ADMSK(0x7f) |						/* cover 2 GB area from 0x80000000 to 0xffffffff */
+            ACR_BA(0x80000000));
+#elif defined(MACHINE_M54455)
+            ACR_ADMSK(0x7f) |
+            ACR_BA(0x80000000));					/* FIXME: not determined yet for this machine */
+#else
+#error unknown machine!
 #endif /* MACHINE_FIREBEE */
-					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
-					MCF_MMU_MMUDR_CM(0x0) |	/* cachable writethrough */
-					/* caveat: can't be supervisor protected since TOS puts the application stack there! */
-					//MCF_MMU_MMUDR_SP |		/* supervisor protect */
-					MCF_MMU_MMUDR_R |		/* read access enable */
-					MCF_MMU_MMUDR_W |		/* write access enable */
-					MCF_MMU_MMUDR_X |		/* execute access enable */
-					MCF_MMU_MMUDR_LK;		/* lock entry */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
-					MCF_MMU_MMUOR_UAA;		/* update allocation address field */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
-					MCF_MMU_MMUOR_ACC |     /* access TLB */
-					MCF_MMU_MMUOR_UAA;      /* update allocation address field */
 
+
+
+    // set_acr1(0x601fc000);
+    set_acr1(ACR_W(0) |
+            ACR_SP(0) |
+            ACR_CM(0) |
 #if defined(MACHINE_FIREBEE)
-	video_tlb = 0x2000;						/* set page as video page */
-	video_sbt = 0x0;						/* clear time */
+            ACR_CM(ACR_CM_CACHE_INH_PRECISE) |		/* ST RAM on the Firebee */
+#elif defined(MACHINE_M5484LITE)
+            ACR_CM(ACR_CM_CACHE_INH_PRECISE) |		/* Compact Flash on the M548xLITE */
+#elif defined(MACHINE_M54455)
+            ACR_CM(ACR_CM_CACHE_INH_PRECISE) |		/* FIXME: not determined yet for this machine */
+#else
+#error unknown machine!
 #endif /* MACHINE_FIREBEE */
+            ACR_AMM(0) |
+            ACR_S(ACR_S_ALL) |
+            ACR_E(1) |
+            ACR_ADMSK(0x7f) |
+            ACR_BA(0x00100000));
 
-	/*
-	 * Make the TOS (in SDRAM) read-only
-	 * This maps virtual 0x00e0'0000 - 0x00ef'ffff to the same virtual address
-	 */
-	MCF_MMU_MMUTR = TOS |					/* virtual address */
-					MCF_MMU_MMUTR_SG |		/* shared global */
-					MCF_MMU_MMUTR_V;		/* valid */
-	MCF_MMU_MMUDR = TOS |					/* physical address */
-					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
-					MCF_MMU_MMUDR_CM(0x1) |	/* cachable copyback */
-					MCF_MMU_MMUDR_R |		/* read access enable */
-					//MCF_MMU_MMUDR_W |		/* write access enable (FIXME: for now) */
-					MCF_MMU_MMUDR_X |		/* execute access enable */
-					MCF_MMU_MMUDR_LK;		/* lock entry */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
-					MCF_MMU_MMUOR_UAA;		/* update allocation address field */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
-					MCF_MMU_MMUOR_ACC |     /* access TLB */
-					MCF_MMU_MMUOR_UAA;      /* update allocation address field */
+#ifdef _NOT_USED_
+    /* set instruction access attributes in ACR2 and ACR3 */
 
-#if MACHINE_FIREBEE
-	/*
-	 * Map FireBee I/O area (0xfff0'0000 - 0xffff'ffff physical) to the Falcon-compatible I/O
-	 * area (0x00f0'0000 - 0x00ff'ffff virtual) for the FireBee
-	 */
+    //set_acr2(0xe007c400);							/* flash area */
+    set_acr2(ACR_W(0) |
+            ACR_SP(0) |
+            ACR_CM(0) |
+            ACR_CM(ACR_CM_CACHE_INH_PRECISE) |
+            ACR_AMM(1) |
+            ACR_S(ACR_S_ALL) |
+            ACR_E(1) |
+            ACR_ADMSK(0x7) |
+            ACR_BA(0xe0000000));
+#endif /* _NOT_USED_ */
 
-	MCF_MMU_MMUTR = 0x00f00000 |			/* virtual address */
-					MCF_MMU_MMUTR_SG |		/* shared global */
-					MCF_MMU_MMUTR_V;		/* valid */
-	MCF_MMU_MMUDR = 0xfff00000 |			/* physical address */
-					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
-					MCF_MMU_MMUDR_CM(0x2) |	/* nocache precise */
-					MCF_MMU_MMUDR_SP |		/* supervisor protect */
-					MCF_MMU_MMUDR_R |		/* read access enable */
-					MCF_MMU_MMUDR_W |		/* write access enable */
-					MCF_MMU_MMUDR_X |		/* execute access enable */
-					MCF_MMU_MMUDR_LK;		/* lock entry */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
-					MCF_MMU_MMUOR_UAA;		/* update allocation address field */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
-					MCF_MMU_MMUOR_ACC |     /* access TLB */
-					MCF_MMU_MMUOR_UAA;      /* update allocation address field */
-#endif /* MACHINE_FIREBEE */
+    set_acr1(0x0);
+    set_acr2(0x0);
+    /* disable ACR3 */
+    set_acr3(0x0);
 
-	/*
-	 * Map (locked) the second last MB of physical SDRAM (this is where BaS .data and .bss reside) to the same
-	 * virtual address. This is also used when BaS is in RAM
-	 */
+    set_mmubar(MMUBAR + 1);		/* set and enable MMUBAR */
 
-	MCF_MMU_MMUTR = (SDRAM_START + SDRAM_SIZE - 0x00200000) |	/* virtual address */
-					MCF_MMU_MMUTR_SG |		/* shared global */
-					MCF_MMU_MMUTR_V;		/* valid */
-	MCF_MMU_MMUDR = (SDRAM_START + SDRAM_SIZE - 0x00200000) |	/* physical address */
-					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
-					MCF_MMU_MMUDR_CM(0x0) |	/* cacheable writethrough */
-					MCF_MMU_MMUDR_SP |		/* supervisor protect */
-					MCF_MMU_MMUDR_R |		/* read access enable */
-					MCF_MMU_MMUDR_W |		/* write access enable */
-					MCF_MMU_MMUDR_X |		/* execute access enable */
-					MCF_MMU_MMUDR_LK;		/* lock entry */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
-					MCF_MMU_MMUOR_UAA;		/* update allocation address field */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
-					MCF_MMU_MMUOR_ACC |     /* access TLB */
-					MCF_MMU_MMUOR_UAA;      /* update allocation address field */
-					
-	/*
-	 * Map (locked) the very last MB of physical SDRAM (this is where the driver buffers reside) to the same
-	 * virtual address. Used uncached for drivers.
-	 */
+    /* clear all MMU TLB entries */
+    MCF_MMU_MMUOR = MCF_MMU_MMUOR_CA;
 
-	MCF_MMU_MMUTR = (SDRAM_START + SDRAM_SIZE - 0x00100000) |	/* virtual address */
-					MCF_MMU_MMUTR_SG |		/* shared global */
-					MCF_MMU_MMUTR_V;		/* valid */
-	MCF_MMU_MMUDR = (SDRAM_START + SDRAM_SIZE - 0x00100000) |	/* physical address */
-					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
-					MCF_MMU_MMUDR_CM(0x2) |	/* nocache precise */
-					MCF_MMU_MMUDR_SP |		/* supervisor protect */
-					MCF_MMU_MMUDR_R |		/* read access enable */
-					MCF_MMU_MMUDR_W |		/* write access enable */
-					//MCF_MMU_MMUDR_X |		/* execute access enable */
-					MCF_MMU_MMUDR_LK;		/* lock entry */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
-					MCF_MMU_MMUOR_UAA;		/* update allocation address field */
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
-					MCF_MMU_MMUOR_ACC |     /* access TLB */
-					MCF_MMU_MMUOR_UAA;      /* update allocation address field */
+    /* create locked TLB entries */
+
+    /*
+     * Map (locked) the second last MB of physical SDRAM (this is where BaS .data and .bss reside) to the same
+     * virtual address. This is also used (completely) when BaS is in RAM
+     */
+    flags.cache_mode = CACHE_NOCACHE_PRECISE;
+    flags.read = 1;
+    flags.write = 1;
+    flags.execute = 1;
+    flags.supervisor_protect = 1;		/* supervisor access only */
+    flags.locked = 1;
+    mmu_map_page(SDRAM_START + SDRAM_SIZE - 0x00200000, SDRAM_START + SDRAM_SIZE - 0x00200000, 0, MMU_PAGE_SIZE_1M, &flags);
+
+    /*
+     * map EmuTOS (locked for now)
+     */
+    flags.read = 1;
+    flags.write = 1;
+    flags.execute = 1;
+    flags.locked = 1;
+    //mmu_map_page(0xe00000, 0xe00000, MMU_PAGE_SIZE_1M, 0, &flags);
+
+    /*
+     * Map (locked) the very last MB of physical SDRAM (this is where the driver buffers reside) to the same
+     * virtual address. Used uncached for drivers.
+     */
+    flags.cache_mode = CACHE_NOCACHE_PRECISE;
+    flags.read = 1;
+    flags.write = 1;
+    flags.execute = 0;
+    flags.supervisor_protect = 1;
+    flags.locked = 1;
+    mmu_map_page(SDRAM_START + SDRAM_SIZE - 0x00100000, SDRAM_START + SDRAM_SIZE - 0x00100000, 0, MMU_PAGE_SIZE_1M, &flags);
 }
 
-void mmutr_miss(uint32_t address)
+/*
+ * enable the MMU. The Coldfire MMU can be used in two different modes
+ * ... FIXME:
+ */
+void mmu_enable(void)
 {
-	dbg("MMU TLB MISS at 0x%08x\r\n", address);
-	flush_and_invalidate_caches();
+    MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN;			/* MMU on */
+    NOP();                                      /* force pipeline sync */
+}
 
-	switch (address)
-	{
-		case keyctl:
-		case keybd:
-			/* do something to emulate the IKBD access */
-			dbg("IKBD access\r\n");
-			break;
+#ifdef DBG_MMU
+void verify_mapping(uint32_t address)
+{
+    /* retrieve mapped page from MMU and make sure everything is correct */
+    int ds;
 
-		case midictl:
-		case midi:
-			/* do something to emulate MIDI access */
-			dbg("MIDI ACIA access\r\n");
-			break;
+    ds = * (int *) address;
+    dbg("found 0x%08x at address\r\n", ds);
+}
+#endif /* DBG_MMU */
 
-		default:
-			/* add missed page to TLB */
-			MCF_MMU_MMUTR = (address & 0xfff00000) | /* virtual aligned to 1M */
-							MCF_MMU_MMUTR_SG |		/* shared global */
-							MCF_MMU_MMUTR_V;		/* valid */
+uint32_t mmutr_miss(uint32_t mmu_sr, uint32_t fault_address, uint32_t pc,
+                uint32_t format_status)
+{
+    uint32_t fault = format_status & 0x0c030000;
 
-			MCF_MMU_MMUDR = (address & 0xfff00000) |	/* physical aligned to 1M */
-							MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
-							MCF_MMU_MMUDR_CM(0x1) |	/* cacheable copyback */
-							MCF_MMU_MMUDR_R |		/* read access enable */
-							MCF_MMU_MMUDR_W |		/* write access enable */
-							MCF_MMU_MMUDR_X;		/* execute access enable */
+    switch (fault)
+    {
+        /* if we have a real TLB miss, map the offending page */
 
-			MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
-							MCF_MMU_MMUOR_UAA;		/* update allocation address field */
+        case 0x04010000:    /* TLB miss on opword of instruction fetch */
+        case 0x04020000:    /* TLB miss on extension word of instruction fetch */
+            dbg("MMU ITLB MISS accessing 0x%08x\r\n"
+                "FS = 0x%08x\r\n"
+                "MMUSR = 0x%08x\r\n"
+                "PC = 0x%08x\r\n",
+                fault_address, format_status, mmu_sr, pc);
+            dbg("fault = 0x%08x\r\n", fault);
+            mmu_map_8k_instruction_page(pc, 0);
 
-			MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
-							MCF_MMU_MMUOR_ACC |     /* access TLB */
-							MCF_MMU_MMUOR_UAA;      /* update allocation address field */
-	}
+            /* due to prefetch, it makes sense to map the next adjacent page also for ITLBs */
+            mmu_map_8k_instruction_page(pc + DEFAULT_PAGE_SIZE, 0);
+            break;
+
+        case 0x08020000:    /* TLB miss on data write */
+        case 0x0c020000:    /* TLB miss on data read or read-modify-write */
+            dbg("MMU DTLB MISS accessing 0x%08x\r\n"
+                "FS = 0x%08x\r\n"
+                "MMUSR = 0x%08x\r\n"
+                "PC = 0x%08x\r\n",
+                fault_address, format_status, mmu_sr, pc);
+            dbg("fault = 0x%08x\r\n", fault);
+            mmu_map_8k_data_page(fault_address, 0);
+            break;
+
+        /* else issue an bus error */
+        default:
+            dbg("bus error\r\n");
+            return 1;       /* signal bus error to caller */
+    }
+
+#ifdef DBG_MMU
+    xprintf("\r\n");
+#endif /* DBG_MMU */
+
+    return 0;   /* signal TLB miss handled to caller */
 }
 
 

sys/startcf.S

@@ -1,3 +1,4 @@
+
 /*
  * This object file must be the first to be linked,
  * so it will be placed at the very beginning of the ROM.
@@ -48,8 +49,11 @@ _rom_entry:
 		/* set stack pointer to end of SRAM */
 		lea 	__SUP_SP,a7
 		move.l	#0,(sp)
+		subq.l	#4,sp
+		move.l	#0,(sp)
 
-		/* Initialize the processor caches.
+		/*
+		 * Initialize the processor caches.
 		 * The instruction cache is fully enabled.
 		 * The data cache is enabled, but cache-inhibited by default.
 		 * Later, the MMU will fully activate the data cache for specific areas.

sys/sysinit.c

@@ -2,7 +2,7 @@
  * File:		sysinit.c
  * Purpose:		Power-on Reset configuration of the Firebee board.
  *
- * Notes: 
+ * Notes:
  *
  * This file is part of BaS_gcc.
  *
@@ -37,14 +37,17 @@
 #include "wait.h"
 #include "util.h"
 #include "version.h"
-#ifdef MACHINE_FIREBEE
+#if defined(MACHINE_FIREBEE)
 #include "firebee.h"
-#endif /* MACHINE_FIREBEE */
-
-#ifdef MACHINE_M5484LITE
+#elif defined(MACHINE_M5484LITE)
 #include "m5484l.h"
+#elif defined(MACHINE_M54455)
+#include "m54455.h"
+#else
+#error "unknown machine"
 #endif /* MACHINE_M5484LITE */
 
+#
 #include "dma.h"
 #include "mod_devicetable.h"
 #include "pci_ids.h"
@@ -52,12 +55,21 @@
 #include "usb.h"
 #include "video.h"
 
-#define UNUSED(x) (void)(x)               /* Unused variable         */
+// #define DEBUG_SYSINIT
+#ifdef DEBUG_SYSINIT
+#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
+#else
+#define dbg(format, arg...) do { ; } while (0)
+#endif /* DEBUG_SYSINIT */
+
+#define UNUSED(x) (void)(x)				/* Unused variable         */
+
+bool fpga_configured = false;			/* for FPGA JTAG configuration */
 
 extern volatile long _VRAM;	/* start address of video ram from linker script */
 
 /*
- * init SLICE TIMER 0 
+ * init SLICE TIMER 0
  * all  = 32.538 sec = 30.736mHz
  * BYT0 = 127.1ms/tick = 7.876Hz   offset 0
  * BYT1 = 496.5us/tick = 2.014kHz  offset 1
@@ -86,16 +98,16 @@ void init_gpio(void)
 	 * configure all four 547x GPIO module DMA pins:
 	 *
 	 * /DACK1 - DMA acknowledge 1
- 	 * /DACK0 - DMA acknowledge 0
- 	 * /DREQ1 - DMA request 1
- 	 * /DREQ0 - DMA request 0
- 	 *
+	 * /DACK0 - DMA acknowledge 0
+	 * /DREQ1 - DMA request 1
+	 * /DREQ0 - DMA request 0
+	 *
 	 * for DMA operation
 	 */
-	MCF_PAD_PAR_DMA = MCF_PAD_PAR_DMA_PAR_DACK0(0b11) |
-			MCF_PAD_PAR_DMA_PAR_DACK1(0b11) |
-			MCF_PAD_PAR_DMA_PAR_DREQ1(0b11) |
-			MCF_PAD_PAR_DMA_PAR_DREQ0(0b11);
+	MCF_PAD_PAR_DMA = MCF_PAD_PAR_DMA_PAR_DACK0(0x3) |
+			MCF_PAD_PAR_DMA_PAR_DACK1(0x3) |
+			MCF_PAD_PAR_DMA_PAR_DREQ1(0x3) |
+			MCF_PAD_PAR_DMA_PAR_DREQ0(0x3);
 
 	/*
 	 * configure FEC0 pin assignment on GPIO module as FEC0
@@ -204,20 +216,6 @@ void init_gpio(void)
 						MCF_PAD_PAR_TIMER_PAR_TOUT3 |
 						MCF_PAD_PAR_TIMER_PAR_TIN2(MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2) |
 						MCF_PAD_PAR_TIMER_PAR_TOUT2;
-
-#if defined(MACHINE_FIREBEE)
-	/*
-	 * Configure GPIO FEC1L port directions (needed to load FPGA configuration)
-	 */
-	MCF_GPIO_PDDR_FEC1L = 0 |								/* bit 7 = input */
-						  0	|								/* bit 6 = input */
-						  0 | 								/* bit 5 = input */
-						  MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 |	/* bit 4 = LED => output */
-						  MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 |	/* bit 3 = PRG_DQ0 => output */
-						  MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 |	/* bit 2 = FPGA_CONFIG => output */
-						  MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 |	/* bit 1 = PRG_CLK (FPGA) => output */
-						  0;								/* bit 0 => input */
-#endif /* MACHINE_FIREBEE */
 }
 
 /*
@@ -253,7 +251,7 @@ void init_serial(void)
 	MCF_PSC0_PSCOPSET = 0x01;
 	MCF_PSC0_PSCCR = 0x05;
 
-#ifdef MACHINE_FIREBEE	/* PSC3 is not connected to anything on the LITE board */
+#if defined(MACHINE_FIREBEE)	/* PSC3 is not connected to anything on the LITE board */
 	/* PSC3: PIC */
 	MCF_PSC3_PSCSICR = 0;	// UART
 	MCF_PSC3_PSCCSR = 0xDD;
@@ -427,27 +425,27 @@ void init_fbcs()
 #if MACHINE_FIREBEE /* FBC setup for FireBee */
 	MCF_FBCS1_CSAR = 0xFFF00000;			/* ATARI I/O ADRESS */
 	MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16	/* 16BIT PORT */
-	    | MCF_FBCS_CSCR_WS(8)				/* DEFAULT 8WS */
-	    | MCF_FBCS_CSCR_AA;					/* AA */
+		| MCF_FBCS_CSCR_WS(8)				/* DEFAULT 8WS */
+		| MCF_FBCS_CSCR_AA;					/* AA */
 	MCF_FBCS1_CSMR = MCF_FBCS_CSMR_BAM_1M | MCF_FBCS_CSMR_V;
 
 	MCF_FBCS2_CSAR = 0xF0000000;			// NEUER I/O ADRESS-BEREICH
 	MCF_FBCS2_CSCR = MCF_FBCS_CSCR_PS_32	// 32BIT PORT
-	    | MCF_FBCS_CSCR_WS(8)				// DEFAULT 4WS
-	    | MCF_FBCS_CSCR_AA;					// AA
+		| MCF_FBCS_CSCR_WS(8)				// DEFAULT 4WS
+		| MCF_FBCS_CSCR_AA;					// AA
 	MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M	// F000'0000-F7FF'FFFF
 			  | MCF_FBCS_CSMR_V);
 
 	MCF_FBCS3_CSAR = 0xF8000000;			// NEUER I/O ADRESS-BEREICH
 	MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16	// 16BIT PORT
-	    | MCF_FBCS_CSCR_AA;	// AA 
+		| MCF_FBCS_CSCR_AA;	// AA
 	MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_64M	// F800'0000-FBFF'FFFF
 			  | MCF_FBCS_CSMR_V);
 
 	MCF_FBCS4_CSAR = 0x40000000;			// VIDEO RAM BEREICH, #FB_CS3 WIRD NICHT BENÜTZT, DECODE DIREKT AUF DEM FPGA
 	MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32	// 32BIT PORT
-	    | MCF_FBCS_CSCR_BSTR				// BURST READ ENABLE
-	    | MCF_FBCS_CSCR_BSTW;				// BURST WRITE ENABLE
+		| MCF_FBCS_CSCR_BSTR				// BURST READ ENABLE
+		| MCF_FBCS_CSCR_BSTW;				// BURST WRITE ENABLE
 	MCF_FBCS4_CSMR = MCF_FBCS_CSMR_BAM_1G	// 4000'0000-7FFF'FFFF
 			  | MCF_FBCS_CSMR_V;
 #elif MACHINE_M5484LITE
@@ -462,7 +460,7 @@ void init_fbcs()
 		| MCF_FBCS_CSCR_WS(32)
 		| MCF_FBCS_CSCR_ASET(1)
 		| MCF_FBCS_CSCR_AA;
-	MCF_FBCS5_CSMR = MCF_FBCS_CSMR_BAM_256M 
+	MCF_FBCS5_CSMR = MCF_FBCS_CSMR_BAM_256M
 		| MCF_FBCS_CSMR_V;
 #endif /* MACHINE_FIREBEE */
 
@@ -489,12 +487,123 @@ void wait_pll(void)
 	} while ((* (volatile int16_t *) 0xf0000800 < 0) && MCF_SLT0_SCNT > trgt);
 }
 
-static volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600;
+
+volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600;
+
+//#define _OLD_CODE_ /* use old PLL initialization code */
+#ifndef _OLD_CODE_
+
+/*
+ * the altpll_reconfig component is connected to the Bus as follows:
+ *
+ * 9 bit data:
+ * 876543210 (this _is_ actually the last part of the address written or read!)
+ * | ||  |
+ * | |+--+- counter_type
+ * +-+----- counter_param
+ *
+ * 9 bit data
+ * 876543210
+ * +-------+- data_in
+ *
+ * counter_type selects which counter should be affected by data_in:
+ * 0000 - N
+ * 0001 - M
+ * 0010 - CP/LF (charge pump/loop filter)
+ * 0011 - VCO (voltage controlled oscillator)
+ * 0100 - C0
+ * 0101 - C1
+ * 0110 - C2
+ * 0111 - C3
+ * 1000 - C4
+ *
+ * counter_param selects which part of the selected counter_type is set/read and how many
+ * bits are used/valid:
+ *
+ * for counter_type N, M, C0-C4:
+ * 000 - high count, 8 bit
+ * 001 - low count, 8 bit
+ * 100 - bypass, 1 bit
+ * 101 - mode (odd/even division), 1 bit
+ *
+ * for counter_type CP/LF:
+ * 101 - charge pump unused, 5 bit
+ * 000 - charge pump current, 3 bit
+ * 100 - loop filter unused, 1 bit
+ * 001 - loop filter resistor, 5 bit
+ * 010 - loop filter capacitance, 2 bit
+ *
+ * for counter_type VCO:
+ * 000 - VCO post scale, 1 bit
+ */
+
+#define PLL_COUNTER_TYPE_N      0
+#define PLL_COUNTER_TYPE_M      1
+#define PLL_COUNTER_TYPE_CPLF   2
+#define PLL_COUNTER_TYPE_VCO    3
+#define PLL_COUNTER_TYPE_C0     4
+#define PLL_COUNTER_TYPE_C1     5
+#define PLL_COUNTER_TYPE_C2     6
+#define PLL_COUNTER_TYPE_C3     7
+#define PLL_COUNTER_TYPE_C4     8
+
+#define PLL_COUNTER_PARAM_HC    0
+#define PLL_COUNTER_PARAM_LC    1
+#define PLL_COUNTER_PARAM_BP    4
+#define PLL_COUNTER_PARAM_MODE  5
+
+#define PLL_COUNTER_PARAM_CP_U  5
+#define PLL_COUNTER_PARAM_CP_C  0
+#define PLL_COUNTER_PARAM_LF_U  4
+#define PLL_COUNTER_PARAM_LF_R  1
+#define PLL_COUNTER_PARAM_LF_C  2
+
+#define PLL_COUNTER_PARAM_VCO_PS    0
+
+void pll_write(int type, int param, int data)
+{
+	wait_pll();
+	* (volatile uint16_t *) (pll_base + ((param << 6) | (type << 2))) = data;
+}
+
+struct pll_init
+{
+	int type;
+	int param;
+	int data;
+};
+
+struct pll_init pll_values[] =
+{
+	{ PLL_COUNTER_TYPE_CPLF, PLL_COUNTER_PARAM_LF_R, 27 },	/* loopfilter R */
+	{ PLL_COUNTER_TYPE_CPLF, PLL_COUNTER_PARAM_LF_C, 1 },	/* charge pump 1 */
+	{ PLL_COUNTER_TYPE_N, PLL_COUNTER_PARAM_HC, 12 },		/* N counter high */
+	{ PLL_COUNTER_TYPE_N, PLL_COUNTER_PARAM_LC, 12 },		/* N counter low */
+	{ PLL_COUNTER_TYPE_C1, PLL_COUNTER_PARAM_BP, 1 },		/* c1 bypass */
+	{ PLL_COUNTER_TYPE_C2, PLL_COUNTER_PARAM_BP, 1 },		/* c2 bypass */
+	{ PLL_COUNTER_TYPE_C3, PLL_COUNTER_PARAM_BP, 1 },		/* c3 bypass */
+	{ PLL_COUNTER_TYPE_C0, PLL_COUNTER_PARAM_HC, 1 },		/* c0 high */
+	{ PLL_COUNTER_TYPE_C0, PLL_COUNTER_PARAM_LC, 1 },		/* c0 low */
+	{ PLL_COUNTER_TYPE_M, PLL_COUNTER_PARAM_MODE, 1 },		/* M odd division */
+	{ PLL_COUNTER_TYPE_M, PLL_COUNTER_PARAM_LC, 1 },		/* M low = 1 */
+	{ PLL_COUNTER_TYPE_M, PLL_COUNTER_PARAM_HC, 145 }		/* M high = 145 = 146 MHz */
+};
+int num_pll_values = sizeof(pll_values) / sizeof(struct pll_init);
+#endif /* _OLD_CODE_ */
 
 void init_pll(void)
 {
+	int i;
+
 	xprintf("FPGA PLL initialization: ");
 
+#ifndef _OLD_CODE_
+	for (i = 0; i < num_pll_values; i++)
+	{
+		pll_write(pll_values[i].type, pll_values[i].param, pll_values[i].data);
+	}
+
+#else /* _OLD_CODE_ */
 	wait_pll();
 	* (volatile uint16_t *) (pll_base + 0x48) = 27;	/* loopfilter  r */
 
@@ -505,7 +614,7 @@ void init_pll(void)
 	* (volatile uint16_t *) (pll_base + 0x00) = 12;		/* N counter high = 12 */
 
 	wait_pll();
-	* (volatile uint16_t *) (pll_base + 0x40) = 12;		/* N counter low = 12 */
+	 * (volatile uint16_t *) (pll_base + 0x40) = 12;		/* N counter low = 12 */
 
 	wait_pll();
 	* (volatile uint16_t *) (pll_base + 0x114) = 1;		/* ck1 bypass */
@@ -532,6 +641,7 @@ void init_pll(void)
 	* (volatile uint16_t *) (pll_base + 0x04) = 145;	/* M high = 145 = 146 MHz */
 
 	wait_pll();
+#endif /* _OLD_CODE_ */
 
 	* (volatile uint8_t *) 0xf0000800 = 0;				/* set */
 
@@ -571,7 +681,7 @@ void init_video_ddr(void) {
 	_VRAM = 0000070022;	/* load MR dll on */
 	NOP();
 
-	* (uint32_t *) 0xf0000400 = 0x01070002; /* fifo on, refresh on, ddrcs und cke on, video dac on */
+	* (uint32_t *) 0xf0000400 = 0x01070002; /* fifo on, refresh on, ddrcs and cke on, video dac on */
 
 	xprintf("finished\r\n");
 }
@@ -580,7 +690,7 @@ void init_video_ddr(void) {
 /*
  * probe for NEC compatible USB host controller and install if found
  */
-void init_usb(void) 
+void init_usb(void)
 {
 	extern struct pci_device_id ohci_usb_pci_table[];
 	extern struct pci_device_id ehci_usb_pci_table[];
@@ -597,41 +707,52 @@ void init_usb(void)
 		if (handle > 0)
 		{
 			uint32_t id = 0;
-			uint32_t class = 0;
+			uint32_t pci_class = 0;
 
 			id = pci_read_config_longword(handle, PCIIDR);
-			class = pci_read_config_longword(handle, PCIREV);
-
-			if (PCI_CLASS_CODE(class) == PCI_CLASS_SERIAL_USB)
+			pci_class = pci_read_config_longword(handle, PCIREV);
+			dbg("compare class code 0x%x to 0x%x\r\n", PCI_CLASS_CODE(pci_class), PCI_CLASS_SERIAL_USB);
+			if (PCI_CLASS_CODE(pci_class) == PCI_CLASS_SERIAL_USB)
 			{
 				xprintf("serial USB found at bus=0x%x, dev=0x%x, fnc=0x%x (0x%x)\r\n",
 						PCI_BUS_FROM_HANDLE(handle),
 						PCI_DEVICE_FROM_HANDLE(handle),
 						PCI_FUNCTION_FROM_HANDLE(handle),
 						handle);
-				if (PCI_SUBCLASS(class) == PCI_CLASS_SERIAL_USB_EHCI)
+				dbg("compare subclass code 0x%x against 0x%x\r\n", PCI_SUBCLASS(pci_class), PCI_CLASS_SERIAL_USB_EHCI);
+				if (PCI_SUBCLASS(pci_class) == PCI_CLASS_SERIAL_USB_EHCI)
 				{
 					board = ehci_usb_pci_table;
 					while (board->vendor)
 					{
+						dbg("compare vendor id 0x%x against 0x%x\r\n", board->vendor, PCI_VENDOR_ID(id));
+						dbg("compare device id 0x%x against 0x%x\r\n", board->device, PCI_DEVICE_ID(id));
 						if ((board->vendor == PCI_VENDOR_ID(id)) && board->device == PCI_DEVICE_ID(id))
 						{
+#ifdef _NOT_YET_	/* FIXME: usb_init() is broken */
+							dbg("match. trying to init board\r\n");
 							if (usb_init(handle, board) >= 0)
 							{
 								usb_found++;
 							}
+#endif /* _NOT_YET_ */
 						}
 						board++;
 					}
 				}
-				if (PCI_SUBCLASS(class) == PCI_CLASS_SERIAL_USB_OHCI)
+
+				dbg("compare subclass code 0x%x against 0x%x\r\n", PCI_SUBCLASS(pci_class), PCI_CLASS_SERIAL_USB_OHCI);
+				if (PCI_SUBCLASS(pci_class) == PCI_CLASS_SERIAL_USB_OHCI)
 				{
 					board = ohci_usb_pci_table;
+
 					while (board->vendor)
 					{
+						dbg("matched. compare vendor id 0x%x against 0x%x\r\n", board->vendor, PCI_VENDOR_ID(id));
+						dbg("compare device id 0x%x against 0x%x\r\n", board->device, PCI_DEVICE_ID(id));
 						if ((board->vendor == PCI_VENDOR_ID(id)) && board->device == PCI_DEVICE_ID(id))
 						{
-							if (usb_init(handle, board) >= 0)
+							// if (usb_init(handle, board) >= 0)
 								usb_found++;
 						}
 						board++;
@@ -639,6 +760,7 @@ void init_usb(void)
 				}
 			}
 		}
+		dbg("PCI device handle = %x\r\n", handle);
 	} while (handle >= 0);
 
 	xprintf("finished (found %d USB controller(s))\r\n", usb_found);
@@ -666,18 +788,20 @@ static bool i2c_bus_free(void)
 /*
  * TFP410 (DVI) on
  */
-void dvi_on(void) {
+void dvi_on(void)
+{
 	uint8_t receivedByte;
 	uint8_t dummyByte; /* only used for a dummy read */
 	int num_tries = 0;
-	
+
 	xprintf("DVI digital video output initialization: ");
 
 	MCF_I2C_I2FDR = 0x3c;		/* divide system clock by 1280: 100kHz standard */
 
-	do {
+	do
+	{
 		/* disable all i2c interrupt routing targets */
-		MCF_I2C_I2ICR = 0x0; //~(MCF_I2C_I2ICR_IE | MCF_I2C_I2ICR_RE | MCF_I2C_I2ICR_TE | MCF_I2C_I2ICR_BNBE);
+		MCF_I2C_I2ICR = 0x0;	// ~(MCF_I2C_I2ICR_IE | MCF_I2C_I2ICR_RE | MCF_I2C_I2ICR_TE | MCF_I2C_I2ICR_BNBE);
 
 		/* disable i2c, disable i2c interrupts, slave, receive, i2c = acknowledge, no repeat start */
 		MCF_I2C_I2CR = 0x0;
@@ -814,16 +938,16 @@ void init_ac97(void) {
 	int va;
 	int vb;
 	int vc;
-	
+
 	xprintf("AC97 sound chip initialization: ");
 	MCF_PAD_PAR_PSC2 = MCF_PAD_PAR_PSC2_PAR_RTS2_RTS	// PSC2=TX,RX BCLK,CTS->AC'97
-	       | MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK
+		   | MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK
 			 | MCF_PAD_PAR_PSC2_PAR_TXD2
 			 | MCF_PAD_PAR_PSC2_PAR_RXD2;
 	MCF_PSC2_PSCMR1 = 0x0;
 	MCF_PSC2_PSCMR2 = 0x0;
 	MCF_PSC2_PSCIMR = 0x0300;
-	MCF_PSC2_PSCSICR = 0x03;	//AC97           
+	MCF_PSC2_PSCSICR = 0x03;	//AC97
 	MCF_PSC2_PSCRFCR = 0x0f000000;
 	MCF_PSC2_PSCTFCR = 0x0f000000;
 	MCF_PSC2_PSCRFAR = 0x00F0;
@@ -844,7 +968,7 @@ void init_ac97(void) {
 		{
 			MCF_PSC2_PSCTB_AC97 = 0x0;	//SLOT2-12:WR REG ALLES 0
 		}
-		
+
 		// read register
 		MCF_PSC2_PSCTB_AC97 = 0xc0000000;	//START SLOT1 + SLOT2, FIRST FRAME
 		MCF_PSC2_PSCTB_AC97 = 0x82000000;	//SLOT1:master volume
@@ -854,7 +978,7 @@ void init_ac97(void) {
 			MCF_PSC2_PSCTB_AC97 = 0x00000000;	//SLOT2-12:RD REG ALLES 0
 		}
 		wait(50);
-		
+
 		va = MCF_PSC2_PSCTB_AC97;
 		if ((va & 0x80000fff) == 0x80000800) {
 			vb = MCF_PSC2_PSCTB_AC97;
@@ -939,8 +1063,6 @@ void clear_bss_segment(void)
 
 void initialize_hardware(void)
 {
-	bool coldboot = true;
-
 	/* Test for FireTOS switch: DIP switch #5 up */
 #ifdef MACHINE_FIREBEE
 	if (!(DIP_SWITCH & (1 << 6))) {
@@ -958,10 +1080,10 @@ void initialize_hardware(void)
 		* (volatile uint32_t *) 0x43a = 0x237698aa;	/* memval2 TOS system variable */
 		* (volatile uint32_t *) 0x51a = 0x5555aaaa;	/* memval3 TOS system variable */
 
-	    /* TT-RAM */
+		/* TT-RAM */
 
-	    * (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */
-	    * (uint32_t *) 0x5a8 = 0x1357bd13;  /* ramvalid TOS system variable */
+		* (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */
+		* (uint32_t *) 0x5a8 = 0x1357bd13;  /* ramvalid TOS system variable */
 
 		/* Jump into FireTOS */
 		typedef void void_func(void);
@@ -974,7 +1096,7 @@ void initialize_hardware(void)
 	init_serial();
 
 	xprintf("\n\n");
-	xprintf("%s BASIS system (BaS) v %d.%d (%s, %s)\r\n\r\n", 
+	xprintf("%s BASIS system (BaS) v %d.%d (%s, %s)\r\n\r\n",
 #if MACHINE_FIREBEE
 	"Firebee"
 #elif MACHINE_M5484LITE
@@ -984,6 +1106,9 @@ void initialize_hardware(void)
 #endif
 	, MAJOR_VERSION, MINOR_VERSION, __DATE__, __TIME__);
 
+	extern char *rom_header;
+
+	xprintf("running from %p\r\n\r\n", &rom_header);
 	/*
 	 * Determine cause(s) of Reset
 	 */
@@ -1052,23 +1177,17 @@ void initialize_hardware(void)
 	/*
 	 * Determine the processor revision
 	 */
-	xprintf(" (revision %d)\r\n",((MCF_SIU_JTAGID & MCF_SIU_JTAGID_REV) >> 28));
+	xprintf(" (revision %d)\r\n", ((MCF_SIU_JTAGID & MCF_SIU_JTAGID_REV) >> 28));
 
 	init_slt();
 	init_fbcs();
-	coldboot = init_ddram();
+	init_ddram();
 
 	/*
 	 * install (preliminary) exception vectors
 	 */
 	setup_vectors();
 
-#ifdef _NOT_USED_
-	/* make sure the handlers are called */
-	__asm__ __volatile__("dc.w 0xafff");  /* should trigger a line-A exception */
-#endif /* _NOT_USED_ */
-
-
 	/*
 	 * save the planet (and reduce case heat): disable clocks of unused SOC modules
 	 */
@@ -1090,6 +1209,7 @@ void initialize_hardware(void)
 
 	/* the following only makes sense _after_ DDRAM has been initialized */
 	clear_bss_segment();
+	xprintf(".bss segment cleared\r\n");
 
 	if (BAS_LMA != BAS_IN_RAM)
 	{
@@ -1101,45 +1221,19 @@ void initialize_hardware(void)
 	}
 
 #if MACHINE_FIREBEE
-	if (coldboot) /* does not work with BDM */
-		;
-	init_fpga();
+	fpga_configured = init_fpga();
 
 	init_pll();
 	init_video_ddr();
 	dvi_on();
 
-#ifdef _NOT_USED_ 
-	/* experimental */
-	{
-		int i;
-		uint32_t *scradr = (uint32_t *) 0xd00000;
-
-		for (i = 0; i < 100; i++)
-		{
-			uint32_t *p = scradr;
-
-			for (p = scradr; p < scradr + 1024 * 150L; p++)
-			{
-				*p = 0xffffffff;
-			}
-			for (p = scradr; p < scradr + 1024 * 150L; p++)
-			{
-				*p = 0x0;
-			}
-		}
-	}
-#endif /* _NOT_USED_ */
-
 #endif /* MACHINE_FIREBEE */
 	driver_mem_init();
 	init_pci();
 	video_init();
-	
-	/* do not try to init USB for now on the Firebee, it hangs the machine */
-#ifndef MACHINE_FIREBEE
-	//init_usb();
-#endif
+
+	/* initialize USB devices */
+	init_usb();
 
 #if MACHINE_FIREBEE
 	init_ac97();

tos/Makefile

@@ -0,0 +1,11 @@
+.PHONY: tos
+.PHONY: jtagwait
+.PHONY: mcdcook
+tos: jtagwait mcdcook
+
+jtagwait:
+	(cd $@; make)
+
+bascook:
+	(cd $@; make)
+	

tos/bascook/Makefile

@@ -0,0 +1,97 @@
+CROSS=Y
+
+CROSSBINDIR_IS_Y=m68k-atari-mint-
+CROSSBINDIR_IS_N=
+
+CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS))
+
+UNAME := $(shell uname)
+ifeq ($(CROSS), Y)
+ifeq ($(UNAME),Linux)
+PREFIX=m68k-atari-mint
+HATARI=hatari
+else
+PREFIX=m68k-atari-mint
+HATARI=/usr/local/bin/hatari
+endif
+else
+PREFIX=/usr
+endif
+
+DEPEND=depend
+TOPDIR= ../..
+
+BAS_INCLUDE=-I$(TOPDIR)/../BaS_gcc/include
+
+INCLUDE=-I$(TOPDIR)/../libcmini/include $(BAS_INCLUDE) -nostdlib
+LIBS=-lcmini -nostdlib -lgcc
+CC=$(PREFIX)/bin/gcc
+
+CC=$(CROSSBINDIR)gcc
+STRIP=$(CROSSBINDIR)strip
+STACK=$(CROSSBINDIR)stack
+
+APP=bascook.prg
+TEST_APP=$(APP)
+
+CFLAGS=\
+	-Os\
+	-g\
+	-Wl,-Map,mapfile\
+	-Wall
+
+SRCDIR=sources
+
+CSRCS=\
+	$(SRCDIR)/bascook.c
+ASRCS=
+
+COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS)))
+AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS)))
+OBJS=$(COBJS) $(AOBJS)
+
+TRGTDIRS=.
+OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS))
+
+#
+# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output
+#
+$(APP):CFLAGS += -mcpu=5475
+
+all: $(TEST_APP)
+
+#
+# generate pattern rules for multilib object files.
+#
+define CC_TEMPLATE
+$(1)/objs/%.o:$(SRCDIR)/%.c
+	$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
+
+$(1)/objs/%.o:$(SRCDIR)/%.S
+	$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
+
+$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
+$(1)/$(APP): $$($(1)_OBJS)
+	$(CC) $$(CFLAGS) -o $$@ $(TOPDIR)/../libcmini/m5475/startup.o $$($(1)_OBJS) -L$(TOPDIR)/../libcmini/m5475 $(LIBS)
+	$(STRIP) $$@
+endef
+$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
+
+$(DEPEND): $(ASRCS) $(CSRCS)
+	-rm -f $(DEPEND)
+	for d in $(TRGTDIRS);\
+		do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \
+    done
+
+
+clean:
+	@rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS))
+	@rm -f $(DEPEND) mapfile
+
+.PHONY: printvars
+printvars:
+	@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
+
+ifneq (clean,$(MAKECMDGOALS))
+-include $(DEPEND)
+endif

tos/bascook/sources/bascook.c

@@ -0,0 +1,122 @@
+#include <stdio.h>
+#include <mint/osbind.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "driver_vec.h"
+
+struct driver_table *get_bas_drivers(void)
+{
+	struct driver_table *ret = NULL;
+
+	__asm__ __volatile(
+		"	trap	#0\n\t"
+		"	move.l	d0,%[ret]\n\t"
+		:	[ret] "=m" (ret)	/* output */
+		:						/* no inputs */
+		:						/* clobbered */
+	);
+
+	return ret;
+}
+
+static uint32_t cookieptr(void)
+{
+	return * (uint32_t *) 0x5a0L;
+}
+
+void setcookie(uint32_t cookie, uint32_t value)
+{
+	uint32_t *cookiejar = (uint32_t *) Supexec(cookieptr);
+	int num_slots;
+	int max_slots;
+
+	num_slots = max_slots = 0;
+	do
+	{
+		if (cookiejar[0] == cookie)
+		{
+			cookiejar[1] = value;
+			return;
+		}
+		cookiejar = &(cookiejar[2]);
+		num_slots++;
+	} while (cookiejar[-2]);
+
+	/*
+	 * Here we are at the end of the list and did not find our cookie.
+	 * Let's check if there is any space left and append our value to the
+	 * list if so. If not, we are lost (extending the cookie jar does only
+	 * work from TSRs)
+	 */
+	if (cookiejar[-1])
+		max_slots = cookiejar[-1];
+
+	if (max_slots > num_slots)
+	{
+		 /* relief, there is space left, extend the list */
+		cookiejar[0] = cookiejar[-2];
+		cookiejar[1] = cookiejar[-1];
+		/* add the new element */
+		cookiejar[-2] = cookie;
+		cookiejar[-1] = value;
+	}
+	else
+		printf("cannot set cookie, cookie jar is full!\r\n");
+}
+
+# define COOKIE_DMAC	0x444D4143L /* FireTOS DMA API */
+
+static char *dt_to_str(enum driver_type dt)
+{
+	switch (dt)
+	{
+		case BLOCKDEV_DRIVER: return "generic block device driver";
+		case CHARDEV_DRIVER:  return "generic character device driver";
+		case VIDEO_DRIVER:    return "video/framebuffer driver";
+		case XHDI_DRIVER:     return "XHDI compatible hard disk driver";
+		case MCD_DRIVER:	  return "multichannel DMA driver";
+		case PCI_DRIVER:	  return "PCI interface driver";
+		default:              return "unknown driver type";
+	}
+}
+
+int main(int argc, char *argv[])
+{
+	struct driver_table *dt;
+	void *ssp;
+
+	(void) Cconws("retrieve BaS driver interface\r\n");
+
+	ssp = (void *) Super(0L);
+	dt = get_bas_drivers();
+	if (dt)
+	{
+		struct generic_interface *ifc = &dt->interfaces[0];
+
+		printf("BaS driver table found at %p, BaS version is %d.%d\r\n", dt,
+				dt->bas_version, dt->bas_revision);
+
+		while (ifc->type != END_OF_DRIVERS)
+		{
+			printf("driver \"%s (%s)\" found,\r\n"
+				   "interface type is %d (%s),\r\n"
+				   "version %d.%d\r\n\r\n",
+					ifc->name, ifc->description, ifc->type, dt_to_str(ifc->type),
+					ifc->version, ifc->revision);
+			if (ifc->type == MCD_DRIVER)
+			{
+				setcookie(COOKIE_DMAC, (uint32_t) ifc->interface.dma);
+				printf("\r\nDMAC cookie set to %p\r\n", ifc->interface.dma);
+			}
+			ifc++;
+		}
+	}
+	Super(ssp);
+
+	while (Cconis()) Cconin();	/* eat keys */
+	// printf("press any key to continue\n\r");
+	// while (! Cconis());
+	return 0;
+}
+

tos/jtagwait/Makefile

@@ -0,0 +1,103 @@
+CROSS=Y
+
+CROSSBINDIR_IS_Y=m68k-atari-mint-
+CROSSBINDIR_IS_N=
+
+CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS))
+
+UNAME := $(shell uname)
+ifeq ($(CROSS), Y)
+ifeq ($(UNAME),Linux)
+PREFIX=m68k-atari-mint
+HATARI=hatari
+else
+PREFIX=m68k-atari-mint
+HATARI=/usr/local/bin/hatari
+endif
+else
+PREFIX=/usr
+endif
+
+DEPEND=depend
+TOPDIR = ../..
+
+INCLUDE=-I$(TOPDIR)/../libcmini/include -nostdlib
+LIBS=-lcmini -nostdlib -lgcc
+CC=$(PREFIX)/bin/gcc
+
+CC=$(CROSSBINDIR)gcc
+STRIP=$(CROSSBINDIR)strip
+STACK=$(CROSSBINDIR)stack
+
+APP=jtagwait.prg
+TEST_APP=$(APP)
+
+CFLAGS=\
+	-O0\
+	-g\
+	-Wl,-Map,mapfile\
+	-Wl,--defsym -Wl,__MBAR=0xff000000\
+	-Wl,--defsym -Wl,__MMUBAR=0xff040000\
+	-Wl,--defsym -Wl,__FPGA_JTAG_LOADED=0xff101000\
+	-Wl,--defsym -Wl,__FPGA_JTAG_VALID=0xff101004\
+	-Wall
+
+SRCDIR=sources
+INCDIR=include
+INCLUDE+=-I$(INCDIR)
+
+CSRCS=\
+	$(SRCDIR)/jtagwait.c \
+	$(SRCDIR)/bas_printf.c
+
+ASRCS=$(SRCDIR)/printf_helper.S
+
+COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS)))
+AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS)))
+OBJS=$(COBJS) $(AOBJS)
+
+TRGTDIRS=./m5475 ./m5475/mshort
+OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS))
+
+#
+# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output
+#
+m5475/$(APP):CFLAGS += -mcpu=5475
+m5475/mshort/$(APP): CFLAGS += -mcpu=5475 -mshort
+
+all:$(patsubst %,%/$(APP),$(TRGTDIRS))
+#
+# generate pattern rules for multilib object files.
+#
+define CC_TEMPLATE
+$(1)/objs/%.o:$(SRCDIR)/%.c
+	$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
+
+$(1)/objs/%.o:$(SRCDIR)/%.S
+	$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
+
+$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
+$(1)/$(APP): $$($(1)_OBJS)
+	$(CC) $$(CFLAGS) -o $$@ $(TOPDIR)/../libcmini/$(1)/startup.o $$($(1)_OBJS) -L$(TOPDIR)/../libcmini/$(1) $(LIBS)
+	$(STRIP) $$@
+endef
+$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
+
+$(DEPEND): $(ASRCS) $(CSRCS)
+	-rm -f $(DEPEND)
+	for d in $(TRGTDIRS);\
+		do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \
+    done
+
+
+clean:
+	@rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS))
+	@rm -f $(DEPEND) mapfile
+
+.PHONY: printvars
+printvars:
+	@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
+
+ifneq (clean,$(MAKECMDGOALS))
+-include $(DEPEND)
+endif

tos/jtagwait/include/MCF5475.h

@@ -0,0 +1,67 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_H__
+#define __MCF5475_H__
+
+#include <stdint.h>
+/***
+ * MCF5475 Derivative Memory map definitions from linker command files:
+ * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
+ * linker symbols must be defined in the linker command file.
+ */
+
+typedef uint32_t __attribute__((__may_alias__)) uint32_t_a;	/* a type to avoid gcc's complaints about pointer aliasing */
+
+extern uint8_t _MBAR[];
+extern uint8_t _MMUBAR[];
+extern uint8_t _RAMBAR0[];
+extern uint8_t _RAMBAR0_SIZE[];
+extern uint8_t _RAMBAR1[];
+extern uint8_t _RAMBAR1_SIZE[];
+
+#define MBAR_ADDRESS    (uint32_t)_MBAR
+#define MMUBAR_ADDRESS  (uint32_t)_MMUBAR
+#define RAMBAR0_ADDRESS (uint32_t)_RAMBAR0
+#define RAMBAR0_SIZE    (uint32_t)_RAMBAR0_SIZE
+#define RAMBAR1_ADDRESS (uint32_t)_RAMBAR1
+#define RAMBAR1_SIZE    (uint32_t)_RAMBAR1_SIZE
+
+
+#include "MCF5475_SIU.h"
+#include "MCF5475_MMU.h"
+#include "MCF5475_SDRAMC.h"
+#include "MCF5475_XLB.h"
+#include "MCF5475_CLOCK.h"
+#include "MCF5475_FBCS.h"
+#include "MCF5475_INTC.h"
+#include "MCF5475_GPT.h"
+#include "MCF5475_SLT.h"
+#include "MCF5475_GPIO.h"
+#include "MCF5475_PAD.h"
+#include "MCF5475_PCI.h"
+#include "MCF5475_PCIARB.h"
+#include "MCF5475_EPORT.h"
+#include "MCF5475_CTM.h"
+#include "MCF5475_DMA.h"
+#include "MCF5475_PSC.h"
+#include "MCF5475_DSPI.h"
+#include "MCF5475_I2C.h"
+#include "MCF5475_FEC.h"
+#include "MCF5475_USB.h"
+#include "MCF5475_SRAM.h"
+#include "MCF5475_SEC.h"
+
+#endif /* __MCF5475_H__ */

tos/jtagwait/include/MCF5475_CLOCK.h

@@ -0,0 +1,47 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_CLOCK_H__
+#define __MCF5475_CLOCK_H__
+
+
+/*********************************************************************
+*
+* Clock Module (CLOCK)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CLOCK_SPCR                       (*(volatile uint32_t*)(&_MBAR[0x300]))
+
+
+/* Bit definitions and macros for MCF_CLOCK_SPCR */
+#define MCF_CLOCK_SPCR_MEMEN                 (0x1)
+#define MCF_CLOCK_SPCR_PCIEN                 (0x2)
+#define MCF_CLOCK_SPCR_FBEN                  (0x4)
+#define MCF_CLOCK_SPCR_CAN0EN                (0x8)
+#define MCF_CLOCK_SPCR_DMAEN                 (0x10)
+#define MCF_CLOCK_SPCR_FEC0EN                (0x20)
+#define MCF_CLOCK_SPCR_FEC1EN                (0x40)
+#define MCF_CLOCK_SPCR_USBEN                 (0x80)
+#define MCF_CLOCK_SPCR_PSCEN                 (0x200)
+#define MCF_CLOCK_SPCR_CAN1EN                (0x800)
+#define MCF_CLOCK_SPCR_CRYENA                (0x1000)
+#define MCF_CLOCK_SPCR_CRYENB                (0x2000)
+#define MCF_CLOCK_SPCR_COREN                 (0x4000)
+#define MCF_CLOCK_SPCR_PLLK                  (0x80000000)
+
+
+#endif /* __MCF5475_CLOCK_H__ */

tos/jtagwait/include/MCF5475_CTM.h

@@ -0,0 +1,76 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_CTM_H__
+#define __MCF5475_CTM_H__
+
+
+/*********************************************************************
+*
+* Comm Timer Module (CTM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CTM_CTCR0                        (*(volatile uint32_t*)(&_MBAR[0x7F00]))
+#define MCF_CTM_CTCR1                        (*(volatile uint32_t*)(&_MBAR[0x7F04]))
+#define MCF_CTM_CTCR2                        (*(volatile uint32_t*)(&_MBAR[0x7F08]))
+#define MCF_CTM_CTCR3                        (*(volatile uint32_t*)(&_MBAR[0x7F0C]))
+#define MCF_CTM_CTCR4                        (*(volatile uint32_t*)(&_MBAR[0x7F10]))
+#define MCF_CTM_CTCR5                        (*(volatile uint32_t*)(&_MBAR[0x7F14]))
+#define MCF_CTM_CTCR6                        (*(volatile uint32_t*)(&_MBAR[0x7F18]))
+#define MCF_CTM_CTCR7                        (*(volatile uint32_t*)(&_MBAR[0x7F1C]))
+#define MCF_CTM_CTCRF(x)                     (*(volatile uint32_t*)(&_MBAR[0x7F00 + ((x)*0x4)]))
+#define MCF_CTM_CTCRV(x)                     (*(volatile uint32_t*)(&_MBAR[0x7F10 + ((x-4)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_CTM_CTCRF */
+#define MCF_CTM_CTCRF_CRV(x)                 (((x)&0xFFFF)<<0)
+#define MCF_CTM_CTCRF_S(x)                   (((x)&0xF)<<0x10)
+#define MCF_CTM_CTCRF_S_CLK_1                (0)
+#define MCF_CTM_CTCRF_S_CLK_2                (0x10000)
+#define MCF_CTM_CTCRF_S_CLK_4                (0x20000)
+#define MCF_CTM_CTCRF_S_CLK_8                (0x30000)
+#define MCF_CTM_CTCRF_S_CLK_16               (0x40000)
+#define MCF_CTM_CTCRF_S_CLK_32               (0x50000)
+#define MCF_CTM_CTCRF_S_CLK_64               (0x60000)
+#define MCF_CTM_CTCRF_S_CLK_128              (0x70000)
+#define MCF_CTM_CTCRF_S_CLK_256              (0x80000)
+#define MCF_CTM_CTCRF_S_CLK_EXT              (0x90000)
+#define MCF_CTM_CTCRF_PCT(x)                 (((x)&0x7)<<0x14)
+#define MCF_CTM_CTCRF_PCT_100                (0)
+#define MCF_CTM_CTCRF_PCT_50                 (0x100000)
+#define MCF_CTM_CTCRF_PCT_25                 (0x200000)
+#define MCF_CTM_CTCRF_PCT_12p5               (0x300000)
+#define MCF_CTM_CTCRF_PCT_6p25               (0x400000)
+#define MCF_CTM_CTCRF_PCT_OFF                (0x500000)
+#define MCF_CTM_CTCRF_M                      (0x800000)
+#define MCF_CTM_CTCRF_IM                     (0x1000000)
+#define MCF_CTM_CTCRF_I                      (0x80000000)
+
+/* Bit definitions and macros for MCF_CTM_CTCRV */
+#define MCF_CTM_CTCRV_CRV(x)                 (((x)&0xFFFFFF)<<0)
+#define MCF_CTM_CTCRV_PCT(x)                 (((x)&0x7)<<0x18)
+#define MCF_CTM_CTCRV_PCT_100                (0)
+#define MCF_CTM_CTCRV_PCT_50                 (0x1000000)
+#define MCF_CTM_CTCRV_PCT_25                 (0x2000000)
+#define MCF_CTM_CTCRV_PCT_12p5               (0x3000000)
+#define MCF_CTM_CTCRV_PCT_6p25               (0x4000000)
+#define MCF_CTM_CTCRV_PCT_OFF                (0x5000000)
+#define MCF_CTM_CTCRV_M                      (0x8000000)
+#define MCF_CTM_CTCRV_S                      (0x10000000)
+
+
+#endif /* __MCF5475_CTM_H__ */

tos/jtagwait/include/MCF5475_DMA.h

@@ -0,0 +1,234 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_DMA_H__
+#define __MCF5475_DMA_H__
+
+
+/*********************************************************************
+*
+* Multichannel DMA (DMA)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DMA_TASKBAR                      (*(volatile uint32_t*)(&_MBAR[0x8000]))
+#define MCF_DMA_CP                           (*(volatile uint32_t*)(&_MBAR[0x8004]))
+#define MCF_DMA_EP                           (*(volatile uint32_t*)(&_MBAR[0x8008]))
+#define MCF_DMA_VP                           (*(volatile uint32_t*)(&_MBAR[0x800C]))
+#define MCF_DMA_PTD                          (*(volatile uint32_t*)(&_MBAR[0x8010]))
+#define MCF_DMA_DIPR                         (*(volatile uint32_t*)(&_MBAR[0x8014]))
+#define MCF_DMA_DIMR                         (*(volatile uint32_t*)(&_MBAR[0x8018]))
+#define MCF_DMA_TCR0                         (*(volatile uint16_t*)(&_MBAR[0x801C]))
+#define MCF_DMA_TCR1                         (*(volatile uint16_t*)(&_MBAR[0x801E]))
+#define MCF_DMA_TCR2                         (*(volatile uint16_t*)(&_MBAR[0x8020]))
+#define MCF_DMA_TCR3                         (*(volatile uint16_t*)(&_MBAR[0x8022]))
+#define MCF_DMA_TCR4                         (*(volatile uint16_t*)(&_MBAR[0x8024]))
+#define MCF_DMA_TCR5                         (*(volatile uint16_t*)(&_MBAR[0x8026]))
+#define MCF_DMA_TCR6                         (*(volatile uint16_t*)(&_MBAR[0x8028]))
+#define MCF_DMA_TCR7                         (*(volatile uint16_t*)(&_MBAR[0x802A]))
+#define MCF_DMA_TCR8                         (*(volatile uint16_t*)(&_MBAR[0x802C]))
+#define MCF_DMA_TCR9                         (*(volatile uint16_t*)(&_MBAR[0x802E]))
+#define MCF_DMA_TCR10                        (*(volatile uint16_t*)(&_MBAR[0x8030]))
+#define MCF_DMA_TCR11                        (*(volatile uint16_t*)(&_MBAR[0x8032]))
+#define MCF_DMA_TCR12                        (*(volatile uint16_t*)(&_MBAR[0x8034]))
+#define MCF_DMA_TCR13                        (*(volatile uint16_t*)(&_MBAR[0x8036]))
+#define MCF_DMA_TCR14                        (*(volatile uint16_t*)(&_MBAR[0x8038]))
+#define MCF_DMA_TCR15                        (*(volatile uint16_t*)(&_MBAR[0x803A]))
+#define MCF_DMA_PRIOR0                       (*(volatile uint8_t *)(&_MBAR[0x803C]))
+#define MCF_DMA_PRIOR1                       (*(volatile uint8_t *)(&_MBAR[0x803D]))
+#define MCF_DMA_PRIOR2                       (*(volatile uint8_t *)(&_MBAR[0x803E]))
+#define MCF_DMA_PRIOR3                       (*(volatile uint8_t *)(&_MBAR[0x803F]))
+#define MCF_DMA_PRIOR4                       (*(volatile uint8_t *)(&_MBAR[0x8040]))
+#define MCF_DMA_PRIOR5                       (*(volatile uint8_t *)(&_MBAR[0x8041]))
+#define MCF_DMA_PRIOR6                       (*(volatile uint8_t *)(&_MBAR[0x8042]))
+#define MCF_DMA_PRIOR7                       (*(volatile uint8_t *)(&_MBAR[0x8043]))
+#define MCF_DMA_PRIOR8                       (*(volatile uint8_t *)(&_MBAR[0x8044]))
+#define MCF_DMA_PRIOR9                       (*(volatile uint8_t *)(&_MBAR[0x8045]))
+#define MCF_DMA_PRIOR10                      (*(volatile uint8_t *)(&_MBAR[0x8046]))
+#define MCF_DMA_PRIOR11                      (*(volatile uint8_t *)(&_MBAR[0x8047]))
+#define MCF_DMA_PRIOR12                      (*(volatile uint8_t *)(&_MBAR[0x8048]))
+#define MCF_DMA_PRIOR13                      (*(volatile uint8_t *)(&_MBAR[0x8049]))
+#define MCF_DMA_PRIOR14                      (*(volatile uint8_t *)(&_MBAR[0x804A]))
+#define MCF_DMA_PRIOR15                      (*(volatile uint8_t *)(&_MBAR[0x804B]))
+#define MCF_DMA_PRIOR16                      (*(volatile uint8_t *)(&_MBAR[0x804C]))
+#define MCF_DMA_PRIOR17                      (*(volatile uint8_t *)(&_MBAR[0x804D]))
+#define MCF_DMA_PRIOR18                      (*(volatile uint8_t *)(&_MBAR[0x804E]))
+#define MCF_DMA_PRIOR19                      (*(volatile uint8_t *)(&_MBAR[0x804F]))
+#define MCF_DMA_PRIOR20                      (*(volatile uint8_t *)(&_MBAR[0x8050]))
+#define MCF_DMA_PRIOR21                      (*(volatile uint8_t *)(&_MBAR[0x8051]))
+#define MCF_DMA_PRIOR22                      (*(volatile uint8_t *)(&_MBAR[0x8052]))
+#define MCF_DMA_PRIOR23                      (*(volatile uint8_t *)(&_MBAR[0x8053]))
+#define MCF_DMA_PRIOR24                      (*(volatile uint8_t *)(&_MBAR[0x8054]))
+#define MCF_DMA_PRIOR25                      (*(volatile uint8_t *)(&_MBAR[0x8055]))
+#define MCF_DMA_PRIOR26                      (*(volatile uint8_t *)(&_MBAR[0x8056]))
+#define MCF_DMA_PRIOR27                      (*(volatile uint8_t *)(&_MBAR[0x8057]))
+#define MCF_DMA_PRIOR28                      (*(volatile uint8_t *)(&_MBAR[0x8058]))
+#define MCF_DMA_PRIOR29                      (*(volatile uint8_t *)(&_MBAR[0x8059]))
+#define MCF_DMA_PRIOR30                      (*(volatile uint8_t *)(&_MBAR[0x805A]))
+#define MCF_DMA_PRIOR31                      (*(volatile uint8_t *)(&_MBAR[0x805B]))
+#define MCF_DMA_IMCR                         (*(volatile uint32_t*)(&_MBAR[0x805C]))
+#define MCF_DMA_TSKSZ0                       (*(volatile uint32_t*)(&_MBAR[0x8060]))
+#define MCF_DMA_TSKSZ1                       (*(volatile uint32_t*)(&_MBAR[0x8064]))
+#define MCF_DMA_DBGCOMP0                     (*(volatile uint32_t*)(&_MBAR[0x8070]))
+#define MCF_DMA_DBGCOMP2                     (*(volatile uint32_t*)(&_MBAR[0x8074]))
+#define MCF_DMA_DBGCTL                       (*(volatile uint32_t*)(&_MBAR[0x8078]))
+#define MCF_DMA_TCR(x)                       (*(volatile uint16_t*)(&_MBAR[0x801C + ((x)*0x2)]))
+#define MCF_DMA_PRIOR(x)                     (*(volatile uint8_t *)(&_MBAR[0x803C + ((x)*0x1)]))
+
+
+/* Bit definitions and macros for MCF_DMA_TASKBAR */
+#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_CP */
+#define MCF_DMA_CP_DESCRIPTOR_POINTER(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_EP */
+#define MCF_DMA_EP_DESCRIPTOR_POINTER(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_VP */
+#define MCF_DMA_VP_VARIABLE_POINTER(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_PTD */
+#define MCF_DMA_PTD_PCTL0                    (0x1)
+#define MCF_DMA_PTD_PCTL1                    (0x2)
+#define MCF_DMA_PTD_PCTL13                   (0x2000)
+#define MCF_DMA_PTD_PCTL14                   (0x4000)
+#define MCF_DMA_PTD_PCTL15                   (0x8000)
+
+/* Bit definitions and macros for MCF_DMA_DIPR */
+#define MCF_DMA_DIPR_TASK(x)                 (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DIMR */
+#define MCF_DMA_DIMR_TASK(x)                 (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_TCR */
+#define MCF_DMA_TCR_ASTSKNUM(x)              (((x)&0xF)<<0)
+#define MCF_DMA_TCR_HLDINITNUM               (0x20)
+#define MCF_DMA_TCR_HIPRITSKEN               (0x40)
+#define MCF_DMA_TCR_ASTRT                    (0x80)
+#define MCF_DMA_TCR_INITNUM(x)               (((x)&0x1F)<<0x8)
+#define MCF_DMA_TCR_ALWINIT                  (0x2000)
+#define MCF_DMA_TCR_V                        (0x4000)
+#define MCF_DMA_TCR_EN                       (0x8000)
+
+/* Bit definitions and macros for MCF_DMA_PRIOR */
+#define MCF_DMA_PRIOR_PRI(x)                 (((x)&0x7)<<0)
+#define MCF_DMA_PRIOR_HLD                    (0x80)
+
+/* Bit definitions and macros for MCF_DMA_IMCR */
+#define MCF_DMA_IMCR_IMC16(x)	(((x)&0x3)<<0)
+#define MCF_DMA_IMCR_IMC17(x)	(((x)&0x3)<<0x2)
+#define MCF_DMA_IMCR_IMC18(x)	(((x)&0x3)<<0x4)
+#define MCF_DMA_IMCR_IMC19(x)	(((x)&0x3)<<0x6)
+#define MCF_DMA_IMCR_IMC20(x)	(((x)&0x3)<<0x8)
+#define MCF_DMA_IMCR_IMC21(x)	(((x)&0x3)<<0xA)
+#define MCF_DMA_IMCR_IMC22(x)	(((x)&0x3)<<0xC)
+#define MCF_DMA_IMCR_IMC23(x)	(((x)&0x3)<<0xE)
+#define MCF_DMA_IMCR_IMC24(x)	(((x)&0x3)<<0x10)
+#define MCF_DMA_IMCR_IMC25(x)	(((x)&0x3)<<0x12)
+#define MCF_DMA_IMCR_IMC26(x)	(((x)&0x3)<<0x14)
+#define MCF_DMA_IMCR_IMC27(x)	(((x)&0x3)<<0x16)
+#define MCF_DMA_IMCR_IMC28(x)	(((x)&0x3)<<0x18)
+#define MCF_DMA_IMCR_IMC29(x)	(((x)&0x3)<<0x1A)
+#define MCF_DMA_IMCR_IMC30(x)	(((x)&0x3)<<0x1C)
+#define MCF_DMA_IMCR_IMC31(x)	(((x)&0x3)<<0x1E)
+
+
+#define MCF_DMA_IMCR_IMC16_FEC0RX    (0x00000000)
+#define MCF_DMA_IMCR_IMC17_FEC0TX    (0x00000000)
+#define MCF_DMA_IMCR_IMC18_FEC0RX    (0x00000020)
+#define MCF_DMA_IMCR_IMC19_FEC0TX    (0x00000080)
+#define MCF_DMA_IMCR_IMC20_FEC1RX    (0x00000100)
+#define MCF_DMA_IMCR_IMC21_DREQ1     (0x00000000)
+#define MCF_DMA_IMCR_IMC21_FEC1TX    (0x00000400)
+#define MCF_DMA_IMCR_IMC22_FEC0RX    (0x00001000)
+#define MCF_DMA_IMCR_IMC23_FEC0TX    (0x00004000)
+#define MCF_DMA_IMCR_IMC24_CTM0      (0x00010000)
+#define MCF_DMA_IMCR_IMC24_FEC1RX    (0x00020000)
+#define MCF_DMA_IMCR_IMC25_CTM1      (0x00040000)
+#define MCF_DMA_IMCR_IMC25_FEC1TX    (0x00080000)
+#define MCF_DMA_IMCR_IMC26_USBEP4    (0x00000000)
+#define MCF_DMA_IMCR_IMC26_CTM2      (0x00200000)
+#define MCF_DMA_IMCR_IMC27_USBEP5    (0x00000000)
+#define MCF_DMA_IMCR_IMC27_CTM3      (0x00800000)
+#define MCF_DMA_IMCR_IMC28_USBEP6    (0x00000000)
+#define MCF_DMA_IMCR_IMC28_CTM4      (0x01000000)
+#define MCF_DMA_IMCR_IMC28_DREQ1     (0x02000000)
+#define MCF_DMA_IMCR_IMC28_PSC2RX    (0x03000000)
+#define MCF_DMA_IMCR_IMC29_DREQ1     (0x04000000)
+#define MCF_DMA_IMCR_IMC29_CTM5      (0x08000000)
+#define MCF_DMA_IMCR_IMC29_PSC2TX    (0x0C000000)
+#define MCF_DMA_IMCR_IMC30_FEC1RX    (0x00000000)
+#define MCF_DMA_IMCR_IMC30_CTM6      (0x10000000)
+#define MCF_DMA_IMCR_IMC30_PSC3RX    (0x30000000)
+#define MCF_DMA_IMCR_IMC31_FEC1TX    (0x00000000)
+#define MCF_DMA_IMCR_IMC31_CTM7      (0x80000000)
+#define MCF_DMA_IMCR_IMC31_PSC3TX    (0xC0000000)
+
+/* Bit definitions and macros for MCF_DMA_TSKSZ0 */
+#define MCF_DMA_TSKSZ0_DSTSZ7(x)             (((x)&0x3)<<0)
+#define MCF_DMA_TSKSZ0_SRCSZ7(x)             (((x)&0x3)<<0x2)
+#define MCF_DMA_TSKSZ0_DSTSZ6(x)             (((x)&0x3)<<0x4)
+#define MCF_DMA_TSKSZ0_SRCSZ6(x)             (((x)&0x3)<<0x6)
+#define MCF_DMA_TSKSZ0_DSTSZ5(x)             (((x)&0x3)<<0x8)
+#define MCF_DMA_TSKSZ0_SRCSZ5(x)             (((x)&0x3)<<0xA)
+#define MCF_DMA_TSKSZ0_DSTSZ4(x)             (((x)&0x3)<<0xC)
+#define MCF_DMA_TSKSZ0_SRCSZ4(x)             (((x)&0x3)<<0xE)
+#define MCF_DMA_TSKSZ0_DSTSZ3(x)             (((x)&0x3)<<0x10)
+#define MCF_DMA_TSKSZ0_SRCSZ3(x)             (((x)&0x3)<<0x12)
+#define MCF_DMA_TSKSZ0_DSTSZ2(x)             (((x)&0x3)<<0x14)
+#define MCF_DMA_TSKSZ0_SRCSZ2(x)             (((x)&0x3)<<0x16)
+#define MCF_DMA_TSKSZ0_DSTSZ1(x)             (((x)&0x3)<<0x18)
+#define MCF_DMA_TSKSZ0_SRCSZ1(x)             (((x)&0x3)<<0x1A)
+#define MCF_DMA_TSKSZ0_DSTSZ0(x)             (((x)&0x3)<<0x1C)
+#define MCF_DMA_TSKSZ0_SRCSZ0(x)             (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_DMA_TSKSZ1 */
+#define MCF_DMA_TSKSZ1_DSTSZ15(x)            (((x)&0x3)<<0)
+#define MCF_DMA_TSKSZ1_SRCSZ15(x)            (((x)&0x3)<<0x2)
+#define MCF_DMA_TSKSZ1_DSTSZ14(x)            (((x)&0x3)<<0x4)
+#define MCF_DMA_TSKSZ1_SRCSZ14(x)            (((x)&0x3)<<0x6)
+#define MCF_DMA_TSKSZ1_DSTSZ13(x)            (((x)&0x3)<<0x8)
+#define MCF_DMA_TSKSZ1_SRCSZ13(x)            (((x)&0x3)<<0xA)
+#define MCF_DMA_TSKSZ1_DSTSZ12(x)            (((x)&0x3)<<0xC)
+#define MCF_DMA_TSKSZ1_SRCSZ12(x)            (((x)&0x3)<<0xE)
+#define MCF_DMA_TSKSZ1_DSTSZ11(x)            (((x)&0x3)<<0x10)
+#define MCF_DMA_TSKSZ1_SRCSZ11(x)            (((x)&0x3)<<0x12)
+#define MCF_DMA_TSKSZ1_DSTSZ10(x)            (((x)&0x3)<<0x14)
+#define MCF_DMA_TSKSZ1_SRCSZ10(x)            (((x)&0x3)<<0x16)
+#define MCF_DMA_TSKSZ1_DSTSZ9(x)             (((x)&0x3)<<0x18)
+#define MCF_DMA_TSKSZ1_SRCSZ9(x)             (((x)&0x3)<<0x1A)
+#define MCF_DMA_TSKSZ1_DSTSZ8(x)             (((x)&0x3)<<0x1C)
+#define MCF_DMA_TSKSZ1_SRCSZ8(x)             (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */
+#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */
+#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DBGCTL */
+#define MCF_DMA_DBGCTL_I                     (0x2)
+#define MCF_DMA_DBGCTL_E                     (0x4)
+#define MCF_DMA_DBGCTL_AND_OR                (0x80)
+#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x)  (((x)&0x7)<<0x8)
+#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x)  (((x)&0x7)<<0xB)
+#define MCF_DMA_DBGCTL_B                     (0x4000)
+#define MCF_DMA_DBGCTL_AA                    (0x8000)
+#define MCF_DMA_DBGCTL_BLOCK_TASKS(x)        (((x)&0xFFFF)<<0x10)
+
+
+#endif /* __MCF5475_DMA_H__ */

tos/jtagwait/include/MCF5475_DSPI.h

@@ -0,0 +1,150 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_DSPI_H__
+#define __MCF5475_DSPI_H__
+
+
+/*********************************************************************
+*
+* DMA Serial Peripheral Interface (DSPI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DSPI_DMCR                        (*(volatile uint32_t*)(&_MBAR[0x8A00]))
+#define MCF_DSPI_DTCR                        (*(volatile uint32_t*)(&_MBAR[0x8A08]))
+#define MCF_DSPI_DCTAR0                      (*(volatile uint32_t*)(&_MBAR[0x8A0C]))
+#define MCF_DSPI_DCTAR1                      (*(volatile uint32_t*)(&_MBAR[0x8A10]))
+#define MCF_DSPI_DCTAR2                      (*(volatile uint32_t*)(&_MBAR[0x8A14]))
+#define MCF_DSPI_DCTAR3                      (*(volatile uint32_t*)(&_MBAR[0x8A18]))
+#define MCF_DSPI_DCTAR4                      (*(volatile uint32_t*)(&_MBAR[0x8A1C]))
+#define MCF_DSPI_DCTAR5                      (*(volatile uint32_t*)(&_MBAR[0x8A20]))
+#define MCF_DSPI_DCTAR6                      (*(volatile uint32_t*)(&_MBAR[0x8A24]))
+#define MCF_DSPI_DCTAR7                      (*(volatile uint32_t*)(&_MBAR[0x8A28]))
+#define MCF_DSPI_DSR                         (*(volatile uint32_t*)(&_MBAR[0x8A2C]))
+#define MCF_DSPI_DIRSR                       (*(volatile uint32_t*)(&_MBAR[0x8A30]))
+#define MCF_DSPI_DTFR                        (*(volatile uint32_t*)(&_MBAR[0x8A34]))
+#define MCF_DSPI_DRFR                        (*(volatile uint32_t*)(&_MBAR[0x8A38]))
+#define MCF_DSPI_DTFDR0                      (*(volatile uint32_t*)(&_MBAR[0x8A3C]))
+#define MCF_DSPI_DTFDR1                      (*(volatile uint32_t*)(&_MBAR[0x8A40]))
+#define MCF_DSPI_DTFDR2                      (*(volatile uint32_t*)(&_MBAR[0x8A44]))
+#define MCF_DSPI_DTFDR3                      (*(volatile uint32_t*)(&_MBAR[0x8A48]))
+#define MCF_DSPI_DRFDR0                      (*(volatile uint32_t*)(&_MBAR[0x8A7C]))
+#define MCF_DSPI_DRFDR1                      (*(volatile uint32_t*)(&_MBAR[0x8A80]))
+#define MCF_DSPI_DRFDR2                      (*(volatile uint32_t*)(&_MBAR[0x8A84]))
+#define MCF_DSPI_DRFDR3                      (*(volatile uint32_t*)(&_MBAR[0x8A88]))
+#define MCF_DSPI_DCTAR(x)                    (*(volatile uint32_t*)(&_MBAR[0x8A0C + ((x)*0x4)]))
+#define MCF_DSPI_DTFDR(x)                    (*(volatile uint32_t*)(&_MBAR[0x8A3C + ((x)*0x4)]))
+#define MCF_DSPI_DRFDR(x)                    (*(volatile uint32_t*)(&_MBAR[0x8A7C + ((x)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_DSPI_DMCR */
+#define MCF_DSPI_DMCR_HALT                   (0x1)
+#define MCF_DSPI_DMCR_SMPL_PT(x)             (((x)&0x3)<<0x8)
+#define MCF_DSPI_DMCR_SMPL_PT_0CLK           (0)
+#define MCF_DSPI_DMCR_SMPL_PT_1CLK           (0x100)
+#define MCF_DSPI_DMCR_SMPL_PT_2CLK           (0x200)
+#define MCF_DSPI_DMCR_CRXF                   (0x400)
+#define MCF_DSPI_DMCR_CTXF                   (0x800)
+#define MCF_DSPI_DMCR_DRXF                   (0x1000)
+#define MCF_DSPI_DMCR_DTXF                   (0x2000)
+#define MCF_DSPI_DMCR_CSIS0                  (0x10000)
+#define MCF_DSPI_DMCR_CSIS2                  (0x40000)
+#define MCF_DSPI_DMCR_CSIS3                  (0x80000)
+#define MCF_DSPI_DMCR_CSIS5                  (0x200000)
+#define MCF_DSPI_DMCR_ROOE                   (0x1000000)
+#define MCF_DSPI_DMCR_PCSSE                  (0x2000000)
+#define MCF_DSPI_DMCR_MTFE                   (0x4000000)
+#define MCF_DSPI_DMCR_FRZ                    (0x8000000)
+#define MCF_DSPI_DMCR_DCONF(x)               (((x)&0x3)<<0x1C)
+#define MCF_DSPI_DMCR_CSCK                   (0x40000000)
+#define MCF_DSPI_DMCR_MSTR                   (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DTCR */
+#define MCF_DSPI_DTCR_SPI_TCNT(x)            (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_DSPI_DCTAR */
+#define MCF_DSPI_DCTAR_BR(x)                 (((x)&0xF)<<0)
+#define MCF_DSPI_DCTAR_DT(x)                 (((x)&0xF)<<0x4)
+#define MCF_DSPI_DCTAR_ASC(x)                (((x)&0xF)<<0x8)
+#define MCF_DSPI_DCTAR_CSSCK(x)              (((x)&0xF)<<0xC)
+#define MCF_DSPI_DCTAR_PBR(x)                (((x)&0x3)<<0x10)
+#define MCF_DSPI_DCTAR_PBR_1CLK              (0)
+#define MCF_DSPI_DCTAR_PBR_3CLK              (0x10000)
+#define MCF_DSPI_DCTAR_PBR_5CLK              (0x20000)
+#define MCF_DSPI_DCTAR_PBR_7CLK              (0x30000)
+#define MCF_DSPI_DCTAR_PDT(x)                (((x)&0x3)<<0x12)
+#define MCF_DSPI_DCTAR_PDT_1CLK              (0)
+#define MCF_DSPI_DCTAR_PDT_3CLK              (0x40000)
+#define MCF_DSPI_DCTAR_PDT_5CLK              (0x80000)
+#define MCF_DSPI_DCTAR_PDT_7CLK              (0xC0000)
+#define MCF_DSPI_DCTAR_PASC(x)               (((x)&0x3)<<0x14)
+#define MCF_DSPI_DCTAR_PASC_1CLK             (0)
+#define MCF_DSPI_DCTAR_PASC_3CLK             (0x100000)
+#define MCF_DSPI_DCTAR_PASC_5CLK             (0x200000)
+#define MCF_DSPI_DCTAR_PASC_7CLK             (0x300000)
+#define MCF_DSPI_DCTAR_PCSSCK(x)             (((x)&0x3)<<0x16)
+#define MCF_DSPI_DCTAR_LSBFE                 (0x1000000)
+#define MCF_DSPI_DCTAR_CPHA                  (0x2000000)
+#define MCF_DSPI_DCTAR_CPOL                  (0x4000000)
+#define MCF_DSPI_DCTAR_TRSZ(x)               (((x)&0xF)<<0x1B)
+
+/* Bit definitions and macros for MCF_DSPI_DSR */
+#define MCF_DSPI_DSR_RXPTR(x)                (((x)&0xF)<<0)
+#define MCF_DSPI_DSR_RXCTR(x)                (((x)&0xF)<<0x4)
+#define MCF_DSPI_DSR_TXPTR(x)                (((x)&0xF)<<0x8)
+#define MCF_DSPI_DSR_TXCTR(x)                (((x)&0xF)<<0xC)
+#define MCF_DSPI_DSR_RFDF                    (0x20000)
+#define MCF_DSPI_DSR_RFOF                    (0x80000)
+#define MCF_DSPI_DSR_TFFF                    (0x2000000)
+#define MCF_DSPI_DSR_TFUF                    (0x8000000)
+#define MCF_DSPI_DSR_EOQF                    (0x10000000)
+#define MCF_DSPI_DSR_TXRXS                   (0x40000000)
+#define MCF_DSPI_DSR_TCF                     (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DIRSR */
+#define MCF_DSPI_DIRSR_RFDFS                 (0x10000)
+#define MCF_DSPI_DIRSR_RFDFE                 (0x20000)
+#define MCF_DSPI_DIRSR_RFOFE                 (0x80000)
+#define MCF_DSPI_DIRSR_TFFFS                 (0x1000000)
+#define MCF_DSPI_DIRSR_TFFFE                 (0x2000000)
+#define MCF_DSPI_DIRSR_TFUFE                 (0x8000000)
+#define MCF_DSPI_DIRSR_EOQFE                 (0x10000000)
+#define MCF_DSPI_DIRSR_TCFE                  (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DTFR */
+#define MCF_DSPI_DTFR_TXDATA(x)              (((x)&0xFFFF)<<0)
+#define MCF_DSPI_DTFR_CS0                    (0x10000)
+#define MCF_DSPI_DTFR_CS2                    (0x40000)
+#define MCF_DSPI_DTFR_CS3                    (0x80000)
+#define MCF_DSPI_DTFR_CS5                    (0x200000)
+#define MCF_DSPI_DTFR_CTCNT                  (0x4000000)
+#define MCF_DSPI_DTFR_EOQ                    (0x8000000)
+#define MCF_DSPI_DTFR_CTAS(x)                (((x)&0x7)<<0x1C)
+#define MCF_DSPI_DTFR_CONT                   (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DRFR */
+#define MCF_DSPI_DRFR_RXDATA(x)              (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DSPI_DTFDR */
+#define MCF_DSPI_DTFDR_TXDATA(x)             (((x)&0xFFFF)<<0)
+#define MCF_DSPI_DTFDR_TXCMD(x)              (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_DSPI_DRFDR */
+#define MCF_DSPI_DRFDR_RXDATA(x)             (((x)&0xFFFF)<<0)
+
+
+#endif /* __MCF5475_DSPI_H__ */

tos/jtagwait/include/MCF5475_EPORT.h

@@ -0,0 +1,123 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_EPORT_H__
+#define __MCF5475_EPORT_H__
+
+
+/*********************************************************************
+*
+* Edge Port Module (EPORT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_EPORT_EPPAR                      (*(volatile uint16_t*)(&_MBAR[0xF00]))
+#define MCF_EPORT_EPDDR                      (*(volatile uint8_t *)(&_MBAR[0xF04]))
+#define MCF_EPORT_EPIER                      (*(volatile uint8_t *)(&_MBAR[0xF05]))
+#define MCF_EPORT_EPDR                       (*(volatile uint8_t *)(&_MBAR[0xF08]))
+#define MCF_EPORT_EPPDR                      (*(volatile uint8_t *)(&_MBAR[0xF09]))
+#define MCF_EPORT_EPFR                       (*(volatile uint8_t *)(&_MBAR[0xF0C]))
+
+
+
+/* Bit definitions and macros for MCF_EPORT_EPPAR */
+#define MCF_EPORT_EPPAR_EPPA1(x)             (((x)&0x3)<<0x2)
+#define MCF_EPORT_EPPAR_EPPA1_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA1_RISING         (0x4)
+#define MCF_EPORT_EPPAR_EPPA1_FALLING        (0x8)
+#define MCF_EPORT_EPPAR_EPPA1_BOTH           (0xC)
+#define MCF_EPORT_EPPAR_EPPA2(x)             (((x)&0x3)<<0x4)
+#define MCF_EPORT_EPPAR_EPPA2_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA2_RISING         (0x10)
+#define MCF_EPORT_EPPAR_EPPA2_FALLING        (0x20)
+#define MCF_EPORT_EPPAR_EPPA2_BOTH           (0x30)
+#define MCF_EPORT_EPPAR_EPPA3(x)             (((x)&0x3)<<0x6)
+#define MCF_EPORT_EPPAR_EPPA3_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA3_RISING         (0x40)
+#define MCF_EPORT_EPPAR_EPPA3_FALLING        (0x80)
+#define MCF_EPORT_EPPAR_EPPA3_BOTH           (0xC0)
+#define MCF_EPORT_EPPAR_EPPA4(x)             (((x)&0x3)<<0x8)
+#define MCF_EPORT_EPPAR_EPPA4_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA4_RISING         (0x100)
+#define MCF_EPORT_EPPAR_EPPA4_FALLING        (0x200)
+#define MCF_EPORT_EPPAR_EPPA4_BOTH           (0x300)
+#define MCF_EPORT_EPPAR_EPPA5(x)             (((x)&0x3)<<0xA)
+#define MCF_EPORT_EPPAR_EPPA5_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA5_RISING         (0x400)
+#define MCF_EPORT_EPPAR_EPPA5_FALLING        (0x800)
+#define MCF_EPORT_EPPAR_EPPA5_BOTH           (0xC00)
+#define MCF_EPORT_EPPAR_EPPA6(x)             (((x)&0x3)<<0xC)
+#define MCF_EPORT_EPPAR_EPPA6_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA6_RISING         (0x1000)
+#define MCF_EPORT_EPPAR_EPPA6_FALLING        (0x2000)
+#define MCF_EPORT_EPPAR_EPPA6_BOTH           (0x3000)
+#define MCF_EPORT_EPPAR_EPPA7(x)             (((x)&0x3)<<0xE)
+#define MCF_EPORT_EPPAR_EPPA7_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA7_RISING         (0x4000)
+#define MCF_EPORT_EPPAR_EPPA7_FALLING        (0x8000)
+#define MCF_EPORT_EPPAR_EPPA7_BOTH           (0xC000)
+#define MCF_EPORT_EPPAR_LEVEL                (0)
+#define MCF_EPORT_EPPAR_RISING               (0x1)
+#define MCF_EPORT_EPPAR_FALLING              (0x2)
+#define MCF_EPORT_EPPAR_BOTH                 (0x3)
+
+/* Bit definitions and macros for MCF_EPORT_EPDDR */
+#define MCF_EPORT_EPDDR_EPDD1                (0x2)
+#define MCF_EPORT_EPDDR_EPDD2                (0x4)
+#define MCF_EPORT_EPDDR_EPDD3                (0x8)
+#define MCF_EPORT_EPDDR_EPDD4                (0x10)
+#define MCF_EPORT_EPDDR_EPDD5                (0x20)
+#define MCF_EPORT_EPDDR_EPDD6                (0x40)
+#define MCF_EPORT_EPDDR_EPDD7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPIER */
+#define MCF_EPORT_EPIER_EPIE1                (0x2)
+#define MCF_EPORT_EPIER_EPIE2                (0x4)
+#define MCF_EPORT_EPIER_EPIE3                (0x8)
+#define MCF_EPORT_EPIER_EPIE4                (0x10)
+#define MCF_EPORT_EPIER_EPIE5                (0x20)
+#define MCF_EPORT_EPIER_EPIE6                (0x40)
+#define MCF_EPORT_EPIER_EPIE7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPDR */
+#define MCF_EPORT_EPDR_EPD1                  (0x2)
+#define MCF_EPORT_EPDR_EPD2                  (0x4)
+#define MCF_EPORT_EPDR_EPD3                  (0x8)
+#define MCF_EPORT_EPDR_EPD4                  (0x10)
+#define MCF_EPORT_EPDR_EPD5                  (0x20)
+#define MCF_EPORT_EPDR_EPD6                  (0x40)
+#define MCF_EPORT_EPDR_EPD7                  (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPPDR */
+#define MCF_EPORT_EPPDR_EPPD1                (0x2)
+#define MCF_EPORT_EPPDR_EPPD2                (0x4)
+#define MCF_EPORT_EPPDR_EPPD3                (0x8)
+#define MCF_EPORT_EPPDR_EPPD4                (0x10)
+#define MCF_EPORT_EPPDR_EPPD5                (0x20)
+#define MCF_EPORT_EPPDR_EPPD6                (0x40)
+#define MCF_EPORT_EPPDR_EPPD7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPFR */
+#define MCF_EPORT_EPFR_EPF1                  (0x2)
+#define MCF_EPORT_EPFR_EPF2                  (0x4)
+#define MCF_EPORT_EPFR_EPF3                  (0x8)
+#define MCF_EPORT_EPFR_EPF4                  (0x10)
+#define MCF_EPORT_EPFR_EPF5                  (0x20)
+#define MCF_EPORT_EPFR_EPF6                  (0x40)
+#define MCF_EPORT_EPFR_EPF7                  (0x80)
+
+
+#endif /* __MCF5475_EPORT_H__ */

tos/jtagwait/include/MCF5475_FBCS.h

@@ -0,0 +1,100 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_FBCS_H__
+#define __MCF5475_FBCS_H__
+
+
+/*********************************************************************
+*
+* FlexBus Chip Select Module (FBCS)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FBCS0_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x500]))
+#define MCF_FBCS0_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x504]))
+#define MCF_FBCS0_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x508]))
+
+#define MCF_FBCS1_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x50C]))
+#define MCF_FBCS1_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x510]))
+#define MCF_FBCS1_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x514]))
+
+#define MCF_FBCS2_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x518]))
+#define MCF_FBCS2_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x51C]))
+#define MCF_FBCS2_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x520]))
+
+#define MCF_FBCS3_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x524]))
+#define MCF_FBCS3_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x528]))
+#define MCF_FBCS3_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x52C]))
+
+#define MCF_FBCS4_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x530]))
+#define MCF_FBCS4_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x534]))
+#define MCF_FBCS4_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x538]))
+
+#define MCF_FBCS5_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x53C]))
+#define MCF_FBCS5_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x540]))
+#define MCF_FBCS5_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x544]))
+
+#define MCF_FBCS_CSAR(x)                     (*(volatile uint32_t*)(&_MBAR[0x500 + ((x)*0xC)]))
+#define MCF_FBCS_CSMR(x)                     (*(volatile uint32_t*)(&_MBAR[0x504 + ((x)*0xC)]))
+#define MCF_FBCS_CSCR(x)                     (*(volatile uint32_t*)(&_MBAR[0x508 + ((x)*0xC)]))
+
+
+/* Bit definitions and macros for MCF_FBCS_CSAR */
+#define MCF_FBCS_CSAR_BA(x)                  ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for MCF_FBCS_CSMR */
+#define MCF_FBCS_CSMR_V                      (0x1)
+#define MCF_FBCS_CSMR_WP                     (0x100)
+#define MCF_FBCS_CSMR_BAM(x)                 (((x)&0xFFFF)<<0x10)
+#define MCF_FBCS_CSMR_BAM_4G                 (0xFFFF0000)
+#define MCF_FBCS_CSMR_BAM_2G                 (0x7FFF0000)
+#define MCF_FBCS_CSMR_BAM_1G                 (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_1024M              (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_512M               (0x1FFF0000)
+#define MCF_FBCS_CSMR_BAM_256M               (0xFFF0000)
+#define MCF_FBCS_CSMR_BAM_128M               (0x7FF0000)
+#define MCF_FBCS_CSMR_BAM_64M                (0x3FF0000)
+#define MCF_FBCS_CSMR_BAM_32M                (0x1FF0000)
+#define MCF_FBCS_CSMR_BAM_16M                (0xFF0000)
+#define MCF_FBCS_CSMR_BAM_8M                 (0x7F0000)
+#define MCF_FBCS_CSMR_BAM_4M                 (0x3F0000)
+#define MCF_FBCS_CSMR_BAM_2M                 (0x1F0000)
+#define MCF_FBCS_CSMR_BAM_1M                 (0xF0000)
+#define MCF_FBCS_CSMR_BAM_1024K              (0xF0000)
+#define MCF_FBCS_CSMR_BAM_512K               (0x70000)
+#define MCF_FBCS_CSMR_BAM_256K               (0x30000)
+#define MCF_FBCS_CSMR_BAM_128K               (0x10000)
+#define MCF_FBCS_CSMR_BAM_64K                (0)
+
+/* Bit definitions and macros for MCF_FBCS_CSCR */
+#define MCF_FBCS_CSCR_BSTW                   (0x8)
+#define MCF_FBCS_CSCR_BSTR                   (0x10)
+#define MCF_FBCS_CSCR_BEM                    (0x20)
+#define MCF_FBCS_CSCR_PS(x)                  (((x)&0x3)<<0x6)
+#define MCF_FBCS_CSCR_PS_32                  (0)
+#define MCF_FBCS_CSCR_PS_8                   (0x40)
+#define MCF_FBCS_CSCR_PS_16                  (0x80)
+#define MCF_FBCS_CSCR_AA                     (0x100)
+#define MCF_FBCS_CSCR_WS(x)                  (((x)&0x3F)<<0xA)
+#define MCF_FBCS_CSCR_WRAH(x)                (((x)&0x3)<<0x10)
+#define MCF_FBCS_CSCR_RDAH(x)                (((x)&0x3)<<0x12)
+#define MCF_FBCS_CSCR_ASET(x)                (((x)&0x3)<<0x14)
+#define MCF_FBCS_CSCR_SWSEN                  (0x800000)
+#define MCF_FBCS_CSCR_SWS(x)                 (((x)&0x3F)<<0x1A)
+
+
+#endif /* __MCF5475_FBCS_H__ */

tos/jtagwait/include/MCF5475_FEC.h

@@ -0,0 +1,680 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_FEC_H__
+#define __MCF5475_FEC_H__
+
+
+/*********************************************************************
+*
+* Fast Ethernet Controller(FEC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FEC0_EIR                         (*(volatile uint32_t*)(&_MBAR[0x9004]))
+#define MCF_FEC0_EIMR                        (*(volatile uint32_t*)(&_MBAR[0x9008]))
+#define MCF_FEC0_ECR                         (*(volatile uint32_t*)(&_MBAR[0x9024]))
+#define MCF_FEC0_MMFR                        (*(volatile uint32_t*)(&_MBAR[0x9040]))
+#define MCF_FEC0_MSCR                        (*(volatile uint32_t*)(&_MBAR[0x9044]))
+#define MCF_FEC0_MIBC                        (*(volatile uint32_t*)(&_MBAR[0x9064]))
+#define MCF_FEC0_RCR                         (*(volatile uint32_t*)(&_MBAR[0x9084]))
+#define MCF_FEC0_RHR                         (*(volatile uint32_t*)(&_MBAR[0x9088]))
+#define MCF_FEC0_TCR                         (*(volatile uint32_t*)(&_MBAR[0x90C4]))
+#define MCF_FEC0_PALR                        (*(volatile uint32_t*)(&_MBAR[0x90E4]))
+#define MCF_FEC0_PAHR                        (*(volatile uint32_t*)(&_MBAR[0x90E8]))
+#define MCF_FEC0_OPD                         (*(volatile uint32_t*)(&_MBAR[0x90EC]))
+#define MCF_FEC0_IAUR                        (*(volatile uint32_t*)(&_MBAR[0x9118]))
+#define MCF_FEC0_IALR                        (*(volatile uint32_t*)(&_MBAR[0x911C]))
+#define MCF_FEC0_GAUR                        (*(volatile uint32_t*)(&_MBAR[0x9120]))
+#define MCF_FEC0_GALR                        (*(volatile uint32_t*)(&_MBAR[0x9124]))
+#define MCF_FEC0_FECTFWR                     (*(volatile uint32_t*)(&_MBAR[0x9144]))
+#define MCF_FEC0_FECRFDR                     (*(volatile uint32_t*)(&_MBAR[0x9184]))
+#define MCF_FEC0_FECRFSR                     (*(volatile uint32_t*)(&_MBAR[0x9188]))
+#define MCF_FEC0_FECRFCR                     (*(volatile uint32_t*)(&_MBAR[0x918C]))
+#define MCF_FEC0_FECRLRFP                    (*(volatile uint32_t*)(&_MBAR[0x9190]))
+#define MCF_FEC0_FECRLWFP                    (*(volatile uint32_t*)(&_MBAR[0x9194]))
+#define MCF_FEC0_FECRFAR                     (*(volatile uint32_t*)(&_MBAR[0x9198]))
+#define MCF_FEC0_FECRFRP                     (*(volatile uint32_t*)(&_MBAR[0x919C]))
+#define MCF_FEC0_FECRFWP                     (*(volatile uint32_t*)(&_MBAR[0x91A0]))
+#define MCF_FEC0_FECTFDR                     (*(volatile uint32_t*)(&_MBAR[0x91A4]))
+#define MCF_FEC0_FECTFSR                     (*(volatile uint32_t*)(&_MBAR[0x91A8]))
+#define MCF_FEC0_FECTFCR                     (*(volatile uint32_t*)(&_MBAR[0x91AC]))
+#define MCF_FEC0_FECTLRFP                    (*(volatile uint32_t*)(&_MBAR[0x91B0]))
+#define MCF_FEC0_FECTLWFP                    (*(volatile uint32_t*)(&_MBAR[0x91B4]))
+#define MCF_FEC0_FECTFAR                     (*(volatile uint32_t*)(&_MBAR[0x91B8]))
+#define MCF_FEC0_FECTFRP                     (*(volatile uint32_t*)(&_MBAR[0x91BC]))
+#define MCF_FEC0_FECTFWP                     (*(volatile uint32_t*)(&_MBAR[0x91C0]))
+#define MCF_FEC0_FECFRST                     (*(volatile uint32_t*)(&_MBAR[0x91C4]))
+#define MCF_FEC0_FECCTCWR                    (*(volatile uint32_t*)(&_MBAR[0x91C8]))
+#define MCF_FEC0_RMON_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9200]))
+#define MCF_FEC0_RMON_T_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9204]))
+#define MCF_FEC0_RMON_T_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9208]))
+#define MCF_FEC0_RMON_T_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x920C]))
+#define MCF_FEC0_RMON_T_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9210]))
+#define MCF_FEC0_RMON_T_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9214]))
+#define MCF_FEC0_RMON_T_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9218]))
+#define MCF_FEC0_RMON_T_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x921C]))
+#define MCF_FEC0_RMON_T_JAB                  (*(volatile uint32_t*)(&_MBAR[0x9220]))
+#define MCF_FEC0_RMON_T_COL                  (*(volatile uint32_t*)(&_MBAR[0x9224]))
+#define MCF_FEC0_RMON_T_P64                  (*(volatile uint32_t*)(&_MBAR[0x9228]))
+#define MCF_FEC0_RMON_T_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x922C]))
+#define MCF_FEC0_RMON_T_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x9230]))
+#define MCF_FEC0_RMON_T_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x9234]))
+#define MCF_FEC0_RMON_T_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x9238]))
+#define MCF_FEC0_RMON_T_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x923C]))
+#define MCF_FEC0_RMON_T_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x9240]))
+#define MCF_FEC0_RMON_T_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x9244]))
+#define MCF_FEC0_IEEE_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9248]))
+#define MCF_FEC0_IEEE_T_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x924C]))
+#define MCF_FEC0_IEEE_T_1COL                 (*(volatile uint32_t*)(&_MBAR[0x9250]))
+#define MCF_FEC0_IEEE_T_MCOL                 (*(volatile uint32_t*)(&_MBAR[0x9254]))
+#define MCF_FEC0_IEEE_T_DEF                  (*(volatile uint32_t*)(&_MBAR[0x9258]))
+#define MCF_FEC0_IEEE_T_LCOL                 (*(volatile uint32_t*)(&_MBAR[0x925C]))
+#define MCF_FEC0_IEEE_T_EXCOL                (*(volatile uint32_t*)(&_MBAR[0x9260]))
+#define MCF_FEC0_IEEE_T_MACERR               (*(volatile uint32_t*)(&_MBAR[0x9264]))
+#define MCF_FEC0_IEEE_T_CSERR                (*(volatile uint32_t*)(&_MBAR[0x9268]))
+#define MCF_FEC0_IEEE_T_SQE                  (*(volatile uint32_t*)(&_MBAR[0x926C]))
+#define MCF_FEC0_IEEE_T_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x9270]))
+#define MCF_FEC0_IEEE_T_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x9274]))
+#define MCF_FEC0_RMON_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9280]))
+#define MCF_FEC0_RMON_R_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9284]))
+#define MCF_FEC0_RMON_R_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9288]))
+#define MCF_FEC0_RMON_R_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x928C]))
+#define MCF_FEC0_RMON_R_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9290]))
+#define MCF_FEC0_RMON_R_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9294]))
+#define MCF_FEC0_RMON_R_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9298]))
+#define MCF_FEC0_RMON_R_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x929C]))
+#define MCF_FEC0_RMON_R_JAB                  (*(volatile uint32_t*)(&_MBAR[0x92A0]))
+#define MCF_FEC0_RMON_R_RESVD_0              (*(volatile uint32_t*)(&_MBAR[0x92A4]))
+#define MCF_FEC0_RMON_R_P64                  (*(volatile uint32_t*)(&_MBAR[0x92A8]))
+#define MCF_FEC0_RMON_R_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x92AC]))
+#define MCF_FEC0_RMON_R_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x92B0]))
+#define MCF_FEC0_RMON_R_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x92B4]))
+#define MCF_FEC0_RMON_R_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x92B8]))
+#define MCF_FEC0_RMON_R_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x92BC]))
+#define MCF_FEC0_RMON_R_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x92C0]))
+#define MCF_FEC0_RMON_R_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x92C4]))
+#define MCF_FEC0_IEEE_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x92C8]))
+#define MCF_FEC0_IEEE_R_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x92CC]))
+#define MCF_FEC0_IEEE_R_CRC                  (*(volatile uint32_t*)(&_MBAR[0x92D0]))
+#define MCF_FEC0_IEEE_R_ALIGN                (*(volatile uint32_t*)(&_MBAR[0x92D4]))
+#define MCF_FEC0_IEEE_R_MACERR               (*(volatile uint32_t*)(&_MBAR[0x92D8]))
+#define MCF_FEC0_IEEE_R_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x92DC]))
+#define MCF_FEC0_IEEE_R_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x92E0]))
+
+#define MCF_FEC1_EIR                         (*(volatile uint32_t*)(&_MBAR[0x9804]))
+#define MCF_FEC1_EIMR                        (*(volatile uint32_t*)(&_MBAR[0x9808]))
+#define MCF_FEC1_ECR                         (*(volatile uint32_t*)(&_MBAR[0x9824]))
+#define MCF_FEC1_MMFR                        (*(volatile uint32_t*)(&_MBAR[0x9840]))
+#define MCF_FEC1_MSCR                        (*(volatile uint32_t*)(&_MBAR[0x9844]))
+#define MCF_FEC1_MIBC                        (*(volatile uint32_t*)(&_MBAR[0x9864]))
+#define MCF_FEC1_RCR                         (*(volatile uint32_t*)(&_MBAR[0x9884]))
+#define MCF_FEC1_RHR                         (*(volatile uint32_t*)(&_MBAR[0x9888]))
+#define MCF_FEC1_TCR                         (*(volatile uint32_t*)(&_MBAR[0x98C4]))
+#define MCF_FEC1_PALR                        (*(volatile uint32_t*)(&_MBAR[0x98E4]))
+#define MCF_FEC1_PAHR                        (*(volatile uint32_t*)(&_MBAR[0x98E8]))
+#define MCF_FEC1_OPD                         (*(volatile uint32_t*)(&_MBAR[0x98EC]))
+#define MCF_FEC1_IAUR                        (*(volatile uint32_t*)(&_MBAR[0x9918]))
+#define MCF_FEC1_IALR                        (*(volatile uint32_t*)(&_MBAR[0x991C]))
+#define MCF_FEC1_GAUR                        (*(volatile uint32_t*)(&_MBAR[0x9920]))
+#define MCF_FEC1_GALR                        (*(volatile uint32_t*)(&_MBAR[0x9924]))
+#define MCF_FEC1_FECTFWR                     (*(volatile uint32_t*)(&_MBAR[0x9944]))
+#define MCF_FEC1_FECRFDR                     (*(volatile uint32_t*)(&_MBAR[0x9984]))
+#define MCF_FEC1_FECRFSR                     (*(volatile uint32_t*)(&_MBAR[0x9988]))
+#define MCF_FEC1_FECRFCR                     (*(volatile uint32_t*)(&_MBAR[0x998C]))
+#define MCF_FEC1_FECRLRFP                    (*(volatile uint32_t*)(&_MBAR[0x9990]))
+#define MCF_FEC1_FECRLWFP                    (*(volatile uint32_t*)(&_MBAR[0x9994]))
+#define MCF_FEC1_FECRFAR                     (*(volatile uint32_t*)(&_MBAR[0x9998]))
+#define MCF_FEC1_FECRFRP                     (*(volatile uint32_t*)(&_MBAR[0x999C]))
+#define MCF_FEC1_FECRFWP                     (*(volatile uint32_t*)(&_MBAR[0x99A0]))
+#define MCF_FEC1_FECTFDR                     (*(volatile uint32_t*)(&_MBAR[0x99A4]))
+#define MCF_FEC1_FECTFSR                     (*(volatile uint32_t*)(&_MBAR[0x99A8]))
+#define MCF_FEC1_FECTFCR                     (*(volatile uint32_t*)(&_MBAR[0x99AC]))
+#define MCF_FEC1_FECTLRFP                    (*(volatile uint32_t*)(&_MBAR[0x99B0]))
+#define MCF_FEC1_FECTLWFP                    (*(volatile uint32_t*)(&_MBAR[0x99B4]))
+#define MCF_FEC1_FECTFAR                     (*(volatile uint32_t*)(&_MBAR[0x99B8]))
+#define MCF_FEC1_FECTFRP                     (*(volatile uint32_t*)(&_MBAR[0x99BC]))
+#define MCF_FEC1_FECTFWP                     (*(volatile uint32_t*)(&_MBAR[0x99C0]))
+#define MCF_FEC1_FECFRST                     (*(volatile uint32_t*)(&_MBAR[0x99C4]))
+#define MCF_FEC1_FECCTCWR                    (*(volatile uint32_t*)(&_MBAR[0x99C8]))
+#define MCF_FEC1_RMON_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9A00]))
+#define MCF_FEC1_RMON_T_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9A04]))
+#define MCF_FEC1_RMON_T_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A08]))
+#define MCF_FEC1_RMON_T_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A0C]))
+#define MCF_FEC1_RMON_T_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9A10]))
+#define MCF_FEC1_RMON_T_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9A14]))
+#define MCF_FEC1_RMON_T_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9A18]))
+#define MCF_FEC1_RMON_T_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x9A1C]))
+#define MCF_FEC1_RMON_T_JAB                  (*(volatile uint32_t*)(&_MBAR[0x9A20]))
+#define MCF_FEC1_RMON_T_COL                  (*(volatile uint32_t*)(&_MBAR[0x9A24]))
+#define MCF_FEC1_RMON_T_P64                  (*(volatile uint32_t*)(&_MBAR[0x9A28]))
+#define MCF_FEC1_RMON_T_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x9A2C]))
+#define MCF_FEC1_RMON_T_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x9A30]))
+#define MCF_FEC1_RMON_T_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x9A34]))
+#define MCF_FEC1_RMON_T_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x9A38]))
+#define MCF_FEC1_RMON_T_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x9A3C]))
+#define MCF_FEC1_RMON_T_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x9A40]))
+#define MCF_FEC1_RMON_T_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x9A44]))
+#define MCF_FEC1_IEEE_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9A48]))
+#define MCF_FEC1_IEEE_T_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x9A4C]))
+#define MCF_FEC1_IEEE_T_1COL                 (*(volatile uint32_t*)(&_MBAR[0x9A50]))
+#define MCF_FEC1_IEEE_T_MCOL                 (*(volatile uint32_t*)(&_MBAR[0x9A54]))
+#define MCF_FEC1_IEEE_T_DEF                  (*(volatile uint32_t*)(&_MBAR[0x9A58]))
+#define MCF_FEC1_IEEE_T_LCOL                 (*(volatile uint32_t*)(&_MBAR[0x9A5C]))
+#define MCF_FEC1_IEEE_T_EXCOL                (*(volatile uint32_t*)(&_MBAR[0x9A60]))
+#define MCF_FEC1_IEEE_T_MACERR               (*(volatile uint32_t*)(&_MBAR[0x9A64]))
+#define MCF_FEC1_IEEE_T_CSERR                (*(volatile uint32_t*)(&_MBAR[0x9A68]))
+#define MCF_FEC1_IEEE_T_SQE                  (*(volatile uint32_t*)(&_MBAR[0x9A6C]))
+#define MCF_FEC1_IEEE_T_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x9A70]))
+#define MCF_FEC1_IEEE_T_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x9A74]))
+#define MCF_FEC1_RMON_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9A80]))
+#define MCF_FEC1_RMON_R_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9A84]))
+#define MCF_FEC1_RMON_R_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A88]))
+#define MCF_FEC1_RMON_R_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A8C]))
+#define MCF_FEC1_RMON_R_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9A90]))
+#define MCF_FEC1_RMON_R_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9A94]))
+#define MCF_FEC1_RMON_R_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9A98]))
+#define MCF_FEC1_RMON_R_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x9A9C]))
+#define MCF_FEC1_RMON_R_JAB                  (*(volatile uint32_t*)(&_MBAR[0x9AA0]))
+#define MCF_FEC1_RMON_R_RESVD_0              (*(volatile uint32_t*)(&_MBAR[0x9AA4]))
+#define MCF_FEC1_RMON_R_P64                  (*(volatile uint32_t*)(&_MBAR[0x9AA8]))
+#define MCF_FEC1_RMON_R_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x9AAC]))
+#define MCF_FEC1_RMON_R_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x9AB0]))
+#define MCF_FEC1_RMON_R_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x9AB4]))
+#define MCF_FEC1_RMON_R_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x9AB8]))
+#define MCF_FEC1_RMON_R_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x9ABC]))
+#define MCF_FEC1_RMON_R_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x9AC0]))
+#define MCF_FEC1_RMON_R_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x9AC4]))
+#define MCF_FEC1_IEEE_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9AC8]))
+#define MCF_FEC1_IEEE_R_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x9ACC]))
+#define MCF_FEC1_IEEE_R_CRC                  (*(volatile uint32_t*)(&_MBAR[0x9AD0]))
+#define MCF_FEC1_IEEE_R_ALIGN                (*(volatile uint32_t*)(&_MBAR[0x9AD4]))
+#define MCF_FEC1_IEEE_R_MACERR               (*(volatile uint32_t*)(&_MBAR[0x9AD8]))
+#define MCF_FEC1_IEEE_R_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x9ADC]))
+#define MCF_FEC1_IEEE_R_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x9AE0]))
+
+#define MCF_FEC_EIR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9004 + ((x)*0x800)]))
+#define MCF_FEC_EIMR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9008 + ((x)*0x800)]))
+#define MCF_FEC_ECR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9024 + ((x)*0x800)]))
+#define MCF_FEC_MMFR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9040 + ((x)*0x800)]))
+#define MCF_FEC_MSCR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9044 + ((x)*0x800)]))
+#define MCF_FEC_MIBC(x)                      (*(volatile uint32_t*)(&_MBAR[0x9064 + ((x)*0x800)]))
+#define MCF_FEC_RCR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9084 + ((x)*0x800)]))
+#define MCF_FEC_RHR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9088 + ((x)*0x800)]))
+#define MCF_FEC_TCR(x)                       (*(volatile uint32_t*)(&_MBAR[0x90C4 + ((x)*0x800)]))
+#define MCF_FEC_PALR(x)                      (*(volatile uint32_t*)(&_MBAR[0x90E4 + ((x)*0x800)]))
+#define MCF_FEC_PAHR(x)                      (*(volatile uint32_t*)(&_MBAR[0x90E8 + ((x)*0x800)]))
+#define MCF_FEC_OPD(x)                       (*(volatile uint32_t*)(&_MBAR[0x90EC + ((x)*0x800)]))
+#define MCF_FEC_IAUR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9118 + ((x)*0x800)]))
+#define MCF_FEC_IALR(x)                      (*(volatile uint32_t*)(&_MBAR[0x911C + ((x)*0x800)]))
+#define MCF_FEC_GAUR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9120 + ((x)*0x800)]))
+#define MCF_FEC_GALR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9124 + ((x)*0x800)]))
+#define MCF_FEC_FECTFWR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9144 + ((x)*0x800)]))
+#define MCF_FEC_FECRFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9184 + ((x)*0x800)]))
+#define MCF_FEC_FECRFSR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9188 + ((x)*0x800)]))
+#define MCF_FEC_FECRFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x918C + ((x)*0x800)]))
+#define MCF_FEC_FECRLRFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x9190 + ((x)*0x800)]))
+#define MCF_FEC_FECRLWFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x9194 + ((x)*0x800)]))
+#define MCF_FEC_FECRFAR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9198 + ((x)*0x800)]))
+#define MCF_FEC_FECRFRP(x)                   (*(volatile uint32_t*)(&_MBAR[0x919C + ((x)*0x800)]))
+#define MCF_FEC_FECRFWP(x)                   (*(volatile uint32_t*)(&_MBAR[0x91A0 + ((x)*0x800)]))
+#define MCF_FEC_FECTFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91A4 + ((x)*0x800)]))
+#define MCF_FEC_FECTFSR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91A8 + ((x)*0x800)]))
+#define MCF_FEC_FECTFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91AC + ((x)*0x800)]))
+#define MCF_FEC_FECTLRFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x91B0 + ((x)*0x800)]))
+#define MCF_FEC_FECTLWFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x91B4 + ((x)*0x800)]))
+#define MCF_FEC_FECTFAR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91B8 + ((x)*0x800)]))
+#define MCF_FEC_FECTFRP(x)                   (*(volatile uint32_t*)(&_MBAR[0x91BC + ((x)*0x800)]))
+#define MCF_FEC_FECTFWP(x)                   (*(volatile uint32_t*)(&_MBAR[0x91C0 + ((x)*0x800)]))
+#define MCF_FEC_FECFRST(x)                   (*(volatile uint32_t*)(&_MBAR[0x91C4 + ((x)*0x800)]))
+#define MCF_FEC_FECCTCWR(x)                  (*(volatile uint32_t*)(&_MBAR[0x91C8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x9200 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_PACKETS(x)            (*(volatile uint32_t*)(&_MBAR[0x9204 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_BC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x9208 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_MC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x920C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_CRC_ALIGN(x)          (*(volatile uint32_t*)(&_MBAR[0x9210 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_UNDERSIZE(x)          (*(volatile uint32_t*)(&_MBAR[0x9214 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_OVERSIZE(x)           (*(volatile uint32_t*)(&_MBAR[0x9218 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_FRAG(x)               (*(volatile uint32_t*)(&_MBAR[0x921C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_JAB(x)                (*(volatile uint32_t*)(&_MBAR[0x9220 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_COL(x)                (*(volatile uint32_t*)(&_MBAR[0x9224 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P64(x)                (*(volatile uint32_t*)(&_MBAR[0x9228 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P65TO127(x)           (*(volatile uint32_t*)(&_MBAR[0x922C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P128TO255(x)          (*(volatile uint32_t*)(&_MBAR[0x9230 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P256TO511(x)          (*(volatile uint32_t*)(&_MBAR[0x9234 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P512TO1023(x)         (*(volatile uint32_t*)(&_MBAR[0x9238 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P1024TO2047(x)        (*(volatile uint32_t*)(&_MBAR[0x923C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P_GTE2048(x)          (*(volatile uint32_t*)(&_MBAR[0x9240 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_OCTETS(x)             (*(volatile uint32_t*)(&_MBAR[0x9244 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x9248 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_FRAME_OK(x)           (*(volatile uint32_t*)(&_MBAR[0x924C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_1COL(x)               (*(volatile uint32_t*)(&_MBAR[0x9250 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_MCOL(x)               (*(volatile uint32_t*)(&_MBAR[0x9254 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_DEF(x)                (*(volatile uint32_t*)(&_MBAR[0x9258 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_LCOL(x)               (*(volatile uint32_t*)(&_MBAR[0x925C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_EXCOL(x)              (*(volatile uint32_t*)(&_MBAR[0x9260 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_MACERR(x)             (*(volatile uint32_t*)(&_MBAR[0x9264 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_CSERR(x)              (*(volatile uint32_t*)(&_MBAR[0x9268 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_SQE(x)                (*(volatile uint32_t*)(&_MBAR[0x926C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_FDXFC(x)              (*(volatile uint32_t*)(&_MBAR[0x9270 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_OCTETS_OK(x)          (*(volatile uint32_t*)(&_MBAR[0x9274 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x9280 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_PACKETS(x)            (*(volatile uint32_t*)(&_MBAR[0x9284 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_BC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x9288 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_MC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x928C + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_CRC_ALIGN(x)          (*(volatile uint32_t*)(&_MBAR[0x9290 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_UNDERSIZE(x)          (*(volatile uint32_t*)(&_MBAR[0x9294 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_OVERSIZE(x)           (*(volatile uint32_t*)(&_MBAR[0x9298 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_FRAG(x)               (*(volatile uint32_t*)(&_MBAR[0x929C + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_JAB(x)                (*(volatile uint32_t*)(&_MBAR[0x92A0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_RESVD_0(x)            (*(volatile uint32_t*)(&_MBAR[0x92A4 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P64(x)                (*(volatile uint32_t*)(&_MBAR[0x92A8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P65TO127(x)           (*(volatile uint32_t*)(&_MBAR[0x92AC + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P128TO255(x)          (*(volatile uint32_t*)(&_MBAR[0x92B0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P256TO511(x)          (*(volatile uint32_t*)(&_MBAR[0x92B4 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P512TO1023(x)         (*(volatile uint32_t*)(&_MBAR[0x92B8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P1024TO2047(x)        (*(volatile uint32_t*)(&_MBAR[0x92BC + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P_GTE2048(x)          (*(volatile uint32_t*)(&_MBAR[0x92C0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_OCTETS(x)             (*(volatile uint32_t*)(&_MBAR[0x92C4 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x92C8 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_FRAME_OK(x)           (*(volatile uint32_t*)(&_MBAR[0x92CC + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_CRC(x)                (*(volatile uint32_t*)(&_MBAR[0x92D0 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_ALIGN(x)              (*(volatile uint32_t*)(&_MBAR[0x92D4 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_MACERR(x)             (*(volatile uint32_t*)(&_MBAR[0x92D8 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_FDXFC(x)              (*(volatile uint32_t*)(&_MBAR[0x92DC + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_OCTETS_OK(x)          (*(volatile uint32_t*)(&_MBAR[0x92E0 + ((x)*0x800)]))
+
+
+/* Bit definitions and macros for MCF_FEC_EIR */
+#define MCF_FEC_EIR_RFERR                    (0x20000)
+#define MCF_FEC_EIR_XFERR                    (0x40000)
+#define MCF_FEC_EIR_XFUN                     (0x80000)
+#define MCF_FEC_EIR_RL                       (0x100000)
+#define MCF_FEC_EIR_LC                       (0x200000)
+#define MCF_FEC_EIR_MII                      (0x800000)
+#define MCF_FEC_EIR_TXF                      (0x8000000)
+#define MCF_FEC_EIR_GRA                      (0x10000000)
+#define MCF_FEC_EIR_BABT                     (0x20000000)
+#define MCF_FEC_EIR_BABR                     (0x40000000)
+#define MCF_FEC_EIR_HBERR                    (0x80000000)
+#define MCF_FEC_EIR_CLEAR_ALL                (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_EIMR */
+#define MCF_FEC_EIMR_RFERR                   (0x20000)
+#define MCF_FEC_EIMR_XFERR                   (0x40000)
+#define MCF_FEC_EIMR_XFUN                    (0x80000)
+#define MCF_FEC_EIMR_RL                      (0x100000)
+#define MCF_FEC_EIMR_LC                      (0x200000)
+#define MCF_FEC_EIMR_MII                     (0x800000)
+#define MCF_FEC_EIMR_TXF                     (0x8000000)
+#define MCF_FEC_EIMR_GRA                     (0x10000000)
+#define MCF_FEC_EIMR_BABT                    (0x20000000)
+#define MCF_FEC_EIMR_BABR                    (0x40000000)
+#define MCF_FEC_EIMR_HBERR                   (0x80000000)
+#define MCF_FEC_EIMR_MASK_ALL                (0)
+#define MCF_FEC_EIMR_UNMASK_ALL              (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_ECR */
+#define MCF_FEC_ECR_RESET                    (0x1)
+#define MCF_FEC_ECR_ETHER_EN                 (0x2)
+
+/* Bit definitions and macros for MCF_FEC_MMFR */
+#define MCF_FEC_MMFR_DATA(x)                 (((x)&0xFFFF)<<0)
+#define MCF_FEC_MMFR_TA(x)                   (((x)&0x3)<<0x10)
+#define MCF_FEC_MMFR_TA_10                   (0x20000)
+#define MCF_FEC_MMFR_RA(x)                   (((x)&0x1F)<<0x12)
+#define MCF_FEC_MMFR_PA(x)                   (((x)&0x1F)<<0x17)
+#define MCF_FEC_MMFR_OP(x)                   (((x)&0x3)<<0x1C)
+#define MCF_FEC_MMFR_OP_READ                 (0x20000000)
+#define MCF_FEC_MMFR_OP_WRITE                (0x10000000)
+#define MCF_FEC_MMFR_ST(x)                   (((x)&0x3)<<0x1E)
+#define MCF_FEC_MMFR_ST_01                   (0x40000000)
+
+/* Bit definitions and macros for MCF_FEC_MSCR */
+#define MCF_FEC_MSCR_MII_SPEED(x)            (((x)&0x3F)<<0x1)
+#define MCF_FEC_MSCR_DIS_PREAMBLE            (0x80)
+#define MCF_FEC_MSCR_MII_SPEED_133           (0x1B<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_120           (0x18<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_66            (0xE<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_60            (0xC<<0x1)
+
+/* Bit definitions and macros for MCF_FEC_MIBC */
+#define MCF_FEC_MIBC_MIB_IDLE                (0x40000000)
+#define MCF_FEC_MIBC_MIB_DISABLE             (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_RCR */
+#define MCF_FEC_RCR_LOOP                     (0x1)
+#define MCF_FEC_RCR_DRT                      (0x2)
+#define MCF_FEC_RCR_MII_MODE                 (0x4)
+#define MCF_FEC_RCR_PROM                     (0x8)
+#define MCF_FEC_RCR_BC_REJ                   (0x10)
+#define MCF_FEC_RCR_FCE                      (0x20)
+#define MCF_FEC_RCR_MAX_FL(x)                (((x)&0x7FF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_RHR */
+#define MCF_FEC_RHR_HASH(x)                  (((x)&0x3F)<<0x18)
+#define MCF_FEC_RHR_MULTCAST                 (0x40000000)
+#define MCF_FEC_RHR_FCE                      (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_TCR */
+#define MCF_FEC_TCR_GTS                      (0x1)
+#define MCF_FEC_TCR_HBC                      (0x2)
+#define MCF_FEC_TCR_FDEN                     (0x4)
+#define MCF_FEC_TCR_TFC_PAUSE                (0x8)
+#define MCF_FEC_TCR_RFC_PAUSE                (0x10)
+
+/* Bit definitions and macros for MCF_FEC_PALR */
+#define MCF_FEC_PALR_PADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_PAHR */
+#define MCF_FEC_PAHR_TYPE(x)                 (((x)&0xFFFF)<<0)
+#define MCF_FEC_PAHR_PADDR2(x)               (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_OPD */
+#define MCF_FEC_OPD_PAUSE_DUR(x)             (((x)&0xFFFF)<<0)
+#define MCF_FEC_OPD_OPCODE(x)                (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_IAUR */
+#define MCF_FEC_IAUR_IADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IALR */
+#define MCF_FEC_IALR_IADDR2(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_GAUR */
+#define MCF_FEC_GAUR_GADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_GALR */
+#define MCF_FEC_GALR_GADDR2(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFWR */
+#define MCF_FEC_FECTFWR_X_WMRK(x)            (((x)&0xF)<<0)
+#define MCF_FEC_FECTFWR_X_WMRK_64            (0)
+#define MCF_FEC_FECTFWR_X_WMRK_128           (0x1)
+#define MCF_FEC_FECTFWR_X_WMRK_192           (0x2)
+#define MCF_FEC_FECTFWR_X_WMRK_256           (0x3)
+#define MCF_FEC_FECTFWR_X_WMRK_320           (0x4)
+#define MCF_FEC_FECTFWR_X_WMRK_384           (0x5)
+#define MCF_FEC_FECTFWR_X_WMRK_448           (0x6)
+#define MCF_FEC_FECTFWR_X_WMRK_512           (0x7)
+#define MCF_FEC_FECTFWR_X_WMRK_576           (0x8)
+#define MCF_FEC_FECTFWR_X_WMRK_640           (0x9)
+#define MCF_FEC_FECTFWR_X_WMRK_704           (0xA)
+#define MCF_FEC_FECTFWR_X_WMRK_768           (0xB)
+#define MCF_FEC_FECTFWR_X_WMRK_832           (0xC)
+#define MCF_FEC_FECTFWR_X_WMRK_896           (0xD)
+#define MCF_FEC_FECTFWR_X_WMRK_960           (0xE)
+#define MCF_FEC_FECTFWR_X_WMRK_1024          (0xF)
+
+/* Bit definitions and macros for MCF_FEC_FECRFDR */
+#define MCF_FEC_FECRFDR_FIFO_DATA(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFSR */
+#define MCF_FEC_FECRFSR_EMT                  (0x10000)
+#define MCF_FEC_FECRFSR_ALARM                (0x20000)
+#define MCF_FEC_FECRFSR_FU                   (0x40000)
+#define MCF_FEC_FECRFSR_FRMRDY               (0x80000)
+#define MCF_FEC_FECRFSR_OF                   (0x100000)
+#define MCF_FEC_FECRFSR_UF                   (0x200000)
+#define MCF_FEC_FECRFSR_RXW                  (0x400000)
+#define MCF_FEC_FECRFSR_FAE                  (0x800000)
+#define MCF_FEC_FECRFSR_FRM(x)               (((x)&0xF)<<0x18)
+#define MCF_FEC_FECRFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_FECRFCR */
+#define MCF_FEC_FECRFCR_COUNTER(x)           (((x)&0xFFFF)<<0)
+#define MCF_FEC_FECRFCR_OF_MSK               (0x80000)
+#define MCF_FEC_FECRFCR_UF_MSK               (0x100000)
+#define MCF_FEC_FECRFCR_RXW_MSK              (0x200000)
+#define MCF_FEC_FECRFCR_FAE_MSK              (0x400000)
+#define MCF_FEC_FECRFCR_IP_MSK               (0x800000)
+#define MCF_FEC_FECRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_FEC_FECRFCR_FRMEN                (0x8000000)
+#define MCF_FEC_FECRFCR_TIMER                (0x10000000)
+
+/* Bit definitions and macros for MCF_FEC_FECRLRFP */
+#define MCF_FEC_FECRLRFP_LRFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRLWFP */
+#define MCF_FEC_FECRLWFP_LWFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFAR */
+#define MCF_FEC_FECRFAR_ALARM(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFRP */
+#define MCF_FEC_FECRFRP_READ(x)              (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFWP */
+#define MCF_FEC_FECRFWP_WRITE(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFDR */
+#define MCF_FEC_FECTFDR_FIFO_DATA(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFSR */
+#define MCF_FEC_FECTFSR_EMT                  (0x10000)
+#define MCF_FEC_FECTFSR_ALARM                (0x20000)
+#define MCF_FEC_FECTFSR_FU                   (0x40000)
+#define MCF_FEC_FECTFSR_FRMRDY               (0x80000)
+#define MCF_FEC_FECTFSR_OF                   (0x100000)
+#define MCF_FEC_FECTFSR_UF                   (0x200000)
+#define MCF_FEC_FECTFSR_FAE                  (0x800000)
+#define MCF_FEC_FECTFSR_FRM(x)               (((x)&0xF)<<0x18)
+#define MCF_FEC_FECTFSR_TXW                  (0x40000000)
+#define MCF_FEC_FECTFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_FECTFCR */
+#define MCF_FEC_FECTFCR_RESERVED             (0x200000)
+#define MCF_FEC_FECTFCR_COUNTER(x)           (((x)&0xFFFF)<<0|0x200000)
+#define MCF_FEC_FECTFCR_TXW_MASK             (0x240000)
+#define MCF_FEC_FECTFCR_OF_MSK               (0x280000)
+#define MCF_FEC_FECTFCR_UF_MSK               (0x300000)
+#define MCF_FEC_FECTFCR_FAE_MSK              (0x600000)
+#define MCF_FEC_FECTFCR_IP_MSK               (0xA00000)
+#define MCF_FEC_FECTFCR_GR(x)                (((x)&0x7)<<0x18|0x200000)
+#define MCF_FEC_FECTFCR_FRMEN                (0x8200000)
+#define MCF_FEC_FECTFCR_TIMER                (0x10200000)
+#define MCF_FEC_FECTFCR_WFR                  (0x20200000)
+#define MCF_FEC_FECTFCR_WCTL                 (0x40200000)
+
+/* Bit definitions and macros for MCF_FEC_FECTLRFP */
+#define MCF_FEC_FECTLRFP_LRFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTLWFP */
+#define MCF_FEC_FECTLWFP_LWFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFAR */
+#define MCF_FEC_FECTFAR_ALARM(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFRP */
+#define MCF_FEC_FECTFRP_READ(x)              (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFWP */
+#define MCF_FEC_FECTFWP_WRITE(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECFRST */
+#define MCF_FEC_FECFRST_RST_CTL              (0x1000000)
+#define MCF_FEC_FECFRST_SW_RST               (0x2000000)
+
+/* Bit definitions and macros for MCF_FEC_FECCTCWR */
+#define MCF_FEC_FECCTCWR_TFCW                (0x1000000)
+#define MCF_FEC_FECCTCWR_CRC                 (0x2000000)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */
+#define MCF_FEC_RMON_T_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */
+#define MCF_FEC_RMON_T_PACKETS_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */
+#define MCF_FEC_RMON_T_BC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */
+#define MCF_FEC_RMON_T_MC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */
+#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */
+#define MCF_FEC_RMON_T_UNDERSIZE_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */
+#define MCF_FEC_RMON_T_OVERSIZE_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */
+#define MCF_FEC_RMON_T_FRAG_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */
+#define MCF_FEC_RMON_T_JAB_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_COL */
+#define MCF_FEC_RMON_T_COL_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */
+#define MCF_FEC_RMON_T_P64_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */
+#define MCF_FEC_RMON_T_P65TO127_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */
+#define MCF_FEC_RMON_T_P128TO255_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */
+#define MCF_FEC_RMON_T_P256TO511_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */
+#define MCF_FEC_RMON_T_P512TO1023_Value(x)   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */
+#define MCF_FEC_RMON_T_P1024TO2047_Value(x)  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */
+#define MCF_FEC_RMON_T_P_GTE2048_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */
+#define MCF_FEC_RMON_T_OCTETS_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */
+#define MCF_FEC_IEEE_T_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */
+#define MCF_FEC_IEEE_T_FRAME_OK_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */
+#define MCF_FEC_IEEE_T_1COL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */
+#define MCF_FEC_IEEE_T_MCOL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */
+#define MCF_FEC_IEEE_T_DEF_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */
+#define MCF_FEC_IEEE_T_LCOL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */
+#define MCF_FEC_IEEE_T_EXCOL_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */
+#define MCF_FEC_IEEE_T_MACERR_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */
+#define MCF_FEC_IEEE_T_CSERR_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */
+#define MCF_FEC_IEEE_T_SQE_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */
+#define MCF_FEC_IEEE_T_FDXFC_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */
+#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */
+#define MCF_FEC_RMON_R_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */
+#define MCF_FEC_RMON_R_PACKETS_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */
+#define MCF_FEC_RMON_R_BC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */
+#define MCF_FEC_RMON_R_MC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */
+#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */
+#define MCF_FEC_RMON_R_UNDERSIZE_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */
+#define MCF_FEC_RMON_R_OVERSIZE_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */
+#define MCF_FEC_RMON_R_FRAG_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */
+#define MCF_FEC_RMON_R_JAB_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */
+#define MCF_FEC_RMON_R_RESVD_0_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */
+#define MCF_FEC_RMON_R_P64_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */
+#define MCF_FEC_RMON_R_P65TO127_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */
+#define MCF_FEC_RMON_R_P128TO255_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */
+#define MCF_FEC_RMON_R_P256TO511_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */
+#define MCF_FEC_RMON_R_P512TO1023_Value(x)   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */
+#define MCF_FEC_RMON_R_P1024TO2047_Value(x)  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */
+#define MCF_FEC_RMON_R_P_GTE2048_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */
+#define MCF_FEC_RMON_R_OCTETS_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */
+#define MCF_FEC_IEEE_R_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */
+#define MCF_FEC_IEEE_R_FRAME_OK_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */
+#define MCF_FEC_IEEE_R_CRC_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */
+#define MCF_FEC_IEEE_R_ALIGN_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */
+#define MCF_FEC_IEEE_R_MACERR_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */
+#define MCF_FEC_IEEE_R_FDXFC_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */
+#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+
+#endif /* __MCF5475_FEC_H__ */

tos/jtagwait/include/MCF5475_GPIO.h

@@ -0,0 +1,543 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_GPIO_H__
+#define __MCF5475_GPIO_H__
+
+
+/*********************************************************************
+*
+* General Purpose I/O (GPIO)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPIO_PODR_FBCTL                  (*(volatile uint8_t *)(&_MBAR[0xA00]))
+#define MCF_GPIO_PDDR_FBCTL                  (*(volatile uint8_t *)(&_MBAR[0xA10]))
+#define MCF_GPIO_PPDSDR_FBCTL                (*(volatile uint8_t *)(&_MBAR[0xA20]))
+#define MCF_GPIO_PCLRR_FBCTL                 (*(volatile uint8_t *)(&_MBAR[0xA30]))
+
+#define MCF_GPIO_PODR_FBCS                   (*(volatile uint8_t *)(&_MBAR[0xA01]))
+#define MCF_GPIO_PDDR_FBCS                   (*(volatile uint8_t *)(&_MBAR[0xA11]))
+#define MCF_GPIO_PPDSDR_FBCS                 (*(volatile uint8_t *)(&_MBAR[0xA21]))
+#define MCF_GPIO_PCLRR_FBCS                  (*(volatile uint8_t *)(&_MBAR[0xA31]))
+
+#define MCF_GPIO_PODR_DMA                    (*(volatile uint8_t *)(&_MBAR[0xA02]))
+#define MCF_GPIO_PDDR_DMA                    (*(volatile uint8_t *)(&_MBAR[0xA12]))
+#define MCF_GPIO_PPDSDR_DMA                  (*(volatile uint8_t *)(&_MBAR[0xA22]))
+#define MCF_GPIO_PCLRR_DMA                   (*(volatile uint8_t *)(&_MBAR[0xA32]))
+
+#define MCF_GPIO_PODR_FEC0H                  (*(volatile uint8_t *)(&_MBAR[0xA04]))
+#define MCF_GPIO_PDDR_FEC0H                  (*(volatile uint8_t *)(&_MBAR[0xA14]))
+#define MCF_GPIO_PPDSDR_FEC0H                (*(volatile uint8_t *)(&_MBAR[0xA24]))
+#define MCF_GPIO_PCLRR_FEC0H                 (*(volatile uint8_t *)(&_MBAR[0xA34]))
+
+#define MCF_GPIO_PODR_FEC0L                  (*(volatile uint8_t *)(&_MBAR[0xA05]))
+#define MCF_GPIO_PDDR_FEC0L                  (*(volatile uint8_t *)(&_MBAR[0xA15]))
+#define MCF_GPIO_PPDSDR_FEC0L                (*(volatile uint8_t *)(&_MBAR[0xA25]))
+#define MCF_GPIO_PCLRR_FEC0L                 (*(volatile uint8_t *)(&_MBAR[0xA35]))
+
+#define MCF_GPIO_PODR_FEC1H                  (*(volatile uint8_t *)(&_MBAR[0xA06]))
+#define MCF_GPIO_PDDR_FEC1H                  (*(volatile uint8_t *)(&_MBAR[0xA16]))
+#define MCF_GPIO_PPDSDR_FEC1H                (*(volatile uint8_t *)(&_MBAR[0xA26]))
+#define MCF_GPIO_PCLRR_FEC1H                 (*(volatile uint8_t *)(&_MBAR[0xA36]))
+
+#define MCF_GPIO_PODR_FEC1L                  (*(volatile uint8_t *)(&_MBAR[0xA07]))
+#define MCF_GPIO_PDDR_FEC1L                  (*(volatile uint8_t *)(&_MBAR[0xA17]))
+#define MCF_GPIO_PPDSDR_FEC1L                (*(volatile uint8_t *)(&_MBAR[0xA27]))
+#define MCF_GPIO_PCLRR_FEC1L                 (*(volatile uint8_t *)(&_MBAR[0xA37]))
+
+#define MCF_GPIO_PODR_FECI2C                 (*(volatile uint8_t *)(&_MBAR[0xA08]))
+#define MCF_GPIO_PDDR_FECI2C                 (*(volatile uint8_t *)(&_MBAR[0xA18]))
+#define MCF_GPIO_PPDSDR_FECI2C               (*(volatile uint8_t *)(&_MBAR[0xA28]))
+#define MCF_GPIO_PCLRR_FECI2C                (*(volatile uint8_t *)(&_MBAR[0xA38]))
+
+#define MCF_GPIO_PODR_PCIBG                  (*(volatile uint8_t *)(&_MBAR[0xA09]))
+#define MCF_GPIO_PDDR_PCIBG                  (*(volatile uint8_t *)(&_MBAR[0xA19]))
+#define MCF_GPIO_PPDSDR_PCIBG                (*(volatile uint8_t *)(&_MBAR[0xA29]))
+#define MCF_GPIO_PCLRR_PCIBG                 (*(volatile uint8_t *)(&_MBAR[0xA39]))
+
+#define MCF_GPIO_PODR_PCIBR                  (*(volatile uint8_t *)(&_MBAR[0xA0A]))
+#define MCF_GPIO_PDDR_PCIBR                  (*(volatile uint8_t *)(&_MBAR[0xA1A]))
+#define MCF_GPIO_PPDSDR_PCIBR                (*(volatile uint8_t *)(&_MBAR[0xA2A]))
+#define MCF_GPIO_PCLRR_PCIBR                 (*(volatile uint8_t *)(&_MBAR[0xA3A]))
+
+#define MCF_GPIO2_PODR_PSC3PSC               (*(volatile uint8_t *)(&_MBAR[0xA0C]))
+#define MCF_GPIO2_PDDR_PSC3PSC               (*(volatile uint8_t *)(&_MBAR[0xA1C]))
+#define MCF_GPIO2_PPDSDR_PSC3PSC             (*(volatile uint8_t *)(&_MBAR[0xA2C]))
+#define MCF_GPIO2_PCLRR_PSC3PSC              (*(volatile uint8_t *)(&_MBAR[0xA3C]))
+
+#define MCF_GPIO0_PODR_PSC1PSC               (*(volatile uint8_t *)(&_MBAR[0xA0D]))
+#define MCF_GPIO0_PDDR_PSC1PSC               (*(volatile uint8_t *)(&_MBAR[0xA1D]))
+#define MCF_GPIO0_PPDSDR_PSC1PSC             (*(volatile uint8_t *)(&_MBAR[0xA2D]))
+#define MCF_GPIO0_PCLRR_PSC1PSC              (*(volatile uint8_t *)(&_MBAR[0xA3D]))
+
+#define MCF_GPIO_PODR_DSPI                   (*(volatile uint8_t *)(&_MBAR[0xA0E]))
+#define MCF_GPIO_PDDR_DSPI                   (*(volatile uint8_t *)(&_MBAR[0xA1E]))
+#define MCF_GPIO_PPDSDR_DSPI                 (*(volatile uint8_t *)(&_MBAR[0xA2E]))
+#define MCF_GPIO_PCLRR_DSPI                  (*(volatile uint8_t *)(&_MBAR[0xA3E]))
+
+
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0      (0x1)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1      (0x2)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2      (0x4)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3      (0x8)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4      (0x10)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5      (0x20)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6      (0x40)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0      (0x1)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1      (0x2)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2      (0x4)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3      (0x8)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4      (0x10)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5      (0x20)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6      (0x40)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0  (0x1)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1  (0x2)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2  (0x4)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3  (0x8)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4  (0x10)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5  (0x20)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6  (0x40)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0    (0x1)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1    (0x2)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2    (0x4)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3    (0x8)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4    (0x10)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5    (0x20)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6    (0x40)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS1        (0x2)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS2        (0x4)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS3        (0x8)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS4        (0x10)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS5        (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1        (0x2)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2        (0x4)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3        (0x8)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4        (0x10)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5        (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1    (0x2)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2    (0x4)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3    (0x8)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4    (0x10)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5    (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1      (0x2)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2      (0x4)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3      (0x8)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4      (0x10)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5      (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
+#define MCF_GPIO_PODR_DMA_PODR_DMA0          (0x1)
+#define MCF_GPIO_PODR_DMA_PODR_DMA1          (0x2)
+#define MCF_GPIO_PODR_DMA_PODR_DMA2          (0x4)
+#define MCF_GPIO_PODR_DMA_PODR_DMA3          (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA0          (0x1)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA1          (0x2)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA2          (0x4)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA3          (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0      (0x1)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1      (0x2)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2      (0x4)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3      (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0        (0x1)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1        (0x2)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2        (0x4)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3        (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0      (0x1)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1      (0x2)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2      (0x4)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3      (0x8)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4      (0x10)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5      (0x20)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6      (0x40)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0      (0x1)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1      (0x2)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2      (0x4)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3      (0x8)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4      (0x10)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5      (0x20)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6      (0x40)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0    (0x1)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1    (0x2)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2    (0x4)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3    (0x8)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4    (0x10)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5    (0x20)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6    (0x40)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0      (0x1)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1      (0x2)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2      (0x4)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3      (0x8)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4      (0x10)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5      (0x20)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6      (0x40)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0      (0x1)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1      (0x2)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2      (0x4)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3      (0x8)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4      (0x10)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5      (0x20)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6      (0x40)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0    (0x1)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1    (0x2)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2    (0x4)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3    (0x8)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4    (0x10)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5    (0x20)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6    (0x40)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0      (0x1)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1      (0x2)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2      (0x4)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3      (0x8)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4      (0x10)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5      (0x20)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6      (0x40)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0      (0x1)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1      (0x2)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2      (0x4)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3      (0x8)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4      (0x10)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5      (0x20)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6      (0x40)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0    (0x1)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1    (0x2)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2    (0x4)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3    (0x8)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4    (0x10)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5    (0x20)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6    (0x40)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0      (0x1)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1      (0x2)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2      (0x4)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3      (0x8)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4      (0x10)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5      (0x20)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6      (0x40)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0      (0x1)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1      (0x2)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2      (0x4)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3      (0x8)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4      (0x10)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5      (0x20)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6      (0x40)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0    (0x1)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1    (0x2)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2    (0x4)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3    (0x8)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4    (0x10)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5    (0x20)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6    (0x40)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0    (0x1)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1    (0x2)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2    (0x4)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3    (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0    (0x1)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1    (0x2)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2    (0x4)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3    (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0  (0x1)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1  (0x2)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2  (0x4)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3  (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0      (0x1)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1      (0x2)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2      (0x4)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3      (0x8)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0      (0x1)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1      (0x2)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2      (0x4)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3      (0x8)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0  (0x1)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1  (0x2)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2  (0x4)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3  (0x8)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4  (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0    (0x1)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1    (0x2)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2    (0x4)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3    (0x8)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4    (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0      (0x1)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1      (0x2)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2      (0x4)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3      (0x8)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0      (0x1)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1      (0x2)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2      (0x4)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3      (0x8)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0  (0x1)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1  (0x2)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2  (0x4)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3  (0x8)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4  (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0    (0x1)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1    (0x2)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2    (0x4)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3    (0x8)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4    (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI0        (0x1)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI1        (0x2)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI2        (0x4)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI3        (0x8)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI4        (0x10)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI5        (0x20)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI6        (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0        (0x1)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1        (0x2)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2        (0x4)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3        (0x8)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4        (0x10)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5        (0x20)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6        (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0    (0x1)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1    (0x2)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2    (0x4)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3    (0x8)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4    (0x10)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5    (0x20)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6    (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0      (0x1)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1      (0x2)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2      (0x4)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3      (0x8)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4      (0x10)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5      (0x20)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6      (0x40)
+
+
+#endif /* __MCF5475_GPIO_H__ */

tos/jtagwait/include/MCF5475_GPT.h

@@ -0,0 +1,100 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_GPT_H__
+#define __MCF5475_GPT_H__
+
+
+/*********************************************************************
+*
+* General Purpose Timers (GPT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPT0_GMS                         (*(volatile uint32_t*)(&_MBAR[0x800]))
+#define MCF_GPT0_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x804]))
+#define MCF_GPT0_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x808]))
+#define MCF_GPT0_GSR                         (*(volatile uint32_t*)(&_MBAR[0x80C]))
+
+#define MCF_GPT1_GMS                         (*(volatile uint32_t*)(&_MBAR[0x810]))
+#define MCF_GPT1_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x814]))
+#define MCF_GPT1_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x818]))
+#define MCF_GPT1_GSR                         (*(volatile uint32_t*)(&_MBAR[0x81C]))
+
+#define MCF_GPT2_GMS                         (*(volatile uint32_t*)(&_MBAR[0x820]))
+#define MCF_GPT2_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x824]))
+#define MCF_GPT2_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x828]))
+#define MCF_GPT2_GSR                         (*(volatile uint32_t*)(&_MBAR[0x82C]))
+
+#define MCF_GPT3_GMS                         (*(volatile uint32_t*)(&_MBAR[0x830]))
+#define MCF_GPT3_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x834]))
+#define MCF_GPT3_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x838]))
+#define MCF_GPT3_GSR                         (*(volatile uint32_t*)(&_MBAR[0x83C]))
+
+#define MCF_GPT_GMS(x)                       (*(volatile uint32_t*)(&_MBAR[0x800 + ((x)*0x10)]))
+#define MCF_GPT_GCIR(x)                      (*(volatile uint32_t*)(&_MBAR[0x804 + ((x)*0x10)]))
+#define MCF_GPT_GPWM(x)                      (*(volatile uint32_t*)(&_MBAR[0x808 + ((x)*0x10)]))
+#define MCF_GPT_GSR(x)                       (*(volatile uint32_t*)(&_MBAR[0x80C + ((x)*0x10)]))
+
+
+/* Bit definitions and macros for MCF_GPT_GMS */
+#define MCF_GPT_GMS_TMS(x)                   (((x)&0x7)<<0)
+#define MCF_GPT_GMS_TMS_DISABLE              (0)
+#define MCF_GPT_GMS_TMS_INCAPT               (0x1)
+#define MCF_GPT_GMS_TMS_OUTCAPT              (0x2)
+#define MCF_GPT_GMS_TMS_PWM                  (0x3)
+#define MCF_GPT_GMS_TMS_GPIO                 (0x4)
+#define MCF_GPT_GMS_GPIO(x)                  (((x)&0x3)<<0x4)
+#define MCF_GPT_GMS_GPIO_INPUT               (0)
+#define MCF_GPT_GMS_GPIO_OUTLO               (0x20)
+#define MCF_GPT_GMS_GPIO_OUTHI               (0x30)
+#define MCF_GPT_GMS_IEN                      (0x100)
+#define MCF_GPT_GMS_OD                       (0x200)
+#define MCF_GPT_GMS_SC                       (0x400)
+#define MCF_GPT_GMS_CE                       (0x1000)
+#define MCF_GPT_GMS_WDEN                     (0x8000)
+#define MCF_GPT_GMS_ICT(x)                   (((x)&0x3)<<0x10)
+#define MCF_GPT_GMS_ICT_ANY                  (0)
+#define MCF_GPT_GMS_ICT_RISE                 (0x10000)
+#define MCF_GPT_GMS_ICT_FALL                 (0x20000)
+#define MCF_GPT_GMS_ICT_PULSE                (0x30000)
+#define MCF_GPT_GMS_OCT(x)                   (((x)&0x3)<<0x14)
+#define MCF_GPT_GMS_OCT_FRCLOW               (0)
+#define MCF_GPT_GMS_OCT_PULSEHI              (0x100000)
+#define MCF_GPT_GMS_OCT_PULSELO              (0x200000)
+#define MCF_GPT_GMS_OCT_TOGGLE               (0x300000)
+#define MCF_GPT_GMS_OCPW(x)                  (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_GPT_GCIR */
+#define MCF_GPT_GCIR_CNT(x)                  (((x)&0xFFFF)<<0)
+#define MCF_GPT_GCIR_PRE(x)                  (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_GPT_GPWM */
+#define MCF_GPT_GPWM_LOAD                    (0x1)
+#define MCF_GPT_GPWM_PWMOP                   (0x100)
+#define MCF_GPT_GPWM_WIDTH(x)                (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_GPT_GSR */
+#define MCF_GPT_GSR_CAPT                     (0x1)
+#define MCF_GPT_GSR_COMP                     (0x2)
+#define MCF_GPT_GSR_PWMP                     (0x4)
+#define MCF_GPT_GSR_TEXP                     (0x8)
+#define MCF_GPT_GSR_PIN                      (0x100)
+#define MCF_GPT_GSR_OVF(x)                   (((x)&0x7)<<0xC)
+#define MCF_GPT_GSR_CAPTURE(x)               (((x)&0xFFFF)<<0x10)
+
+
+#endif /* __MCF5475_GPT_H__ */

tos/jtagwait/include/MCF5475_I2C.h

@@ -0,0 +1,69 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_I2C_H__
+#define __MCF5475_I2C_H__
+
+
+/*********************************************************************
+*
+* I2C Module (I2C)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_I2C_I2ADR                        (*(volatile uint8_t *)(&_MBAR[0x8F00]))
+#define MCF_I2C_I2FDR                        (*(volatile uint8_t *)(&_MBAR[0x8F04]))
+#define MCF_I2C_I2CR                         (*(volatile uint8_t *)(&_MBAR[0x8F08]))
+#define MCF_I2C_I2SR                         (*(volatile uint8_t *)(&_MBAR[0x8F0C]))
+#define MCF_I2C_I2DR                         (*(volatile uint8_t *)(&_MBAR[0x8F10]))
+#define MCF_I2C_I2ICR                        (*(volatile uint8_t *)(&_MBAR[0x8F20]))
+
+
+
+/* Bit definitions and macros for MCF_I2C_I2ADR */
+#define MCF_I2C_I2ADR_ADR(x)                 (((x)&0x7F)<<0x1)
+
+/* Bit definitions and macros for MCF_I2C_I2FDR */
+#define MCF_I2C_I2FDR_IC(x)                  (((x)&0x3F)<<0)
+
+/* Bit definitions and macros for MCF_I2C_I2CR */
+#define MCF_I2C_I2CR_RSTA                    (0x4)
+#define MCF_I2C_I2CR_TXAK                    (0x8)
+#define MCF_I2C_I2CR_MTX                     (0x10)
+#define MCF_I2C_I2CR_MSTA                    (0x20)
+#define MCF_I2C_I2CR_IIEN                    (0x40)
+#define MCF_I2C_I2CR_IEN                     (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2SR */
+#define MCF_I2C_I2SR_RXAK                    (0x1)
+#define MCF_I2C_I2SR_IIF                     (0x2)
+#define MCF_I2C_I2SR_SRW                     (0x4)
+#define MCF_I2C_I2SR_IAL                     (0x10)
+#define MCF_I2C_I2SR_IBB                     (0x20)
+#define MCF_I2C_I2SR_IAAS                    (0x40)
+#define MCF_I2C_I2SR_ICF                     (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2DR */
+#define MCF_I2C_I2DR_DATA(x)                 (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_I2C_I2ICR */
+#define MCF_I2C_I2ICR_IE                     (0x1)
+#define MCF_I2C_I2ICR_RE                     (0x2)
+#define MCF_I2C_I2ICR_TE                     (0x4)
+#define MCF_I2C_I2ICR_BNBE                   (0x8)
+
+
+#endif /* __MCF5475_I2C_H__ */

tos/jtagwait/include/MCF5475_INTC.h

@@ -0,0 +1,331 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_INTC_H__
+#define __MCF5475_INTC_H__
+
+
+/*********************************************************************
+*
+* Interrupt Controller (INTC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_INTC_IPRH                        (*(volatile uint32_t*)(&_MBAR[0x700]))
+#define MCF_INTC_IPRL                        (*(volatile uint32_t*)(&_MBAR[0x704]))
+#define MCF_INTC_IMRH                        (*(volatile uint32_t*)(&_MBAR[0x708]))
+#define MCF_INTC_IMRL                        (*(volatile uint32_t*)(&_MBAR[0x70C]))
+#define MCF_INTC_INTFRCH                     (*(volatile uint32_t*)(&_MBAR[0x710]))
+#define MCF_INTC_INTFRCL                     (*(volatile uint32_t*)(&_MBAR[0x714]))
+#define MCF_INTC_IRLR                        (*(volatile uint8_t *)(&_MBAR[0x718]))
+#define MCF_INTC_IACKLPR                     (*(volatile uint8_t *)(&_MBAR[0x719]))
+#define MCF_INTC_ICR01                       (*(volatile uint8_t *)(&_MBAR[0x741]))
+#define MCF_INTC_ICR02                       (*(volatile uint8_t *)(&_MBAR[0x742]))
+#define MCF_INTC_ICR03                       (*(volatile uint8_t *)(&_MBAR[0x743]))
+#define MCF_INTC_ICR04                       (*(volatile uint8_t *)(&_MBAR[0x744]))
+#define MCF_INTC_ICR05                       (*(volatile uint8_t *)(&_MBAR[0x745]))
+#define MCF_INTC_ICR06                       (*(volatile uint8_t *)(&_MBAR[0x746]))
+#define MCF_INTC_ICR07                       (*(volatile uint8_t *)(&_MBAR[0x747]))
+#define MCF_INTC_ICR08                       (*(volatile uint8_t *)(&_MBAR[0x748]))
+#define MCF_INTC_ICR09                       (*(volatile uint8_t *)(&_MBAR[0x749]))
+#define MCF_INTC_ICR10                       (*(volatile uint8_t *)(&_MBAR[0x74A]))
+#define MCF_INTC_ICR11                       (*(volatile uint8_t *)(&_MBAR[0x74B]))
+#define MCF_INTC_ICR12                       (*(volatile uint8_t *)(&_MBAR[0x74C]))
+#define MCF_INTC_ICR13                       (*(volatile uint8_t *)(&_MBAR[0x74D]))
+#define MCF_INTC_ICR14                       (*(volatile uint8_t *)(&_MBAR[0x74E]))
+#define MCF_INTC_ICR15                       (*(volatile uint8_t *)(&_MBAR[0x74F]))
+#define MCF_INTC_ICR16                       (*(volatile uint8_t *)(&_MBAR[0x750]))
+#define MCF_INTC_ICR17                       (*(volatile uint8_t *)(&_MBAR[0x751]))
+#define MCF_INTC_ICR18                       (*(volatile uint8_t *)(&_MBAR[0x752]))
+#define MCF_INTC_ICR19                       (*(volatile uint8_t *)(&_MBAR[0x753]))
+#define MCF_INTC_ICR20                       (*(volatile uint8_t *)(&_MBAR[0x754]))
+#define MCF_INTC_ICR21                       (*(volatile uint8_t *)(&_MBAR[0x755]))
+#define MCF_INTC_ICR22                       (*(volatile uint8_t *)(&_MBAR[0x756]))
+#define MCF_INTC_ICR23                       (*(volatile uint8_t *)(&_MBAR[0x757]))
+#define MCF_INTC_ICR24                       (*(volatile uint8_t *)(&_MBAR[0x758]))
+#define MCF_INTC_ICR25                       (*(volatile uint8_t *)(&_MBAR[0x759]))
+#define MCF_INTC_ICR26                       (*(volatile uint8_t *)(&_MBAR[0x75A]))
+#define MCF_INTC_ICR27                       (*(volatile uint8_t *)(&_MBAR[0x75B]))
+#define MCF_INTC_ICR28                       (*(volatile uint8_t *)(&_MBAR[0x75C]))
+#define MCF_INTC_ICR29                       (*(volatile uint8_t *)(&_MBAR[0x75D]))
+#define MCF_INTC_ICR30                       (*(volatile uint8_t *)(&_MBAR[0x75E]))
+#define MCF_INTC_ICR31                       (*(volatile uint8_t *)(&_MBAR[0x75F]))
+#define MCF_INTC_ICR32                       (*(volatile uint8_t *)(&_MBAR[0x760]))
+#define MCF_INTC_ICR33                       (*(volatile uint8_t *)(&_MBAR[0x761]))
+#define MCF_INTC_ICR34                       (*(volatile uint8_t *)(&_MBAR[0x762]))
+#define MCF_INTC_ICR35                       (*(volatile uint8_t *)(&_MBAR[0x763]))
+#define MCF_INTC_ICR36                       (*(volatile uint8_t *)(&_MBAR[0x764]))
+#define MCF_INTC_ICR37                       (*(volatile uint8_t *)(&_MBAR[0x765]))
+#define MCF_INTC_ICR38                       (*(volatile uint8_t *)(&_MBAR[0x766]))
+#define MCF_INTC_ICR39                       (*(volatile uint8_t *)(&_MBAR[0x767]))
+#define MCF_INTC_ICR40                       (*(volatile uint8_t *)(&_MBAR[0x768]))
+#define MCF_INTC_ICR41                       (*(volatile uint8_t *)(&_MBAR[0x769]))
+#define MCF_INTC_ICR42                       (*(volatile uint8_t *)(&_MBAR[0x76A]))
+#define MCF_INTC_ICR43                       (*(volatile uint8_t *)(&_MBAR[0x76B]))
+#define MCF_INTC_ICR44                       (*(volatile uint8_t *)(&_MBAR[0x76C]))
+#define MCF_INTC_ICR45                       (*(volatile uint8_t *)(&_MBAR[0x76D]))
+#define MCF_INTC_ICR46                       (*(volatile uint8_t *)(&_MBAR[0x76E]))
+#define MCF_INTC_ICR47                       (*(volatile uint8_t *)(&_MBAR[0x76F]))
+#define MCF_INTC_ICR48                       (*(volatile uint8_t *)(&_MBAR[0x770]))
+#define MCF_INTC_ICR49                       (*(volatile uint8_t *)(&_MBAR[0x771]))
+#define MCF_INTC_ICR50                       (*(volatile uint8_t *)(&_MBAR[0x772]))
+#define MCF_INTC_ICR51                       (*(volatile uint8_t *)(&_MBAR[0x773]))
+#define MCF_INTC_ICR52                       (*(volatile uint8_t *)(&_MBAR[0x774]))
+#define MCF_INTC_ICR53                       (*(volatile uint8_t *)(&_MBAR[0x775]))
+#define MCF_INTC_ICR54                       (*(volatile uint8_t *)(&_MBAR[0x776]))
+#define MCF_INTC_ICR55                       (*(volatile uint8_t *)(&_MBAR[0x777]))
+#define MCF_INTC_ICR56                       (*(volatile uint8_t *)(&_MBAR[0x778]))
+#define MCF_INTC_ICR57                       (*(volatile uint8_t *)(&_MBAR[0x779]))
+#define MCF_INTC_ICR58                       (*(volatile uint8_t *)(&_MBAR[0x77A]))
+#define MCF_INTC_ICR59                       (*(volatile uint8_t *)(&_MBAR[0x77B]))
+#define MCF_INTC_ICR60                       (*(volatile uint8_t *)(&_MBAR[0x77C]))
+#define MCF_INTC_ICR61                       (*(volatile uint8_t *)(&_MBAR[0x77D]))
+#define MCF_INTC_ICR62                       (*(volatile uint8_t *)(&_MBAR[0x77E]))
+#define MCF_INTC_ICR63                       (*(volatile uint8_t *)(&_MBAR[0x77F]))
+#define MCF_INTC_SWIACK                      (*(volatile uint8_t *)(&_MBAR[0x7E0]))
+#define MCF_INTC_L1IACK                      (*(volatile uint8_t *)(&_MBAR[0x7E4]))
+#define MCF_INTC_L2IACK                      (*(volatile uint8_t *)(&_MBAR[0x7E8]))
+#define MCF_INTC_L3IACK                      (*(volatile uint8_t *)(&_MBAR[0x7EC]))
+#define MCF_INTC_L4IACK                      (*(volatile uint8_t *)(&_MBAR[0x7F0]))
+#define MCF_INTC_L5IACK                      (*(volatile uint8_t *)(&_MBAR[0x7F4]))
+#define MCF_INTC_L6IACK                      (*(volatile uint8_t *)(&_MBAR[0x7F8]))
+#define MCF_INTC_L7IACK                      (*(volatile uint8_t *)(&_MBAR[0x7FC]))
+#define MCF_INTC_ICR(x)                      (*(volatile uint8_t *)(&_MBAR[0x741 + ((x-1)*0x1)]))
+#define MCF_INTC_LIACK(x)                    (*(volatile uint8_t *)(&_MBAR[0x7E4 + ((x-1)*0x4)]))
+
+
+
+/* Bit definitions and macros for MCF_INTC_IPRH */
+#define MCF_INTC_IPRH_INT32                  (0x1)
+#define MCF_INTC_IPRH_INT33                  (0x2)
+#define MCF_INTC_IPRH_INT34                  (0x4)
+#define MCF_INTC_IPRH_INT35                  (0x8)
+#define MCF_INTC_IPRH_INT36                  (0x10)
+#define MCF_INTC_IPRH_INT37                  (0x20)
+#define MCF_INTC_IPRH_INT38                  (0x40)
+#define MCF_INTC_IPRH_INT39                  (0x80)
+#define MCF_INTC_IPRH_INT40                  (0x100)
+#define MCF_INTC_IPRH_INT41                  (0x200)
+#define MCF_INTC_IPRH_INT42                  (0x400)
+#define MCF_INTC_IPRH_INT43                  (0x800)
+#define MCF_INTC_IPRH_INT44                  (0x1000)
+#define MCF_INTC_IPRH_INT45                  (0x2000)
+#define MCF_INTC_IPRH_INT46                  (0x4000)
+#define MCF_INTC_IPRH_INT47                  (0x8000)
+#define MCF_INTC_IPRH_INT48                  (0x10000)
+#define MCF_INTC_IPRH_INT49                  (0x20000)
+#define MCF_INTC_IPRH_INT50                  (0x40000)
+#define MCF_INTC_IPRH_INT51                  (0x80000)
+#define MCF_INTC_IPRH_INT52                  (0x100000)
+#define MCF_INTC_IPRH_INT53                  (0x200000)
+#define MCF_INTC_IPRH_INT54                  (0x400000)
+#define MCF_INTC_IPRH_INT55                  (0x800000)
+#define MCF_INTC_IPRH_INT56                  (0x1000000)
+#define MCF_INTC_IPRH_INT57                  (0x2000000)
+#define MCF_INTC_IPRH_INT58                  (0x4000000)
+#define MCF_INTC_IPRH_INT59                  (0x8000000)
+#define MCF_INTC_IPRH_INT60                  (0x10000000)
+#define MCF_INTC_IPRH_INT61                  (0x20000000)
+#define MCF_INTC_IPRH_INT62                  (0x40000000)
+#define MCF_INTC_IPRH_INT63                  (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IPRL */
+#define MCF_INTC_IPRL_INT1                   (0x2)
+#define MCF_INTC_IPRL_INT2                   (0x4)
+#define MCF_INTC_IPRL_INT3                   (0x8)
+#define MCF_INTC_IPRL_INT4                   (0x10)
+#define MCF_INTC_IPRL_INT5                   (0x20)
+#define MCF_INTC_IPRL_INT6                   (0x40)
+#define MCF_INTC_IPRL_INT7                   (0x80)
+#define MCF_INTC_IPRL_INT8                   (0x100)
+#define MCF_INTC_IPRL_INT9                   (0x200)
+#define MCF_INTC_IPRL_INT10                  (0x400)
+#define MCF_INTC_IPRL_INT11                  (0x800)
+#define MCF_INTC_IPRL_INT12                  (0x1000)
+#define MCF_INTC_IPRL_INT13                  (0x2000)
+#define MCF_INTC_IPRL_INT14                  (0x4000)
+#define MCF_INTC_IPRL_INT15                  (0x8000)
+#define MCF_INTC_IPRL_INT16                  (0x10000)
+#define MCF_INTC_IPRL_INT17                  (0x20000)
+#define MCF_INTC_IPRL_INT18                  (0x40000)
+#define MCF_INTC_IPRL_INT19                  (0x80000)
+#define MCF_INTC_IPRL_INT20                  (0x100000)
+#define MCF_INTC_IPRL_INT21                  (0x200000)
+#define MCF_INTC_IPRL_INT22                  (0x400000)
+#define MCF_INTC_IPRL_INT23                  (0x800000)
+#define MCF_INTC_IPRL_INT24                  (0x1000000)
+#define MCF_INTC_IPRL_INT25                  (0x2000000)
+#define MCF_INTC_IPRL_INT26                  (0x4000000)
+#define MCF_INTC_IPRL_INT27                  (0x8000000)
+#define MCF_INTC_IPRL_INT28                  (0x10000000)
+#define MCF_INTC_IPRL_INT29                  (0x20000000)
+#define MCF_INTC_IPRL_INT30                  (0x40000000)
+#define MCF_INTC_IPRL_INT31                  (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRH */
+#define MCF_INTC_IMRH_INT_MASK32             (0x1)
+#define MCF_INTC_IMRH_INT_MASK33             (0x2)
+#define MCF_INTC_IMRH_INT_MASK34             (0x4)
+#define MCF_INTC_IMRH_INT_MASK35             (0x8)
+#define MCF_INTC_IMRH_INT_MASK36             (0x10)
+#define MCF_INTC_IMRH_INT_MASK37             (0x20)
+#define MCF_INTC_IMRH_INT_MASK38             (0x40)
+#define MCF_INTC_IMRH_INT_MASK39             (0x80)
+#define MCF_INTC_IMRH_INT_MASK40             (0x100)
+#define MCF_INTC_IMRH_INT_MASK41             (0x200)
+#define MCF_INTC_IMRH_INT_MASK42             (0x400)
+#define MCF_INTC_IMRH_INT_MASK43             (0x800)
+#define MCF_INTC_IMRH_INT_MASK44             (0x1000)
+#define MCF_INTC_IMRH_INT_MASK45             (0x2000)
+#define MCF_INTC_IMRH_INT_MASK46             (0x4000)
+#define MCF_INTC_IMRH_INT_MASK47             (0x8000)
+#define MCF_INTC_IMRH_INT_MASK48             (0x10000)
+#define MCF_INTC_IMRH_INT_MASK49             (0x20000)
+#define MCF_INTC_IMRH_INT_MASK50             (0x40000)
+#define MCF_INTC_IMRH_INT_MASK51             (0x80000)
+#define MCF_INTC_IMRH_INT_MASK52             (0x100000)
+#define MCF_INTC_IMRH_INT_MASK53             (0x200000)
+#define MCF_INTC_IMRH_INT_MASK54             (0x400000)
+#define MCF_INTC_IMRH_INT_MASK55             (0x800000)
+#define MCF_INTC_IMRH_INT_MASK56             (0x1000000)
+#define MCF_INTC_IMRH_INT_MASK57             (0x2000000)
+#define MCF_INTC_IMRH_INT_MASK58             (0x4000000)
+#define MCF_INTC_IMRH_INT_MASK59             (0x8000000)
+#define MCF_INTC_IMRH_INT_MASK60             (0x10000000)
+#define MCF_INTC_IMRH_INT_MASK61             (0x20000000)
+#define MCF_INTC_IMRH_INT_MASK62             (0x40000000)
+#define MCF_INTC_IMRH_INT_MASK63             (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRL */
+#define MCF_INTC_IMRL_MASKALL                (0x1)
+#define MCF_INTC_IMRL_INT_MASK1              (0x2)
+#define MCF_INTC_IMRL_INT_MASK2              (0x4)
+#define MCF_INTC_IMRL_INT_MASK3              (0x8)
+#define MCF_INTC_IMRL_INT_MASK4              (0x10)
+#define MCF_INTC_IMRL_INT_MASK5              (0x20)
+#define MCF_INTC_IMRL_INT_MASK6              (0x40)
+#define MCF_INTC_IMRL_INT_MASK7              (0x80)
+#define MCF_INTC_IMRL_INT_MASK8              (0x100)
+#define MCF_INTC_IMRL_INT_MASK9              (0x200)
+#define MCF_INTC_IMRL_INT_MASK10             (0x400)
+#define MCF_INTC_IMRL_INT_MASK11             (0x800)
+#define MCF_INTC_IMRL_INT_MASK12             (0x1000)
+#define MCF_INTC_IMRL_INT_MASK13             (0x2000)
+#define MCF_INTC_IMRL_INT_MASK14             (0x4000)
+#define MCF_INTC_IMRL_INT_MASK15             (0x8000)
+#define MCF_INTC_IMRL_INT_MASK16             (0x10000)
+#define MCF_INTC_IMRL_INT_MASK17             (0x20000)
+#define MCF_INTC_IMRL_INT_MASK18             (0x40000)
+#define MCF_INTC_IMRL_INT_MASK19             (0x80000)
+#define MCF_INTC_IMRL_INT_MASK20             (0x100000)
+#define MCF_INTC_IMRL_INT_MASK21             (0x200000)
+#define MCF_INTC_IMRL_INT_MASK22             (0x400000)
+#define MCF_INTC_IMRL_INT_MASK23             (0x800000)
+#define MCF_INTC_IMRL_INT_MASK24             (0x1000000)
+#define MCF_INTC_IMRL_INT_MASK25             (0x2000000)
+#define MCF_INTC_IMRL_INT_MASK26             (0x4000000)
+#define MCF_INTC_IMRL_INT_MASK27             (0x8000000)
+#define MCF_INTC_IMRL_INT_MASK28             (0x10000000)
+#define MCF_INTC_IMRL_INT_MASK29             (0x20000000)
+#define MCF_INTC_IMRL_INT_MASK30             (0x40000000)
+#define MCF_INTC_IMRL_INT_MASK31             (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCH */
+#define MCF_INTC_INTFRCH_INTFRC32            (0x1)
+#define MCF_INTC_INTFRCH_INTFRC33            (0x2)
+#define MCF_INTC_INTFRCH_INTFRC34            (0x4)
+#define MCF_INTC_INTFRCH_INTFRC35            (0x8)
+#define MCF_INTC_INTFRCH_INTFRC36            (0x10)
+#define MCF_INTC_INTFRCH_INTFRC37            (0x20)
+#define MCF_INTC_INTFRCH_INTFRC38            (0x40)
+#define MCF_INTC_INTFRCH_INTFRC39            (0x80)
+#define MCF_INTC_INTFRCH_INTFRC40            (0x100)
+#define MCF_INTC_INTFRCH_INTFRC41            (0x200)
+#define MCF_INTC_INTFRCH_INTFRC42            (0x400)
+#define MCF_INTC_INTFRCH_INTFRC43            (0x800)
+#define MCF_INTC_INTFRCH_INTFRC44            (0x1000)
+#define MCF_INTC_INTFRCH_INTFRC45            (0x2000)
+#define MCF_INTC_INTFRCH_INTFRC46            (0x4000)
+#define MCF_INTC_INTFRCH_INTFRC47            (0x8000)
+#define MCF_INTC_INTFRCH_INTFRC48            (0x10000)
+#define MCF_INTC_INTFRCH_INTFRC49            (0x20000)
+#define MCF_INTC_INTFRCH_INTFRC50            (0x40000)
+#define MCF_INTC_INTFRCH_INTFRC51            (0x80000)
+#define MCF_INTC_INTFRCH_INTFRC52            (0x100000)
+#define MCF_INTC_INTFRCH_INTFRC53            (0x200000)
+#define MCF_INTC_INTFRCH_INTFRC54            (0x400000)
+#define MCF_INTC_INTFRCH_INTFRC55            (0x800000)
+#define MCF_INTC_INTFRCH_INTFRC56            (0x1000000)
+#define MCF_INTC_INTFRCH_INTFRC57            (0x2000000)
+#define MCF_INTC_INTFRCH_INTFRC58            (0x4000000)
+#define MCF_INTC_INTFRCH_INTFRC59            (0x8000000)
+#define MCF_INTC_INTFRCH_INTFRC60            (0x10000000)
+#define MCF_INTC_INTFRCH_INTFRC61            (0x20000000)
+#define MCF_INTC_INTFRCH_INTFRC62            (0x40000000)
+#define MCF_INTC_INTFRCH_INTFRC63            (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCL */
+#define MCF_INTC_INTFRCL_INTFRC1             (0x2)
+#define MCF_INTC_INTFRCL_INTFRC2             (0x4)
+#define MCF_INTC_INTFRCL_INTFRC3             (0x8)
+#define MCF_INTC_INTFRCL_INTFRC4             (0x10)
+#define MCF_INTC_INTFRCL_INTFRC5             (0x20)
+#define MCF_INTC_INTFRCL_INTFRC6             (0x40)
+#define MCF_INTC_INTFRCL_INTFRC7             (0x80)
+#define MCF_INTC_INTFRCL_INTFRC8             (0x100)
+#define MCF_INTC_INTFRCL_INTFRC9             (0x200)
+#define MCF_INTC_INTFRCL_INTFRC10            (0x400)
+#define MCF_INTC_INTFRCL_INTFRC11            (0x800)
+#define MCF_INTC_INTFRCL_INTFRC12            (0x1000)
+#define MCF_INTC_INTFRCL_INTFRC13            (0x2000)
+#define MCF_INTC_INTFRCL_INTFRC14            (0x4000)
+#define MCF_INTC_INTFRCL_INTFRC15            (0x8000)
+#define MCF_INTC_INTFRCL_INTFRC16            (0x10000)
+#define MCF_INTC_INTFRCL_INTFRC17            (0x20000)
+#define MCF_INTC_INTFRCL_INTFRC18            (0x40000)
+#define MCF_INTC_INTFRCL_INTFRC19            (0x80000)
+#define MCF_INTC_INTFRCL_INTFRC20            (0x100000)
+#define MCF_INTC_INTFRCL_INTFRC21            (0x200000)
+#define MCF_INTC_INTFRCL_INTFRC22            (0x400000)
+#define MCF_INTC_INTFRCL_INTFRC23            (0x800000)
+#define MCF_INTC_INTFRCL_INTFRC24            (0x1000000)
+#define MCF_INTC_INTFRCL_INTFRC25            (0x2000000)
+#define MCF_INTC_INTFRCL_INTFRC26            (0x4000000)
+#define MCF_INTC_INTFRCL_INTFRC27            (0x8000000)
+#define MCF_INTC_INTFRCL_INTFRC28            (0x10000000)
+#define MCF_INTC_INTFRCL_INTFRC29            (0x20000000)
+#define MCF_INTC_INTFRCL_INTFRC30            (0x40000000)
+#define MCF_INTC_INTFRCL_INTFRC31            (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IRLR */
+#define MCF_INTC_IRLR_IRQ(x)                 (((x)&0x7F)<<0x1)
+
+/* Bit definitions and macros for MCF_INTC_IACKLPR */
+#define MCF_INTC_IACKLPR_PRI(x)              (((x)&0xF)<<0)
+#define MCF_INTC_IACKLPR_LEVEL(x)            (((x)&0x7)<<0x4)
+
+/* Bit definitions and macros for MCF_INTC_ICR */
+#define MCF_INTC_ICR_IP(x)                   (((x)&0x7)<<0)
+#define MCF_INTC_ICR_IL(x)                   (((x)&0x7)<<0x3)
+
+/* Bit definitions and macros for MCF_INTC_SWIACK */
+#define MCF_INTC_SWIACK_VECTOR(x)            (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_INTC_LIACK */
+#define MCF_INTC_LIACK_VECTOR(x)             (((x)&0xFF)<<0)
+
+
+#endif /* __MCF5475_INTC_H__ */