Recover the original Bas_gcc sources tagged as version 0.8.7,

which are the ones working.

.gdbinit

@@ -3,7 +3,7 @@ define tr
 	#!killall m68k-bdm-gdbserver
 	target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3
 	#target remote localhost:1234
-	#target remote | m68k-bdm-gdbserver pipe /dev/tblcf3
+	#target remote | m68k-bdm-gdbserver pipe /dev/tblcf1
 	#target dbug /dev/ttyS0
 	#monitor bdm-reset
 end

BaS_gcc.files

@@ -4,20 +4,6 @@ dma/MCD_tasks.c
 dma/MCD_tasksInit.c
 exe/basflash.c
 exe/basflash_start.c
-firebee/bas.elf
-firebee/bas.lk
-firebee/bas.map
-firebee/bas.s19
-firebee/basflash.elf
-firebee/basflash.map
-firebee/basflash.s19
-firebee/bashflash.lk
-firebee/depend
-firebee/libbas.a
-firebee/ram.elf
-firebee/ram.lk
-firebee/ram.map
-firebee/ram.s19
 flash/flash.c
 flash/s19reader.c
 fs/cc932.c
@@ -53,6 +39,7 @@ include/fecbd.h
 include/ff.h
 include/ffconf.h
 include/firebee.h
+include/font.h
 include/i2c-algo-bit.h
 include/i2c.h
 include/icmp.h
@@ -111,6 +98,7 @@ include/tftp.h
 include/udp.h
 include/usb.h
 include/usb_defs.h
+include/usb_hub.h
 include/user_io.h
 include/util.h
 include/version.h
@@ -130,34 +118,6 @@ include/x86prim_ops.h
 include/x86regs.h
 include/xhdi_sd.h
 kbd/ikbd.c
-m54455/bas.elf
-m54455/bas.lk
-m54455/bas.map
-m54455/bas.s19
-m54455/basflash.elf
-m54455/basflash.map
-m54455/basflash.s19
-m54455/bashflash.lk
-m54455/depend
-m54455/libbas.a
-m54455/ram.elf
-m54455/ram.lk
-m54455/ram.map
-m54455/ram.s19
-m5484lite/bas.elf
-m5484lite/bas.lk
-m5484lite/bas.map
-m5484lite/bas.s19
-m5484lite/basflash.elf
-m5484lite/basflash.map
-m5484lite/basflash.s19
-m5484lite/bashflash.lk
-m5484lite/depend
-m5484lite/libbas.a
-m5484lite/ram.elf
-m5484lite/ram.lk
-m5484lite/ram.map
-m5484lite/ram.s19
 net/am79c874.c
 net/arp.c
 net/bcm5222.c
@@ -171,7 +131,6 @@ net/nif.c
 net/queue.c
 net/tftp.c
 net/udp.c
-nutil/s19header
 nutil/s19header.c
 pci/ehci-hcd.c
 pci/ohci-hcd.c
@@ -186,56 +145,16 @@ spi/sd_card.c
 sys/BaS.c
 sys/cache.c
 sys/driver_mem.c
-sys/exceptions.S
 sys/fault_vectors.c
 sys/init_fpga.c
 sys/interrupts.c
 sys/mmu.c
-sys/startcf.S
 sys/sysinit.c
-usb/usb.c
-usb/usb_mouse.c
-util/bas_printf.c
-util/bas_string.c
-util/printf_helper.S
-util/wait.c
-video/fbmem.c
-video/fbmodedb.c
-video/fbmon.c
-video/fnt_st_8x16.c
-video/offscreen.c
-video/vdi_fill.c
-video/videl.c
-video/video.c
-x86emu/x86biosemu.c
-x86emu/x86debug.c
-x86emu/x86decode.c
-x86emu/x86fpu.c
-x86emu/x86ops.c
-x86emu/x86ops2.c
-x86emu/x86pcibios.c
-x86emu/x86prim_ops.c
-x86emu/x86sys.c
-xhdi/xhdi_interface.c
-xhdi/xhdi_sd.c
-xhdi/xhdi_vec.S
-bas.lk.in
-bas_firebee.bdm
-bas_m5484.bdm
-basflash.lk.in
-check.bdm
-COPYING
-COPYING.LESSER
-dump.bdm
-mcf5474.gdb
-Makefile
-tos/jtagwait/Makefile
-tos/jtagwait/sources/jtagwait.c
-tos/jtagwait/include/driver_vec.h
-tos/bascook/Makefile
-tos/mcdcook/sources/bascook.c
+tos/bascook/sources/bascook.c
 tos/jtagwait/include/bas_printf.h
 tos/jtagwait/include/bas_string.h
+tos/jtagwait/include/driver_vec.h
+tos/jtagwait/include/MCF5475.h
 tos/jtagwait/include/MCF5475_CLOCK.h
 tos/jtagwait/include/MCF5475_CTM.h
 tos/jtagwait/include/MCF5475_DMA.h
@@ -259,13 +178,23 @@ tos/jtagwait/include/MCF5475_SLT.h
 tos/jtagwait/include/MCF5475_SRAM.h
 tos/jtagwait/include/MCF5475_USB.h
 tos/jtagwait/include/MCF5475_XLB.h
-tos/jtagwait/include/MCF5475.h
-tos/jtagwait/include/driver_vec.h
+tos/jtagwait/sources/jtagwait.c
+usb/usb.c
+usb/usb_hub.c
+usb/usb_kbd.c
 tos/jtagwait/sources/bas_printf.c
 tos/jtagwait/sources/bas_string.c
-tos/jtagwait/sources/printf_helper.S
-tos/bascook/Makefile
-tos/bascook/sources/bascook.c
-tos/Makefile
-usb/usb_hub.c
-include/usb_hub.h
+tos/vmem_test/Makefile
+tos/vmem_test/sources/bas_printf.c
+tos/vmem_test/sources/bas_string.c
+tos/vmem_test/sources/printf_helper.S
+tos/vmem_test/sources/vmem_test.c
+sys/startcf.S
+sys/exceptions.S
+util/bas_printf.c
+util/bas_string.c
+util/printf_helper.S
+util/wait.c
+bas.lk.in
+i2c/i2c.c
+Makefile

BaS_gcc.includes

@@ -1,2 +1,2 @@
 include
-/usr/m68k-elf/include
+tos/jtagwait/include

Makefile

@@ -1,4 +1,4 @@
-# # Makefile for Firebee BaS
+# Makefile for Firebee BaS
 #
 # This Makefile is meant for cross compiling the BaS with Vincent Riviere's cross compilers.
 # If you want to compile native on an Atari (you will need at least GCC 4.6.3), set
@@ -31,26 +31,28 @@ NATIVECC=gcc
 
 INCLUDE=-Iinclude
 CFLAGS=-mcpu=5474 \
+        -g \
 		-Wall \
-		-g3 \
 		-fomit-frame-pointer \
 		-ffreestanding \
 		-fleading-underscore \
+		-mno-strict-align \
 		-Wa,--register-prefix-optional
 CFLAGS_OPTIMIZED = -mcpu=5474 \
 		-Wall \
-		-g3 \
 		-O2 \
+		-g \
 		-fomit-frame-pointer \
 		-ffreestanding \
 		-fleading-underscore \
 		-Wa,--register-prefix-optional
+LDFLAGS=-g
 
 TRGTDIRS= ./firebee ./m5484lite ./m54455
 OBJDIRS=$(patsubst %, %/objs,$(TRGTDIRS))
 TOOLDIR=util
 
-VPATH=dma exe flash fs if kbd pci spi sys usb net util video radeon x86emu xhdi
+VPATH=dma exe flash fs i2c if kbd pci spi sys usb net util video radeon x86emu xhdi
 
 # Linker control file. The final $(LDCFILE) is intermediate only (preprocessed version of $(LDCSRC)
 LDCFILE=bas.lk
@@ -83,6 +85,7 @@ CSRCS= \
 	s19reader.c \
 	flash.c \
 	dma.c \
+        i2c.c \
 	xhdi_sd.c \
 	xhdi_interface.c \
 	pci.c \
@@ -97,6 +100,7 @@ CSRCS= \
 	ehci-hcd.c \
 	usb_hub.c \
 	usb_mouse.c \
+	usb_kbd.c \
 	ikbd.c \
 	\
 	nbuf.c \
@@ -270,7 +274,7 @@ endif
 $(1)_MAPFILE_RAM=$(1)/$$(basename $$(RAM_EXEC)).map
 $(1)/$$(RAM_EXEC): $(1)/$(LIBBAS) $(LDCSRC)
 	$(CPP) $(INCLUDE) -DCOMPILE_RAM -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCSRC) -o $(1)/$$(LDRFILE)
-	$(LD) -g --oformat $$(FORMAT) -Map $$($(1)_MAPFILE_RAM) --cref -T $(1)/$$(LDRFILE) -o $$@
+	$(LD) $(LDFLAGS) --oformat $$(FORMAT) -Map $$($(1)_MAPFILE_RAM) --cref -T $(1)/$$(LDRFILE) -o $$@
 ifeq ($(COMPILE_ELF),Y)
 	$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
 else

bas.lk.in

@@ -10,253 +10,256 @@
 
 /* make bas_rom access flags rx if compiling to RAM */
 #ifdef COMPILE_RAM
-#define ROMFLAGS	WX
+#define ROMFLAGS    WX
 #else
-#define ROMFLAGS	RX
+#define ROMFLAGS    RX
 #endif /* COMPILE_RAM */
 
 MEMORY
 {
    bas_rom (ROMFLAGS) : ORIGIN = TARGET_ADDRESS, LENGTH = 0x00100000
    /*
-	* target to copy BaS data segment to. 1M should be enough for now
-	*/
+    * target to copy BaS data segment to. 1M should be enough for now
+    */
    bas_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00200000, LENGTH = 0x00100000
    /*
-	* driver_ram is an uncached, reserved memory area for drivers (e.g. USB) that need this type of memory
-	*/
+    * driver_ram is an uncached, reserved memory area for drivers (e.g. USB) that need this type of memory
+    */
    driver_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00100000, LENGTH = 0x00100000
 }
 
 SECTIONS
 {
-	/* BaS in ROM */
-	.text :
-	{
-		OBJDIR/startcf.o(.text) /* this one is the entry point so it must be the first */
+        /* BaS in ROM */
+        .text :
+        {
+                OBJDIR/startcf.o(.text) /* this one is the entry point so it must be the first */
 
-		OBJDIR/sysinit.o(.text)
-		OBJDIR/fault_vectors.o(.text)
+                OBJDIR/sysinit.o(.text)
+                OBJDIR/fault_vectors.o(.text)
 #ifdef MACHINE_FIREBEE
-		OBJDIR/init_fpga.o(.text)
+                OBJDIR/init_fpga.o(.text)
 #endif /* MACHINE_FIREBEE */
-		OBJDIR/wait.o(.text)
-		OBJDIR/exceptions.o(.text)
-		OBJDIR/driver_vec.o(.text)
-		OBJDIR/interrupts.o(.text)
-		OBJDIR/mmu.o(.text)
+                OBJDIR/wait.o(.text)
+                OBJDIR/exceptions.o(.text)
+                OBJDIR/driver_vec.o(.text)
+                OBJDIR/interrupts.o(.text)
+                OBJDIR/mmu.o(.text)
 
-		OBJDIR/BaS.o(.text)
-		OBJDIR/pci.o(.text)
-		OBJDIR/pci_wrappers.o(.text)
-		OBJDIR/usb.o(.text)
-		OBJDIR/driver_mem.o(.text)
-		OBJDIR/usb_hub.o(.text)
-		OBJDIR/usb_mouse.o(.text)
-		OBJDIR/ohci-hcd.o(.text)
-		OBJDIR/ehci-hcd.o(.text)
-		OBJDIR/wait.o(.text)
+                OBJDIR/BaS.o(.text)
+                OBJDIR/pci.o(.text)
+                OBJDIR/pci_wrappers.o(.text)
+                OBJDIR/usb.o(.text)
+                OBJDIR/driver_mem.o(.text)
+                OBJDIR/usb_hub.o(.text)
+                OBJDIR/usb_mouse.o(.text)
+                OBJDIR/usb_kbd.o(.text)
+                OBJDIR/ohci-hcd.o(.text)
+                OBJDIR/ehci-hcd.o(.text)
+                OBJDIR/wait.o(.text)
 
-		OBJDIR/nbuf.o(.text)
-		OBJDIR/net_timer.o(.text)
-		OBJDIR/queue.o(.text)
-		OBJDIR/nif.o(.text)
-		OBJDIR/fecbd.o(.text)
-		OBJDIR/fec.o(.text)
-		OBJDIR/am79c874.o(.text)
-		OBJDIR/bcm5222.o(.text)
-		OBJDIR/ip.o(.text)
-		OBJDIR/udp.o(text)
-		OBJDIR/bootp.o(text)
-		OBJDIR/tftp.o(text)
-		OBJDIR/arp.o(text)
+                OBJDIR/nbuf.o(.text)
+                OBJDIR/net_timer.o(.text)
+                OBJDIR/queue.o(.text)
+                OBJDIR/nif.o(.text)
+                OBJDIR/fecbd.o(.text)
+                OBJDIR/fec.o(.text)
+                OBJDIR/am79c874.o(.text)
+                OBJDIR/bcm5222.o(.text)
+                OBJDIR/ip.o(.text)
+                OBJDIR/udp.o(text)
+                OBJDIR/bootp.o(text)
+                OBJDIR/tftp.o(text)
+                OBJDIR/arp.o(text)
 
-		OBJDIR/unicode.o(.text)
-		OBJDIR/mmc.o(.text)
-		OBJDIR/ff.o(.text)
-		OBJDIR/sd_card.o(.text)
-		OBJDIR/s19reader.o(.text)
-		OBJDIR/bas_printf.o(.text)
-		OBJDIR/bas_string.o(.text)
-		OBJDIR/printf_helper.o(.text)
-		OBJDIR/cache.o(.text)
-		OBJDIR/dma.o(.text)
-		OBJDIR/MCD_dmaApi.o(.text)
-		OBJDIR/MCD_tasks.o(.text)
-		OBJDIR/MCD_tasksInit.o(.text)
+                OBJDIR/unicode.o(.text)
+                OBJDIR/mmc.o(.text)
+                OBJDIR/ff.o(.text)
+                OBJDIR/sd_card.o(.text)
+                OBJDIR/s19reader.o(.text)
+                OBJDIR/bas_printf.o(.text)
+                OBJDIR/bas_string.o(.text)
+                OBJDIR/printf_helper.o(.text)
+                OBJDIR/cache.o(.text)
+                OBJDIR/dma.o(.text)
+                OBJDIR/MCD_dmaApi.o(.text)
+                OBJDIR/MCD_tasks.o(.text)
+                OBJDIR/MCD_tasksInit.o(.text)
 
-		OBJDIR/video.o(.text)
-		OBJDIR/videl.o(.text)
-		OBJDIR/fbmem.o(.text)
-		OBJDIR/fbmon.o(.text)
-		OBJDIR/fbmodedb.o(.text)
-		OBJDIR/offscreen.o(.text)
+                OBJDIR/video.o(.text)
+                OBJDIR/videl.o(.text)
+                OBJDIR/fbmem.o(.text)
+                OBJDIR/fbmon.o(.text)
+                OBJDIR/fbmodedb.o(.text)
+                OBJDIR/offscreen.o(.text)
 
-		OBJDIR/x86decode.o(.text)
-		OBJDIR/x86ops.o(.text)
-		OBJDIR/x86ops2.o(.text)
-		OBJDIR/x86fpu.o(.text)
-		OBJDIR/x86sys.o(.text)
-		OBJDIR/x86biosemu.o(.text)
-		OBJDIR/x86debug.o(.text)
-		OBJDIR/x86prim_ops.o(.text)
-		OBJDIR/x86pcibios.o(.text)
+                OBJDIR/x86decode.o(.text)
+                OBJDIR/x86ops.o(.text)
+                OBJDIR/x86ops2.o(.text)
+                OBJDIR/x86fpu.o(.text)
+                OBJDIR/x86sys.o(.text)
+                OBJDIR/x86biosemu.o(.text)
+                OBJDIR/x86debug.o(.text)
+                OBJDIR/x86prim_ops.o(.text)
+                OBJDIR/x86pcibios.o(.text)
 
-		OBJDIR/radeon_base.o(.text)
-		OBJDIR/radeon_accel.o(.text)
-		OBJDIR/radeon_cursor.o(.text)
-		OBJDIR/radeon_monitor.o(.text)
+                OBJDIR/radeon_base.o(.text)
+                OBJDIR/radeon_accel.o(.text)
+                OBJDIR/radeon_cursor.o(.text)
+                OBJDIR/radeon_monitor.o(.text)
 
-		OBJDIR/xhdi_sd.o(.text)
-		OBJDIR/xhdi_interface.o(.text)
-		OBJDIR/xhdi_vec.o(.text)
+                OBJDIR/xhdi_sd.o(.text)
+                OBJDIR/xhdi_interface.o(.text)
+                OBJDIR/xhdi_vec.o(.text)
 
 #ifdef COMPILE_RAM
-		/*
-		 * if we compile to RAM anyway, there is no need to copy anything
-		 */
-		. = ALIGN(4);
-		__BAS_DATA_START = .;
-		*(.data)
-		__BAS_DATA_END = .;
-		__BAS_BSS_START = .;
-		*(.bss)
-		__BAS_BSS_END = .;
+                /*
+                 * if we compile to RAM anyway, there is no need to copy anything
+                 */
+                . = ALIGN(4);
+                __BAS_DATA_START = .;
+                *(.data)
+                __BAS_DATA_END = .;
+                __BAS_BSS_START = .;
+                *(.bss)
+                __BAS_BSS_END = .;
 #endif /* COMPILE_RAM */
 
 #if (FORMAT_ELF == 1)
-		*(.rodata)
-		*(.rodata.*)
+                *(.rodata)
+                *(.rodata.*)
 #endif
-	} > bas_rom
+        } > bas_rom
 
 #if (TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS)
-	/*
-	 * put BaS .data and .bss segments to flash, but relocate it to RAM after initialize_hardware() ran
-	 */
-	.bas :
-	AT (ALIGN(ADDR(.text) + SIZEOF(.text), 4))
-	{
-		. = ALIGN(4);		/* same alignment than AT() statement! */
-		__BAS_DATA_START = .;
-		*(.data)
-		__BAS_DATA_END = .;
-		__BAS_BSS_START = .;
-		*(.bss)
-		__BAS_BSS_END = .;
+        /*
+         * put BaS .data and .bss segments to flash, but relocate it to RAM after initialize_hardware() ran
+         */
+        .bas :
+        AT (ALIGN(ADDR(.text) + SIZEOF(.text), 4))
+        {
+                . = ALIGN(4);       /* same alignment than AT() statement! */
+                __BAS_DATA_START = .;
+                *(.data)
+                __BAS_DATA_END = .;
+                __BAS_BSS_START = .;
+                *(.bss)
+                __BAS_BSS_END = .;
 
-		. = ALIGN(16);
-	} > bas_ram
+                . = ALIGN(16);
+        } > bas_ram
 #endif
 
-	.driver_memory :
-	{
-		. = ALIGN(4);
-		_driver_mem_buffer = .;
-		//. = . + DRIVER_MEM_BUFFER_SIZE;
-	} > driver_ram
+        .driver_memory :
+        {
+                . = ALIGN(4);
+                _driver_mem_buffer = .;
+                //. = . + DRIVER_MEM_BUFFER_SIZE;
+        } > driver_ram
 
-	/*
-	 * Global memory map
-	 */
+        /*
+         * Global memory map
+         */
 
-	/* SDRAM Initialization */
-	___SDRAM                = SDRAM_START;
-	___SDRAM_SIZE           = SDRAM_SIZE;
-	_SDRAM_VECTOR_TABLE		= ___SDRAM;
+        /* SDRAM Initialization */
+        ___SDRAM                = SDRAM_START;
+        ___SDRAM_SIZE           = SDRAM_SIZE;
+        _SDRAM_VECTOR_TABLE     = ___SDRAM;
 
-	/* ST-RAM */
-	__STRAM                 = ___SDRAM;
-	__STRAM_END             = __TOS;
+        /* ST-RAM */
+        __STRAM                 = ___SDRAM;
+        __STRAM_END             = __TOS;
 
-	/* TOS */
-	__TOS                   = 0x00e00000;
+        /* TOS */
+        __TOS                   = 0x00e00000;
 
-	/* FastRAM */
-	__FASTRAM               = 0x10000000;
-	__TARGET_ADDRESS		= TARGET_ADDRESS;
+        /* FastRAM */
+        __FASTRAM               = 0x10000000;
+        __TARGET_ADDRESS        = TARGET_ADDRESS;
 
 #if TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS
-	__FASTRAM_END           = __BAS_IN_RAM;
+        __FASTRAM_END           = __BAS_IN_RAM;
 #else
-	__FASTRAM_END			= TARGET_ADDRESS;
+        __FASTRAM_END           = TARGET_ADDRESS;
 #endif
-	__FASTRAM_SIZE			= __FASTRAM_END - __FASTRAM;
+        __FASTRAM_SIZE          = __FASTRAM_END - __FASTRAM;
 
-	/* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */
-	___BOOT_FLASH           = BOOTFLASH_BASE_ADDRESS;
-	___BOOT_FLASH_SIZE      = BOOTFLASH_SIZE;
+        /* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */
+        ___BOOT_FLASH           = BOOTFLASH_BASE_ADDRESS;
+        ___BOOT_FLASH_SIZE      = BOOTFLASH_SIZE;
 
 #if TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS
-	/* BaS */
-	__BAS_LMA               = LOADADDR(.bas);
-	__BAS_IN_RAM            = ADDR(.bas);
-	__BAS_SIZE              = SIZEOF(.bas);
+        /* BaS */
+        __BAS_LMA               = LOADADDR(.bas);
+        __BAS_IN_RAM            = ADDR(.bas);
+        __BAS_SIZE              = SIZEOF(.bas);
 #else
-	/* BaS is already in RAM - no need to copy anything */
-	__BAS_IN_RAM			= __FASTRAM_END;
-	__BAS_SIZE				= 0;
-	__BAS_LMA				= __BAS_IN_RAM;
+        /* BaS is already in RAM - no need to copy anything */
+        __BAS_IN_RAM            = __FASTRAM_END;
+        __BAS_SIZE              = 0;
+        __BAS_LMA               = __BAS_IN_RAM;
 #endif
 
-	/* Other flash components */
-	__FIRETOS               = 0xe0400000;
-	__EMUTOS                = EMUTOS_BASE_ADDRESS;
-	__EMUTOS_SIZE           = 0x00100000;
+        /* Other flash components */
+        __FIRETOS               = 0xe0400000;
+        __EMUTOS                = EMUTOS_BASE_ADDRESS;
+        __EMUTOS_SIZE           = 0x00100000;
 
-	/* where FPGA data lives in flash */
-	__FPGA_CONFIG 		= 0xe0700000;
-	__FPGA_CONFIG_SIZE 	= 0x100000;
+        /* where FPGA data lives in flash */
+        __FPGA_CONFIG       = 0xe0700000;
+        __FPGA_CONFIG_SIZE  = 0x100000;
 
-	/* VIDEO RAM BASIS */
-	__VRAM                  = 0x60000000;
+        /* VIDEO RAM BASIS */
+        __VRAM                  = 0x60000000;
 
-	/* Memory mapped registers */
-	__MBAR                  = 0xFF000000;
+        /* Memory mapped registers */
+        __MBAR                  = 0xFF000000;
 
-	/* 32KB on-chip System SRAM */
-	__SYS_SRAM              = __MBAR + 0x10000;
-	__SYS_SRAM_SIZE         = 0x00008000;
+        /* 32KB on-chip System SRAM */
+        __SYS_SRAM              = __MBAR + 0x10000;
+        __SYS_SRAM_SIZE         = 0x00008000;
 
-	/* MMU memory mapped registers */
-	__MMUBAR                = 0xFF040000;
+        /* MMU memory mapped registers */
+        __MMUBAR                = 0xFF040000;
 
-	/*
-	 * 4KB on-chip Core SRAM0: -> exception table
-	 */
-	__RAMBAR0               = 0xFF100000;
-	__RAMBAR0_SIZE          = 0x00001000;
+        /*
+         * 4KB on-chip Core SRAM0: -> exception table
+         */
+        __RAMBAR0               = 0xFF100000;
+        __RAMBAR0_SIZE          = 0x00001000;
 
-	/* 4KB on-chip Core SRAM1 */
-	__RAMBAR1               = 0xFF101000;
-	__RAMBAR1_SIZE          = 0x00001000;
-	__SUP_SP                = __RAMBAR1 + __RAMBAR1_SIZE - 4;
+        /* 4KB on-chip Core SRAM1 */
+        __RAMBAR1               = 0xFF101000;
+        __RAMBAR1_SIZE          = 0x00001000;
+        __SUP_SP                = __RAMBAR1 + __RAMBAR1_SIZE - 4;
 
-	/*
-	 * this flag (if 1) indicates that FPGA configuration has been loaded through JTAG
-	 * and shouldn't be overwritten on boot
-	 */
-	__FPGA_JTAG_LOADED		= __RAMBAR1;
-	__FPGA_JTAG_VALID		= __RAMBAR1 + 4;
-	/* system variables */
+    /*
+     * this flag (if 1) indicates that FPGA configuration has been loaded through JTAG
+     * and shouldn't be overwritten on boot
+     */
+    __FPGA_JTAG_LOADED      = __RAMBAR1;
+    __FPGA_JTAG_VALID       = __RAMBAR1 + 4;
+    /* system variables */
 
-	/* RAMBAR0 0 to 0x7FF -> exception vectors */
-	_rt_mod    = __RAMBAR0 + 0x800;
-	_rt_ssp    = __RAMBAR0 + 0x804;
-	_rt_usp    = __RAMBAR0 + 0x808;
-	_rt_vbr    = __RAMBAR0 + 0x80C;  	/* (8)01 */
-	_rt_cacr   = __RAMBAR0 + 0x810;   	/* 002 */
-	_rt_asid   = __RAMBAR0 + 0x814;   	/* 003 */
-	_rt_acr0   = __RAMBAR0 + 0x818;   	/* 004 */
-	_rt_acr1   = __RAMBAR0 + 0x81c;   	/* 005 */
-	_rt_acr2   = __RAMBAR0 + 0x820;   	/* 006 */
-	_rt_acr3   = __RAMBAR0 + 0x824;   	/* 007 */
-	_rt_mmubar = __RAMBAR0 + 0x828;		/* 008 */
-	_rt_sr     = __RAMBAR0 + 0x82c;
-	_d0_save   = __RAMBAR0 + 0x830;
-	_a7_save   = __RAMBAR0 + 0x834;
-	_video_tlb = __RAMBAR0 + 0x838;
-	_video_sbt = __RAMBAR0 + 0x83C;
-	_rt_mbar   = __RAMBAR0 + 0x844;   	/* (c)0f */
+        /* system variables */
+
+        /* RAMBAR0 0 to 0x7FF -> exception vectors */
+        _rt_mod    = __RAMBAR0 + 0x800;
+        _rt_ssp    = __RAMBAR0 + 0x804;
+        _rt_usp    = __RAMBAR0 + 0x808;
+        _rt_vbr    = __RAMBAR0 + 0x80C;     /* (8)01 */
+        _rt_cacr   = __RAMBAR0 + 0x810;     /* 002 */
+        _rt_asid   = __RAMBAR0 + 0x814;     /* 003 */
+        _rt_acr0   = __RAMBAR0 + 0x818;     /* 004 */
+        _rt_acr1   = __RAMBAR0 + 0x81c;     /* 005 */
+        _rt_acr2   = __RAMBAR0 + 0x820;     /* 006 */
+        _rt_acr3   = __RAMBAR0 + 0x824;     /* 007 */
+        _rt_mmubar = __RAMBAR0 + 0x828;     /* 008 */
+        _rt_sr     = __RAMBAR0 + 0x82c;
+        _d0_save   = __RAMBAR0 + 0x830;
+        _a7_save   = __RAMBAR0 + 0x834;
+        _video_tlb = __RAMBAR0 + 0x838;
+        _video_sbt = __RAMBAR0 + 0x83C;
+        _rt_mbar   = __RAMBAR0 + 0x844;     /* (c)0f */
 
 }

bas_firebee.bdm

@@ -63,10 +63,6 @@ write 0xFF000104 0x710D0F00 4	# SDCR (lock SDMR and enable refresh)
 sleep 100
 
 load -v firebee/ram.elf
-write-ctrl 0x80e	0x2700
-write-ctrl 0x2	0xa50c8120
-dump-register SR
-dump-register CACR
-dump-register MBAR
+
 execute
 wait

dma/MCD_tasks.c

@@ -7,253 +7,253 @@
 
 #include "MCD_dma.h"
 
-uint32_t MCD_varTab0[];
-uint32_t MCD_varTab1[];
-uint32_t MCD_varTab2[];
-uint32_t MCD_varTab3[];
-uint32_t MCD_varTab4[];
-uint32_t MCD_varTab5[];
-uint32_t MCD_varTab6[];
-uint32_t MCD_varTab7[];
-uint32_t MCD_varTab8[];
-uint32_t MCD_varTab9[];
-uint32_t MCD_varTab10[];
-uint32_t MCD_varTab11[];
-uint32_t MCD_varTab12[];
-uint32_t MCD_varTab13[];
-uint32_t MCD_varTab14[];
-uint32_t MCD_varTab15[];
+u32 MCD_varTab0[];
+u32 MCD_varTab1[];
+u32 MCD_varTab2[];
+u32 MCD_varTab3[];
+u32 MCD_varTab4[];
+u32 MCD_varTab5[];
+u32 MCD_varTab6[];
+u32 MCD_varTab7[];
+u32 MCD_varTab8[];
+u32 MCD_varTab9[];
+u32 MCD_varTab10[];
+u32 MCD_varTab11[];
+u32 MCD_varTab12[];
+u32 MCD_varTab13[];
+u32 MCD_varTab14[];
+u32 MCD_varTab15[];
 
-uint32_t MCD_funcDescTab0[];
+u32 MCD_funcDescTab0[];
 #ifdef MCD_INCLUDE_EU
-uint32_t MCD_funcDescTab1[];
-uint32_t MCD_funcDescTab2[];
-uint32_t MCD_funcDescTab3[];
-uint32_t MCD_funcDescTab4[];
-uint32_t MCD_funcDescTab5[];
-uint32_t MCD_funcDescTab6[];
-uint32_t MCD_funcDescTab7[];
-uint32_t MCD_funcDescTab8[];
-uint32_t MCD_funcDescTab9[];
-uint32_t MCD_funcDescTab10[];
-uint32_t MCD_funcDescTab11[];
-uint32_t MCD_funcDescTab12[];
-uint32_t MCD_funcDescTab13[];
-uint32_t MCD_funcDescTab14[];
-uint32_t MCD_funcDescTab15[];
+u32 MCD_funcDescTab1[];
+u32 MCD_funcDescTab2[];
+u32 MCD_funcDescTab3[];
+u32 MCD_funcDescTab4[];
+u32 MCD_funcDescTab5[];
+u32 MCD_funcDescTab6[];
+u32 MCD_funcDescTab7[];
+u32 MCD_funcDescTab8[];
+u32 MCD_funcDescTab9[];
+u32 MCD_funcDescTab10[];
+u32 MCD_funcDescTab11[];
+u32 MCD_funcDescTab12[];
+u32 MCD_funcDescTab13[];
+u32 MCD_funcDescTab14[];
+u32 MCD_funcDescTab15[];
 #endif
 
-uint32_t MCD_contextSave0[];
-uint32_t MCD_contextSave1[];
-uint32_t MCD_contextSave2[];
-uint32_t MCD_contextSave3[];
-uint32_t MCD_contextSave4[];
-uint32_t MCD_contextSave5[];
-uint32_t MCD_contextSave6[];
-uint32_t MCD_contextSave7[];
-uint32_t MCD_contextSave8[];
-uint32_t MCD_contextSave9[];
-uint32_t MCD_contextSave10[];
-uint32_t MCD_contextSave11[];
-uint32_t MCD_contextSave12[];
-uint32_t MCD_contextSave13[];
-uint32_t MCD_contextSave14[];
-uint32_t MCD_contextSave15[];
+u32 MCD_contextSave0[];
+u32 MCD_contextSave1[];
+u32 MCD_contextSave2[];
+u32 MCD_contextSave3[];
+u32 MCD_contextSave4[];
+u32 MCD_contextSave5[];
+u32 MCD_contextSave6[];
+u32 MCD_contextSave7[];
+u32 MCD_contextSave8[];
+u32 MCD_contextSave9[];
+u32 MCD_contextSave10[];
+u32 MCD_contextSave11[];
+u32 MCD_contextSave12[];
+u32 MCD_contextSave13[];
+u32 MCD_contextSave14[];
+u32 MCD_contextSave15[];
 
-uint32_t MCD_realTaskTableSrc[] =
+u32 MCD_realTaskTableSrc[] =
 {
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab0,   /* Task 0 Variable Table */
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_varTab0,   /* Task 0 Variable Table */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave0,  /* Task 0 context save space */
+    (u32)MCD_contextSave0,  /* Task 0 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab1,   /* Task 1 Variable Table */
+    (u32)MCD_varTab1,   /* Task 1 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab1,  /* Task 1 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab1,  /* Task 1 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave1,  /* Task 1 context save space */
+    (u32)MCD_contextSave1,  /* Task 1 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab2,   /* Task 2 Variable Table */
+    (u32)MCD_varTab2,   /* Task 2 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab2,  /* Task 2 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab2,  /* Task 2 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave2,  /* Task 2 context save space */
+    (u32)MCD_contextSave2,  /* Task 2 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab3,   /* Task 3 Variable Table */
+    (u32)MCD_varTab3,   /* Task 3 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab3,  /* Task 3 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab3,  /* Task 3 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave3,  /* Task 3 context save space */
+    (u32)MCD_contextSave3,  /* Task 3 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab4,   /* Task 4 Variable Table */
+    (u32)MCD_varTab4,   /* Task 4 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab4,  /* Task 4 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab4,  /* Task 4 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave4,  /* Task 4 context save space */
+    (u32)MCD_contextSave4,  /* Task 4 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab5,   /* Task 5 Variable Table */
+    (u32)MCD_varTab5,   /* Task 5 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab5,  /* Task 5 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab5,  /* Task 5 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave5,  /* Task 5 context save space */
+    (u32)MCD_contextSave5,  /* Task 5 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab6,   /* Task 6 Variable Table */
+    (u32)MCD_varTab6,   /* Task 6 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab6,  /* Task 6 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab6,  /* Task 6 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave6,  /* Task 6 context save space */
+    (u32)MCD_contextSave6,  /* Task 6 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab7,   /* Task 7 Variable Table */
+    (u32)MCD_varTab7,   /* Task 7 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab7,  /* Task 7 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab7,  /* Task 7 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave7,  /* Task 7 context save space */
+    (u32)MCD_contextSave7,  /* Task 7 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab8,   /* Task 8 Variable Table */
+    (u32)MCD_varTab8,   /* Task 8 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab8,  /* Task 8 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab8,  /* Task 8 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave8,  /* Task 8 context save space */
+    (u32)MCD_contextSave8,  /* Task 8 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab9,   /* Task 9 Variable Table */
+    (u32)MCD_varTab9,   /* Task 9 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab9,  /* Task 9 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab9,  /* Task 9 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave9,  /* Task 9 context save space */
+    (u32)MCD_contextSave9,  /* Task 9 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab10,  /* Task 10 Variable Table */
+    (u32)MCD_varTab10,  /* Task 10 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab10, /* Task 10 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab10, /* Task 10 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave10, /* Task 10 context save space */
+    (u32)MCD_contextSave10, /* Task 10 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab11,  /* Task 11 Variable Table */
+    (u32)MCD_varTab11,  /* Task 11 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab11, /* Task 11 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab11, /* Task 11 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave11, /* Task 11 context save space */
+    (u32)MCD_contextSave11, /* Task 11 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab12,  /* Task 12 Variable Table */
+    (u32)MCD_varTab12,  /* Task 12 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab12, /* Task 12 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab12, /* Task 12 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave12, /* Task 12 context save space */
+    (u32)MCD_contextSave12, /* Task 12 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab13,  /* Task 13 Variable Table */
+    (u32)MCD_varTab13,  /* Task 13 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab13, /* Task 13 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab13, /* Task 13 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave13, /* Task 13 context save space */
+    (u32)MCD_contextSave13, /* Task 13 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab14,  /* Task 14 Variable Table */
+    (u32)MCD_varTab14,  /* Task 14 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab14, /* Task 14 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab14, /* Task 14 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave14, /* Task 14 context save space */
+    (u32)MCD_contextSave14, /* Task 14 context save space */
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_varTab15,  /* Task 15 Variable Table */
+    (u32)MCD_varTab15,  /* Task 15 Variable Table */
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_funcDescTab15, /* Task 15 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab15, /* Task 15 Function Descriptor Table & Flags */
 #else
-    (uint32_t)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
+    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
 #endif
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_contextSave15, /* Task 15 context save space */
+    (u32)MCD_contextSave15, /* Task 15 context save space */
     0x00000000,
 };
 
 
-uint32_t MCD_varTab0[] =
+u32 MCD_varTab0[] =
 {   /* Task 0 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -290,7 +290,7 @@ uint32_t MCD_varTab0[] =
 };
 
 
-uint32_t MCD_varTab1[] =
+u32 MCD_varTab1[] =
 {   /* Task 1 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -326,7 +326,7 @@ uint32_t MCD_varTab1[] =
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab2[]=
+u32 MCD_varTab2[]=
 {   /* Task 2 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -362,7 +362,7 @@ uint32_t MCD_varTab2[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab3[]=
+u32 MCD_varTab3[]=
 {   /* Task 3 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -398,7 +398,7 @@ uint32_t MCD_varTab3[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab4[]=
+u32 MCD_varTab4[]=
 {   /* Task 4 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -434,7 +434,7 @@ uint32_t MCD_varTab4[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab5[]=
+u32 MCD_varTab5[]=
 {   /* Task 5 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -470,7 +470,7 @@ uint32_t MCD_varTab5[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab6[]=
+u32 MCD_varTab6[]=
 {   /* Task 6 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -506,7 +506,7 @@ uint32_t MCD_varTab6[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab7[]=
+u32 MCD_varTab7[]=
 {   /* Task 7 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -542,7 +542,7 @@ uint32_t MCD_varTab7[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab8[]=
+u32 MCD_varTab8[]=
 {   /* Task 8 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -578,7 +578,7 @@ uint32_t MCD_varTab8[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab9[]=
+u32 MCD_varTab9[]=
 {   /* Task 9 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -614,7 +614,7 @@ uint32_t MCD_varTab9[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab10[]=
+u32 MCD_varTab10[]=
 {   /* Task 10 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -650,7 +650,7 @@ uint32_t MCD_varTab10[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab11[]=
+u32 MCD_varTab11[]=
 {   /* Task 11 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -686,7 +686,7 @@ uint32_t MCD_varTab11[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab12[]=
+u32 MCD_varTab12[]=
 {   /* Task 12 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -722,7 +722,7 @@ uint32_t MCD_varTab12[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab13[]=
+u32 MCD_varTab13[]=
 {   /* Task 13 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -758,7 +758,7 @@ uint32_t MCD_varTab13[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab14[]=
+u32 MCD_varTab14[]=
 {   /* Task 14 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -794,7 +794,7 @@ uint32_t MCD_varTab14[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_varTab15[]=
+u32 MCD_varTab15[]=
 {   /* Task 15 Variable Table */
     0x00000000, /* var[0] */
     0x00000000, /* var[1] */
@@ -830,7 +830,7 @@ uint32_t MCD_varTab15[]=
     0x00000000, /* inc[7] */
 };
 
-uint32_t MCD_funcDescTab0[]=
+u32 MCD_funcDescTab0[]=
 {   /* Task 0 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -899,7 +899,7 @@ uint32_t MCD_funcDescTab0[]=
 };
 
 #ifdef MCD_INCLUDE_EU
-uint32_t MCD_funcDescTab1[]=
+u32 MCD_funcDescTab1[]=
 {   /* Task 1 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -967,7 +967,7 @@ uint32_t MCD_funcDescTab1[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab2[]=
+u32 MCD_funcDescTab2[]=
 {   /* Task 2 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1035,7 +1035,7 @@ uint32_t MCD_funcDescTab2[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab3[]=
+u32 MCD_funcDescTab3[]=
 {   /* Task 3 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1103,7 +1103,7 @@ uint32_t MCD_funcDescTab3[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab4[]=
+u32 MCD_funcDescTab4[]=
 {   /* Task 4 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1171,7 +1171,7 @@ uint32_t MCD_funcDescTab4[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab5[]=
+u32 MCD_funcDescTab5[]=
 {   /* Task 5 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1239,7 +1239,7 @@ uint32_t MCD_funcDescTab5[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab6[]=
+u32 MCD_funcDescTab6[]=
 {   /* Task 6 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1307,7 +1307,7 @@ uint32_t MCD_funcDescTab6[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab7[]=
+u32 MCD_funcDescTab7[]=
 {   /* Task 7 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1375,7 +1375,7 @@ uint32_t MCD_funcDescTab7[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab8[]=
+u32 MCD_funcDescTab8[]=
 {   /* Task 8 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1443,7 +1443,7 @@ uint32_t MCD_funcDescTab8[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab9[]=
+u32 MCD_funcDescTab9[]=
 {   /* Task 9 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1511,7 +1511,7 @@ uint32_t MCD_funcDescTab9[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab10[]=
+u32 MCD_funcDescTab10[]=
 {   /* Task 10 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1579,7 +1579,7 @@ uint32_t MCD_funcDescTab10[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab11[]=
+u32 MCD_funcDescTab11[]=
 {   /* Task 11 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1647,7 +1647,7 @@ uint32_t MCD_funcDescTab11[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab12[]=
+u32 MCD_funcDescTab12[]=
 {   /* Task 12 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1715,7 +1715,7 @@ uint32_t MCD_funcDescTab12[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab13[]=
+u32 MCD_funcDescTab13[]=
 {   /* Task 13 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1783,7 +1783,7 @@ uint32_t MCD_funcDescTab13[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab14[]=
+u32 MCD_funcDescTab14[]=
 {   /* Task 14 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1851,7 +1851,7 @@ uint32_t MCD_funcDescTab14[]=
     0x202f2000, /* andCrcRestartBit(), EU# 3 */
 };
 
-uint32_t MCD_funcDescTab15[]=
+u32 MCD_funcDescTab15[]=
 {   /* Task 15 Function Descriptor Table */
     0x00000000,
     0x00000000,
@@ -1920,45 +1920,45 @@ uint32_t MCD_funcDescTab15[]=
 };
 #endif /*MCD_INCLUDE_EU*/
 
-uint32_t MCD_contextSave0[128];  /* Task 0 context save space */
-uint32_t MCD_contextSave1[128];  /* Task 1 context save space */
-uint32_t MCD_contextSave2[128];  /* Task 2 context save space */
-uint32_t MCD_contextSave3[128];  /* Task 3 context save space */
-uint32_t MCD_contextSave4[128];  /* Task 4 context save space */
-uint32_t MCD_contextSave5[128];  /* Task 5 context save space */
-uint32_t MCD_contextSave6[128];  /* Task 6 context save space */
-uint32_t MCD_contextSave7[128];  /* Task 7 context save space */
-uint32_t MCD_contextSave8[128];  /* Task 8 context save space */
-uint32_t MCD_contextSave9[128];  /* Task 9 context save space */
-uint32_t MCD_contextSave10[128]; /* Task 10 context save space */
-uint32_t MCD_contextSave11[128]; /* Task 11 context save space */
-uint32_t MCD_contextSave12[128]; /* Task 12 context save space */
-uint32_t MCD_contextSave13[128]; /* Task 13 context save space */
-uint32_t MCD_contextSave14[128]; /* Task 14 context save space */
-uint32_t MCD_contextSave15[128]; /* Task 15 context save space */
+u32 MCD_contextSave0[128];  /* Task 0 context save space */
+u32 MCD_contextSave1[128];  /* Task 1 context save space */
+u32 MCD_contextSave2[128];  /* Task 2 context save space */
+u32 MCD_contextSave3[128];  /* Task 3 context save space */
+u32 MCD_contextSave4[128];  /* Task 4 context save space */
+u32 MCD_contextSave5[128];  /* Task 5 context save space */
+u32 MCD_contextSave6[128];  /* Task 6 context save space */
+u32 MCD_contextSave7[128];  /* Task 7 context save space */
+u32 MCD_contextSave8[128];  /* Task 8 context save space */
+u32 MCD_contextSave9[128];  /* Task 9 context save space */
+u32 MCD_contextSave10[128]; /* Task 10 context save space */
+u32 MCD_contextSave11[128]; /* Task 11 context save space */
+u32 MCD_contextSave12[128]; /* Task 12 context save space */
+u32 MCD_contextSave13[128]; /* Task 13 context save space */
+u32 MCD_contextSave14[128]; /* Task 14 context save space */
+u32 MCD_contextSave15[128]; /* Task 15 context save space */
 
 
-uint32_t MCD_ChainNoEu_TDT[];
-uint32_t MCD_SingleNoEu_TDT[];
+u32 MCD_ChainNoEu_TDT[];
+u32 MCD_SingleNoEu_TDT[];
 #ifdef MCD_INCLUDE_EU
-uint32_t MCD_ChainEu_TDT[];
-uint32_t MCD_SingleEu_TDT[];
+u32 MCD_ChainEu_TDT[];
+u32 MCD_SingleEu_TDT[];
 #endif
-uint32_t MCD_ENetRcv_TDT[];
-uint32_t MCD_ENetXmit_TDT[];
+u32 MCD_ENetRcv_TDT[];
+u32 MCD_ENetXmit_TDT[];
 
-uint32_t MCD_modelTaskTableSrc[]=
+u32 MCD_modelTaskTableSrc[]=
 {
-    (uint32_t)MCD_ChainNoEu_TDT,
-    (uint32_t)&((uint8_t*)MCD_ChainNoEu_TDT)[0x0000016c],
+    (u32)MCD_ChainNoEu_TDT,
+    (u32)&((u8*)MCD_ChainNoEu_TDT)[0x0000016c],
     0x00000000,
     0x00000000,
     0x00000000,
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_SingleNoEu_TDT,
-    (uint32_t)&((uint8_t*)MCD_SingleNoEu_TDT)[0x000000d4],
+    (u32)MCD_SingleNoEu_TDT,
+    (u32)&((u8*)MCD_SingleNoEu_TDT)[0x000000d4],
     0x00000000,
     0x00000000,
     0x00000000,
@@ -1966,16 +1966,16 @@ uint32_t MCD_modelTaskTableSrc[]=
     0x00000000,
     0x00000000,
 #ifdef MCD_INCLUDE_EU
-    (uint32_t)MCD_ChainEu_TDT,
-    (uint32_t)&((uint8_t*)MCD_ChainEu_TDT)[0x000001b4],
+    (u32)MCD_ChainEu_TDT,
+    (u32)&((u8*)MCD_ChainEu_TDT)[0x000001b4],
     0x00000000,
     0x00000000,
     0x00000000,
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_SingleEu_TDT,
-    (uint32_t)&((uint8_t*)MCD_SingleEu_TDT)[0x00000124],
+    (u32)MCD_SingleEu_TDT,
+    (u32)&((u8*)MCD_SingleEu_TDT)[0x00000124],
     0x00000000,
     0x00000000,
     0x00000000,
@@ -1983,16 +1983,16 @@ uint32_t MCD_modelTaskTableSrc[]=
     0x00000000,
     0x00000000,
 #endif    
-    (uint32_t)MCD_ENetRcv_TDT,
-    (uint32_t)&((uint8_t*)MCD_ENetRcv_TDT)[0x0000009c],
+    (u32)MCD_ENetRcv_TDT,
+    (u32)&((u8*)MCD_ENetRcv_TDT)[0x0000009c],
     0x00000000,
     0x00000000,
     0x00000000,
     0x00000000,
     0x00000000,
     0x00000000,
-    (uint32_t)MCD_ENetXmit_TDT,
-    (uint32_t)&((uint8_t*)MCD_ENetXmit_TDT)[0x000000d0],
+    (u32)MCD_ENetXmit_TDT,
+    (u32)&((u8*)MCD_ENetXmit_TDT)[0x000000d0],
     0x00000000,
     0x00000000,
     0x00000000,
@@ -2000,7 +2000,7 @@ uint32_t MCD_modelTaskTableSrc[]=
     0x00000000,
     0x00000000,
 };
-uint32_t MCD_ChainNoEu_TDT[]=
+u32 MCD_ChainNoEu_TDT[]=
 {
     0x80004000, /* 0000(:370):  LCDEXT: idx0 = 0x00000000; ; */
     0x8118801b, /* 0004(:370):  LCD: idx1 = var2; idx1 once var0; idx1 += inc3 */
@@ -2095,7 +2095,7 @@ uint32_t MCD_ChainNoEu_TDT[]=
     0x000001f8, /* 0168(:0):      NOP */
     0x000001f8, /* 016C(:0):    NOP */
 };
-uint32_t MCD_SingleNoEu_TDT[]=
+u32 MCD_SingleNoEu_TDT[]=
 {
     0x8198001b, /* 0000(:657):  LCD: idx0 = var3; idx0 once var0; idx0 += inc3 */
     0x7000000d, /* 0004(:658):    DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */
@@ -2153,7 +2153,7 @@ uint32_t MCD_SingleNoEu_TDT[]=
     0x040001f8, /* 00D4(:713):    DRD1A: FN=0 INT init=0 WS=0 RS=0 */
 };
 #ifdef MCD_INCLUDE_EU
-uint32_t MCD_ChainEu_TDT[]=
+u32 MCD_ChainEu_TDT[]=
 {
     0x80004000, /* 0000(:947):  LCDEXT: idx0 = 0x00000000; ; */
     0x8198801b, /* 0004(:947):  LCD: idx1 = var3; idx1 once var0; idx1 += inc3 */
@@ -2266,7 +2266,7 @@ uint32_t MCD_ChainEu_TDT[]=
     0x000001f8, /* 01B0(:0):      NOP */
     0x000001f8, /* 01B4(:0):    NOP */
 };
-uint32_t MCD_SingleEu_TDT[]=
+u32 MCD_SingleEu_TDT[]=
 {
     0x8218001b, /* 0000(:1248):  LCD: idx0 = var4; idx0 once var0; idx0 += inc3 */
     0x7000000d, /* 0004(:1249):    DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */
@@ -2344,7 +2344,7 @@ uint32_t MCD_SingleEu_TDT[]=
     0x040001f8, /* 0124(:1316):    DRD1A: FN=0 INT init=0 WS=0 RS=0 */
 };
 #endif
-uint32_t MCD_ENetRcv_TDT[]=
+u32 MCD_ENetRcv_TDT[]=
 {
     0x80004000, /* 0000(:1389):  LCDEXT: idx0 = 0x00000000; ; */
     0x81988000, /* 0004(:1389):  LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
@@ -2387,7 +2387,7 @@ uint32_t MCD_ENetRcv_TDT[]=
     0x040001f8, /* 0098(:1441):      DRD1A: FN=0 INT init=0 WS=0 RS=0 */
     0x000001f8, /* 009C(:0):    NOP */
 };
-uint32_t MCD_ENetXmit_TDT[]=
+u32 MCD_ENetXmit_TDT[]=
 {
     0x80004000, /* 0000(:1516):  LCDEXT: idx0 = 0x00000000; ; */
     0x81988000, /* 0004(:1516):  LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */

dma/MCD_tasksInit.c

@@ -11,7 +11,6 @@
  */
 
 #include "MCD_dma.h"
-#include "MCD_tasksInit.h"
 
 extern dmaRegs *MCD_dmaBar;
 
@@ -23,33 +22,33 @@ extern dmaRegs *MCD_dmaBar;
 void  MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
 {
 
-    MCD_SET_VAR(taskTable+channel, 2, (uint32_t)currBD); /* var[2] */
-    MCD_SET_VAR(taskTable+channel, 25, (uint32_t)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
-    MCD_SET_VAR(taskTable+channel, 24, (uint32_t)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
-    MCD_SET_VAR(taskTable+channel, 11, (uint32_t)xferSize);  /* var[11] */
-    MCD_SET_VAR(taskTable+channel, 26, (uint32_t)(0x2000 << 16) | (0xffff & xferSizeIncr));  /* inc[2] */
-    MCD_SET_VAR(taskTable+channel, 0, (uint32_t)cSave);  /* var[0] */
-    MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */
-    MCD_SET_VAR(taskTable+channel, 3, (uint32_t)0x00000000); /* var[3] */
-    MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */
-    MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */
-    MCD_SET_VAR(taskTable+channel, 6, (uint32_t)0x00000000); /* var[6] */
-    MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */
-    MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */
-    MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000000); /* var[9] */
-    MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x00000000);    /* var[10] */
-    MCD_SET_VAR(taskTable+channel, 12, (uint32_t)0x00000000);    /* var[12] */
-    MCD_SET_VAR(taskTable+channel, 13, (uint32_t)0x80000000);    /* var[13] */
-    MCD_SET_VAR(taskTable+channel, 14, (uint32_t)0x00000010);    /* var[14] */
-    MCD_SET_VAR(taskTable+channel, 15, (uint32_t)0x00000004);    /* var[15] */
-    MCD_SET_VAR(taskTable+channel, 16, (uint32_t)0x08000000);    /* var[16] */
-    MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x00000000);    /* inc[3] */
-    MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0x80000000);    /* inc[4] */
-    MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0x80000001);    /* inc[5] */
-    MCD_SET_VAR(taskTable+channel, 30, (uint32_t)0x40000000);    /* inc[6] */
+    MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
+    MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
+    MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
+    MCD_SET_VAR(taskTable+channel, 11, (u32)xferSize);  /* var[11] */
+    MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr));  /* inc[2] */
+    MCD_SET_VAR(taskTable+channel, 0, (u32)cSave);  /* var[0] */
+    MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
+    MCD_SET_VAR(taskTable+channel, 3, (u32)0x00000000); /* var[3] */
+    MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
+    MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
+    MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
+    MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
+    MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
+    MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
+    MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000);    /* var[10] */
+    MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000);    /* var[12] */
+    MCD_SET_VAR(taskTable+channel, 13, (u32)0x80000000);    /* var[13] */
+    MCD_SET_VAR(taskTable+channel, 14, (u32)0x00000010);    /* var[14] */
+    MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004);    /* var[15] */
+    MCD_SET_VAR(taskTable+channel, 16, (u32)0x08000000);    /* var[16] */
+    MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000);    /* inc[3] */
+    MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000);    /* inc[4] */
+    MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000001);    /* inc[5] */
+    MCD_SET_VAR(taskTable+channel, 30, (u32)0x40000000);    /* inc[6] */
 
     /* Set the task's Enable bit in its Task Control Register */
-    MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000;
+    MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
 }
 
 
@@ -57,29 +56,29 @@ void  MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xfer
  * Task 1
  */
  
-void  MCD_startDmaSingleNoEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
+void  MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
 {
 
-    MCD_SET_VAR(taskTable+channel, 7, (uint32_t)srcAddr);    /* var[7] */
-    MCD_SET_VAR(taskTable+channel, 25, (uint32_t)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
-    MCD_SET_VAR(taskTable+channel, 2, (uint32_t)destAddr);   /* var[2] */
-    MCD_SET_VAR(taskTable+channel, 24, (uint32_t)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
-    MCD_SET_VAR(taskTable+channel, 3, (uint32_t)dmaSize);    /* var[3] */
-    MCD_SET_VAR(taskTable+channel, 26, (uint32_t)(0x2000 << 16) | (0xffff & xferSizeIncr));  /* inc[2] */
-    MCD_SET_VAR(taskTable+channel, 5, (uint32_t)flags);  /* var[5] */
-    MCD_SET_VAR(taskTable+channel, 1, (uint32_t)currBD); /* var[1] */
-    MCD_SET_VAR(taskTable+channel, 0, (uint32_t)cSave);  /* var[0] */
-    MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */
-    MCD_SET_VAR(taskTable+channel, 6, (uint32_t)0x00000000); /* var[6] */
-    MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */
-    MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000004); /* var[9] */
-    MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x08000000);    /* var[10] */
-    MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x00000000);    /* inc[3] */
-    MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0x80000001);    /* inc[4] */
-    MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0x40000000);    /* inc[5] */
+    MCD_SET_VAR(taskTable+channel, 7, (u32)srcAddr);    /* var[7] */
+    MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
+    MCD_SET_VAR(taskTable+channel, 2, (u32)destAddr);   /* var[2] */
+    MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
+    MCD_SET_VAR(taskTable+channel, 3, (u32)dmaSize);    /* var[3] */
+    MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr));  /* inc[2] */
+    MCD_SET_VAR(taskTable+channel, 5, (u32)flags);  /* var[5] */
+    MCD_SET_VAR(taskTable+channel, 1, (u32)currBD); /* var[1] */
+    MCD_SET_VAR(taskTable+channel, 0, (u32)cSave);  /* var[0] */
+    MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
+    MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
+    MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
+    MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000004); /* var[9] */
+    MCD_SET_VAR(taskTable+channel, 10, (u32)0x08000000);    /* var[10] */
+    MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000);    /* inc[3] */
+    MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000001);    /* inc[4] */
+    MCD_SET_VAR(taskTable+channel, 29, (u32)0x40000000);    /* inc[5] */
 
     /* Set the task's Enable bit in its Task Control Register */
-    MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000;
+    MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
 }
 
 
@@ -90,36 +89,36 @@ void  MCD_startDmaSingleNoEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, s
 void  MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
 {
 
-    MCD_SET_VAR(taskTable+channel, 3, (uint32_t)currBD); /* var[3] */
-    MCD_SET_VAR(taskTable+channel, 25, (uint32_t)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
-    MCD_SET_VAR(taskTable+channel, 24, (uint32_t)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
-    MCD_SET_VAR(taskTable+channel, 12, (uint32_t)xferSize);  /* var[12] */
-    MCD_SET_VAR(taskTable+channel, 26, (uint32_t)(0x2000 << 16) | (0xffff & xferSizeIncr));  /* inc[2] */
-    MCD_SET_VAR(taskTable+channel, 0, (uint32_t)cSave);  /* var[0] */
-    MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */
-    MCD_SET_VAR(taskTable+channel, 2, (uint32_t)0x00000000); /* var[2] */
-    MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */
-    MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */
-    MCD_SET_VAR(taskTable+channel, 6, (uint32_t)0x00000000); /* var[6] */
-    MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */
-    MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */
-    MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000000); /* var[9] */
-    MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x00000000);    /* var[10] */
-    MCD_SET_VAR(taskTable+channel, 11, (uint32_t)0x00000000);    /* var[11] */
-    MCD_SET_VAR(taskTable+channel, 13, (uint32_t)0x00000000);    /* var[13] */
-    MCD_SET_VAR(taskTable+channel, 14, (uint32_t)0x80000000);    /* var[14] */
-    MCD_SET_VAR(taskTable+channel, 15, (uint32_t)0x00000010);    /* var[15] */
-    MCD_SET_VAR(taskTable+channel, 16, (uint32_t)0x00000001);    /* var[16] */
-    MCD_SET_VAR(taskTable+channel, 17, (uint32_t)0x00000004);    /* var[17] */
-    MCD_SET_VAR(taskTable+channel, 18, (uint32_t)0x08000000);    /* var[18] */
-    MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x00000000);    /* inc[3] */
-    MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0x80000000);    /* inc[4] */
-    MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0xc0000000);    /* inc[5] */
-    MCD_SET_VAR(taskTable+channel, 30, (uint32_t)0x80000001);    /* inc[6] */
-    MCD_SET_VAR(taskTable+channel, 31, (uint32_t)0x40000000);    /* inc[7] */
+    MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
+    MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
+    MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
+    MCD_SET_VAR(taskTable+channel, 12, (u32)xferSize);  /* var[12] */
+    MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr));  /* inc[2] */
+    MCD_SET_VAR(taskTable+channel, 0, (u32)cSave);  /* var[0] */
+    MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
+    MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
+    MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
+    MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
+    MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
+    MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
+    MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
+    MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
+    MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000);    /* var[10] */
+    MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000000);    /* var[11] */
+    MCD_SET_VAR(taskTable+channel, 13, (u32)0x00000000);    /* var[13] */
+    MCD_SET_VAR(taskTable+channel, 14, (u32)0x80000000);    /* var[14] */
+    MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000010);    /* var[15] */
+    MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000001);    /* var[16] */
+    MCD_SET_VAR(taskTable+channel, 17, (u32)0x00000004);    /* var[17] */
+    MCD_SET_VAR(taskTable+channel, 18, (u32)0x08000000);    /* var[18] */
+    MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000);    /* inc[3] */
+    MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000);    /* inc[4] */
+    MCD_SET_VAR(taskTable+channel, 29, (u32)0xc0000000);    /* inc[5] */
+    MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001);    /* inc[6] */
+    MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000);    /* inc[7] */
 
     /* Set the task's Enable bit in its Task Control Register */
-    MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000;
+    MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
 }
 
 
@@ -127,33 +126,33 @@ void  MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSi
  * Task 3
  */
  
-void  MCD_startDmaSingleEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
+void  MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
 {
 
-    MCD_SET_VAR(taskTable+channel, 8, (uint32_t)srcAddr);    /* var[8] */
-    MCD_SET_VAR(taskTable+channel, 25, (uint32_t)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
-    MCD_SET_VAR(taskTable+channel, 3, (uint32_t)destAddr);   /* var[3] */
-    MCD_SET_VAR(taskTable+channel, 24, (uint32_t)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
-    MCD_SET_VAR(taskTable+channel, 4, (uint32_t)dmaSize);    /* var[4] */
-    MCD_SET_VAR(taskTable+channel, 26, (uint32_t)(0x2000 << 16) | (0xffff & xferSizeIncr));  /* inc[2] */
-    MCD_SET_VAR(taskTable+channel, 6, (uint32_t)flags);  /* var[6] */
-    MCD_SET_VAR(taskTable+channel, 2, (uint32_t)currBD); /* var[2] */
-    MCD_SET_VAR(taskTable+channel, 0, (uint32_t)cSave);  /* var[0] */
-    MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */
-    MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */
-    MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */
-    MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000000); /* var[9] */
-    MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x00000001);    /* var[10] */
-    MCD_SET_VAR(taskTable+channel, 11, (uint32_t)0x00000004);    /* var[11] */
-    MCD_SET_VAR(taskTable+channel, 12, (uint32_t)0x08000000);    /* var[12] */
-    MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x00000000);    /* inc[3] */
-    MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0xc0000000);    /* inc[4] */
-    MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0x80000000);    /* inc[5] */
-    MCD_SET_VAR(taskTable+channel, 30, (uint32_t)0x80000001);    /* inc[6] */
-    MCD_SET_VAR(taskTable+channel, 31, (uint32_t)0x40000000);    /* inc[7] */
+    MCD_SET_VAR(taskTable+channel, 8, (u32)srcAddr);    /* var[8] */
+    MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
+    MCD_SET_VAR(taskTable+channel, 3, (u32)destAddr);   /* var[3] */
+    MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
+    MCD_SET_VAR(taskTable+channel, 4, (u32)dmaSize);    /* var[4] */
+    MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr));  /* inc[2] */
+    MCD_SET_VAR(taskTable+channel, 6, (u32)flags);  /* var[6] */
+    MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
+    MCD_SET_VAR(taskTable+channel, 0, (u32)cSave);  /* var[0] */
+    MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
+    MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
+    MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
+    MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
+    MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000001);    /* var[10] */
+    MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000004);    /* var[11] */
+    MCD_SET_VAR(taskTable+channel, 12, (u32)0x08000000);    /* var[12] */
+    MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000);    /* inc[3] */
+    MCD_SET_VAR(taskTable+channel, 28, (u32)0xc0000000);    /* inc[4] */
+    MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000);    /* inc[5] */
+    MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001);    /* inc[6] */
+    MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000);    /* inc[7] */
 
     /* Set the task's Enable bit in its Task Control Register */
-    MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000;
+    MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
 }
 
 
@@ -161,29 +160,29 @@ void  MCD_startDmaSingleEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, sho
  * Task 4
  */
  
-void  MCD_startDmaENetRcv(int8_t *bDBase, int8_t *currBD, int8_t *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel)
+void  MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel)
 {
 
-    MCD_SET_VAR(taskTable+channel, 0, (uint32_t)bDBase); /* var[0] */
-    MCD_SET_VAR(taskTable+channel, 3, (uint32_t)currBD); /* var[3] */
-    MCD_SET_VAR(taskTable+channel, 6, (uint32_t)rcvFifoPtr); /* var[6] */
-    MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */
-    MCD_SET_VAR(taskTable+channel, 2, (uint32_t)0x00000000); /* var[2] */
-    MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */
-    MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */
-    MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */
-    MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */
-    MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x0000ffff); /* var[9] */
-    MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x30000000);    /* var[10] */
-    MCD_SET_VAR(taskTable+channel, 11, (uint32_t)0x0fffffff);    /* var[11] */
-    MCD_SET_VAR(taskTable+channel, 12, (uint32_t)0x00000008);    /* var[12] */
-    MCD_SET_VAR(taskTable+channel, 24, (uint32_t)0x00000000);    /* inc[0] */
-    MCD_SET_VAR(taskTable+channel, 25, (uint32_t)0x60000000);    /* inc[1] */
-    MCD_SET_VAR(taskTable+channel, 26, (uint32_t)0x20000004);    /* inc[2] */
-    MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x40000000);    /* inc[3] */
+    MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
+    MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
+    MCD_SET_VAR(taskTable+channel, 6, (u32)rcvFifoPtr); /* var[6] */
+    MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
+    MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
+    MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
+    MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
+    MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
+    MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
+    MCD_SET_VAR(taskTable+channel, 9, (u32)0x0000ffff); /* var[9] */
+    MCD_SET_VAR(taskTable+channel, 10, (u32)0x30000000);    /* var[10] */
+    MCD_SET_VAR(taskTable+channel, 11, (u32)0x0fffffff);    /* var[11] */
+    MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000008);    /* var[12] */
+    MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000);    /* inc[0] */
+    MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000);    /* inc[1] */
+    MCD_SET_VAR(taskTable+channel, 26, (u32)0x20000004);    /* inc[2] */
+    MCD_SET_VAR(taskTable+channel, 27, (u32)0x40000000);    /* inc[3] */
 
     /* Set the task's Enable bit in its Task Control Register */
-    MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000;
+    MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
 }
 
 
@@ -191,35 +190,35 @@ void  MCD_startDmaENetRcv(int8_t *bDBase, int8_t *currBD, int8_t *rcvFifoPtr, vo
  * Task 5
  */
  
-void  MCD_startDmaENetXmit(int8_t *bDBase, int8_t *currBD, int8_t *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel)
+void  MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel)
 {
 
-    MCD_SET_VAR(taskTable+channel, 0, (uint32_t)bDBase); /* var[0] */
-    MCD_SET_VAR(taskTable+channel, 3, (uint32_t)currBD); /* var[3] */
-    MCD_SET_VAR(taskTable+channel, 11, (uint32_t)xmitFifoPtr);   /* var[11] */
-    MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */
-    MCD_SET_VAR(taskTable+channel, 2, (uint32_t)0x00000000); /* var[2] */
-    MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */
-    MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */
-    MCD_SET_VAR(taskTable+channel, 6, (uint32_t)0x00000000); /* var[6] */
-    MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */
-    MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */
-    MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000000); /* var[9] */
-    MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x00000000);    /* var[10] */
-    MCD_SET_VAR(taskTable+channel, 12, (uint32_t)0x00000000);    /* var[12] */
-    MCD_SET_VAR(taskTable+channel, 13, (uint32_t)0x0000ffff);    /* var[13] */
-    MCD_SET_VAR(taskTable+channel, 14, (uint32_t)0xffffffff);    /* var[14] */
-    MCD_SET_VAR(taskTable+channel, 15, (uint32_t)0x00000004);    /* var[15] */
-    MCD_SET_VAR(taskTable+channel, 16, (uint32_t)0x00000008);    /* var[16] */
-    MCD_SET_VAR(taskTable+channel, 24, (uint32_t)0x00000000);    /* inc[0] */
-    MCD_SET_VAR(taskTable+channel, 25, (uint32_t)0x60000000);    /* inc[1] */
-    MCD_SET_VAR(taskTable+channel, 26, (uint32_t)0x40000000);    /* inc[2] */
-    MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0xc000fffc);    /* inc[3] */
-    MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0xe0000004);    /* inc[4] */
-    MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0x80000000);    /* inc[5] */
-    MCD_SET_VAR(taskTable+channel, 30, (uint32_t)0x4000ffff);    /* inc[6] */
-    MCD_SET_VAR(taskTable+channel, 31, (uint32_t)0xe0000001);    /* inc[7] */
+    MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
+    MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
+    MCD_SET_VAR(taskTable+channel, 11, (u32)xmitFifoPtr);   /* var[11] */
+    MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
+    MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
+    MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
+    MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
+    MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
+    MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
+    MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
+    MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
+    MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000);    /* var[10] */
+    MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000);    /* var[12] */
+    MCD_SET_VAR(taskTable+channel, 13, (u32)0x0000ffff);    /* var[13] */
+    MCD_SET_VAR(taskTable+channel, 14, (u32)0xffffffff);    /* var[14] */
+    MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004);    /* var[15] */
+    MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000008);    /* var[16] */
+    MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000);    /* inc[0] */
+    MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000);    /* inc[1] */
+    MCD_SET_VAR(taskTable+channel, 26, (u32)0x40000000);    /* inc[2] */
+    MCD_SET_VAR(taskTable+channel, 27, (u32)0xc000fffc);    /* inc[3] */
+    MCD_SET_VAR(taskTable+channel, 28, (u32)0xe0000004);    /* inc[4] */
+    MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000);    /* inc[5] */
+    MCD_SET_VAR(taskTable+channel, 30, (u32)0x4000ffff);    /* inc[6] */
+    MCD_SET_VAR(taskTable+channel, 31, (u32)0xe0000001);    /* inc[7] */
 
     /* Set the task's Enable bit in its Task Control Register */
-    MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000;
+    MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
 }

flash_scripts/flash_m548x_etos.bdm

@@ -63,4 +63,4 @@ erase 0xe0000000 37
 erase 0xe0000000 38
 erase 0xe0000000 39
 
-load ../../emutos/emutos-m548x_bas.elf
+load ../../emutos/emutos-m548x-bas_gcc.elf

i2c/i2c.c

@@ -0,0 +1,41 @@
+
+#include <bas_types.h>
+
+void i2c_init(void)
+{
+
+}
+
+void i2c_set_frequency(int hz)
+{
+}
+
+int i2c_read(int address, char *data, int length, bool repeated)
+{
+    return 0;
+}
+
+int i2c_read_byte(int ack)
+{
+    return 0;
+}
+
+int i2c_write(int address, const char *data, int length, bool repeated)
+{
+    return 0;
+}
+
+int i2c_write_byte(int data)
+{
+    return 0;
+}
+
+void i2c_start(void)
+{
+
+}
+
+void i2c_stop(void)
+{
+
+}

if/driver_vec.c

@@ -30,13 +30,14 @@
 #include "driver_vec.h"
 #include "driver_mem.h"
 #include "pci.h"
+#include "mmu.h"
 
 /*
  * driver interface struct for the SD card BaS driver
  */
 static struct xhdi_driver_interface xhdi_call_interface =
 {
-	xhdi_call
+    xhdi_call
 };
 
 /*
@@ -46,27 +47,27 @@ static struct xhdi_driver_interface xhdi_call_interface =
  */
 static struct dma_driver_interface dma_interface =
 {
-	.version = 0x0101,
-	.magic = 0x444d4143, 						/* 'DMAC' */
-	.dma_set_initiator = dma_set_initiator,
-	.dma_get_initiator = dma_get_initiator,
-	.dma_free_initiator = dma_free_initiator,
-	.dma_set_channel = dma_set_channel,
-	.dma_get_channel = dma_get_channel,
-	.dma_free_channel = dma_free_channel,
-	.dma_clear_channel = dma_clear_channel,
-	.MCD_startDma = (int (*)(long, int8_t *, unsigned int, int8_t *, unsigned int,
-					unsigned int, unsigned int, unsigned int, int,
-					unsigned int, unsigned int)) MCD_startDma,
-	.MCD_dmaStatus = (int32_t (*)(int32_t)) MCD_dmaStatus,
-	.MCD_XferProgrQuery = (int32_t (*)(int32_t, MCD_XferProg *)) MCD_XferProgrQuery,
-	.MCD_killDma = (int32_t (*)(int32_t)) MCD_killDma,
-	.MCD_continDma = (int32_t (*)(int32_t)) MCD_continDma,
-	.MCD_pauseDma = (int32_t (*)(int32_t)) MCD_pauseDma,
-	.MCD_resumeDma = (int32_t (*)(int32_t)) MCD_resumeDma,
-	.MCD_csumQuery = (int32_t (*)(int32_t, uint32_t *)) MCD_csumQuery,
-	.dma_malloc = driver_mem_alloc,
-	.dma_free = driver_mem_free
+    .version = 0x0101,
+    .magic = 0x444d4143, 						/* 'DMAC' */
+    .dma_set_initiator = dma_set_initiator,
+    .dma_get_initiator = dma_get_initiator,
+    .dma_free_initiator = dma_free_initiator,
+    .dma_set_channel = dma_set_channel,
+    .dma_get_channel = dma_get_channel,
+    .dma_free_channel = dma_free_channel,
+    .dma_clear_channel = dma_clear_channel,
+    .MCD_startDma = (int (*)(long, int8_t *, unsigned int, int8_t *, unsigned int,
+                    unsigned int, unsigned int, unsigned int, int,
+                    unsigned int, unsigned int)) MCD_startDma,
+    .MCD_dmaStatus = (int32_t (*)(int32_t)) MCD_dmaStatus,
+    .MCD_XferProgrQuery = (int32_t (*)(int32_t, MCD_XferProg *)) MCD_XferProgrQuery,
+    .MCD_killDma = (int32_t (*)(int32_t)) MCD_killDma,
+    .MCD_continDma = (int32_t (*)(int32_t)) MCD_continDma,
+    .MCD_pauseDma = (int32_t (*)(int32_t)) MCD_pauseDma,
+    .MCD_resumeDma = (int32_t (*)(int32_t)) MCD_resumeDma,
+    .MCD_csumQuery = (int32_t (*)(int32_t, uint32_t *)) MCD_csumQuery,
+    .dma_malloc = driver_mem_alloc,
+    .dma_free = driver_mem_free
 };
 
 extern struct fb_info *info_fb;
@@ -76,51 +77,51 @@ extern struct fb_info *info_fb;
  */
 static struct pci_bios_interface pci_interface =
 {
-	.subjar = 0,
-	.version = 0x00010000,
-	.find_pci_device = wrapper_find_pci_device,
-	.find_pci_classcode = wrapper_find_pci_classcode,
-	.read_config_byte = wrapper_read_config_byte,
-	.read_config_word = wrapper_read_config_word,
-	.read_config_longword = wrapper_read_config_longword,
-	.fast_read_config_byte = wrapper_fast_read_config_byte,
-	.fast_read_config_word = wrapper_fast_read_config_word,
-	.fast_read_config_longword = wrapper_fast_read_config_longword,
-	.write_config_byte = wrapper_write_config_byte,
-	.write_config_word = wrapper_write_config_word,
-	.write_config_longword = wrapper_write_config_longword,
-	.hook_interrupt = wrapper_hook_interrupt,
-	.unhook_interrupt = wrapper_unhook_interrupt,
-	.special_cycle = wrapper_special_cycle,
-	.get_routing = wrapper_get_routing,
-	.set_interrupt = wrapper_set_interrupt,
-	.get_resource = wrapper_get_resource,
-	.get_card_used = wrapper_get_card_used,
-	.set_card_used = wrapper_set_card_used,
-	.read_mem_byte = wrapper_read_mem_byte,
-	.read_mem_word = wrapper_read_mem_word,
-	.read_mem_longword = wrapper_read_mem_longword,
-	.fast_read_mem_byte = wrapper_fast_read_mem_byte,
-	.fast_read_mem_word = wrapper_fast_read_mem_word,
-	.fast_read_mem_longword = wrapper_fast_read_mem_longword,
-	.write_mem_byte = wrapper_write_mem_byte,
-	.write_mem_word = wrapper_write_mem_word,
-	.write_mem_longword = wrapper_write_mem_longword,
-	.read_io_byte = wrapper_read_io_byte,
-	.read_io_word = wrapper_read_io_word,
-	.read_io_longword = wrapper_read_io_longword,
-	.fast_read_io_byte = wrapper_fast_read_io_byte,
-	.fast_read_io_word = wrapper_fast_read_io_word,
-	.fast_read_io_longword = wrapper_fast_read_io_longword,
-	.write_io_byte = wrapper_write_io_byte,
-	.write_io_word = wrapper_write_io_word,
-	.write_io_longword = wrapper_write_io_longword,
-	.get_machine_id = wrapper_get_machine_id,
-	.get_pagesize = wrapper_get_pagesize,
-	.virt_to_bus = wrapper_virt_to_bus,
-	.bus_to_virt = wrapper_bus_to_virt,
-	.virt_to_phys = wrapper_virt_to_phys,
-	.phys_to_virt = wrapper_phys_to_virt,
+    .subjar = 0,
+    .version = 0x00010000,
+    .find_pci_device = wrapper_find_pci_device,
+    .find_pci_classcode = wrapper_find_pci_classcode,
+    .read_config_byte = wrapper_read_config_byte,
+    .read_config_word = wrapper_read_config_word,
+    .read_config_longword = wrapper_read_config_longword,
+    .fast_read_config_byte = wrapper_fast_read_config_byte,
+    .fast_read_config_word = wrapper_fast_read_config_word,
+    .fast_read_config_longword = wrapper_fast_read_config_longword,
+    .write_config_byte = wrapper_write_config_byte,
+    .write_config_word = wrapper_write_config_word,
+    .write_config_longword = wrapper_write_config_longword,
+    .hook_interrupt = wrapper_hook_interrupt,
+    .unhook_interrupt = wrapper_unhook_interrupt,
+    .special_cycle = wrapper_special_cycle,
+    .get_routing = wrapper_get_routing,
+    .set_interrupt = wrapper_set_interrupt,
+    .get_resource = wrapper_get_resource,
+    .get_card_used = wrapper_get_card_used,
+    .set_card_used = wrapper_set_card_used,
+    .read_mem_byte = wrapper_read_mem_byte,
+    .read_mem_word = wrapper_read_mem_word,
+    .read_mem_longword = wrapper_read_mem_longword,
+    .fast_read_mem_byte = wrapper_fast_read_mem_byte,
+    .fast_read_mem_word = wrapper_fast_read_mem_word,
+    .fast_read_mem_longword = wrapper_fast_read_mem_longword,
+    .write_mem_byte = wrapper_write_mem_byte,
+    .write_mem_word = wrapper_write_mem_word,
+    .write_mem_longword = wrapper_write_mem_longword,
+    .read_io_byte = wrapper_read_io_byte,
+    .read_io_word = wrapper_read_io_word,
+    .read_io_longword = wrapper_read_io_longword,
+    .fast_read_io_byte = wrapper_fast_read_io_byte,
+    .fast_read_io_word = wrapper_fast_read_io_word,
+    .fast_read_io_longword = wrapper_fast_read_io_longword,
+    .write_io_byte = wrapper_write_io_byte,
+    .write_io_word = wrapper_write_io_word,
+    .write_io_longword = wrapper_write_io_longword,
+    .get_machine_id = wrapper_get_machine_id,
+    .get_pagesize = wrapper_get_pagesize,
+    .virt_to_bus = wrapper_virt_to_bus,
+    .bus_to_virt = wrapper_bus_to_virt,
+    .virt_to_phys = wrapper_virt_to_phys,
+    .phys_to_virt = wrapper_phys_to_virt,
 };
 
 /*
@@ -128,69 +129,122 @@ static struct pci_bios_interface pci_interface =
  */
 static struct framebuffer_driver_interface framebuffer_interface =
 {
-	.framebuffer_info = &info_fb
+    .framebuffer_info = &info_fb
+};
+
+/*
+ * driver interface struct for the BaS MMU driver
+ */
+static struct mmu_driver_interface mmu_interface =
+{
+    .map_page_locked = &mmu_map_data_page_locked,
+    .unlock_page = &mmu_unlock_data_page,
+    .report_locked_pages = &mmu_report_locked_pages,
+    .report_pagesize = &mmu_report_pagesize
 };
 
 static struct generic_interface interfaces[] =
 {
-	{
-		/* BaS SD-card driver interface */
+    {
+        /* BaS SD-card driver interface */
 
-		.type = XHDI_DRIVER,
-		.name = "SDCARD",
-		.description = "BaS SD Card driver",
-		.version = 0,
-		.revision = 1,
-		.interface.xhdi = &xhdi_call_interface
-	},
-	{
-		.type = MCD_DRIVER,
-		.name = "MCDDMA",
-		.description = "BaS Multichannel DMA driver",
-		.version = 0,
-		.revision = 1,
-		.interface.dma = &dma_interface,
-	},
-	{
-		.type = VIDEO_DRIVER,
-		.name = "RADEON",
-		.description = "BaS RADEON framebuffer driver",
-		.version = 0,
-		.revision = 1,
-		.interface.fb = &framebuffer_interface,
-	},
-	{
-		.type = PCI_DRIVER,
-		.name = "PCI",
-		.description = "BaS PCI_BIOS driver",
-		.version = 0,
-		.revision = 1,
-		.interface.pci = &pci_interface,
-	},
-	/* insert new drivers here */
+        .type = XHDI_DRIVER,
+        .name = "SDCARD",
+        .description = "BaS SD Card driver",
+        .version = 0,
+        .revision = 1,
+        .interface.xhdi = &xhdi_call_interface
+    },
+    {
+        .type = MCD_DRIVER,
+        .name = "MCDDMA",
+        .description = "BaS Multichannel DMA driver",
+        .version = 0,
+        .revision = 1,
+        .interface.dma = &dma_interface,
+    },
+    {
+        .type = VIDEO_DRIVER,
+        .name = "RADEON",
+        .description = "BaS RADEON framebuffer driver",
+        .version = 0,
+        .revision = 1,
+        .interface.fb = &framebuffer_interface,
+    },
+    {
+        .type = PCI_DRIVER,
+        .name = "PCI",
+        .description = "BaS PCI_BIOS driver",
+        .version = 0,
+        .revision = 1,
+        .interface.pci = &pci_interface,
+    },
+    {
+        .type = MMU_DRIVER,
+        .name = "MMU",
+        .description = "BaS MMU driver",
+        .version = 0,
+        .revision = 1,
+        .interface.mmu = &mmu_interface,
+    },
+    /* insert new drivers here */
 
-	{
-		.type = END_OF_DRIVERS
-	}
+    {
+        .type = END_OF_DRIVERS
+    }
 };
 
+extern void remove_handler(void);   /* forward declaration */
+
 /*
  * this is the driver table we expose to the OS
  */
 static struct driver_table bas_drivers =
 {
-	.bas_version = MAJOR_VERSION,
-	.bas_revision = MINOR_VERSION,
-	.remove_handler = NULL,
-	.interfaces = interfaces
+    .bas_version = MAJOR_VERSION,
+    .bas_revision = MINOR_VERSION,
+    .remove_handler = remove_handler,
+    .interfaces = interfaces
 };
 
+void remove_handler(void)
+{
+    extern void std_exc_vec(void);
+    uint32_t *trap_0_vector = (uint32_t *) 0x80;
+
+    *trap_0_vector = (uint32_t) std_exc_vec;
+}
+
 void __attribute__((interrupt)) get_bas_drivers(void)
 {
-	__asm__ __volatile__(
-		"move.l	#%[drivers],d0\n\t"
-		:	                            /* no output */
-		:	[drivers] "o" (bas_drivers)		/* input */
-		:									/* clobber */
-	);
+    __asm__ __volatile(
+        /*
+         * sp should now point to the next instruction after the trap
+         * The trap itself is 2 bytes, the four bytes before that must
+         * read '_BAS' or we are not meant by this call
+         */
+        "		move.l	a0,-(sp)				\n\t"	// save registers
+        "       move.l  d0,-(sp)                \n\t"
+        "		move.l	12(sp),a0         		\n\t"	// get return address
+        "       move.l  -6(a0),d0               \n\t"   //
+        "		cmp.l	#0x5f424153,d0			\n\t"	// is it '_BAS'?
+        "		beq		fetch_drivers			\n\t"	// yes
+        /*
+         * This seems indeed a "normal" trap #0. Better pass control to "normal" trap #0 processing
+         * If trap #0 isn't set to something sensible, we'll probably crash here, but this must be
+         * prevented on the caller side.
+         */
+        "		move.l	(sp)+,d0				\n\t"	// restore registers
+        "		move.l	(sp)+,a0				\n\t"
+        "		move.l	0x80,-(sp)				\n\t"	// fetch vector
+        "		rts								\n\t"	// and jump through it
+
+        "fetch_drivers:							\n\t"
+        "		move.l	#%[drivers],d0			\n\t"	// return driver struct in d0
+        "		addq.l	#4,sp					\n\t"	// adjust stack
+        "       move.l  (sp)+,a0                \n\t"   // restore register
+        :	                            /* no output */
+        :	[drivers] "o" (bas_drivers)		/* input */
+        :									/* clobber */
+    );
 }

include/MCD_dma.h

@@ -7,14 +7,11 @@
 #ifndef _MCD_API_H
 #define _MCD_API_H
 
-#include "bas_types.h"
-
 /*
  * Turn Execution Unit tasks ON (#define) or OFF (#undef)
  */
 #undef MCD_INCLUDE_EU
 //#define MCD_INCLUDE_EU
-
 /*
  * Number of DMA channels
  */
@@ -49,33 +46,39 @@
 /*
  * Portability typedefs
  */
+typedef int s32;
+typedef unsigned int u32;
+typedef short s16;
+typedef unsigned short u16;
+typedef char s8;
+typedef unsigned char u8;
 
 /*
  * These structures represent the internal registers of the
  * multi-channel DMA
  */
 struct dmaRegs_s {
-   uint32_t taskbar;         /* task table base address register */
-   uint32_t currPtr;
-   uint32_t endPtr;
-   uint32_t varTablePtr;
-   uint16_t dma_rsvd0;
-   uint16_t ptdControl;      /* ptd control */
-   uint32_t intPending;      /* interrupt pending register */
-   uint32_t intMask;         /* interrupt mask register */
-   uint16_t taskControl[16]; /* task control registers */
-   uint8_t  priority[32];    /* priority registers */
-   uint32_t initiatorMux;    /* initiator mux control */
-   uint32_t taskSize0;       /* task size control register 0. */
-   uint32_t taskSize1;       /* task size control register 1. */
-   uint32_t dma_rsvd1;       /* reserved */
-   uint32_t dma_rsvd2;       /* reserved */
-   uint32_t debugComp1;      /* debug comparator 1 */
-   uint32_t debugComp2;      /* debug comparator 2 */
-   uint32_t debugControl;    /* debug control */
-   uint32_t debugStatus;     /* debug status */
-   uint32_t ptdDebug;        /* priority task decode debug */
-   uint32_t dma_rsvd3[31];   /* reserved */
+   u32 taskbar;         /* task table base address register */
+   u32 currPtr;
+   u32 endPtr;
+   u32 varTablePtr;
+   u16 dma_rsvd0;
+   u16 ptdControl;      /* ptd control */
+   u32 intPending;      /* interrupt pending register */
+   u32 intMask;         /* interrupt mask register */
+   u16 taskControl[16]; /* task control registers */
+   u8  priority[32];    /* priority registers */
+   u32 initiatorMux;    /* initiator mux control */
+   u32 taskSize0;       /* task size control register 0. */
+   u32 taskSize1;       /* task size control register 1. */
+   u32 dma_rsvd1;       /* reserved */
+   u32 dma_rsvd2;       /* reserved */
+   u32 debugComp1;      /* debug comparator 1 */
+   u32 debugComp2;      /* debug comparator 2 */
+   u32 debugControl;    /* debug control */
+   u32 debugStatus;     /* debug status */
+   u32 ptdDebug;        /* priority task decode debug */
+   u32 dma_rsvd3[31];   /* reserved */
 };
 typedef volatile struct dmaRegs_s dmaRegs;
 
@@ -161,7 +164,7 @@ typedef volatile struct dmaRegs_s dmaRegs;
  */
 /* Byte swapping: */
 #define MCD_NO_BYTE_SWAP    0x00045670  /* to disable byte swapping. */
-#define MCD_BYTE_REVERSE    0x00076540  /* to reverse the bytes of each uint32_t of the DMAed data. */
+#define MCD_BYTE_REVERSE    0x00076540  /* to reverse the bytes of each u32 of the DMAed data. */
 #define MCD_U16_REVERSE     0x00067450  /* to reverse the 16-bit halves of
                                            each 32-bit data value being DMAed.*/
 #define MCD_U16_BYTE_REVERSE    0x00054760 /* to reverse the byte halves of each
@@ -228,44 +231,44 @@ typedef volatile struct dmaRegs_s dmaRegs;
 
 /* Task Table Entry struct*/
 typedef struct {
-    uint32_t TDTstart;   /* task descriptor table start */
-    uint32_t TDTend;     /* task descriptor table end */
-    uint32_t varTab;     /* variable table start */
-    uint32_t FDTandFlags;    /* function descriptor table start and flags */
-    volatile uint32_t descAddrAndStatus;
-    volatile uint32_t modifiedVarTab;
-    uint32_t contextSaveSpace;   /* context save space start */
-    uint32_t literalBases;
+    u32 TDTstart;   /* task descriptor table start */
+    u32 TDTend;     /* task descriptor table end */
+    u32 varTab;     /* variable table start */
+    u32 FDTandFlags;    /* function descriptor table start and flags */
+    volatile u32 descAddrAndStatus;
+    volatile u32 modifiedVarTab;
+    u32 contextSaveSpace;   /* context save space start */
+    u32 literalBases;
 } TaskTableEntry;
 
 
 /* Chained buffer descriptor */
 typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
 struct MCD_bufDesc_struct {
-   uint32_t flags;         /* flags describing the DMA */
-   uint32_t csumResult;    /* checksum from checksumming performed since last checksum reset */
-   int8_t  *srcAddr;      /* the address to move data from */
-   int8_t  *destAddr;     /* the address to move data to */
-   int8_t  *lastDestAddr; /* the last address written to */
-   uint32_t dmaSize;       /* the number of bytes to transfer independent of the transfer size */
+   u32 flags;         /* flags describing the DMA */
+   u32 csumResult;    /* checksum from checksumming performed since last checksum reset */
+   s8  *srcAddr;      /* the address to move data from */
+   s8  *destAddr;     /* the address to move data to */
+   s8  *lastDestAddr; /* the last address written to */
+   u32 dmaSize;       /* the number of bytes to transfer independent of the transfer size */
    MCD_bufDesc *next; /* next buffer descriptor in chain */
-   uint32_t info;          /* private information about this descriptor;  DMA does not affect it */
+   u32 info;          /* private information about this descriptor;  DMA does not affect it */
 };
 
 /* Progress Query struct */
 typedef volatile struct MCD_XferProg_struct {
-   int8_t *lastSrcAddr;         /* the most-recent or last, post-increment source address */
-   int8_t *lastDestAddr;        /* the most-recent or last, post-increment destination address */
-   uint32_t  dmaSize;            /* the amount of data transferred for the current buffer */
+   s8 *lastSrcAddr;         /* the most-recent or last, post-increment source address */
+   s8 *lastDestAddr;        /* the most-recent or last, post-increment destination address */
+   u32  dmaSize;            /* the amount of data transferred for the current buffer */
    MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */
 } MCD_XferProg;
 
 
 /* FEC buffer descriptor */
 typedef volatile struct MCD_bufDescFec_struct {
-    uint16_t statCtrl;
-    uint16_t length;
-    uint32_t dataPointer;
+    u16 statCtrl;
+    u16 length;
+    u32 dataPointer;
 } MCD_bufDescFec;
 
 
@@ -279,65 +282,65 @@ typedef volatile struct MCD_bufDescFec_struct {
  */
 int MCD_startDma (
    int channel,   /* the channel on which to run the DMA */
-   int8_t  *srcAddr,  /* the address to move data from, or buffer-descriptor address */
-   int16_t srcIncr,   /* the amount to increment the source address per transfer */
-   int8_t  *destAddr, /* the address to move data to */
-   int16_t destIncr,  /* the amount to increment the destination address per transfer */
-   uint32_t dmaSize,   /* the number of bytes to transfer independent of the transfer size */
-   uint32_t xferSize,  /* the number bytes in of each data movement (1, 2, or 4) */
-   uint32_t initiator, /* what device initiates the DMA */
+   s8  *srcAddr,  /* the address to move data from, or buffer-descriptor address */
+   s16 srcIncr,   /* the amount to increment the source address per transfer */
+   s8  *destAddr, /* the address to move data to */
+   s16 destIncr,  /* the amount to increment the destination address per transfer */
+   u32 dmaSize,   /* the number of bytes to transfer independent of the transfer size */
+   u32 xferSize,  /* the number bytes in of each data movement (1, 2, or 4) */
+   u32 initiator, /* what device initiates the DMA */
    int priority,  /* priority of the DMA */
-   uint32_t flags,     /* flags describing the DMA */
-   uint32_t funcDesc   /* a description of byte swapping, bit swapping, and CRC actions */
+   u32 flags,     /* flags describing the DMA */
+   u32 funcDesc   /* a description of byte swapping, bit swapping, and CRC actions */
 );
 
-/* 
- * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA 
- * registers, relocating and creating the appropriate task structures, and 
+/*
+ * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
+ * registers, relocating and creating the appropriate task structures, and
  * setting up some global settings
  */
-int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, uint32_t flags);
+int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags);
 
-/* 
+/*
  * MCD_dmaStatus() returns the status of the DMA on the requested channel.
  */
 int MCD_dmaStatus (int channel);
 
-/* 
+/*
  * MCD_XferProgrQuery() returns progress of DMA on requested channel
  */
 int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep);
 
-/* 
+/*
  * MCD_killDma() halts the DMA on the requested channel, without any
  * intention of resuming the DMA.
  */
 int MCD_killDma (int channel);
 
-/* 
+/*
  * MCD_continDma() continues a DMA which as stopped due to encountering an
  * unready buffer descriptor.
  */
 int MCD_continDma (int channel);
 
-/* 
+/*
  * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
- * running on that channel). 
+ * running on that channel).
  */
 int MCD_pauseDma (int channel);
 
-/* 
+/*
  * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
  * running on that channel).
  */
 int MCD_resumeDma (int channel);
 
-/* 
+/*
  * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA
  */
-int MCD_csumQuery (int channel, uint32_t *csum);
+int MCD_csumQuery (int channel, u32 *csum);
 
-/* 
+/*
  * MCD_getCodeSize provides the packed size required by the microcoded task
  * and structures.
  */
@@ -350,7 +353,7 @@ int MCD_getCodeSize(void);
 int MCD_getVersion(char **longVersion);
 
 /* macro for setting a location in the variable table */
-#define MCD_SET_VAR(taskTab,idx,value) ((uint32_t *)(taskTab)->varTab)[idx] = value
+#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
    /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
       so I'm avoiding surrounding it with "do {} while(0)" */
 

include/MCD_tasksInit.h

@@ -15,7 +15,7 @@ void  MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xfer
 /*
  * Task 1
  */
-void  MCD_startDmaSingleNoEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
+void  MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
 
 
 /*
@@ -27,18 +27,18 @@ void  MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSi
 /*
  * Task 3
  */
-void  MCD_startDmaSingleEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
+void  MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
 
 
 /*
  * Task 4
  */
-void  MCD_startDmaENetRcv(int8_t *bDBase, int8_t *currBD, int8_t *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel);
+void  MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel);
 
 
 /*
  * Task 5
  */
-void  MCD_startDmaENetXmit(int8_t *bDBase, int8_t *currBD, int8_t *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel);
+void  MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel);
 
 #endif  /* MCD_TSK_INIT_H */

include/MCF5475_INTC.h

@@ -107,7 +107,6 @@
 #define MCF_INTC_LIACK(x)                    (*(volatile uint8_t *)(&_MBAR[0x7E4 + ((x-1)*0x4)]))
 
 
-
 /* Bit definitions and macros for MCF_INTC_IPRH */
 #define MCF_INTC_IPRH_INT32                  (0x1)
 #define MCF_INTC_IPRH_INT33                  (0x2)

include/dma.h

@@ -26,10 +26,6 @@
 #include "MCD_dma.h"
 #include "bas_string.h"
 
-#define DMA_INTC_LVL        5
-#define DMA_INTC_PRI        3
-
-
 void *dma_memcpy(void *dst, void *src, size_t n);
 extern int dma_init(void);
 extern int dma_get_channel(int requestor);
@@ -39,9 +35,9 @@ extern void dma_clear_channel(int channel);
 extern uint32_t dma_get_initiator(int requestor);
 extern int dma_set_initiator(int initiator);
 extern void dma_free_initiator(int initiator);
-extern void dma_irq_enable(uint8_t lvl, uint8_t pri);
+extern void dma_irq_enable(void);
 extern void dma_irq_disable(void);
-extern int dma_interrupt_handler(void *arg1, void *arg2);
+extern bool dma_interrupt_handler(void *arg1, void *arg2);
 
 
 #endif /* _DMA_H_ */

include/driver_vec.h

@@ -31,55 +31,57 @@
 
 enum driver_type
 {
-	BLOCKDEV_DRIVER,
-	CHARDEV_DRIVER,
-	XHDI_DRIVER,
-	MCD_DRIVER,
-	VIDEO_DRIVER,
-	PCI_DRIVER,
-	END_OF_DRIVERS,		/* marks end of driver list */
+    BLOCKDEV_DRIVER,
+    CHARDEV_DRIVER,
+    XHDI_DRIVER,
+    MCD_DRIVER,
+    VIDEO_DRIVER,
+    PCI_DRIVER,
+    MMU_DRIVER,
+    END_OF_DRIVERS = 0xffffffff,        /* marks end of driver list */
 };
 
 struct generic_driver_interface
 {
-	uint32_t (*init)(void);
-	uint32_t (*read)(void *buf, size_t count);
-	uint32_t (*write)(const void *buf, size_t count);
-	uint32_t (*ioctl)(uint32_t request, ...);
+    uint32_t (*init)(void);
+    uint32_t (*read)(void *buf, size_t count);
+    uint32_t (*write)(const void *buf, size_t count);
+    uint32_t (*ioctl)(uint32_t request, ...);
 };
 
 struct dma_driver_interface
 {
-	int32_t version;
-	int32_t magic;
-	int (*dma_set_initiator)(int initiator);
-	uint32_t (*dma_get_initiator)(int requestor);
-	void (*dma_free_initiator)(int requestor);
-	int (*dma_set_channel)(int requestor, void (*handler)(void));
-	int (*dma_get_channel)(int requestor);
-	void (*dma_free_channel)(int requestor);
-	void (*dma_clear_channel)(int channel);
-	int (*MCD_startDma)(long channel,
-						int8_t *srcAddr, unsigned int srcIncr, int8_t *destAddr, unsigned int destIncr,
-						unsigned int dmaSize, unsigned int xferSize, unsigned int initiator, int priority,
-						unsigned int flags, unsigned int funcDesc);
-	int32_t (*MCD_dmaStatus)(int32_t channel);
-	int32_t (*MCD_XferProgrQuery)(int32_t channel, MCD_XferProg *progRep);
-	int32_t (*MCD_killDma)(int32_t channel);
-	int32_t (*MCD_continDma)(int32_t channel);
-	int32_t (*MCD_pauseDma)(int32_t channel);
-	int32_t (*MCD_resumeDma)(int32_t channel);
-	int32_t (*MCD_csumQuery)(int32_t channel, uint32_t *csum);
-	void *(*dma_malloc)(uint32_t amount);
-	int32_t (*dma_free)(void *addr);
+    int32_t version;
+    int32_t magic;
+    int (*dma_set_initiator)(int initiator);
+    uint32_t (*dma_get_initiator)(int requestor);
+    void (*dma_free_initiator)(int requestor);
+    int (*dma_set_channel)(int requestor, void (*handler)(void));
+    int (*dma_get_channel)(int requestor);
+    void (*dma_free_channel)(int requestor);
+    void (*dma_clear_channel)(int channel);
+    int (*MCD_startDma)(long channel,
+                        int8_t *srcAddr, unsigned int srcIncr, int8_t *destAddr, unsigned int destIncr,
+                        unsigned int dmaSize, unsigned int xferSize, unsigned int initiator, int priority,
+                        unsigned int flags, unsigned int funcDesc);
+    int32_t (*MCD_dmaStatus)(int32_t channel);
+    int32_t (*MCD_XferProgrQuery)(int32_t channel, MCD_XferProg *progRep);
+    int32_t (*MCD_killDma)(int32_t channel);
+    int32_t (*MCD_continDma)(int32_t channel);
+    int32_t (*MCD_pauseDma)(int32_t channel);
+    int32_t (*MCD_resumeDma)(int32_t channel);
+    int32_t (*MCD_csumQuery)(int32_t channel, uint32_t *csum);
+    void *(*dma_malloc)(uint32_t amount);
+    int32_t (*dma_free)(void *addr);
 };
 
 struct xhdi_driver_interface
 {
-	uint32_t (*xhdivec)();
+    uint32_t (*xhdivec)();
 };
 
-/* Interpretation of offset for color fields: All offsets are from the right,
+/*
+ * Interpretation of offset for color fields: All offsets are from the right,
  * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you
  * can use the offset as right argument to <<). A pixel afterwards is a bit
  * stream and is written to video memory as that unmodified. This implies
@@ -87,10 +89,10 @@ struct xhdi_driver_interface
  */
 struct fb_bitfield
 {
-	unsigned long offset;           /* beginning of bitfield    */
-	unsigned long length;           /* length of bitfield       */
-	unsigned long msb_right;        /* != 0 : Most significant bit is */
-									/* right */
+    unsigned long offset;           /* beginning of bitfield    */
+    unsigned long length;           /* length of bitfield       */
+    unsigned long msb_right;        /* != 0 : Most significant bit is */
+    /* right */
 };
 
 /*
@@ -98,192 +100,202 @@ struct fb_bitfield
  */
 struct fb_var_screeninfo
 {
-	unsigned long xres;             /* visible resolution       */
-	unsigned long yres;
-	unsigned long xres_virtual;     /* virtual resolution       */
-	unsigned long yres_virtual;
-	unsigned long xoffset;          /* offset from virtual to visible */
-	unsigned long yoffset;          /* resolution           */
+    unsigned long xres;             /* visible resolution       */
+    unsigned long yres;
+    unsigned long xres_virtual;     /* virtual resolution       */
+    unsigned long yres_virtual;
+    unsigned long xoffset;          /* offset from virtual to visible */
+    unsigned long yoffset;          /* resolution           */
 
-	unsigned long bits_per_pixel;   /* guess what           */
-	unsigned long grayscale;        /* != 0 Graylevels instead of colors */
+    unsigned long bits_per_pixel;   /* guess what           */
+    unsigned long grayscale;        /* != 0 Graylevels instead of colors */
 
-	struct fb_bitfield red;         /* bitfield in fb mem if true color, */
-	struct fb_bitfield green;       /* else only length is significant */
-	struct fb_bitfield blue;
-	struct fb_bitfield transp;      /* transparency         */
+    struct fb_bitfield red;         /* bitfield in fb mem if true color, */
+    struct fb_bitfield green;       /* else only length is significant */
+    struct fb_bitfield blue;
+    struct fb_bitfield transp;      /* transparency         */
 
-	unsigned long nonstd;           /* != 0 Non standard pixel format */
+    unsigned long nonstd;           /* != 0 Non standard pixel format */
 
-	unsigned long activate;         /* see FB_ACTIVATE_*        */
+    unsigned long activate;         /* see FB_ACTIVATE_*        */
 
-	unsigned long height;           /* height of picture in mm    */
-	unsigned long width;            /* width of picture in mm     */
+    unsigned long height;           /* height of picture in mm    */
+    unsigned long width;            /* width of picture in mm     */
 
-	unsigned long accel_flags;      /* (OBSOLETE) see fb_info.flags */
+    unsigned long accel_flags;      /* (OBSOLETE) see fb_info.flags */
 
-	/* Timing: All values in pixclocks, except pixclock (of course) */
-	unsigned long pixclock;         /* pixel clock in ps (pico seconds) */
-	unsigned long left_margin;      /* time from sync to picture    */
-	unsigned long right_margin;     /* time from picture to sync    */
-	unsigned long upper_margin;     /* time from sync to picture    */
-	unsigned long lower_margin;
-	unsigned long hsync_len;        /* length of horizontal sync    */
-	unsigned long vsync_len;        /* length of vertical sync  */
-	unsigned long sync;             /* see FB_SYNC_*        */
-	unsigned long vmode;            /* see FB_VMODE_*       */
-	unsigned long rotate;           /* angle we rotate counter clockwise */
-	unsigned long refresh;
-	unsigned long reserved[4];      /* Reserved for future compatibility */
+    /* Timing: All values in pixclocks, except pixclock (of course) */
+    unsigned long pixclock;         /* pixel clock in ps (pico seconds) */
+    unsigned long left_margin;      /* time from sync to picture    */
+    unsigned long right_margin;     /* time from picture to sync    */
+    unsigned long upper_margin;     /* time from sync to picture    */
+    unsigned long lower_margin;
+    unsigned long hsync_len;        /* length of horizontal sync    */
+    unsigned long vsync_len;        /* length of vertical sync  */
+    unsigned long sync;             /* see FB_SYNC_*        */
+    unsigned long vmode;            /* see FB_VMODE_*       */
+    unsigned long rotate;           /* angle we rotate counter clockwise */
+    unsigned long refresh;
+    unsigned long reserved[4];      /* Reserved for future compatibility */
 };
 
 struct fb_fix_screeninfo
 {
-	char id[16];                    /* identification string eg "TT Builtin" */
-	unsigned long smem_start;       /* Start of frame buffer mem */
-									/* (physical address) */
-	unsigned long smem_len;         /* Length of frame buffer mem */
-	unsigned long type;             /* see FB_TYPE_*        */
-	unsigned long type_aux;         /* Interleave for interleaved Planes */
-	unsigned long visual;           /* see FB_VISUAL_*      */
-	unsigned short xpanstep;        /* zero if no hardware panning  */
-	unsigned short ypanstep;        /* zero if no hardware panning  */
-	unsigned short ywrapstep;       /* zero if no hardware ywrap    */
-	unsigned long line_length;      /* length of a line in bytes    */
-	unsigned long mmio_start;       /* Start of Memory Mapped I/O   */
-									/* (physical address) */
-	unsigned long mmio_len;         /* Length of Memory Mapped I/O  */
-	unsigned long accel;            /* Indicate to driver which */
-									/*  specific chip/card we have  */
-	unsigned short reserved[3];     /* Reserved for future compatibility */
+    char id[16];                    /* identification string eg "TT Builtin" */
+    unsigned long smem_start;       /* Start of frame buffer mem */
+    /* (physical address) */
+    unsigned long smem_len;         /* Length of frame buffer mem */
+    unsigned long type;             /* see FB_TYPE_*        */
+    unsigned long type_aux;         /* Interleave for interleaved Planes */
+    unsigned long visual;           /* see FB_VISUAL_*      */
+    unsigned short xpanstep;        /* zero if no hardware panning  */
+    unsigned short ypanstep;        /* zero if no hardware panning  */
+    unsigned short ywrapstep;       /* zero if no hardware ywrap    */
+    unsigned long line_length;      /* length of a line in bytes    */
+    unsigned long mmio_start;       /* Start of Memory Mapped I/O   */
+    /* (physical address) */
+    unsigned long mmio_len;         /* Length of Memory Mapped I/O  */
+    unsigned long accel;            /* Indicate to driver which */
+    /*  specific chip/card we have  */
+    unsigned short reserved[3];     /* Reserved for future compatibility */
 };
 
 struct fb_chroma
 {
-	unsigned long redx; /* in fraction of 1024 */
-	unsigned long greenx;
-	unsigned long bluex;
-	unsigned long whitex;
-	unsigned long redy;
-	unsigned long greeny;
-	unsigned long bluey;
-	unsigned long whitey;
+    unsigned long redx;             /* in fraction of 1024 */
+    unsigned long greenx;
+    unsigned long bluex;
+    unsigned long whitex;
+    unsigned long redy;
+    unsigned long greeny;
+    unsigned long bluey;
+    unsigned long whitey;
 };
 
 struct fb_monspecs
 {
-	struct fb_chroma chroma;
-	struct fb_videomode *modedb;    /* mode database */
-	unsigned char  manufacturer[4]; /* Manufacturer */
-	unsigned char  monitor[14];     /* Monitor String */
-	unsigned char  serial_no[14];   /* Serial Number */
-	unsigned char  ascii[14];       /* ? */
-	unsigned long modedb_len;       /* mode database length */
-	unsigned long model;            /* Monitor Model */
-	unsigned long serial;           /* Serial Number - Integer */
-	unsigned long year;             /* Year manufactured */
-	unsigned long week;             /* Week Manufactured */
-	unsigned long hfmin;            /* hfreq lower limit (Hz) */
-	unsigned long hfmax;            /* hfreq upper limit (Hz) */
-	unsigned long dclkmin;          /* pixelclock lower limit (Hz) */
-	unsigned long dclkmax;          /* pixelclock upper limit (Hz) */
-	unsigned short input;           /* display type - see FB_DISP_* */
-	unsigned short dpms;            /* DPMS support - see FB_DPMS_ */
-	unsigned short signal;          /* Signal Type - see FB_SIGNAL_* */
-	unsigned short vfmin;           /* vfreq lower limit (Hz) */
-	unsigned short vfmax;           /* vfreq upper limit (Hz) */
-	unsigned short gamma;           /* Gamma - in fractions of 100 */
-	unsigned short gtf  : 1;        /* supports GTF */
-	unsigned short misc;            /* Misc flags - see FB_MISC_* */
-	unsigned char  version;         /* EDID version... */
-	unsigned char  revision;        /* ...and revision */
-	unsigned char  max_x;           /* Maximum horizontal size (cm) */
-	unsigned char  max_y;           /* Maximum vertical size (cm) */
+    struct fb_chroma chroma;
+    struct fb_videomode *modedb;    /* mode database */
+    unsigned char  manufacturer[4]; /* Manufacturer */
+    unsigned char  monitor[14];     /* Monitor String */
+    unsigned char  serial_no[14];   /* Serial Number */
+    unsigned char  ascii[14];       /* ? */
+    unsigned long modedb_len;       /* mode database length */
+    unsigned long model;            /* Monitor Model */
+    unsigned long serial;           /* Serial Number - Integer */
+    unsigned long year;             /* Year manufactured */
+    unsigned long week;             /* Week Manufactured */
+    unsigned long hfmin;            /* hfreq lower limit (Hz) */
+    unsigned long hfmax;            /* hfreq upper limit (Hz) */
+    unsigned long dclkmin;          /* pixelclock lower limit (Hz) */
+    unsigned long dclkmax;          /* pixelclock upper limit (Hz) */
+    unsigned short input;           /* display type - see FB_DISP_* */
+    unsigned short dpms;            /* DPMS support - see FB_DPMS_ */
+    unsigned short signal;          /* Signal Type - see FB_SIGNAL_* */
+    unsigned short vfmin;           /* vfreq lower limit (Hz) */
+    unsigned short vfmax;           /* vfreq upper limit (Hz) */
+    unsigned short gamma;           /* Gamma - in fractions of 100 */
+    unsigned short gtf  : 1;        /* supports GTF */
+    unsigned short misc;            /* Misc flags - see FB_MISC_* */
+    unsigned char  version;         /* EDID version... */
+    unsigned char  revision;        /* ...and revision */
+    unsigned char  max_x;           /* Maximum horizontal size (cm) */
+    unsigned char  max_y;           /* Maximum vertical size (cm) */
 };
 
 struct framebuffer_driver_interface
 {
-	struct fb_info **framebuffer_info;	/* pointer to an fb_info struct (defined in include/fb.h) */
+    struct fb_info **framebuffer_info;  /* pointer to an fb_info struct (defined in include/fb.h) */
 };
 
-struct pci_bios_interface {
-	uint32_t subjar;
-	uint32_t version;
-	/* Although we declare this functions as standard gcc functions (cdecl),
-	 * they expect paramenters inside registers (fastcall) unsupported by gcc m68k.
-	 * Caller will take care of parameters passing convention.
-	 */
-	int32_t (*find_pci_device)	(uint32_t id, uint16_t index);
-	int32_t (*find_pci_classcode)	(uint32_t class, uint16_t index);
-	int32_t (*read_config_byte)	(int32_t handle, uint16_t reg, uint8_t *address);
-	int32_t (*read_config_word)	(int32_t handle, uint16_t reg, uint16_t *address);
-	int32_t (*read_config_longword)	(int32_t handle, uint16_t reg, uint32_t *address);
-	uint8_t (*fast_read_config_byte)	(int32_t handle, uint16_t reg);
-	uint16_t (*fast_read_config_word)	(int32_t handle, uint16_t reg);
-	uint32_t (*fast_read_config_longword)	(int32_t handle, uint16_t reg);
-	int32_t (*write_config_byte)	(int32_t handle, uint16_t reg, uint16_t val);
-	int32_t (*write_config_word)	(int32_t handle, uint16_t reg, uint16_t val);
-	int32_t (*write_config_longword)	(int32_t handle, uint16_t reg, uint32_t val);
-	int32_t (*hook_interrupt)	(int32_t handle, uint32_t *routine, uint32_t *parameter);
-	int32_t (*unhook_interrupt)	(int32_t handle);
-	int32_t (*special_cycle)	(uint16_t bus, uint32_t data);
-	int32_t (*get_routing)	(int32_t handle);
-	int32_t (*set_interrupt)	(int32_t handle);
-	int32_t (*get_resource)	(int32_t handle);
-	int32_t (*get_card_used)	(int32_t handle, uint32_t *address);
-	int32_t (*set_card_used)	(int32_t handle, uint32_t *callback);
-	int32_t (*read_mem_byte)	(int32_t handle, uint32_t offset, uint8_t *address);
-	int32_t (*read_mem_word)	(int32_t handle, uint32_t offset, uint16_t *address);
-	int32_t (*read_mem_longword)	(int32_t handle, uint32_t offset, uint32_t *address);
-	uint8_t (*fast_read_mem_byte)	(int32_t handle, uint32_t offset);
-	uint16_t (*fast_read_mem_word)	(int32_t handle, uint32_t offset);
-	uint32_t (*fast_read_mem_longword)	(int32_t handle, uint32_t offset);
-	int32_t (*write_mem_byte)	(int32_t handle, uint32_t offset, uint16_t val);
-	int32_t (*write_mem_word)	(int32_t handle, uint32_t offset, uint16_t val);
-	int32_t (*write_mem_longword)	(int32_t handle, uint32_t offset, uint32_t val);
-	int32_t (*read_io_byte)	(int32_t handle, uint32_t offset, uint8_t *address);
-	int32_t (*read_io_word)	(int32_t handle, uint32_t offset, uint16_t *address);
-	int32_t (*read_io_longword)	(int32_t handle, uint32_t offset, uint32_t *address);
-	uint8_t (*fast_read_io_byte)	(int32_t handle, uint32_t offset);
-	uint16_t (*fast_read_io_word)	(int32_t handle, uint32_t offset);
-	uint32_t (*fast_read_io_longword)	(int32_t handle, uint32_t offset);
-	int32_t (*write_io_byte)	(int32_t handle, uint32_t offset, uint16_t val);
-	int32_t (*write_io_word)	(int32_t handle, uint32_t offset, uint16_t val);
-	int32_t (*write_io_longword)	(int32_t handle, uint32_t offset, uint32_t val);
-	int32_t (*get_machine_id)	(void);
-	int32_t (*get_pagesize)	(void);
-	int32_t (*virt_to_bus)	(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
-	int32_t (*bus_to_virt)	(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
-	int32_t (*virt_to_phys)	(uint32_t address, PCI_CONV_ADR *pointer);
-	int32_t (*phys_to_virt)	(uint32_t address, PCI_CONV_ADR *pointer);
-//	int32_t reserved[2];
+struct pci_bios_interface
+{
+    uint32_t subjar;
+    uint32_t version;
+    /* Although we declare this functions as standard gcc functions (cdecl),
+     * they expect parameters inside registers (fastcall) unsupported by gcc m68k.
+     * Caller will take care of parameters passing convention.
+     */
+    int32_t (*find_pci_device)(uint32_t id, uint16_t index);
+    int32_t (*find_pci_classcode)(uint32_t class, uint16_t index);
+    int32_t (*read_config_byte)(int32_t handle, uint16_t reg, uint8_t *address);
+    int32_t (*read_config_word)(int32_t handle, uint16_t reg, uint16_t *address);
+    int32_t (*read_config_longword)(int32_t handle, uint16_t reg, uint32_t *address);
+    uint8_t (*fast_read_config_byte)(int32_t handle, uint16_t reg);
+    uint16_t (*fast_read_config_word)(int32_t handle, uint16_t reg);
+    uint32_t (*fast_read_config_longword)(int32_t handle, uint16_t reg);
+    int32_t (*write_config_byte)(int32_t handle, uint16_t reg, uint16_t val);
+    int32_t (*write_config_word)(int32_t handle, uint16_t reg, uint16_t val);
+    int32_t (*write_config_longword)(int32_t handle, uint16_t reg, uint32_t val);
+    int32_t (*hook_interrupt)(int32_t handle, uint32_t *routine, uint32_t *parameter);
+    int32_t (*unhook_interrupt)(int32_t handle);
+    int32_t (*special_cycle)(uint16_t bus, uint32_t data);
+    int32_t (*get_routing)(int32_t handle);
+    int32_t (*set_interrupt)(int32_t handle);
+    int32_t (*get_resource)(int32_t handle);
+    int32_t (*get_card_used)(int32_t handle, uint32_t *address);
+    int32_t (*set_card_used)(int32_t handle, uint32_t *callback);
+    int32_t (*read_mem_byte)(int32_t handle, uint32_t offset, uint8_t *address);
+    int32_t (*read_mem_word)(int32_t handle, uint32_t offset, uint16_t *address);
+    int32_t (*read_mem_longword)(int32_t handle, uint32_t offset, uint32_t *address);
+    uint8_t (*fast_read_mem_byte)(int32_t handle, uint32_t offset);
+    uint16_t (*fast_read_mem_word)(int32_t handle, uint32_t offset);
+    uint32_t (*fast_read_mem_longword)(int32_t handle, uint32_t offset);
+    int32_t (*write_mem_byte)(int32_t handle, uint32_t offset, uint16_t val);
+    int32_t (*write_mem_word)(int32_t handle, uint32_t offset, uint16_t val);
+    int32_t (*write_mem_longword)(int32_t handle, uint32_t offset, uint32_t val);
+    int32_t (*read_io_byte)(int32_t handle, uint32_t offset, uint8_t *address);
+    int32_t (*read_io_word)(int32_t handle, uint32_t offset, uint16_t *address);
+    int32_t (*read_io_longword)(int32_t handle, uint32_t offset, uint32_t *address);
+    uint8_t (*fast_read_io_byte)(int32_t handle, uint32_t offset);
+    uint16_t (*fast_read_io_word)(int32_t handle, uint32_t offset);
+    uint32_t (*fast_read_io_longword)(int32_t handle, uint32_t offset);
+    int32_t (*write_io_byte)(int32_t handle, uint32_t offset, uint16_t val);
+    int32_t (*write_io_word)(int32_t handle, uint32_t offset, uint16_t val);
+    int32_t (*write_io_longword)(int32_t handle, uint32_t offset, uint32_t val);
+    int32_t (*get_machine_id)(void);
+    int32_t (*get_pagesize)(void);
+    int32_t (*virt_to_bus)(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+    int32_t (*bus_to_virt)(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
+    int32_t (*virt_to_phys)(uint32_t address, PCI_CONV_ADR *pointer);
+    int32_t (*phys_to_virt)(uint32_t address, PCI_CONV_ADR *pointer);
+    //  int32_t reserved[2];
+};
+
+struct mmu_driver_interface
+{
+    int32_t (*map_page_locked)(uint32_t address, uint32_t length, int asid);
+    int32_t (*unlock_page)(uint32_t address, uint32_t length, int asid);
+    int32_t (*report_locked_pages)(uint32_t *num_itlb, uint32_t *num_dtlb);
+    uint32_t (*report_pagesize)(void);
 };
 
 union interface
 {
-	struct generic_driver_interface *gdi;
-	struct xhdi_driver_interface *xhdi;
-	struct dma_driver_interface *dma;
-	struct framebuffer_driver_interface *fb;
-	struct pci_bios_interface *pci;
+    struct generic_driver_interface *gdi;
+    struct xhdi_driver_interface *xhdi;
+    struct dma_driver_interface *dma;
+    struct framebuffer_driver_interface *fb;
+    struct pci_bios_interface *pci;
+    struct mmu_driver_interface *mmu;
 };
 
 struct generic_interface
 {
-	enum driver_type type;
-	char name[16];
-	char description[64];
-	int version;
-	int revision;
-	union interface interface;
+    enum driver_type type;
+    char name[16];
+    char description[64];
+    int version;
+    int revision;
+    union interface interface;
 };
 
 struct driver_table
 {
-	uint32_t bas_version;
-	uint32_t bas_revision;
-	uint32_t (*remove_handler)();			/* calling this will disable the BaS' hook into trap #0 */
-	struct generic_interface *interfaces;
+    uint32_t bas_version;
+    uint32_t bas_revision;
+    void (*remove_handler)(void);           /* calling this will disable the BaS' hook into trap #0 */
+    struct generic_interface *interfaces;
 };
 
 

include/ehci.h

@@ -23,43 +23,42 @@
 #define USB_EHCI_H
 
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	5
-#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
-#endif
 
 /* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
 #define DeviceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+    ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
 
 #define DeviceOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
+    ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
 
 #define InterfaceRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+    ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
 
 #define EndpointRequest \
-	((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+    ((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
 
 #define EndpointOutRequest \
-	((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
+    ((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
 
 /*
  * Register Space.
  */
-struct ehci_hccr {
-	uint32_t cr_capbase;
+struct ehci_hccr
+{
+    uint32_t cr_capbase;
 #define HC_LENGTH(p)		(((p) >> 0) & 0x00ff)
 #define HC_VERSION(p)		(((p) >> 16) & 0xffff)
-	uint32_t cr_hcsparams;
+    uint32_t cr_hcsparams;
 #define HCS_PPC(p)			((p) & (1 << 4))
 #define HCS_INDICATOR(p)	((p) & (1 << 16)) /* Port indicators */
 #define HCS_N_PORTS(p)		(((p) >> 0) & 0xf)
-	uint32_t cr_hccparams;
-	uint8_t cr_hcsp_portrt[8];
+    uint32_t cr_hccparams;
+    uint8_t cr_hcsp_portrt[8];
 } __attribute__ ((packed));
 
-struct ehci_hcor {
-	uint32_t or_usbcmd;
+struct ehci_hcor
+{
+    uint32_t or_usbcmd;
 #define CMD_PARK	(1 << 11)		/* enable "park" */
 #define CMD_PARK_CNT(c)	(((c) >> 8) & 3)	/* how many transfers to park */
 #define CMD_ASE		(1 << 5)		/* async schedule enable */
@@ -68,7 +67,7 @@ struct ehci_hcor {
 #define CMD_PSE		(1 << 4)		/* periodic schedule enable */
 #define CMD_RESET	(1 << 1)		/* reset HC not bus */
 #define CMD_RUN		(1 << 0)		/* start/stop HC */
-	uint32_t or_usbsts;
+    uint32_t or_usbsts;
 #define	STD_ASS		(1 << 15)
 #define STS_PSSTAT	(1 << 14)
 #define STS_RECL	(1 << 13)
@@ -79,55 +78,55 @@ struct ehci_hcor {
 #define STS_PCD		(1 << 2)
 #define STS_USBERRINT (1 << 1)
 #define STS_USBINT	(1 << 0)
-	uint32_t or_usbintr;
+    uint32_t or_usbintr;
 #define INTR_IAAE	(1 << 5)
 #define INTR_HSEE	(1 << 4)
 #define INTR_FLRE	(1 << 3)
 #define INTR_PCDE	(1 << 2)
 #define INTR_USBERRINTE (1 << 1)
 #define INTR_USBINTE (1 << 0)
-	uint32_t or_frindex;
-	uint32_t or_ctrldssegment;
-	uint32_t or_periodiclistbase;
-	uint32_t or_asynclistaddr;
-	uint32_t _reserved_[9];
-	uint32_t or_configflag;
+    uint32_t or_frindex;
+    uint32_t or_ctrldssegment;
+    uint32_t or_periodiclistbase;
+    uint32_t or_asynclistaddr;
+    uint32_t _reserved_[9];
+    uint32_t or_configflag;
 #define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
-	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
-	uint32_t or_systune;
+    uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
+    uint32_t or_systune;
 } __attribute__ ((packed));
 
-#define USBMODE		0x68			/* USB Device mode */
+#define USBMODE         0x68		/* USB Device mode */
 #define USBMODE_SDIS	(1 << 3)	/* Stream disable */
-#define USBMODE_BE	(1 << 2)		/* BE/LE endiannes select */
+#define USBMODE_BE      (1 << 2)	/* BE/LE endiannes select */
 #define USBMODE_CM_HC	(3 << 0)	/* host controller mode */
 #define USBMODE_CM_IDLE	(0 << 0)	/* idle state */
 
 /* Interface descriptor */
 struct usb_linux_interface_descriptor
 {
-	unsigned char	bLength;
-	unsigned char	bDescriptorType;
-	unsigned char	bInterfaceNumber;
-	unsigned char	bAlternateSetting;
-	unsigned char	bNumEndpoints;
-	unsigned char	bInterfaceClass;
-	unsigned char	bInterfaceSubClass;
-	unsigned char	bInterfaceProtocol;
-	unsigned char	iInterface;
+    unsigned char	bLength;
+    unsigned char	bDescriptorType;
+    unsigned char	bInterfaceNumber;
+    unsigned char	bAlternateSetting;
+    unsigned char	bNumEndpoints;
+    unsigned char	bInterfaceClass;
+    unsigned char	bInterfaceSubClass;
+    unsigned char	bInterfaceProtocol;
+    unsigned char	iInterface;
 } __attribute__ ((packed));
 
 /* Configuration descriptor information.. */
 struct usb_linux_config_descriptor
 {
-	unsigned char	bLength;
-	unsigned char	bDescriptorType;
-	unsigned short	wTotalLength;
-	unsigned char	bNumInterfaces;
-	unsigned char	bConfigurationValue;
-	unsigned char	iConfiguration;
-	unsigned char	bmAttributes;
-	unsigned char	MaxPower;
+    unsigned char	bLength;
+    unsigned char	bDescriptorType;
+    unsigned short	wTotalLength;
+    unsigned char	bNumInterfaces;
+    unsigned char	bConfigurationValue;
+    unsigned char	iConfiguration;
+    unsigned char	bmAttributes;
+    unsigned char	MaxPower;
 } __attribute__ ((packed));
 
 #if defined CONFIG_EHCI_DESC_BIG_ENDIAN
@@ -178,31 +177,31 @@ struct usb_linux_config_descriptor
 /* Queue Element Transfer Descriptor (qTD). */
 struct qTD
 {
-	uint32_t qt_next;
+    uint32_t qt_next;
 #define	QT_NEXT_TERMINATE	1
-	uint32_t qt_altnext;
-	uint32_t qt_token;
-	uint32_t qt_buffer[5];
+    uint32_t qt_altnext;
+    uint32_t qt_token;
+    uint32_t qt_buffer[5];
 };
 
 /* Queue Head (QH). */
 struct QH
 {
-	uint32_t qh_link;
+    uint32_t qh_link;
 #define	QH_LINK_TERMINATE	1
 #define	QH_LINK_TYPE_ITD	0
 #define	QH_LINK_TYPE_QH		2
 #define	QH_LINK_TYPE_SITD	4
 #define	QH_LINK_TYPE_FSTN	6
-	uint32_t qh_endpt1;
-	uint32_t qh_endpt2;
-	uint32_t qh_curtd;
-	struct qTD qh_overlay;
-	/*
-	 * Add dummy fill value to make the size of this struct
-	 * aligned to 32 bytes
-	 */
-	uint8_t fill[16];
+    uint32_t qh_endpt1;
+    uint32_t qh_endpt2;
+    uint32_t qh_curtd;
+    struct qTD qh_overlay;
+    /*
+     * Add dummy fill value to make the size of this struct
+     * aligned to 32 bytes
+     */
+    uint8_t fill[16];
 };
 
 /* Low level init functions */

include/fec.h

@@ -2,7 +2,7 @@
  * File:    fec.h
  * Purpose: Driver for the Fast Ethernet Controller (FEC)
  *
- * Notes:       
+ * Notes:
  */
 
 #ifndef _FEC_H_
@@ -30,30 +30,30 @@
  */
 typedef struct
 {
-	int total;      /* total count of errors   */
-	int hberr;      /* heartbeat error         */
-	int babr;       /* babbling receiver       */
-	int babt;       /* babbling transmitter    */
-	int gra;        /* graceful stop complete  */
-	int txf;        /* transmit frame          */
-	int mii;        /* MII                     */
-	int lc;         /* late collision          */
-	int rl;         /* collision retry limit   */
-	int xfun;       /* transmit FIFO underrrun */
-	int xferr;      /* transmit FIFO error     */
-	int rferr;      /* receive FIFO error      */
-	int dtxf;       /* DMA transmit frame      */
-	int drxf;       /* DMA receive frame       */
-	int rfsw_inv;   /* Invalid bit in RFSW     */
-	int rfsw_l;     /* RFSW Last in Frame      */
-	int rfsw_m;     /* RFSW Miss               */
-	int rfsw_bc;    /* RFSW Broadcast          */
-	int rfsw_mc;    /* RFSW Multicast          */
-	int rfsw_lg;    /* RFSW Length Violation   */
-	int rfsw_no;    /* RFSW Non-octet          */
-	int rfsw_cr;    /* RFSW Bad CRC            */
-	int rfsw_ov;    /* RFSW Overflow           */
-	int rfsw_tr;    /* RFSW Truncated          */
+        int total;      /* total count of errors   */
+        int hberr;      /* heartbeat error         */
+        int babr;       /* babbling receiver       */
+        int babt;       /* babbling transmitter    */
+        int gra;        /* graceful stop complete  */
+        int txf;        /* transmit frame          */
+        int mii;        /* MII                     */
+        int lc;         /* late collision          */
+        int rl;         /* collision retry limit   */
+        int xfun;       /* transmit FIFO underrrun */
+        int xferr;      /* transmit FIFO error     */
+        int rferr;      /* receive FIFO error      */
+        int dtxf;       /* DMA transmit frame      */
+        int drxf;       /* DMA receive frame       */
+        int rfsw_inv;   /* Invalid bit in RFSW     */
+        int rfsw_l;     /* RFSW Last in Frame      */
+        int rfsw_m;     /* RFSW Miss               */
+        int rfsw_bc;    /* RFSW Broadcast          */
+        int rfsw_mc;    /* RFSW Multicast          */
+        int rfsw_lg;    /* RFSW Length Violation   */
+        int rfsw_no;    /* RFSW Non-octet          */
+        int rfsw_cr;    /* RFSW Bad CRC            */
+        int rfsw_ov;    /* RFSW Overflow           */
+        int rfsw_tr;    /* RFSW Truncated          */
 } FEC_EVENT_LOG;
 
 
@@ -87,8 +87,8 @@ extern int fec1_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *);
 extern void fec_irq_enable(uint8_t, uint8_t, uint8_t);
 extern void fec_irq_disable(uint8_t);
 extern void fec_interrupt_handler(uint8_t);
-extern int fec0_interrupt_handler(void *, void *);
-extern int fec1_interrupt_handler(void *, void *);
+extern bool fec0_interrupt_handler(void *, void *);
+extern bool fec1_interrupt_handler(void *, void *);
 extern void fec_eth_setup(uint8_t, uint8_t, uint8_t, uint8_t, const uint8_t *);
 extern void fec_eth_reset(uint8_t);
 extern void fec_eth_stop(uint8_t);

include/i2c-algo-bit.h

@@ -32,18 +32,19 @@
  * manipulate the line states, and to init any hw-specific features. This is
  * only used if you have more than one hw-type of adapter running. 
  */
-struct i2c_algo_bit_data {
-	void *data;		/* private data for lowlevel routines */
-	void (*setsda) (void *data, int state);
-	void (*setscl) (void *data, int state);
-	int  (*getsda) (void *data);
-	int  (*getscl) (void *data);
+struct i2c_algo_bit_data
+{
+    void *data;		/* private data for lowlevel routines */
+    void (*setsda) (void *data, int state);
+    void (*setscl) (void *data, int state);
+    int  (*getsda) (void *data);
+    int  (*getscl) (void *data);
 
-	/* local settings */
-	int udelay;		/* half-clock-cycle time in microsecs */
-				/* i.e. clock is (500 / udelay) KHz */
-	int mdelay;		/* in millisecs, unused */
-	int timeout;		/* in jiffies */
+    /* local settings */
+    int udelay;     /* half-clock-cycle time in microsecs */
+                    /* i.e. clock is (500 / udelay) KHz */
+    int mdelay;     /* in millisecs, unused */
+    int timeout;    /* in jiffies */
 };
 
 #define I2C_BIT_ADAP_MAX	16

include/i2c.h

@@ -28,6 +28,8 @@
 #ifndef _I2C_H
 #define _I2C_H
 
+#include "bas_types.h"
+
 /* --- General options ------------------------------------------------	*/
 
 struct i2c_msg;
@@ -44,39 +46,51 @@ extern int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
  * be addressed using the same bus algorithms - i.e. bit-banging or the PCF8584
  * to name two of the most common.
  */
-struct i2c_algorithm {
-	unsigned int id;
-	int (*master_xfer)(struct i2c_adapter *adap,struct i2c_msg *msgs, int num);
-	/* --- ioctl like call to set div. parameters. */
-	int (*algo_control)(struct i2c_adapter *, unsigned int, unsigned long);
+struct i2c_algorithm
+{
+    unsigned int id;
+    int (*master_xfer)(struct i2c_adapter *adap,struct i2c_msg *msgs, int num);
+    /* --- ioctl like call to set div. parameters. */
+    int (*algo_control)(struct i2c_adapter *, unsigned int, unsigned long);
 };
 
 /*
  * i2c_adapter is the structure used to identify a physical i2c bus along
  * with the access algorithms necessary to access it.
  */
-struct i2c_adapter {
-	struct i2c_algorithm *algo;/* the algorithm to access the bus	*/
-	void *algo_data;
-	int timeout;
-	int retries;
-	int nr;
+struct i2c_adapter
+{
+    struct i2c_algorithm *algo;     /* the algorithm to access the bus	*/
+    void *algo_data;
+    int timeout;
+    int retries;
+    int nr;
 };
 
 /*
  * I2C Message - used for pure i2c transaction, also from /dev interface
  */
-struct i2c_msg {
-	unsigned short addr;	/* slave address			*/
- 	unsigned short flags;		
-#define I2C_M_TEN	0x10	/* we have a ten bit chip address	*/
-#define I2C_M_RD	0x01
-#define I2C_M_NOSTART	0x4000
-#define I2C_M_REV_DIR_ADDR	0x2000
-#define I2C_M_IGNORE_NAK	0x1000
-#define I2C_M_NO_RD_ACK		0x0800
- 	unsigned short len;		/* msg length				*/
- 	unsigned char *buf;		/* pointer to msg data			*/
+struct i2c_msg
+{
+    unsigned short addr;	/* slave address			*/
+    unsigned short flags;
+#define I2C_M_TEN           0x10	/* we have a ten bit chip address	*/
+#define I2C_M_RD            0x01
+#define I2C_M_NOSTART       0x4000
+#define I2C_M_REV_DIR_ADDR  0x2000
+#define I2C_M_IGNORE_NAK    0x1000
+#define I2C_M_NO_RD_ACK     0x0800
+    unsigned short len;     /* msg length				*/
+    unsigned char *buf;     /* pointer to msg data			*/
 };
 
+extern void i2c_init(void);
+extern void i2c_set_frequency(int hz);
+extern int i2c_read(int address, char *data, int lengt, bool repeated);
+extern int i2c_read_byte(int ack);
+extern int i2c_write(int address, const char *data, int length, bool repeated);
+extern int i2c_write_byte(int data);
+extern void i2c_start(void);
+extern void i2c_stop(void);
+
 #endif /* _I2C_H */

include/interrupts.h

@@ -27,82 +27,123 @@
 #include <stdbool.h>
 
 /* interrupt sources */
-#define INT_SOURCE_EPORT_EPF1		1	// edge port flag 1
-#define	INT_SOURCE_EPORT_EPF2		2	// edge port flag 2
-#define	INT_SOURCE_EPORT_EPF3		3	// edge port flag 3
-#define	INT_SOURCE_EPORT_EPF4		4	// edge port flag 4
-#define	INT_SOURCE_EPORT_EPF5		5	// edge port flag 5
-#define	INT_SOURCE_EPORT_EPF6		6	// edge port flag 6
-#define	INT_SOURCE_EPORT_EPF7		7	// edge port flag 7
-#define	INT_SOURCE_USB_EP0ISR		15	// USB endpoint 0 interrupt
-#define	INT_SOURCE_USB_EP1ISR		16	// USB endpoint 1 interrupt
-#define	INT_SOURCE_USB_EP2ISR		17	// USB endpoint 2 interrupt
-#define	INT_SOURCE_USB_EP3ISR		18	// USB endpoint 3 interrupt
-#define	INT_SOURCE_USB_EP4ISR		19	// USB endpoint 4 interrupt
-#define	INT_SOURCE_USB_EP5ISR		20	// USB endpoint 5 interrupt
-#define	INT_SOURCE_USB_EP6ISR		21	// USB endpoint 6 interrupt
-#define	INT_SOURCE_USB_USBISR		22	// USB general interrupt
-#define	INT_SOURCE_USB_USBAISR		23	// USB core interrupt
-#define	INT_SOURCE_USB_ANY			24	// OR of all USB interrupts
-#define	INT_SOURCE_USB_DSPI_OVF		25	// DSPI overflow or underflow
-#define	INT_SOURCE_USB_DSPI_RFOF	26	// receive FIFO overflow interrupt
-#define	INT_SOURCE_USB_DSPI_RFDF	27	// receive FIFO drain interrupt
-#define	INT_SOURCE_USB_DSPI_TFUF	28	// transmit FIFO underflow interrupt
-#define	INT_SOURCE_USB_DSPI_TCF		29	// transfer complete interrupt
-#define	INT_SOURCE_USB_DSPI_TFFF	30	// transfer FIFO fill interrupt
-#define	INT_SOURCE_USB_DSPI_EOQF	31	// end of queue interrupt
-#define	INT_SOURCE_PSC3				32	// PSC3 interrupt
-#define	INT_SOURCE_PSC2				33	// PSC2 interrupt
-#define	INT_SOURCE_PSC1				34	// PSC1 interrupt
-#define	INT_SOURCE_PSC0				35	// PSC0 interrupt
-#define	INT_SOURCE_CTIMERS			36	// combined source for comm timers
-#define	INT_SOURCE_SEC				37	// SEC interrupt
-#define	INT_SOURCE_FEC1				38	// FEC1 interrupt
-#define	INT_SOURCE_FEC0				39	// FEC0 interrupt
-#define	INT_SOURCE_I2C				40	// I2C interrupt
-#define	INT_SOURCE_PCIARB			41	// PCI arbiter interrupt
-#define	INT_SOURCE_CBPCI			42	// COMM bus PCI interrupt
-#define	INT_SOURCE_XLBPCI			43	// XLB PCI interrupt
-#define	INT_SOURCE_XLBARB			47	// XLBARB to PCI interrupt
-#define	INT_SOURCE_DMA				48	// multichannel DMA interrupt
-#define	INT_SOURCE_CAN0_ERROR		49	// FlexCAN error interrupt
-#define	INT_SOURCE_CAN0_BUSOFF		50	// FlexCAN bus off interrupt
-#define	INT_SOURCE_CAN0_MBOR		51	// message buffer ORed interrupt
-#define	INT_SOURCE_SLT1				53	// slice timer 1 interrupt
-#define	INT_SOURCE_SLT0				54	// slice timer 0 interrupt
-#define	INT_SOURCE_CAN1_ERROR		55	// FlexCAN error interrupt
-#define	INT_SOURCE_CAN1_BUSOFF		56	// FlexCAN bus off interrupt
-#define	INT_SOURCE_CAN1_MBOR		57	// message buffer ORed interrupt
-#define	INT_SOURCE_GPT3				59	// GPT3 timer interrupt
-#define	INT_SOURCE_GPT2				60	// GPT2 timer interrupt
-#define	INT_SOURCE_GPT1				61	// GPT1 timer interrupt
-#define	INT_SOURCE_GPT0				62	// GPT0 timer interrupt
+#define INT_SOURCE_EPORT_EPF1       1   // edge port flag 1
+#define INT_SOURCE_EPORT_EPF2       2   // edge port flag 2
+#define INT_SOURCE_EPORT_EPF3       3   // edge port flag 3
+#define INT_SOURCE_EPORT_EPF4       4   // edge port flag 4
+#define INT_SOURCE_EPORT_EPF5       5   // edge port flag 5
+#define INT_SOURCE_EPORT_EPF6       6   // edge port flag 6
+#define INT_SOURCE_EPORT_EPF7       7   // edge port flag 7
+#define INT_SOURCE_USB_EP0ISR       15  // USB endpoint 0 interrupt
+#define INT_SOURCE_USB_EP1ISR       16  // USB endpoint 1 interrupt
+#define INT_SOURCE_USB_EP2ISR       17  // USB endpoint 2 interrupt
+#define INT_SOURCE_USB_EP3ISR       18  // USB endpoint 3 interrupt
+#define INT_SOURCE_USB_EP4ISR       19  // USB endpoint 4 interrupt
+#define INT_SOURCE_USB_EP5ISR       20  // USB endpoint 5 interrupt
+#define INT_SOURCE_USB_EP6ISR       21  // USB endpoint 6 interrupt
+#define INT_SOURCE_USB_USBISR       22  // USB general interrupt
+#define INT_SOURCE_USB_USBAISR      23  // USB core interrupt
+#define INT_SOURCE_USB_ANY          24  // OR of all USB interrupts
+#define INT_SOURCE_USB_DSPI_OVF     25  // DSPI overflow or underflow
+#define INT_SOURCE_USB_DSPI_RFOF    26  // receive FIFO overflow interrupt
+#define INT_SOURCE_USB_DSPI_RFDF    27  // receive FIFO drain interrupt
+#define INT_SOURCE_USB_DSPI_TFUF    28  // transmit FIFO underflow interrupt
+#define INT_SOURCE_USB_DSPI_TCF     29  // transfer complete interrupt
+#define INT_SOURCE_USB_DSPI_TFFF    30  // transfer FIFO fill interrupt
+#define INT_SOURCE_USB_DSPI_EOQF    31  // end of queue interrupt
+#define INT_SOURCE_PSC3             32  // PSC3 interrupt
+#define INT_SOURCE_PSC2             33  // PSC2 interrupt
+#define INT_SOURCE_PSC1             34  // PSC1 interrupt
+#define INT_SOURCE_PSC0             35  // PSC0 interrupt
+#define INT_SOURCE_CTIMERS          36  // combined source for comm timers
+#define INT_SOURCE_SEC              37  // SEC interrupt
+#define INT_SOURCE_FEC1             38  // FEC1 interrupt
+#define INT_SOURCE_FEC0             39  // FEC0 interrupt
+#define INT_SOURCE_I2C              40  // I2C interrupt
+#define INT_SOURCE_PCIARB           41  // PCI arbiter interrupt
+#define INT_SOURCE_CBPCI            42  // COMM bus PCI interrupt
+#define INT_SOURCE_XLBPCI           43  // XLB PCI interrupt
+#define INT_SOURCE_XLBARB           47  // XLBARB to PCI interrupt
+#define INT_SOURCE_DMA              48  // multichannel DMA interrupt
+#define INT_SOURCE_CAN0_ERROR       49  // FlexCAN error interrupt
+#define INT_SOURCE_CAN0_BUSOFF      50  // FlexCAN bus off interrupt
+#define INT_SOURCE_CAN0_MBOR        51  // message buffer ORed interrupt
+#define INT_SOURCE_SLT1             53  // slice timer 1 interrupt
+#define INT_SOURCE_SLT0             54  // slice timer 0 interrupt
+#define INT_SOURCE_CAN1_ERROR       55  // FlexCAN error interrupt
+#define INT_SOURCE_CAN1_BUSOFF      56  // FlexCAN bus off interrupt
+#define INT_SOURCE_CAN1_MBOR        57  // message buffer ORed interrupt
+#define INT_SOURCE_GPT3             59  // GPT3 timer interrupt
+#define INT_SOURCE_GPT2             60  // GPT2 timer interrupt
+#define INT_SOURCE_GPT1             61  // GPT1 timer interrupt
+#define INT_SOURCE_GPT0             62  // GPT0 timer interrupt
 
 
-#define FEC0_INTC_LVL	5			/* interrupt level for FEC0 */
-#define FEC0_INTC_PRI	1			/* interrupt priority for FEC0 */
+#define FEC0_INTC_LVL   6           /* interrupt level for FEC0 */
+#define FEC0_INTC_PRI   7           /* interrupt priority for FEC0 */
 
-#define FEC1_INTC_LVL	5			/* interrupt level for FEC1 */
-#define FEC1_INTC_PRI	0			/* interrupt priority for FEC1 */
+#define FEC1_INTC_LVL   6           /* interrupt level for FEC1 */
+#define FEC1_INTC_PRI   6           /* interrupt priority for FEC1 */
 
-#define FEC_INTC_LVL(x)		((x == 0) ? FEC0_INTC_LVL : FEC1_INTC_LVL)
-#define FEC_INTC_PRI(x)		((x == 0) ? FEC0_INTC_PRI : FEC1_INTC_PRI)
+#define FEC_INTC_LVL(x)     ((x == 0) ? FEC0_INTC_LVL : FEC1_INTC_LVL)
+#define FEC_INTC_PRI(x)     ((x == 0) ? FEC0_INTC_PRI : FEC1_INTC_PRI)
 
 #define FEC0RX_DMA_PRI      5
-#define FEC1RX_DMA_PRI      3
+#define FEC1RX_DMA_PRI      4
 #define FECRX_DMA_PRI(x)    ((x == 0) ? FEC0RX_DMA_PRI : FEC1RX_DMA_PRI)
-#define FEC0TX_DMA_PRI      6
-#define FEC1TX_DMA_PRI      4
+#define FEC0TX_DMA_PRI      2
+#define FEC1TX_DMA_PRI      1
 #define FECTX_DMA_PRI(x)    ((x == 0) ? FEC0TX_DMA_PRI : FEC1TX_DMA_PRI)
 
-extern int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority, uint8_t intr, void (*handler)(void));
+#if defined(MACHINE_FIREBEE)
 
-#define ISR_DBUG_ISR	0x01
-#define ISR_USER_ISR 	0x02
+/* Firebee FPGA interrupt controller */
+#define FBEE_INTR_CONTROL   * ((volatile uint32_t *) 0xf0010000)
+#define FBEE_INTR_ENABLE    * ((volatile uint32_t *) 0xf0010004)
+#define FBEE_INTR_CLEAR     * ((volatile uint32_t *) 0xf0010008)
+#define FBEE_INTR_PENDING   * ((volatile uint32_t *) 0xff01000c)
+
+/* register bits for Firebee FPGA-based interrupt controller */
+#define FBEE_INTR_PIC               (1 << 0)        /* PIC interrupt enable/pending/clear bit */
+#define FBEE_INTR_ETHERNET          (1 << 1)        /* ethernet PHY interrupt enable/pending/clear bit */
+#define FBEE_INTR_DVI               (1 << 2)        /* TFP410 monitor sense interrupt enable/pending/clear bit */
+#define FBEE_INTR_PCI_INTA          (1 << 3)        /* /PCIINTA enable/pending clear bit */
+#define FBEE_INTR_PCI_INTB          (1 << 4)        /* /PCIINTB enable/pending clear bit */
+#define FBEE_INTR_PCI_INTC          (1 << 5)        /* /PCIINTC enable/pending clear bit */
+#define FBEE_INTR_PCI_INTD          (1 << 6)        /* /PCIINTD enable/pending clear bit */
+#define FBEE_INTR_DSP               (1 << 7)        /* DSP interrupt enable/pending/clear bit */
+#define FBEE_INTR_VSYNC             (1 << 8)        /* VSYNC interrupt enable/pending/clear bit */
+#define FBEE_INTR_HSYNC             (1 << 9)        /* HSYNC interrupt enable/pending/clear bit */
+
+#define FBEE_INTR_INT_HSYNC_IRQ2    (1 << 26)       /* these bits are only meaningful for the FBEE_INTR_ENABLE register */
+#define FBEE_INTR_INT_CTR0_IRQ3     (1 << 27)
+#define FBEE_INTR_INT_VSYNC_IRQ4    (1 << 28)
+#define FBEE_INTR_INT_FPGA_IRQ5     (1 << 29)
+#define FBEE_INTR_INT_MFP_IRQ6      (1 << 30)
+#define FBEE_INTR_INT_IRQ7          (1 << 31)
+
+/*
+ * Atari MFP interrupt registers.
+ */
+
+#define FALCON_MFP_IERA     *((volatile uint8_t *) 0xfffffa07)
+#define FALCON_MFP_IERB     *((volatile uint8_t *) 0xfffffa09)
+#define FALCON_MFP_IPRA     *((volatile uint8_t *) 0xfffffa0b)
+#define FALCON_MFP_IPRB     *((volatile uint8_t *) 0xfffffa0d)
+#define FALCON_MFP_IMRA     *((volatile uint8_t *) 0xfffffa13)
+#define FALCON_MFP_IMRB     *((volatile uint8_t *) 0xfffffa15)
+
+#endif /* MACHINE_FIREBEE */
 
 extern void isr_init(void);
-extern int isr_register_handler(int vector, int (*handler)(void *, void *), void *hdev, void *harg);
-extern void isr_remove_handler(int (*handler)(void *, void *));
+extern bool isr_set_prio_and_level(int int_source, int priority, int level);
+extern bool isr_enable_int_source(int int_source);
+extern bool isr_register_handler(int vector, int level, int priority, bool (*handler)(void *, void *), void *hdev, void *harg);
+extern void isr_remove_handler(bool (*handler)(void *, void *));
 extern bool isr_execute_handler(int vector);
-extern int pic_interrupt_handler(void *arg1, void *arg2);
+extern bool pic_interrupt_handler(void *arg1, void *arg2);
+extern bool xlbpci_interrupt_handler(void *arg1, void *arg2);
+extern bool pciarb_interrupt_handler(void *arg1, void *arg2);
+extern bool gpt0_interrupt_handler(void *arg1, void *arg2);
+extern bool irq5_handler(void *arg1, void *arg2);
 #endif /* _INTERRUPTS_H_ */

include/mmu.h

@@ -58,12 +58,19 @@
 
 enum mmu_page_size
 {
-	MMU_PAGE_SIZE_1M	= 0,
-	MMU_PAGE_SIZE_4K	= 1,
-	MMU_PAGE_SIZE_8K	= 2,
-	MMU_PAGE_SIZE_1K	= 3
+    MMU_PAGE_SIZE_1M	= 0,
+    MMU_PAGE_SIZE_4K	= 1,
+    MMU_PAGE_SIZE_8K	= 2,
+    MMU_PAGE_SIZE_1K	= 3
 };
 
+#define SIZE_1M             0x100000        /* 1 Megabyte */
+#define SIZE_4K             0x1000          /* 4 KB */
+#define SIZE_8K             0x2000          /* 8 KB */
+#define SIZE_1K             0x400           /* 1 KB */
+
+#define DEFAULT_PAGE_SIZE   0x00100000      /* 1M pagesize */
+
 /*
  * cache modes
  */
@@ -83,15 +90,6 @@ enum mmu_page_size
 #define	ACCESS_WRITE	(1 << 1)
 #define ACCESS_EXECUTE	(1 << 2)
 
-struct mmu_map_flags
-{
-	unsigned cache_mode:2;
-	unsigned protection:1;
-	unsigned page_id:8;
-	unsigned access:3;
-	unsigned locked:1;
-	unsigned unused:17;
-};
 
 /*
  * global variables from linker script
@@ -99,7 +97,16 @@ struct mmu_map_flags
 extern long video_tlb;
 extern long video_sbt;
 
-extern void mmu_init(void);
-extern int mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, const struct mmu_map_flags *flags);
+struct mmu_page_descriptor;
 
+extern void mmu_init(void);
+extern int mmu_map_page(int32_t virt, int32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor *flags);
+
+/*
+ * API functions for the BaS driver interface
+ */
+extern int32_t mmu_map_data_page_locked(uint32_t address, uint32_t length, int asid);
+extern int32_t mmu_unlock_data_page(uint32_t address, uint32_t length, int asid);
+extern int32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb);
+extern uint32_t mmu_report_pagesize(void);
 #endif /* _MMU_H_ */

include/mod_devicetable.h

@@ -3,10 +3,14 @@
 
 #define PCI_ANY_ID (~0)
 
-struct pci_device_id {
-	unsigned long vendor, device;		/* Vendor and device ID or PCI_ANY_ID*/
-	unsigned long subvendor, subdevice;	/* Subsystem ID's or PCI_ANY_ID */
-	unsigned long class, class_mask;	/* (class,subclass,prog-if) triplet */
+struct pci_device_id
+{
+    unsigned long vendor;       /* Vendor and device ID or PCI_ANY_ID*/
+    unsigned long device;
+    unsigned long subvendor;    /* Subsystem ID's or PCI_ANY_ID */
+    unsigned long subdevice;
+    unsigned long class;        /* (class,subclass,prog-if) triplet */
+    unsigned long class_mask;
 	unsigned long driver_data;	/* Data private to the driver */
 };
 
@@ -15,7 +19,8 @@ struct pci_device_id {
 #define IEEE1394_MATCH_SPECIFIER_ID	0x0004
 #define IEEE1394_MATCH_VERSION		0x0008
 
-struct ieee1394_device_id {
+struct ieee1394_device_id
+{
 	unsigned long match_flags;
 	unsigned long vendor_id;
 	unsigned long model_id;
@@ -81,7 +86,8 @@ struct ieee1394_device_id {
  * matches towards the beginning of your table, so that driver_info can
  * record quirks of specific products.
  */
-struct usb_device_id {
+struct usb_device_id
+{
 	/* which fields to match against? */
 	unsigned short		match_flags;
 
@@ -106,10 +112,10 @@ struct usb_device_id {
 };
 
 /* Some useful macros to use to create struct usb_device_id */
-#define USB_DEVICE_ID_MATCH_VENDOR		0x0001
-#define USB_DEVICE_ID_MATCH_PRODUCT		0x0002
-#define USB_DEVICE_ID_MATCH_DEV_LO		0x0004
-#define USB_DEVICE_ID_MATCH_DEV_HI		0x0008
+#define USB_DEVICE_ID_MATCH_VENDOR          0x0001
+#define USB_DEVICE_ID_MATCH_PRODUCT         0x0002
+#define USB_DEVICE_ID_MATCH_DEV_LO          0x0004
+#define USB_DEVICE_ID_MATCH_DEV_HI          0x0008
 #define USB_DEVICE_ID_MATCH_DEV_CLASS		0x0010
 #define USB_DEVICE_ID_MATCH_DEV_SUBCLASS	0x0020
 #define USB_DEVICE_ID_MATCH_DEV_PROTOCOL	0x0040
@@ -118,18 +124,19 @@ struct usb_device_id {
 #define USB_DEVICE_ID_MATCH_INT_PROTOCOL	0x0200
 
 /* s390 CCW devices */
-struct ccw_device_id {
+struct ccw_device_id
+{
 	unsigned short	match_flags;	/* which fields to match against */
 
-	unsigned short	cu_type;	/* control unit type     */
-	unsigned short	dev_type;	/* device type           */
-	unsigned char	cu_model;	/* control unit model    */
-	unsigned char	dev_model;	/* device model          */
+    unsigned short	cu_type;        /* control unit type     */
+    unsigned short	dev_type;       /* device type           */
+    unsigned char	cu_model;       /* control unit model    */
+    unsigned char	dev_model;      /* device model          */
 
 	unsigned long driver_info;
 };
 
-#define CCW_DEVICE_ID_MATCH_CU_TYPE		0x01
+#define CCW_DEVICE_ID_MATCH_CU_TYPE         0x01
 #define CCW_DEVICE_ID_MATCH_CU_MODEL		0x02
 #define CCW_DEVICE_ID_MATCH_DEVICE_TYPE		0x04
 #define CCW_DEVICE_ID_MATCH_DEVICE_MODEL	0x08
@@ -138,15 +145,18 @@ struct ccw_device_id {
 #define PNP_ID_LEN	8
 #define PNP_MAX_DEVICES	8
 
-struct pnp_device_id {
+struct pnp_device_id
+{
 	unsigned char id[PNP_ID_LEN];
 	unsigned long driver_data;
 };
 
-struct pnp_card_device_id {
+struct pnp_card_device_id
+{
 	unsigned char id[PNP_ID_LEN];
 	unsigned long driver_data;
-	struct {
+    struct
+    {
 		unsigned char id[PNP_ID_LEN];
 	} devs[PNP_MAX_DEVICES];
 };
@@ -154,7 +164,8 @@ struct pnp_card_device_id {
 
 #define SERIO_ANY	0xff
 
-struct serio_device_id {
+struct serio_device_id
+{
 	unsigned char type;
 	unsigned char extra;
 	unsigned char id;

include/ohci.h

@@ -6,65 +6,63 @@
  *
  * usb-ohci.h
  */
- 
+
 #define USB_OHCI_MAX_ROOT_PORTS	4
 
 static int cc_to_error[16] =
 {
 
 /* mapping of the OHCI CC status to error codes */
-	/* No  Error  */	       0,
-	/* CRC Error  */	       USB_ST_CRC_ERR,
-	/* Bit Stuff  */	       USB_ST_BIT_ERR,
-	/* Data Togg  */	       USB_ST_CRC_ERR,
-	/* Stall      */	       USB_ST_STALLED,
-	/* DevNotResp */	       -1,
-	/* PIDCheck   */	       USB_ST_BIT_ERR,
-	/* UnExpPID   */	       USB_ST_BIT_ERR,
-	/* DataOver   */	       USB_ST_BUF_ERR,
-	/* DataUnder  */	       USB_ST_BUF_ERR,
-	/* reservd    */	       -1,
-	/* reservd    */	       -1,
-	/* BufferOver */	       USB_ST_BUF_ERR,
-	/* BuffUnder  */	       USB_ST_BUF_ERR,
-	/* Not Access */	       -1,
-	/* Not Access */	       -1
+    /* No  Error  */	       0,
+    /* CRC Error  */	       USB_ST_CRC_ERR,
+    /* Bit Stuff  */	       USB_ST_BIT_ERR,
+    /* Data Togg  */	       USB_ST_CRC_ERR,
+    /* Stall      */	       USB_ST_STALLED,
+    /* DevNotResp */	       -1,
+    /* PIDCheck   */	       USB_ST_BIT_ERR,
+    /* UnExpPID   */	       USB_ST_BIT_ERR,
+    /* DataOver   */	       USB_ST_BUF_ERR,
+    /* DataUnder  */	       USB_ST_BUF_ERR,
+    /* reservd    */	       -1,
+    /* reservd    */	       -1,
+    /* BufferOver */	       USB_ST_BUF_ERR,
+    /* BuffUnder  */	       USB_ST_BUF_ERR,
+    /* Not Access */	       -1,
+    /* Not Access */	       -1
 };
 
-#ifdef DEBUG_OHCI
 static const char *cc_to_string[16] =
 {
-	"No Error",
-	"CRC: Last data packet from endpoint contained a CRC error.",
-	"BITSTUFFING:\r\nLast data packet from endpoint contained a bit stuffing violation",
-	"DATATOGGLEMISMATCH:\r\n Last packet from endpoint had data toggle PID\r\n" \
-		     "that did not match the expected value.",
-	"STALL: TD was moved to the Done Queue because the endpoint returned a STALL PID",
-	"DEVICENOTRESPONDING:\r\nDevice did not respond to token (IN) or did\r\n" \
-		     "not provide a handshake (OUT)",
-	"PIDCHECKFAILURE:\r\nCheck bits on PID from endpoint failed on data PID\r\n"\
-		     "(IN) or handshake (OUT)",
-	"UNEXPECTEDPID:\r\nReceive PID was not valid when encountered or PID\r\n" \
-		     "value is not defined.",
-	"DATAOVERRUN:\r\nThe amount of data returned by the endpoint exceeded\r\n" \
-		     "either the size of the maximum data packet allowed\r\n" \
-		     "from the endpoint (found in MaximumPacketSize field\r\n" \
-		     "of ED) or the remaining buffer size.",
-	"DATAUNDERRUN:\r\nThe endpoint returned less than MaximumPacketSize\r\n" \
-		     "and that amount was not sufficient to fill the\r\n" \
-		     "specified buffer",
-	"reserved1",
-	"reserved2",
-	"BUFFEROVERRUN:\r\nDuring an IN, HC received data from endpoint faster\r\n" \
-		     "than it could be written to system memory",
-	"BUFFERUNDERRUN:\r\nDuring an OUT, HC could not retrieve data from\r\n" \
-		     "system memory fast enough to keep up with data USB data rate.",
-	"NOT ACCESSED:\r\nThis code is set by software before the TD is placed\r\n" \
-		     "on a list to be processed by the HC.(1)",
-	"NOT ACCESSED:\r\nThis code is set by software before the TD is placed\r\n" \
-		     "on a list to be processed by the HC.(2)",
+    "No Error",
+    "CRC: Last data packet from endpoint contained a CRC error.",
+    "BITSTUFFING:\r\nLast data packet from endpoint contained a bit stuffing violation",
+    "DATATOGGLEMISMATCH:\r\n Last packet from endpoint had data toggle PID\r\n" \
+             "that did not match the expected value.",
+    "STALL: TD was moved to the Done Queue because the endpoint returned a STALL PID",
+    "DEVICENOTRESPONDING:\r\nDevice did not respond to token (IN) or did\r\n" \
+             "not provide a handshake (OUT)",
+    "PIDCHECKFAILURE:\r\nCheck bits on PID from endpoint failed on data PID\r\n"\
+             "(IN) or handshake (OUT)",
+    "UNEXPECTEDPID:\r\nReceive PID was not valid when encountered or PID\r\n" \
+             "value is not defined.",
+    "DATAOVERRUN:\r\nThe amount of data returned by the endpoint exceeded\r\n" \
+             "either the size of the maximum data packet allowed\r\n" \
+             "from the endpoint (found in MaximumPacketSize field\r\n" \
+             "of ED) or the remaining buffer size.",
+    "DATAUNDERRUN:\r\nThe endpoint returned less than MaximumPacketSize\r\n" \
+             "and that amount was not sufficient to fill the\r\n" \
+             "specified buffer",
+    "reserved1",
+    "reserved2",
+    "BUFFEROVERRUN:\r\nDuring an IN, HC received data from endpoint faster\r\n" \
+             "than it could be written to system memory",
+    "BUFFERUNDERRUN:\r\nDuring an OUT, HC could not retrieve data from\r\n" \
+             "system memory fast enough to keep up with data USB data rate.",
+    "NOT ACCESSED:\r\nThis code is set by software before the TD is placed\r\n" \
+             "on a list to be processed by the HC.(1)",
+    "NOT ACCESSED:\r\nThis code is set by software before the TD is placed\r\n" \
+             "on a list to be processed by the HC.(2)",
 };
-#endif /* DEBUG_OHCI */
 
 /* ED States */
 
@@ -77,24 +75,24 @@ static const char *cc_to_string[16] =
 /* usb_ohci_ed */
 struct ed
 {
-	uint32_t hwINFO;
-	uint32_t hwTailP;
-	uint32_t hwHeadP;
-	uint32_t hwNextED;
+    uint32_t hwINFO;
+    uint32_t hwTailP;
+    uint32_t hwHeadP;
+    uint32_t hwNextED;
 
-	struct ed *ed_prev;
-	uint8_t int_period;
-	uint8_t int_branch;
-	uint8_t int_load;
-	uint8_t int_interval;
-	uint8_t state;
-	uint8_t type;
-	uint16_t last_iso;
-	struct ed *ed_rm_list;
+    struct ed *ed_prev;
+    uint8_t int_period;
+    uint8_t int_branch;
+    uint8_t int_load;
+    uint8_t int_interval;
+    uint8_t state;
+    uint8_t type;
+    uint16_t last_iso;
+    struct ed *ed_rm_list;
 
-	struct usb_device *usb_dev;
-	void *purb;
-	uint32_t unused[2];
+    struct usb_device *usb_dev;
+    void *purb;
+    uint32_t unused[2];
 } __attribute__((aligned(16)));
 typedef struct ed ed_t;
 
@@ -139,21 +137,21 @@ typedef struct ed ed_t;
 
 struct td
 {
-	uint32_t hwINFO;
-	uint32_t hwCBP;		/* Current Buffer Pointer */
-	uint32_t hwNextTD;		/* Next TD Pointer */
-	uint32_t hwBE;		/* Memory Buffer End Pointer */
+    uint32_t hwINFO;
+    uint32_t hwCBP;		/* Current Buffer Pointer */
+    uint32_t hwNextTD;		/* Next TD Pointer */
+    uint32_t hwBE;		/* Memory Buffer End Pointer */
 
-	uint16_t hwPSW[MAXPSW];
-	uint8_t unused;
-	uint8_t index;
-	struct ed *ed;
-	struct td *next_dl_td;
-	struct usb_device *usb_dev;
-	int transfer_len;
-	uint32_t data;
+    uint16_t hwPSW[MAXPSW];
+    uint8_t unused;
+    uint8_t index;
+    struct ed *ed;
+    struct td *next_dl_td;
+    struct usb_device *usb_dev;
+    int transfer_len;
+    uint32_t data;
 
-	uint32_t unused2[2];
+    uint32_t unused2[2];
 } __attribute__((aligned(32)));
 typedef struct td td_t;
 
@@ -168,16 +166,16 @@ typedef struct td td_t;
 #define NUM_INTS 32	/* part of the OHCI standard */
 struct ohci_hcca
 {
-	uint32_t	int_table[NUM_INTS];	/* Interrupt ED table */
+    uint32_t	int_table[NUM_INTS];	/* Interrupt ED table */
 #if defined(CONFIG_MPC5200)
-	uint16_t	pad1;			/* set to 0 on each frame_no change */
-	uint16_t	frame_no;		/* current frame number */
+    uint16_t	pad1;			/* set to 0 on each frame_no change */
+    uint16_t	frame_no;		/* current frame number */
 #else
-	uint16_t	frame_no;		/* current frame number */
-	uint16_t	pad1;			/* set to 0 on each frame_no change */
+    uint16_t	frame_no;		/* current frame number */
+    uint16_t	pad1;			/* set to 0 on each frame_no change */
 #endif
-	uint32_t	done_head;		/* info returned for an interrupt */
-	uint8_t		reserved_for_hc[116];
+    uint32_t	done_head;		/* info returned for an interrupt */
+    uint8_t		reserved_for_hc[116];
 } __attribute__((aligned(256)));
 
 /*
@@ -187,35 +185,35 @@ struct ohci_hcca
  */
 struct ohci_regs
 {
-	/* control and status registers */
-	uint32_t	revision;
-	uint32_t	control;
-	uint32_t	cmdstatus;
-	uint32_t	intrstatus;
-	uint32_t	intrenable;
-	uint32_t	intrdisable;
-	/* memory pointers */
-	uint32_t	hcca;
-	uint32_t	ed_periodcurrent;
-	uint32_t	ed_controlhead;
-	uint32_t	ed_controlcurrent;
-	uint32_t	ed_bulkhead;
-	uint32_t	ed_bulkcurrent;
-	uint32_t	donehead;
-	/* frame counters */
-	uint32_t	fminterval;
-	uint32_t	fmremaining;
-	uint32_t	fmnumber;
-	uint32_t	periodicstart;
-	uint32_t	lsthresh;
-	/* Root hub ports */
+    /* control and status registers */
+    uint32_t	revision;
+    uint32_t	control;
+    uint32_t	cmdstatus;
+    uint32_t	intrstatus;
+    uint32_t	intrenable;
+    uint32_t	intrdisable;
+    /* memory pointers */
+    uint32_t	hcca;
+    uint32_t	ed_periodcurrent;
+    uint32_t	ed_controlhead;
+    uint32_t	ed_controlcurrent;
+    uint32_t	ed_bulkhead;
+    uint32_t	ed_bulkcurrent;
+    uint32_t	donehead;
+    /* frame counters */
+    uint32_t	fminterval;
+    uint32_t	fmremaining;
+    uint32_t	fmnumber;
+    uint32_t	periodicstart;
+    uint32_t	lsthresh;
+    /* Root hub ports */
     struct	ohci_roothub_regs
     {
-		uint32_t	a;
-		uint32_t	b;
-		uint32_t	status;
-		uint32_t	portstatus[USB_OHCI_MAX_ROOT_PORTS];
-	} roothub;
+        uint32_t	a;
+        uint32_t	b;
+        uint32_t	status;
+        uint32_t	portstatus[USB_OHCI_MAX_ROOT_PORTS];
+    } roothub;
 } __attribute__((aligned(32)));
 
 /* Some EHCI controls */
@@ -272,11 +270,11 @@ struct ohci_regs
 /* Virtual Root HUB */
 struct virt_root_hub
 {
-	int devnum; /* Address of Root Hub endpoint */
-	void *dev;  /* was urb */
-	void *int_addr;
-	int send;
-	int interval;
+    int devnum; /* Address of Root Hub endpoint */
+    void *dev;  /* was urb */
+    void *int_addr;
+    int send;
+    int interval;
 };
 
 /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
@@ -374,18 +372,18 @@ struct virt_root_hub
 #define N_URB_TD 48
 typedef struct
 {
-	ed_t *ed;
-	uint16_t length;	/* number of tds associated with this request */
-	uint16_t td_cnt;	/* number of tds already serviced */
-	struct usb_device *dev;
-	int   state;
-	uint32_t pipe;
-	void *transfer_buffer;
-	int transfer_buffer_length;
-	int interval;
-	int actual_length;
-	int finished;
-	td_t *td[N_URB_TD];	/* list pointer to all corresponding TDs associated with this request */
+    ed_t *ed;
+    uint16_t length;	/* number of tds associated with this request */
+    uint16_t td_cnt;	/* number of tds already serviced */
+    struct usb_device *dev;
+    int   state;
+    uint32_t pipe;
+    void *transfer_buffer;
+    int transfer_buffer_length;
+    int interval;
+    int actual_length;
+    int finished;
+    td_t *td[N_URB_TD];	/* list pointer to all corresponding TDs associated with this request */
 } urb_priv_t;
 #define URB_DEL 1
 
@@ -393,8 +391,8 @@ typedef struct
 
 struct ohci_device
 {
-	ed_t	ed[NUM_EDS];
-	int ed_cnt;
+    ed_t	ed[NUM_EDS];
+    int ed_cnt;
 };
 
 /*
@@ -406,45 +404,45 @@ struct ohci_device
 
 typedef struct ohci
 {
-	/* ------- common part -------- */
-	long handle;              /* PCI BIOS */
-	const struct pci_device_id *ent;
-	int usbnum;
+    /* ------- common part -------- */
+    long handle;              /* PCI BIOS */
+    const struct pci_device_id *ent;
+    int usbnum;
   /* ---- end of common part ---- */
-	int big_endian;           /* PCI BIOS */
-	int controller;
-	struct ohci_hcca *hcca_unaligned;
-	struct ohci_hcca *hcca;		/* hcca */
-	td_t *td_unaligned;
-	struct ohci_device *ohci_dev_unaligned;
-	/* this allocates EDs for all possible endpoints */
-	struct ohci_device *ohci_dev;
+    int big_endian;           /* PCI BIOS */
+    int controller;
+    struct ohci_hcca *hcca_unaligned;
+    struct ohci_hcca *hcca;		/* hcca */
+    td_t *td_unaligned;
+    struct ohci_device *ohci_dev_unaligned;
+    /* this allocates EDs for all possible endpoints */
+    struct ohci_device *ohci_dev;
 
-	int irq_enabled;
-	int stat_irq;
-	int irq;
-	int disabled;			/* e.g. got a UE, we're hung */
-	int sleeping;
+    int irq_enabled;
+    int stat_irq;
+    int irq;
+    int disabled;			/* e.g. got a UE, we're hung */
+    int sleeping;
 #define OHCI_FLAGS_NEC 0x80000000
-	uint32_t flags;		/* for HC bugs */
+    uint32_t flags;		/* for HC bugs */
 
-	uint32_t offset;
-	uint32_t dma_offset;
-	struct ohci_regs *regs; /* OHCI controller's memory */
+    uint32_t offset;
+    uint32_t dma_offset;
+    struct ohci_regs *regs; /* OHCI controller's memory */
 
-	int ohci_int_load[32];	 /* load of the 32 Interrupt Chains (for load balancing)*/
-	ed_t *ed_rm_list[2];	 /* lists of all endpoints to be removed */
-	ed_t *ed_bulktail;	 /* last endpoint of bulk list */
-	ed_t *ed_controltail;	 /* last endpoint of control list */
-	int intrstatus;
-	uint32_t hc_control;		/* copy of the hc control reg */
-	uint32_t ndp;          /* copy NDP from roothub_a */
-	struct virt_root_hub rh;
+    int ohci_int_load[32];	 /* load of the 32 Interrupt Chains (for load balancing)*/
+    ed_t *ed_rm_list[2];	 /* lists of all endpoints to be removed */
+    ed_t *ed_bulktail;	 /* last endpoint of bulk list */
+    ed_t *ed_controltail;	 /* last endpoint of control list */
+    int intrstatus;
+    uint32_t hc_control;		/* copy of the hc control reg */
+    uint32_t ndp;          /* copy NDP from roothub_a */
+    struct virt_root_hub rh;
 
-	const char *slot_name;
+    const char *slot_name;
 
-	/* device which was disconnected */
-	struct usb_device *devgone;
+    /* device which was disconnected */
+    struct usb_device *devgone;
 } ohci_t;
 
 /* hcd */
@@ -460,7 +458,7 @@ static ed_t * ep_add_ed(ohci_t * ohci, struct usb_device * usb_dev, uint32_t pip
 
 static inline void ed_free(struct ed *ed)
 {
-	ed->usb_dev = NULL;
+    ed->usb_dev = NULL;
 }
 
 

include/pci.h

@@ -44,13 +44,13 @@
 #define PCIHTR                0x0E   /* PCI Header Type Register            */
 #define PCIBISTR              0x0F   /* PCI Build-In Self Test Register     */
 #define PCIBAR0               0x10   /* PCI Base Address Register for Memory
-										Accesses to Local, Runtime, and DMA */
+                                        Accesses to Local, Runtime, and DMA */
 #define PCIBAR1               0x14   /* PCI Base Address Register for I/O
-										Accesses to Local, Runtime, and DMA */
+                                        Accesses to Local, Runtime, and DMA */
 #define PCIBAR2               0x18   /* PCI Base Address Register for Memory
-										Accesses to Local Address Space 0   */
+                                        Accesses to Local Address Space 0   */
 #define PCIBAR3               0x1C   /* PCI Base Address Register for Memory
-										Accesses to Local Address Space 1   */
+                                        Accesses to Local Address Space 1   */
 #define PCIBAR4               0x20   /* PCI Base Address Register, reserved */
 #define PCIBAR5               0x24   /* PCI Base Address Register, reserved */
 #define PCICIS                0x28   /* PCI Cardbus CIS Pointer, not support*/
@@ -64,7 +64,7 @@
 #define PCIMLR                0x3F   /* PCI Max_Lat Register                */
 #define PMCAPID               0x40   /* Power Management Capability ID      */
 #define PMNEXT                0x41   /* Power Management Next Capability
-										Pointer                             */
+                                        Pointer                             */
 #define PMC                   0x42   /* Power Management Capabilities       */
 #define PMCSR                 0x44   /* Power Management Control/Status     */
 #define PMCSR_BSE             0x46   /* PMCSR Bridge Support Extensions     */
@@ -74,7 +74,7 @@
 #define HS_CSR                0x4A   /* Hot Swap Control/Status             */
 #define PVPDCNTL              0x4C   /* PCI Vital Product Data Control      */
 #define PVPD_NEXT             0x4D   /* PCI Vital Product Data Next
-										Capability Pointer                  */
+                                        Capability Pointer                  */
 #define PVPDAD                0x4E   /* PCI Vital Product Data Address      */
 #define PVPDATA               0x50   /* PCI VPD Data                        */
 
@@ -91,9 +91,12 @@
 #define PCICSR_STEPPING		(1 << 7)	/* if set: stepping enabled */
 #define PCICSR_SERR			(1 << 8)	/* if set: SERR pin enabled */
 #define PCICSR_FAST_BTOB_E	(1 << 9)	/* if set: fast back-to-back enabled */
+#define PCICSR_INT_DISABLE  (1 << 10)   /* if set: disable interrupts from this device */
 /*
  * bit definitions for PCICSR upper half (Status Register)
  */
+#define PCICSR_INTERRUPT    (1 << 3)    /* device requested interrupt */
+#define PCICSR_CAPABILITIES (1 << 4)    /* if set, capabilities pointer is valid */
 #define PCICSR_66MHZ		(1 << 5)	/* 66 MHz capable */
 #define PCICSR_UDF			(1 << 6)	/* UDF supported */
 #define PCICSR_FAST_BTOB	(1 << 7)	/* Fast back-to-back enabled */
@@ -125,18 +128,18 @@
 
 struct pci_rd          /* structure of resource descriptor    */
 {
-	unsigned short next;               /* length of the following structure   */
-	unsigned short flags;              /* type of resource and misc. flags    */
-	unsigned long start;               /* start-address of resource           */
-	unsigned long length;              /* length of resource                  */
-	unsigned long offset;              /* offset PCI to phys. CPU Address     */
-	unsigned long dmaoffset;           /* offset for DMA-transfers            */
+    unsigned short next;               /* length of the following structure   */
+    unsigned short flags;              /* type of resource and misc. flags    */
+    unsigned long start;               /* start-address of resource           */
+    unsigned long length;              /* length of resource                  */
+    unsigned long offset;              /* offset PCI to phys. CPU Address     */
+    unsigned long dmaoffset;           /* offset for DMA-transfers            */
 } __attribute__ ((packed));
 
 typedef struct                       /* structure of address conversion     */
 {
-	unsigned long adr;                 /* calculated address (CPU<->PCI)      */
-	unsigned long len;                 /* length of memory range              */
+    unsigned long adr;                 /* calculated address (CPU<->PCI)      */
+    unsigned long len;                 /* length of memory range              */
 } PCI_CONV_ADR;
 
 /******************************************************************************/
@@ -224,10 +227,14 @@ typedef struct                       /* structure of address conversion     */
 extern void init_eport(void);
 extern void init_xlbus_arbiter(void);
 extern void init_pci(void);
+extern int pci_handle2index(int32_t handle);
 
 extern int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index);
 extern int32_t pci_find_classcode(uint32_t classcode, int index);
 
+extern int32_t pci_get_interrupt_cause(void);
+extern int32_t pci_call_interrupt_chain(int32_t handle, int32_t data);
+
 /*
  * match bits for pci_find_classcode()
  */
@@ -243,7 +250,9 @@ extern int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t va
 extern int32_t pci_write_config_word(int32_t handle, int offset, uint16_t value);
 extern int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value);
 
-extern int32_t pci_hook_interrupt(int32_t handle, void *interrupt_handler, void *parameter);
+typedef int (*pci_interrupt_handler)(int param);
+
+extern int32_t pci_hook_interrupt(int32_t handle, void *handler, void *parameter);
 extern int32_t pci_unhook_interrupt(int32_t handle);
 
 extern struct pci_rd *pci_get_resource(int32_t handle);
@@ -332,14 +341,13 @@ extern int32_t wrapper_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
 extern int32_t wrapper_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
 
 #define PCI_MK_CONF_ADDR(bus, device, function)	(MCF_PCI_PCICAR_E | \
-												((bus) << 16) | \
-												((device << 8) | \
-												(function))
+                                                ((bus) << 16) | \
+                                                ((device << 8) | \
+                                                (function))
 
 #define PCI_HANDLE(bus, slot, function)	(0 | ((bus & 0xff) << 10 | (slot & 0x1f) << 3 | (function & 7)))
 #define PCI_BUS_FROM_HANDLE(h)				(((h) & 0xff00) >> 10)
 #define PCI_DEVICE_FROM_HANDLE(h)			(((h) & 0xf8) >> 3)
 #define PCI_FUNCTION_FROM_HANDLE(h)			(((h) & 0x7))
 
-extern void chip_errata_135(void); /* needed in ohci-hcd.c */
 #endif /* _PCI_H_ */

include/pci_ids.h

@@ -598,8 +598,10 @@
 #define PCI_DEVICE_ID_NEC_VL		0x0016 /* PCI-VL Bridge */
 #define PCI_DEVICE_ID_NEC_STARALPHA2	0x002c /* STAR ALPHA2 */
 #define PCI_DEVICE_ID_NEC_CBUS_2	0x002d /* PCI-Cbus Bridge */
+#define PCI_DEVICE_ID_NEC_USB_A     0x0031
 #define PCI_DEVICE_ID_NEC_USB		0x0035 /* PCI-USB Host */
 #define PCI_DEVICE_ID_NEC_USB_2		0x00e0 /* PCI-USB 2 Host */
+#define PCI_DEVICE_ID_NEC_USB_3     0x00f0
 #define PCI_DEVICE_ID_NEC_CBUS_3	0x003b
 #define PCI_DEVICE_ID_NEC_NAPCCARD	0x003e
 #define PCI_DEVICE_ID_NEC_PCX2		0x0046 /* PowerVR */
@@ -798,7 +800,7 @@
 
 #define PCI_VENDOR_ID_ANIGMA		0x1051
 #define PCI_DEVICE_ID_ANIGMA_MC145575	0x0100
-  
+
 #define PCI_VENDOR_ID_EFAR		0x1055
 #define PCI_DEVICE_ID_EFAR_SLC90E66_1	0x9130
 #define PCI_DEVICE_ID_EFAR_SLC90E66_0	0x9460
@@ -1507,7 +1509,7 @@
 
 #define PCI_VENDOR_ID_ZIATECH		0x1138
 #define PCI_DEVICE_ID_ZIATECH_5550_HC	0x5550
- 
+
 #define PCI_VENDOR_ID_CYCLONE		0x113c
 #define PCI_DEVICE_ID_CYCLONE_SDK	0x0001
 
@@ -1707,8 +1709,8 @@
 #define PCI_DEVICE_ID_RP8OCTA		0x0005
 #define PCI_DEVICE_ID_RP8J		0x0006
 #define PCI_DEVICE_ID_RP4J		0x0007
-#define PCI_DEVICE_ID_RP8SNI		0x0008	
-#define PCI_DEVICE_ID_RP16SNI		0x0009	
+#define PCI_DEVICE_ID_RP8SNI		0x0008
+#define PCI_DEVICE_ID_RP16SNI		0x0009
 #define PCI_DEVICE_ID_RPP4		0x000A
 #define PCI_DEVICE_ID_RPP8		0x000B
 #define PCI_DEVICE_ID_RP8M		0x000C
@@ -1719,9 +1721,9 @@
 #define PCI_DEVICE_ID_URP8INTF		0x0802
 #define PCI_DEVICE_ID_URP16INTF		0x0803
 #define PCI_DEVICE_ID_URP8OCTA		0x0805
-#define PCI_DEVICE_ID_UPCI_RM3_8PORT	0x080C       
+#define PCI_DEVICE_ID_UPCI_RM3_8PORT	0x080C
 #define PCI_DEVICE_ID_UPCI_RM3_4PORT	0x080D
-#define PCI_DEVICE_ID_CRP16INTF		0x0903       
+#define PCI_DEVICE_ID_CRP16INTF		0x0903
 
 #define PCI_VENDOR_ID_CYCLADES		0x120e
 #define PCI_DEVICE_ID_CYCLOM_Y_Lo	0x0100
@@ -2143,7 +2145,7 @@
 #define PCI_DEVICE_ID_RASTEL_2PORT	0x2000
 
 #define PCI_VENDOR_ID_ZOLTRIX		0x15b0
-#define PCI_DEVICE_ID_ZOLTRIX_2BD0	0x2bd0 
+#define PCI_DEVICE_ID_ZOLTRIX_2BD0	0x2bd0
 
 #define PCI_VENDOR_ID_MELLANOX		0x15b3
 #define PCI_DEVICE_ID_MELLANOX_TAVOR	0x5a44
@@ -2288,8 +2290,8 @@
 #define PCI_DEVICE_ID_INTEL_82092AA_0	0x1221
 #define PCI_DEVICE_ID_INTEL_82092AA_1	0x1222
 #define PCI_DEVICE_ID_INTEL_7116	0x1223
-#define PCI_DEVICE_ID_INTEL_7505_0	0x2550  
-#define PCI_DEVICE_ID_INTEL_7505_1	0x2552  
+#define PCI_DEVICE_ID_INTEL_7505_0	0x2550
+#define PCI_DEVICE_ID_INTEL_7505_1	0x2552
 #define PCI_DEVICE_ID_INTEL_7205_0	0x255d
 #define PCI_DEVICE_ID_INTEL_82596	0x1226
 #define PCI_DEVICE_ID_INTEL_82865	0x1227

include/usb.h

@@ -39,7 +39,7 @@ extern long *tab_funcs_pci;
 #define __u8 uint8_t
 #define __u16 uint16_t
 #define __u32 uint32_t
-#define u8 uint8_t
+//#define u8 uint8_t
 #define u16 uint16_t
 #define u32 uint32_t
 #define uint8_t uint8_t
@@ -55,179 +55,182 @@ extern int sprintD(char *s, const char *fmt, ...);
 #define USB_ALTSETTINGALLOC		4
 #define USB_MAXALTSETTING		128	/* Hard limit */
 
-#define USB_MAX_BUS           3
-#define USB_MAX_DEVICE       16
-#define USB_MAXCONFIG         8
-#define USB_MAXINTERFACES     8
-#define USB_MAXENDPOINTS     16
-#define USB_MAXCHILDREN       8	/* This is arbitrary */
-#define USB_MAX_HUB          16
+#define USB_MAX_BUS             3
+#define USB_MAX_DEVICE          16
+#define USB_MAXCONFIG           8
+#define USB_MAXINTERFACES       8
+#define USB_MAXENDPOINTS        16
+#define USB_MAXCHILDREN         8	/* This is arbitrary */
+#define USB_MAX_HUB             16
 
-#define USB_CNTL_TIMEOUT 100 /* 100ms timeout */
+#define USB_CNTL_TIMEOUT 100    /* 100 ms timeout */
 
 #define USB_BUFSIZ	512
 
 /* String descriptor */
 struct usb_string_descriptor
 {
-	uint8_t	bLength;
-	uint8_t	bDescriptorType;
-	uint16_t	wData[1];
+    uint8_t	bLength;
+    uint8_t	bDescriptorType;
+    uint16_t	wData[1];
 } __attribute__ ((packed));
 
 /* device request (setup) */
 struct devrequest
 {
-	uint8_t	requesttype;
-	uint8_t	request;
-	uint16_t	value;
-	uint16_t	index;
-	uint16_t	length;
+    uint8_t	requesttype;
+    uint8_t	request;
+    uint16_t	value;
+    uint16_t	index;
+    uint16_t	length;
 } __attribute__ ((packed));
 
 /* All standard descriptors have these 2 fields in common */
 struct usb_descriptor_header
 {
-	uint8_t	bLength;
-	uint8_t	bDescriptorType;
+    uint8_t	bLength;
+    uint8_t	bDescriptorType;
 } __attribute__ ((packed));
 
 /* Device descriptor */
 struct usb_device_descriptor
 {
-	uint8_t	bLength;
-	uint8_t	bDescriptorType;
-	uint16_t	bcdUSB;
-	uint8_t	bDeviceClass;
-	uint8_t	bDeviceSubClass;
-	uint8_t	bDeviceProtocol;
-	uint8_t	bMaxPacketSize0;
-	uint16_t	idVendor;
-	uint16_t	idProduct;
-	uint16_t	bcdDevice;
-	uint8_t	iManufacturer;
-	uint8_t	iProduct;
-	uint8_t	iSerialNumber;
-	uint8_t	bNumConfigurations;
+    uint8_t	bLength;
+    uint8_t	bDescriptorType;
+    uint16_t bcdUSB;
+    uint8_t	bDeviceClass;
+    uint8_t	bDeviceSubClass;
+    uint8_t	bDeviceProtocol;
+    uint8_t	bMaxPacketSize0;
+    uint16_t idVendor;
+    uint16_t idProduct;
+    uint16_t bcdDevice;
+    uint8_t	iManufacturer;
+    uint8_t	iProduct;
+    uint8_t	iSerialNumber;
+    uint8_t	bNumConfigurations;
 } __attribute__ ((packed));
 
 /* Endpoint descriptor */
 struct usb_endpoint_descriptor
 {
-	uint8_t	bLength;
-	uint8_t	bDescriptorType;
-	uint8_t	bEndpointAddress;
-	uint8_t	bmAttributes;
-	uint16_t	wMaxPacketSize;
-	uint8_t	bInterval;
-	uint8_t	bRefresh;
-	uint8_t	bSynchAddress;
+    uint8_t	bLength;
+    uint8_t	bDescriptorType;
+    uint8_t	bEndpointAddress;
+    uint8_t	bmAttributes;
+    uint16_t wMaxPacketSize;
+    uint8_t	bInterval;
+    uint8_t	bRefresh;
+    uint8_t	bSynchAddress;
 } __attribute__ ((packed)) __attribute__ ((aligned(2)));
 
 /* Interface descriptor */
 struct usb_interface_descriptor
 {
-	uint8_t	bLength;
-	uint8_t	bDescriptorType;
-	uint8_t	bInterfaceNumber;
-	uint8_t	bAlternateSetting;
-	uint8_t	bNumEndpoints;
-	uint8_t	bInterfaceClass;
-	uint8_t	bInterfaceSubClass;
-	uint8_t	bInterfaceProtocol;
-	uint8_t	iInterface;
+    uint8_t	bLength;
+    uint8_t	bDescriptorType;
+    uint8_t	bInterfaceNumber;
+    uint8_t	bAlternateSetting;
+    uint8_t	bNumEndpoints;
+    uint8_t	bInterfaceClass;
+    uint8_t	bInterfaceSubClass;
+    uint8_t	bInterfaceProtocol;
+    uint8_t	iInterface;
 
-	uint8_t	no_of_ep;
-	uint8_t	num_altsetting;
-	uint8_t	act_altsetting;
+    uint8_t	no_of_ep;
+    uint8_t	num_altsetting;
+    uint8_t	act_altsetting;
 
-	struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
+    struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
 } __attribute__ ((packed));
 
 
 /* Configuration descriptor information.. */
 struct usb_config_descriptor
 {
-	uint8_t	bLength;
-	uint8_t	bDescriptorType;
-	uint16_t	wTotalLength;
-	uint8_t	bNumInterfaces;
-	uint8_t	bConfigurationValue;
-	uint8_t	iConfiguration;
-	uint8_t	bmAttributes;
-	uint8_t	MaxPower;
+    uint8_t	bLength;
+    uint8_t	bDescriptorType;
+    uint16_t	wTotalLength;
+    uint8_t	bNumInterfaces;
+    uint8_t	bConfigurationValue;
+    uint8_t	iConfiguration;
+    uint8_t	bmAttributes;
+    uint8_t	MaxPower;
 
-	uint8_t	no_of_if;	/* number of interfaces */
-	struct usb_interface_descriptor if_desc[USB_MAXINTERFACES];
+    uint8_t	no_of_if;	/* number of interfaces */
+    struct usb_interface_descriptor if_desc[USB_MAXINTERFACES];
 } __attribute__ ((packed));
 
 enum
 {
-	/* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */
-	PACKET_SIZE_8   = 0,
-	PACKET_SIZE_16  = 1,
-	PACKET_SIZE_32  = 2,
-	PACKET_SIZE_64  = 3,
+    /* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */
+    PACKET_SIZE_8   = 0,
+    PACKET_SIZE_16  = 1,
+    PACKET_SIZE_32  = 2,
+    PACKET_SIZE_64  = 3,
 };
 
 struct usb_device
 {
-	int	devnum;			/* Device number on USB bus */
-	int	speed;			/* full/low/high */
-	char mf[32];			/* manufacturer */
-	char prod[32];		/* product */
-	char serial[32];		/* serial number */
+    int	devnum;             /* Device number on USB bus */
+    int	speed;              /* full/low/high */
+    char mf[32];			/* manufacturer */
+    char prod[32];          /* product */
+    char serial[32];		/* serial number */
 
-	/* Maximum packet size; one of: PACKET_SIZE_* */
-	int maxpacketsize;
-	/* one bit for each endpoint ([0] = IN, [1] = OUT) */
-	unsigned int toggle[2];
-	/* endpoint halts; one bit per endpoint # & direction;
-	 * [0] = IN, [1] = OUT
-	 */
-	unsigned int halted[2];
-	int epmaxpacketin[16];		/* INput endpoint specific maximums */
-	int epmaxpacketout[16];		/* OUTput endpoint specific maximums */
+    /* Maximum packet size; one of: PACKET_SIZE_* */
+    int maxpacketsize;
 
-	int configno;			/* selected config number */
-	struct usb_device_descriptor descriptor; /* Device Descriptor */
-	struct usb_config_descriptor config; /* config descriptor */
+    /* one bit for each endpoint ([0] = IN, [1] = OUT) */
+    unsigned int toggle[2];
 
-	int have_langid;		/* whether string_langid is valid yet */
-	int string_langid;		/* language ID for strings */
-	int (*irq_handle)(struct usb_device *dev);
-	uint32_t irq_status;
-	int irq_act_len;		/* transfered bytes */
-	void *privptr;
-	/*
-	 * Child devices -  if this is a hub device
-	 * Each instance needs its own set of data structures.
-	 */
-	uint32_t status;
-	int act_len;			/* transfered bytes */
-	int maxchild;			/* Number of ports if hub */
-	int portnr;
-	struct usb_device *parent;
-	struct usb_device *children[USB_MAXCHILDREN];
-	void *priv_hcd;
-	int (*deregister)(struct usb_device *dev);
+    /* endpoint halts; one bit per endpoint # & direction;
+     * [0] = IN, [1] = OUT
+     */
+    unsigned int halted[2];
+    int epmaxpacketin[16];		/* INput endpoint specific maximums */
+    int epmaxpacketout[16];		/* OUTput endpoint specific maximums */
 
-	struct usb_hub_device *hub;
-	int usbnum;
+    int configno;               /* selected config number */
+    struct usb_device_descriptor descriptor;    /* Device Descriptor */
+    struct usb_config_descriptor config;        /* config descriptor */
+
+    int have_langid;            /* whether string_langid is valid yet */
+    int string_langid;          /* language ID for strings */
+    int (*irq_handle)(struct usb_device *dev);
+    uint32_t irq_status;
+    int irq_act_len;            /* transfered bytes */
+    void *privptr;
+
+    /*
+     * Child devices -  if this is a hub device
+     * Each instance needs its own set of data structures.
+     */
+    uint32_t status;
+    int act_len;			/* transfered bytes */
+    int maxchild;			/* Number of ports if hub */
+    int portnr;
+    struct usb_device *parent;
+    struct usb_device *children[USB_MAXCHILDREN];
+    void *priv_hcd;
+    int (*deregister)(struct usb_device *dev);
+
+    struct usb_hub_device *hub;
+    int usbnum;
 };
 
 typedef struct
 {
-	long ident;
-	union
-	{
-		long l;
-		short i[2];
-		char c[4];
-	} v;
+    long ident;
+    union
+    {
+        long l;
+        short i[2];
+        char c[4];
+    } v;
 } USB_COOKIE;
 
-/**********************************************************************
+/*
  * this is how the lowlevel part communicate with the outer world
  */
 
@@ -275,7 +278,7 @@ extern int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol);
 extern int usb_set_idle(struct usb_device *dev, int ifnum, int duration, int report_id);
 extern struct usb_device *usb_get_dev_index(int index, int bus);
 extern int usb_control_msg(struct usb_device *dev, unsigned int pipe, uint8_t request, uint8_t requesttype,
-						   uint16_t value, uint16_t index, void *data, uint16_t size, int timeout);
+                           uint16_t value, uint16_t index, void *data, uint16_t size, int timeout);
 extern int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, void *data, int len, int *actual_length, int timeout);
 extern int usb_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
 extern void usb_disable_asynch(int disable);
@@ -322,44 +325,45 @@ extern int usb_set_interface(struct usb_device *dev, int interface, int alternat
  * specification, so that much of the uhci driver can just mask the bits
  * appropriately.
  */
+
 /* Create various pipes... */
-#define create_pipe(dev,endpoint) \
-		(((dev)->devnum << 8) | (endpoint << 15) | \
-		((dev)->speed << 26) | (dev)->maxpacketsize)
+#define create_pipe(dev, endpoint) \
+        (((dev)->devnum << 8) | (endpoint << 15) | \
+        ((dev)->speed << 26) | (dev)->maxpacketsize)
 #define default_pipe(dev) ((dev)->speed << 26)
 
 #define usb_sndctrlpipe(dev, endpoint)	((PIPE_CONTROL << 30) | \
-					 create_pipe(dev, endpoint))
+                     create_pipe(dev, endpoint))
 #define usb_rcvctrlpipe(dev, endpoint)	((PIPE_CONTROL << 30) | \
-					 create_pipe(dev, endpoint) | \
-					 USB_DIR_IN)
+                     create_pipe(dev, endpoint) | \
+                     USB_DIR_IN)
 #define usb_sndisocpipe(dev, endpoint)	((PIPE_ISOCHRONOUS << 30) | \
-					 create_pipe(dev, endpoint))
+                     create_pipe(dev, endpoint))
 #define usb_rcvisocpipe(dev, endpoint)	((PIPE_ISOCHRONOUS << 30) | \
-					 create_pipe(dev, endpoint) | \
-					 USB_DIR_IN)
+                     create_pipe(dev, endpoint) | \
+                     USB_DIR_IN)
 #define usb_sndbulkpipe(dev, endpoint)	((PIPE_BULK << 30) | \
-					 create_pipe(dev, endpoint))
+                     create_pipe(dev, endpoint))
 #define usb_rcvbulkpipe(dev, endpoint)	((PIPE_BULK << 30) | \
-					 create_pipe(dev, endpoint) | \
-					 USB_DIR_IN)
+                     create_pipe(dev, endpoint) | \
+                     USB_DIR_IN)
 #define usb_sndintpipe(dev, endpoint)	((PIPE_INTERRUPT << 30) | \
-					 create_pipe(dev, endpoint))
+                     create_pipe(dev, endpoint))
 #define usb_rcvintpipe(dev, endpoint)	((PIPE_INTERRUPT << 30) | \
-					 create_pipe(dev, endpoint) | \
-					 USB_DIR_IN)
+                     create_pipe(dev, endpoint) | \
+                     USB_DIR_IN)
 #define usb_snddefctrl(dev)		((PIPE_CONTROL << 30) | \
-					 default_pipe(dev))
+                     default_pipe(dev))
 #define usb_rcvdefctrl(dev)		((PIPE_CONTROL << 30) | \
-					 default_pipe(dev) | \
-					 USB_DIR_IN)
+                     default_pipe(dev) | \
+                     USB_DIR_IN)
 
 /* The D0/D1 toggle bits */
 #define usb_gettoggle(dev, ep, out) (((dev)->toggle[out] >> ep) & 1)
 #define usb_dotoggle(dev, ep, out)  ((dev)->toggle[out] ^= (1 << ep))
 #define usb_settoggle(dev, ep, out, bit) ((dev)->toggle[out] = \
-						((dev)->toggle[out] & \
-						 ~(1 << ep)) | ((bit) << ep))
+                        ((dev)->toggle[out] & \
+                         ~(1 << ep)) | ((bit) << ep))
 
 /* Endpoint halt control/status */
 #define usb_endpoint_out(ep_dir)	(((ep_dir >> 7) & 1) ^ 1)
@@ -368,7 +372,7 @@ extern int usb_set_interface(struct usb_device *dev, int interface, int alternat
 #define usb_endpoint_halted(dev, ep, out) ((dev)->halted[out] & (1 << (ep)))
 
 #define usb_packetid(pipe)	(((pipe) & USB_DIR_IN) ? USB_PID_IN : \
-				 USB_PID_OUT)
+                 USB_PID_OUT)
 
 #define usb_pipeout(pipe)	((((pipe) >> 7) & 1) ^ 1)
 #define usb_pipein(pipe)	(((pipe) >> 7) & 1)
@@ -390,37 +394,37 @@ extern int usb_set_interface(struct usb_device *dev, int interface, int alternat
  */
 struct usb_port_status
 {
-	uint16_t wPortStatus;
-	uint16_t wPortChange;
+    uint16_t wPortStatus;
+    uint16_t wPortChange;
 } __attribute__ ((packed));
 
 struct usb_hub_status
 {
-	uint16_t wHubStatus;
-	uint16_t wHubChange;
+    uint16_t wHubStatus;
+    uint16_t wHubChange;
 } __attribute__ ((packed));
 
 
 /* Hub descriptor */
 struct usb_hub_descriptor
 {
-	uint8_t  bLength;
-	uint8_t  bDescriptorType;
-	uint8_t  bNbrPorts;
-	uint16_t wHubCharacteristics;
-	uint8_t  bPwrOn2PwrGood;
-	uint8_t  bHubContrCurrent;
-	uint8_t  DeviceRemovable[(USB_MAXCHILDREN+1+7)/8];
-	uint8_t  PortPowerCtrlMask[(USB_MAXCHILDREN+1+7)/8];
-	/* DeviceRemovable and PortPwrCtrlMask want to be variable-length
-	   bitmaps that hold max 255 entries. (bit0 is ignored) */
+    uint8_t  bLength;
+    uint8_t  bDescriptorType;
+    uint8_t  bNbrPorts;
+    uint16_t wHubCharacteristics;
+    uint8_t  bPwrOn2PwrGood;
+    uint8_t  bHubContrCurrent;
+    uint8_t  DeviceRemovable[(USB_MAXCHILDREN+1+7)/8];
+    uint8_t  PortPowerCtrlMask[(USB_MAXCHILDREN+1+7)/8];
+    /* DeviceRemovable and PortPwrCtrlMask want to be variable-length
+       bitmaps that hold max 255 entries. (bit0 is ignored) */
 } __attribute__ ((packed));
 
 
 struct usb_hub_device
 {
-	struct usb_device *pusb_dev;
-	struct usb_hub_descriptor desc;
+    struct usb_device *pusb_dev;
+    struct usb_hub_descriptor desc;
 };
 
 #endif /*_USB_H_ */

include/version.h

@@ -29,7 +29,7 @@
  */
 
 #define MAJOR_VERSION	0
-#define MINOR_VERSION	86
+#define MINOR_VERSION	87
 
 
 #endif /* VERSION_H_ */

include/wait.h

@@ -44,6 +44,8 @@
 typedef bool (*checker_func)(void);
 
 extern void wait(uint32_t);
+extern void wait_us(uint32_t);  /* this is just an alias to the above */
+
 inline static void udelay(long us)
 {
     wait((uint32_t) us);

include/xhdi_sd.h

@@ -85,7 +85,7 @@ typedef struct _BPB
 /* a riddle: how do you typedef a function pointer to a function that returns its own type? ;) */
 typedef void* (*xhdi_call_fun)(int xhdi_fun, ...);
 
-extern unsigned long xhdi_call(uint16_t *stack);
+extern uint32_t xhdi_call(uint16_t *stack);
 
 extern xhdi_call_fun xhdi_sd_install(xhdi_call_fun old_vector) __attribute__((__interrupt__));
 

net/fecbd.c

@@ -11,7 +11,7 @@
 #include "bas_printf.h"
 #include <stddef.h>
 
-#define DBG_FECBD
+//#define DBG_FECBD
 #ifdef DBG_FECBD
 #define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
 #else
@@ -62,94 +62,94 @@ static int iRxbd;
  */
 void fecbd_init(uint8_t ch)
 {
-	NBUF *nbuf;
-	int i;
+    NBUF *nbuf;
+    int i;
 
     dbg("\r\n");
 
-	/* 
-	 * Align Buffer Descriptors to 4-byte boundary 
-	 */
-	RxBD = (FECBD *)(((int) unaligned_bds + 3) & 0xFFFFFFFC);
-	TxBD = (FECBD *)((int) RxBD + (sizeof(FECBD) * 2 * NRXBD));
+    /* 
+     * Align Buffer Descriptors to 4-byte boundary 
+     */
+    RxBD = (FECBD *)(((int) unaligned_bds + 3) & 0xFFFFFFFC);
+    TxBD = (FECBD *)((int) RxBD + (sizeof(FECBD) * 2 * NRXBD));
 
     dbg("initialise RX buffer descriptor ring\r\n");
 
-	/* 
-	 * Initialize the Rx Buffer Descriptor ring 
-	 */
-	for (i = 0; i < NRXBD; ++i)
-	{
-		/* Grab a network buffer from the free list */
-		nbuf = nbuf_alloc();
-		if (nbuf == NULL)
-		{
+    /* 
+     * Initialize the Rx Buffer Descriptor ring 
+     */
+    for (i = 0; i < NRXBD; ++i)
+    {
+        /* Grab a network buffer from the free list */
+        nbuf = nbuf_alloc();
+        if (nbuf == NULL)
+        {
             dbg("could not allocate network buffer\r\n");
-			return;
-		}
+            return;
+        }
 
-		/* Initialize the BD */
-		RxBD(ch,i).status = RX_BD_E | RX_BD_INTERRUPT;
-		RxBD(ch,i).length = RX_BUF_SZ;
-		RxBD(ch,i).data =  nbuf->data;
+        /* Initialize the BD */
+        RxBD(ch,i).status = RX_BD_E | RX_BD_INTERRUPT;
+        RxBD(ch,i).length = RX_BUF_SZ;
+        RxBD(ch,i).data =  nbuf->data;
 
-		/* Add the network buffer to the Rx queue */
-		nbuf_add(NBUF_RX_RING, nbuf);
-	}
+        /* Add the network buffer to the Rx queue */
+        nbuf_add(NBUF_RX_RING, nbuf);
+    }
 
-	/*
-	 * Set the WRAP bit on the last one
-	 */
-	RxBD(ch, i - 1).status |= RX_BD_W;
+    /*
+     * Set the WRAP bit on the last one
+     */
+    RxBD(ch, i - 1).status |= RX_BD_W;
 
     dbg("initialise TX buffer descriptor ring\r\n");
 
-	/* 
-	 * Initialize the Tx Buffer Descriptor ring 
-	 */
-	for (i = 0; i < NTXBD; ++i)
-	{
-		TxBD(ch, i).status = TX_BD_INTERRUPT;
-		TxBD(ch, i).length = 0;
-		TxBD(ch, i).data = NULL;
-	}
+    /* 
+     * Initialize the Tx Buffer Descriptor ring 
+     */
+    for (i = 0; i < NTXBD; ++i)
+    {
+        TxBD(ch, i).status = TX_BD_INTERRUPT;
+        TxBD(ch, i).length = 0;
+        TxBD(ch, i).data = NULL;
+    }
 
-	/*
-	 * Set the WRAP bit on the last one
-	 */
-	TxBD(ch, i - 1).status |= TX_BD_W;
+    /*
+     * Set the WRAP bit on the last one
+     */
+    TxBD(ch, i - 1).status |= TX_BD_W;
 
-	/* 
-	 * Initialize the buffer descriptor indexes 
-	 */
-	iTxbd_new = iTxbd_old = iRxbd = 0;
+    /* 
+     * Initialize the buffer descriptor indexes 
+     */
+    iTxbd_new = iTxbd_old = iRxbd = 0;
 }
 
 void fecbd_dump(uint8_t ch)
 {
 #ifdef DBG_FECBD
-	int i;
+    int i;
 
-	xprintf("\n------------ FEC%d BDs -----------\n",ch);
-	xprintf("RxBD Ring\n");
-	for (i = 0; i < NRXBD; i++)
-	{
-		xprintf("%02d: BD Addr=0x%08x, Ctrl=0x%04x, Lgth=%04d, DataPtr=0x%08x\n",
-				i, &RxBD(ch, i), 
-				RxBD(ch, i).status, 
-				RxBD(ch, i).length, 
-				RxBD(ch, i).data);
-	}
-	xprintf("TxBD Ring\n");
-	for (i = 0; i < NTXBD; i++)
-	{
-		xprintf("%02d: BD Addr=0x%08x, Ctrl=0x%04x, Lgth=%04d, DataPtr=0x%08x\n",
-				i, &TxBD(ch, i), 
-				TxBD(ch, i).status, 
-				TxBD(ch, i).length, 
-				TxBD(ch, i).data);
-	}
-	xprintf("--------------------------------\n\n");
+    xprintf("\n------------ FEC%d BDs -----------\n",ch);
+    xprintf("RxBD Ring\n");
+    for (i = 0; i < NRXBD; i++)
+    {
+        xprintf("%02d: BD Addr=0x%08x, Ctrl=0x%04x, Lgth=%04d, DataPtr=0x%08x\n",
+                i, &RxBD(ch, i), 
+                RxBD(ch, i).status, 
+                RxBD(ch, i).length, 
+                RxBD(ch, i).data);
+    }
+    xprintf("TxBD Ring\n");
+    for (i = 0; i < NTXBD; i++)
+    {
+        xprintf("%02d: BD Addr=0x%08x, Ctrl=0x%04x, Lgth=%04d, DataPtr=0x%08x\n",
+                i, &TxBD(ch, i), 
+                TxBD(ch, i).status, 
+                TxBD(ch, i).length, 
+                TxBD(ch, i).data);
+    }
+    xprintf("--------------------------------\n\n");
 #endif /* DBG_FECBD */
 }
 
@@ -165,28 +165,28 @@ void fecbd_dump(uint8_t ch)
  */
 uint32_t fecbd_get_start(uint8_t ch, uint8_t direction)
 {
-	switch (direction)
-	{
-		case Rx:
-			return (uint32_t)((int)RxBD + (ch * sizeof(FECBD) * NRXBD));
-		case Tx:
-		default:
-			return (uint32_t)((int)TxBD + (ch * sizeof(FECBD) * NTXBD));
-	}
+    switch (direction)
+    {
+        case Rx:
+            return (uint32_t)((int)RxBD + (ch * sizeof(FECBD) * NRXBD));
+        case Tx:
+        default:
+            return (uint32_t)((int)TxBD + (ch * sizeof(FECBD) * NTXBD));
+    }
 }
 
 FECBD *fecbd_rx_alloc(uint8_t ch)
 {
-	int i = iRxbd;
+    int i = iRxbd;
 
-	/* Check to see if the ring of BDs is full */
-	if (RxBD(ch, i).status & RX_BD_E)
-		return NULL;
+    /* Check to see if the ring of BDs is full */
+    if (RxBD(ch, i).status & RX_BD_E)
+        return NULL;
 
-	/* Increment the circular index */
-	iRxbd = (uint8_t)((iRxbd + 1) % NRXBD);
+    /* Increment the circular index */
+    iRxbd = (uint8_t)((iRxbd + 1) % NRXBD);
 
-	return &RxBD(ch, i);
+    return &RxBD(ch, i);
 }
 
 /*
@@ -201,16 +201,16 @@ FECBD *fecbd_rx_alloc(uint8_t ch)
  */
 FECBD *fecbd_tx_alloc(uint8_t ch)
 {
-	int i = iTxbd_new;
+    int i = iTxbd_new;
 
-	/* Check to see if the ring of BDs is full */
-	if (TxBD(ch, i).status & TX_BD_R)
-		return NULL;
+    /* Check to see if the ring of BDs is full */
+    if (TxBD(ch, i).status & TX_BD_R)
+        return NULL;
 
-	/* Increment the circular index */
-	iTxbd_new = (uint8_t)((iTxbd_new + 1) % NTXBD);
+    /* Increment the circular index */
+    iTxbd_new = (uint8_t)((iTxbd_new + 1) % NTXBD);
 
-	return &TxBD(ch, i);
+    return &TxBD(ch, i);
 }
 
 /*
@@ -226,14 +226,14 @@ FECBD *fecbd_tx_alloc(uint8_t ch)
  */
 FECBD *fecbd_tx_free(uint8_t ch)
 {
-	int i = iTxbd_old;
+    int i = iTxbd_old;
 
-	/* Check to see if the ring of BDs is empty */
-	if ((TxBD(ch, i).data == NULL) || (TxBD(ch, i).status & TX_BD_R))
-		return NULL;
+    /* Check to see if the ring of BDs is empty */
+    if ((TxBD(ch, i).data == NULL) || (TxBD(ch, i).status & TX_BD_R))
+        return NULL;
 
-	/* Increment the circular index */
-	iTxbd_old = (uint8_t)((iTxbd_old + 1) % NTXBD);
+    /* Increment the circular index */
+    iTxbd_old = (uint8_t)((iTxbd_old + 1) % NTXBD);
 
-	return &TxBD(ch, i);
+    return &TxBD(ch, i);
 }

net/ip.c

@@ -1,5 +1,5 @@
 /*
- * File:        ip.c
+ * File:    ip.c
  * Purpose:     Internet Protcol device driver
  *
  * Notes:
@@ -12,7 +12,7 @@
 #include "bas_string.h"
 
 
-#define IP_DEBUG
+//#define IP_DEBUG
 #if defined(IP_DEBUG)
 #define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
@@ -21,300 +21,297 @@
 
 void ip_init(IP_INFO *info, IP_ADDR_P myip, IP_ADDR_P gateway, IP_ADDR_P netmask)
 {
-	int index;
+    int index;
 
-	for (index = 0; index < sizeof(IP_ADDR); index++)
-	{
-		info->myip[index] = myip[index];
-		info->gateway[index] = gateway[index];
-		info->netmask[index] = netmask[index];
-		info->broadcast[index] = 0xFF;
-	}
+    for (index = 0; index < sizeof(IP_ADDR); index++)
+    {
+        info->myip[index] = myip[index];
+        info->gateway[index] = gateway[index];
+        info->netmask[index] = netmask[index];
+        info->broadcast[index] = 0xFF;
+    }
 
-	info->rx = 0;
-	info->rx_unsup = 0;
-	info->tx = 0;
-	info->err = 0;
+    info->rx = 0;
+    info->rx_unsup = 0;
+    info->tx = 0;
+    info->err = 0;
 }
 
 uint8_t *ip_get_myip(IP_INFO *info)
 {
-	if (info != 0)
-	{
-		return (uint8_t *) &info->myip[0];
-	}
-	dbg("info is NULL!\n\t");
-	return 0;
+    if (info != 0)
+    {
+        return (uint8_t *) &info->myip[0];
+    }
+    dbg("info is NULL!\n\t");
+    return 0;
 }
 
 int ip_addr_compare(IP_ADDR_P addr1, IP_ADDR_P addr2)
 {
-	int i;
+    int i;
 
-	for (i = 0; i < sizeof(IP_ADDR); i++)
-	{
-		if (addr1[i] != addr2[i])
-			return 0;
-	}
-	return 1;
+    for (i = 0; i < sizeof(IP_ADDR); i++)
+    {
+        if (addr1[i] != addr2[i])
+            return 0;
+    }
+    return 1;
 }
 
 uint8_t *ip_resolve_route(NIF *nif, IP_ADDR_P destip)
 {
-	/*
-	 * This function determines whether or not an outgoing IP
-	 * packet needs to be transmitted on the local net or sent
-	 * to the router for transmission.
-	 */
-	IP_INFO *info;
-	IP_ADDR mask, result;
-	IP_ADDR bc = { 255, 255, 255, 255 };
-	int i;
+    /*
+     * This function determines whether or not an outgoing IP
+     * packet needs to be transmitted on the local net or sent
+     * to the router for transmission.
+     */
+    IP_INFO *info;
+    IP_ADDR mask, result;
+    IP_ADDR bc = { 255, 255, 255, 255 };
+    int i;
 
-	info = nif_get_protocol_info(nif, ETH_FRM_IP);
+    info = nif_get_protocol_info(nif, ETH_FRM_IP);
 
-	if (memcmp(destip, bc, 4) == 0)
-	{
-		dbg("destip is broadcast address, no gateway needed\r\n");
-		return destip;
-	}
+    if (memcmp(destip, bc, 4) == 0)
+    {
+        dbg("destip is broadcast address, no gateway needed\r\n");
+        return destip;
+    }
 
-	/* create mask for local IP */
-	for (i = 0; i < sizeof(IP_ADDR); i++)
-	{
-		mask[i] = info->myip[i] & info->netmask[i];
-	}
+    /* create mask for local IP */
+    for (i = 0; i < sizeof(IP_ADDR); i++)
+    {
+        mask[i] = info->myip[i] & info->netmask[i];
+    }
 
-	/* apply mask to the destination IP */
-	for (i = 0; i < sizeof(IP_ADDR); i++)
-	{
-		result[i] = mask[i] & destip[i];
-	}
+    /* apply mask to the destination IP */
+    for (i = 0; i < sizeof(IP_ADDR); i++)
+    {
+        result[i] = mask[i] & destip[i];
+    }
 
-	/* See if destination IP is local or not */
-	if (ip_addr_compare(mask, result))
-	{
-		/* The destination IP is on the local net */
-		return arp_resolve(nif, ETH_FRM_IP, destip);
-	}
-	else
-	{
-		/* The destination IP is not on the local net */
-		return arp_resolve(nif, ETH_FRM_IP, info->gateway);
-	}
+    /* See if destination IP is local or not */
+    if (ip_addr_compare(mask, result))
+    {
+        /* The destination IP is on the local net */
+        return arp_resolve(nif, ETH_FRM_IP, destip);
+    }
+    else
+    {
+        /* The destination IP is not on the local net */
+        return arp_resolve(nif, ETH_FRM_IP, info->gateway);
+    }
 }
 
 int ip_send(NIF *nif, uint8_t *dest, uint8_t *src, uint8_t protocol, NBUF *pNbuf)
 {
-	/*
-	 * This function assembles an IP datagram and passes it
-	 * onto the hardware to be sent over the network.
-	 */
-	uint8_t *route;
-	ip_frame_hdr *ipframe;
+    /*
+     * This function assembles an IP datagram and passes it
+     * onto the hardware to be sent over the network.
+     */
+    uint8_t *route;
+    ip_frame_hdr *ipframe;
 
-	/*
-	 * Construct the IP header
-	 */
-	ipframe = (ip_frame_hdr*) &pNbuf->data[IP_HDR_OFFSET];
+    /*
+     * Construct the IP header
+     */
+    ipframe = (ip_frame_hdr*) &pNbuf->data[IP_HDR_OFFSET];
 
-	/* IP version 4, Internet Header Length of 5 32-bit words */
-	ipframe->version_ihl = 0x45;
+    /* IP version 4, Internet Header Length of 5 32-bit words */
+    ipframe->version_ihl = 0x45;
 
-	/* Type of Service == 0, normal and routine */
-	ipframe->service_type = 0x00;
+    /* Type of Service == 0, normal and routine */
+    ipframe->service_type = 0x00;
 
-	/* Total length of data */
-	ipframe->total_length = (uint16_t) (pNbuf->length + IP_HDR_SIZE);
+    /* Total length of data */
+    ipframe->total_length = (uint16_t) (pNbuf->length + IP_HDR_SIZE);
 
-	/* User defined identification */
-	ipframe->identification = 0x0000;
+    /* User defined identification */
+    ipframe->identification = 0x0000;
 
-	/* Fragment Flags and Offset -- Don't fragment, last frag */
-	ipframe->flags_frag_offset = 0x0000;
+    /* Fragment Flags and Offset -- Don't fragment, last frag */
+    ipframe->flags_frag_offset = 0x0000;
 
-	/* Time To Live */
-	ipframe->ttl = 0xFF;
+    /* Time To Live */
+    ipframe->ttl = 0xFF;
 
-	/* Protocol */
-	ipframe->protocol = protocol;
+    /* Protocol */
+    ipframe->protocol = protocol;
 
-	/* Checksum, computed later, zeroed for computation */
-	ipframe->checksum = 0x0000;
+    /* Checksum, computed later, zeroed for computation */
+    ipframe->checksum = 0x0000;
 
-	/* source IP address */
-	ipframe->source_addr[0] = src[0];
-	ipframe->source_addr[1] = src[1];
-	ipframe->source_addr[2] = src[2];
-	ipframe->source_addr[3] = src[3];
+    /* source IP address */
+    ipframe->source_addr[0] = src[0];
+    ipframe->source_addr[1] = src[1];
+    ipframe->source_addr[2] = src[2];
+    ipframe->source_addr[3] = src[3];
 
-	/* dest IP address */
-	ipframe->dest_addr[0] = dest[0];
-	ipframe->dest_addr[1] = dest[1];
-	ipframe->dest_addr[2] = dest[2];
-	ipframe->dest_addr[3] = dest[3];
+    /* dest IP address */
+    ipframe->dest_addr[0] = dest[0];
+    ipframe->dest_addr[1] = dest[1];
+    ipframe->dest_addr[2] = dest[2];
+    ipframe->dest_addr[3] = dest[3];
 
-	/* Compute checksum */
-	ipframe->checksum = ip_chksum((uint16_t *) ipframe, IP_HDR_SIZE);
+    /* Compute checksum */
+    ipframe->checksum = ip_chksum((uint16_t *) ipframe, IP_HDR_SIZE);
 
-	/* Increment the packet length by the size of the IP header */
-	pNbuf->length += IP_HDR_SIZE;
+    /* Increment the packet length by the size of the IP header */
+    pNbuf->length += IP_HDR_SIZE;
 
-	/*
-	 * Determine the hardware address of the recipient
-	 */
-	IP_ADDR bc = { 255, 255, 255, 255};
-	if (memcmp(bc, dest, 4) != 0)
-	{
-		route = ip_resolve_route(nif, dest);
-		if (route == NULL)
-		{
-			dbg("Unable to locate %d.%d.%d.%d\r\n",
-					dest[0], dest[1], dest[2], dest[3]);
-			return 0;
-		}
-	}
-	else
-	{
-		route = bc;
-		dbg("route = broadcast\r\n");
-		dbg("nif = %p\r\n", nif);
-		dbg("nif->send = %p\r\n", nif->send);
-	}
+    /*
+     * Determine the hardware address of the recipient
+     */
+    IP_ADDR bc = { 255, 255, 255, 255};
+    if (memcmp(bc, dest, 4) != 0)
+    {
+        route = ip_resolve_route(nif, dest);
+        if (route == NULL)
+        {
+            dbg("Unable to locate %d.%d.%d.%d\r\n",
+                    dest[0], dest[1], dest[2], dest[3]);
+            return 0;
+        }
+    }
+    else
+    {
+        route = bc;
+        dbg("route = broadcast\r\n");
+        dbg("nif = %p\r\n", nif);
+        dbg("nif->send = %p\r\n", nif->send);
+    }
 
-	return nif->send(nif, route, &nif->hwa[0], ETH_FRM_IP, pNbuf);
+    return nif->send(nif, route, &nif->hwa[0], ETH_FRM_IP, pNbuf);
 }
 
 #if defined(DEBUG_PRINT)
 void dump_ip_frame(ip_frame_hdr *ipframe)
 {
-	xprintf("Version:  %02X\n", ((ipframe->version_ihl & 0x00f0) >> 4));
-	xprintf("IHL:      %02X\n", ipframe->version_ihl & 0x000f);
-	xprintf("Service:  %02X\n", ipframe->service_type);
-	xprintf("Length:   %04X\n", ipframe->total_length);
-	xprintf("Ident:    %04X\n", ipframe->identification);
-	xprintf("Flags:    %02X\n", ((ipframe->flags_frag_offset & 0xC000) >> 14));
-	xprintf("Frag:     %04X\n", ipframe->flags_frag_offset & 0x3FFF);
-	xprintf("TTL:      %02X\n", ipframe->ttl);
-	xprintf("Protocol: %02X\n", ipframe->protocol);
-	xprintf("Chksum:   %04X\n", ipframe->checksum);
-	xprintf("Source  : %d.%d.%d.%d\n",
-			ipframe->source_addr[0],
-			ipframe->source_addr[1],
-			ipframe->source_addr[2],
-			ipframe->source_addr[3]);
-	xprintf("Dest    : %d.%d.%d.%d\n",
-			ipframe->dest_addr[0],
-			ipframe->dest_addr[1],
-			ipframe->dest_addr[2],
-			ipframe->dest_addr[3]);
-	xprintf("Options: %08X\n", ipframe->options);
+    xprintf("Version:  %02X\n", ((ipframe->version_ihl & 0x00f0) >> 4));
+    xprintf("IHL:      %02X\n", ipframe->version_ihl & 0x000f);
+    xprintf("Service:  %02X\n", ipframe->service_type);
+    xprintf("Length:   %04X\n", ipframe->total_length);
+    xprintf("Ident:    %04X\n", ipframe->identification);
+    xprintf("Flags:    %02X\n", ((ipframe->flags_frag_offset & 0xC000) >> 14));
+    xprintf("Frag:     %04X\n", ipframe->flags_frag_offset & 0x3FFF);
+    xprintf("TTL:      %02X\n", ipframe->ttl);
+    xprintf("Protocol: %02X\n", ipframe->protocol);
+    xprintf("Chksum:   %04X\n", ipframe->checksum);
+    xprintf("Source  : %d.%d.%d.%d\n",
+            ipframe->source_addr[0],
+            ipframe->source_addr[1],
+            ipframe->source_addr[2],
+            ipframe->source_addr[3]);
+    xprintf("Dest    : %d.%d.%d.%d\n",
+            ipframe->dest_addr[0],
+            ipframe->dest_addr[1],
+            ipframe->dest_addr[2],
+            ipframe->dest_addr[3]);
+    xprintf("Options: %08X\n", ipframe->options);
 }
 #endif
 
 
 uint16_t ip_chksum(uint16_t *data, int num)
 {
-	int chksum, ichksum;
-	uint16_t temp;
+    int chksum, ichksum;
+    uint16_t temp;
 
-	chksum = 0;
-	num = num >> 1; /* from bytes to words */
-	for (; num; num--, data++)
-	{
-		temp = *data;
-		ichksum = chksum + temp;
-		ichksum = ichksum & 0x0000FFFF;
-		if ((ichksum < temp) || (ichksum < chksum))
-		{
-			ichksum += 1;
-			ichksum = ichksum & 0x0000FFFF;
-		}
-		chksum = ichksum;
-	}
-	return (uint16_t) ~chksum;
+    chksum = 0;
+    num = num >> 1; /* from bytes to words */
+    for (; num; num--, data++)
+    {
+        temp = *data;
+        ichksum = chksum + temp;
+        ichksum = ichksum & 0x0000FFFF;
+        if ((ichksum < temp) || (ichksum < chksum))
+        {
+            ichksum += 1;
+            ichksum = ichksum & 0x0000FFFF;
+        }
+        chksum = ichksum;
+    }
+    return (uint16_t) ~chksum;
 }
 
 static int validate_ip_hdr(NIF *nif, ip_frame_hdr *ipframe)
 {
-	int index, chksum;
-	IP_INFO *info;
+    int index, chksum;
+    IP_INFO *info;
 
-	/*
-	 * Check the IP Version
-	 */
-	if (IP_VERSION(ipframe) != 4)
-		return 0;
+    /*
+     * Check the IP Version
+     */
+    if (IP_VERSION(ipframe) != 4)
+        return 0;
 
-	/*
-	 * Check Internet Header Length
-	 */
-	if (IP_IHL(ipframe) < 5)
-		return 0;
+    /*
+     * Check Internet Header Length
+     */
+    if (IP_IHL(ipframe) < 5)
+        return 0;
 
-	/*
-	 * Check the destination IP address
-	 */
-	info = nif_get_protocol_info(nif,ETH_FRM_IP);
-	for (index = 0; index < sizeof(IP_ADDR); index++)
-		if (info->myip[index] != ipframe->dest_addr[index])
-			return 0;
+    /*
+     * Check the destination IP address
+     */
+    info = nif_get_protocol_info(nif,ETH_FRM_IP);
+    for (index = 0; index < sizeof(IP_ADDR); index++)
+        if (info->myip[index] != ipframe->dest_addr[index])
+            return 0;
 
-	/*
-	 * Check the checksum
-	 */
-	chksum = (int)((uint16_t) IP_CHKSUM(ipframe));
-	IP_CHKSUM(ipframe) = 0;
+    /*
+     * Check the checksum
+     */
+    chksum = (int)((uint16_t) IP_CHKSUM(ipframe));
+    IP_CHKSUM(ipframe) = 0;
 
-	if (ip_chksum((uint16_t *) ipframe, IP_IHL(ipframe) * 4) != chksum)
-		return 0;
+    if (ip_chksum((uint16_t *) ipframe, IP_IHL(ipframe) * 4) != chksum)
+        return 0;
 
-	IP_CHKSUM(ipframe) = (uint16_t) chksum;
+    IP_CHKSUM(ipframe) = (uint16_t) chksum;
 
-	return 1;
+    return 1;
 }
 
 void ip_handler(NIF *nif, NBUF *pNbuf)
 {
-	/*
-	 * IP packet handler
-	 */
-	ip_frame_hdr *ipframe;
+    /*
+     * IP packet handler
+     */
+    ip_frame_hdr *ipframe;
 
-	dbg("packet received\r\n");
+    dbg("packet received\r\n");
 
-	ipframe = (ip_frame_hdr *) &pNbuf->data[pNbuf->offset];
+    ipframe = (ip_frame_hdr *) &pNbuf->data[pNbuf->offset];
 
-	/*
-	 * Verify valid IP header and destination IP
-	 */
-	if (!validate_ip_hdr(nif, ipframe))
-	{
-		dbg("not a valid IP packet!\r\n");
+    /*
+     * Verify valid IP header and destination IP
+     */
+    if (!validate_ip_hdr(nif, ipframe))
+    {
+        dbg("not a valid IP packet!\r\n");
 
-		nbuf_free(pNbuf);
-		return;
-	}
+        nbuf_free(pNbuf);
+        return;
+    }
 
-	pNbuf->offset += (IP_IHL(ipframe) * 4);
-	pNbuf->length = (uint16_t)(IP_LENGTH(ipframe) - (IP_IHL(ipframe) * 4));
-
-	/*
-	 * Call the appriopriate handler
-	 */
-	switch (IP_PROTOCOL(ipframe))
-	{
-		case IP_PROTO_ICMP:
-			// FIXME: icmp_handler(nif, pNbuf);
-			break;
-		case IP_PROTO_UDP:
-			udp_handler(nif,pNbuf);
-			break;
-		default:
-			dbg("no protocol handler registered for protocol %d\r\n",
-					__FUNCTION__, IP_PROTOCOL(ipframe));
-			nbuf_free(pNbuf);
-			break;
-	}
-	return;
+    /*
+     * Call the appriopriate handler
+     */
+    switch (IP_PROTOCOL(ipframe))
+    {
+        case IP_PROTO_ICMP:
+            // FIXME: icmp_handler(nif, pNbuf);
+            break;
+        case IP_PROTO_UDP:
+            udp_handler(nif,pNbuf);
+            break;
+        default:
+            dbg("no protocol handler registered for protocol %d\r\n",
+                    __FUNCTION__, IP_PROTOCOL(ipframe));
+            nbuf_free(pNbuf);
+            break;
+    }
+    return;
 }

net/net_timer.c

@@ -31,166 +31,172 @@
 
 static NET_TIMER net_timer[4] =
 {
-	{0, 0, 0, 0, 0, 0, 0},
-	{0, 0, 0, 0, 0, 0, 0},
-	{0, 0, 0, 0, 0, 0, 0},
-	{0, 0, 0, 0, 0, 0, 0}
+    {0, 0, 0, 0, 0, 0, 0},
+    {0, 0, 0, 0, 0, 0, 0},
+    {0, 0, 0, 0, 0, 0, 0},
+    {0, 0, 0, 0, 0, 0, 0}
 };
 
 
-int timer_default_isr(void *not_used, NET_TIMER *t)
+bool timer_default_isr(void *not_used, NET_TIMER *t)
 {
-	(void) not_used;
+    (void) not_used;
 
-	/*
-	 * Clear the pending event
-	 */
-	MCF_GPT_GMS(t->ch) = 0;
+    /*
+     * Clear the pending event
+     */
+    MCF_GPT_GMS(t->ch) = 0;
 
-	dbg("timer isr called for timer channel %d\r\n");
+    dbg("timer isr called for timer channel %d\r\n");
 
-	/*
-	 * Clear the reference - the desired seconds have expired
-	 */
-	t->reference = 0;
+    /*
+     * Clear the reference - the desired seconds have expired
+     */
+    t->reference = 0;
 
-	return 1;
+    return 1;
 }
 
 void timer_irq_enable(uint8_t ch)
 {
-	/*
-	 * Setup the appropriate ICR
-	 */
-	MCF_INTC_ICR(TIMER_VECTOR(ch) - 64) =
-		(uint8_t)(0
-				| MCF_INTC_ICR_IP(net_timer[ch].pri)
-				| MCF_INTC_ICR_IL(net_timer[ch].lvl));
+    /*
+     * Setup the appropriate ICR
+     */
+    MCF_INTC_ICR(TIMER_VECTOR(ch) - 64) = MCF_INTC_ICR_IP(net_timer[ch].pri) |
+                                          MCF_INTC_ICR_IL(net_timer[ch].lvl);
 
-	/*
-	 * Unmask the FEC interrupt in the interrupt controller
-	 */
-	if (ch == 3)
-		MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK59;
-	else if (ch == 2)
-		MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK60;
-	else if (ch == 1)
-		MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK61;
-	else
-		MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK62;
+    /*
+     * Unmask the FEC interrupt in the interrupt controller
+     */
+    if (ch == 3)
+    {
+        MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK59;
+    }
+    else if (ch == 2)
+    {
+        MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK60;
+    }
+    else if (ch == 1)
+    {
+        MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK61;
+    }
+    else
+    {
+        MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK62;
+    }
 }
 
 bool timer_set_secs(uint8_t ch, uint32_t secs)
 {
-	uint16_t timeout;
+    uint16_t timeout;
 
-	/*
-	 * Reset the timer
-	 */
-	MCF_GPT_GMS(ch) = 0;
+    /*
+     * Reset the timer
+     */
+    MCF_GPT_GMS(ch) = 0;
 
-	/*
-	 * Get the timeout in seconds
-	 */
-	timeout = (uint16_t)(secs * net_timer[ch].cnt);
+    /*
+     * Get the timeout in seconds
+     */
+    timeout = (uint16_t)(secs * net_timer[ch].cnt);
 
-	/*
-	 * Set the reference indicating that we have not yet reached the
-	 * desired timeout
-	 */
-	net_timer[ch].reference = 1;
+    /*
+     * Set the reference indicating that we have not yet reached the
+     * desired timeout
+     */
+    net_timer[ch].reference = 1;
 
-	/*
-	 * Enable timer interrupt to the processor
-	 */
-	timer_irq_enable(ch);
+    /*
+     * Enable timer interrupt to the processor
+     */
+    timer_irq_enable(ch);
 
-	/*
-	 * Enable the timer using the pre-calculated values
-	 */
-	MCF_GPT_GCIR(ch) = (0
-			| MCF_GPT_GCIR_CNT(timeout)
-			| MCF_GPT_GCIR_PRE(net_timer[ch].pre)
-			);
-	MCF_GPT_GMS(ch) = net_timer[ch].gms;
+    /*
+     * Enable the timer using the pre-calculated values
+     */
+    MCF_GPT_GCIR(ch) = (0
+            | MCF_GPT_GCIR_CNT(timeout)
+            | MCF_GPT_GCIR_PRE(net_timer[ch].pre)
+            );
+    MCF_GPT_GMS(ch) = net_timer[ch].gms;
 
-	return true;
+    return true;
 }
 
 uint32_t timer_get_reference(uint8_t ch)
 {
-	return (uint32_t) net_timer[ch].reference;
+    return (uint32_t) net_timer[ch].reference;
 }
 
 bool timer_init(uint8_t ch, uint8_t lvl, uint8_t pri)
 {
-	/*
-	 * Initialize the timer to expire after one second
-	 *
-	 * This routine should only be called by the project (board) specific
-	 * initialization code.
-	 */
-	if (!((ch <= 3) && (lvl <= 7) && (lvl >= 1) && (pri <= 7)))
-	{
-		dbg("illegal parameters (ch=%d, lvl=%d, pri=%d)\r\n", ch, lvl, pri);
+    /*
+     * Initialize the timer to expire after one second
+     *
+     * This routine should only be called by the project (board) specific
+     * initialization code.
+     */
+    if (!((ch <= 3) && (lvl <= 7) && (lvl >= 1) && (pri <= 7)))
+    {
+        dbg("illegal parameters (ch=%d, lvl=%d, pri=%d)\r\n", ch, lvl, pri);
 
-		return false;
-	}
+        return false;
+    }
 
-	/*
-	 * Reset the timer
-	 */
-	MCF_GPT_GMS(ch) = 0;
+    /*
+     * Reset the timer
+     */
+    MCF_GPT_GMS(ch) = 0;
 
-	/*
-	 * Save off the channel, and interrupt lvl/pri information
-	 */
-	net_timer[ch].ch = ch;
-	net_timer[ch].lvl = lvl;
-	net_timer[ch].pri = pri;
+    /*
+     * Save off the channel, and interrupt lvl/pri information
+     */
+    net_timer[ch].ch = ch;
+    net_timer[ch].lvl = lvl;
+    net_timer[ch].pri = pri;
 
-	/*
-	 * Register the timer interrupt handler
-	 */
-	if (!isr_register_handler(TIMER_VECTOR(ch),
-				(int (*)(void *,void *)) timer_default_isr,
-				NULL,
-				(void *) &net_timer[ch])
-	   )
-	{
-		dbg("could not register timer interrupt handler\r\n");
-		return false;
-	}
-	dbg("timer handler registered\r\n", __FUNCTION__);
+    /*
+     * Register the timer interrupt handler
+     */
+    if (!isr_register_handler(TIMER_VECTOR(ch), 3, 0,
+                (bool (*)(void *,void *)) timer_default_isr,
+                NULL,
+                (void *) &net_timer[ch])
+       )
+    {
+        dbg("could not register timer interrupt handler\r\n");
+        return false;
+    }
+    dbg("timer handler registered\r\n", __FUNCTION__);
 
-	/*
-	 * Calculate the require CNT value to get a 1 second timeout
-	 *
-	 * 1 sec = CNT * Clk Period * PRE
-	 * CNT = 1 sec / (Clk Period * PRE)
-	 * CNT = Clk Freq / PRE
-	 *
-	 * The system clock frequency is defined as SYSTEM_CLOCK and
-	 * is given in MHz. We need to multiple it by 1000000 to get the
-	 * true value.  If we assume PRE to be the maximum of 0xFFFF,
-	 * then the CNT value needed to achieve a 1 second timeout is
-	 * given by:
-	 *
-	 * CNT = SYSTEM_CLOCK * (1000000/0xFFFF)
-	 */
-	net_timer[ch].pre = 0xFFFF;
-	net_timer[ch].cnt = (uint16_t) ((SYSCLK / 1000) * (1000000 / 0xFFFF));
+    /*
+     * Calculate the require CNT value to get a 1 second timeout
+     *
+     * 1 sec = CNT * Clk Period * PRE
+     * CNT = 1 sec / (Clk Period * PRE)
+     * CNT = Clk Freq / PRE
+     *
+     * The system clock frequency is defined as SYSTEM_CLOCK and
+     * is given in MHz. We need to multiple it by 1000000 to get the
+     * true value.  If we assume PRE to be the maximum of 0xFFFF,
+     * then the CNT value needed to achieve a 1 second timeout is
+     * given by:
+     *
+     * CNT = SYSTEM_CLOCK * (1000000/0xFFFF)
+     */
+    net_timer[ch].pre = 0xFFFF;
+    net_timer[ch].cnt = (uint16_t) ((SYSCLK / 1000) * (1000000 / 0xFFFF));
 
-	/*
-	 * Save off the appropriate mode select register value
-	 */
-	net_timer[ch].gms = (0
-			| MCF_GPT_GMS_TMS_GPIO
-			| MCF_GPT_GMS_IEN
-			| MCF_GPT_GMS_SC
-			| MCF_GPT_GMS_CE
-			);
+    /*
+     * Save off the appropriate mode select register value
+     */
+    net_timer[ch].gms = (0
+            | MCF_GPT_GMS_TMS_GPIO
+            | MCF_GPT_GMS_IEN
+            | MCF_GPT_GMS_SC
+            | MCF_GPT_GMS_CE
+            );
 
-	return true;
+    return true;
 }
 

net/udp.c

@@ -21,8 +21,8 @@
 
 typedef struct
 {
-	uint16_t port;
-	void (*handler)(NIF *, NBUF *);
+    uint16_t port;
+    void (*handler)(NIF *, NBUF *);
 } UDP_BOUND_PORT;
 
 #define UDP_MAX_PORTS   (5)     /* plenty for this implementation */
@@ -34,151 +34,151 @@ static uint16_t udp_port;
 
 void udp_init(void)
 {
-	int index;
+    int index;
 
-	for (index = 0; index < UDP_MAX_PORTS; ++index)
-	{
-		udp_port_table[index].port = 0;
-		udp_port_table[index].handler = 0;
-	}
+    for (index = 0; index < UDP_MAX_PORTS; ++index)
+    {
+        udp_port_table[index].port = 0;
+        udp_port_table[index].handler = 0;
+    }
 
-	udp_port = DEFAULT_UDP_PORT;    /* next free port */
+    udp_port = DEFAULT_UDP_PORT;    /* next free port */
 }
 
 void udp_prime_port(uint16_t init_port)
 {
-	udp_port = init_port;
+    udp_port = init_port;
 }
 
 void udp_bind_port(uint16_t port, void (*handler)(NIF *, NBUF *))
 {
-	int index;
+    int index;
 
-	for (index = 0; index < UDP_MAX_PORTS; ++index)
-	{
-		if (udp_port_table[index].port == 0)
-		{
-			udp_port_table[index].port = port;
-			udp_port_table[index].handler = handler;
+    for (index = 0; index < UDP_MAX_PORTS; ++index)
+    {
+        if (udp_port_table[index].port == 0)
+        {
+            udp_port_table[index].port = port;
+            udp_port_table[index].handler = handler;
 
-			return;
-		}
-	}
+            return;
+        }
+    }
 }
 
 void udp_free_port(uint16_t port)
 {
-	int index;
+    int index;
 
-	for (index = 0; index < UDP_MAX_PORTS; ++index)
-	{
-		if (udp_port_table[index].port == port)
-		{
-			udp_port_table[index].port = 0;
+    for (index = 0; index < UDP_MAX_PORTS; ++index)
+    {
+        if (udp_port_table[index].port == port)
+        {
+            udp_port_table[index].port = 0;
 
-			return;
-		}
-	}
+            return;
+        }
+    }
 }
 
 static void *udp_port_handler(uint16_t port)
 {
-	int index;
+    int index;
 
-	for (index = 0; index < UDP_MAX_PORTS; ++index)
-	{
-		if (udp_port_table[index].port == port)
-		{
-			return (void *) udp_port_table[index].handler;
-		}
-	}
-	return NULL;
+    for (index = 0; index < UDP_MAX_PORTS; ++index)
+    {
+        if (udp_port_table[index].port == port)
+        {
+            return (void *) udp_port_table[index].handler;
+        }
+    }
+    return NULL;
 }
 
 uint16_t udp_obtain_free_port(void)
 {
-	uint16_t port;
+    uint16_t port;
 
-	port = udp_port;
-	if (--udp_port <= 255)
-		udp_port = DEFAULT_UDP_PORT;
+    port = udp_port;
+    if (--udp_port <= 255)
+        udp_port = DEFAULT_UDP_PORT;
 
-	return port;
+    return port;
 }
 
 int udp_send(NIF *nif, uint8_t *dest, int sport, int dport, NBUF *pNbuf)
 {
-	uint8_t *myip;
+    uint8_t *myip;
 
-	if (nif == NULL)
-	{
+    if (nif == NULL)
+    {
         dbg("nif is NULL\r\n");
-		return 0;
-	}
+        return 0;
+    }
 
-	/*
-	 * This function takes data, creates a UDP frame from it and
-	 * passes it onto the IP layer
-	 */
-	udp_frame_hdr *udpframe;
+    /*
+     * This function takes data, creates a UDP frame from it and
+     * passes it onto the IP layer
+     */
+    udp_frame_hdr *udpframe;
 
-	udpframe = (udp_frame_hdr *) &pNbuf->data[UDP_HDR_OFFSET];
+    udpframe = (udp_frame_hdr *) &pNbuf->data[UDP_HDR_OFFSET];
 
-	/* Set UDP source port */
-	udpframe->src_port = (uint16_t) sport;
+    /* Set UDP source port */
+    udpframe->src_port = (uint16_t) sport;
 
-	/* Set UDP destination port */
-	udpframe->dest_port = (uint16_t) dport;
+    /* Set UDP destination port */
+    udpframe->dest_port = (uint16_t) dport;
 
-	/* Set length */
-	udpframe->length = (uint16_t) (pNbuf->length + UDP_HDR_SIZE);
+    /* Set length */
+    udpframe->length = (uint16_t) (pNbuf->length + UDP_HDR_SIZE);
 
-	/* No checksum calcualation needed */
-	udpframe->chksum = (uint16_t) 0;
+    /* No checksum calcualation needed */
+    udpframe->chksum = (uint16_t) 0;
 
-	/* Add the length of the UDP packet to the total length of the packet */
-	pNbuf->length += 8;
+    /* Add the length of the UDP packet to the total length of the packet */
+    pNbuf->length += 8;
 
-	myip = ip_get_myip(nif_get_protocol_info(nif, ETH_FRM_IP));
+    myip = ip_get_myip(nif_get_protocol_info(nif, ETH_FRM_IP));
 
     dbg("sent UDP request to %d.%d.%d.%d from %d.%d.%d.%d\r\n",
-			dest[0], dest[1], dest[2], dest[3],
-			myip[0], myip[1], myip[2], myip[3]);
+            dest[0], dest[1], dest[2], dest[3],
+            myip[0], myip[1], myip[2], myip[3]);
 
-	return (ip_send(nif, dest, myip, IP_PROTO_UDP, pNbuf));
+    return (ip_send(nif, dest, myip, IP_PROTO_UDP, pNbuf));
 
 }
 
 void udp_handler(NIF *nif, NBUF *pNbuf)
 {
-	/*
-	 * This function handles incoming UDP packets
-	 */
-	udp_frame_hdr *udpframe;
-	void (*handler)(NIF *, NBUF *);
+    /*
+     * This function handles incoming UDP packets
+     */
+    udp_frame_hdr *udpframe;
+    void (*handler)(NIF *, NBUF *);
 
-	udpframe = (udp_frame_hdr *) &pNbuf->data[pNbuf->offset];
+    udpframe = (udp_frame_hdr *) &pNbuf->data[pNbuf->offset];
 
     dbg("packet received\r\n",);
 
-	/*
-	 * Adjust the length and valid data offset of the packet we are
-	 * passing on
-	 */
-	pNbuf->length -= UDP_HDR_SIZE;
-	pNbuf->offset += UDP_HDR_SIZE;
+    /*
+     * Adjust the length and valid data offset of the packet we are
+     * passing on
+     */
+    pNbuf->length -= UDP_HDR_SIZE;
+    pNbuf->offset += UDP_HDR_SIZE;
 
-	/*
-	 * Traverse the list of bound ports to see if there is a higher
-	 * level protocol to pass the packet on to
-	 */
-	if ((handler = (void(*)(NIF*, NBUF*)) udp_port_handler(UDP_DEST(udpframe))) != NULL)
-		handler(nif, pNbuf);
-	else
-	{
+    /*
+     * Traverse the list of bound ports to see if there is a higher
+     * level protocol to pass the packet on to
+     */
+    if ((handler = (void(*)(NIF*, NBUF*)) udp_port_handler(UDP_DEST(udpframe))) != NULL)
+        handler(nif, pNbuf);
+    else
+    {
         dbg("received UDP packet for non-supported port\n");
-		nbuf_free(pNbuf);
-	}
+        nbuf_free(pNbuf);
+    }
 
-	return;
+    return;
 }

sys/BaS.c

@@ -48,6 +48,8 @@
 #include "interrupts.h"
 #include "exceptions.h"
 #include "net_timer.h"
+#include "pci.h"
+#include "video.h"
 
 //#define BAS_DEBUG
 #if defined(BAS_DEBUG)
@@ -55,6 +57,7 @@
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif
+#define err(format, arg...) do { xprintf("ERROR: %s(): " format, __FUNCTION__, ##arg); } while (0)
 
 /* imported routines */
 extern int vec_init();
@@ -76,10 +79,12 @@ extern uint8_t _EMUTOS_SIZE[];
  */
 static inline bool pic_txready(void)
 {
-	if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_TXRDY)
-		return true;
+    if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_TXRDY)
+    {
+        return true;
+    }
 
-	return false;
+    return false;
 }
 
 /*
@@ -87,157 +92,175 @@ static inline bool pic_txready(void)
  */
 static inline bool pic_rxready(void)
 {
-	if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_RXRDY)
-		return true;
+    if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_RXRDY)
+    {
+        return true;
+    }
 
-	return false;
+    return false;
 }
 
 void write_pic_byte(uint8_t value)
 {
-	/* Wait until the transmitter is ready or 1000us are passed */
-	waitfor(1000, pic_txready);
+    /*
+     * Wait until the transmitter is ready or 1000us are passed
+     */
+    waitfor(1000, pic_txready);
 
-	/* Transmit the byte */
-	*(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT) = value; // Really 8-bit
+    /*
+     * Transmit the byte
+     */
+    *(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT) = value; // Really 8-bit
 }
 
 uint8_t read_pic_byte(void)
 {
-	/* Wait until a byte has been received or 1000us are passed */
-	waitfor(1000, pic_rxready);
+    /*
+     * Wait until a byte has been received or 1000us are passed
+     */
+    waitfor(1000, pic_rxready);
 
-	/* Return the received byte */
-	return * (volatile uint8_t *) (&MCF_PSC3_PSCTB_8BIT); // Really 8-bit
+    /*
+     * Return the received byte
+     */
+    return * (volatile uint8_t *) (&MCF_PSC3_PSCTB_8BIT); // Really 8-bit
 }
 
 void pic_init(void)
 {
-	char answer[4] = "OLD";
+    char answer[4] = "OLD";
 
-	xprintf("initialize the PIC: ");
+    xprintf("initialize the PIC: ");
 
-	/* Send the PIC initialization string */
-	write_pic_byte('A');
-	write_pic_byte('C');
-	write_pic_byte('P');
-	write_pic_byte('F');
+    /*
+     * Send the PIC initialization string
+     */
+    write_pic_byte('A');
+    write_pic_byte('C');
+    write_pic_byte('P');
+    write_pic_byte('F');
 
-	/* Read the 3-char answer string. Should be "OK!". */
-	answer[0] = read_pic_byte();
-	answer[1] = read_pic_byte();
-	answer[2] = read_pic_byte();
-	answer[3] = '\0';
+    /*
+     * Read the 3-char answer string. Should be "OK!".
+     */
+    answer[0] = read_pic_byte();
+    answer[1] = read_pic_byte();
+    answer[2] = read_pic_byte();
+    answer[3] = '\0';
 
-	if (answer[0] != 'O' || answer[1] != 'K' || answer[2] != '!')
-	{
-		dbg("PIC initialization failed. Already initialized?\r\n");
-	}
-	else
-	{
-		xprintf("%s\r\n", answer);
-	}
+    if (answer[0] != 'O' || answer[1] != 'K' || answer[2] != '!')
+    {
+        dbg("PIC initialization failed. Already initialized?\r\n");
+    }
+    else
+    {
+        xprintf("%s\r\n", answer);
+    }
 }
 
 void nvram_init(void)
 {
-	int i;
+    int i;
 
-	xprintf("Restore the NVRAM data: ");
+    xprintf("Restore the NVRAM data: ");
 
-	/* Request for NVRAM backup data */
-	write_pic_byte(0x01);
+    /* Request for NVRAM backup data */
+    write_pic_byte(0x01);
 
-	/* Check answer type */
-	if (read_pic_byte() != 0x81)
-	{
-		// FIXME: PIC protocol error
-		xprintf("FAILED\r\n");
-		return;
-	}
+    /* Check answer type */
+    if (read_pic_byte() != 0x81)
+    {
+        // FIXME: PIC protocol error
+        xprintf("FAILED\r\n");
+        return;
+    }
 
-	/* Restore the NVRAM backup to the FPGA */
-	for (i = 0; i < 64; i++)
-	{
-		uint8_t data = read_pic_byte();
-		*(volatile uint8_t*)0xffff8961 = i;
-		*(volatile uint8_t*)0xffff8963 = data;
-	}
+    /* Restore the NVRAM backup to the FPGA */
+    for (i = 0; i < 64; i++)
+    {
+        uint8_t data = read_pic_byte();
+        *(volatile uint8_t*)0xffff8961 = i;
+        *(volatile uint8_t*)0xffff8963 = data;
+    }
 
-	xprintf("finished\r\n");
+    xprintf("finished\r\n");
 }
 
-#define KBD_ACIA_CONTROL		((uint8_t *) 0xfffffc00)
-#define MIDI_ACIA_CONTROL		((uint8_t *) 0xfffffc04)
-#define MFP_INTR_IN_SERVICE_A	((uint8_t *) 0xfffffa0f)
-#define MFP_INTR_IN_SERVICE_B	((uint8_t *) 0xfffffa11)
+#define KBD_ACIA_CONTROL        * ((uint8_t *) 0xfffffc00)
+#define MIDI_ACIA_CONTROL       * ((uint8_t *) 0xfffffc04)
+#define MFP_INTR_IN_SERVICE_A   * ((uint8_t *) 0xfffffa0f)
+#define MFP_INTR_IN_SERVICE_B   * ((uint8_t *) 0xfffffa11)
 
 void acia_init()
 {
-	xprintf("init ACIA: ");
-	/* init ACIA */
-	* KBD_ACIA_CONTROL = 3;		/* master reset */
-	NOP();
+    xprintf("init ACIA: ");
+    /* init ACIA */
+    KBD_ACIA_CONTROL = 3;       /* master reset */
+    NOP();
 
-	* MIDI_ACIA_CONTROL = 3;	/* master reset */
-	NOP();
+    MIDI_ACIA_CONTROL = 3;      /* master reset */
+    NOP();
 
-	* KBD_ACIA_CONTROL = 0x96;	/* clock div = 64, 8N1, RTS low, TX int disable, RX int enable */
-	NOP();
+    KBD_ACIA_CONTROL = 0x96;    /* clock div = 64, 8N1, RTS low, TX int disable, RX int enable */
+    NOP();
 
-	* MFP_INTR_IN_SERVICE_A = -1;
-	NOP();
+    MFP_INTR_IN_SERVICE_A = 0xff;
+    NOP();
 
-	* MFP_INTR_IN_SERVICE_B = -1;
-	NOP();
+    MFP_INTR_IN_SERVICE_B = 0xff;
+    NOP();
 
-	xprintf("finished\r\n");
+    xprintf("finished\r\n");
 }
 
-/* ACP interrupt controller */
-#define FPGA_INTR_CONTRL	(volatile uint32_t *) 0xf0010000
-#define FPGA_INTR_ENABLE	(volatile uint8_t *)  0xf0010004
-#define FPGA_INTR_PENDIN	(volatile uint32_t *) 0xf0010008
-
 void enable_coldfire_interrupts()
 {
-	xprintf("enable interrupts: ");
+    xprintf("enable interrupts: ");
 #if defined(MACHINE_FIREBEE)
-	*FPGA_INTR_CONTRL = 0L;				/* disable all interrupts */
+    FBEE_INTR_CONTROL = 0L;                /* disable all interrupts */
 #endif /* MACHINE_FIREBEE */
-	MCF_EPORT_EPPAR = 0xaaa8;			/* all interrupts on falling edge */
+
+    MCF_EPORT_EPPAR = 0xaaa8;               /* all interrupts on falling edge */
 
 #if defined(MACHINE_FIREBEE)
-	/*
-	 * TIN0 on the Coldfire is connected to the FPGA. TIN0 triggers every write
-	 * access to 0xff8201 (vbasehi), i.e. everytime the video base address is written
-	 */
-	MCF_GPT0_GMS = MCF_GPT_GMS_ICT(1) |	/* timer 0 on, video change capture on rising edge */
-			MCF_GPT_GMS_IEN |
-			MCF_GPT_GMS_TMS(1);
-										/* route GPT0 interrupt on interrupt controller */
-	MCF_INTC_ICR62 = 0x3f;				/* interrupt level 7, interrupt priority 7 */
+    /*
+     * TIN0 on the Coldfire is connected to the FPGA. TIN0 triggers every write
+     * access to 0xff8201 (vbasehi), i.e. everytime the video base address is written
+     */
+    MCF_GPT0_GMS = MCF_GPT_GMS_ICT(1) |     /* timer 0 on, video change capture on rising edge */
+            MCF_GPT_GMS_IEN |
+            MCF_GPT_GMS_TMS(1);             /* route GPT0 interrupt on interrupt controller */
+    MCF_INTC_ICR62 = MCF_INTC_ICR_IL(7) |
+                     MCF_INTC_ICR_IP(6);    /* interrupt level 7, interrupt priority 7 */
 
-	*FPGA_INTR_ENABLE  = 0xfe;	/* enable int 1-7 */
-	MCF_EPORT_EPIER = 0xfe;				/* int 1-7 on */
-	MCF_EPORT_EPFR = 0xff;				/* clear all pending interrupts */
-	MCF_INTC_IMRL = 0xffffff00;			/* int 1-7 on */
-	MCF_INTC_IMRH = 0xbffffffe;			/* psc3 and timer 0 int on */
+
+    MCF_EPORT_EPIER = 0xfe;                 /* int 1-7 on */
+    MCF_EPORT_EPFR = 0xff;                  /* clear all pending interrupts */
+    MCF_INTC_IMRL = 0xffffff00;             /* int 1-7 on */
+    //MCF_INTC_IMRH = 0xbffffffe;             /* psc3 and timer 0 int on */
+    MCF_INTC_IMRH = 0;
+    FBEE_INTR_ENABLE = FBEE_INTR_INT_IRQ7 | /* enable pseudo bus error */
+            FBEE_INTR_INT_MFP_IRQ6 |        /* enable MFP interrupts */
+            FBEE_INTR_INT_FPGA_IRQ5 |       /* enable Firebee (PIC, PCI, ETH PHY, DVI, DSP) interrupts */
+            FBEE_INTR_INT_VSYNC_IRQ4 |      /* enable vsync interrupts */
+            FBEE_INTR_PCI_INTA |            /* enable PCI interrupts */
+            FBEE_INTR_PCI_INTB |
+            FBEE_INTR_PCI_INTC |
+            FBEE_INTR_PCI_INTD;
 #endif
 
-	xprintf("finished\r\n");
+    xprintf("finished\r\n");
 }
 
 void disable_coldfire_interrupts()
 {
 #if defined(MACHINE_FIREBEE)
-	*FPGA_INTR_ENABLE = 0;		/* disable all interrupts */
+    FBEE_INTR_ENABLE = 0;      /* disable all interrupts */
 #endif /* MACHINE_FIREBEE */
 
-	MCF_EPORT_EPIER = 0x0;
-	MCF_EPORT_EPFR = 0x0;
-	MCF_INTC_IMRL = 0xfffffffe;
-	MCF_INTC_IMRH = 0xffffffff;
+    MCF_EPORT_EPIER = 0x0;
+    MCF_INTC_IMRL = 0xfffffffe;
+    MCF_INTC_IMRH = 0xffffffff;
 }
 
 
@@ -252,178 +275,184 @@ NIF nif2;
  */
 void init_isr(void)
 {
-	isr_init();		/* need to call that explicitely, otherwise isr table might be full */
+    isr_init();     /* need to call that explicitely, otherwise isr table might be full */
 
-	/*
-	 * register the FEC interrupt handler
-	 */
-	if (!isr_register_handler(64 + INT_SOURCE_FEC0, fec0_interrupt_handler, NULL, (void *) &nif1))
-	{
-		dbg("unable to register isr for FEC0\r\n");
-		return;
-	}
+    /*
+     * register the FEC interrupt handler
+     */
+    if (!isr_register_handler(64 + INT_SOURCE_FEC0, 5, 1, fec0_interrupt_handler, NULL, (void *) &nif1))
+    {
+        err("unable to register isr for FEC0\r\n");
+    }
 
-	/*
-	 * Register the DMA interrupt handler
-	 */
+    /*
+     * Register the DMA interrupt handler
+     */
 
-	if (!isr_register_handler(64 + INT_SOURCE_DMA, dma_interrupt_handler, NULL,NULL))
-	{
-		dbg("Error: Unable to register isr for DMA\r\n");
-		return;
-	}
+    if (!isr_register_handler(64 + INT_SOURCE_DMA, 5, 3, dma_interrupt_handler, NULL, NULL))
+    {
+        err("unable to register isr for DMA\r\n");
+    }
 
-	dma_irq_enable(5, 3);	/* TODO: need to match the FEC driver's specs in MiNT? */
+#ifdef MACHINE_FIREBEE
+    /*
+     * register GPT0 timer interrupt vector
+     */
+    if (!isr_register_handler(64 + INT_SOURCE_GPT0, 5, 2, gpt0_interrupt_handler, NULL, NULL))
+    {
+        err("unable to register isr for GPT0 timer\r\n");
+    }
 
-	/*
-	 * register the PIC interrupt handler
-	 */
-	if (isr_register_handler(64 + INT_SOURCE_PSC3, pic_interrupt_handler, NULL, NULL))
-	{
-		dbg("Error: unable to register ISR for PSC3\r\n");
-		return;
-	}
+    /*
+     * register the PIC interrupt handler
+     */
+    if (!isr_register_handler(64 + INT_SOURCE_PSC3, 5, 5, pic_interrupt_handler, NULL, NULL))
+    {
+        err("Error: unable to register ISR for PSC3\r\n");
+    }
+#endif /* MACHINE_FIREBEE */
+
+    /*
+     * register the XLB PCI interrupt handler
+     */
+    if (!isr_register_handler(64 + INT_SOURCE_XLBPCI, 7, 0, xlbpci_interrupt_handler, NULL, NULL))
+    {
+        err("Error: unable to register isr for XLB PCI interrupts\r\n");
+    }
+
+    MCF_XLB_XARB_IMR = MCF_XLB_XARB_IMR_SEAE |      /* slave error acknowledge interrupt */
+                       MCF_XLB_XARB_IMR_MME |       /* multiple master at prio 0 interrupt */
+                       MCF_XLB_XARB_IMR_TTAE |      /* TT address only interrupt */
+                       MCF_XLB_XARB_IMR_TTRE |      /* TT reserved interrupt enable */
+                       MCF_XLB_XARB_IMR_ECWE |      /* external control word interrupt */
+                       MCF_XLB_XARB_IMR_TTME |      /* TBST/TSIZ mismatch interrupt */
+                       MCF_XLB_XARB_IMR_BAE;        /* bus activity tenure timeout interrupt */
+
+    if (!isr_register_handler(64 + INT_SOURCE_PCIARB, 7, 1, pciarb_interrupt_handler, NULL, NULL))
+    {
+        err("Error: unable to register isr for PCIARB interrupts\r\n");
+
+        return;
+    }
+    MCF_PCIARB_PACR = MCF_PCIARB_PACR_EXTMINTEN(0x1f) | /* external master broken interrupt */
+                      MCF_PCIARB_PACR_INTMINTEN;        /* internal master broken interrupt */
 }
 
 void BaS(void)
 {
-	uint8_t *src;
-	uint8_t *dst = (uint8_t *) TOS;
+    uint8_t *src;
+    uint8_t *dst = (uint8_t *) TOS;
 
 #if defined(MACHINE_FIREBEE)        /* LITE board has no pic and (currently) no nvram */
-	pic_init();
-	nvram_init();
+    pic_init();
+    nvram_init();
 #endif /* MACHINE_FIREBEE */
 
-	xprintf("copy EmuTOS: ");
+    xprintf("initialize MMU: ");
+    mmu_init();
+    xprintf("finished\r\n");
 
-	/* copy EMUTOS */
-	src = (uint8_t *) EMUTOS;
-	dma_memcpy(dst, src, EMUTOS_SIZE);
-	xprintf("finished\r\n");
+    xprintf("copy EmuTOS: ");
 
-	xprintf("initialize MMU: ");
-	mmu_init();
-	xprintf("finished\r\n");
+    dma_init();
 
-	xprintf("initialize exception vector table: ");
-	vec_init();
-	xprintf("finished\r\n");
+    /* copy EMUTOS */
+    src = (uint8_t *) EMUTOS;
+    dma_memcpy(dst, src, EMUTOS_SIZE);
+    xprintf("finished\r\n");
 
-	xprintf("flush caches: ");
-	flush_and_invalidate_caches();
-	xprintf("finished\r\n");
-	xprintf("enable MMU: ");
-	MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN;			/* MMU on */
-	NOP();										/* force pipeline sync */
-	xprintf("finished\r\n");
+    xprintf("initialize exception vector table: ");
+    vec_init();
+    xprintf("finished\r\n");
 
-	#ifdef MACHINE_FIREBEE
-	xprintf("IDE reset: ");
-	/* IDE reset */
-	* (volatile uint8_t *) (0xffff8802 - 2) = 14;
-	* (volatile uint8_t *) (0xffff8802 - 0) = 0x80;
-	wait(1);
+    xprintf("flush caches: ");
+    flush_and_invalidate_caches();
+    xprintf("finished\r\n");
+    xprintf("enable MMU: ");
+    MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN;           /* MMU on */
+    NOP();                                      /* force pipeline sync */
+    xprintf("finished\r\n");
 
-	* (volatile uint8_t *) (0xffff8802 - 0) = 0;
+    #ifdef MACHINE_FIREBEE
+    xprintf("IDE reset: ");
+    /* IDE reset */
+    * (volatile uint8_t *) (0xffff8802 - 2) = 14;
+    * (volatile uint8_t *) (0xffff8802 - 0) = 0x80;
+    wait(1);
 
-	xprintf("finished\r\n");
-	xprintf("enable video: ");
-	/*
-	 * video setup (25MHz)
-	 */
-	* (volatile uint32_t *) (0xf0000410 + 0) = 0x032002ba;	/* horizontal 640x480 */
-	* (volatile uint32_t *) (0xf0000410 + 4) = 0x020c020a;	/* vertical 640x480 */
-	* (volatile uint32_t *) (0xf0000410 + 8) = 0x0190015d;	/* horizontal 320x240 */
-	* (volatile uint32_t *) (0xf0000410 + 12) = 0x020C020A;	/* vertical 320x230 */
+    * (volatile uint8_t *) (0xffff8802 - 0) = 0;
 
-#ifdef _NOT_USED_
-//  32MHz
-	* (volatile uint32_t *) (0xf0000410 + 0) = 0x037002ba;	/* horizontal 640x480 */
-	* (volatile uint32_t *) (0xf0000410 + 4) = 0x020d020a;	/* vertical 640x480 */
-	* (volatile uint32_t *) (0xf0000410 + 8) = 0x02a001e0;	/* horizontal 320x240 */
-	* (volatile uint32_t *) (0xf0000410 + 12) = 0x05a00160;	/* vertical 320x230 */
-#endif /* _NOT_USED_ */
+    xprintf("finished\r\n");
+    xprintf("enable video: ");
+    /*
+     * video setup (25MHz)
+     */
+    * (volatile uint32_t *) (0xf0000410 + 0) = 0x032002ba;  /* horizontal 640x480 */
+    * (volatile uint32_t *) (0xf0000410 + 4) = 0x020c020a;  /* vertical 640x480 */
+    * (volatile uint32_t *) (0xf0000410 + 8) = 0x0190015d;  /* horizontal 320x240 */
+    * (volatile uint32_t *) (0xf0000410 + 12) = 0x020C020A; /* vertical 320x230 */
 
-	/* fifo on, refresh on, ddrcs and cke on, video dac on */
-	* (volatile uint32_t *) (0xf0000410 - 0x20) = 0x01070002;
-
-	xprintf("finished\r\n");
-
-	enable_coldfire_interrupts();
-
-#ifdef _NOT_USED_
-	screen_init();
-
-		/* experimental */
-	{
-		int i;
-		uint32_t *scradr = 0xd00000;
-
-		for (i = 0; i < 100; i++)
-		{
-			uint32_t *p = scradr;
-
-			for (p = scradr; p < scradr + 1024 * 150L; p++)
-			{
-				*p = 0xffffffff;
-			}
-
-			for (p = scradr; p < scradr + 1024 * 150L; p++)
-			{
-				*p = 0x0;
-			}
-		}
-	}
-#endif /* _NOT_USED_ */
+    /* fifo on, refresh on, ddrcs and cke on, video dac on */
+    * (volatile uint32_t *) (0xf0000410 - 0x20) = 0x01070002;
 
+    xprintf("finished\r\n");
 #endif /* MACHINE_FIREBEE */
 
-	sd_card_init();
+    sd_card_init();
 
-	/*
-	 * memory setup
-	 */
-	memset((void *) 0x400, 0, 0x400);
+    /*
+     * memory setup
+     */
+    memset((void *) 0x400, 0, 0x400);
 
 #if defined(MACHINE_FIREBEE)
-	/* set Falcon bus control register */
-	/* sets bit 3 and 6. Both are undefined on an original Falcon? */
+    /* set Falcon bus control register */
+    /* sets bit 3 and 6. Both are undefined on an original Falcon? */
 
-	* (volatile uint8_t *) 0xffff8007 = 0x48;
+    * (volatile uint8_t *) 0xffff8007 = 0x48;
 #endif /* MACHINE_FIREBEE */
 
-	/* ST RAM */
+    /* ST RAM */
 
-	* (uint32_t *) 0x42e = STRAM_END;	/* phystop TOS system variable */
-	* (uint32_t *) 0x420 = 0x752019f3;	/* memvalid TOS system variable */
-	* (uint32_t *) 0x43a = 0x237698aa;	/* memval2 TOS system variable */
-	* (uint32_t *) 0x51a = 0x5555aaaa;	/* memval3 TOS system variable */
+    * (uint32_t *) 0x42e = STRAM_END;   /* phystop TOS system variable */
+    * (uint32_t *) 0x420 = 0x752019f3;  /* memvalid TOS system variable */
+    * (uint32_t *) 0x43a = 0x237698aa;  /* memval2 TOS system variable */
+    * (uint32_t *) 0x51a = 0x5555aaaa;  /* memval3 TOS system variable */
 
-	/* TT-RAM */
+    /* TT-RAM */
 
-	* (uint32_t *) 0x5a4 = FASTRAM_END;	/* ramtop TOS system variable */
-	* (uint32_t *) 0x5a8 = 0x1357bd13;	/* ramvalid TOS system variable */
+    * (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */
+    * (uint32_t *) 0x5a8 = 0x1357bd13;  /* ramvalid TOS system variable */
 
 #if defined(MACHINE_FIREBEE) /* m5484lite has no ACIA and no dip switch... */
-	acia_init();
+    acia_init();
 #endif /* MACHINE_FIREBEE */
 
-	srec_execute("BASFLASH.S19");
+    srec_execute("BASFLASH.S19");
 
-	/* Jump into the OS */
-	typedef void void_func(void);
-	struct rom_header
-	{
-		void *initial_sp;
-		void_func *initial_pc;
-	};
+    /* Jump into the OS */
+    typedef void void_func(void);
+    struct rom_header
+    {
+        void *initial_sp;
+        void_func *initial_pc;
+    };
 
-	xprintf("BaS initialization finished, enable interrupts\r\n");
-	enable_coldfire_interrupts();
-	init_isr();
+    xprintf("BaS initialization finished, enable interrupts\r\n");
+    init_isr();
 
-	xprintf("call EmuTOS\r\n");
-	struct rom_header *os_header = (struct rom_header *) TOS;
-	os_header->initial_pc();
+    enable_coldfire_interrupts();
+    dma_irq_enable();
+
+    init_pci();
+    // video_init();
+
+    /* initialize USB devices */
+    //init_usb();
+
+    set_ipl(7);     /* disable interrupts */
+
+    xprintf("call EmuTOS\r\n");
+    struct rom_header *os_header = (struct rom_header *) TOS;
+    os_header->initial_pc();
 }

sys/driver_mem.c

@@ -27,7 +27,7 @@
 #error "unknown machine!"
 #endif
 
-#define DBG_DM
+//#define DBG_DM
 #ifdef	DBG_DM
 #define	dbg(fmt, args...)	xprintf(fmt, ##args)
 #else
@@ -44,10 +44,10 @@ extern uint8_t driver_mem_buffer[DRIVER_MEM_BUFFER_SIZE];	/* defined in linker c
 
 MD
 {
-	MD *m_link;
-	long m_start;
-	long m_length;
-	void *m_own;
+    MD *m_link;
+    long m_start;
+    long m_length;
+    void *m_own;
 };
 
 /* MPB - Memory Partition Block */
@@ -56,9 +56,9 @@ MD
 
 MPB
 {
-	MD *mp_mfl;
-	MD *mp_mal;
-	MD *mp_rover;
+    MD *mp_mfl;
+    MD *mp_mal;
+    MD *mp_rover;
 };
 
 #define MAXMD 256
@@ -68,273 +68,273 @@ static MPB pmd;
 
 static void *xmgetblk(void)
 {
-	int i;
+    int i;
 
-	for (i = 0; i < MAXMD; i++)
-	{
-		if (tab_md[i].m_own == NULL)
-		{
-			tab_md[i].m_own = (void*)1L;
-			return(&tab_md[i]);
-		}
-	}
-	return NULL;
+    for (i = 0; i < MAXMD; i++)
+    {
+        if (tab_md[i].m_own == NULL)
+        {
+            tab_md[i].m_own = (void*)1L;
+            return(&tab_md[i]);
+        }
+    }
+    return NULL;
 }
 
 static void xmfreblk(void *m)
 {
-	int i = (int)(((long) m - (long) tab_md) / sizeof(MD));
-	if ((i > 0) && (i < MAXMD))
-	{
-		tab_md[i].m_own = NULL;
-	}
+    int i = (int)(((long) m - (long) tab_md) / sizeof(MD));
+    if ((i > 0) && (i < MAXMD))
+    {
+        tab_md[i].m_own = NULL;
+    }
 }
 
 static MD *ffit(long amount, MPB *mp)
 {
-	MD *p, *q, *p1;                    /* free list is composed of MD's */
-	int maxflg;
-	long maxval;
+    MD *p, *q, *p1;                    /* free list is composed of MD's */
+    int maxflg;
+    long maxval;
 
-	if (amount != -1)
-	{
-		amount += 15;                  /* 16 bytes alignment */
-		amount &= 0xFFFFFFF0;
-	}
+    if (amount != -1)
+    {
+        amount += 15;                  /* 16 bytes alignment */
+        amount &= 0xFFFFFFF0;
+    }
 
-	if ((q = mp->mp_rover) == 0)      /* get rotating pointer */
-	{
-		return 0;
-	}
+    if ((q = mp->mp_rover) == 0)      /* get rotating pointer */
+    {
+        return 0;
+    }
 
-	maxval = 0;
-	maxflg = ((amount == -1) ? true : false) ;
-	p = q->m_link;                   /* start with next MD */
-	do /* search the list for an MD with enough space */
-	{
-		if (p == 0)
-		{
-			/*  at end of list, wrap back to start  */
-			q = (MD *) &mp->mp_mfl;      /*  q => mfl field  */
-			p = q->m_link;               /*  p => 1st MD     */
-		}
-		if ((!maxflg) && (p->m_length >= amount))
-		{
-			/*  big enough */
-			if (p->m_length == amount)
-			{
-				q->m_link = p->m_link;     /* take the whole thing */
-			}
-			else
-			{
-				/*
-				 * break it up - 1st allocate a new
-				 * MD to describe the remainder
-				 */
-				p1 = xmgetblk();
-				if (p1 == NULL)
-				{
-					return(NULL);
-				}
+    maxval = 0;
+    maxflg = ((amount == -1) ? true : false) ;
+    p = q->m_link;                   /* start with next MD */
+    do /* search the list for an MD with enough space */
+    {
+        if (p == 0)
+        {
+            /*  at end of list, wrap back to start  */
+            q = (MD *) &mp->mp_mfl;      /*  q => mfl field  */
+            p = q->m_link;               /*  p => 1st MD     */
+        }
+        if ((!maxflg) && (p->m_length >= amount))
+        {
+            /*  big enough */
+            if (p->m_length == amount)
+            {
+                q->m_link = p->m_link;     /* take the whole thing */
+            }
+            else
+            {
+                /*
+                 * break it up - 1st allocate a new
+                 * MD to describe the remainder
+                 */
+                p1 = xmgetblk();
+                if (p1 == NULL)
+                {
+                    return(NULL);
+                }
 
-				/* init new MD */
-				p1->m_length = p->m_length - amount;
-				p1->m_start = p->m_start + amount;
-				p1->m_link = p->m_link;
-				p->m_length = amount;      /* adjust allocated block */
-				q->m_link = p1;
-			}
-			/* link allocate block into allocated list,
-				mark owner of block, & adjust rover  */
-			p->m_link = mp->mp_mal;
-			mp->mp_mal = p;
-			mp->mp_rover = (q == (MD *) &mp->mp_mfl ? q->m_link : q);
-			return(p);                   /* got some */
-		}
-		else if (p->m_length > maxval)
-			maxval = p->m_length;
-		p = ( q=p )->m_link;
-	} while(q != mp->mp_rover);
+                /* init new MD */
+                p1->m_length = p->m_length - amount;
+                p1->m_start = p->m_start + amount;
+                p1->m_link = p->m_link;
+                p->m_length = amount;      /* adjust allocated block */
+                q->m_link = p1;
+            }
+            /* link allocate block into allocated list,
+                mark owner of block, & adjust rover  */
+            p->m_link = mp->mp_mal;
+            mp->mp_mal = p;
+            mp->mp_rover = (q == (MD *) &mp->mp_mfl ? q->m_link : q);
+            return(p);                   /* got some */
+        }
+        else if (p->m_length > maxval)
+            maxval = p->m_length;
+        p = ( q=p )->m_link;
+    } while(q != mp->mp_rover);
 
-	/*
-	 * return either the max, or 0 (error)
-	 */
-	if (maxflg)
-	{
-		maxval -= 15;		/* 16 bytes alignment */
-		if (maxval < 0)
-		{
-			maxval = 0;
-		}
-		else
-		{
-			maxval &= 0xFFFFFFF0;
-		}
-	}
-	return(maxflg ? (MD *) maxval : 0);
+    /*
+     * return either the max, or 0 (error)
+     */
+    if (maxflg)
+    {
+        maxval -= 15;		/* 16 bytes alignment */
+        if (maxval < 0)
+        {
+            maxval = 0;
+        }
+        else
+        {
+            maxval &= 0xFFFFFFF0;
+        }
+    }
+    return(maxflg ? (MD *) maxval : 0);
 }
 
 static void freeit(MD *m, MPB *mp)
 {
-	MD *p, *q;
+    MD *p, *q;
 
-	q = 0;
-	for (p = mp->mp_mfl; p ; p = (q = p) -> m_link)
-	{
-		if (m->m_start <= p->m_start)
-		{
-			break;
-		}
-	}
-	m->m_link = p;
+    q = 0;
+    for (p = mp->mp_mfl; p ; p = (q = p) -> m_link)
+    {
+        if (m->m_start <= p->m_start)
+        {
+            break;
+        }
+    }
+    m->m_link = p;
 
-	if (q)
-	{
-		q->m_link = m;
-	}
-	else
-	{
-		mp->mp_mfl = m;
-	}
+    if (q)
+    {
+        q->m_link = m;
+    }
+    else
+    {
+        mp->mp_mfl = m;
+    }
 
-	if (!mp->mp_rover)
-	{
-		mp->mp_rover = m;
-	}
+    if (!mp->mp_rover)
+    {
+        mp->mp_rover = m;
+    }
 
-	if (p)
-	{
-		if (m->m_start + m->m_length == p->m_start)
-		{
-			/* join to higher neighbor */
-			m->m_length += p->m_length;
-			m->m_link = p->m_link;
-			if (p == mp->mp_rover)
-			{
-				mp->mp_rover = m;
-			}
-			xmfreblk(p);
-		}
-	}
-	if (q)
-	{
-		if (q->m_start + q->m_length == m->m_start)
-		{
-			/* join to lower neighbor */
-			q->m_length += m->m_length;
-			q->m_link = m->m_link;
-			if (m == mp->mp_rover)
-			{
-				mp->mp_rover = q;
-			}
-			xmfreblk(m);
-		}
-	}
+    if (p)
+    {
+        if (m->m_start + m->m_length == p->m_start)
+        {
+            /* join to higher neighbor */
+            m->m_length += p->m_length;
+            m->m_link = p->m_link;
+            if (p == mp->mp_rover)
+            {
+                mp->mp_rover = m;
+            }
+            xmfreblk(p);
+        }
+    }
+    if (q)
+    {
+        if (q->m_start + q->m_length == m->m_start)
+        {
+            /* join to lower neighbor */
+            q->m_length += m->m_length;
+            q->m_link = m->m_link;
+            if (m == mp->mp_rover)
+            {
+                mp->mp_rover = q;
+            }
+            xmfreblk(m);
+        }
+    }
 }
 
 int32_t driver_mem_free(void *addr)
 {
-	int level;
-	MD *p, **q;
-	MPB *mpb;
-	mpb = &pmd;
-	level = set_ipl(7);
+    int level;
+    MD *p, **q;
+    MPB *mpb;
+    mpb = &pmd;
+    level = set_ipl(7);
 
-	for(p = *(q = &mpb->mp_mal); p; p = *(q = &p->m_link))
-	{
-		if ((long) addr == p->m_start)
-		{
-			break;
-		}
-	}
+    for(p = *(q = &mpb->mp_mal); p; p = *(q = &p->m_link))
+    {
+        if ((long) addr == p->m_start)
+        {
+            break;
+        }
+    }
 
-	if (!p)
-	{
-		set_ipl(level);
-		return(-1);
-	}
+    if (!p)
+    {
+        set_ipl(level);
+        return(-1);
+    }
 
-	*q = p->m_link;
-	freeit(p, mpb);
-	set_ipl(level);
+    *q = p->m_link;
+    freeit(p, mpb);
+    set_ipl(level);
 
-	dbg("%s: driver_mem_free(0x%08X)\r\n", __FUNCTION__, addr);
+    dbg("%s: driver_mem_free(0x%08X)\r\n", __FUNCTION__, addr);
 
-	return(0);
+    return(0);
 }
 
 void *driver_mem_alloc(uint32_t amount)
 {
-	void *ret = NULL;
-	int level;
-	MD *m;
+    void *ret = NULL;
+    int level;
+    MD *m;
 
-	if (amount == -1L)
-	{
-		return (void *) ffit(-1L, &pmd);
-	}
+    if (amount == -1L)
+    {
+        return (void *) ffit(-1L, &pmd);
+    }
 
-	if (amount <= 0 )
-	{
-		return(0);
-	}
+    if (amount <= 0 )
+    {
+        return(0);
+    }
 
-	if ((amount & 1))
-	{
-		amount++;
-	}
+    if ((amount & 1))
+    {
+        amount++;
+    }
 
-	level = set_ipl(7);
-	m = ffit(amount, &pmd);
+    level = set_ipl(7);
+    m = ffit(amount, &pmd);
 
-	if (m != NULL)
-	{
-		ret = (void *) m->m_start;
-	}
-	set_ipl(level);
-	dbg("%s: driver_mem_alloc(%d) = 0x%08X\r\n", __FUNCTION__, amount, ret);
+    if (m != NULL)
+    {
+        ret = (void *) m->m_start;
+    }
+    set_ipl(level);
+    dbg("%s: driver_mem_alloc(%d) = 0x%08X\r\n", __FUNCTION__, amount, ret);
 
-	return ret;
+    return ret;
 }
 
 static int use_count = 0;
 
 int driver_mem_init(void)
 {
-	if (use_count == 0)
-	{
-		dbg("%s: initialise driver_mem_buffer[] at %p, size 0x%x\r\n", __FUNCTION__, driver_mem_buffer, DRIVER_MEM_BUFFER_SIZE);
-		memset(driver_mem_buffer, 0, DRIVER_MEM_BUFFER_SIZE);
+    if (use_count == 0)
+    {
+        dbg("%s: initialise driver_mem_buffer[] at %p, size 0x%x\r\n", __FUNCTION__, driver_mem_buffer, DRIVER_MEM_BUFFER_SIZE);
+        memset(driver_mem_buffer, 0, DRIVER_MEM_BUFFER_SIZE);
 
-		pmd.mp_mfl = pmd.mp_rover = &tab_md[0];
-		tab_md[0].m_link = (MD *) NULL;
-		tab_md[0].m_start = ((long) driver_mem_buffer + 15) & ~15;
-		tab_md[0].m_length = DRIVER_MEM_BUFFER_SIZE;
-		tab_md[0].m_own = (void *) 1L;
-		pmd.mp_mal = (MD *) NULL;
-		memset(driver_mem_buffer, 0, tab_md[0].m_length);
+        pmd.mp_mfl = pmd.mp_rover = &tab_md[0];
+        tab_md[0].m_link = (MD *) NULL;
+        tab_md[0].m_start = ((long) driver_mem_buffer + 15) & ~15;
+        tab_md[0].m_length = DRIVER_MEM_BUFFER_SIZE;
+        tab_md[0].m_own = (void *) 1L;
+        pmd.mp_mal = (MD *) NULL;
+        memset(driver_mem_buffer, 0, tab_md[0].m_length);
 
-		dbg("%s: uncached driver memory buffer at 0x%08X size %d\r\n", __FUNCTION__, tab_md[0].m_start, tab_md[0].m_length);
-	}
-	use_count++;
-	dbg("%s: driver_mem now has a use count of %d\r\n", __FUNCTION__, use_count);
+        dbg("%s: uncached driver memory buffer at 0x%08X size %d\r\n", __FUNCTION__, tab_md[0].m_start, tab_md[0].m_length);
+    }
+    use_count++;
+    dbg("%s: driver_mem now has a use count of %d\r\n", __FUNCTION__, use_count);
 
-	return 0;
+    return 0;
 }
 
 void driver_mem_release(void)
 {
-	if (use_count-- == 0)
-	{
+    if (use_count-- == 0)
+    {
 #ifndef CONFIG_USB_MEM_NO_CACHE
 #ifdef USE_RADEON_MEMORY
-		if (driver_mem_buffer == (void *) offscren_reserved())
-			return;
+        if (driver_mem_buffer == (void *) offscren_reserved())
+            return;
 
 #endif
 #endif
-	}
-	dbg("%s: driver_mem use count now %d\r\n", __FUNCTION__, use_count);
+    }
+    dbg("%s: driver_mem use count now %d\r\n", __FUNCTION__, use_count);
 }
 
 

sys/fault_vectors.c

@@ -30,173 +30,181 @@ extern exception_handler SDRAM_VECTOR_TABLE[];
  */
 void fault_handler(uint32_t pc, uint32_t format_status)
 {
-	int format;
-	int fault_status;
-	int vector;
-	int sr;
+    int format;
+    int fault_status;
+    int vector;
+    int sr;
 
-	xprintf("\007\007exception! Processor halted.\r\n");
-	xprintf("format_status: %lx\r\n", format_status);
-	xprintf("pc: %lx\r\n", pc);
+    xprintf("\007\007exception! Processor halted.\r\n");
+    xprintf("format_status: %lx\r\n", format_status);
+    xprintf("pc: %lx\r\n", pc);
 
-	/*
-	 * extract info from format-/status word
-	 */
-	format = 	    (format_status & 0b11110000000000000000000000000000) >> 28;
-	fault_status = ((format_status & 0b00001100000000000000000000000000) >> 26) |
-			       ((format_status & 0b00000000000000110000000000000000) >> 16);
-	vector       =  (format_status & 0b00000011111111000000000000000000) >> 18;
-	sr           =  (format_status & 0b00000000000000001111111111111111);
+    /*
+     * extract info from format-/status word
+     */
+    format =        (format_status & 0b11110000000000000000000000000000) >> 28;
+    fault_status = ((format_status & 0b00001100000000000000000000000000) >> 26) |
+                   ((format_status & 0b00000000000000110000000000000000) >> 16);
+    vector       =  (format_status & 0b00000011111111000000000000000000) >> 18;
+    sr           =  (format_status & 0b00000000000000001111111111111111);
 
-	xprintf("format: %x\r\n", format);
-	xprintf("fault_status: %x (", fault_status);
-	switch (fault_status)
-	{
-	case 0:
-		xprintf("not an access or address error nor an interrupted debug service routine");
-		break;
-	case 1:
-	case 3:
-	case 11:
-		xprintf("reserved");
-		break;
-	case 2:
-		xprintf("interrupt during a debug service routine for faults other than access errors");
-		break;
-	case 4:
-		xprintf("error (for example, protection fault) on instruction fetch");
-		break;
-	case 5:
-		xprintf("TLB miss on opword or instruction fetch");
-		break;
-	case 6:
-		xprintf("TLB miss on extension word of instruction fetch");
-		break;
-	case 7:
-		xprintf("IFP access error while executing in emulator mode");
-		break;
-	case 8:
-		xprintf("error on data write");
-		break;
-	case 9:
-		xprintf("error on attempted write to write-protected space");
-		break;
-	case 10:
-		xprintf("TLB miss on data write");
-		break;
-	case 12:
-		xprintf("error on data read");
-		break;
-	case 13:
-		xprintf("attempted read, read-modify-write of protected space");
-		break;
-	case 14:
-		xprintf("TLB miss on data read or read-modify-write");
-		break;
-	case 15:
-		xprintf("OEP access error while executing in emulator mode");
-	}
-	xprintf(")\r\n");
+    xprintf("format: %x\r\n", format);
+    xprintf("fault_status: %x (", fault_status);
+    switch (fault_status)
+    {
+    case 0:
+        xprintf("not an access or address error nor an interrupted debug service routine");
+        break;
+    case 1:
+    case 3:
+    case 11:
+        xprintf("reserved");
+        break;
+    case 2:
+        xprintf("interrupt during a debug service routine for faults other than access errors");
+        break;
+    case 4:
+        xprintf("error (for example, protection fault) on instruction fetch");
+        break;
+    case 5:
+        xprintf("TLB miss on opword or instruction fetch");
+        break;
+    case 6:
+        xprintf("TLB miss on extension word of instruction fetch");
+        break;
+    case 7:
+        xprintf("IFP access error while executing in emulator mode");
+        break;
+    case 8:
+        xprintf("error on data write");
+        break;
+    case 9:
+        xprintf("error on attempted write to write-protected space");
+        break;
+    case 10:
+        xprintf("TLB miss on data write");
+        break;
+    case 12:
+        xprintf("error on data read");
+        break;
+    case 13:
+        xprintf("attempted read, read-modify-write of protected space");
+        break;
+    case 14:
+        xprintf("TLB miss on data read or read-modify-write");
+        break;
+    case 15:
+        xprintf("OEP access error while executing in emulator mode");
+    }
+    xprintf(")\r\n");
 
-	xprintf("vector = %02x (", vector);
-	switch (vector)
-	{
-	case 2:
-		xprintf("access error");
-		break;
-	case 3:
-		xprintf("address error");
-		break;
-	case 4:
-		xprintf("illegal instruction");
-		break;
-	case 5:
-		xprintf("divide by zero");
-		break;
-	case 8:
-		xprintf("privilege violation");
-		break;
-	case 9:
-		xprintf("trace");
-		break;
-	case 10:
-		xprintf("unimplemented line-a opcode");
-		break;
-	case 11:
-		xprintf("unimplemented line-f opcode");
-		break;
-	case 12:
-		xprintf("non-PC breakpoint debug interrupt");
-		break;
-	case 13:
-		xprintf("PC breakpoint debug interrupt");
-		break;
-	case 14:
-		xprintf("format error");
-		break;
-	case 24:
-		xprintf("spurious interrupt");
-		break;
-	default:
-		if ( ((fault_status >= 6) && (fault_status <= 7)) ||
-			 ((fault_status >= 16) && (fault_status <= 23)))
-		{
-			xprintf("reserved");
-		}
-		else if ((fault_status >= 25) && (fault_status <= 31))
-		{
-			xprintf("level %d autovectored interrupt", fault_status - 24);
-		}
-		else if ((fault_status >= 32) && (fault_status <= 47))
-		{
-			xprintf("trap #%d", fault_status - 32);
-		}
-		else
-		{
-			xprintf("unknown fault status");
-		}
-	}
-	xprintf(")\r\n");
-	xprintf("sr=%4x\r\n", sr);
+    xprintf("vector = %02x (", vector);
+    switch (vector)
+    {
+    case 2:
+        xprintf("access error");
+        break;
+    case 3:
+        xprintf("address error");
+        break;
+    case 4:
+        xprintf("illegal instruction");
+        break;
+    case 5:
+        xprintf("divide by zero");
+        break;
+    case 8:
+        xprintf("privilege violation");
+        break;
+    case 9:
+        xprintf("trace");
+        break;
+    case 10:
+        xprintf("unimplemented line-a opcode");
+        break;
+    case 11:
+        xprintf("unimplemented line-f opcode");
+        break;
+    case 12:
+        xprintf("non-PC breakpoint debug interrupt");
+        break;
+    case 13:
+        xprintf("PC breakpoint debug interrupt");
+        break;
+    case 14:
+        xprintf("format error");
+        break;
+    case 24:
+        xprintf("spurious interrupt");
+        break;
+    default:
+        if ( ((vector >= 6) && (vector <= 7)) ||
+             ((vector >= 16) && (vector <= 23)))
+        {
+            xprintf("reserved");
+        }
+        else if ((vector >= 25) && (vector <= 31))
+        {
+            xprintf("level %d autovectored interrupt", fault_status - 24);
+        }
+        else if ((vector >= 32) && (vector <= 47))
+        {
+            xprintf("trap #%d", vector - 32);
+        }
+        else
+        {
+            xprintf("unknown vector\r\n");
+        }
+    }
+    xprintf(")\r\n");
+    xprintf("sr=%4x\r\n", sr);
+
+    __asm__ __volatile__(
+        " move.w    0x2700,d0       \r\n"       // disable interrupts
+        " move.w    d0,sr           \r\n"
+        " halt                      \r\n"       // stop processor
+        : /* no output */
+        : /* no input */
+        : "memory");
 }
 
 void __attribute__((interrupt)) handler(void)
 {
-	/*
-	 * Prepare exception stack contents so it can be handled by a C routine.
-	 *
-	 * For standard routines, we'd have to save registers here.
-	 * Since we do not intend to return anyway, we just ignore that requirement.
-	 */
-	__asm__ __volatile__("move.l	(sp),-(sp)\n\t"\
-						 "move.l	8(sp),-(sp)\n\t"\
-						 "bsr		_fault_handler\n\t"\
-						 "halt\n\t"\
-							: : : "memory");
+    /*
+     * Prepare exception stack contents so it can be handled by a C routine.
+     *
+     * For standard routines, we'd have to save registers here.
+     * Since we do not intend to return anyway, we just ignore that requirement.
+     */
+    __asm__ __volatile__("move.l    (sp),-(sp)\n\t"\
+                         "move.l    8(sp),-(sp)\n\t"\
+                         "bsr       _fault_handler\n\t"\
+                         "halt\n\t"\
+                            : : : "memory");
 }
 
 void setup_vectors(void)
 {
-	int i;
+    int i;
 
-	xprintf("\r\ninstall early exception vector table:");
+    xprintf("\r\ninstall early exception vector table:");
 
-	for (i = 8; i < 256; i++)
-	{
-		SDRAM_VECTOR_TABLE[i] = &handler;
-	}
+    for (i = 8; i < 256; i++)
+    {
+        SDRAM_VECTOR_TABLE[i] = &handler;
+    }
 
-	/*
-	 * make sure VBR points to our table
-	 */
-	__asm__ __volatile__("clr.l		d0\n\t"\
-						 "movec.l	d0,VBR\n\t"\
-						 "nop\n\t"\
-                         "move.l	d0,_rt_vbr"
+    /*
+     * make sure VBR points to our table
+     */
+    __asm__ __volatile__("clr.l     d0\n\t"\
+                         "movec.l   d0,VBR\n\t"\
+                         "nop\n\t"\
+                         "move.l    d0,_rt_vbr"
                          :                      /* outputs */
                          :                      /* inputs */
                          : "d0", "memory", "cc" /* clobbered registers */
                         );
 
-	xprintf("finished.\r\n");
+    xprintf("finished.\r\n");
 }

sys/init_fpga.c

@@ -34,54 +34,55 @@
 #define dbg(format, arg...) do { ; } while (0)
 #endif
 
-#define FPGA_STATUS		(1 << 0)
-#define FPGA_CLOCK		(1 << 1)
-#define FPGA_CONFIG		(1 << 2)
-#define FPGA_DATA0		(1 << 3)
-#define FPGA_CONF_DONE	(1 << 5)
+#define FPGA_STATUS     (1 << 0)
+#define FPGA_CLOCK      (1 << 1)
+#define FPGA_CONFIG     (1 << 2)
+#define FPGA_DATA0      (1 << 3)
+#define FPGA_CONF_DONE  (1 << 5)
 
 extern uint8_t _FPGA_CONFIG[];
-#define FPGA_FLASH_DATA	&_FPGA_CONFIG[0]
+#define FPGA_FLASH_DATA &_FPGA_CONFIG[0]
 extern uint8_t _FPGA_CONFIG_SIZE[];
-#define FPGA_FLASH_DATA_SIZE	((uint32_t) &_FPGA_CONFIG_SIZE[0])
+#define FPGA_FLASH_DATA_SIZE    ((uint32_t) &_FPGA_CONFIG_SIZE[0])
 
 /*
  * flag located in processor SRAM1 that indicates that the FPGA configuration has
- * been loaded through JTAG. init_fpga() will honour this and not overwrite config.
+ * been loaded through the onboard JTAG interface.
+ * init_fpga() will honour this and not overwrite config.
  */
 extern bool _FPGA_JTAG_LOADED;
-extern long _FPGA_JTAG_VALID;
-#define VALID_JTAG		0xaffeaffe
+extern int32_t _FPGA_JTAG_VALID;
+#define VALID_JTAG 0xaffeaffe
 
 void config_gpio_for_fpga_config(void)
 {
 #if defined(MACHINE_FIREBEE)
-	/*
-	 * Configure GPIO FEC1L port directions (needed to load FPGA configuration)
-	 */
-	MCF_GPIO_PDDR_FEC1L = 0 |								/* bit 7 = input */
-						  0	|								/* bit 6 = input */
-						  0 | 								/* bit 5 = input */
-						  MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 |	/* bit 4 = LED => output */
-						  MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 |	/* bit 3 = PRG_DQ0 => output */
-						  MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 |	/* bit 2 = FPGA_CONFIG => output */
-						  MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 |	/* bit 1 = PRG_CLK (FPGA) => output */
-						  0;								/* bit 0 => input */
+    /*
+     * Configure GPIO FEC1L port directions (needed to load FPGA configuration)
+     */
+    MCF_GPIO_PDDR_FEC1L = 0 |                   /* bit 7 = input */
+            0   |                               /* bit 6 = input */
+            0 |                                 /* bit 5 = input */
+            MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 |   /* bit 4 = LED => output */
+            MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 |   /* bit 3 = PRG_DQ0 => output */
+            MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 |   /* bit 2 = FPGA_CONFIG => output */
+            MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 |   /* bit 1 = PRG_CLK (FPGA) => output */
+            0;                                  /* bit 0 => input */
 #endif /* MACHINE_FIREBEE */
 }
 
 void config_gpio_for_jtag_config(void)
 {
-	/*
-	 * configure FEC1L port directions to enable external JTAG configuration download to FPGA
-	 */
-	MCF_GPIO_PDDR_FEC1L = 0 |
-						  MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4;	/* bit 4 = LED => output */
-															/* all other bits = input */
-	/*
-	 * unfortunately, the GPIO module cannot trigger interrupts. That means CONF_DONE needs to be polled to detect
-	 * external FPGA (re)configuration and reset the system in that case. Could be done from the OS as well...
-	 */
+    /*
+     * configure FEC1L port directions to enable external JTAG configuration download to FPGA
+     */
+    MCF_GPIO_PDDR_FEC1L = 0 |
+                          MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4;  /* bit 4 = LED => output */
+                                                            /* all other bits = input */
+    /*
+     * unfortunately, the GPIO module cannot trigger interrupts. That means CONF_DONE needs to be polled to detect
+     * external FPGA (re)configuration and reset the system in that case. Could be done from the OS as well...
+     */
 }
 
 /*
@@ -89,96 +90,100 @@ void config_gpio_for_jtag_config(void)
  */
 bool init_fpga(void)
 {
-	uint8_t *fpga_data;
-	volatile int32_t time, start, end;
-	int i;
+    uint8_t *fpga_data;
+    volatile int32_t time, start, end;
+    int i;
 
-	dbg("FPGA load config\r\n(_FPGA_JTAG_LOADED = %x, _FPGA_JTAG_VALID = %x)...\r\n", _FPGA_JTAG_LOADED, _FPGA_JTAG_VALID);
-	if (_FPGA_JTAG_LOADED == true && _FPGA_JTAG_VALID == VALID_JTAG)
-	{
-		dbg("detected _FPGA_JTAG_LOADED flag. Not overwriting FPGA config.\r\n");
+    dbg("FPGA load config\r\n(_FPGA_JTAG_LOADED = %x, _FPGA_JTAG_VALID = %x)...\r\n", _FPGA_JTAG_LOADED, _FPGA_JTAG_VALID);
+    if (_FPGA_JTAG_LOADED == true && _FPGA_JTAG_VALID == VALID_JTAG)
+    {
+        dbg("detected _FPGA_JTAG_LOADED flag. Not overwriting FPGA config.\r\n");
 
-		/* reset the flag so that next boot will load config again from flash */
-		_FPGA_JTAG_LOADED = 0;
-		return true;
-	}
-	start = MCF_SLT0_SCNT;
+        /* reset the flag so that next boot will load config again from flash */
+        _FPGA_JTAG_LOADED = 0;
+        _FPGA_JTAG_VALID = 0;
 
-	config_gpio_for_fpga_config();
-	MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;		/* FPGA clock => low */
+        return true;
+    }
+    start = MCF_SLT0_SCNT;
 
-	/* pulling FPGA_CONFIG to low resets the FPGA */
-	MCF_GPIO_PODR_FEC1L &= ~FPGA_CONFIG;	/* FPGA config => low */
-	wait(10);			/* give it some time to do its reset stuff */
+    config_gpio_for_fpga_config();
+    MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;                 /* FPGA clock => low */
 
-	while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS) && (MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));
+    /* pulling FPGA_CONFIG to low resets the FPGA */
+    MCF_GPIO_PODR_FEC1L &= ~FPGA_CONFIG;                /* FPGA config => low */
+    wait(10);                                           /* give it some time to do its reset stuff */
 
-	MCF_GPIO_PODR_FEC1L |= FPGA_CONFIG;				/* pull FPGA_CONFIG high to start config cycle */
-	while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS));	/* wait until status becomes high */
+    while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS) && (MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));
 
-	/*
-	 * excerpt from an Altera configuration manual:
-	 *
-	 * The low-to-high transition of nCONFIG on the FPGA begins the configuration cycle. The
-	 * configuration cycle consists of 3 stages<65>reset, configuration, and initialization.
-	 * While nCONFIG is low, the device is in reset. When the device comes out of reset,
-	 * nCONFIG must be at a logic high level in order for the device to release the open-drain
-	 * nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA
-	 * is ready to receive configuration data. Before and during configuration, all user I/O pins
-	 * are tri-stated. Stratix series, Arria series, and Cyclone series have weak pull-up resistors
-	 * on the I/O pins which are on, before and during configuration.
-	 *
-	 * To begin configuration, nCONFIG and nSTATUS must be at a logic high level. You can delay
-	 * configuration by holding the nCONFIG low. The device receives configuration data on its
-	 * DATA0 pins. Configuration data is latched into the FPGA on the rising edge of DCLK. After
-	 * the FPGA has received all configuration data successfully, it releases the CONF_DONE pin,
-	 * which is pulled high by a pull-up resistor. A low to high transition on CONF_DONE indicates
-	 * configuration is complete and initialization of the device can begin.
-	 */
+    MCF_GPIO_PODR_FEC1L |= FPGA_CONFIG;                 /* pull FPGA_CONFIG high to start config cycle */
+    while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS))
+        ;                                               /* wait until status becomes high */
 
-	const uint8_t *fpga_flash_data_end = FPGA_FLASH_DATA + FPGA_FLASH_DATA_SIZE;
+    /*
+     * excerpt from an Altera configuration manual:
+     *
+     * The low-to-high transition of nCONFIG on the FPGA begins the configuration cycle. The
+     * configuration cycle consists of 3 stages<65>reset, configuration, and initialization.
+     * While nCONFIG is low, the device is in reset. When the device comes out of reset,
+     * nCONFIG must be at a logic high level in order for the device to release the open-drain
+     * nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA
+     * is ready to receive configuration data. Before and during configuration, all user I/O pins
+     * are tri-stated. Stratix series, Arria series, and Cyclone series have weak pull-up resistors
+     * on the I/O pins which are on, before and during configuration.
+     *
+     * To begin configuration, nCONFIG and nSTATUS must be at a logic high level. You can delay
+     * configuration by holding the nCONFIG low. The device receives configuration data on its
+     * DATA0 pins. Configuration data is latched into the FPGA on the rising edge of DCLK. After
+     * the FPGA has received all configuration data successfully, it releases the CONF_DONE pin,
+     * which is pulled high by a pull-up resistor. A low to high transition on CONF_DONE indicates
+     * configuration is complete and initialization of the device can begin.
+     */
 
-	fpga_data = (uint8_t *) FPGA_FLASH_DATA;
-	do
-	{
-		uint8_t value = *fpga_data++;
-		for (i = 0; i < 8; i++, value >>= 1)
-		{
+    const uint8_t *fpga_flash_data_end = FPGA_FLASH_DATA + FPGA_FLASH_DATA_SIZE;
 
-			if (value & 1)
-			{
-				/* bit set -> toggle DATA0 to high */
-				MCF_GPIO_PODR_FEC1L |= FPGA_DATA0;
-			}
-			else
-			{
-				/* bit is cleared -> toggle DATA0 to low */
-				MCF_GPIO_PODR_FEC1L &= ~FPGA_DATA0;
-			}
-			/* toggle DCLK -> FPGA reads the bit */
-			MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK;
-			MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;
-		}
-	} while ((!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)) && (fpga_data < fpga_flash_data_end));
+    fpga_data = (uint8_t *) FPGA_FLASH_DATA;
+    do
+    {
+        uint8_t value = *fpga_data++;
+        for (i = 0; i < 8; i++, value >>= 1)
+        {
 
-	if (fpga_data < fpga_flash_data_end)
-	{
+            if (value & 1)
+            {
+                /* bit set -> toggle DATA0 to high */
+                MCF_GPIO_PODR_FEC1L |= FPGA_DATA0;
+            }
+            else
+            {
+                /* bit is cleared -> toggle DATA0 to low */
+                MCF_GPIO_PODR_FEC1L &= ~FPGA_DATA0;
+            }
+            /* toggle DCLK -> FPGA reads the bit */
+            MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK;
+            MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;
+        }
+    } while ((!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)) && (fpga_data < fpga_flash_data_end));
+
+    if (fpga_data < fpga_flash_data_end)
+    {
 #ifdef _NOT_USED_
-		while (fpga_data++ < fpga_flash_data_end)
-		{
-			/* toggle a little more since it's fun ;) */
-			MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK;
-			MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;
-		}
+        while (fpga_data++ < fpga_flash_data_end)
+        {
+            /* toggle a little more since it's fun ;) */
+            MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK;
+            MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;
+        }
 #endif /* _NOT_USED_ */
-		end = MCF_SLT0_SCNT;
-		time = (start - end) / (SYSCLK / 1000) / 1000;
+        end = MCF_SLT0_SCNT;
+        time = (start - end) / (SYSCLK / 1000) / 1000;
 
-		xprintf("finished (took %f seconds).\r\n", time / 1000.0);
-		config_gpio_for_jtag_config();
-		return true;
-	}
-	xprintf("FAILED!\r\n");
-	config_gpio_for_jtag_config();
-	return false;
+        xprintf("finished (took %f seconds).\r\n", time / 1000.0);
+        config_gpio_for_jtag_config();
+        return true;
+    }
+    xprintf("FAILED!\r\n");
+    config_gpio_for_jtag_config();
+
+    return false;
 }

sys/interrupts.c

@@ -35,63 +35,16 @@
 #include "cache.h"
 #include "util.h"
 #include "dma.h"
+#include "pci.h"
 
-extern void (*rt_vbr[])(void);
-#define VBR	rt_vbr
-
-#define IRQ_DEBUG
+//#define IRQ_DEBUG
 #if defined(IRQ_DEBUG)
 #define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif
+#define err(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
 
-/*
- * register an interrupt handler at the Coldfire interrupt controller and add the handler to
- * the interrupt vector table
- */
-int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority, uint8_t intr, void (*handler)(void))
-{
-	int ipl;
-	int i;
-	volatile uint8_t *ICR = &MCF_INTC_ICR01 - 1;
-	uint8_t lp;
-
-	source &= 63;
-	priority &= 7;
-
-	if (source < 1 || source > 63)
-	{
-		dbg("interrupt source %d not defined\r\n", source);
-		return -1;
-	}
-
-	lp = MCF_INTC_ICR_IL(level) | MCF_INTC_ICR_IP(priority);
-
-	/* check if this combination is already set somewhere */
-	for (i = 1; i < 64; i++)
-	{
-		if (ICR[i] == lp)
-		{
-			dbg("level %d and priority %d already used for interrupt source %d!\r\n",
-					level, priority, i);
-			return -1;
-		}
-	}
-
-	/* disable interrupts */
-	ipl = set_ipl(7);
-
-	VBR[64 + source] = handler;	/* first 64 vectors are system exceptions */
-
-	/* set level and priority in interrupt controller */
-	ICR[source] = lp;
-
-	/* set interrupt mask to where it was before */
-	set_ipl(ipl);
-
-	return 0;
-}
 
 #ifndef MAX_ISR_ENTRY
 #define MAX_ISR_ENTRY   (20)
@@ -100,10 +53,10 @@ int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority,
 
 struct isrentry
 {
-	int     vector;
-	int     (*handler)(void *, void *);
-	void    *hdev;
-	void    *harg;
+    int vector;
+    bool (*handler)(void *, void *);
+    void *hdev;
+    void *harg;
 };
 
 static struct isrentry isrtab[MAX_ISR_ENTRY];      /* list of interrupt service routines */
@@ -113,7 +66,62 @@ static struct isrentry isrtab[MAX_ISR_ENTRY];      /* list of interrupt service
  */
 void isr_init(void)
 {
-	memset(isrtab, 0, sizeof(isrtab));
+    memset(isrtab, 0, sizeof(isrtab));
+}
+
+bool isr_set_prio_and_level(int int_source, int priority, int level)
+{
+    if (int_source > 8 && int_source <= 62)
+    {
+        /*
+        * preset interrupt control registers with level and priority
+        */
+        dbg("set MCF_INTC_ICR(%d) to priority %d, level %d\r\n",
+            int_source, priority, level);
+        MCF_INTC_ICR(int_source) = MCF_INTC_ICR_IP(priority) |
+                                   MCF_INTC_ICR_IL(level);
+    }
+    else if (int_source >= 1 && int_source <= 8)
+    {
+        dbg("interrrupt control register for vector %d is read only!\r\n");
+    }
+    else
+    {
+        err("invalid vector - interrupt control register not set.\r\n");
+        return false;
+    }
+
+    return true;
+}
+
+/*
+ * enable internal int source in interrupt controller
+ */
+bool isr_enable_int_source(int int_source)
+{
+    dbg("anding int_source %d, MCF_INTC_IMR%c = 0x%08x, now 0x%08x\r\n",
+        int_source,
+        int_source < 32 && int_source > 0 ? 'L' :
+                    int_source >= 32 && int_source <= 62 ? 'H' : 'U',
+        int_source < 32 && int_source > 0 ? ~(1 << int_source) :
+                    int_source >= 32 && int_source <= 62 ? ~(1 << (int_source - 32)) : 0,
+        MCF_INTC_IMRH);
+
+    if (int_source < 32 && int_source > 0)
+    {
+        MCF_INTC_IMRL &= ~(1 << int_source);
+    }
+    else if (int_source >= 32 && int_source <= 62)
+    {
+        MCF_INTC_IMRH &= ~(1 << (int_source - 32));
+    }
+    else
+    {
+        err("vector %d does not correspond to an internal interrupt source\r\n");
+        return false;
+    }
+
+    return true;
 }
 
 /*
@@ -124,87 +132,105 @@ void isr_init(void)
  * pointer to the device itself, and the second a pointer to a data
  * structure used by the device driver for that particular device.
  */
-int isr_register_handler(int vector, int (*handler)(void *, void *), void *hdev, void *harg)
+bool isr_register_handler(int vector, int level, int priority, bool (*handler)(void *, void *), void *hdev, void *harg)
 {
-	int index;
+    int index;
+    int int_source;
 
-	if ((vector == 0) || (handler == NULL))
-	{
-		dbg("illegal vector or handler!\r\n");
-		return false;
-	}
+    if ((vector == 0) || (handler == NULL))
+    {
+        dbg("illegal vector or handler!\r\n");
 
-	for (index = 0; index < MAX_ISR_ENTRY; index++)
-	{
-		if (isrtab[index].vector == vector)
-		{
-			/* one cross each, only! */
-			dbg("already set handler with this vector (%d, %d)\r\n", vector);
-			return false;
-		}
+        return false;
+    }
 
-		if (isrtab[index].vector == 0)
-		{
-			isrtab[index].vector = vector;
-			isrtab[index].handler = handler;
-			isrtab[index].hdev = hdev;
-			isrtab[index].harg = harg;
+    for (index = 0; index < MAX_ISR_ENTRY; index++)
+    {
+        if (isrtab[index].vector == vector)
+        {
+            /* one cross each, only! */
+            dbg("already set handler with this vector (%d, %d)\r\n", vector);
 
-			return true;
-		}
-	}
-	dbg("no available slots to register handler for vector %d\n\r", vector);
+            return false;
+        }
 
-	return false;   /* no available slots */
+        if (isrtab[index].vector == 0)
+        {
+            isrtab[index].vector = vector;
+            isrtab[index].handler = handler;
+            isrtab[index].hdev = hdev;
+            isrtab[index].harg = harg;
+
+            int_source = vector - 64;
+
+            if (!isr_enable_int_source(int_source))
+            {
+                err("failed to enable internal interrupt souce %d in IMRL/IMRH\r\n", int_source);
+                return false;
+            }
+
+            if (!isr_set_prio_and_level(int_source, priority, level))
+            {
+                err("failed to set priority and level for interrupt source %d\r\n", int_source);
+                return false;
+            }
+
+            return true;
+        }
+    }
+    dbg("no available slots to register handler for vector %d\n\r", vector);
+
+    return false;   /* no available slots */
 }
 
-void isr_remove_handler(int (*handler)(void *, void *))
+void isr_remove_handler(bool (*handler)(void *, void *))
 {
-	/*
-	 * This routine removes from the ISR table all
-	 * entries that matches 'handler'.
-	 */
-	int index;
+    /*
+     * This routine removes from the ISR table all
+     * entries that matches 'handler'.
+     */
+    int index;
 
-	for (index = 0; index < MAX_ISR_ENTRY; index++)
-	{
-		if (isrtab[index].handler == handler)
-		{
-			memset(&isrtab[index], 0, sizeof(struct isrentry));
+    for (index = 0; index < MAX_ISR_ENTRY; index++)
+    {
+        if (isrtab[index].handler == handler)
+        {
+            memset(&isrtab[index], 0, sizeof(struct isrentry));
 
-			return;
-		}
-	}
-	dbg("no such handler registered (handler=%p\r\n", handler);
+            return;
+        }
+    }
+    dbg("no such handler registered (handler=%p\r\n", handler);
 }
 
 /*
  * This routine searches the ISR table for an entry that matches
- * 'vector'.  If one is found, then 'handler' is executed.
+ * 'vector'. If one is found, then 'handler' is executed.
+ *
+ * This routine returns either true or false where
+ *  true = interrupt has been handled, return to caller
+ *  false= interrupt has been handled or hasn't, but needs to be forwarded to TOS
  */
 bool isr_execute_handler(int vector)
 {
-	int index;
-	bool retval = false;
+    int index;
 
-	/*
-	 * locate a BaS Interrupt Service Routine handler.
-	 */
-	for (index = 0; index < MAX_ISR_ENTRY; index++)
-	{
-		if (isrtab[index].vector == vector)
-		{
-			retval = true;
+    dbg("vector = %d\r\n", vector);
 
-			if (isrtab[index].handler(isrtab[index].hdev, isrtab[index].harg))
-			{
-				return retval;
-			}
-		}
-	}
-	dbg("no BaS isr handler for vector %d found\r\n", vector);
+    /*
+     * locate an interrupt service routine handler.
+     */
+    for (index = 0; index < MAX_ISR_ENTRY; index++)
+    {
+        if (isrtab[index].vector == vector)
+        {
+            isrtab[index].handler(isrtab[index].hdev, isrtab[index].harg);
+            return true;
+        }
+    }
+    err("no isr handler for vector %d found. Spurious?\r\n", vector);
 
-	return retval;
+    return true;
 }
 
 /*
@@ -213,139 +239,140 @@ bool isr_execute_handler(int vector)
  * Handles PIC requests that come in from PSC3 serial interface. Currently, that
  * is RTC/NVRAM requests only
  */
-int pic_interrupt_handler(void *arg1, void *arg2)
+bool pic_interrupt_handler(void *arg1, void *arg2)
 {
-	uint8_t rcv_byte;
+    uint8_t rcv_byte;
 
-	rcv_byte = MCF_PSC3_PSCRB_8BIT;
-	if (rcv_byte == 2)	// PIC requests RTC data
-	{
-		uint8_t *rtc_reg = (uint8_t *) 0xffff8961;
-		uint8_t *rtc_data = (uint8_t *) 0xffff8963;
-		int index = 0;
+    rcv_byte = MCF_PSC3_PSCRB_8BIT;
+    if (rcv_byte == 2)                  /* PIC requests RTC data */
+    {
+        uint8_t *rtc_reg = (uint8_t *) 0xffff8961;
+        uint8_t *rtc_data = (uint8_t *) 0xffff8963;
+        int index = 0;
 
-		xprintf("PIC interrupt: requesting RTC data\r\n");
+        err("PIC interrupt: requesting RTC data\r\n");
 
-		MCF_PSC3_PSCTB_8BIT = 0x82;		// header byte to PIC
-		do
-		{
-			*rtc_reg = 0;
-			MCF_PSC3_PSCTB_8BIT = *rtc_data;
-		} while (index++ < 64);
-	}
-	return 1;
+        MCF_PSC3_PSCTB_8BIT = 0x82;     // header byte to PIC
+        do
+        {
+            *rtc_reg = 0;
+            MCF_PSC3_PSCTB_8BIT = *rtc_data;
+        } while (index++ < 64);
+    }
+    return true;
 }
 
-extern int32_t video_sbt;
-extern int32_t video_tlb;
-
-void video_addr_timeout(void)
+bool xlbpci_interrupt_handler(void *arg1, void *arg2)
 {
-	uint32_t addr = 0x0L;
-	uint32_t *src;
-	uint32_t *dst;
-	uint32_t asid;
+    uint32_t reason;
 
-	dbg("video address timeout\r\n");
-	flush_and_invalidate_caches();
+    dbg("XLB PCI interrupt\r\n");
 
-	do
-	{
-		uint32_t tlb;
-		uint32_t page_attr;
+    reason = MCF_PCI_PCIISR;
 
-		/*
-		 * search tlb entry id for addr (if not available, the MMU
-		 * will provide a new one based on its LRU algorithm)
-		 */
-		MCF_MMU_MMUAR = addr;
-		MCF_MMU_MMUOR =
-				MCF_MMU_MMUOR_STLB |
-				MCF_MMU_MMUOR_RW |
-				MCF_MMU_MMUOR_ACC;
-		NOP();
-		tlb = (MCF_MMU_MMUOR >> 16) & 0xffff;
+    if (reason & MCF_PCI_PCIISR_RE)
+    {
+        dbg("Retry error. Retry terminated or max retries reached. Cleared\r\n");
+        MCF_PCI_PCIISR |= MCF_PCI_PCIISR_RE;
+    }
 
-		/*
-		 * retrieve tlb entry with the found TLB entry id
-		 */
-		MCF_MMU_MMUAR = tlb;
-		MCF_MMU_MMUOR =
-				MCF_MMU_MMUOR_STLB |
-				MCF_MMU_MMUOR_ADR |
-				MCF_MMU_MMUOR_RW |
-				MCF_MMU_MMUOR_ACC;
-		NOP();
+    if (reason & MCF_PCI_PCIISR_IA)
+    {
+        dbg("Initiator abort. No target answered in time. Cleared.\r\n");
+        MCF_PCI_PCIISR |= MCF_PCI_PCIISR_IA;
+    }
 
-		asid = (MCF_MMU_MMUTR >> 2) & 0x1fff;	/* fetch ASID of page */;
-		if (asid != sca_page_ID)                /* check if screen area */
-		{
-			addr += 0x100000;
-			continue;                           /* next page */
-		}
+    if (reason & MCF_PCI_PCIISR_TA)
+    {
+        dbg("Target abort. Cleared.\r\n");
+        MCF_PCI_PCIISR |= MCF_PCI_PCIISR_TA;
+    }
 
-		/* modify found TLB entry */
-		if (addr == 0x0)
-		{
-			page_attr =
-				MCF_MMU_MMUDR_LK |
-				MCF_MMU_MMUDR_SZ(0) |
-				MCF_MMU_MMUDR_CM(0) |
-				MCF_MMU_MMUDR_R |
-				MCF_MMU_MMUDR_W |
-				MCF_MMU_MMUDR_X;
-		}
-		else
-		{
-			page_attr =
-				MCF_MMU_MMUTR_SG |
-				MCF_MMU_MMUTR_V;
-		}
-
-
-		MCF_MMU_MMUTR = addr;
-		MCF_MMU_MMUDR = page_attr;
-		MCF_MMU_MMUOR =
-				MCF_MMU_MMUOR_STLB |
-				MCF_MMU_MMUOR_ADR |
-				MCF_MMU_MMUOR_ACC |
-				MCF_MMU_MMUOR_UAA;
-		NOP();
-
-		dst = (uint32_t *) 0x60000000 + addr;
-		src = (uint32_t *) addr;
-		while (dst < (uint32_t *) 0x60000000 + addr + 0x10000)
-		{
-			*dst++ = *src++;
-			*dst++ = *src++;
-			*dst++ = *src++;
-			*dst++ = *src++;
-		}
-
-
-
-		addr += 0x100000;
-	} while (addr < 0xd00000);
-	video_tlb = 0x2000;
-	video_sbt = 0;
+    return true;
 }
 
+bool pciarb_interrupt_handler(void *arg1, void *arg2)
+{
+    dbg("PCI ARB interrupt\r\n");
+
+    return true;
+}
+
+#if defined(MACHINE_FIREBEE)
+/*
+ * This gets called from irq5 in exceptions.S
+ *
+ * IRQ5 are the "FBEE" (PIC, ETH PHY, PCI, DVI monitor sense and DSP) interrupts multiplexed by the FPGA interrupt handler
+ */
+bool irq5_handler(void *arg1, void *arg2)
+{
+    uint32_t pending_interrupts = FBEE_INTR_PENDING;
+
+    dbg("IRQ5!\r\n");
+    if (pending_interrupts & FBEE_INTR_PIC)
+    {
+        dbg("PIC interrupt\r\n");
+        FBEE_INTR_CLEAR = FBEE_INTR_PIC;
+    }
+
+    if (pending_interrupts & FBEE_INTR_ETHERNET)
+    {
+        dbg("ethernet 0 PHY interrupt\r\n");
+        FBEE_INTR_CLEAR = FBEE_INTR_ETHERNET;
+    }
+
+    if (pending_interrupts & FBEE_INTR_DVI)
+    {
+        dbg("DVI monitor sense interrupt\r\n");
+        FBEE_INTR_CLEAR = FBEE_INTR_DVI;
+    }
+
+    if (pending_interrupts & FBEE_INTR_PCI_INTA ||
+        pending_interrupts & FBEE_INTR_PCI_INTB ||
+        pending_interrupts & FBEE_INTR_PCI_INTC ||
+        pending_interrupts & FBEE_INTR_PCI_INTD)
+    {
+        dbg("PCI interrupt IRQ5\r\n");
+        FBEE_INTR_CLEAR = FBEE_INTR_PCI_INTA |
+                          FBEE_INTR_PCI_INTB |
+                          FBEE_INTR_PCI_INTC |
+                          FBEE_INTR_PCI_INTD;
+    }
+
+    if (pending_interrupts & FBEE_INTR_DSP)
+    {
+        dbg("DSP interrupt\r\n");
+        FBEE_INTR_CLEAR = FBEE_INTR_DSP;
+    }
+
+    if (pending_interrupts & FBEE_INTR_VSYNC || pending_interrupts & FBEE_INTR_HSYNC)
+    {
+        dbg("vsync or hsync interrupt!\r\n");
+        FBEE_INTR_CLEAR = FBEE_INTR_VSYNC | FBEE_INTR_HSYNC;
+        /* hsync and vsync should go to TOS unhandled */
+        return false;
+    }
+
+    MCF_EPORT_EPFR |= (1 << 5);             /* clear interrupt from edge port */
+
+    return true;
+}
 
 /*
  * blink the Firebee's LED to show we are still alive
  */
 void blink_led(void)
 {
-	static uint16_t blinker = 0;
+    static uint16_t blinker = 0;
 
-	if ((blinker++ & 0x80) > 0)
-	{
-		MCF_GPIO_PODR_FEC1L |= (1 << 4);    /* LED off */
-	}
-	else
-	{
-		MCF_GPIO_PODR_FEC1L &= ~(1 << 4);   /* LED on */
-	}
+    if ((blinker++ & 0x80) > 0)
+    {
+        MCF_GPIO_PODR_FEC1L |= (1 << 4);    /* LED off */
+    }
+    else
+    {
+        MCF_GPIO_PODR_FEC1L &= ~(1 << 4);   /* LED on */
+    }
 }
 
 /*
@@ -363,57 +390,74 @@ void blink_led(void)
 
 bool irq6_acsi_dma_interrupt(void)
 {
-	dbg("ACSI DMA interrupt\r\n");
+    dbg("ACSI DMA interrupt\r\n");
 
-	/*
-	 * TODO: implement handler
-	 */
+    /*
+     * TODO: implement handler
+     */
 
-	return false;
+    return false;
 }
 
-bool irq6_interrupt_handler(uint32_t sf1, uint32_t sf2)
+bool irq6_handler(uint32_t sf1, uint32_t sf2)
 {
-	bool handled = false;
+    //err("IRQ6!\r\n");
 
-	MCF_EPORT_EPFR |= (1 << 6);	/* clear int6 from edge port */
+    if (FALCON_MFP_IPRA || FALCON_MFP_IPRB)
+    {
+        blink_led();
+    }
 
-	if (video_sbt != 0 && (video_sbt - 0x70000000) > MCF_SLT0_SCNT)
-	{
-		video_addr_timeout();
-		handled = true;
-	}
+    MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */
 
-	/*
-	 * check if ACSI DMA interrupt
-	 */
-
-	if (FALCON_MFP_IERA & (1 << 7))
-	{
-		/* ACSI interrupt is enabled */
-		if (FALCON_MFP_IPRA & (1 << 7))
-		{
-			irq6_acsi_dma_interrupt();
-			handled = true;
-		}
-	}
-
-	if (FALCON_MFP_IPRA || FALCON_MFP_IPRB)
-	{
-		blink_led();
-	}
-
-	return handled;
+    return false;               /* always forward IRQ6 to TOS */
 }
 
+#else /* MACHINE_FIREBEE */
+
+bool irq5_handler(void *arg1, void *arg2)
+{
+    MCF_EPORT_EPFR |= (1 << 5); /* clear int5 from edge port */
+
+    return true;
+}
+
+bool irq6_handler(void *arg1, void *arg2)
+{
+    err("IRQ6!\r\n");
+
+    MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */
+
+    return false;       /* always forward IRQ6 to TOS */
+}
+
+/*
+ * This gets called from irq7 in exceptions.S
+ * Once we arrive here, the SR has been set to disable interrupts and the gcc scratch registers have been saved
+ */
+bool irq7_handler(void)
+{
+    int32_t handle;
+    int32_t value = 0;
+    int32_t newvalue;
+
+    MCF_EPORT_EPFR |= (1 << 7);
+    dbg("IRQ7!\r\n");
+    if ((handle = pci_get_interrupt_cause()) > 0)
+    {
+        newvalue = pci_call_interrupt_chain(handle, value);
+        if (newvalue == value)
+        {
+            dbg("interrupt not handled!\r\n");
+        }
+    }
+    MCF_EPORT_EPFR |= (1 << 7); /* clear int7 from edge port */
+
+    return true;
+}
+#endif /* MACHINE_M548X */
+
 #if defined(MACHINE_FIREBEE)
-#define vbasehi		(* (volatile uint8_t *) 0xffff8201)
-#define vbasemid	(* (volatile uint8_t *) 0xffff8203)
-#define vbaselow	(* (volatile uint8_t *) 0xffff820d)
-
-#define vwrap		(* (volatile uint16_t *) 0xffff8210)
-#define vde			(* (volatile uint16_t *) 0xffff82aa)
-#define vdb			(* (volatile uint16_t *) 0xffff82a8)
 /*
  * this is the higlevel interrupt service routine for gpt0 timer interrupts.
  *
@@ -428,114 +472,14 @@ bool irq6_interrupt_handler(uint32_t sf1, uint32_t sf2)
  * video RAM starting at 0x60000000) and copies SDRAM contents of that page to the video
  * RAM page.
  */
-void gpt0_interrupt_handler(void)
+bool gpt0_interrupt_handler(void *arg0, void *arg1)
 {
-	uint32_t video_address;
-	uint32_t video_end_address;
-	int page_number;
-	bool already_set;
-	extern uint32_t _STRAM_END;
+    dbg("handler called\n\r");
 
-	dbg("screen base = 0x%x\r\n", vbasehi);
+    MCF_GPT0_GMS &= ~1;     /* rearm trigger */
+    NOP();
+    MCF_GPT0_GMS |= 1;
 
-	if (vbasehi < 2)			/* screen base lower than 0x20000? */
-	{
-		goto rearm_trigger;		/* do nothing */
-	}
-	else if (vbasehi >= 0xd0)	/* higher than 0xd00000 (normal Falcon address)? */
-	{
-		video_sbt = MCF_SLT0_SCNT;	/* FIXME: no idea why we need to save the time here */
-	}
-	video_address = (vbasehi << 16) | (vbasemid << 8) | vbaselow;
-
-	page_number = video_address >> 20;				/* calculate a page number */
-	already_set = (video_tlb & (1 << page_number));	/* already in bitset? */
-	video_tlb |= page_number;						/* set it */
-
-	if (! already_set)	/* newly set page, need to copy contents */
-	{
-		flush_and_invalidate_caches();
-		dma_memcpy((uint8_t *) video_address + 0x60000000, (uint8_t *) video_address, 0x100000);
-
-		/*
-		 * create an MMU TLB entry for the new video page
-		 */
-
-		/*
-		 * first search for an existing entry with our address. If none is found,
-		 * the MMU will propose a new one
-		 */
-		MCF_MMU_MMUAR = video_address;
-		MCF_MMU_MMUOR = 0x106;
-		NOP();
-
-		/*
-		 * take this MMU TLB entry and set it to our video address and page mapping
-		 */
-		MCF_MMU_MMUAR = (MCF_MMU_MMUOR >> 16) & 0xffff;	/* set TLB id */
-
-		MCF_MMU_MMUTR = video_address |
-						MCF_MMU_MMUTR_ID(sca_page_ID) |	/* set video page ID */
-						MCF_MMU_MMUTR_SG |				/* shared global */
-						MCF_MMU_MMUTR_V;				/* valid */
-		MCF_MMU_MMUDR = (video_address + 0x60000000) |	/* physical address */
-						MCF_MMU_MMUDR_SZ(0) |			/* 1 MB page size */
-						MCF_MMU_MMUDR_CM(0) |			/* writethrough */
-						MCF_MMU_MMUDR_R |				/* readable */
-						MCF_MMU_MMUDR_W |				/* writeable */
-						MCF_MMU_MMUDR_X;				/* executable */
-		MCF_MMU_MMUOR = 0x10b;							/* update TLB entry */
-	}
-
-	/*
-	 * Calculate the effective screen memory size to see if we need to map another page
-	 * in case the new screen spans more than one single page
-	 */
-	video_end_address = video_address + (vde - vdb) * vwrap;
-	if (video_end_address < _STRAM_END)
-	{
-		page_number = video_end_address >> 20;			/* calculate a page number */
-		already_set = (video_tlb & (1 << page_number));	/* already in bitset? */
-		video_tlb |= page_number;						/* set it */
-
-		if (! already_set)	/* newly set page, need to copy contents */
-		{
-			flush_and_invalidate_caches();
-			dma_memcpy((uint8_t *) video_end_address + 0x60000000, (uint8_t *) video_end_address, 0x100000);
-
-			/*
-			 * create an MMU TLB entry for the new video page
-			 */
-
-			/*
-			 * first search for an existing entry with our address. If none is found,
-			 * the MMU will propose a new one
-			 */
-			MCF_MMU_MMUAR = video_end_address;
-			MCF_MMU_MMUOR = 0x106;
-			NOP();
-
-			/*
-			 * take this MMU TLB entry and set it to our video address and page mapping
-			 */
-			MCF_MMU_MMUAR = (MCF_MMU_MMUOR >> 16) & 0xffff;	/* set TLB id */
-
-			MCF_MMU_MMUTR = video_end_address |
-							MCF_MMU_MMUTR_ID(sca_page_ID) |	/* set video page ID */
-							MCF_MMU_MMUTR_SG |				/* shared global */
-							MCF_MMU_MMUTR_V;				/* valid */
-			MCF_MMU_MMUDR = (video_end_address + 0x60000000) |	/* physical address */
-							MCF_MMU_MMUDR_SZ(0) |			/* 1 MB page size */
-							MCF_MMU_MMUDR_CM(0) |			/* writethrough */
-							MCF_MMU_MMUDR_R |				/* readable */
-							MCF_MMU_MMUDR_W |				/* writeable */
-							MCF_MMU_MMUDR_X;				/* executable */
-			MCF_MMU_MMUOR = 0x10b;							/* update TLB entry */
-		}
-	}
-rearm_trigger:
-	MCF_GPT0_GMS &= ~1;		/* rearm trigger */
-	NOP();
-	MCF_GPT0_GMS |= 1;
+    return true;
 }
 #endif /* MACHINE_FIREBEE */

tos/Makefile

@@ -1,11 +1,15 @@
 .PHONY: tos
 .PHONY: jtagwait
-.PHONY: mcdcook
-tos: jtagwait mcdcook
+.PHONY: bascook
+.PHONY: vmem_test
+tos: jtagwait bascook vmem_test
 
 jtagwait:
 	(cd $@; make)
 
 bascook:
 	(cd $@; make)
-	
+
+vmem_test:
+	(cd $@; make)
+

tos/bascook/sources/bascook.c

@@ -7,116 +7,158 @@
 
 struct driver_table *get_bas_drivers(void)
 {
-	struct driver_table *ret = NULL;
+    struct driver_table *ret = NULL;
 
-	__asm__ __volatile(
-		"	trap	#0\n\t"
-		"	move.l	d0,%[ret]\n\t"
-		:	[ret] "=m" (ret)	/* output */
-		:						/* no inputs */
-		:						/* clobbered */
-	);
+    __asm__ __volatile__(
+        "			bra.s	 do_trap			\n\t"
+        "			.dc.l	0x5f424153			\n\t"	// '_BAS'
+        "do_trap:	trap	#0					\n\t"
+        "			move.l	d0,%[ret]			\n\t"
+        :	[ret] "=m" (ret)	/* output */
+        :						/* no inputs */
+        :						/* clobbered */
+    );
 
-	return ret;
+    return ret;
+}
+
+/*
+ * temporarily replace the trap 0 handler with this so we can avoid
+ * getting caught by BaS versions that don't understand the driver interface
+ * exposure call.
+ * If we get here, we have a BaS version that doesn't support the trap 0 interface
+ */
+static void __attribute__((interrupt)) my_own_trap0_handler(void)
+{
+    __asm__ __volatile__(
+        "		clr.l		d0				\n\t"		// return 0 to indicate not supported
+        :
+        :
+        :
+    );
 }
 
 static uint32_t cookieptr(void)
 {
-	return * (uint32_t *) 0x5a0L;
+    return * (uint32_t *) 0x5a0L;
 }
 
 void setcookie(uint32_t cookie, uint32_t value)
 {
-	uint32_t *cookiejar = (uint32_t *) Supexec(cookieptr);
-	int num_slots;
-	int max_slots;
+    uint32_t *cookiejar = (uint32_t *) Supexec(cookieptr);
+    int num_slots;
+    int max_slots;
 
-	num_slots = max_slots = 0;
-	do
-	{
-		if (cookiejar[0] == cookie)
-		{
-			cookiejar[1] = value;
-			return;
-		}
-		cookiejar = &(cookiejar[2]);
-		num_slots++;
-	} while (cookiejar[-2]);
+    num_slots = max_slots = 0;
+    do
+    {
+        if (cookiejar[0] == cookie)
+        {
+            cookiejar[1] = value;
+            return;
+        }
+        cookiejar = &(cookiejar[2]);
+        num_slots++;
+    } while (cookiejar[-2]);
 
-	/*
-	 * Here we are at the end of the list and did not find our cookie.
-	 * Let's check if there is any space left and append our value to the
-	 * list if so. If not, we are lost (extending the cookie jar does only
-	 * work from TSRs)
-	 */
-	if (cookiejar[-1])
-		max_slots = cookiejar[-1];
+    /*
+     * Here we are at the end of the list and did not find our cookie.
+     * Let's check if there is any space left and append our value to the
+     * list if so. If not, we are lost (extending the cookie jar does only
+     * work from TSRs)
+     */
+    if (cookiejar[-1])
+    {
+        max_slots = cookiejar[-1];
+    }
 
-	if (max_slots > num_slots)
-	{
-		 /* relief, there is space left, extend the list */
-		cookiejar[0] = cookiejar[-2];
-		cookiejar[1] = cookiejar[-1];
-		/* add the new element */
-		cookiejar[-2] = cookie;
-		cookiejar[-1] = value;
-	}
-	else
-		printf("cannot set cookie, cookie jar is full!\r\n");
+    if (max_slots > num_slots)
+    {
+         /* relief, there is space left, extend the list */
+        cookiejar[0] = cookiejar[-2];
+        cookiejar[1] = cookiejar[-1];
+        /* add the new element */
+        cookiejar[-2] = cookie;
+        cookiejar[-1] = value;
+    }
+    else
+        printf("cannot set cookie, cookie jar is full!\r\n");
 }
 
-# define COOKIE_DMAC	0x444D4143L /* FireTOS DMA API */
+#define COOKIE_DMAC	0x444d4143L /* FireTOS DMA API */
 
 static char *dt_to_str(enum driver_type dt)
 {
-	switch (dt)
-	{
-		case BLOCKDEV_DRIVER: return "generic block device driver";
-		case CHARDEV_DRIVER:  return "generic character device driver";
-		case VIDEO_DRIVER:    return "video/framebuffer driver";
-		case XHDI_DRIVER:     return "XHDI compatible hard disk driver";
-		case MCD_DRIVER:	  return "multichannel DMA driver";
-		case PCI_DRIVER:	  return "PCI interface driver";
-		default:              return "unknown driver type";
-	}
+    switch (dt)
+    {
+        case BLOCKDEV_DRIVER: return "generic block device driver";
+        case CHARDEV_DRIVER:  return "generic character device driver";
+        case VIDEO_DRIVER:    return "video/framebuffer driver";
+        case XHDI_DRIVER:     return "XHDI compatible hard disk driver";
+        case MCD_DRIVER:	  return "multichannel DMA driver";
+        case PCI_DRIVER:	  return "PCI interface driver";
+        case MMU_DRIVER:	  return "MMU lock/unlock pages driver";
+        default:              return "unknown driver type";
+    }
 }
 
 int main(int argc, char *argv[])
 {
-	struct driver_table *dt;
-	void *ssp;
+    struct driver_table *dt;
+    void *ssp;
+    void *old_vector;
+    char **sysbase = (char **) 0x4f2;
+    uint32_t sig;
 
-	(void) Cconws("retrieve BaS driver interface\r\n");
+    (void) Cconws("retrieve BaS driver interface\r\n");
 
-	ssp = (void *) Super(0L);
-	dt = get_bas_drivers();
-	if (dt)
-	{
-		struct generic_interface *ifc = &dt->interfaces[0];
+    ssp = (void *) Super(0L);								/* go to supervisor mode, we are doing dirty tricks */
+    sig = * (long *)((*sysbase) + 0x2c);
+    /*
+     * first check if we are on EmuTOS, FireTOS want's to do everything itself
+     */
+    if (sig == 0x45544f53)
+    {
+        old_vector = Setexc(0x20, my_own_trap0_handler);		/* set our own temporarily */
+        dt = get_bas_drivers();									/* trap #0 */
+        (void) Setexc(0x20, old_vector);						/* restore original vector */
 
-		printf("BaS driver table found at %p, BaS version is %d.%d\r\n", dt,
-				dt->bas_version, dt->bas_revision);
+        if (dt)
+        {
+            struct generic_interface *ifc = &dt->interfaces[0];
 
-		while (ifc->type != END_OF_DRIVERS)
-		{
-			printf("driver \"%s (%s)\" found,\r\n"
-				   "interface type is %d (%s),\r\n"
-				   "version %d.%d\r\n\r\n",
-					ifc->name, ifc->description, ifc->type, dt_to_str(ifc->type),
-					ifc->version, ifc->revision);
-			if (ifc->type == MCD_DRIVER)
-			{
-				setcookie(COOKIE_DMAC, (uint32_t) ifc->interface.dma);
-				printf("\r\nDMAC cookie set to %p\r\n", ifc->interface.dma);
-			}
-			ifc++;
-		}
-	}
-	Super(ssp);
+            printf("BaS driver table found at %p, BaS version is %d.%d\r\n", dt,
+                    dt->bas_version, dt->bas_revision);
 
-	while (Cconis()) Cconin();	/* eat keys */
-	// printf("press any key to continue\n\r");
-	// while (! Cconis());
-	return 0;
+            while (ifc->type != END_OF_DRIVERS)
+            {
+                printf("driver \"%s (%s)\" found,\r\n"
+                       "interface type is %d (%s),\r\n"
+                       "version %d.%d\r\n\r\n",
+                        ifc->name, ifc->description, ifc->type, dt_to_str(ifc->type),
+                        ifc->version, ifc->revision);
+                if (ifc->type == MCD_DRIVER)
+                {
+                    setcookie(COOKIE_DMAC, (uint32_t) ifc->interface.dma);
+                    printf("\r\nDMAC cookie set to %p\r\n", ifc->interface.dma);
+                }
+                ifc++;
+            }
+        }
+        else
+        {
+            printf("driver table not found.\r\n");
+        }
+    }
+    else
+    {
+        printf("not running on EmuTOS,\r\n(signature 0x%04x instead of 0x%04x\r\n",
+               (uint32_t) sig, 0x45544f53);
+    }
+    Super(ssp);
+
+    while (Cconis()) Cconin();	/* eat keys */
+
+    return 0;
 }
 

tos/jtagwait/sources/jtagwait.c

@@ -7,12 +7,12 @@
 #include "MCF5475.h"
 #include "driver_vec.h"
 
-extern bool _FPGA_JTAG_LOADED;
-extern long	_FPGA_JTAG_VALID;
+extern long _FPGA_JTAG_LOADED;
+extern long _FPGA_JTAG_VALID;
 
-#define VALID_JTAG	0xaffeaffe
+#define VALID_JTAG  0xaffeaffe
 
-#define FPGA_CONFIG                     	(1 << 2)
+#define FPGA_CONFIG                         (1 << 2)
 #define FPGA_CONF_DONE                      (1 << 5)
 
 #define SRAM1_START     0xff101000
@@ -22,108 +22,102 @@ extern long	_FPGA_JTAG_VALID;
 #define NOP() __asm__ __volatile__("nop\n\t" : : : "memory")
 
 long bas_start = 0xe0000000;
-volatile uint32_t *_VRAM = (uint32_t *) 0xFFF00000;
+volatile uint32_t *_VRAM = (uint32_t *) 0x60000000;
 
 
 void wait_for_jtag(void)
 {
-	int i;
+    int i;
 
-	/* set supervisor stack to end of SRAM1 */
-	__asm__ __volatile__ (
-		"		move	#0x2700,sr\n\t"			/* disable interrupts */
-		"		move.l	%[stack],d0\n\t"		/* 4KB on-chip core SRAM1 */
-		"		move.l	d0,sp\n\t"				/* set stack pointer */
-		:
-		: [stack] "i" (SAFE_STACK)
-		: "d0", "cc"	/* clobber */
-	);
+    /* set supervisor stack to end of SRAM1 */
+    __asm__ __volatile__ (
+        "       move    #0x2700,sr\n\t"         /* disable interrupts */
+        "       move.l  %[stack],d0\n\t"        /* 4KB on-chip core SRAM1 */
+        "       move.l  d0,sp\n\t"              /* set stack pointer */
+        :
+        : [stack] "i" (SAFE_STACK)
+        : "d0", "cc"    /* clobber */
+    );
 
-	MCF_EPORT_EPIER = 0x0;				/* disable EPORT interrupts */
-	MCF_INTC_IMRL = 0xffffffff;
-	MCF_INTC_IMRH = 0xffffffff;			/* disable interrupt controller */
+    MCF_EPORT_EPIER = 0x0;              /* disable EPORT interrupts */
+    MCF_INTC_IMRL = 0xffffffff;
+    MCF_INTC_IMRH = 0xffffffff;         /* disable interrupt controller */
 
-	MCF_MMU_MMUCR &= ~MCF_MMU_MMUCR_EN;	/* disable MMU */
+    MCF_MMU_MMUCR &= ~MCF_MMU_MMUCR_EN; /* disable MMU */
 
-	xprintf("relocated supervisor stack, disabled interrupts and disabled MMU\r\n");
+    xprintf("relocated supervisor stack, disabled interrupts and disabled MMU\r\n");
 
-	/*
-	 * configure FEC1L port directions to enable external JTAG configuration download to FPGA
-	 */
-	MCF_GPIO_PDDR_FEC1L = 0 |
-						  MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4;	/* bit 4 = LED => output */
-															/* all other bits = input */
+    /*
+     * configure FEC1L port directions to enable external JTAG configuration download to FPGA
+     */
+    MCF_GPIO_PDDR_FEC1L = 0 |
+                          MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4;  /* bit 4 = LED => output */
+                                                            /* all other bits = input */
 
-	/*
-	 * now that GPIO ports have been switched to input, we can poll for FPGA config
-	 * started from the JTAG interface (CONF_DONE goes low) and finish (CONF_DONE goes high)
-	 */
-	xprintf("waiting for JTAG configuration start\r\n");
-	while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));		/* wait for JTAG config load started */
+    /*
+     * configure DSPI_CS3 as GPIO input to avoid the MCU driving against the FPGA blink
+     */
+    MCF_PAD_PAR_DSPI &= ~MCF_PAD_PAR_DSPI_PAR_CS3(MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3);
+    /*
+     * now that GPIO ports have been switched to input, we can poll for FPGA config
+     * started from the JTAG interface (CONF_DONE goes low) and finish (CONF_DONE goes high)
+     */
+    xprintf("waiting for JTAG configuration start\r\n");
+    while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));       /* wait for JTAG config load started */
 
-	xprintf("waiting for JTAG configuration to finish\r\n");
-	while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));     /* wait for JTAG config load finished */
+    xprintf("waiting for JTAG configuration to finish\r\n");
+    while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));     /* wait for JTAG config load finished */
 
-	xprintf("JTAG configuration finished.\r\n");
-	_FPGA_JTAG_LOADED = true;       /* indicate jtag loaded FPGA config to BaS */
-	_FPGA_JTAG_VALID = VALID_JTAG;  /* set magic word to indicate _FPGA_JTAG_LOADED is valid */
+    xprintf("JTAG configuration finished.\r\n");
+    _FPGA_JTAG_LOADED = 1;                              /* indicate jtag loaded FPGA config to BaS */
+    _FPGA_JTAG_VALID = VALID_JTAG;                      /* set magic word to indicate _FPGA_JTAG_LOADED is valid */
 
-	/* wait */
-	xprintf("wait a little to let things settle...\r\n");
-	for (i = 0; i < 100000000; i++);
+    /* wait */
+    xprintf("wait a little to let things settle...\r\n");
+    for (i = 0; i < 100000; i++);
 
-	xprintf("write byte data to FPGA memory\r\n");
-	for (i = 0; i < 512; i++)
-	{
-		_VRAM[i] = i;
-	}
-	hexdump((uint8_t *) _VRAM, 512);
-
-	xprintf("wait a little to let things settle...\r\n");
-	for (i = 0; i < 100000000; i++);
-
-	__asm__ __volatile__(
-		"		jmp		(%[bas_start])\n\t"
-		: /* no output */
-		: [bas_start] "a" (bas_start)
-		: /* clobber not needed */
-	);
+    __asm__ __volatile__(
+        "       jmp     (%[bas_start])\n\t"
+        : /* no output */
+        : [bas_start] "a" (bas_start)
+        : /* clobber not needed */
+    );
 }
 
 int main(int argc, char *argv[])
 {
-	printf("\033E\r\nFPGA JTAG configuration support\r\n");
-	printf("<C> 2014 M. Fröschle\r\n");
+    printf("\033E\r\nFPGA JTAG configuration support\r\n");
+    printf("<C> 2014 M. Froeschle\r\n");
 
-	printf("You may now savely load a new FPGA configuration through the JTAG interface\r\n"
-		   "and your Firebee will reboot once finished using that new configuration.\r\n");
-	if (argc == 2)
-	{
-		/*
-		 * we got an argument. This is supposed to be the address that we need to jump to after JTAG
-		 * configuration has been finished. Meant to support BaS in RAM testing
-		 */
-		char *addr_str = argv[1];
-		char *addr = NULL;
-		char *end = NULL;
+    printf("You may now savely load a new FPGA configuration through the JTAG interface\r\n"
+           "and your Firebee will reboot once finished using that new configuration.\r\n");
+    if (argc == 2)
+    {
+        /*
+         * we got an argument. This is supposed to be the address that we need to jump to after JTAG
+         * configuration has been finished. Meant to support BaS in RAM testing
+         */
+        char *addr_str = argv[1];
+        char *addr = NULL;
+        char *end = NULL;
 
-		addr = (char *) strtol(addr_str, &end, 16);
-		if (addr != NULL && addr <= (char *) 0xe0000000 && addr >= (char *) 0x10000000)
-		{
-			/*
-			 * seems to be a valid address
-			 */
-			bas_start = (long) addr;
+        addr = (char *) strtol(addr_str, &end, 16);
+        if (addr != NULL && addr <= (char *) 0xe0000000 && addr >= (char *) 0x10000000)
+        {
+            /*
+             * seems to be a valid address
+             */
+            bas_start = (long) addr;
 
-			printf("BaS start address set to %p\r\n", (void *) bas_start);
-		}
-		else
-		{
-			printf("\r\nNote: BaS start address %p not valid. Stick to %p.\r\n", addr, (void *) bas_start);
-		}
-	}
-	Supexec(wait_for_jtag);
+            printf("BaS start address set to %p\r\n", (void *) bas_start);
+        }
+        else
+        {
+            printf("\r\nNote: BaS start address %p not valid. Stick to %p.\r\n", addr, (void *) bas_start);
+        }
+    }
+    Supexec(wait_for_jtag);
 
-	return 0;       /* just to make the compiler happy, we will never return */
+    return 0;       /* just to make the compiler happy, we will never return */
 }
 

tos/vmem_test/Makefile

@@ -0,0 +1,104 @@
+CROSS=Y
+
+CROSSBINDIR_IS_Y=m68k-atari-mint-
+CROSSBINDIR_IS_N=
+
+CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS))
+
+UNAME := $(shell uname)
+ifeq ($(CROSS), Y)
+ifeq ($(UNAME),Linux)
+PREFIX=m68k-atari-mint
+HATARI=hatari
+else
+PREFIX=m68k-atari-mint
+HATARI=/usr/local/bin/hatari
+endif
+else
+PREFIX=/usr
+endif
+
+DEPEND=depend
+TOPDIR = ../..
+
+INCLUDE=-I$(TOPDIR)/../libcmini/include -nostdlib
+LIBS=-lcmini -nostdlib -lgcc
+CC=$(PREFIX)/bin/gcc
+
+CC=$(CROSSBINDIR)gcc
+STRIP=$(CROSSBINDIR)strip
+STACK=$(CROSSBINDIR)stack
+
+APP=vmem_test.prg
+TEST_APP=$(APP)
+
+CFLAGS=\
+	-O0\
+	-g\
+	-Wl,-Map,mapfile\
+	-Wl,--defsym -Wl,__MBAR=0xff000000\
+	-Wl,--defsym -Wl,__MMUBAR=0xff040000\
+	-Wl,--defsym -Wl,__FPGA_JTAG_LOADED=0xff101000\
+	-Wl,--defsym -Wl,__FPGA_JTAG_VALID=0xff101004\
+    -Wl,--defsym -Wl,__VRAM=0x60000000\
+	-Wall
+
+SRCDIR=sources
+INCDIR=include
+INCLUDE+=-I$(INCDIR)
+
+CSRCS=\
+	$(SRCDIR)/vmem_test.c \
+	$(SRCDIR)/bas_printf.c
+
+ASRCS=$(SRCDIR)/printf_helper.S
+
+COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS)))
+AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS)))
+OBJS=$(COBJS) $(AOBJS)
+
+TRGTDIRS=./m5475 ./m5475/mshort
+OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS))
+
+#
+# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output
+#
+m5475/$(APP):CFLAGS += -mcpu=5475
+m5475/mshort/$(APP): CFLAGS += -mcpu=5475 -mshort
+
+all:$(patsubst %,%/$(APP),$(TRGTDIRS))
+#
+# generate pattern rules for multilib object files.
+#
+define CC_TEMPLATE
+$(1)/objs/%.o:$(SRCDIR)/%.c
+	$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
+
+$(1)/objs/%.o:$(SRCDIR)/%.S
+	$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
+
+$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
+$(1)/$(APP): $$($(1)_OBJS)
+	$(CC) $$(CFLAGS) -o $$@ $(TOPDIR)/../libcmini/$(1)/startup.o $$($(1)_OBJS) -L$(TOPDIR)/../libcmini/$(1) $(LIBS)
+	$(STRIP) $$@
+endef
+$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
+
+$(DEPEND): $(ASRCS) $(CSRCS)
+	-rm -f $(DEPEND)
+	for d in $(TRGTDIRS);\
+		do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \
+    done
+
+
+clean:
+	@rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS))
+	@rm -f $(DEPEND) mapfile
+
+.PHONY: printvars
+printvars:
+	@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
+
+ifneq (clean,$(MAKECMDGOALS))
+-include $(DEPEND)
+endif

tos/vmem_test/include/MCF5475.h

@@ -0,0 +1,67 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_H__
+#define __MCF5475_H__
+
+#include <stdint.h>
+/***
+ * MCF5475 Derivative Memory map definitions from linker command files:
+ * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
+ * linker symbols must be defined in the linker command file.
+ */
+
+typedef uint32_t __attribute__((__may_alias__)) uint32_t_a;	/* a type to avoid gcc's complaints about pointer aliasing */
+
+extern uint8_t _MBAR[];
+extern uint8_t _MMUBAR[];
+extern uint8_t _RAMBAR0[];
+extern uint8_t _RAMBAR0_SIZE[];
+extern uint8_t _RAMBAR1[];
+extern uint8_t _RAMBAR1_SIZE[];
+
+#define MBAR_ADDRESS    (uint32_t)_MBAR
+#define MMUBAR_ADDRESS  (uint32_t)_MMUBAR
+#define RAMBAR0_ADDRESS (uint32_t)_RAMBAR0
+#define RAMBAR0_SIZE    (uint32_t)_RAMBAR0_SIZE
+#define RAMBAR1_ADDRESS (uint32_t)_RAMBAR1
+#define RAMBAR1_SIZE    (uint32_t)_RAMBAR1_SIZE
+
+
+#include "MCF5475_SIU.h"
+#include "MCF5475_MMU.h"
+#include "MCF5475_SDRAMC.h"
+#include "MCF5475_XLB.h"
+#include "MCF5475_CLOCK.h"
+#include "MCF5475_FBCS.h"
+#include "MCF5475_INTC.h"
+#include "MCF5475_GPT.h"
+#include "MCF5475_SLT.h"
+#include "MCF5475_GPIO.h"
+#include "MCF5475_PAD.h"
+#include "MCF5475_PCI.h"
+#include "MCF5475_PCIARB.h"
+#include "MCF5475_EPORT.h"
+#include "MCF5475_CTM.h"
+#include "MCF5475_DMA.h"
+#include "MCF5475_PSC.h"
+#include "MCF5475_DSPI.h"
+#include "MCF5475_I2C.h"
+#include "MCF5475_FEC.h"
+#include "MCF5475_USB.h"
+#include "MCF5475_SRAM.h"
+#include "MCF5475_SEC.h"
+
+#endif /* __MCF5475_H__ */

tos/vmem_test/include/MCF5475_CLOCK.h

@@ -0,0 +1,47 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_CLOCK_H__
+#define __MCF5475_CLOCK_H__
+
+
+/*********************************************************************
+*
+* Clock Module (CLOCK)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CLOCK_SPCR                       (*(volatile uint32_t*)(&_MBAR[0x300]))
+
+
+/* Bit definitions and macros for MCF_CLOCK_SPCR */
+#define MCF_CLOCK_SPCR_MEMEN                 (0x1)
+#define MCF_CLOCK_SPCR_PCIEN                 (0x2)
+#define MCF_CLOCK_SPCR_FBEN                  (0x4)
+#define MCF_CLOCK_SPCR_CAN0EN                (0x8)
+#define MCF_CLOCK_SPCR_DMAEN                 (0x10)
+#define MCF_CLOCK_SPCR_FEC0EN                (0x20)
+#define MCF_CLOCK_SPCR_FEC1EN                (0x40)
+#define MCF_CLOCK_SPCR_USBEN                 (0x80)
+#define MCF_CLOCK_SPCR_PSCEN                 (0x200)
+#define MCF_CLOCK_SPCR_CAN1EN                (0x800)
+#define MCF_CLOCK_SPCR_CRYENA                (0x1000)
+#define MCF_CLOCK_SPCR_CRYENB                (0x2000)
+#define MCF_CLOCK_SPCR_COREN                 (0x4000)
+#define MCF_CLOCK_SPCR_PLLK                  (0x80000000)
+
+
+#endif /* __MCF5475_CLOCK_H__ */

tos/vmem_test/include/MCF5475_CTM.h

@@ -0,0 +1,76 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_CTM_H__
+#define __MCF5475_CTM_H__
+
+
+/*********************************************************************
+*
+* Comm Timer Module (CTM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CTM_CTCR0                        (*(volatile uint32_t*)(&_MBAR[0x7F00]))
+#define MCF_CTM_CTCR1                        (*(volatile uint32_t*)(&_MBAR[0x7F04]))
+#define MCF_CTM_CTCR2                        (*(volatile uint32_t*)(&_MBAR[0x7F08]))
+#define MCF_CTM_CTCR3                        (*(volatile uint32_t*)(&_MBAR[0x7F0C]))
+#define MCF_CTM_CTCR4                        (*(volatile uint32_t*)(&_MBAR[0x7F10]))
+#define MCF_CTM_CTCR5                        (*(volatile uint32_t*)(&_MBAR[0x7F14]))
+#define MCF_CTM_CTCR6                        (*(volatile uint32_t*)(&_MBAR[0x7F18]))
+#define MCF_CTM_CTCR7                        (*(volatile uint32_t*)(&_MBAR[0x7F1C]))
+#define MCF_CTM_CTCRF(x)                     (*(volatile uint32_t*)(&_MBAR[0x7F00 + ((x)*0x4)]))
+#define MCF_CTM_CTCRV(x)                     (*(volatile uint32_t*)(&_MBAR[0x7F10 + ((x-4)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_CTM_CTCRF */
+#define MCF_CTM_CTCRF_CRV(x)                 (((x)&0xFFFF)<<0)
+#define MCF_CTM_CTCRF_S(x)                   (((x)&0xF)<<0x10)
+#define MCF_CTM_CTCRF_S_CLK_1                (0)
+#define MCF_CTM_CTCRF_S_CLK_2                (0x10000)
+#define MCF_CTM_CTCRF_S_CLK_4                (0x20000)
+#define MCF_CTM_CTCRF_S_CLK_8                (0x30000)
+#define MCF_CTM_CTCRF_S_CLK_16               (0x40000)
+#define MCF_CTM_CTCRF_S_CLK_32               (0x50000)
+#define MCF_CTM_CTCRF_S_CLK_64               (0x60000)
+#define MCF_CTM_CTCRF_S_CLK_128              (0x70000)
+#define MCF_CTM_CTCRF_S_CLK_256              (0x80000)
+#define MCF_CTM_CTCRF_S_CLK_EXT              (0x90000)
+#define MCF_CTM_CTCRF_PCT(x)                 (((x)&0x7)<<0x14)
+#define MCF_CTM_CTCRF_PCT_100                (0)
+#define MCF_CTM_CTCRF_PCT_50                 (0x100000)
+#define MCF_CTM_CTCRF_PCT_25                 (0x200000)
+#define MCF_CTM_CTCRF_PCT_12p5               (0x300000)
+#define MCF_CTM_CTCRF_PCT_6p25               (0x400000)
+#define MCF_CTM_CTCRF_PCT_OFF                (0x500000)
+#define MCF_CTM_CTCRF_M                      (0x800000)
+#define MCF_CTM_CTCRF_IM                     (0x1000000)
+#define MCF_CTM_CTCRF_I                      (0x80000000)
+
+/* Bit definitions and macros for MCF_CTM_CTCRV */
+#define MCF_CTM_CTCRV_CRV(x)                 (((x)&0xFFFFFF)<<0)
+#define MCF_CTM_CTCRV_PCT(x)                 (((x)&0x7)<<0x18)
+#define MCF_CTM_CTCRV_PCT_100                (0)
+#define MCF_CTM_CTCRV_PCT_50                 (0x1000000)
+#define MCF_CTM_CTCRV_PCT_25                 (0x2000000)
+#define MCF_CTM_CTCRV_PCT_12p5               (0x3000000)
+#define MCF_CTM_CTCRV_PCT_6p25               (0x4000000)
+#define MCF_CTM_CTCRV_PCT_OFF                (0x5000000)
+#define MCF_CTM_CTCRV_M                      (0x8000000)
+#define MCF_CTM_CTCRV_S                      (0x10000000)
+
+
+#endif /* __MCF5475_CTM_H__ */

tos/vmem_test/include/MCF5475_DMA.h

@@ -0,0 +1,234 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_DMA_H__
+#define __MCF5475_DMA_H__
+
+
+/*********************************************************************
+*
+* Multichannel DMA (DMA)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DMA_TASKBAR                      (*(volatile uint32_t*)(&_MBAR[0x8000]))
+#define MCF_DMA_CP                           (*(volatile uint32_t*)(&_MBAR[0x8004]))
+#define MCF_DMA_EP                           (*(volatile uint32_t*)(&_MBAR[0x8008]))
+#define MCF_DMA_VP                           (*(volatile uint32_t*)(&_MBAR[0x800C]))
+#define MCF_DMA_PTD                          (*(volatile uint32_t*)(&_MBAR[0x8010]))
+#define MCF_DMA_DIPR                         (*(volatile uint32_t*)(&_MBAR[0x8014]))
+#define MCF_DMA_DIMR                         (*(volatile uint32_t*)(&_MBAR[0x8018]))
+#define MCF_DMA_TCR0                         (*(volatile uint16_t*)(&_MBAR[0x801C]))
+#define MCF_DMA_TCR1                         (*(volatile uint16_t*)(&_MBAR[0x801E]))
+#define MCF_DMA_TCR2                         (*(volatile uint16_t*)(&_MBAR[0x8020]))
+#define MCF_DMA_TCR3                         (*(volatile uint16_t*)(&_MBAR[0x8022]))
+#define MCF_DMA_TCR4                         (*(volatile uint16_t*)(&_MBAR[0x8024]))
+#define MCF_DMA_TCR5                         (*(volatile uint16_t*)(&_MBAR[0x8026]))
+#define MCF_DMA_TCR6                         (*(volatile uint16_t*)(&_MBAR[0x8028]))
+#define MCF_DMA_TCR7                         (*(volatile uint16_t*)(&_MBAR[0x802A]))
+#define MCF_DMA_TCR8                         (*(volatile uint16_t*)(&_MBAR[0x802C]))
+#define MCF_DMA_TCR9                         (*(volatile uint16_t*)(&_MBAR[0x802E]))
+#define MCF_DMA_TCR10                        (*(volatile uint16_t*)(&_MBAR[0x8030]))
+#define MCF_DMA_TCR11                        (*(volatile uint16_t*)(&_MBAR[0x8032]))
+#define MCF_DMA_TCR12                        (*(volatile uint16_t*)(&_MBAR[0x8034]))
+#define MCF_DMA_TCR13                        (*(volatile uint16_t*)(&_MBAR[0x8036]))
+#define MCF_DMA_TCR14                        (*(volatile uint16_t*)(&_MBAR[0x8038]))
+#define MCF_DMA_TCR15                        (*(volatile uint16_t*)(&_MBAR[0x803A]))
+#define MCF_DMA_PRIOR0                       (*(volatile uint8_t *)(&_MBAR[0x803C]))
+#define MCF_DMA_PRIOR1                       (*(volatile uint8_t *)(&_MBAR[0x803D]))
+#define MCF_DMA_PRIOR2                       (*(volatile uint8_t *)(&_MBAR[0x803E]))
+#define MCF_DMA_PRIOR3                       (*(volatile uint8_t *)(&_MBAR[0x803F]))
+#define MCF_DMA_PRIOR4                       (*(volatile uint8_t *)(&_MBAR[0x8040]))
+#define MCF_DMA_PRIOR5                       (*(volatile uint8_t *)(&_MBAR[0x8041]))
+#define MCF_DMA_PRIOR6                       (*(volatile uint8_t *)(&_MBAR[0x8042]))
+#define MCF_DMA_PRIOR7                       (*(volatile uint8_t *)(&_MBAR[0x8043]))
+#define MCF_DMA_PRIOR8                       (*(volatile uint8_t *)(&_MBAR[0x8044]))
+#define MCF_DMA_PRIOR9                       (*(volatile uint8_t *)(&_MBAR[0x8045]))
+#define MCF_DMA_PRIOR10                      (*(volatile uint8_t *)(&_MBAR[0x8046]))
+#define MCF_DMA_PRIOR11                      (*(volatile uint8_t *)(&_MBAR[0x8047]))
+#define MCF_DMA_PRIOR12                      (*(volatile uint8_t *)(&_MBAR[0x8048]))
+#define MCF_DMA_PRIOR13                      (*(volatile uint8_t *)(&_MBAR[0x8049]))
+#define MCF_DMA_PRIOR14                      (*(volatile uint8_t *)(&_MBAR[0x804A]))
+#define MCF_DMA_PRIOR15                      (*(volatile uint8_t *)(&_MBAR[0x804B]))
+#define MCF_DMA_PRIOR16                      (*(volatile uint8_t *)(&_MBAR[0x804C]))
+#define MCF_DMA_PRIOR17                      (*(volatile uint8_t *)(&_MBAR[0x804D]))
+#define MCF_DMA_PRIOR18                      (*(volatile uint8_t *)(&_MBAR[0x804E]))
+#define MCF_DMA_PRIOR19                      (*(volatile uint8_t *)(&_MBAR[0x804F]))
+#define MCF_DMA_PRIOR20                      (*(volatile uint8_t *)(&_MBAR[0x8050]))
+#define MCF_DMA_PRIOR21                      (*(volatile uint8_t *)(&_MBAR[0x8051]))
+#define MCF_DMA_PRIOR22                      (*(volatile uint8_t *)(&_MBAR[0x8052]))
+#define MCF_DMA_PRIOR23                      (*(volatile uint8_t *)(&_MBAR[0x8053]))
+#define MCF_DMA_PRIOR24                      (*(volatile uint8_t *)(&_MBAR[0x8054]))
+#define MCF_DMA_PRIOR25                      (*(volatile uint8_t *)(&_MBAR[0x8055]))
+#define MCF_DMA_PRIOR26                      (*(volatile uint8_t *)(&_MBAR[0x8056]))
+#define MCF_DMA_PRIOR27                      (*(volatile uint8_t *)(&_MBAR[0x8057]))
+#define MCF_DMA_PRIOR28                      (*(volatile uint8_t *)(&_MBAR[0x8058]))
+#define MCF_DMA_PRIOR29                      (*(volatile uint8_t *)(&_MBAR[0x8059]))
+#define MCF_DMA_PRIOR30                      (*(volatile uint8_t *)(&_MBAR[0x805A]))
+#define MCF_DMA_PRIOR31                      (*(volatile uint8_t *)(&_MBAR[0x805B]))
+#define MCF_DMA_IMCR                         (*(volatile uint32_t*)(&_MBAR[0x805C]))
+#define MCF_DMA_TSKSZ0                       (*(volatile uint32_t*)(&_MBAR[0x8060]))
+#define MCF_DMA_TSKSZ1                       (*(volatile uint32_t*)(&_MBAR[0x8064]))
+#define MCF_DMA_DBGCOMP0                     (*(volatile uint32_t*)(&_MBAR[0x8070]))
+#define MCF_DMA_DBGCOMP2                     (*(volatile uint32_t*)(&_MBAR[0x8074]))
+#define MCF_DMA_DBGCTL                       (*(volatile uint32_t*)(&_MBAR[0x8078]))
+#define MCF_DMA_TCR(x)                       (*(volatile uint16_t*)(&_MBAR[0x801C + ((x)*0x2)]))
+#define MCF_DMA_PRIOR(x)                     (*(volatile uint8_t *)(&_MBAR[0x803C + ((x)*0x1)]))
+
+
+/* Bit definitions and macros for MCF_DMA_TASKBAR */
+#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_CP */
+#define MCF_DMA_CP_DESCRIPTOR_POINTER(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_EP */
+#define MCF_DMA_EP_DESCRIPTOR_POINTER(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_VP */
+#define MCF_DMA_VP_VARIABLE_POINTER(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_PTD */
+#define MCF_DMA_PTD_PCTL0                    (0x1)
+#define MCF_DMA_PTD_PCTL1                    (0x2)
+#define MCF_DMA_PTD_PCTL13                   (0x2000)
+#define MCF_DMA_PTD_PCTL14                   (0x4000)
+#define MCF_DMA_PTD_PCTL15                   (0x8000)
+
+/* Bit definitions and macros for MCF_DMA_DIPR */
+#define MCF_DMA_DIPR_TASK(x)                 (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DIMR */
+#define MCF_DMA_DIMR_TASK(x)                 (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_TCR */
+#define MCF_DMA_TCR_ASTSKNUM(x)              (((x)&0xF)<<0)
+#define MCF_DMA_TCR_HLDINITNUM               (0x20)
+#define MCF_DMA_TCR_HIPRITSKEN               (0x40)
+#define MCF_DMA_TCR_ASTRT                    (0x80)
+#define MCF_DMA_TCR_INITNUM(x)               (((x)&0x1F)<<0x8)
+#define MCF_DMA_TCR_ALWINIT                  (0x2000)
+#define MCF_DMA_TCR_V                        (0x4000)
+#define MCF_DMA_TCR_EN                       (0x8000)
+
+/* Bit definitions and macros for MCF_DMA_PRIOR */
+#define MCF_DMA_PRIOR_PRI(x)                 (((x)&0x7)<<0)
+#define MCF_DMA_PRIOR_HLD                    (0x80)
+
+/* Bit definitions and macros for MCF_DMA_IMCR */
+#define MCF_DMA_IMCR_IMC16(x)	(((x)&0x3)<<0)
+#define MCF_DMA_IMCR_IMC17(x)	(((x)&0x3)<<0x2)
+#define MCF_DMA_IMCR_IMC18(x)	(((x)&0x3)<<0x4)
+#define MCF_DMA_IMCR_IMC19(x)	(((x)&0x3)<<0x6)
+#define MCF_DMA_IMCR_IMC20(x)	(((x)&0x3)<<0x8)
+#define MCF_DMA_IMCR_IMC21(x)	(((x)&0x3)<<0xA)
+#define MCF_DMA_IMCR_IMC22(x)	(((x)&0x3)<<0xC)
+#define MCF_DMA_IMCR_IMC23(x)	(((x)&0x3)<<0xE)
+#define MCF_DMA_IMCR_IMC24(x)	(((x)&0x3)<<0x10)
+#define MCF_DMA_IMCR_IMC25(x)	(((x)&0x3)<<0x12)
+#define MCF_DMA_IMCR_IMC26(x)	(((x)&0x3)<<0x14)
+#define MCF_DMA_IMCR_IMC27(x)	(((x)&0x3)<<0x16)
+#define MCF_DMA_IMCR_IMC28(x)	(((x)&0x3)<<0x18)
+#define MCF_DMA_IMCR_IMC29(x)	(((x)&0x3)<<0x1A)
+#define MCF_DMA_IMCR_IMC30(x)	(((x)&0x3)<<0x1C)
+#define MCF_DMA_IMCR_IMC31(x)	(((x)&0x3)<<0x1E)
+
+
+#define MCF_DMA_IMCR_IMC16_FEC0RX    (0x00000000)
+#define MCF_DMA_IMCR_IMC17_FEC0TX    (0x00000000)
+#define MCF_DMA_IMCR_IMC18_FEC0RX    (0x00000020)
+#define MCF_DMA_IMCR_IMC19_FEC0TX    (0x00000080)
+#define MCF_DMA_IMCR_IMC20_FEC1RX    (0x00000100)
+#define MCF_DMA_IMCR_IMC21_DREQ1     (0x00000000)
+#define MCF_DMA_IMCR_IMC21_FEC1TX    (0x00000400)
+#define MCF_DMA_IMCR_IMC22_FEC0RX    (0x00001000)
+#define MCF_DMA_IMCR_IMC23_FEC0TX    (0x00004000)
+#define MCF_DMA_IMCR_IMC24_CTM0      (0x00010000)
+#define MCF_DMA_IMCR_IMC24_FEC1RX    (0x00020000)
+#define MCF_DMA_IMCR_IMC25_CTM1      (0x00040000)
+#define MCF_DMA_IMCR_IMC25_FEC1TX    (0x00080000)
+#define MCF_DMA_IMCR_IMC26_USBEP4    (0x00000000)
+#define MCF_DMA_IMCR_IMC26_CTM2      (0x00200000)
+#define MCF_DMA_IMCR_IMC27_USBEP5    (0x00000000)
+#define MCF_DMA_IMCR_IMC27_CTM3      (0x00800000)
+#define MCF_DMA_IMCR_IMC28_USBEP6    (0x00000000)
+#define MCF_DMA_IMCR_IMC28_CTM4      (0x01000000)
+#define MCF_DMA_IMCR_IMC28_DREQ1     (0x02000000)
+#define MCF_DMA_IMCR_IMC28_PSC2RX    (0x03000000)
+#define MCF_DMA_IMCR_IMC29_DREQ1     (0x04000000)
+#define MCF_DMA_IMCR_IMC29_CTM5      (0x08000000)
+#define MCF_DMA_IMCR_IMC29_PSC2TX    (0x0C000000)
+#define MCF_DMA_IMCR_IMC30_FEC1RX    (0x00000000)
+#define MCF_DMA_IMCR_IMC30_CTM6      (0x10000000)
+#define MCF_DMA_IMCR_IMC30_PSC3RX    (0x30000000)
+#define MCF_DMA_IMCR_IMC31_FEC1TX    (0x00000000)
+#define MCF_DMA_IMCR_IMC31_CTM7      (0x80000000)
+#define MCF_DMA_IMCR_IMC31_PSC3TX    (0xC0000000)
+
+/* Bit definitions and macros for MCF_DMA_TSKSZ0 */
+#define MCF_DMA_TSKSZ0_DSTSZ7(x)             (((x)&0x3)<<0)
+#define MCF_DMA_TSKSZ0_SRCSZ7(x)             (((x)&0x3)<<0x2)
+#define MCF_DMA_TSKSZ0_DSTSZ6(x)             (((x)&0x3)<<0x4)
+#define MCF_DMA_TSKSZ0_SRCSZ6(x)             (((x)&0x3)<<0x6)
+#define MCF_DMA_TSKSZ0_DSTSZ5(x)             (((x)&0x3)<<0x8)
+#define MCF_DMA_TSKSZ0_SRCSZ5(x)             (((x)&0x3)<<0xA)
+#define MCF_DMA_TSKSZ0_DSTSZ4(x)             (((x)&0x3)<<0xC)
+#define MCF_DMA_TSKSZ0_SRCSZ4(x)             (((x)&0x3)<<0xE)
+#define MCF_DMA_TSKSZ0_DSTSZ3(x)             (((x)&0x3)<<0x10)
+#define MCF_DMA_TSKSZ0_SRCSZ3(x)             (((x)&0x3)<<0x12)
+#define MCF_DMA_TSKSZ0_DSTSZ2(x)             (((x)&0x3)<<0x14)
+#define MCF_DMA_TSKSZ0_SRCSZ2(x)             (((x)&0x3)<<0x16)
+#define MCF_DMA_TSKSZ0_DSTSZ1(x)             (((x)&0x3)<<0x18)
+#define MCF_DMA_TSKSZ0_SRCSZ1(x)             (((x)&0x3)<<0x1A)
+#define MCF_DMA_TSKSZ0_DSTSZ0(x)             (((x)&0x3)<<0x1C)
+#define MCF_DMA_TSKSZ0_SRCSZ0(x)             (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_DMA_TSKSZ1 */
+#define MCF_DMA_TSKSZ1_DSTSZ15(x)            (((x)&0x3)<<0)
+#define MCF_DMA_TSKSZ1_SRCSZ15(x)            (((x)&0x3)<<0x2)
+#define MCF_DMA_TSKSZ1_DSTSZ14(x)            (((x)&0x3)<<0x4)
+#define MCF_DMA_TSKSZ1_SRCSZ14(x)            (((x)&0x3)<<0x6)
+#define MCF_DMA_TSKSZ1_DSTSZ13(x)            (((x)&0x3)<<0x8)
+#define MCF_DMA_TSKSZ1_SRCSZ13(x)            (((x)&0x3)<<0xA)
+#define MCF_DMA_TSKSZ1_DSTSZ12(x)            (((x)&0x3)<<0xC)
+#define MCF_DMA_TSKSZ1_SRCSZ12(x)            (((x)&0x3)<<0xE)
+#define MCF_DMA_TSKSZ1_DSTSZ11(x)            (((x)&0x3)<<0x10)
+#define MCF_DMA_TSKSZ1_SRCSZ11(x)            (((x)&0x3)<<0x12)
+#define MCF_DMA_TSKSZ1_DSTSZ10(x)            (((x)&0x3)<<0x14)
+#define MCF_DMA_TSKSZ1_SRCSZ10(x)            (((x)&0x3)<<0x16)
+#define MCF_DMA_TSKSZ1_DSTSZ9(x)             (((x)&0x3)<<0x18)
+#define MCF_DMA_TSKSZ1_SRCSZ9(x)             (((x)&0x3)<<0x1A)
+#define MCF_DMA_TSKSZ1_DSTSZ8(x)             (((x)&0x3)<<0x1C)
+#define MCF_DMA_TSKSZ1_SRCSZ8(x)             (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */
+#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */
+#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DBGCTL */
+#define MCF_DMA_DBGCTL_I                     (0x2)
+#define MCF_DMA_DBGCTL_E                     (0x4)
+#define MCF_DMA_DBGCTL_AND_OR                (0x80)
+#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x)  (((x)&0x7)<<0x8)
+#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x)  (((x)&0x7)<<0xB)
+#define MCF_DMA_DBGCTL_B                     (0x4000)
+#define MCF_DMA_DBGCTL_AA                    (0x8000)
+#define MCF_DMA_DBGCTL_BLOCK_TASKS(x)        (((x)&0xFFFF)<<0x10)
+
+
+#endif /* __MCF5475_DMA_H__ */

tos/vmem_test/include/MCF5475_DSPI.h

@@ -0,0 +1,150 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_DSPI_H__
+#define __MCF5475_DSPI_H__
+
+
+/*********************************************************************
+*
+* DMA Serial Peripheral Interface (DSPI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DSPI_DMCR                        (*(volatile uint32_t*)(&_MBAR[0x8A00]))
+#define MCF_DSPI_DTCR                        (*(volatile uint32_t*)(&_MBAR[0x8A08]))
+#define MCF_DSPI_DCTAR0                      (*(volatile uint32_t*)(&_MBAR[0x8A0C]))
+#define MCF_DSPI_DCTAR1                      (*(volatile uint32_t*)(&_MBAR[0x8A10]))
+#define MCF_DSPI_DCTAR2                      (*(volatile uint32_t*)(&_MBAR[0x8A14]))
+#define MCF_DSPI_DCTAR3                      (*(volatile uint32_t*)(&_MBAR[0x8A18]))
+#define MCF_DSPI_DCTAR4                      (*(volatile uint32_t*)(&_MBAR[0x8A1C]))
+#define MCF_DSPI_DCTAR5                      (*(volatile uint32_t*)(&_MBAR[0x8A20]))
+#define MCF_DSPI_DCTAR6                      (*(volatile uint32_t*)(&_MBAR[0x8A24]))
+#define MCF_DSPI_DCTAR7                      (*(volatile uint32_t*)(&_MBAR[0x8A28]))
+#define MCF_DSPI_DSR                         (*(volatile uint32_t*)(&_MBAR[0x8A2C]))
+#define MCF_DSPI_DIRSR                       (*(volatile uint32_t*)(&_MBAR[0x8A30]))
+#define MCF_DSPI_DTFR                        (*(volatile uint32_t*)(&_MBAR[0x8A34]))
+#define MCF_DSPI_DRFR                        (*(volatile uint32_t*)(&_MBAR[0x8A38]))
+#define MCF_DSPI_DTFDR0                      (*(volatile uint32_t*)(&_MBAR[0x8A3C]))
+#define MCF_DSPI_DTFDR1                      (*(volatile uint32_t*)(&_MBAR[0x8A40]))
+#define MCF_DSPI_DTFDR2                      (*(volatile uint32_t*)(&_MBAR[0x8A44]))
+#define MCF_DSPI_DTFDR3                      (*(volatile uint32_t*)(&_MBAR[0x8A48]))
+#define MCF_DSPI_DRFDR0                      (*(volatile uint32_t*)(&_MBAR[0x8A7C]))
+#define MCF_DSPI_DRFDR1                      (*(volatile uint32_t*)(&_MBAR[0x8A80]))
+#define MCF_DSPI_DRFDR2                      (*(volatile uint32_t*)(&_MBAR[0x8A84]))
+#define MCF_DSPI_DRFDR3                      (*(volatile uint32_t*)(&_MBAR[0x8A88]))
+#define MCF_DSPI_DCTAR(x)                    (*(volatile uint32_t*)(&_MBAR[0x8A0C + ((x)*0x4)]))
+#define MCF_DSPI_DTFDR(x)                    (*(volatile uint32_t*)(&_MBAR[0x8A3C + ((x)*0x4)]))
+#define MCF_DSPI_DRFDR(x)                    (*(volatile uint32_t*)(&_MBAR[0x8A7C + ((x)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_DSPI_DMCR */
+#define MCF_DSPI_DMCR_HALT                   (0x1)
+#define MCF_DSPI_DMCR_SMPL_PT(x)             (((x)&0x3)<<0x8)
+#define MCF_DSPI_DMCR_SMPL_PT_0CLK           (0)
+#define MCF_DSPI_DMCR_SMPL_PT_1CLK           (0x100)
+#define MCF_DSPI_DMCR_SMPL_PT_2CLK           (0x200)
+#define MCF_DSPI_DMCR_CRXF                   (0x400)
+#define MCF_DSPI_DMCR_CTXF                   (0x800)
+#define MCF_DSPI_DMCR_DRXF                   (0x1000)
+#define MCF_DSPI_DMCR_DTXF                   (0x2000)
+#define MCF_DSPI_DMCR_CSIS0                  (0x10000)
+#define MCF_DSPI_DMCR_CSIS2                  (0x40000)
+#define MCF_DSPI_DMCR_CSIS3                  (0x80000)
+#define MCF_DSPI_DMCR_CSIS5                  (0x200000)
+#define MCF_DSPI_DMCR_ROOE                   (0x1000000)
+#define MCF_DSPI_DMCR_PCSSE                  (0x2000000)
+#define MCF_DSPI_DMCR_MTFE                   (0x4000000)
+#define MCF_DSPI_DMCR_FRZ                    (0x8000000)
+#define MCF_DSPI_DMCR_DCONF(x)               (((x)&0x3)<<0x1C)
+#define MCF_DSPI_DMCR_CSCK                   (0x40000000)
+#define MCF_DSPI_DMCR_MSTR                   (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DTCR */
+#define MCF_DSPI_DTCR_SPI_TCNT(x)            (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_DSPI_DCTAR */
+#define MCF_DSPI_DCTAR_BR(x)                 (((x)&0xF)<<0)
+#define MCF_DSPI_DCTAR_DT(x)                 (((x)&0xF)<<0x4)
+#define MCF_DSPI_DCTAR_ASC(x)                (((x)&0xF)<<0x8)
+#define MCF_DSPI_DCTAR_CSSCK(x)              (((x)&0xF)<<0xC)
+#define MCF_DSPI_DCTAR_PBR(x)                (((x)&0x3)<<0x10)
+#define MCF_DSPI_DCTAR_PBR_1CLK              (0)
+#define MCF_DSPI_DCTAR_PBR_3CLK              (0x10000)
+#define MCF_DSPI_DCTAR_PBR_5CLK              (0x20000)
+#define MCF_DSPI_DCTAR_PBR_7CLK              (0x30000)
+#define MCF_DSPI_DCTAR_PDT(x)                (((x)&0x3)<<0x12)
+#define MCF_DSPI_DCTAR_PDT_1CLK              (0)
+#define MCF_DSPI_DCTAR_PDT_3CLK              (0x40000)
+#define MCF_DSPI_DCTAR_PDT_5CLK              (0x80000)
+#define MCF_DSPI_DCTAR_PDT_7CLK              (0xC0000)
+#define MCF_DSPI_DCTAR_PASC(x)               (((x)&0x3)<<0x14)
+#define MCF_DSPI_DCTAR_PASC_1CLK             (0)
+#define MCF_DSPI_DCTAR_PASC_3CLK             (0x100000)
+#define MCF_DSPI_DCTAR_PASC_5CLK             (0x200000)
+#define MCF_DSPI_DCTAR_PASC_7CLK             (0x300000)
+#define MCF_DSPI_DCTAR_PCSSCK(x)             (((x)&0x3)<<0x16)
+#define MCF_DSPI_DCTAR_LSBFE                 (0x1000000)
+#define MCF_DSPI_DCTAR_CPHA                  (0x2000000)
+#define MCF_DSPI_DCTAR_CPOL                  (0x4000000)
+#define MCF_DSPI_DCTAR_TRSZ(x)               (((x)&0xF)<<0x1B)
+
+/* Bit definitions and macros for MCF_DSPI_DSR */
+#define MCF_DSPI_DSR_RXPTR(x)                (((x)&0xF)<<0)
+#define MCF_DSPI_DSR_RXCTR(x)                (((x)&0xF)<<0x4)
+#define MCF_DSPI_DSR_TXPTR(x)                (((x)&0xF)<<0x8)
+#define MCF_DSPI_DSR_TXCTR(x)                (((x)&0xF)<<0xC)
+#define MCF_DSPI_DSR_RFDF                    (0x20000)
+#define MCF_DSPI_DSR_RFOF                    (0x80000)
+#define MCF_DSPI_DSR_TFFF                    (0x2000000)
+#define MCF_DSPI_DSR_TFUF                    (0x8000000)
+#define MCF_DSPI_DSR_EOQF                    (0x10000000)
+#define MCF_DSPI_DSR_TXRXS                   (0x40000000)
+#define MCF_DSPI_DSR_TCF                     (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DIRSR */
+#define MCF_DSPI_DIRSR_RFDFS                 (0x10000)
+#define MCF_DSPI_DIRSR_RFDFE                 (0x20000)
+#define MCF_DSPI_DIRSR_RFOFE                 (0x80000)
+#define MCF_DSPI_DIRSR_TFFFS                 (0x1000000)
+#define MCF_DSPI_DIRSR_TFFFE                 (0x2000000)
+#define MCF_DSPI_DIRSR_TFUFE                 (0x8000000)
+#define MCF_DSPI_DIRSR_EOQFE                 (0x10000000)
+#define MCF_DSPI_DIRSR_TCFE                  (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DTFR */
+#define MCF_DSPI_DTFR_TXDATA(x)              (((x)&0xFFFF)<<0)
+#define MCF_DSPI_DTFR_CS0                    (0x10000)
+#define MCF_DSPI_DTFR_CS2                    (0x40000)
+#define MCF_DSPI_DTFR_CS3                    (0x80000)
+#define MCF_DSPI_DTFR_CS5                    (0x200000)
+#define MCF_DSPI_DTFR_CTCNT                  (0x4000000)
+#define MCF_DSPI_DTFR_EOQ                    (0x8000000)
+#define MCF_DSPI_DTFR_CTAS(x)                (((x)&0x7)<<0x1C)
+#define MCF_DSPI_DTFR_CONT                   (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DRFR */
+#define MCF_DSPI_DRFR_RXDATA(x)              (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DSPI_DTFDR */
+#define MCF_DSPI_DTFDR_TXDATA(x)             (((x)&0xFFFF)<<0)
+#define MCF_DSPI_DTFDR_TXCMD(x)              (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_DSPI_DRFDR */
+#define MCF_DSPI_DRFDR_RXDATA(x)             (((x)&0xFFFF)<<0)
+
+
+#endif /* __MCF5475_DSPI_H__ */

tos/vmem_test/include/MCF5475_EPORT.h

@@ -0,0 +1,123 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_EPORT_H__
+#define __MCF5475_EPORT_H__
+
+
+/*********************************************************************
+*
+* Edge Port Module (EPORT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_EPORT_EPPAR                      (*(volatile uint16_t*)(&_MBAR[0xF00]))
+#define MCF_EPORT_EPDDR                      (*(volatile uint8_t *)(&_MBAR[0xF04]))
+#define MCF_EPORT_EPIER                      (*(volatile uint8_t *)(&_MBAR[0xF05]))
+#define MCF_EPORT_EPDR                       (*(volatile uint8_t *)(&_MBAR[0xF08]))
+#define MCF_EPORT_EPPDR                      (*(volatile uint8_t *)(&_MBAR[0xF09]))
+#define MCF_EPORT_EPFR                       (*(volatile uint8_t *)(&_MBAR[0xF0C]))
+
+
+
+/* Bit definitions and macros for MCF_EPORT_EPPAR */
+#define MCF_EPORT_EPPAR_EPPA1(x)             (((x)&0x3)<<0x2)
+#define MCF_EPORT_EPPAR_EPPA1_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA1_RISING         (0x4)
+#define MCF_EPORT_EPPAR_EPPA1_FALLING        (0x8)
+#define MCF_EPORT_EPPAR_EPPA1_BOTH           (0xC)
+#define MCF_EPORT_EPPAR_EPPA2(x)             (((x)&0x3)<<0x4)
+#define MCF_EPORT_EPPAR_EPPA2_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA2_RISING         (0x10)
+#define MCF_EPORT_EPPAR_EPPA2_FALLING        (0x20)
+#define MCF_EPORT_EPPAR_EPPA2_BOTH           (0x30)
+#define MCF_EPORT_EPPAR_EPPA3(x)             (((x)&0x3)<<0x6)
+#define MCF_EPORT_EPPAR_EPPA3_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA3_RISING         (0x40)
+#define MCF_EPORT_EPPAR_EPPA3_FALLING        (0x80)
+#define MCF_EPORT_EPPAR_EPPA3_BOTH           (0xC0)
+#define MCF_EPORT_EPPAR_EPPA4(x)             (((x)&0x3)<<0x8)
+#define MCF_EPORT_EPPAR_EPPA4_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA4_RISING         (0x100)
+#define MCF_EPORT_EPPAR_EPPA4_FALLING        (0x200)
+#define MCF_EPORT_EPPAR_EPPA4_BOTH           (0x300)
+#define MCF_EPORT_EPPAR_EPPA5(x)             (((x)&0x3)<<0xA)
+#define MCF_EPORT_EPPAR_EPPA5_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA5_RISING         (0x400)
+#define MCF_EPORT_EPPAR_EPPA5_FALLING        (0x800)
+#define MCF_EPORT_EPPAR_EPPA5_BOTH           (0xC00)
+#define MCF_EPORT_EPPAR_EPPA6(x)             (((x)&0x3)<<0xC)
+#define MCF_EPORT_EPPAR_EPPA6_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA6_RISING         (0x1000)
+#define MCF_EPORT_EPPAR_EPPA6_FALLING        (0x2000)
+#define MCF_EPORT_EPPAR_EPPA6_BOTH           (0x3000)
+#define MCF_EPORT_EPPAR_EPPA7(x)             (((x)&0x3)<<0xE)
+#define MCF_EPORT_EPPAR_EPPA7_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA7_RISING         (0x4000)
+#define MCF_EPORT_EPPAR_EPPA7_FALLING        (0x8000)
+#define MCF_EPORT_EPPAR_EPPA7_BOTH           (0xC000)
+#define MCF_EPORT_EPPAR_LEVEL                (0)
+#define MCF_EPORT_EPPAR_RISING               (0x1)
+#define MCF_EPORT_EPPAR_FALLING              (0x2)
+#define MCF_EPORT_EPPAR_BOTH                 (0x3)
+
+/* Bit definitions and macros for MCF_EPORT_EPDDR */
+#define MCF_EPORT_EPDDR_EPDD1                (0x2)
+#define MCF_EPORT_EPDDR_EPDD2                (0x4)
+#define MCF_EPORT_EPDDR_EPDD3                (0x8)
+#define MCF_EPORT_EPDDR_EPDD4                (0x10)
+#define MCF_EPORT_EPDDR_EPDD5                (0x20)
+#define MCF_EPORT_EPDDR_EPDD6                (0x40)
+#define MCF_EPORT_EPDDR_EPDD7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPIER */
+#define MCF_EPORT_EPIER_EPIE1                (0x2)
+#define MCF_EPORT_EPIER_EPIE2                (0x4)
+#define MCF_EPORT_EPIER_EPIE3                (0x8)
+#define MCF_EPORT_EPIER_EPIE4                (0x10)
+#define MCF_EPORT_EPIER_EPIE5                (0x20)
+#define MCF_EPORT_EPIER_EPIE6                (0x40)
+#define MCF_EPORT_EPIER_EPIE7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPDR */
+#define MCF_EPORT_EPDR_EPD1                  (0x2)
+#define MCF_EPORT_EPDR_EPD2                  (0x4)
+#define MCF_EPORT_EPDR_EPD3                  (0x8)
+#define MCF_EPORT_EPDR_EPD4                  (0x10)
+#define MCF_EPORT_EPDR_EPD5                  (0x20)
+#define MCF_EPORT_EPDR_EPD6                  (0x40)
+#define MCF_EPORT_EPDR_EPD7                  (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPPDR */
+#define MCF_EPORT_EPPDR_EPPD1                (0x2)
+#define MCF_EPORT_EPPDR_EPPD2                (0x4)
+#define MCF_EPORT_EPPDR_EPPD3                (0x8)
+#define MCF_EPORT_EPPDR_EPPD4                (0x10)
+#define MCF_EPORT_EPPDR_EPPD5                (0x20)
+#define MCF_EPORT_EPPDR_EPPD6                (0x40)
+#define MCF_EPORT_EPPDR_EPPD7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPFR */
+#define MCF_EPORT_EPFR_EPF1                  (0x2)
+#define MCF_EPORT_EPFR_EPF2                  (0x4)
+#define MCF_EPORT_EPFR_EPF3                  (0x8)
+#define MCF_EPORT_EPFR_EPF4                  (0x10)
+#define MCF_EPORT_EPFR_EPF5                  (0x20)
+#define MCF_EPORT_EPFR_EPF6                  (0x40)
+#define MCF_EPORT_EPFR_EPF7                  (0x80)
+
+
+#endif /* __MCF5475_EPORT_H__ */

tos/vmem_test/include/MCF5475_FBCS.h

@@ -0,0 +1,100 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_FBCS_H__
+#define __MCF5475_FBCS_H__
+
+
+/*********************************************************************
+*
+* FlexBus Chip Select Module (FBCS)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FBCS0_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x500]))
+#define MCF_FBCS0_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x504]))
+#define MCF_FBCS0_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x508]))
+
+#define MCF_FBCS1_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x50C]))
+#define MCF_FBCS1_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x510]))
+#define MCF_FBCS1_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x514]))
+
+#define MCF_FBCS2_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x518]))
+#define MCF_FBCS2_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x51C]))
+#define MCF_FBCS2_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x520]))
+
+#define MCF_FBCS3_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x524]))
+#define MCF_FBCS3_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x528]))
+#define MCF_FBCS3_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x52C]))
+
+#define MCF_FBCS4_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x530]))
+#define MCF_FBCS4_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x534]))
+#define MCF_FBCS4_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x538]))
+
+#define MCF_FBCS5_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x53C]))
+#define MCF_FBCS5_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x540]))
+#define MCF_FBCS5_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x544]))
+
+#define MCF_FBCS_CSAR(x)                     (*(volatile uint32_t*)(&_MBAR[0x500 + ((x)*0xC)]))
+#define MCF_FBCS_CSMR(x)                     (*(volatile uint32_t*)(&_MBAR[0x504 + ((x)*0xC)]))
+#define MCF_FBCS_CSCR(x)                     (*(volatile uint32_t*)(&_MBAR[0x508 + ((x)*0xC)]))
+
+
+/* Bit definitions and macros for MCF_FBCS_CSAR */
+#define MCF_FBCS_CSAR_BA(x)                  ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for MCF_FBCS_CSMR */
+#define MCF_FBCS_CSMR_V                      (0x1)
+#define MCF_FBCS_CSMR_WP                     (0x100)
+#define MCF_FBCS_CSMR_BAM(x)                 (((x)&0xFFFF)<<0x10)
+#define MCF_FBCS_CSMR_BAM_4G                 (0xFFFF0000)
+#define MCF_FBCS_CSMR_BAM_2G                 (0x7FFF0000)
+#define MCF_FBCS_CSMR_BAM_1G                 (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_1024M              (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_512M               (0x1FFF0000)
+#define MCF_FBCS_CSMR_BAM_256M               (0xFFF0000)
+#define MCF_FBCS_CSMR_BAM_128M               (0x7FF0000)
+#define MCF_FBCS_CSMR_BAM_64M                (0x3FF0000)
+#define MCF_FBCS_CSMR_BAM_32M                (0x1FF0000)
+#define MCF_FBCS_CSMR_BAM_16M                (0xFF0000)
+#define MCF_FBCS_CSMR_BAM_8M                 (0x7F0000)
+#define MCF_FBCS_CSMR_BAM_4M                 (0x3F0000)
+#define MCF_FBCS_CSMR_BAM_2M                 (0x1F0000)
+#define MCF_FBCS_CSMR_BAM_1M                 (0xF0000)
+#define MCF_FBCS_CSMR_BAM_1024K              (0xF0000)
+#define MCF_FBCS_CSMR_BAM_512K               (0x70000)
+#define MCF_FBCS_CSMR_BAM_256K               (0x30000)
+#define MCF_FBCS_CSMR_BAM_128K               (0x10000)
+#define MCF_FBCS_CSMR_BAM_64K                (0)
+
+/* Bit definitions and macros for MCF_FBCS_CSCR */
+#define MCF_FBCS_CSCR_BSTW                   (0x8)
+#define MCF_FBCS_CSCR_BSTR                   (0x10)
+#define MCF_FBCS_CSCR_BEM                    (0x20)
+#define MCF_FBCS_CSCR_PS(x)                  (((x)&0x3)<<0x6)
+#define MCF_FBCS_CSCR_PS_32                  (0)
+#define MCF_FBCS_CSCR_PS_8                   (0x40)
+#define MCF_FBCS_CSCR_PS_16                  (0x80)
+#define MCF_FBCS_CSCR_AA                     (0x100)
+#define MCF_FBCS_CSCR_WS(x)                  (((x)&0x3F)<<0xA)
+#define MCF_FBCS_CSCR_WRAH(x)                (((x)&0x3)<<0x10)
+#define MCF_FBCS_CSCR_RDAH(x)                (((x)&0x3)<<0x12)
+#define MCF_FBCS_CSCR_ASET(x)                (((x)&0x3)<<0x14)
+#define MCF_FBCS_CSCR_SWSEN                  (0x800000)
+#define MCF_FBCS_CSCR_SWS(x)                 (((x)&0x3F)<<0x1A)
+
+
+#endif /* __MCF5475_FBCS_H__ */

tos/vmem_test/include/MCF5475_FEC.h

@@ -0,0 +1,680 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_FEC_H__
+#define __MCF5475_FEC_H__
+
+
+/*********************************************************************
+*
+* Fast Ethernet Controller(FEC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FEC0_EIR                         (*(volatile uint32_t*)(&_MBAR[0x9004]))
+#define MCF_FEC0_EIMR                        (*(volatile uint32_t*)(&_MBAR[0x9008]))
+#define MCF_FEC0_ECR                         (*(volatile uint32_t*)(&_MBAR[0x9024]))
+#define MCF_FEC0_MMFR                        (*(volatile uint32_t*)(&_MBAR[0x9040]))
+#define MCF_FEC0_MSCR                        (*(volatile uint32_t*)(&_MBAR[0x9044]))
+#define MCF_FEC0_MIBC                        (*(volatile uint32_t*)(&_MBAR[0x9064]))
+#define MCF_FEC0_RCR                         (*(volatile uint32_t*)(&_MBAR[0x9084]))
+#define MCF_FEC0_RHR                         (*(volatile uint32_t*)(&_MBAR[0x9088]))
+#define MCF_FEC0_TCR                         (*(volatile uint32_t*)(&_MBAR[0x90C4]))
+#define MCF_FEC0_PALR                        (*(volatile uint32_t*)(&_MBAR[0x90E4]))
+#define MCF_FEC0_PAHR                        (*(volatile uint32_t*)(&_MBAR[0x90E8]))
+#define MCF_FEC0_OPD                         (*(volatile uint32_t*)(&_MBAR[0x90EC]))
+#define MCF_FEC0_IAUR                        (*(volatile uint32_t*)(&_MBAR[0x9118]))
+#define MCF_FEC0_IALR                        (*(volatile uint32_t*)(&_MBAR[0x911C]))
+#define MCF_FEC0_GAUR                        (*(volatile uint32_t*)(&_MBAR[0x9120]))
+#define MCF_FEC0_GALR                        (*(volatile uint32_t*)(&_MBAR[0x9124]))
+#define MCF_FEC0_FECTFWR                     (*(volatile uint32_t*)(&_MBAR[0x9144]))
+#define MCF_FEC0_FECRFDR                     (*(volatile uint32_t*)(&_MBAR[0x9184]))
+#define MCF_FEC0_FECRFSR                     (*(volatile uint32_t*)(&_MBAR[0x9188]))
+#define MCF_FEC0_FECRFCR                     (*(volatile uint32_t*)(&_MBAR[0x918C]))
+#define MCF_FEC0_FECRLRFP                    (*(volatile uint32_t*)(&_MBAR[0x9190]))
+#define MCF_FEC0_FECRLWFP                    (*(volatile uint32_t*)(&_MBAR[0x9194]))
+#define MCF_FEC0_FECRFAR                     (*(volatile uint32_t*)(&_MBAR[0x9198]))
+#define MCF_FEC0_FECRFRP                     (*(volatile uint32_t*)(&_MBAR[0x919C]))
+#define MCF_FEC0_FECRFWP                     (*(volatile uint32_t*)(&_MBAR[0x91A0]))
+#define MCF_FEC0_FECTFDR                     (*(volatile uint32_t*)(&_MBAR[0x91A4]))
+#define MCF_FEC0_FECTFSR                     (*(volatile uint32_t*)(&_MBAR[0x91A8]))
+#define MCF_FEC0_FECTFCR                     (*(volatile uint32_t*)(&_MBAR[0x91AC]))
+#define MCF_FEC0_FECTLRFP                    (*(volatile uint32_t*)(&_MBAR[0x91B0]))
+#define MCF_FEC0_FECTLWFP                    (*(volatile uint32_t*)(&_MBAR[0x91B4]))
+#define MCF_FEC0_FECTFAR                     (*(volatile uint32_t*)(&_MBAR[0x91B8]))
+#define MCF_FEC0_FECTFRP                     (*(volatile uint32_t*)(&_MBAR[0x91BC]))
+#define MCF_FEC0_FECTFWP                     (*(volatile uint32_t*)(&_MBAR[0x91C0]))
+#define MCF_FEC0_FECFRST                     (*(volatile uint32_t*)(&_MBAR[0x91C4]))
+#define MCF_FEC0_FECCTCWR                    (*(volatile uint32_t*)(&_MBAR[0x91C8]))
+#define MCF_FEC0_RMON_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9200]))
+#define MCF_FEC0_RMON_T_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9204]))
+#define MCF_FEC0_RMON_T_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9208]))
+#define MCF_FEC0_RMON_T_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x920C]))
+#define MCF_FEC0_RMON_T_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9210]))
+#define MCF_FEC0_RMON_T_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9214]))
+#define MCF_FEC0_RMON_T_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9218]))
+#define MCF_FEC0_RMON_T_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x921C]))
+#define MCF_FEC0_RMON_T_JAB                  (*(volatile uint32_t*)(&_MBAR[0x9220]))
+#define MCF_FEC0_RMON_T_COL                  (*(volatile uint32_t*)(&_MBAR[0x9224]))
+#define MCF_FEC0_RMON_T_P64                  (*(volatile uint32_t*)(&_MBAR[0x9228]))
+#define MCF_FEC0_RMON_T_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x922C]))
+#define MCF_FEC0_RMON_T_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x9230]))
+#define MCF_FEC0_RMON_T_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x9234]))
+#define MCF_FEC0_RMON_T_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x9238]))
+#define MCF_FEC0_RMON_T_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x923C]))
+#define MCF_FEC0_RMON_T_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x9240]))
+#define MCF_FEC0_RMON_T_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x9244]))
+#define MCF_FEC0_IEEE_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9248]))
+#define MCF_FEC0_IEEE_T_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x924C]))
+#define MCF_FEC0_IEEE_T_1COL                 (*(volatile uint32_t*)(&_MBAR[0x9250]))
+#define MCF_FEC0_IEEE_T_MCOL                 (*(volatile uint32_t*)(&_MBAR[0x9254]))
+#define MCF_FEC0_IEEE_T_DEF                  (*(volatile uint32_t*)(&_MBAR[0x9258]))
+#define MCF_FEC0_IEEE_T_LCOL                 (*(volatile uint32_t*)(&_MBAR[0x925C]))
+#define MCF_FEC0_IEEE_T_EXCOL                (*(volatile uint32_t*)(&_MBAR[0x9260]))
+#define MCF_FEC0_IEEE_T_MACERR               (*(volatile uint32_t*)(&_MBAR[0x9264]))
+#define MCF_FEC0_IEEE_T_CSERR                (*(volatile uint32_t*)(&_MBAR[0x9268]))
+#define MCF_FEC0_IEEE_T_SQE                  (*(volatile uint32_t*)(&_MBAR[0x926C]))
+#define MCF_FEC0_IEEE_T_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x9270]))
+#define MCF_FEC0_IEEE_T_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x9274]))
+#define MCF_FEC0_RMON_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9280]))
+#define MCF_FEC0_RMON_R_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9284]))
+#define MCF_FEC0_RMON_R_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9288]))
+#define MCF_FEC0_RMON_R_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x928C]))
+#define MCF_FEC0_RMON_R_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9290]))
+#define MCF_FEC0_RMON_R_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9294]))
+#define MCF_FEC0_RMON_R_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9298]))
+#define MCF_FEC0_RMON_R_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x929C]))
+#define MCF_FEC0_RMON_R_JAB                  (*(volatile uint32_t*)(&_MBAR[0x92A0]))
+#define MCF_FEC0_RMON_R_RESVD_0              (*(volatile uint32_t*)(&_MBAR[0x92A4]))
+#define MCF_FEC0_RMON_R_P64                  (*(volatile uint32_t*)(&_MBAR[0x92A8]))
+#define MCF_FEC0_RMON_R_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x92AC]))
+#define MCF_FEC0_RMON_R_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x92B0]))
+#define MCF_FEC0_RMON_R_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x92B4]))
+#define MCF_FEC0_RMON_R_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x92B8]))
+#define MCF_FEC0_RMON_R_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x92BC]))
+#define MCF_FEC0_RMON_R_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x92C0]))
+#define MCF_FEC0_RMON_R_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x92C4]))
+#define MCF_FEC0_IEEE_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x92C8]))
+#define MCF_FEC0_IEEE_R_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x92CC]))
+#define MCF_FEC0_IEEE_R_CRC                  (*(volatile uint32_t*)(&_MBAR[0x92D0]))
+#define MCF_FEC0_IEEE_R_ALIGN                (*(volatile uint32_t*)(&_MBAR[0x92D4]))
+#define MCF_FEC0_IEEE_R_MACERR               (*(volatile uint32_t*)(&_MBAR[0x92D8]))
+#define MCF_FEC0_IEEE_R_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x92DC]))
+#define MCF_FEC0_IEEE_R_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x92E0]))
+
+#define MCF_FEC1_EIR                         (*(volatile uint32_t*)(&_MBAR[0x9804]))
+#define MCF_FEC1_EIMR                        (*(volatile uint32_t*)(&_MBAR[0x9808]))
+#define MCF_FEC1_ECR                         (*(volatile uint32_t*)(&_MBAR[0x9824]))
+#define MCF_FEC1_MMFR                        (*(volatile uint32_t*)(&_MBAR[0x9840]))
+#define MCF_FEC1_MSCR                        (*(volatile uint32_t*)(&_MBAR[0x9844]))
+#define MCF_FEC1_MIBC                        (*(volatile uint32_t*)(&_MBAR[0x9864]))
+#define MCF_FEC1_RCR                         (*(volatile uint32_t*)(&_MBAR[0x9884]))
+#define MCF_FEC1_RHR                         (*(volatile uint32_t*)(&_MBAR[0x9888]))
+#define MCF_FEC1_TCR                         (*(volatile uint32_t*)(&_MBAR[0x98C4]))
+#define MCF_FEC1_PALR                        (*(volatile uint32_t*)(&_MBAR[0x98E4]))
+#define MCF_FEC1_PAHR                        (*(volatile uint32_t*)(&_MBAR[0x98E8]))
+#define MCF_FEC1_OPD                         (*(volatile uint32_t*)(&_MBAR[0x98EC]))
+#define MCF_FEC1_IAUR                        (*(volatile uint32_t*)(&_MBAR[0x9918]))
+#define MCF_FEC1_IALR                        (*(volatile uint32_t*)(&_MBAR[0x991C]))
+#define MCF_FEC1_GAUR                        (*(volatile uint32_t*)(&_MBAR[0x9920]))
+#define MCF_FEC1_GALR                        (*(volatile uint32_t*)(&_MBAR[0x9924]))
+#define MCF_FEC1_FECTFWR                     (*(volatile uint32_t*)(&_MBAR[0x9944]))
+#define MCF_FEC1_FECRFDR                     (*(volatile uint32_t*)(&_MBAR[0x9984]))
+#define MCF_FEC1_FECRFSR                     (*(volatile uint32_t*)(&_MBAR[0x9988]))
+#define MCF_FEC1_FECRFCR                     (*(volatile uint32_t*)(&_MBAR[0x998C]))
+#define MCF_FEC1_FECRLRFP                    (*(volatile uint32_t*)(&_MBAR[0x9990]))
+#define MCF_FEC1_FECRLWFP                    (*(volatile uint32_t*)(&_MBAR[0x9994]))
+#define MCF_FEC1_FECRFAR                     (*(volatile uint32_t*)(&_MBAR[0x9998]))
+#define MCF_FEC1_FECRFRP                     (*(volatile uint32_t*)(&_MBAR[0x999C]))
+#define MCF_FEC1_FECRFWP                     (*(volatile uint32_t*)(&_MBAR[0x99A0]))
+#define MCF_FEC1_FECTFDR                     (*(volatile uint32_t*)(&_MBAR[0x99A4]))
+#define MCF_FEC1_FECTFSR                     (*(volatile uint32_t*)(&_MBAR[0x99A8]))
+#define MCF_FEC1_FECTFCR                     (*(volatile uint32_t*)(&_MBAR[0x99AC]))
+#define MCF_FEC1_FECTLRFP                    (*(volatile uint32_t*)(&_MBAR[0x99B0]))
+#define MCF_FEC1_FECTLWFP                    (*(volatile uint32_t*)(&_MBAR[0x99B4]))
+#define MCF_FEC1_FECTFAR                     (*(volatile uint32_t*)(&_MBAR[0x99B8]))
+#define MCF_FEC1_FECTFRP                     (*(volatile uint32_t*)(&_MBAR[0x99BC]))
+#define MCF_FEC1_FECTFWP                     (*(volatile uint32_t*)(&_MBAR[0x99C0]))
+#define MCF_FEC1_FECFRST                     (*(volatile uint32_t*)(&_MBAR[0x99C4]))
+#define MCF_FEC1_FECCTCWR                    (*(volatile uint32_t*)(&_MBAR[0x99C8]))
+#define MCF_FEC1_RMON_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9A00]))
+#define MCF_FEC1_RMON_T_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9A04]))
+#define MCF_FEC1_RMON_T_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A08]))
+#define MCF_FEC1_RMON_T_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A0C]))
+#define MCF_FEC1_RMON_T_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9A10]))
+#define MCF_FEC1_RMON_T_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9A14]))
+#define MCF_FEC1_RMON_T_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9A18]))
+#define MCF_FEC1_RMON_T_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x9A1C]))
+#define MCF_FEC1_RMON_T_JAB                  (*(volatile uint32_t*)(&_MBAR[0x9A20]))
+#define MCF_FEC1_RMON_T_COL                  (*(volatile uint32_t*)(&_MBAR[0x9A24]))
+#define MCF_FEC1_RMON_T_P64                  (*(volatile uint32_t*)(&_MBAR[0x9A28]))
+#define MCF_FEC1_RMON_T_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x9A2C]))
+#define MCF_FEC1_RMON_T_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x9A30]))
+#define MCF_FEC1_RMON_T_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x9A34]))
+#define MCF_FEC1_RMON_T_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x9A38]))
+#define MCF_FEC1_RMON_T_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x9A3C]))
+#define MCF_FEC1_RMON_T_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x9A40]))
+#define MCF_FEC1_RMON_T_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x9A44]))
+#define MCF_FEC1_IEEE_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9A48]))
+#define MCF_FEC1_IEEE_T_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x9A4C]))
+#define MCF_FEC1_IEEE_T_1COL                 (*(volatile uint32_t*)(&_MBAR[0x9A50]))
+#define MCF_FEC1_IEEE_T_MCOL                 (*(volatile uint32_t*)(&_MBAR[0x9A54]))
+#define MCF_FEC1_IEEE_T_DEF                  (*(volatile uint32_t*)(&_MBAR[0x9A58]))
+#define MCF_FEC1_IEEE_T_LCOL                 (*(volatile uint32_t*)(&_MBAR[0x9A5C]))
+#define MCF_FEC1_IEEE_T_EXCOL                (*(volatile uint32_t*)(&_MBAR[0x9A60]))
+#define MCF_FEC1_IEEE_T_MACERR               (*(volatile uint32_t*)(&_MBAR[0x9A64]))
+#define MCF_FEC1_IEEE_T_CSERR                (*(volatile uint32_t*)(&_MBAR[0x9A68]))
+#define MCF_FEC1_IEEE_T_SQE                  (*(volatile uint32_t*)(&_MBAR[0x9A6C]))
+#define MCF_FEC1_IEEE_T_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x9A70]))
+#define MCF_FEC1_IEEE_T_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x9A74]))
+#define MCF_FEC1_RMON_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9A80]))
+#define MCF_FEC1_RMON_R_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9A84]))
+#define MCF_FEC1_RMON_R_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A88]))
+#define MCF_FEC1_RMON_R_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A8C]))
+#define MCF_FEC1_RMON_R_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9A90]))
+#define MCF_FEC1_RMON_R_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9A94]))
+#define MCF_FEC1_RMON_R_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9A98]))
+#define MCF_FEC1_RMON_R_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x9A9C]))
+#define MCF_FEC1_RMON_R_JAB                  (*(volatile uint32_t*)(&_MBAR[0x9AA0]))
+#define MCF_FEC1_RMON_R_RESVD_0              (*(volatile uint32_t*)(&_MBAR[0x9AA4]))
+#define MCF_FEC1_RMON_R_P64                  (*(volatile uint32_t*)(&_MBAR[0x9AA8]))
+#define MCF_FEC1_RMON_R_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x9AAC]))
+#define MCF_FEC1_RMON_R_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x9AB0]))
+#define MCF_FEC1_RMON_R_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x9AB4]))
+#define MCF_FEC1_RMON_R_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x9AB8]))
+#define MCF_FEC1_RMON_R_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x9ABC]))
+#define MCF_FEC1_RMON_R_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x9AC0]))
+#define MCF_FEC1_RMON_R_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x9AC4]))
+#define MCF_FEC1_IEEE_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9AC8]))
+#define MCF_FEC1_IEEE_R_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x9ACC]))
+#define MCF_FEC1_IEEE_R_CRC                  (*(volatile uint32_t*)(&_MBAR[0x9AD0]))
+#define MCF_FEC1_IEEE_R_ALIGN                (*(volatile uint32_t*)(&_MBAR[0x9AD4]))
+#define MCF_FEC1_IEEE_R_MACERR               (*(volatile uint32_t*)(&_MBAR[0x9AD8]))
+#define MCF_FEC1_IEEE_R_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x9ADC]))
+#define MCF_FEC1_IEEE_R_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x9AE0]))
+
+#define MCF_FEC_EIR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9004 + ((x)*0x800)]))
+#define MCF_FEC_EIMR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9008 + ((x)*0x800)]))
+#define MCF_FEC_ECR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9024 + ((x)*0x800)]))
+#define MCF_FEC_MMFR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9040 + ((x)*0x800)]))
+#define MCF_FEC_MSCR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9044 + ((x)*0x800)]))
+#define MCF_FEC_MIBC(x)                      (*(volatile uint32_t*)(&_MBAR[0x9064 + ((x)*0x800)]))
+#define MCF_FEC_RCR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9084 + ((x)*0x800)]))
+#define MCF_FEC_RHR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9088 + ((x)*0x800)]))
+#define MCF_FEC_TCR(x)                       (*(volatile uint32_t*)(&_MBAR[0x90C4 + ((x)*0x800)]))
+#define MCF_FEC_PALR(x)                      (*(volatile uint32_t*)(&_MBAR[0x90E4 + ((x)*0x800)]))
+#define MCF_FEC_PAHR(x)                      (*(volatile uint32_t*)(&_MBAR[0x90E8 + ((x)*0x800)]))
+#define MCF_FEC_OPD(x)                       (*(volatile uint32_t*)(&_MBAR[0x90EC + ((x)*0x800)]))
+#define MCF_FEC_IAUR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9118 + ((x)*0x800)]))
+#define MCF_FEC_IALR(x)                      (*(volatile uint32_t*)(&_MBAR[0x911C + ((x)*0x800)]))
+#define MCF_FEC_GAUR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9120 + ((x)*0x800)]))
+#define MCF_FEC_GALR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9124 + ((x)*0x800)]))
+#define MCF_FEC_FECTFWR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9144 + ((x)*0x800)]))
+#define MCF_FEC_FECRFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9184 + ((x)*0x800)]))
+#define MCF_FEC_FECRFSR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9188 + ((x)*0x800)]))
+#define MCF_FEC_FECRFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x918C + ((x)*0x800)]))
+#define MCF_FEC_FECRLRFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x9190 + ((x)*0x800)]))
+#define MCF_FEC_FECRLWFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x9194 + ((x)*0x800)]))
+#define MCF_FEC_FECRFAR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9198 + ((x)*0x800)]))
+#define MCF_FEC_FECRFRP(x)                   (*(volatile uint32_t*)(&_MBAR[0x919C + ((x)*0x800)]))
+#define MCF_FEC_FECRFWP(x)                   (*(volatile uint32_t*)(&_MBAR[0x91A0 + ((x)*0x800)]))
+#define MCF_FEC_FECTFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91A4 + ((x)*0x800)]))
+#define MCF_FEC_FECTFSR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91A8 + ((x)*0x800)]))
+#define MCF_FEC_FECTFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91AC + ((x)*0x800)]))
+#define MCF_FEC_FECTLRFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x91B0 + ((x)*0x800)]))
+#define MCF_FEC_FECTLWFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x91B4 + ((x)*0x800)]))
+#define MCF_FEC_FECTFAR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91B8 + ((x)*0x800)]))
+#define MCF_FEC_FECTFRP(x)                   (*(volatile uint32_t*)(&_MBAR[0x91BC + ((x)*0x800)]))
+#define MCF_FEC_FECTFWP(x)                   (*(volatile uint32_t*)(&_MBAR[0x91C0 + ((x)*0x800)]))
+#define MCF_FEC_FECFRST(x)                   (*(volatile uint32_t*)(&_MBAR[0x91C4 + ((x)*0x800)]))
+#define MCF_FEC_FECCTCWR(x)                  (*(volatile uint32_t*)(&_MBAR[0x91C8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x9200 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_PACKETS(x)            (*(volatile uint32_t*)(&_MBAR[0x9204 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_BC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x9208 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_MC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x920C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_CRC_ALIGN(x)          (*(volatile uint32_t*)(&_MBAR[0x9210 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_UNDERSIZE(x)          (*(volatile uint32_t*)(&_MBAR[0x9214 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_OVERSIZE(x)           (*(volatile uint32_t*)(&_MBAR[0x9218 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_FRAG(x)               (*(volatile uint32_t*)(&_MBAR[0x921C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_JAB(x)                (*(volatile uint32_t*)(&_MBAR[0x9220 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_COL(x)                (*(volatile uint32_t*)(&_MBAR[0x9224 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P64(x)                (*(volatile uint32_t*)(&_MBAR[0x9228 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P65TO127(x)           (*(volatile uint32_t*)(&_MBAR[0x922C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P128TO255(x)          (*(volatile uint32_t*)(&_MBAR[0x9230 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P256TO511(x)          (*(volatile uint32_t*)(&_MBAR[0x9234 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P512TO1023(x)         (*(volatile uint32_t*)(&_MBAR[0x9238 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P1024TO2047(x)        (*(volatile uint32_t*)(&_MBAR[0x923C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P_GTE2048(x)          (*(volatile uint32_t*)(&_MBAR[0x9240 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_OCTETS(x)             (*(volatile uint32_t*)(&_MBAR[0x9244 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x9248 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_FRAME_OK(x)           (*(volatile uint32_t*)(&_MBAR[0x924C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_1COL(x)               (*(volatile uint32_t*)(&_MBAR[0x9250 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_MCOL(x)               (*(volatile uint32_t*)(&_MBAR[0x9254 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_DEF(x)                (*(volatile uint32_t*)(&_MBAR[0x9258 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_LCOL(x)               (*(volatile uint32_t*)(&_MBAR[0x925C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_EXCOL(x)              (*(volatile uint32_t*)(&_MBAR[0x9260 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_MACERR(x)             (*(volatile uint32_t*)(&_MBAR[0x9264 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_CSERR(x)              (*(volatile uint32_t*)(&_MBAR[0x9268 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_SQE(x)                (*(volatile uint32_t*)(&_MBAR[0x926C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_FDXFC(x)              (*(volatile uint32_t*)(&_MBAR[0x9270 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_OCTETS_OK(x)          (*(volatile uint32_t*)(&_MBAR[0x9274 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x9280 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_PACKETS(x)            (*(volatile uint32_t*)(&_MBAR[0x9284 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_BC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x9288 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_MC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x928C + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_CRC_ALIGN(x)          (*(volatile uint32_t*)(&_MBAR[0x9290 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_UNDERSIZE(x)          (*(volatile uint32_t*)(&_MBAR[0x9294 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_OVERSIZE(x)           (*(volatile uint32_t*)(&_MBAR[0x9298 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_FRAG(x)               (*(volatile uint32_t*)(&_MBAR[0x929C + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_JAB(x)                (*(volatile uint32_t*)(&_MBAR[0x92A0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_RESVD_0(x)            (*(volatile uint32_t*)(&_MBAR[0x92A4 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P64(x)                (*(volatile uint32_t*)(&_MBAR[0x92A8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P65TO127(x)           (*(volatile uint32_t*)(&_MBAR[0x92AC + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P128TO255(x)          (*(volatile uint32_t*)(&_MBAR[0x92B0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P256TO511(x)          (*(volatile uint32_t*)(&_MBAR[0x92B4 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P512TO1023(x)         (*(volatile uint32_t*)(&_MBAR[0x92B8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P1024TO2047(x)        (*(volatile uint32_t*)(&_MBAR[0x92BC + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P_GTE2048(x)          (*(volatile uint32_t*)(&_MBAR[0x92C0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_OCTETS(x)             (*(volatile uint32_t*)(&_MBAR[0x92C4 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x92C8 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_FRAME_OK(x)           (*(volatile uint32_t*)(&_MBAR[0x92CC + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_CRC(x)                (*(volatile uint32_t*)(&_MBAR[0x92D0 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_ALIGN(x)              (*(volatile uint32_t*)(&_MBAR[0x92D4 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_MACERR(x)             (*(volatile uint32_t*)(&_MBAR[0x92D8 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_FDXFC(x)              (*(volatile uint32_t*)(&_MBAR[0x92DC + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_OCTETS_OK(x)          (*(volatile uint32_t*)(&_MBAR[0x92E0 + ((x)*0x800)]))
+
+
+/* Bit definitions and macros for MCF_FEC_EIR */
+#define MCF_FEC_EIR_RFERR                    (0x20000)
+#define MCF_FEC_EIR_XFERR                    (0x40000)
+#define MCF_FEC_EIR_XFUN                     (0x80000)
+#define MCF_FEC_EIR_RL                       (0x100000)
+#define MCF_FEC_EIR_LC                       (0x200000)
+#define MCF_FEC_EIR_MII                      (0x800000)
+#define MCF_FEC_EIR_TXF                      (0x8000000)
+#define MCF_FEC_EIR_GRA                      (0x10000000)
+#define MCF_FEC_EIR_BABT                     (0x20000000)
+#define MCF_FEC_EIR_BABR                     (0x40000000)
+#define MCF_FEC_EIR_HBERR                    (0x80000000)
+#define MCF_FEC_EIR_CLEAR_ALL                (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_EIMR */
+#define MCF_FEC_EIMR_RFERR                   (0x20000)
+#define MCF_FEC_EIMR_XFERR                   (0x40000)
+#define MCF_FEC_EIMR_XFUN                    (0x80000)
+#define MCF_FEC_EIMR_RL                      (0x100000)
+#define MCF_FEC_EIMR_LC                      (0x200000)
+#define MCF_FEC_EIMR_MII                     (0x800000)
+#define MCF_FEC_EIMR_TXF                     (0x8000000)
+#define MCF_FEC_EIMR_GRA                     (0x10000000)
+#define MCF_FEC_EIMR_BABT                    (0x20000000)
+#define MCF_FEC_EIMR_BABR                    (0x40000000)
+#define MCF_FEC_EIMR_HBERR                   (0x80000000)
+#define MCF_FEC_EIMR_MASK_ALL                (0)
+#define MCF_FEC_EIMR_UNMASK_ALL              (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_ECR */
+#define MCF_FEC_ECR_RESET                    (0x1)
+#define MCF_FEC_ECR_ETHER_EN                 (0x2)
+
+/* Bit definitions and macros for MCF_FEC_MMFR */
+#define MCF_FEC_MMFR_DATA(x)                 (((x)&0xFFFF)<<0)
+#define MCF_FEC_MMFR_TA(x)                   (((x)&0x3)<<0x10)
+#define MCF_FEC_MMFR_TA_10                   (0x20000)
+#define MCF_FEC_MMFR_RA(x)                   (((x)&0x1F)<<0x12)
+#define MCF_FEC_MMFR_PA(x)                   (((x)&0x1F)<<0x17)
+#define MCF_FEC_MMFR_OP(x)                   (((x)&0x3)<<0x1C)
+#define MCF_FEC_MMFR_OP_READ                 (0x20000000)
+#define MCF_FEC_MMFR_OP_WRITE                (0x10000000)
+#define MCF_FEC_MMFR_ST(x)                   (((x)&0x3)<<0x1E)
+#define MCF_FEC_MMFR_ST_01                   (0x40000000)
+
+/* Bit definitions and macros for MCF_FEC_MSCR */
+#define MCF_FEC_MSCR_MII_SPEED(x)            (((x)&0x3F)<<0x1)
+#define MCF_FEC_MSCR_DIS_PREAMBLE            (0x80)
+#define MCF_FEC_MSCR_MII_SPEED_133           (0x1B<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_120           (0x18<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_66            (0xE<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_60            (0xC<<0x1)
+
+/* Bit definitions and macros for MCF_FEC_MIBC */
+#define MCF_FEC_MIBC_MIB_IDLE                (0x40000000)
+#define MCF_FEC_MIBC_MIB_DISABLE             (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_RCR */
+#define MCF_FEC_RCR_LOOP                     (0x1)
+#define MCF_FEC_RCR_DRT                      (0x2)
+#define MCF_FEC_RCR_MII_MODE                 (0x4)
+#define MCF_FEC_RCR_PROM                     (0x8)
+#define MCF_FEC_RCR_BC_REJ                   (0x10)
+#define MCF_FEC_RCR_FCE                      (0x20)
+#define MCF_FEC_RCR_MAX_FL(x)                (((x)&0x7FF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_RHR */
+#define MCF_FEC_RHR_HASH(x)                  (((x)&0x3F)<<0x18)
+#define MCF_FEC_RHR_MULTCAST                 (0x40000000)
+#define MCF_FEC_RHR_FCE                      (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_TCR */
+#define MCF_FEC_TCR_GTS                      (0x1)
+#define MCF_FEC_TCR_HBC                      (0x2)
+#define MCF_FEC_TCR_FDEN                     (0x4)
+#define MCF_FEC_TCR_TFC_PAUSE                (0x8)
+#define MCF_FEC_TCR_RFC_PAUSE                (0x10)
+
+/* Bit definitions and macros for MCF_FEC_PALR */
+#define MCF_FEC_PALR_PADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_PAHR */
+#define MCF_FEC_PAHR_TYPE(x)                 (((x)&0xFFFF)<<0)
+#define MCF_FEC_PAHR_PADDR2(x)               (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_OPD */
+#define MCF_FEC_OPD_PAUSE_DUR(x)             (((x)&0xFFFF)<<0)
+#define MCF_FEC_OPD_OPCODE(x)                (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_IAUR */
+#define MCF_FEC_IAUR_IADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IALR */
+#define MCF_FEC_IALR_IADDR2(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_GAUR */
+#define MCF_FEC_GAUR_GADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_GALR */
+#define MCF_FEC_GALR_GADDR2(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFWR */
+#define MCF_FEC_FECTFWR_X_WMRK(x)            (((x)&0xF)<<0)
+#define MCF_FEC_FECTFWR_X_WMRK_64            (0)
+#define MCF_FEC_FECTFWR_X_WMRK_128           (0x1)
+#define MCF_FEC_FECTFWR_X_WMRK_192           (0x2)
+#define MCF_FEC_FECTFWR_X_WMRK_256           (0x3)
+#define MCF_FEC_FECTFWR_X_WMRK_320           (0x4)
+#define MCF_FEC_FECTFWR_X_WMRK_384           (0x5)
+#define MCF_FEC_FECTFWR_X_WMRK_448           (0x6)
+#define MCF_FEC_FECTFWR_X_WMRK_512           (0x7)
+#define MCF_FEC_FECTFWR_X_WMRK_576           (0x8)
+#define MCF_FEC_FECTFWR_X_WMRK_640           (0x9)
+#define MCF_FEC_FECTFWR_X_WMRK_704           (0xA)
+#define MCF_FEC_FECTFWR_X_WMRK_768           (0xB)
+#define MCF_FEC_FECTFWR_X_WMRK_832           (0xC)
+#define MCF_FEC_FECTFWR_X_WMRK_896           (0xD)
+#define MCF_FEC_FECTFWR_X_WMRK_960           (0xE)
+#define MCF_FEC_FECTFWR_X_WMRK_1024          (0xF)
+
+/* Bit definitions and macros for MCF_FEC_FECRFDR */
+#define MCF_FEC_FECRFDR_FIFO_DATA(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFSR */
+#define MCF_FEC_FECRFSR_EMT                  (0x10000)
+#define MCF_FEC_FECRFSR_ALARM                (0x20000)
+#define MCF_FEC_FECRFSR_FU                   (0x40000)
+#define MCF_FEC_FECRFSR_FRMRDY               (0x80000)
+#define MCF_FEC_FECRFSR_OF                   (0x100000)
+#define MCF_FEC_FECRFSR_UF                   (0x200000)
+#define MCF_FEC_FECRFSR_RXW                  (0x400000)
+#define MCF_FEC_FECRFSR_FAE                  (0x800000)
+#define MCF_FEC_FECRFSR_FRM(x)               (((x)&0xF)<<0x18)
+#define MCF_FEC_FECRFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_FECRFCR */
+#define MCF_FEC_FECRFCR_COUNTER(x)           (((x)&0xFFFF)<<0)
+#define MCF_FEC_FECRFCR_OF_MSK               (0x80000)
+#define MCF_FEC_FECRFCR_UF_MSK               (0x100000)
+#define MCF_FEC_FECRFCR_RXW_MSK              (0x200000)
+#define MCF_FEC_FECRFCR_FAE_MSK              (0x400000)
+#define MCF_FEC_FECRFCR_IP_MSK               (0x800000)
+#define MCF_FEC_FECRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_FEC_FECRFCR_FRMEN                (0x8000000)
+#define MCF_FEC_FECRFCR_TIMER                (0x10000000)
+
+/* Bit definitions and macros for MCF_FEC_FECRLRFP */
+#define MCF_FEC_FECRLRFP_LRFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRLWFP */
+#define MCF_FEC_FECRLWFP_LWFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFAR */
+#define MCF_FEC_FECRFAR_ALARM(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFRP */
+#define MCF_FEC_FECRFRP_READ(x)              (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFWP */
+#define MCF_FEC_FECRFWP_WRITE(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFDR */
+#define MCF_FEC_FECTFDR_FIFO_DATA(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFSR */
+#define MCF_FEC_FECTFSR_EMT                  (0x10000)
+#define MCF_FEC_FECTFSR_ALARM                (0x20000)
+#define MCF_FEC_FECTFSR_FU                   (0x40000)
+#define MCF_FEC_FECTFSR_FRMRDY               (0x80000)
+#define MCF_FEC_FECTFSR_OF                   (0x100000)
+#define MCF_FEC_FECTFSR_UF                   (0x200000)
+#define MCF_FEC_FECTFSR_FAE                  (0x800000)
+#define MCF_FEC_FECTFSR_FRM(x)               (((x)&0xF)<<0x18)
+#define MCF_FEC_FECTFSR_TXW                  (0x40000000)
+#define MCF_FEC_FECTFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_FECTFCR */
+#define MCF_FEC_FECTFCR_RESERVED             (0x200000)
+#define MCF_FEC_FECTFCR_COUNTER(x)           (((x)&0xFFFF)<<0|0x200000)
+#define MCF_FEC_FECTFCR_TXW_MASK             (0x240000)
+#define MCF_FEC_FECTFCR_OF_MSK               (0x280000)
+#define MCF_FEC_FECTFCR_UF_MSK               (0x300000)
+#define MCF_FEC_FECTFCR_FAE_MSK              (0x600000)
+#define MCF_FEC_FECTFCR_IP_MSK               (0xA00000)
+#define MCF_FEC_FECTFCR_GR(x)                (((x)&0x7)<<0x18|0x200000)
+#define MCF_FEC_FECTFCR_FRMEN                (0x8200000)
+#define MCF_FEC_FECTFCR_TIMER                (0x10200000)
+#define MCF_FEC_FECTFCR_WFR                  (0x20200000)
+#define MCF_FEC_FECTFCR_WCTL                 (0x40200000)
+
+/* Bit definitions and macros for MCF_FEC_FECTLRFP */
+#define MCF_FEC_FECTLRFP_LRFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTLWFP */
+#define MCF_FEC_FECTLWFP_LWFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFAR */
+#define MCF_FEC_FECTFAR_ALARM(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFRP */
+#define MCF_FEC_FECTFRP_READ(x)              (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFWP */
+#define MCF_FEC_FECTFWP_WRITE(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECFRST */
+#define MCF_FEC_FECFRST_RST_CTL              (0x1000000)
+#define MCF_FEC_FECFRST_SW_RST               (0x2000000)
+
+/* Bit definitions and macros for MCF_FEC_FECCTCWR */
+#define MCF_FEC_FECCTCWR_TFCW                (0x1000000)
+#define MCF_FEC_FECCTCWR_CRC                 (0x2000000)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */
+#define MCF_FEC_RMON_T_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */
+#define MCF_FEC_RMON_T_PACKETS_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */
+#define MCF_FEC_RMON_T_BC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */
+#define MCF_FEC_RMON_T_MC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */
+#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */
+#define MCF_FEC_RMON_T_UNDERSIZE_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */
+#define MCF_FEC_RMON_T_OVERSIZE_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */
+#define MCF_FEC_RMON_T_FRAG_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */
+#define MCF_FEC_RMON_T_JAB_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_COL */
+#define MCF_FEC_RMON_T_COL_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */
+#define MCF_FEC_RMON_T_P64_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */
+#define MCF_FEC_RMON_T_P65TO127_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */
+#define MCF_FEC_RMON_T_P128TO255_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */
+#define MCF_FEC_RMON_T_P256TO511_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */
+#define MCF_FEC_RMON_T_P512TO1023_Value(x)   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */
+#define MCF_FEC_RMON_T_P1024TO2047_Value(x)  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */
+#define MCF_FEC_RMON_T_P_GTE2048_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */
+#define MCF_FEC_RMON_T_OCTETS_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */
+#define MCF_FEC_IEEE_T_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */
+#define MCF_FEC_IEEE_T_FRAME_OK_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */
+#define MCF_FEC_IEEE_T_1COL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */
+#define MCF_FEC_IEEE_T_MCOL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */
+#define MCF_FEC_IEEE_T_DEF_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */
+#define MCF_FEC_IEEE_T_LCOL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */
+#define MCF_FEC_IEEE_T_EXCOL_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */
+#define MCF_FEC_IEEE_T_MACERR_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */
+#define MCF_FEC_IEEE_T_CSERR_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */
+#define MCF_FEC_IEEE_T_SQE_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */
+#define MCF_FEC_IEEE_T_FDXFC_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */
+#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */
+#define MCF_FEC_RMON_R_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */
+#define MCF_FEC_RMON_R_PACKETS_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */
+#define MCF_FEC_RMON_R_BC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */
+#define MCF_FEC_RMON_R_MC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */
+#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */
+#define MCF_FEC_RMON_R_UNDERSIZE_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */
+#define MCF_FEC_RMON_R_OVERSIZE_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */
+#define MCF_FEC_RMON_R_FRAG_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */
+#define MCF_FEC_RMON_R_JAB_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */
+#define MCF_FEC_RMON_R_RESVD_0_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */
+#define MCF_FEC_RMON_R_P64_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */
+#define MCF_FEC_RMON_R_P65TO127_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */
+#define MCF_FEC_RMON_R_P128TO255_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */
+#define MCF_FEC_RMON_R_P256TO511_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */
+#define MCF_FEC_RMON_R_P512TO1023_Value(x)   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */
+#define MCF_FEC_RMON_R_P1024TO2047_Value(x)  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */
+#define MCF_FEC_RMON_R_P_GTE2048_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */
+#define MCF_FEC_RMON_R_OCTETS_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */
+#define MCF_FEC_IEEE_R_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */
+#define MCF_FEC_IEEE_R_FRAME_OK_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */
+#define MCF_FEC_IEEE_R_CRC_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */
+#define MCF_FEC_IEEE_R_ALIGN_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */
+#define MCF_FEC_IEEE_R_MACERR_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */
+#define MCF_FEC_IEEE_R_FDXFC_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */
+#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+
+#endif /* __MCF5475_FEC_H__ */

tos/vmem_test/include/MCF5475_GPIO.h

@@ -0,0 +1,543 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_GPIO_H__
+#define __MCF5475_GPIO_H__
+
+
+/*********************************************************************
+*
+* General Purpose I/O (GPIO)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPIO_PODR_FBCTL                  (*(volatile uint8_t *)(&_MBAR[0xA00]))
+#define MCF_GPIO_PDDR_FBCTL                  (*(volatile uint8_t *)(&_MBAR[0xA10]))
+#define MCF_GPIO_PPDSDR_FBCTL                (*(volatile uint8_t *)(&_MBAR[0xA20]))
+#define MCF_GPIO_PCLRR_FBCTL                 (*(volatile uint8_t *)(&_MBAR[0xA30]))
+
+#define MCF_GPIO_PODR_FBCS                   (*(volatile uint8_t *)(&_MBAR[0xA01]))
+#define MCF_GPIO_PDDR_FBCS                   (*(volatile uint8_t *)(&_MBAR[0xA11]))
+#define MCF_GPIO_PPDSDR_FBCS                 (*(volatile uint8_t *)(&_MBAR[0xA21]))
+#define MCF_GPIO_PCLRR_FBCS                  (*(volatile uint8_t *)(&_MBAR[0xA31]))
+
+#define MCF_GPIO_PODR_DMA                    (*(volatile uint8_t *)(&_MBAR[0xA02]))
+#define MCF_GPIO_PDDR_DMA                    (*(volatile uint8_t *)(&_MBAR[0xA12]))
+#define MCF_GPIO_PPDSDR_DMA                  (*(volatile uint8_t *)(&_MBAR[0xA22]))
+#define MCF_GPIO_PCLRR_DMA                   (*(volatile uint8_t *)(&_MBAR[0xA32]))
+
+#define MCF_GPIO_PODR_FEC0H                  (*(volatile uint8_t *)(&_MBAR[0xA04]))
+#define MCF_GPIO_PDDR_FEC0H                  (*(volatile uint8_t *)(&_MBAR[0xA14]))
+#define MCF_GPIO_PPDSDR_FEC0H                (*(volatile uint8_t *)(&_MBAR[0xA24]))
+#define MCF_GPIO_PCLRR_FEC0H                 (*(volatile uint8_t *)(&_MBAR[0xA34]))
+
+#define MCF_GPIO_PODR_FEC0L                  (*(volatile uint8_t *)(&_MBAR[0xA05]))
+#define MCF_GPIO_PDDR_FEC0L                  (*(volatile uint8_t *)(&_MBAR[0xA15]))
+#define MCF_GPIO_PPDSDR_FEC0L                (*(volatile uint8_t *)(&_MBAR[0xA25]))
+#define MCF_GPIO_PCLRR_FEC0L                 (*(volatile uint8_t *)(&_MBAR[0xA35]))
+
+#define MCF_GPIO_PODR_FEC1H                  (*(volatile uint8_t *)(&_MBAR[0xA06]))
+#define MCF_GPIO_PDDR_FEC1H                  (*(volatile uint8_t *)(&_MBAR[0xA16]))
+#define MCF_GPIO_PPDSDR_FEC1H                (*(volatile uint8_t *)(&_MBAR[0xA26]))
+#define MCF_GPIO_PCLRR_FEC1H                 (*(volatile uint8_t *)(&_MBAR[0xA36]))
+
+#define MCF_GPIO_PODR_FEC1L                  (*(volatile uint8_t *)(&_MBAR[0xA07]))
+#define MCF_GPIO_PDDR_FEC1L                  (*(volatile uint8_t *)(&_MBAR[0xA17]))
+#define MCF_GPIO_PPDSDR_FEC1L                (*(volatile uint8_t *)(&_MBAR[0xA27]))
+#define MCF_GPIO_PCLRR_FEC1L                 (*(volatile uint8_t *)(&_MBAR[0xA37]))
+
+#define MCF_GPIO_PODR_FECI2C                 (*(volatile uint8_t *)(&_MBAR[0xA08]))
+#define MCF_GPIO_PDDR_FECI2C                 (*(volatile uint8_t *)(&_MBAR[0xA18]))
+#define MCF_GPIO_PPDSDR_FECI2C               (*(volatile uint8_t *)(&_MBAR[0xA28]))
+#define MCF_GPIO_PCLRR_FECI2C                (*(volatile uint8_t *)(&_MBAR[0xA38]))
+
+#define MCF_GPIO_PODR_PCIBG                  (*(volatile uint8_t *)(&_MBAR[0xA09]))
+#define MCF_GPIO_PDDR_PCIBG                  (*(volatile uint8_t *)(&_MBAR[0xA19]))
+#define MCF_GPIO_PPDSDR_PCIBG                (*(volatile uint8_t *)(&_MBAR[0xA29]))
+#define MCF_GPIO_PCLRR_PCIBG                 (*(volatile uint8_t *)(&_MBAR[0xA39]))
+
+#define MCF_GPIO_PODR_PCIBR                  (*(volatile uint8_t *)(&_MBAR[0xA0A]))
+#define MCF_GPIO_PDDR_PCIBR                  (*(volatile uint8_t *)(&_MBAR[0xA1A]))
+#define MCF_GPIO_PPDSDR_PCIBR                (*(volatile uint8_t *)(&_MBAR[0xA2A]))
+#define MCF_GPIO_PCLRR_PCIBR                 (*(volatile uint8_t *)(&_MBAR[0xA3A]))
+
+#define MCF_GPIO2_PODR_PSC3PSC               (*(volatile uint8_t *)(&_MBAR[0xA0C]))
+#define MCF_GPIO2_PDDR_PSC3PSC               (*(volatile uint8_t *)(&_MBAR[0xA1C]))
+#define MCF_GPIO2_PPDSDR_PSC3PSC             (*(volatile uint8_t *)(&_MBAR[0xA2C]))
+#define MCF_GPIO2_PCLRR_PSC3PSC              (*(volatile uint8_t *)(&_MBAR[0xA3C]))
+
+#define MCF_GPIO0_PODR_PSC1PSC               (*(volatile uint8_t *)(&_MBAR[0xA0D]))
+#define MCF_GPIO0_PDDR_PSC1PSC               (*(volatile uint8_t *)(&_MBAR[0xA1D]))
+#define MCF_GPIO0_PPDSDR_PSC1PSC             (*(volatile uint8_t *)(&_MBAR[0xA2D]))
+#define MCF_GPIO0_PCLRR_PSC1PSC              (*(volatile uint8_t *)(&_MBAR[0xA3D]))
+
+#define MCF_GPIO_PODR_DSPI                   (*(volatile uint8_t *)(&_MBAR[0xA0E]))
+#define MCF_GPIO_PDDR_DSPI                   (*(volatile uint8_t *)(&_MBAR[0xA1E]))
+#define MCF_GPIO_PPDSDR_DSPI                 (*(volatile uint8_t *)(&_MBAR[0xA2E]))
+#define MCF_GPIO_PCLRR_DSPI                  (*(volatile uint8_t *)(&_MBAR[0xA3E]))
+
+
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0      (0x1)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1      (0x2)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2      (0x4)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3      (0x8)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4      (0x10)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5      (0x20)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6      (0x40)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0      (0x1)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1      (0x2)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2      (0x4)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3      (0x8)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4      (0x10)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5      (0x20)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6      (0x40)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0  (0x1)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1  (0x2)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2  (0x4)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3  (0x8)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4  (0x10)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5  (0x20)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6  (0x40)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0    (0x1)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1    (0x2)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2    (0x4)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3    (0x8)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4    (0x10)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5    (0x20)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6    (0x40)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS1        (0x2)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS2        (0x4)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS3        (0x8)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS4        (0x10)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS5        (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1        (0x2)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2        (0x4)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3        (0x8)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4        (0x10)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5        (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1    (0x2)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2    (0x4)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3    (0x8)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4    (0x10)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5    (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1      (0x2)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2      (0x4)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3      (0x8)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4      (0x10)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5      (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
+#define MCF_GPIO_PODR_DMA_PODR_DMA0          (0x1)
+#define MCF_GPIO_PODR_DMA_PODR_DMA1          (0x2)
+#define MCF_GPIO_PODR_DMA_PODR_DMA2          (0x4)
+#define MCF_GPIO_PODR_DMA_PODR_DMA3          (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA0          (0x1)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA1          (0x2)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA2          (0x4)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA3          (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0      (0x1)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1      (0x2)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2      (0x4)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3      (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0        (0x1)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1        (0x2)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2        (0x4)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3        (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0      (0x1)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1      (0x2)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2      (0x4)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3      (0x8)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4      (0x10)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5      (0x20)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6      (0x40)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0      (0x1)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1      (0x2)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2      (0x4)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3      (0x8)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4      (0x10)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5      (0x20)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6      (0x40)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0    (0x1)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1    (0x2)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2    (0x4)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3    (0x8)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4    (0x10)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5    (0x20)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6    (0x40)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0      (0x1)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1      (0x2)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2      (0x4)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3      (0x8)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4      (0x10)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5      (0x20)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6      (0x40)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0      (0x1)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1      (0x2)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2      (0x4)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3      (0x8)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4      (0x10)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5      (0x20)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6      (0x40)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0    (0x1)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1    (0x2)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2    (0x4)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3    (0x8)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4    (0x10)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5    (0x20)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6    (0x40)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0      (0x1)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1      (0x2)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2      (0x4)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3      (0x8)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4      (0x10)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5      (0x20)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6      (0x40)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0      (0x1)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1      (0x2)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2      (0x4)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3      (0x8)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4      (0x10)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5      (0x20)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6      (0x40)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0    (0x1)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1    (0x2)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2    (0x4)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3    (0x8)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4    (0x10)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5    (0x20)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6    (0x40)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0      (0x1)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1      (0x2)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2      (0x4)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3      (0x8)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4      (0x10)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5      (0x20)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6      (0x40)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0      (0x1)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1      (0x2)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2      (0x4)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3      (0x8)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4      (0x10)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5      (0x20)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6      (0x40)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0    (0x1)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1    (0x2)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2    (0x4)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3    (0x8)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4    (0x10)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5    (0x20)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6    (0x40)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0    (0x1)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1    (0x2)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2    (0x4)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3    (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0    (0x1)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1    (0x2)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2    (0x4)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3    (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0  (0x1)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1  (0x2)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2  (0x4)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3  (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0      (0x1)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1      (0x2)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2      (0x4)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3      (0x8)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0      (0x1)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1      (0x2)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2      (0x4)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3      (0x8)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0  (0x1)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1  (0x2)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2  (0x4)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3  (0x8)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4  (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0    (0x1)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1    (0x2)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2    (0x4)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3    (0x8)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4    (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0      (0x1)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1      (0x2)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2      (0x4)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3      (0x8)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0      (0x1)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1      (0x2)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2      (0x4)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3      (0x8)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0  (0x1)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1  (0x2)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2  (0x4)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3  (0x8)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4  (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0    (0x1)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1    (0x2)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2    (0x4)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3    (0x8)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4    (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI0        (0x1)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI1        (0x2)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI2        (0x4)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI3        (0x8)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI4        (0x10)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI5        (0x20)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI6        (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0        (0x1)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1        (0x2)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2        (0x4)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3        (0x8)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4        (0x10)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5        (0x20)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6        (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0    (0x1)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1    (0x2)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2    (0x4)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3    (0x8)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4    (0x10)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5    (0x20)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6    (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0      (0x1)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1      (0x2)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2      (0x4)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3      (0x8)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4      (0x10)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5      (0x20)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6      (0x40)
+
+
+#endif /* __MCF5475_GPIO_H__ */

tos/vmem_test/include/MCF5475_GPT.h

@@ -0,0 +1,100 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_GPT_H__
+#define __MCF5475_GPT_H__
+
+
+/*********************************************************************
+*
+* General Purpose Timers (GPT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPT0_GMS                         (*(volatile uint32_t*)(&_MBAR[0x800]))
+#define MCF_GPT0_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x804]))
+#define MCF_GPT0_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x808]))
+#define MCF_GPT0_GSR                         (*(volatile uint32_t*)(&_MBAR[0x80C]))
+
+#define MCF_GPT1_GMS                         (*(volatile uint32_t*)(&_MBAR[0x810]))
+#define MCF_GPT1_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x814]))
+#define MCF_GPT1_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x818]))
+#define MCF_GPT1_GSR                         (*(volatile uint32_t*)(&_MBAR[0x81C]))
+
+#define MCF_GPT2_GMS                         (*(volatile uint32_t*)(&_MBAR[0x820]))
+#define MCF_GPT2_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x824]))
+#define MCF_GPT2_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x828]))
+#define MCF_GPT2_GSR                         (*(volatile uint32_t*)(&_MBAR[0x82C]))
+
+#define MCF_GPT3_GMS                         (*(volatile uint32_t*)(&_MBAR[0x830]))
+#define MCF_GPT3_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x834]))
+#define MCF_GPT3_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x838]))
+#define MCF_GPT3_GSR                         (*(volatile uint32_t*)(&_MBAR[0x83C]))
+
+#define MCF_GPT_GMS(x)                       (*(volatile uint32_t*)(&_MBAR[0x800 + ((x)*0x10)]))
+#define MCF_GPT_GCIR(x)                      (*(volatile uint32_t*)(&_MBAR[0x804 + ((x)*0x10)]))
+#define MCF_GPT_GPWM(x)                      (*(volatile uint32_t*)(&_MBAR[0x808 + ((x)*0x10)]))
+#define MCF_GPT_GSR(x)                       (*(volatile uint32_t*)(&_MBAR[0x80C + ((x)*0x10)]))
+
+
+/* Bit definitions and macros for MCF_GPT_GMS */
+#define MCF_GPT_GMS_TMS(x)                   (((x)&0x7)<<0)
+#define MCF_GPT_GMS_TMS_DISABLE              (0)
+#define MCF_GPT_GMS_TMS_INCAPT               (0x1)
+#define MCF_GPT_GMS_TMS_OUTCAPT              (0x2)
+#define MCF_GPT_GMS_TMS_PWM                  (0x3)
+#define MCF_GPT_GMS_TMS_GPIO                 (0x4)
+#define MCF_GPT_GMS_GPIO(x)                  (((x)&0x3)<<0x4)
+#define MCF_GPT_GMS_GPIO_INPUT               (0)
+#define MCF_GPT_GMS_GPIO_OUTLO               (0x20)
+#define MCF_GPT_GMS_GPIO_OUTHI               (0x30)
+#define MCF_GPT_GMS_IEN                      (0x100)
+#define MCF_GPT_GMS_OD                       (0x200)
+#define MCF_GPT_GMS_SC                       (0x400)
+#define MCF_GPT_GMS_CE                       (0x1000)
+#define MCF_GPT_GMS_WDEN                     (0x8000)
+#define MCF_GPT_GMS_ICT(x)                   (((x)&0x3)<<0x10)
+#define MCF_GPT_GMS_ICT_ANY                  (0)
+#define MCF_GPT_GMS_ICT_RISE                 (0x10000)
+#define MCF_GPT_GMS_ICT_FALL                 (0x20000)
+#define MCF_GPT_GMS_ICT_PULSE                (0x30000)
+#define MCF_GPT_GMS_OCT(x)                   (((x)&0x3)<<0x14)
+#define MCF_GPT_GMS_OCT_FRCLOW               (0)
+#define MCF_GPT_GMS_OCT_PULSEHI              (0x100000)
+#define MCF_GPT_GMS_OCT_PULSELO              (0x200000)
+#define MCF_GPT_GMS_OCT_TOGGLE               (0x300000)
+#define MCF_GPT_GMS_OCPW(x)                  (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_GPT_GCIR */
+#define MCF_GPT_GCIR_CNT(x)                  (((x)&0xFFFF)<<0)
+#define MCF_GPT_GCIR_PRE(x)                  (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_GPT_GPWM */
+#define MCF_GPT_GPWM_LOAD                    (0x1)
+#define MCF_GPT_GPWM_PWMOP                   (0x100)
+#define MCF_GPT_GPWM_WIDTH(x)                (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_GPT_GSR */
+#define MCF_GPT_GSR_CAPT                     (0x1)
+#define MCF_GPT_GSR_COMP                     (0x2)
+#define MCF_GPT_GSR_PWMP                     (0x4)
+#define MCF_GPT_GSR_TEXP                     (0x8)
+#define MCF_GPT_GSR_PIN                      (0x100)
+#define MCF_GPT_GSR_OVF(x)                   (((x)&0x7)<<0xC)
+#define MCF_GPT_GSR_CAPTURE(x)               (((x)&0xFFFF)<<0x10)
+
+
+#endif /* __MCF5475_GPT_H__ */

tos/vmem_test/include/MCF5475_I2C.h

@@ -0,0 +1,69 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_I2C_H__
+#define __MCF5475_I2C_H__
+
+
+/*********************************************************************
+*
+* I2C Module (I2C)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_I2C_I2ADR                        (*(volatile uint8_t *)(&_MBAR[0x8F00]))
+#define MCF_I2C_I2FDR                        (*(volatile uint8_t *)(&_MBAR[0x8F04]))
+#define MCF_I2C_I2CR                         (*(volatile uint8_t *)(&_MBAR[0x8F08]))
+#define MCF_I2C_I2SR                         (*(volatile uint8_t *)(&_MBAR[0x8F0C]))
+#define MCF_I2C_I2DR                         (*(volatile uint8_t *)(&_MBAR[0x8F10]))
+#define MCF_I2C_I2ICR                        (*(volatile uint8_t *)(&_MBAR[0x8F20]))
+
+
+
+/* Bit definitions and macros for MCF_I2C_I2ADR */
+#define MCF_I2C_I2ADR_ADR(x)                 (((x)&0x7F)<<0x1)
+
+/* Bit definitions and macros for MCF_I2C_I2FDR */
+#define MCF_I2C_I2FDR_IC(x)                  (((x)&0x3F)<<0)
+
+/* Bit definitions and macros for MCF_I2C_I2CR */
+#define MCF_I2C_I2CR_RSTA                    (0x4)
+#define MCF_I2C_I2CR_TXAK                    (0x8)
+#define MCF_I2C_I2CR_MTX                     (0x10)
+#define MCF_I2C_I2CR_MSTA                    (0x20)
+#define MCF_I2C_I2CR_IIEN                    (0x40)
+#define MCF_I2C_I2CR_IEN                     (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2SR */
+#define MCF_I2C_I2SR_RXAK                    (0x1)
+#define MCF_I2C_I2SR_IIF                     (0x2)
+#define MCF_I2C_I2SR_SRW                     (0x4)
+#define MCF_I2C_I2SR_IAL                     (0x10)
+#define MCF_I2C_I2SR_IBB                     (0x20)
+#define MCF_I2C_I2SR_IAAS                    (0x40)
+#define MCF_I2C_I2SR_ICF                     (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2DR */
+#define MCF_I2C_I2DR_DATA(x)                 (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_I2C_I2ICR */
+#define MCF_I2C_I2ICR_IE                     (0x1)
+#define MCF_I2C_I2ICR_RE                     (0x2)
+#define MCF_I2C_I2ICR_TE                     (0x4)
+#define MCF_I2C_I2ICR_BNBE                   (0x8)
+
+
+#endif /* __MCF5475_I2C_H__ */

tos/vmem_test/include/MCF5475_INTC.h

@@ -0,0 +1,331 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_INTC_H__
+#define __MCF5475_INTC_H__
+
+
+/*********************************************************************
+*
+* Interrupt Controller (INTC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_INTC_IPRH                        (*(volatile uint32_t*)(&_MBAR[0x700]))
+#define MCF_INTC_IPRL                        (*(volatile uint32_t*)(&_MBAR[0x704]))
+#define MCF_INTC_IMRH                        (*(volatile uint32_t*)(&_MBAR[0x708]))
+#define MCF_INTC_IMRL                        (*(volatile uint32_t*)(&_MBAR[0x70C]))
+#define MCF_INTC_INTFRCH                     (*(volatile uint32_t*)(&_MBAR[0x710]))
+#define MCF_INTC_INTFRCL                     (*(volatile uint32_t*)(&_MBAR[0x714]))
+#define MCF_INTC_IRLR                        (*(volatile uint8_t *)(&_MBAR[0x718]))
+#define MCF_INTC_IACKLPR                     (*(volatile uint8_t *)(&_MBAR[0x719]))
+#define MCF_INTC_ICR01                       (*(volatile uint8_t *)(&_MBAR[0x741]))
+#define MCF_INTC_ICR02                       (*(volatile uint8_t *)(&_MBAR[0x742]))
+#define MCF_INTC_ICR03                       (*(volatile uint8_t *)(&_MBAR[0x743]))
+#define MCF_INTC_ICR04                       (*(volatile uint8_t *)(&_MBAR[0x744]))
+#define MCF_INTC_ICR05                       (*(volatile uint8_t *)(&_MBAR[0x745]))
+#define MCF_INTC_ICR06                       (*(volatile uint8_t *)(&_MBAR[0x746]))
+#define MCF_INTC_ICR07                       (*(volatile uint8_t *)(&_MBAR[0x747]))
+#define MCF_INTC_ICR08                       (*(volatile uint8_t *)(&_MBAR[0x748]))
+#define MCF_INTC_ICR09                       (*(volatile uint8_t *)(&_MBAR[0x749]))
+#define MCF_INTC_ICR10                       (*(volatile uint8_t *)(&_MBAR[0x74A]))
+#define MCF_INTC_ICR11                       (*(volatile uint8_t *)(&_MBAR[0x74B]))
+#define MCF_INTC_ICR12                       (*(volatile uint8_t *)(&_MBAR[0x74C]))
+#define MCF_INTC_ICR13                       (*(volatile uint8_t *)(&_MBAR[0x74D]))
+#define MCF_INTC_ICR14                       (*(volatile uint8_t *)(&_MBAR[0x74E]))
+#define MCF_INTC_ICR15                       (*(volatile uint8_t *)(&_MBAR[0x74F]))
+#define MCF_INTC_ICR16                       (*(volatile uint8_t *)(&_MBAR[0x750]))
+#define MCF_INTC_ICR17                       (*(volatile uint8_t *)(&_MBAR[0x751]))
+#define MCF_INTC_ICR18                       (*(volatile uint8_t *)(&_MBAR[0x752]))
+#define MCF_INTC_ICR19                       (*(volatile uint8_t *)(&_MBAR[0x753]))
+#define MCF_INTC_ICR20                       (*(volatile uint8_t *)(&_MBAR[0x754]))
+#define MCF_INTC_ICR21                       (*(volatile uint8_t *)(&_MBAR[0x755]))
+#define MCF_INTC_ICR22                       (*(volatile uint8_t *)(&_MBAR[0x756]))
+#define MCF_INTC_ICR23                       (*(volatile uint8_t *)(&_MBAR[0x757]))
+#define MCF_INTC_ICR24                       (*(volatile uint8_t *)(&_MBAR[0x758]))
+#define MCF_INTC_ICR25                       (*(volatile uint8_t *)(&_MBAR[0x759]))
+#define MCF_INTC_ICR26                       (*(volatile uint8_t *)(&_MBAR[0x75A]))
+#define MCF_INTC_ICR27                       (*(volatile uint8_t *)(&_MBAR[0x75B]))
+#define MCF_INTC_ICR28                       (*(volatile uint8_t *)(&_MBAR[0x75C]))
+#define MCF_INTC_ICR29                       (*(volatile uint8_t *)(&_MBAR[0x75D]))
+#define MCF_INTC_ICR30                       (*(volatile uint8_t *)(&_MBAR[0x75E]))
+#define MCF_INTC_ICR31                       (*(volatile uint8_t *)(&_MBAR[0x75F]))
+#define MCF_INTC_ICR32                       (*(volatile uint8_t *)(&_MBAR[0x760]))
+#define MCF_INTC_ICR33                       (*(volatile uint8_t *)(&_MBAR[0x761]))
+#define MCF_INTC_ICR34                       (*(volatile uint8_t *)(&_MBAR[0x762]))
+#define MCF_INTC_ICR35                       (*(volatile uint8_t *)(&_MBAR[0x763]))
+#define MCF_INTC_ICR36                       (*(volatile uint8_t *)(&_MBAR[0x764]))
+#define MCF_INTC_ICR37                       (*(volatile uint8_t *)(&_MBAR[0x765]))
+#define MCF_INTC_ICR38                       (*(volatile uint8_t *)(&_MBAR[0x766]))
+#define MCF_INTC_ICR39                       (*(volatile uint8_t *)(&_MBAR[0x767]))
+#define MCF_INTC_ICR40                       (*(volatile uint8_t *)(&_MBAR[0x768]))
+#define MCF_INTC_ICR41                       (*(volatile uint8_t *)(&_MBAR[0x769]))
+#define MCF_INTC_ICR42                       (*(volatile uint8_t *)(&_MBAR[0x76A]))
+#define MCF_INTC_ICR43                       (*(volatile uint8_t *)(&_MBAR[0x76B]))
+#define MCF_INTC_ICR44                       (*(volatile uint8_t *)(&_MBAR[0x76C]))
+#define MCF_INTC_ICR45                       (*(volatile uint8_t *)(&_MBAR[0x76D]))
+#define MCF_INTC_ICR46                       (*(volatile uint8_t *)(&_MBAR[0x76E]))
+#define MCF_INTC_ICR47                       (*(volatile uint8_t *)(&_MBAR[0x76F]))
+#define MCF_INTC_ICR48                       (*(volatile uint8_t *)(&_MBAR[0x770]))
+#define MCF_INTC_ICR49                       (*(volatile uint8_t *)(&_MBAR[0x771]))
+#define MCF_INTC_ICR50                       (*(volatile uint8_t *)(&_MBAR[0x772]))
+#define MCF_INTC_ICR51                       (*(volatile uint8_t *)(&_MBAR[0x773]))
+#define MCF_INTC_ICR52                       (*(volatile uint8_t *)(&_MBAR[0x774]))
+#define MCF_INTC_ICR53                       (*(volatile uint8_t *)(&_MBAR[0x775]))
+#define MCF_INTC_ICR54                       (*(volatile uint8_t *)(&_MBAR[0x776]))
+#define MCF_INTC_ICR55                       (*(volatile uint8_t *)(&_MBAR[0x777]))
+#define MCF_INTC_ICR56                       (*(volatile uint8_t *)(&_MBAR[0x778]))
+#define MCF_INTC_ICR57                       (*(volatile uint8_t *)(&_MBAR[0x779]))
+#define MCF_INTC_ICR58                       (*(volatile uint8_t *)(&_MBAR[0x77A]))
+#define MCF_INTC_ICR59                       (*(volatile uint8_t *)(&_MBAR[0x77B]))
+#define MCF_INTC_ICR60                       (*(volatile uint8_t *)(&_MBAR[0x77C]))
+#define MCF_INTC_ICR61                       (*(volatile uint8_t *)(&_MBAR[0x77D]))
+#define MCF_INTC_ICR62                       (*(volatile uint8_t *)(&_MBAR[0x77E]))
+#define MCF_INTC_ICR63                       (*(volatile uint8_t *)(&_MBAR[0x77F]))
+#define MCF_INTC_SWIACK                      (*(volatile uint8_t *)(&_MBAR[0x7E0]))
+#define MCF_INTC_L1IACK                      (*(volatile uint8_t *)(&_MBAR[0x7E4]))
+#define MCF_INTC_L2IACK                      (*(volatile uint8_t *)(&_MBAR[0x7E8]))
+#define MCF_INTC_L3IACK                      (*(volatile uint8_t *)(&_MBAR[0x7EC]))
+#define MCF_INTC_L4IACK                      (*(volatile uint8_t *)(&_MBAR[0x7F0]))
+#define MCF_INTC_L5IACK                      (*(volatile uint8_t *)(&_MBAR[0x7F4]))
+#define MCF_INTC_L6IACK                      (*(volatile uint8_t *)(&_MBAR[0x7F8]))
+#define MCF_INTC_L7IACK                      (*(volatile uint8_t *)(&_MBAR[0x7FC]))
+#define MCF_INTC_ICR(x)                      (*(volatile uint8_t *)(&_MBAR[0x741 + ((x-1)*0x1)]))
+#define MCF_INTC_LIACK(x)                    (*(volatile uint8_t *)(&_MBAR[0x7E4 + ((x-1)*0x4)]))
+
+
+
+/* Bit definitions and macros for MCF_INTC_IPRH */
+#define MCF_INTC_IPRH_INT32                  (0x1)
+#define MCF_INTC_IPRH_INT33                  (0x2)
+#define MCF_INTC_IPRH_INT34                  (0x4)
+#define MCF_INTC_IPRH_INT35                  (0x8)
+#define MCF_INTC_IPRH_INT36                  (0x10)
+#define MCF_INTC_IPRH_INT37                  (0x20)
+#define MCF_INTC_IPRH_INT38                  (0x40)
+#define MCF_INTC_IPRH_INT39                  (0x80)
+#define MCF_INTC_IPRH_INT40                  (0x100)
+#define MCF_INTC_IPRH_INT41                  (0x200)
+#define MCF_INTC_IPRH_INT42                  (0x400)
+#define MCF_INTC_IPRH_INT43                  (0x800)
+#define MCF_INTC_IPRH_INT44                  (0x1000)
+#define MCF_INTC_IPRH_INT45                  (0x2000)
+#define MCF_INTC_IPRH_INT46                  (0x4000)
+#define MCF_INTC_IPRH_INT47                  (0x8000)
+#define MCF_INTC_IPRH_INT48                  (0x10000)
+#define MCF_INTC_IPRH_INT49                  (0x20000)
+#define MCF_INTC_IPRH_INT50                  (0x40000)
+#define MCF_INTC_IPRH_INT51                  (0x80000)
+#define MCF_INTC_IPRH_INT52                  (0x100000)
+#define MCF_INTC_IPRH_INT53                  (0x200000)
+#define MCF_INTC_IPRH_INT54                  (0x400000)
+#define MCF_INTC_IPRH_INT55                  (0x800000)
+#define MCF_INTC_IPRH_INT56                  (0x1000000)
+#define MCF_INTC_IPRH_INT57                  (0x2000000)
+#define MCF_INTC_IPRH_INT58                  (0x4000000)
+#define MCF_INTC_IPRH_INT59                  (0x8000000)
+#define MCF_INTC_IPRH_INT60                  (0x10000000)
+#define MCF_INTC_IPRH_INT61                  (0x20000000)
+#define MCF_INTC_IPRH_INT62                  (0x40000000)
+#define MCF_INTC_IPRH_INT63                  (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IPRL */
+#define MCF_INTC_IPRL_INT1                   (0x2)
+#define MCF_INTC_IPRL_INT2                   (0x4)
+#define MCF_INTC_IPRL_INT3                   (0x8)
+#define MCF_INTC_IPRL_INT4                   (0x10)
+#define MCF_INTC_IPRL_INT5                   (0x20)
+#define MCF_INTC_IPRL_INT6                   (0x40)
+#define MCF_INTC_IPRL_INT7                   (0x80)
+#define MCF_INTC_IPRL_INT8                   (0x100)
+#define MCF_INTC_IPRL_INT9                   (0x200)
+#define MCF_INTC_IPRL_INT10                  (0x400)
+#define MCF_INTC_IPRL_INT11                  (0x800)
+#define MCF_INTC_IPRL_INT12                  (0x1000)
+#define MCF_INTC_IPRL_INT13                  (0x2000)
+#define MCF_INTC_IPRL_INT14                  (0x4000)
+#define MCF_INTC_IPRL_INT15                  (0x8000)
+#define MCF_INTC_IPRL_INT16                  (0x10000)
+#define MCF_INTC_IPRL_INT17                  (0x20000)
+#define MCF_INTC_IPRL_INT18                  (0x40000)
+#define MCF_INTC_IPRL_INT19                  (0x80000)
+#define MCF_INTC_IPRL_INT20                  (0x100000)
+#define MCF_INTC_IPRL_INT21                  (0x200000)
+#define MCF_INTC_IPRL_INT22                  (0x400000)
+#define MCF_INTC_IPRL_INT23                  (0x800000)
+#define MCF_INTC_IPRL_INT24                  (0x1000000)
+#define MCF_INTC_IPRL_INT25                  (0x2000000)
+#define MCF_INTC_IPRL_INT26                  (0x4000000)
+#define MCF_INTC_IPRL_INT27                  (0x8000000)
+#define MCF_INTC_IPRL_INT28                  (0x10000000)
+#define MCF_INTC_IPRL_INT29                  (0x20000000)
+#define MCF_INTC_IPRL_INT30                  (0x40000000)
+#define MCF_INTC_IPRL_INT31                  (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRH */
+#define MCF_INTC_IMRH_INT_MASK32             (0x1)
+#define MCF_INTC_IMRH_INT_MASK33             (0x2)
+#define MCF_INTC_IMRH_INT_MASK34             (0x4)
+#define MCF_INTC_IMRH_INT_MASK35             (0x8)
+#define MCF_INTC_IMRH_INT_MASK36             (0x10)
+#define MCF_INTC_IMRH_INT_MASK37             (0x20)
+#define MCF_INTC_IMRH_INT_MASK38             (0x40)
+#define MCF_INTC_IMRH_INT_MASK39             (0x80)
+#define MCF_INTC_IMRH_INT_MASK40             (0x100)
+#define MCF_INTC_IMRH_INT_MASK41             (0x200)
+#define MCF_INTC_IMRH_INT_MASK42             (0x400)
+#define MCF_INTC_IMRH_INT_MASK43             (0x800)
+#define MCF_INTC_IMRH_INT_MASK44             (0x1000)
+#define MCF_INTC_IMRH_INT_MASK45             (0x2000)
+#define MCF_INTC_IMRH_INT_MASK46             (0x4000)
+#define MCF_INTC_IMRH_INT_MASK47             (0x8000)
+#define MCF_INTC_IMRH_INT_MASK48             (0x10000)
+#define MCF_INTC_IMRH_INT_MASK49             (0x20000)
+#define MCF_INTC_IMRH_INT_MASK50             (0x40000)
+#define MCF_INTC_IMRH_INT_MASK51             (0x80000)
+#define MCF_INTC_IMRH_INT_MASK52             (0x100000)
+#define MCF_INTC_IMRH_INT_MASK53             (0x200000)
+#define MCF_INTC_IMRH_INT_MASK54             (0x400000)
+#define MCF_INTC_IMRH_INT_MASK55             (0x800000)
+#define MCF_INTC_IMRH_INT_MASK56             (0x1000000)
+#define MCF_INTC_IMRH_INT_MASK57             (0x2000000)
+#define MCF_INTC_IMRH_INT_MASK58             (0x4000000)
+#define MCF_INTC_IMRH_INT_MASK59             (0x8000000)
+#define MCF_INTC_IMRH_INT_MASK60             (0x10000000)
+#define MCF_INTC_IMRH_INT_MASK61             (0x20000000)
+#define MCF_INTC_IMRH_INT_MASK62             (0x40000000)
+#define MCF_INTC_IMRH_INT_MASK63             (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRL */
+#define MCF_INTC_IMRL_MASKALL                (0x1)
+#define MCF_INTC_IMRL_INT_MASK1              (0x2)
+#define MCF_INTC_IMRL_INT_MASK2              (0x4)
+#define MCF_INTC_IMRL_INT_MASK3              (0x8)
+#define MCF_INTC_IMRL_INT_MASK4              (0x10)
+#define MCF_INTC_IMRL_INT_MASK5              (0x20)
+#define MCF_INTC_IMRL_INT_MASK6              (0x40)
+#define MCF_INTC_IMRL_INT_MASK7              (0x80)
+#define MCF_INTC_IMRL_INT_MASK8              (0x100)
+#define MCF_INTC_IMRL_INT_MASK9              (0x200)
+#define MCF_INTC_IMRL_INT_MASK10             (0x400)
+#define MCF_INTC_IMRL_INT_MASK11             (0x800)
+#define MCF_INTC_IMRL_INT_MASK12             (0x1000)
+#define MCF_INTC_IMRL_INT_MASK13             (0x2000)
+#define MCF_INTC_IMRL_INT_MASK14             (0x4000)
+#define MCF_INTC_IMRL_INT_MASK15             (0x8000)
+#define MCF_INTC_IMRL_INT_MASK16             (0x10000)
+#define MCF_INTC_IMRL_INT_MASK17             (0x20000)
+#define MCF_INTC_IMRL_INT_MASK18             (0x40000)
+#define MCF_INTC_IMRL_INT_MASK19             (0x80000)
+#define MCF_INTC_IMRL_INT_MASK20             (0x100000)
+#define MCF_INTC_IMRL_INT_MASK21             (0x200000)
+#define MCF_INTC_IMRL_INT_MASK22             (0x400000)
+#define MCF_INTC_IMRL_INT_MASK23             (0x800000)
+#define MCF_INTC_IMRL_INT_MASK24             (0x1000000)
+#define MCF_INTC_IMRL_INT_MASK25             (0x2000000)
+#define MCF_INTC_IMRL_INT_MASK26             (0x4000000)
+#define MCF_INTC_IMRL_INT_MASK27             (0x8000000)
+#define MCF_INTC_IMRL_INT_MASK28             (0x10000000)
+#define MCF_INTC_IMRL_INT_MASK29             (0x20000000)
+#define MCF_INTC_IMRL_INT_MASK30             (0x40000000)
+#define MCF_INTC_IMRL_INT_MASK31             (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCH */
+#define MCF_INTC_INTFRCH_INTFRC32            (0x1)
+#define MCF_INTC_INTFRCH_INTFRC33            (0x2)
+#define MCF_INTC_INTFRCH_INTFRC34            (0x4)
+#define MCF_INTC_INTFRCH_INTFRC35            (0x8)
+#define MCF_INTC_INTFRCH_INTFRC36            (0x10)
+#define MCF_INTC_INTFRCH_INTFRC37            (0x20)
+#define MCF_INTC_INTFRCH_INTFRC38            (0x40)
+#define MCF_INTC_INTFRCH_INTFRC39            (0x80)
+#define MCF_INTC_INTFRCH_INTFRC40            (0x100)
+#define MCF_INTC_INTFRCH_INTFRC41            (0x200)
+#define MCF_INTC_INTFRCH_INTFRC42            (0x400)
+#define MCF_INTC_INTFRCH_INTFRC43            (0x800)
+#define MCF_INTC_INTFRCH_INTFRC44            (0x1000)
+#define MCF_INTC_INTFRCH_INTFRC45            (0x2000)
+#define MCF_INTC_INTFRCH_INTFRC46            (0x4000)
+#define MCF_INTC_INTFRCH_INTFRC47            (0x8000)
+#define MCF_INTC_INTFRCH_INTFRC48            (0x10000)
+#define MCF_INTC_INTFRCH_INTFRC49            (0x20000)
+#define MCF_INTC_INTFRCH_INTFRC50            (0x40000)
+#define MCF_INTC_INTFRCH_INTFRC51            (0x80000)
+#define MCF_INTC_INTFRCH_INTFRC52            (0x100000)
+#define MCF_INTC_INTFRCH_INTFRC53            (0x200000)
+#define MCF_INTC_INTFRCH_INTFRC54            (0x400000)
+#define MCF_INTC_INTFRCH_INTFRC55            (0x800000)
+#define MCF_INTC_INTFRCH_INTFRC56            (0x1000000)
+#define MCF_INTC_INTFRCH_INTFRC57            (0x2000000)
+#define MCF_INTC_INTFRCH_INTFRC58            (0x4000000)
+#define MCF_INTC_INTFRCH_INTFRC59            (0x8000000)
+#define MCF_INTC_INTFRCH_INTFRC60            (0x10000000)
+#define MCF_INTC_INTFRCH_INTFRC61            (0x20000000)
+#define MCF_INTC_INTFRCH_INTFRC62            (0x40000000)
+#define MCF_INTC_INTFRCH_INTFRC63            (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCL */
+#define MCF_INTC_INTFRCL_INTFRC1             (0x2)
+#define MCF_INTC_INTFRCL_INTFRC2             (0x4)
+#define MCF_INTC_INTFRCL_INTFRC3             (0x8)
+#define MCF_INTC_INTFRCL_INTFRC4             (0x10)
+#define MCF_INTC_INTFRCL_INTFRC5             (0x20)
+#define MCF_INTC_INTFRCL_INTFRC6             (0x40)
+#define MCF_INTC_INTFRCL_INTFRC7             (0x80)
+#define MCF_INTC_INTFRCL_INTFRC8             (0x100)
+#define MCF_INTC_INTFRCL_INTFRC9             (0x200)
+#define MCF_INTC_INTFRCL_INTFRC10            (0x400)
+#define MCF_INTC_INTFRCL_INTFRC11            (0x800)
+#define MCF_INTC_INTFRCL_INTFRC12            (0x1000)
+#define MCF_INTC_INTFRCL_INTFRC13            (0x2000)
+#define MCF_INTC_INTFRCL_INTFRC14            (0x4000)
+#define MCF_INTC_INTFRCL_INTFRC15            (0x8000)
+#define MCF_INTC_INTFRCL_INTFRC16            (0x10000)
+#define MCF_INTC_INTFRCL_INTFRC17            (0x20000)
+#define MCF_INTC_INTFRCL_INTFRC18            (0x40000)
+#define MCF_INTC_INTFRCL_INTFRC19            (0x80000)
+#define MCF_INTC_INTFRCL_INTFRC20            (0x100000)
+#define MCF_INTC_INTFRCL_INTFRC21            (0x200000)
+#define MCF_INTC_INTFRCL_INTFRC22            (0x400000)
+#define MCF_INTC_INTFRCL_INTFRC23            (0x800000)
+#define MCF_INTC_INTFRCL_INTFRC24            (0x1000000)
+#define MCF_INTC_INTFRCL_INTFRC25            (0x2000000)
+#define MCF_INTC_INTFRCL_INTFRC26            (0x4000000)
+#define MCF_INTC_INTFRCL_INTFRC27            (0x8000000)
+#define MCF_INTC_INTFRCL_INTFRC28            (0x10000000)
+#define MCF_INTC_INTFRCL_INTFRC29            (0x20000000)
+#define MCF_INTC_INTFRCL_INTFRC30            (0x40000000)
+#define MCF_INTC_INTFRCL_INTFRC31            (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IRLR */
+#define MCF_INTC_IRLR_IRQ(x)                 (((x)&0x7F)<<0x1)
+
+/* Bit definitions and macros for MCF_INTC_IACKLPR */
+#define MCF_INTC_IACKLPR_PRI(x)              (((x)&0xF)<<0)
+#define MCF_INTC_IACKLPR_LEVEL(x)            (((x)&0x7)<<0x4)
+
+/* Bit definitions and macros for MCF_INTC_ICR */
+#define MCF_INTC_ICR_IP(x)                   (((x)&0x7)<<0)
+#define MCF_INTC_ICR_IL(x)                   (((x)&0x7)<<0x3)
+
+/* Bit definitions and macros for MCF_INTC_SWIACK */
+#define MCF_INTC_SWIACK_VECTOR(x)            (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_INTC_LIACK */
+#define MCF_INTC_LIACK_VECTOR(x)             (((x)&0xFF)<<0)
+
+
+#endif /* __MCF5475_INTC_H__ */

tos/vmem_test/include/MCF5475_MMU.h

@@ -0,0 +1,79 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_MMU_H__
+#define __MCF5475_MMU_H__
+
+
+/*********************************************************************
+*
+* Memory Management Unit (MMU)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+
+/* note the uint32_t_a - this is to avoid gcc warnings about pointer aliasing */
+#define MCF_MMU_MMUCR                        (*(volatile uint32_t_a*)(&_MMUBAR[0]))
+#define MCF_MMU_MMUOR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x4]))
+#define MCF_MMU_MMUSR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x8]))
+#define MCF_MMU_MMUAR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x10]))
+#define MCF_MMU_MMUTR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x14]))
+#define MCF_MMU_MMUDR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x18]))
+
+
+/* Bit definitions and macros for MCF_MMU_MMUCR */
+#define MCF_MMU_MMUCR_EN                     (0x1)
+#define MCF_MMU_MMUCR_ASM                    (0x2)
+
+/* Bit definitions and macros for MCF_MMU_MMUOR */
+#define MCF_MMU_MMUOR_UAA                    (0x1)
+#define MCF_MMU_MMUOR_ACC                    (0x2)
+#define MCF_MMU_MMUOR_RW                     (0x4)
+#define MCF_MMU_MMUOR_ADR                    (0x8)
+#define MCF_MMU_MMUOR_ITLB                   (0x10)
+#define MCF_MMU_MMUOR_CAS                    (0x20)
+#define MCF_MMU_MMUOR_CNL                    (0x40)
+#define MCF_MMU_MMUOR_CA                     (0x80)
+#define MCF_MMU_MMUOR_STLB                   (0x100)
+#define MCF_MMU_MMUOR_AA(x)                  (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_MMU_MMUSR */
+#define MCF_MMU_MMUSR_HIT                    (0x2)
+#define MCF_MMU_MMUSR_WF                     (0x8)
+#define MCF_MMU_MMUSR_RF                     (0x10)
+#define MCF_MMU_MMUSR_SPF                    (0x20)
+
+/* Bit definitions and macros for MCF_MMU_MMUAR */
+#define MCF_MMU_MMUAR_FA(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_MMU_MMUTR */
+#define MCF_MMU_MMUTR_V                      (0x1)
+#define MCF_MMU_MMUTR_SG                     (0x2)
+#define MCF_MMU_MMUTR_ID(x)                  (((x)&0xFF)<<0x2)
+#define MCF_MMU_MMUTR_VA(x)                  (((x)&0x3FFFFF)<<0xA)
+
+/* Bit definitions and macros for MCF_MMU_MMUDR */
+#define MCF_MMU_MMUDR_LK                     (0x2)
+#define MCF_MMU_MMUDR_X                      (0x4)
+#define MCF_MMU_MMUDR_W                      (0x8)
+#define MCF_MMU_MMUDR_R                      (0x10)
+#define MCF_MMU_MMUDR_SP                     (0x20)
+#define MCF_MMU_MMUDR_CM(x)                  (((x)&0x3)<<0x6)
+#define MCF_MMU_MMUDR_SZ(x)                  (((x)&0x3)<<0x8)
+#define MCF_MMU_MMUDR_PA(x)                  (((x)&0x3FFFFF)<<0xA)
+
+
+#endif /* __MCF5475_MMU_H__ */

tos/vmem_test/include/MCF5475_PAD.h

@@ -0,0 +1,233 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PAD_H__
+#define __MCF5475_PAD_H__
+
+
+/*********************************************************************
+*
+* Common GPIO
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PAD_PAR_FBCTL                    (*(volatile uint16_t*)(&_MBAR[0xA40]))
+#define MCF_PAD_PAR_FBCS                     (*(volatile uint8_t *)(&_MBAR[0xA42]))
+#define MCF_PAD_PAR_DMA                      (*(volatile uint8_t *)(&_MBAR[0xA43]))
+#define MCF_PAD_PAR_FECI2CIRQ                (*(volatile uint16_t*)(&_MBAR[0xA44]))
+#define MCF_PAD_PAR_PCIBG                    (*(volatile uint16_t*)(&_MBAR[0xA48]))
+#define MCF_PAD_PAR_PCIBR                    (*(volatile uint16_t*)(&_MBAR[0xA4A]))
+#define MCF_PAD_PAR_PSC3                     (*(volatile uint8_t *)(&_MBAR[0xA4C]))
+#define MCF_PAD_PAR_PSC2                     (*(volatile uint8_t *)(&_MBAR[0xA4D]))
+#define MCF_PAD_PAR_PSC1                     (*(volatile uint8_t *)(&_MBAR[0xA4E]))
+#define MCF_PAD_PAR_PSC0                     (*(volatile uint8_t *)(&_MBAR[0xA4F]))
+#define MCF_PAD_PAR_DSPI                     (*(volatile uint16_t*)(&_MBAR[0xA50]))
+#define MCF_PAD_PAR_TIMER                    (*(volatile uint8_t *)(&_MBAR[0xA52]))
+
+
+/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */
+#define MCF_PAD_PAR_FBCTL_PAR_ALE(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_GPIO       (0)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_TBST       (0x2)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_ALE        (0x3)
+#define MCF_PAD_PAR_FBCTL_PAR_TA             (0x4)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_GPIO       (0)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_TBST       (0x20)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_RW         (0x30)
+#define MCF_PAD_PAR_FBCTL_PAR_OE             (0x40)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE0           (0x100)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE1           (0x400)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE2           (0x1000)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE3           (0x4000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_FBCS */
+#define MCF_PAD_PAR_FBCS_PAR_CS1             (0x2)
+#define MCF_PAD_PAR_FBCS_PAR_CS2             (0x4)
+#define MCF_PAD_PAR_FBCS_PAR_CS3             (0x8)
+#define MCF_PAD_PAR_FBCS_PAR_CS4             (0x10)
+#define MCF_PAD_PAR_FBCS_PAR_CS5             (0x20)
+
+/* Bit definitions and macros for MCF_PAD_PAR_DMA */
+#define MCF_PAD_PAR_DMA_PAR_DREQ0(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_TIN0       (0x2)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0      (0x3)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1(x)         (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_IRQ1       (0x4)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_TIN1       (0x8)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1      (0xC)
+#define MCF_PAD_PAR_DMA_PAR_DACK0(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_TOUT0      (0x20)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_DACK0      (0x30)
+#define MCF_PAD_PAR_DMA_PAR_DACK1(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_TOUT1      (0x80)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_DACK1      (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_FECI2CIRQ */
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5       (0x1)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6       (0x2)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_SCL        (0x4)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_SDA        (0x8)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC(x)   (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_SCL  (0x80)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC (0xC0)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO(x)  (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x200)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO (0x300)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII      (0x400)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E17        (0x800)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC      (0x1000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO     (0x2000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII      (0x4000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E07        (0x8000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PCIBG */
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0(x)      (((x)&0x3)<<0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_TOUT0   (0x2)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0  (0x3)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1(x)      (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_TOUT1   (0x8)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1  (0xC)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2(x)      (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_TOUT2   (0x20)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2  (0x30)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3(x)      (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_TOUT3   (0x80)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3  (0xC0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4(x)      (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST    (0x200)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4  (0x300)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PCIBR */
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0(x)      (((x)&0x3)<<0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_TIN0    (0x2)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0  (0x3)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1(x)      (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_TIN1    (0x8)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1  (0xC)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2(x)      (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_TIN2    (0x20)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2  (0x30)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3(x)      (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_TIN3    (0x80)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3  (0xC0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4(x)      (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4    (0x200)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4  (0x300)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC3 */
+#define MCF_PAD_PAR_PSC3_PAR_TXD3            (0x4)
+#define MCF_PAD_PAR_PSC3_PAR_RXD3            (0x8)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_GPIO       (0)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_RTS        (0x30)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_GPIO       (0)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC2 */
+#define MCF_PAD_PAR_PSC2_PAR_TXD2            (0x4)
+#define MCF_PAD_PAR_PSC2_PAR_RXD2            (0x8)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_GPIO       (0)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_RTS        (0x30)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_GPIO       (0)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC1 */
+#define MCF_PAD_PAR_PSC1_PAR_TXD1            (0x4)
+#define MCF_PAD_PAR_PSC1_PAR_RXD1            (0x8)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_GPIO       (0)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_RTS        (0x30)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_GPIO       (0)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC0 */
+#define MCF_PAD_PAR_PSC0_PAR_TXD0            (0x4)
+#define MCF_PAD_PAR_PSC0_PAR_RXD0            (0x8)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_GPIO       (0)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_RTS        (0x30)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_GPIO       (0)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_DSPI */
+#define MCF_PAD_PAR_DSPI_PAR_SOUT(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_GPIO       (0)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_TXD        (0x2)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT       (0x3)
+#define MCF_PAD_PAR_DSPI_PAR_SIN(x)          (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_RXD         (0x8)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_SIN         (0xC)
+#define MCF_PAD_PAR_DSPI_PAR_SCK(x)          (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_BCLK        (0x10)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_CTS         (0x20)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_SCK         (0x30)
+#define MCF_PAD_PAR_DSPI_PAR_CS0(x)          (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_FSYNC       (0x40)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_RTS         (0x80)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0     (0xC0)
+#define MCF_PAD_PAR_DSPI_PAR_CS2(x)          (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_TOUT2       (0x200)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2     (0x300)
+#define MCF_PAD_PAR_DSPI_PAR_CS3(x)          (((x)&0x3)<<0xA)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_TOUT3       (0x800)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3     (0xC00)
+#define MCF_PAD_PAR_DSPI_PAR_CS5             (0x1000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_TIMER */
+#define MCF_PAD_PAR_TIMER_PAR_TOUT2          (0x1)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2(x)        (((x)&0x3)<<0x1)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2      (0x4)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2_TIN2      (0x6)
+#define MCF_PAD_PAR_TIMER_PAR_TOUT3          (0x8)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3(x)        (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3      (0x20)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3_TIN3      (0x30)
+
+
+#endif /* __MCF5475_PAD_H__ */

tos/vmem_test/include/MCF5475_PCI.h

@@ -0,0 +1,376 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PCI_H__
+#define __MCF5475_PCI_H__
+
+
+/*********************************************************************
+*
+* PCI Bus Controller (PCI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PCI_PCIIDR                       (*(volatile uint32_t*)(&_MBAR[0xB00]))
+#define MCF_PCI_PCISCR                       (*(volatile uint32_t*)(&_MBAR[0xB04]))
+#define MCF_PCI_PCICCRIR                     (*(volatile uint32_t*)(&_MBAR[0xB08]))
+#define MCF_PCI_PCICR1                       (*(volatile uint32_t*)(&_MBAR[0xB0C]))
+#define MCF_PCI_PCIBAR0                      (*(volatile uint32_t*)(&_MBAR[0xB10]))
+#define MCF_PCI_PCIBAR1                      (*(volatile uint32_t*)(&_MBAR[0xB14]))
+#define MCF_PCI_PCICCPR                      (*(volatile uint32_t*)(&_MBAR[0xB28]))
+#define MCF_PCI_PCISID                       (*(volatile uint32_t*)(&_MBAR[0xB2C]))
+#define MCF_PCI_PCICR2                       (*(volatile uint32_t*)(&_MBAR[0xB3C]))
+#define MCF_PCI_PCIGSCR                      (*(volatile uint32_t*)(&_MBAR[0xB60]))
+#define MCF_PCI_PCITBATR0                    (*(volatile uint32_t*)(&_MBAR[0xB64]))
+#define MCF_PCI_PCITBATR1                    (*(volatile uint32_t*)(&_MBAR[0xB68]))
+#define MCF_PCI_PCITCR                       (*(volatile uint32_t*)(&_MBAR[0xB6C]))
+#define MCF_PCI_PCIIW0BTAR                   (*(volatile uint32_t*)(&_MBAR[0xB70]))
+#define MCF_PCI_PCIIW1BTAR                   (*(volatile uint32_t*)(&_MBAR[0xB74]))
+#define MCF_PCI_PCIIW2BTAR                   (*(volatile uint32_t*)(&_MBAR[0xB78]))
+#define MCF_PCI_PCIIWCR                      (*(volatile uint32_t*)(&_MBAR[0xB80]))
+#define MCF_PCI_PCIICR                       (*(volatile uint32_t*)(&_MBAR[0xB84]))
+#define MCF_PCI_PCIISR                       (*(volatile uint32_t*)(&_MBAR[0xB88]))
+#define MCF_PCI_PCICAR                       (*(volatile uint32_t*)(&_MBAR[0xBF8]))
+#define MCF_PCI_PCITPSR                      (*(volatile uint32_t*)(&_MBAR[0x8400]))
+#define MCF_PCI_PCITSAR                      (*(volatile uint32_t*)(&_MBAR[0x8404]))
+#define MCF_PCI_PCITTCR                      (*(volatile uint32_t*)(&_MBAR[0x8408]))
+#define MCF_PCI_PCITER                       (*(volatile uint32_t*)(&_MBAR[0x840C]))
+#define MCF_PCI_PCITNAR                      (*(volatile uint32_t*)(&_MBAR[0x8410]))
+#define MCF_PCI_PCITLWR                      (*(volatile uint32_t*)(&_MBAR[0x8414]))
+#define MCF_PCI_PCITDCR                      (*(volatile uint32_t*)(&_MBAR[0x8418]))
+#define MCF_PCI_PCITSR                       (*(volatile uint32_t*)(&_MBAR[0x841C]))
+#define MCF_PCI_PCITFDR                      (*(volatile uint32_t*)(&_MBAR[0x8440]))
+#define MCF_PCI_PCITFSR                      (*(volatile uint32_t*)(&_MBAR[0x8444]))
+#define MCF_PCI_PCITFCR                      (*(volatile uint32_t*)(&_MBAR[0x8448]))
+#define MCF_PCI_PCITFAR                      (*(volatile uint32_t*)(&_MBAR[0x844C]))
+#define MCF_PCI_PCITFRPR                     (*(volatile uint32_t*)(&_MBAR[0x8450]))
+#define MCF_PCI_PCITFWPR                     (*(volatile uint32_t*)(&_MBAR[0x8454]))
+#define MCF_PCI_PCIRPSR                      (*(volatile uint32_t*)(&_MBAR[0x8480]))
+#define MCF_PCI_PCIRSAR                      (*(volatile uint32_t*)(&_MBAR[0x8484]))
+#define MCF_PCI_PCIRTCR                      (*(volatile uint32_t*)(&_MBAR[0x8488]))
+#define MCF_PCI_PCIRER                       (*(volatile uint32_t*)(&_MBAR[0x848C]))
+#define MCF_PCI_PCIRNAR                      (*(volatile uint32_t*)(&_MBAR[0x8490]))
+#define MCF_PCI_PCIRDCR                      (*(volatile uint32_t*)(&_MBAR[0x8498]))
+#define MCF_PCI_PCIRSR                       (*(volatile uint32_t*)(&_MBAR[0x849C]))
+#define MCF_PCI_PCIRFDR                      (*(volatile uint32_t*)(&_MBAR[0x84C0]))
+#define MCF_PCI_PCIRFSR                      (*(volatile uint32_t*)(&_MBAR[0x84C4]))
+#define MCF_PCI_PCIRFCR                      (*(volatile uint32_t*)(&_MBAR[0x84C8]))
+#define MCF_PCI_PCIRFAR                      (*(volatile uint32_t*)(&_MBAR[0x84CC]))
+#define MCF_PCI_PCIRFRPR                     (*(volatile uint32_t*)(&_MBAR[0x84D0]))
+#define MCF_PCI_PCIRFWPR                     (*(volatile uint32_t*)(&_MBAR[0x84D4]))
+
+
+/* Bit definitions and macros for MCF_PCI_PCIIDR */
+#define MCF_PCI_PCIIDR_VENDORID(x)           (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCIIDR_DEVICEID(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCISCR */
+#define MCF_PCI_PCISCR_IO                    (0x1)
+#define MCF_PCI_PCISCR_M                     (0x2)
+#define MCF_PCI_PCISCR_B                     (0x4)
+#define MCF_PCI_PCISCR_SP                    (0x8)
+#define MCF_PCI_PCISCR_MW                    (0x10)
+#define MCF_PCI_PCISCR_V                     (0x20)
+#define MCF_PCI_PCISCR_PER                   (0x40)
+#define MCF_PCI_PCISCR_ST                    (0x80)
+#define MCF_PCI_PCISCR_S                     (0x100)
+#define MCF_PCI_PCISCR_F                     (0x200)
+#define MCF_PCI_PCISCR_C                     (0x100000)
+#define MCF_PCI_PCISCR_66M                   (0x200000)
+#define MCF_PCI_PCISCR_R                     (0x400000)
+#define MCF_PCI_PCISCR_FC                    (0x800000)
+#define MCF_PCI_PCISCR_DP                    (0x1000000)
+#define MCF_PCI_PCISCR_DT(x)                 (((x)&0x3)<<0x19)
+#define MCF_PCI_PCISCR_TS                    (0x8000000)
+#define MCF_PCI_PCISCR_TR                    (0x10000000)
+#define MCF_PCI_PCISCR_MA                    (0x20000000)
+#define MCF_PCI_PCISCR_SE                    (0x40000000)
+#define MCF_PCI_PCISCR_PE                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCICCRIR */
+#define MCF_PCI_PCICCRIR_REVISIONID(x)       (((x)&0xFF)<<0)
+#define MCF_PCI_PCICCRIR_CLASSCODE(x)        (((x)&0xFFFFFF)<<0x8)
+
+/* Bit definitions and macros for MCF_PCI_PCICR1 */
+#define MCF_PCI_PCICR1_CACHELINESIZE(x)      (((x)&0xFF)<<0)
+#define MCF_PCI_PCICR1_LATTIMER(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCICR1_HEADERTYPE(x)         (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICR1_BIST(x)               (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIBAR0 */
+#define MCF_PCI_PCIBAR0_IOM                  (0x1)
+#define MCF_PCI_PCIBAR0_RANGE(x)             (((x)&0x3)<<0x1)
+#define MCF_PCI_PCIBAR0_PREF                 (0x8)
+#define MCF_PCI_PCIBAR0_BAR0(x)              (((x)&0x3FFF)<<0x12)
+
+/* Bit definitions and macros for MCF_PCI_PCIBAR1 */
+#define MCF_PCI_PCIBAR1_IOM                  (0x1)
+#define MCF_PCI_PCIBAR1_RANGE(x)             (((x)&0x3)<<0x1)
+#define MCF_PCI_PCIBAR1_PREF                 (0x8)
+#define MCF_PCI_PCIBAR1_BAR1(x)              (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_PCI_PCICCPR */
+#define MCF_PCI_PCICCPR_PCICCP(x)            (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCISID */
+#define MCF_PCI_PCISID_VENDORID(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCICR2 */
+#define MCF_PCI_PCICR2_INTLINE(x)            (((x)&0xFF)<<0)
+#define MCF_PCI_PCICR2_INTPIN(x)             (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCICR2_MINGNT(x)             (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICR2_MAXLAT(x)             (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIGSCR */
+#define MCF_PCI_PCIGSCR_PR                   (0x1)
+#define MCF_PCI_PCIGSCR_SEE                  (0x1000)
+#define MCF_PCI_PCIGSCR_PEE                  (0x2000)
+#define MCF_PCI_PCIGSCR_CLKINRESERVED(x)     (((x)&0x7)<<0x10)
+#define MCF_PCI_PCIGSCR_XLB2CLKIN(x)         (((x)&0x7)<<0x18)
+#define MCF_PCI_PCIGSCR_SE                   (0x10000000)
+#define MCF_PCI_PCIGSCR_PE                   (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITBATR0 */
+#define MCF_PCI_PCITBATR0_EN                 (0x1)
+#define MCF_PCI_PCITBATR0_BAT0(x)            (((x)&0x3FFF)<<0x12)
+
+/* Bit definitions and macros for MCF_PCI_PCITBATR1 */
+#define MCF_PCI_PCITBATR1_EN                 (0x1)
+#define MCF_PCI_PCITBATR1_BAT1(x)            (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_PCI_PCITCR */
+#define MCF_PCI_PCITCR_P                     (0x10000)
+#define MCF_PCI_PCITCR_LD                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */
+#define MCF_PCI_PCIIW0BTAR_WTA0(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW0BTAR_WAM0(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW0BTAR_WBA0(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */
+#define MCF_PCI_PCIIW1BTAR_WTA1(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW1BTAR_WAM1(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW1BTAR_WBA1(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */
+#define MCF_PCI_PCIIW2BTAR_WTA2(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW2BTAR_WAM2(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW2BTAR_WBA2(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIWCR */
+#define MCF_PCI_PCIIWCR_WINCTRL2_E           (0x100)
+#define MCF_PCI_PCIIWCR_WINCTRL2_PRC(x)      (((x)&0x3)<<0x9)
+#define MCF_PCI_PCIIWCR_WINCTRL2_IOM         (0x800)
+#define MCF_PCI_PCIIWCR_WINCTRL1_E           (0x10000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_PRC(x)      (((x)&0x3)<<0x11)
+#define MCF_PCI_PCIIWCR_WINCTRL1_IOM         (0x80000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_E           (0x1000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_PRC(x)      (((x)&0x3)<<0x19)
+#define MCF_PCI_PCIIWCR_WINCTRL0_IOM         (0x8000000)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD     (0x100)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE   (0x300)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL    (0x500)
+#define MCF_PCI_PCIIWCR_WINCTRL2_IO          (0x900)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD     (0x10000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE   (0x30000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL    (0x50000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_IO          (0x90000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD     (0x1000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE   (0x3000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL    (0x5000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_IO          (0x9000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIICR */
+#define MCF_PCI_PCIICR_MAXRETRY(x)           (((x)&0xFF)<<0)
+#define MCF_PCI_PCIICR_TAE                   (0x1000000)
+#define MCF_PCI_PCIICR_IAE                   (0x2000000)
+#define MCF_PCI_PCIICR_REE                   (0x4000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIISR */
+#define MCF_PCI_PCIISR_TA                    (0x1000000)
+#define MCF_PCI_PCIISR_IA                    (0x2000000)
+#define MCF_PCI_PCIISR_RE                    (0x4000000)
+
+/* Bit definitions and macros for MCF_PCI_PCICAR */
+#define MCF_PCI_PCICAR_DWORD(x)              (((x)&0x3F)<<0x2)
+#define MCF_PCI_PCICAR_FUNCNUM(x)            (((x)&0x7)<<0x8)
+#define MCF_PCI_PCICAR_DEVNUM(x)             (((x)&0x1F)<<0xB)
+#define MCF_PCI_PCICAR_BUSNUM(x)             (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICAR_E                     (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITPSR */
+#define MCF_PCI_PCITPSR_PKTSIZE(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCITSAR */
+#define MCF_PCI_PCITSAR_STARTADD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITTCR */
+#define MCF_PCI_PCITTCR_DI                   (0x1)
+#define MCF_PCI_PCITTCR_W                    (0x10)
+#define MCF_PCI_PCITTCR_MAXBEATS(x)          (((x)&0x7)<<0x8)
+#define MCF_PCI_PCITTCR_MAXRETRY(x)          (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCITTCR_PCICMD(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCITER */
+#define MCF_PCI_PCITER_NE                    (0x10000)
+#define MCF_PCI_PCITER_IAE                   (0x20000)
+#define MCF_PCI_PCITER_TAE                   (0x40000)
+#define MCF_PCI_PCITER_RE                    (0x80000)
+#define MCF_PCI_PCITER_SE                    (0x100000)
+#define MCF_PCI_PCITER_FEE                   (0x200000)
+#define MCF_PCI_PCITER_ME                    (0x1000000)
+#define MCF_PCI_PCITER_BE                    (0x8000000)
+#define MCF_PCI_PCITER_CM                    (0x10000000)
+#define MCF_PCI_PCITER_RF                    (0x40000000)
+#define MCF_PCI_PCITER_RC                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITNAR */
+#define MCF_PCI_PCITNAR_NEXTADDRESS(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITLWR */
+#define MCF_PCI_PCITLWR_LASTWORD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITDCR */
+#define MCF_PCI_PCITDCR_PKTSDONE(x)          (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCITDCR_BYTESDONE(x)         (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCITSR */
+#define MCF_PCI_PCITSR_IA                    (0x10000)
+#define MCF_PCI_PCITSR_TA                    (0x20000)
+#define MCF_PCI_PCITSR_RE                    (0x40000)
+#define MCF_PCI_PCITSR_SE                    (0x80000)
+#define MCF_PCI_PCITSR_FE                    (0x100000)
+#define MCF_PCI_PCITSR_BE1                   (0x200000)
+#define MCF_PCI_PCITSR_BE2                   (0x400000)
+#define MCF_PCI_PCITSR_BE3                   (0x800000)
+#define MCF_PCI_PCITSR_NT                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFDR */
+#define MCF_PCI_PCITFDR_FIFODATAWORD(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFSR */
+#define MCF_PCI_PCITFSR_EMPTY                (0x10000)
+#define MCF_PCI_PCITFSR_ALARM                (0x20000)
+#define MCF_PCI_PCITFSR_FULL                 (0x40000)
+#define MCF_PCI_PCITFSR_FR                   (0x80000)
+#define MCF_PCI_PCITFSR_OF                   (0x100000)
+#define MCF_PCI_PCITFSR_UF                   (0x200000)
+#define MCF_PCI_PCITFSR_RXW                  (0x400000)
+#define MCF_PCI_PCITFSR_FAE                  (0x800000)
+#define MCF_PCI_PCITFSR_TXW                  (0x40000000)
+#define MCF_PCI_PCITFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFCR */
+#define MCF_PCI_PCITFCR_TXW_MASK             (0x40000)
+#define MCF_PCI_PCITFCR_OF_MASK              (0x80000)
+#define MCF_PCI_PCITFCR_UF_MASK              (0x100000)
+#define MCF_PCI_PCITFCR_RXW_MASK             (0x200000)
+#define MCF_PCI_PCITFCR_FAE_MASK             (0x400000)
+#define MCF_PCI_PCITFCR_IP_MASK              (0x800000)
+#define MCF_PCI_PCITFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PCI_PCITFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFAR */
+#define MCF_PCI_PCITFAR_ALARM(x)             (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFRPR */
+#define MCF_PCI_PCITFRPR_READPTR(x)          (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFWPR */
+#define MCF_PCI_PCITFWPR_WRITEPTR(x)         (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRPSR */
+#define MCF_PCI_PCIRPSR_PKTSIZE(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCIRSAR */
+#define MCF_PCI_PCIRSAR_STARTADD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRTCR */
+#define MCF_PCI_PCIRTCR_DI                   (0x1)
+#define MCF_PCI_PCIRTCR_W                    (0x10)
+#define MCF_PCI_PCIRTCR_MAXBEATS(x)          (((x)&0x7)<<0x8)
+#define MCF_PCI_PCIRTCR_FB                   (0x1000)
+#define MCF_PCI_PCIRTCR_MAXRETRY(x)          (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIRTCR_PCICMD(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIRER */
+#define MCF_PCI_PCIRER_NE                    (0x10000)
+#define MCF_PCI_PCIRER_IAE                   (0x20000)
+#define MCF_PCI_PCIRER_TAE                   (0x40000)
+#define MCF_PCI_PCIRER_RE                    (0x80000)
+#define MCF_PCI_PCIRER_SE                    (0x100000)
+#define MCF_PCI_PCIRER_FEE                   (0x200000)
+#define MCF_PCI_PCIRER_ME                    (0x1000000)
+#define MCF_PCI_PCIRER_BE                    (0x8000000)
+#define MCF_PCI_PCIRER_CM                    (0x10000000)
+#define MCF_PCI_PCIRER_FE                    (0x20000000)
+#define MCF_PCI_PCIRER_RF                    (0x40000000)
+#define MCF_PCI_PCIRER_RC                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRNAR */
+#define MCF_PCI_PCIRNAR_NEXTADDRESS(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRDCR */
+#define MCF_PCI_PCIRDCR_PKTSDONE(x)          (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCIRDCR_BYTESDONE(x)         (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCIRSR */
+#define MCF_PCI_PCIRSR_IA                    (0x10000)
+#define MCF_PCI_PCIRSR_TA                    (0x20000)
+#define MCF_PCI_PCIRSR_RE                    (0x40000)
+#define MCF_PCI_PCIRSR_SE                    (0x80000)
+#define MCF_PCI_PCIRSR_FE                    (0x100000)
+#define MCF_PCI_PCIRSR_BE1                   (0x200000)
+#define MCF_PCI_PCIRSR_BE2                   (0x400000)
+#define MCF_PCI_PCIRSR_BE3                   (0x800000)
+#define MCF_PCI_PCIRSR_NT                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFDR */
+#define MCF_PCI_PCIRFDR_FIFODATAWORD(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFSR */
+#define MCF_PCI_PCIRFSR_EMPTY                (0x10000)
+#define MCF_PCI_PCIRFSR_ALARM                (0x20000)
+#define MCF_PCI_PCIRFSR_FULL                 (0x40000)
+#define MCF_PCI_PCIRFSR_FR                   (0x80000)
+#define MCF_PCI_PCIRFSR_OF                   (0x100000)
+#define MCF_PCI_PCIRFSR_UF                   (0x200000)
+#define MCF_PCI_PCIRFSR_RXW                  (0x400000)
+#define MCF_PCI_PCIRFSR_FAE                  (0x800000)
+#define MCF_PCI_PCIRFSR_TXW                  (0x40000000)
+#define MCF_PCI_PCIRFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFCR */
+#define MCF_PCI_PCIRFCR_TXW_MASK             (0x40000)
+#define MCF_PCI_PCIRFCR_OF_MASK              (0x80000)
+#define MCF_PCI_PCIRFCR_UF_MASK              (0x100000)
+#define MCF_PCI_PCIRFCR_RXW_MASK             (0x200000)
+#define MCF_PCI_PCIRFCR_FAE_MASK             (0x400000)
+#define MCF_PCI_PCIRFCR_IP_MASK              (0x800000)
+#define MCF_PCI_PCIRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PCI_PCIRFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFAR */
+#define MCF_PCI_PCIRFAR_ALARM(x)             (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFRPR */
+#define MCF_PCI_PCIRFRPR_READPTR(x)          (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFWPR */
+#define MCF_PCI_PCIRFWPR_WRITEPTR(x)         (((x)&0x7F)<<0)
+
+
+#endif /* __MCF5475_PCI_H__ */

tos/vmem_test/include/MCF5475_PCIARB.h

@@ -0,0 +1,43 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PCIARB_H__
+#define __MCF5475_PCIARB_H__
+
+
+/*********************************************************************
+*
+* PCI Bus Arbiter Module (PCIARB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PCIARB_PACR                      (*(volatile uint32_t*)(&_MBAR[0xC00]))
+#define MCF_PCIARB_PASR                      (*(volatile uint32_t*)(&_MBAR[0xC04]))
+
+
+/* Bit definitions and macros for MCF_PCIARB_PACR */
+#define MCF_PCIARB_PACR_INTMPRI              (0x1)
+#define MCF_PCIARB_PACR_EXTMPRI(x)           (((x)&0x1F)<<0x1)
+#define MCF_PCIARB_PACR_INTMINTEN            (0x10000)
+#define MCF_PCIARB_PACR_EXTMINTEN(x)         (((x)&0x1F)<<0x11)
+#define MCF_PCIARB_PACR_DS                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCIARB_PASR */
+#define MCF_PCIARB_PASR_ITLMBK               (0x10000)
+#define MCF_PCIARB_PASR_EXTMBK(x)            (((x)&0x1F)<<0x11)
+
+
+#endif /* __MCF5475_PCIARB_H__ */

tos/vmem_test/include/MCF5475_PSC.h

@@ -0,0 +1,527 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PSC_H__
+#define __MCF5475_PSC_H__
+
+
+/*********************************************************************
+*
+* Programmable Serial Controller (PSC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PSC0_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8600]))
+#define MCF_PSC0_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8600]))
+#define MCF_PSC0_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8604]))
+#define MCF_PSC0_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8604]))
+#define MCF_PSC0_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8608]))
+#define MCF_PSC0_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8610]))
+#define MCF_PSC0_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8610]))
+#define MCF_PSC0_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8614]))
+#define MCF_PSC0_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8614]))
+#define MCF_PSC0_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8618]))
+#define MCF_PSC0_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x861C]))
+#define MCF_PSC0_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8634]))
+#define MCF_PSC0_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8638]))
+#define MCF_PSC0_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x863C]))
+#define MCF_PSC0_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8640]))
+#define MCF_PSC0_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8644]))
+#define MCF_PSC0_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8648]))
+#define MCF_PSC0_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x864C]))
+#define MCF_PSC0_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8650]))
+#define MCF_PSC0_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8654]))
+#define MCF_PSC0_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8658]))
+#define MCF_PSC0_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x865C]))
+#define MCF_PSC0_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8660]))
+#define MCF_PSC0_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8664]))
+#define MCF_PSC0_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8668]))
+#define MCF_PSC0_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x866E]))
+#define MCF_PSC0_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8672]))
+#define MCF_PSC0_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8676]))
+#define MCF_PSC0_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x867A]))
+#define MCF_PSC0_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x867E]))
+#define MCF_PSC0_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8680]))
+#define MCF_PSC0_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8684]))
+#define MCF_PSC0_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8688]))
+#define MCF_PSC0_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x868E]))
+#define MCF_PSC0_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8692]))
+#define MCF_PSC0_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8696]))
+#define MCF_PSC0_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x869A]))
+#define MCF_PSC0_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x869E]))
+
+#define MCF_PSC1_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8700]))
+#define MCF_PSC1_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8700]))
+#define MCF_PSC1_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8704]))
+#define MCF_PSC1_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8704]))
+#define MCF_PSC1_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8708]))
+#define MCF_PSC1_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8710]))
+#define MCF_PSC1_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8710]))
+#define MCF_PSC1_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8714]))
+#define MCF_PSC1_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8714]))
+#define MCF_PSC1_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8718]))
+#define MCF_PSC1_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x871C]))
+#define MCF_PSC1_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8734]))
+#define MCF_PSC1_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8738]))
+#define MCF_PSC1_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x873C]))
+#define MCF_PSC1_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8740]))
+#define MCF_PSC1_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8744]))
+#define MCF_PSC1_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8748]))
+#define MCF_PSC1_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x874C]))
+#define MCF_PSC1_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8750]))
+#define MCF_PSC1_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8754]))
+#define MCF_PSC1_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8758]))
+#define MCF_PSC1_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x875C]))
+#define MCF_PSC1_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8760]))
+#define MCF_PSC1_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8764]))
+#define MCF_PSC1_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8768]))
+#define MCF_PSC1_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x876E]))
+#define MCF_PSC1_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8772]))
+#define MCF_PSC1_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8776]))
+#define MCF_PSC1_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x877A]))
+#define MCF_PSC1_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x877E]))
+#define MCF_PSC1_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8780]))
+#define MCF_PSC1_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8784]))
+#define MCF_PSC1_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8788]))
+#define MCF_PSC1_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x878E]))
+#define MCF_PSC1_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8792]))
+#define MCF_PSC1_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8796]))
+#define MCF_PSC1_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x879A]))
+#define MCF_PSC1_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x879E]))
+
+#define MCF_PSC2_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8800]))
+#define MCF_PSC2_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8800]))
+#define MCF_PSC2_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8804]))
+#define MCF_PSC2_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8804]))
+#define MCF_PSC2_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8808]))
+#define MCF_PSC2_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8810]))
+#define MCF_PSC2_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8810]))
+#define MCF_PSC2_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8814]))
+#define MCF_PSC2_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8814]))
+#define MCF_PSC2_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8818]))
+#define MCF_PSC2_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x881C]))
+#define MCF_PSC2_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8834]))
+#define MCF_PSC2_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8838]))
+#define MCF_PSC2_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x883C]))
+#define MCF_PSC2_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8840]))
+#define MCF_PSC2_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8844]))
+#define MCF_PSC2_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8848]))
+#define MCF_PSC2_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x884C]))
+#define MCF_PSC2_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8850]))
+#define MCF_PSC2_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8854]))
+#define MCF_PSC2_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8858]))
+#define MCF_PSC2_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x885C]))
+#define MCF_PSC2_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8860]))
+#define MCF_PSC2_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8864]))
+#define MCF_PSC2_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8868]))
+#define MCF_PSC2_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x886E]))
+#define MCF_PSC2_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8872]))
+#define MCF_PSC2_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8876]))
+#define MCF_PSC2_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x887A]))
+#define MCF_PSC2_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x887E]))
+#define MCF_PSC2_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8880]))
+#define MCF_PSC2_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8884]))
+#define MCF_PSC2_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8888]))
+#define MCF_PSC2_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x888E]))
+#define MCF_PSC2_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8892]))
+#define MCF_PSC2_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8896]))
+#define MCF_PSC2_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x889A]))
+#define MCF_PSC2_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x889E]))
+
+#define MCF_PSC3_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8900]))
+#define MCF_PSC3_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8900]))
+#define MCF_PSC3_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8904]))
+#define MCF_PSC3_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8904]))
+#define MCF_PSC3_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8908]))
+#define MCF_PSC3_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8910]))
+#define MCF_PSC3_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8910]))
+#define MCF_PSC3_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8914]))
+#define MCF_PSC3_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8914]))
+#define MCF_PSC3_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8918]))
+#define MCF_PSC3_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x891C]))
+#define MCF_PSC3_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8934]))
+#define MCF_PSC3_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8938]))
+#define MCF_PSC3_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x893C]))
+#define MCF_PSC3_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8940]))
+#define MCF_PSC3_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8944]))
+#define MCF_PSC3_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8948]))
+#define MCF_PSC3_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x894C]))
+#define MCF_PSC3_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8950]))
+#define MCF_PSC3_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8954]))
+#define MCF_PSC3_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8958]))
+#define MCF_PSC3_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x895C]))
+#define MCF_PSC3_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8960]))
+#define MCF_PSC3_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8964]))
+#define MCF_PSC3_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8968]))
+#define MCF_PSC3_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x896E]))
+#define MCF_PSC3_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8972]))
+#define MCF_PSC3_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8976]))
+#define MCF_PSC3_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x897A]))
+#define MCF_PSC3_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x897E]))
+#define MCF_PSC3_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8980]))
+#define MCF_PSC3_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8984]))
+#define MCF_PSC3_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8988]))
+#define MCF_PSC3_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x898E]))
+#define MCF_PSC3_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8992]))
+#define MCF_PSC3_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8996]))
+#define MCF_PSC3_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x899A]))
+#define MCF_PSC3_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x899E]))
+
+#define MCF_PSC_PSCMR(x)                     (*(volatile uint8_t *)(&_MBAR[0x8600 + ((x)*0x100)]))
+#define MCF_PSC_PSCCSR(x)                    (*(volatile uint8_t *)(&_MBAR[0x8604 + ((x)*0x100)]))
+#define MCF_PSC_PSCSR(x)                     (*(volatile uint16_t*)(&_MBAR[0x8604 + ((x)*0x100)]))
+#define MCF_PSC_PSCCR(x)                     (*(volatile uint8_t *)(&_MBAR[0x8608 + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_8BIT(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_8BIT(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_16BIT(x)               (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_16BIT(x)               (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_AC97(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_AC97(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCIPCR(x)                   (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)]))
+#define MCF_PSC_PSCACR(x)                    (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)]))
+#define MCF_PSC_PSCIMR(x)                    (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)]))
+#define MCF_PSC_PSCISR(x)                    (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)]))
+#define MCF_PSC_PSCCTUR(x)                   (*(volatile uint8_t *)(&_MBAR[0x8618 + ((x)*0x100)]))
+#define MCF_PSC_PSCCTLR(x)                   (*(volatile uint8_t *)(&_MBAR[0x861C + ((x)*0x100)]))
+#define MCF_PSC_PSCIP(x)                     (*(volatile uint8_t *)(&_MBAR[0x8634 + ((x)*0x100)]))
+#define MCF_PSC_PSCOPSET(x)                  (*(volatile uint8_t *)(&_MBAR[0x8638 + ((x)*0x100)]))
+#define MCF_PSC_PSCOPRESET(x)                (*(volatile uint8_t *)(&_MBAR[0x863C + ((x)*0x100)]))
+#define MCF_PSC_PSCSICR(x)                   (*(volatile uint8_t *)(&_MBAR[0x8640 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRCR1(x)                  (*(volatile uint8_t *)(&_MBAR[0x8644 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRCR2(x)                  (*(volatile uint8_t *)(&_MBAR[0x8648 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRSDR(x)                  (*(volatile uint8_t *)(&_MBAR[0x864C + ((x)*0x100)]))
+#define MCF_PSC_PSCIRMDR(x)                  (*(volatile uint8_t *)(&_MBAR[0x8650 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRFDR(x)                  (*(volatile uint8_t *)(&_MBAR[0x8654 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFCNT(x)                  (*(volatile uint16_t*)(&_MBAR[0x8658 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFCNT(x)                  (*(volatile uint16_t*)(&_MBAR[0x865C + ((x)*0x100)]))
+#define MCF_PSC_PSCRFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8660 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFSR(x)                   (*(volatile uint16_t*)(&_MBAR[0x8664 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8668 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFAR(x)                   (*(volatile uint16_t*)(&_MBAR[0x866E + ((x)*0x100)]))
+#define MCF_PSC_PSCRFRP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8672 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFWP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8676 + ((x)*0x100)]))
+#define MCF_PSC_PSCRLRFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x867A + ((x)*0x100)]))
+#define MCF_PSC_PSCRLWFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x867E + ((x)*0x100)]))
+#define MCF_PSC_PSCTFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8680 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFSR(x)                   (*(volatile uint16_t*)(&_MBAR[0x8684 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8688 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFAR(x)                   (*(volatile uint16_t*)(&_MBAR[0x868E + ((x)*0x100)]))
+#define MCF_PSC_PSCTFRP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8692 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFWP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8696 + ((x)*0x100)]))
+#define MCF_PSC_PSCTLRFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x869A + ((x)*0x100)]))
+#define MCF_PSC_PSCTLWFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x869E + ((x)*0x100)]))
+
+/* Bit definitions and macros for MCF_PSC_PSCMR */
+#define MCF_PSC_PSCMR_SB(x)                  (((x)&0xF)<<0)
+#define MCF_PSC_PSCMR_TXCTS                  (0x10)
+#define MCF_PSC_PSCMR_TXRTS                  (0x20)
+#define MCF_PSC_PSCMR_CM(x)                  (((x)&0x3)<<0x6)
+#define MCF_PSC_PSCMR_CM_NORMAL              (0)
+#define MCF_PSC_PSCMR_CM_ECHO                (0x40)
+#define MCF_PSC_PSCMR_CM_LOCAL_LOOP          (0x80)
+#define MCF_PSC_PSCMR_CM_REMOTE_LOOP         (0xC0)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_1         (0x7)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_15        (0x8)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_2         (0xF)
+#define MCF_PSC_PSCMR_PM_MULTI_ADDR          (0x1C)
+#define MCF_PSC_PSCMR_PM_MULTI_DATA          (0x18)
+#define MCF_PSC_PSCMR_PM_NONE                (0x10)
+#define MCF_PSC_PSCMR_PM_FORCE_HI            (0xC)
+#define MCF_PSC_PSCMR_PM_FORCE_LO            (0x8)
+#define MCF_PSC_PSCMR_PM_ODD                 (0x4)
+#define MCF_PSC_PSCMR_PM_EVEN                (0)
+#define MCF_PSC_PSCMR_BC(x)                  (((x)&0x3)<<0)
+#define MCF_PSC_PSCMR_BC_5                   (0)
+#define MCF_PSC_PSCMR_BC_6                   (0x1)
+#define MCF_PSC_PSCMR_BC_7                   (0x2)
+#define MCF_PSC_PSCMR_BC_8                   (0x3)
+#define MCF_PSC_PSCMR_PT                     (0x4)
+#define MCF_PSC_PSCMR_PM(x)                  (((x)&0x3)<<0x3)
+#define MCF_PSC_PSCMR_ERR                    (0x20)
+#define MCF_PSC_PSCMR_RXIRQ_FU               (0x40)
+#define MCF_PSC_PSCMR_RXRTS                  (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCCSR */
+#define MCF_PSC_PSCCSR_TCSEL(x)              (((x)&0xF)<<0)
+#define MCF_PSC_PSCCSR_RCSEL(x)              (((x)&0xF)<<0x4)
+#define MCF_PSC_PSCCSR_TCSEL_SYS_CLK         (0x0D)
+#define MCF_PSC_PSCCSR_TCSEL_CTM16           (0x0E)
+#define MCF_PSC_PSCCSR_TCSEL_CTM             (0x0F)
+#define MCF_PSC_PSCCSR_RCSEL_SYS_CLK         (0xD0)
+#define MCF_PSC_PSCCSR_RCSEL_CTM16           (0xE0)
+#define MCF_PSC_PSCCSR_RCSEL_CTM             (0xF0)
+
+/* Bit definitions and macros for MCF_PSC_PSCSR */
+#define MCF_PSC_PSCSR_ERR                    (0x40)
+#define MCF_PSC_PSCSR_CDE_DEOF               (0x80)
+#define MCF_PSC_PSCSR_RXRDY                  (0x100)
+#define MCF_PSC_PSCSR_FU                     (0x200)
+#define MCF_PSC_PSCSR_TXRDY                  (0x400)
+#define MCF_PSC_PSCSR_TXEMP_URERR            (0x800)
+#define MCF_PSC_PSCSR_OE                     (0x1000)
+#define MCF_PSC_PSCSR_PE_CRCERR              (0x2000)
+#define MCF_PSC_PSCSR_FE_PHYERR              (0x4000)
+#define MCF_PSC_PSCSR_RB_NEOF                (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCCR */
+#define MCF_PSC_PSCCR_RXC(x)                 (((x)&0x3)<<0)
+#define MCF_PSC_PSCCR_RX_ENABLED             (0x1)
+#define MCF_PSC_PSCCR_RX_DISABLED            (0x2)
+#define MCF_PSC_PSCCR_TXC(x)                 (((x)&0x3)<<0x2)
+#define MCF_PSC_PSCCR_TX_ENABLED             (0x4)
+#define MCF_PSC_PSCCR_TX_DISABLED            (0x8)
+#define MCF_PSC_PSCCR_MISC(x)                (((x)&0x7)<<0x4)
+#define MCF_PSC_PSCCR_NONE                   (0)
+#define MCF_PSC_PSCCR_RESET_MR               (0x10)
+#define MCF_PSC_PSCCR_RESET_RX               (0x20)
+#define MCF_PSC_PSCCR_RESET_TX               (0x30)
+#define MCF_PSC_PSCCR_RESET_ERROR            (0x40)
+#define MCF_PSC_PSCCR_RESET_BKCHGINT         (0x50)
+#define MCF_PSC_PSCCR_START_BREAK            (0x60)
+#define MCF_PSC_PSCCR_STOP_BREAK             (0x70)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_8BIT */
+#define MCF_PSC_PSCRB_8BIT_RB3(x)            (((x)&0xFF)<<0)
+#define MCF_PSC_PSCRB_8BIT_RB2(x)            (((x)&0xFF)<<0x8)
+#define MCF_PSC_PSCRB_8BIT_RB1(x)            (((x)&0xFF)<<0x10)
+#define MCF_PSC_PSCRB_8BIT_RB0(x)            (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_8BIT */
+#define MCF_PSC_PSCTB_8BIT_TB3(x)            (((x)&0xFF)<<0)
+#define MCF_PSC_PSCTB_8BIT_TB2(x)            (((x)&0xFF)<<0x8)
+#define MCF_PSC_PSCTB_8BIT_TB1(x)            (((x)&0xFF)<<0x10)
+#define MCF_PSC_PSCTB_8BIT_TB0(x)            (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_16BIT */
+#define MCF_PSC_PSCRB_16BIT_RB1(x)           (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCRB_16BIT_RB0(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_16BIT */
+#define MCF_PSC_PSCTB_16BIT_TB1(x)           (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCTB_16BIT_TB0(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_AC97 */
+#define MCF_PSC_PSCRB_AC97_SOF               (0x800)
+#define MCF_PSC_PSCRB_AC97_RB(x)             (((x)&0xFFFFF)<<0xC)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_AC97 */
+#define MCF_PSC_PSCTB_AC97_TB(x)             (((x)&0xFFFFF)<<0xC)
+
+/* Bit definitions and macros for MCF_PSC_PSCIPCR */
+#define MCF_PSC_PSCIPCR_RESERVED             (0xC)
+#define MCF_PSC_PSCIPCR_CTS                  (0xD)
+#define MCF_PSC_PSCIPCR_D_CTS                (0x1C)
+#define MCF_PSC_PSCIPCR_SYNC                 (0x8C)
+
+/* Bit definitions and macros for MCF_PSC_PSCACR */
+#define MCF_PSC_PSCACR_IEC0                  (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCIMR */
+#define MCF_PSC_PSCIMR_ERR                   (0x40)
+#define MCF_PSC_PSCIMR_DEOF                  (0x80)
+#define MCF_PSC_PSCIMR_TXRDY                 (0x100)
+#define MCF_PSC_PSCIMR_RXRDY_FU              (0x200)
+#define MCF_PSC_PSCIMR_DB                    (0x400)
+#define MCF_PSC_PSCIMR_IPC                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCISR */
+#define MCF_PSC_PSCISR_ERR                   (0x40)
+#define MCF_PSC_PSCISR_DEOF                  (0x80)
+#define MCF_PSC_PSCISR_TXRDY                 (0x100)
+#define MCF_PSC_PSCISR_RXRDY_FU              (0x200)
+#define MCF_PSC_PSCISR_DB                    (0x400)
+#define MCF_PSC_PSCISR_IPC                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCCTUR */
+#define MCF_PSC_PSCCTUR_CT(x)                (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCCTLR */
+#define MCF_PSC_PSCCTLR_CT(x)                (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCIP */
+#define MCF_PSC_PSCIP_CTS                    (0x1)
+#define MCF_PSC_PSCIP_TGL                    (0x40)
+#define MCF_PSC_PSCIP_LPWR_B                 (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCOPSET */
+#define MCF_PSC_PSCOPSET_RTS                 (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCOPRESET */
+#define MCF_PSC_PSCOPRESET_RTS               (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCSICR */
+#define MCF_PSC_PSCSICR_SIM(x)               (((x)&0x7)<<0)
+#define MCF_PSC_PSCSICR_SIM_UART             (0)
+#define MCF_PSC_PSCSICR_SIM_MODEM8           (0x1)
+#define MCF_PSC_PSCSICR_SIM_MODEM16          (0x2)
+#define MCF_PSC_PSCSICR_SIM_AC97             (0x3)
+#define MCF_PSC_PSCSICR_SIM_SIR              (0x4)
+#define MCF_PSC_PSCSICR_SIM_MIR              (0x5)
+#define MCF_PSC_PSCSICR_SIM_FIR              (0x6)
+#define MCF_PSC_PSCSICR_SHDIR                (0x10)
+#define MCF_PSC_PSCSICR_DTS1                 (0x20)
+#define MCF_PSC_PSCSICR_AWR                  (0x40)
+#define MCF_PSC_PSCSICR_ACRB                 (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRCR1 */
+#define MCF_PSC_PSCIRCR1_SPUL                (0x1)
+#define MCF_PSC_PSCIRCR1_SIPEN               (0x2)
+#define MCF_PSC_PSCIRCR1_FD                  (0x4)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRCR2 */
+#define MCF_PSC_PSCIRCR2_NXTEOF              (0x1)
+#define MCF_PSC_PSCIRCR2_ABORT               (0x2)
+#define MCF_PSC_PSCIRCR2_SIPREQ              (0x4)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRSDR */
+#define MCF_PSC_PSCIRSDR_IRSTIM(x)           (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRMDR */
+#define MCF_PSC_PSCIRMDR_M_FDIV(x)           (((x)&0x7F)<<0)
+#define MCF_PSC_PSCIRMDR_FREQ                (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRFDR */
+#define MCF_PSC_PSCIRFDR_F_FDIV(x)           (((x)&0xF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFCNT */
+#define MCF_PSC_PSCRFCNT_CNT(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFCNT */
+#define MCF_PSC_PSCTFCNT_CNT(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFDR */
+#define MCF_PSC_PSCRFDR_DATA(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFSR */
+#define MCF_PSC_PSCRFSR_EMT                  (0x1)
+#define MCF_PSC_PSCRFSR_ALARM                (0x2)
+#define MCF_PSC_PSCRFSR_FU                   (0x4)
+#define MCF_PSC_PSCRFSR_FRMRDY               (0x8)
+#define MCF_PSC_PSCRFSR_OF                   (0x10)
+#define MCF_PSC_PSCRFSR_UF                   (0x20)
+#define MCF_PSC_PSCRFSR_RXW                  (0x40)
+#define MCF_PSC_PSCRFSR_FAE                  (0x80)
+#define MCF_PSC_PSCRFSR_FRM(x)               (((x)&0xF)<<0x8)
+#define MCF_PSC_PSCRFSR_FRM_BYTE0            (0x800)
+#define MCF_PSC_PSCRFSR_FRM_BYTE1            (0x400)
+#define MCF_PSC_PSCRFSR_FRM_BYTE2            (0x200)
+#define MCF_PSC_PSCRFSR_FRM_BYTE3            (0x100)
+#define MCF_PSC_PSCRFSR_TAG(x)               (((x)&0x3)<<0xC)
+#define MCF_PSC_PSCRFSR_TXW                  (0x4000)
+#define MCF_PSC_PSCRFSR_IP                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFCR */
+#define MCF_PSC_PSCRFCR_CNTR(x)              (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCRFCR_TXW_MSK              (0x40000)
+#define MCF_PSC_PSCRFCR_OF_MSK               (0x80000)
+#define MCF_PSC_PSCRFCR_UF_MSK               (0x100000)
+#define MCF_PSC_PSCRFCR_RXW_MSK              (0x200000)
+#define MCF_PSC_PSCRFCR_FAE_MSK              (0x400000)
+#define MCF_PSC_PSCRFCR_IP_MSK               (0x800000)
+#define MCF_PSC_PSCRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PSC_PSCRFCR_FRMEN                (0x8000000)
+#define MCF_PSC_PSCRFCR_TIMER                (0x10000000)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFAR */
+#define MCF_PSC_PSCRFAR_ALARM(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFRP */
+#define MCF_PSC_PSCRFRP_READ(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFWP */
+#define MCF_PSC_PSCRFWP_WRITE(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRLRFP */
+#define MCF_PSC_PSCRLRFP_LRFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRLWFP */
+#define MCF_PSC_PSCRLWFP_LWFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFDR */
+#define MCF_PSC_PSCTFDR_DATA(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFSR */
+#define MCF_PSC_PSCTFSR_EMT                  (0x1)
+#define MCF_PSC_PSCTFSR_ALARM                (0x2)
+#define MCF_PSC_PSCTFSR_FU                   (0x4)
+#define MCF_PSC_PSCTFSR_FRMRDY               (0x8)
+#define MCF_PSC_PSCTFSR_OF                   (0x10)
+#define MCF_PSC_PSCTFSR_UF                   (0x20)
+#define MCF_PSC_PSCTFSR_RXW                  (0x40)
+#define MCF_PSC_PSCTFSR_FAE                  (0x80)
+#define MCF_PSC_PSCTFSR_FRM(x)               (((x)&0xF)<<0x8)
+#define MCF_PSC_PSCTFSR_FRM_BYTE0            (0x800)
+#define MCF_PSC_PSCTFSR_FRM_BYTE1            (0x400)
+#define MCF_PSC_PSCTFSR_FRM_BYTE2            (0x200)
+#define MCF_PSC_PSCTFSR_FRM_BYTE3            (0x100)
+#define MCF_PSC_PSCTFSR_TAG(x)               (((x)&0x3)<<0xC)
+#define MCF_PSC_PSCTFSR_TXW                  (0x4000)
+#define MCF_PSC_PSCTFSR_IP                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFCR */
+#define MCF_PSC_PSCTFCR_CNTR(x)              (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCTFCR_TXW_MSK              (0x40000)
+#define MCF_PSC_PSCTFCR_OF_MSK               (0x80000)
+#define MCF_PSC_PSCTFCR_UF_MSK               (0x100000)
+#define MCF_PSC_PSCTFCR_RXW_MSK              (0x200000)
+#define MCF_PSC_PSCTFCR_FAE_MSK              (0x400000)
+#define MCF_PSC_PSCTFCR_IP_MSK               (0x800000)
+#define MCF_PSC_PSCTFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PSC_PSCTFCR_FRMEN                (0x8000000)
+#define MCF_PSC_PSCTFCR_TIMER                (0x10000000)
+#define MCF_PSC_PSCTFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFAR */
+#define MCF_PSC_PSCTFAR_ALARM(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFRP */
+#define MCF_PSC_PSCTFRP_READ(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFWP */
+#define MCF_PSC_PSCTFWP_WRITE(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTLRFP */
+#define MCF_PSC_PSCTLRFP_LRFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTLWFP */
+#define MCF_PSC_PSCTLWFP_LWFP(x)             (((x)&0x1FF)<<0)
+
+
+#endif /* __MCF5475_PSC_H__ */

tos/vmem_test/include/MCF5475_SDRAMC.h

@@ -0,0 +1,106 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SDRAMC_H__
+#define __MCF5475_SDRAMC_H__
+
+
+/*********************************************************************
+*
+* Synchronous DRAM Controller (SDRAMC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SDRAMC_SDRAMDS                   (*(volatile uint32_t*)(&_MBAR[0x4]))
+#define MCF_SDRAMC_CS0CFG                    (*(volatile uint32_t*)(&_MBAR[0x20]))
+#define MCF_SDRAMC_CS1CFG                    (*(volatile uint32_t*)(&_MBAR[0x24]))
+#define MCF_SDRAMC_CS2CFG                    (*(volatile uint32_t*)(&_MBAR[0x28]))
+#define MCF_SDRAMC_CS3CFG                    (*(volatile uint32_t*)(&_MBAR[0x2C]))
+#define MCF_SDRAMC_SDMR                      (*(volatile uint32_t*)(&_MBAR[0x100]))
+#define MCF_SDRAMC_SDCR                      (*(volatile uint32_t*)(&_MBAR[0x104]))
+#define MCF_SDRAMC_SDCFG1                    (*(volatile uint32_t*)(&_MBAR[0x108]))
+#define MCF_SDRAMC_SDCFG2                    (*(volatile uint32_t*)(&_MBAR[0x10C]))
+#define MCF_SDRAMC_CSCFG(x)                  (*(volatile uint32_t*)(&_MBAR[0x20 + ((x)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */
+#define MCF_SDRAMC_SDRAMDS_SB_D(x)           (((x)&0x3)<<0)
+#define MCF_SDRAMC_SDRAMDS_SB_S(x)           (((x)&0x3)<<0x2)
+#define MCF_SDRAMC_SDRAMDS_SB_A(x)           (((x)&0x3)<<0x4)
+#define MCF_SDRAMC_SDRAMDS_SB_C(x)           (((x)&0x3)<<0x6)
+#define MCF_SDRAMC_SDRAMDS_SB_E(x)           (((x)&0x3)<<0x8)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA        (0)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA        (0x1)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA         (0x2)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE        (0x3)
+
+/* Bit definitions and macros for MCF_SDRAMC_CSCFG */
+#define MCF_SDRAMC_CSCFG_CSSZ(x)             (((x)&0x1F)<<0)
+#define MCF_SDRAMC_CSCFG_CSSZ_DISABLED       (0)
+#define MCF_SDRAMC_CSCFG_CSSZ_1MBYTE         (0x13)
+#define MCF_SDRAMC_CSCFG_CSSZ_2MBYTE         (0x14)
+#define MCF_SDRAMC_CSCFG_CSSZ_4MBYTE         (0x15)
+#define MCF_SDRAMC_CSCFG_CSSZ_8MBYTE         (0x16)
+#define MCF_SDRAMC_CSCFG_CSSZ_16MBYTE        (0x17)
+#define MCF_SDRAMC_CSCFG_CSSZ_32MBYTE        (0x18)
+#define MCF_SDRAMC_CSCFG_CSSZ_64MBYTE        (0x19)
+#define MCF_SDRAMC_CSCFG_CSSZ_128MBYTE       (0x1A)
+#define MCF_SDRAMC_CSCFG_CSSZ_256MBYTE       (0x1B)
+#define MCF_SDRAMC_CSCFG_CSSZ_512MBYTE       (0x1C)
+#define MCF_SDRAMC_CSCFG_CSSZ_1GBYTE         (0x1D)
+#define MCF_SDRAMC_CSCFG_CSSZ_2GBYTE         (0x1E)
+#define MCF_SDRAMC_CSCFG_CSSZ_4GBYTE         (0x1F)
+#define MCF_SDRAMC_CSCFG_CSBA(x)             (((x)&0xFFF)<<0x14)
+#define MCF_SDRAMC_CSCFG_BA(x)               ((x)&0xFFF00000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDMR */
+#define MCF_SDRAMC_SDMR_CMD                  (0x10000)
+#define MCF_SDRAMC_SDMR_AD(x)                (((x)&0xFFF)<<0x12)
+#define MCF_SDRAMC_SDMR_BNKAD(x)             (((x)&0x3)<<0x1E)
+#define MCF_SDRAMC_SDMR_BK_LMR               (0)
+#define MCF_SDRAMC_SDMR_BK_LEMR              (0x40000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCR */
+#define MCF_SDRAMC_SDCR_IPALL                (0x2)
+#define MCF_SDRAMC_SDCR_IREF                 (0x4)
+#define MCF_SDRAMC_SDCR_BUFF                 (0x10)
+#define MCF_SDRAMC_SDCR_DQS_OE(x)            (((x)&0xF)<<0x8)
+#define MCF_SDRAMC_SDCR_RCNT(x)              (((x)&0x3F)<<0x10)
+#define MCF_SDRAMC_SDCR_DRIVE                (0x400000)
+#define MCF_SDRAMC_SDCR_AP                   (0x800000)
+#define MCF_SDRAMC_SDCR_MUX(x)               (((x)&0x3)<<0x18)
+#define MCF_SDRAMC_SDCR_REF                  (0x10000000)
+#define MCF_SDRAMC_SDCR_DDR                  (0x20000000)
+#define MCF_SDRAMC_SDCR_CKE                  (0x40000000)
+#define MCF_SDRAMC_SDCR_MODE_EN              (0x80000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
+#define MCF_SDRAMC_SDCFG1_WTLAT(x)           (((x)&0x7)<<0x4)
+#define MCF_SDRAMC_SDCFG1_REF2ACT(x)         (((x)&0xF)<<0x8)
+#define MCF_SDRAMC_SDCFG1_PRE2ACT(x)         (((x)&0x7)<<0xC)
+#define MCF_SDRAMC_SDCFG1_ACT2RW(x)          (((x)&0x7)<<0x10)
+#define MCF_SDRAMC_SDCFG1_RDLAT(x)           (((x)&0xF)<<0x14)
+#define MCF_SDRAMC_SDCFG1_SWT2RD(x)          (((x)&0x7)<<0x18)
+#define MCF_SDRAMC_SDCFG1_SRD2RW(x)          (((x)&0xF)<<0x1C)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
+#define MCF_SDRAMC_SDCFG2_BL(x)              (((x)&0xF)<<0x10)
+#define MCF_SDRAMC_SDCFG2_BRD2WT(x)          (((x)&0xF)<<0x14)
+#define MCF_SDRAMC_SDCFG2_BWT2RW(x)          (((x)&0xF)<<0x18)
+#define MCF_SDRAMC_SDCFG2_BRD2PRE(x)         (((x)&0xF)<<0x1C)
+
+
+#endif /* __MCF5475_SDRAMC_H__ */

tos/vmem_test/include/MCF5475_SEC.h

@@ -0,0 +1,398 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SEC_H__
+#define __MCF5475_SEC_H__
+
+
+/*********************************************************************
+*
+* Integrated Security Engine (SEC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SEC_EUACRH                       (*(volatile uint32_t*)(&_MBAR[0x21000]))
+#define MCF_SEC_EUACRL                       (*(volatile uint32_t*)(&_MBAR[0x21004]))
+#define MCF_SEC_SIMRH                        (*(volatile uint32_t*)(&_MBAR[0x21008]))
+#define MCF_SEC_SIMRL                        (*(volatile uint32_t*)(&_MBAR[0x2100C]))
+#define MCF_SEC_SISRH                        (*(volatile uint32_t*)(&_MBAR[0x21010]))
+#define MCF_SEC_SISRL                        (*(volatile uint32_t*)(&_MBAR[0x21014]))
+#define MCF_SEC_SICRH                        (*(volatile uint32_t*)(&_MBAR[0x21018]))
+#define MCF_SEC_SICRL                        (*(volatile uint32_t*)(&_MBAR[0x2101C]))
+#define MCF_SEC_SIDR                         (*(volatile uint32_t*)(&_MBAR[0x21020]))
+#define MCF_SEC_EUASRH                       (*(volatile uint32_t*)(&_MBAR[0x21028]))
+#define MCF_SEC_EUASRL                       (*(volatile uint32_t*)(&_MBAR[0x2102C]))
+#define MCF_SEC_SMCR                         (*(volatile uint32_t*)(&_MBAR[0x21030]))
+#define MCF_SEC_MEAR                         (*(volatile uint32_t*)(&_MBAR[0x21038]))
+#define MCF_SEC_CCCR0                        (*(volatile uint32_t*)(&_MBAR[0x2200C]))
+#define MCF_SEC_CCPSRH0                      (*(volatile uint32_t*)(&_MBAR[0x22010]))
+#define MCF_SEC_CCPSRL0                      (*(volatile uint32_t*)(&_MBAR[0x22014]))
+#define MCF_SEC_CDPR0                        (*(volatile uint32_t*)(&_MBAR[0x22044]))
+#define MCF_SEC_FR0                          (*(volatile uint32_t*)(&_MBAR[0x2204C]))
+#define MCF_SEC_CCCR1                        (*(volatile uint32_t*)(&_MBAR[0x2300C]))
+#define MCF_SEC_CCPSRH1                      (*(volatile uint32_t*)(&_MBAR[0x23010]))
+#define MCF_SEC_CCPSRL1                      (*(volatile uint32_t*)(&_MBAR[0x23014]))
+#define MCF_SEC_CDPR1                        (*(volatile uint32_t*)(&_MBAR[0x23044]))
+#define MCF_SEC_FR1                          (*(volatile uint32_t*)(&_MBAR[0x2304C]))
+#define MCF_SEC_AFRCR                        (*(volatile uint32_t*)(&_MBAR[0x28018]))
+#define MCF_SEC_AFSR                         (*(volatile uint32_t*)(&_MBAR[0x28028]))
+#define MCF_SEC_AFISR                        (*(volatile uint32_t*)(&_MBAR[0x28030]))
+#define MCF_SEC_AFIMR                        (*(volatile uint32_t*)(&_MBAR[0x28038]))
+#define MCF_SEC_DRCR                         (*(volatile uint32_t*)(&_MBAR[0x2A018]))
+#define MCF_SEC_DSR                          (*(volatile uint32_t*)(&_MBAR[0x2A028]))
+#define MCF_SEC_DISR                         (*(volatile uint32_t*)(&_MBAR[0x2A030]))
+#define MCF_SEC_DIMR                         (*(volatile uint32_t*)(&_MBAR[0x2A038]))
+#define MCF_SEC_MDRCR                        (*(volatile uint32_t*)(&_MBAR[0x2C018]))
+#define MCF_SEC_MDSR                         (*(volatile uint32_t*)(&_MBAR[0x2C028]))
+#define MCF_SEC_MDISR                        (*(volatile uint32_t*)(&_MBAR[0x2C030]))
+#define MCF_SEC_MDIMR                        (*(volatile uint32_t*)(&_MBAR[0x2C038]))
+#define MCF_SEC_RNGRCR                       (*(volatile uint32_t*)(&_MBAR[0x2E018]))
+#define MCF_SEC_RNGSR                        (*(volatile uint32_t*)(&_MBAR[0x2E028]))
+#define MCF_SEC_RNGISR                       (*(volatile uint32_t*)(&_MBAR[0x2E030]))
+#define MCF_SEC_RNGIMR                       (*(volatile uint32_t*)(&_MBAR[0x2E038]))
+#define MCF_SEC_AESRCR                       (*(volatile uint32_t*)(&_MBAR[0x32018]))
+#define MCF_SEC_AESSR                        (*(volatile uint32_t*)(&_MBAR[0x32028]))
+#define MCF_SEC_AESISR                       (*(volatile uint32_t*)(&_MBAR[0x32030]))
+#define MCF_SEC_AESIMR                       (*(volatile uint32_t*)(&_MBAR[0x32038]))
+#define MCF_SEC_CCCRn(x)                     (*(volatile uint32_t*)(&_MBAR[0x2200C + ((x)*0x1000)]))
+#define MCF_SEC_CCPSRHn(x)                   (*(volatile uint32_t*)(&_MBAR[0x22010 + ((x)*0x1000)]))
+#define MCF_SEC_CCPSRLn(x)                   (*(volatile uint32_t*)(&_MBAR[0x22014 + ((x)*0x1000)]))
+#define MCF_SEC_CDPRn(x)                     (*(volatile uint32_t*)(&_MBAR[0x22044 + ((x)*0x1000)]))
+#define MCF_SEC_FRn(x)                       (*(volatile uint32_t*)(&_MBAR[0x2204C + ((x)*0x1000)]))
+
+
+/* Bit definitions and macros for MCF_SEC_EUACRH */
+#define MCF_SEC_EUACRH_AFEU(x)               (((x)&0xF)<<0)
+#define MCF_SEC_EUACRH_AFFEU_NOASSIGN        (0)
+#define MCF_SEC_EUACRH_AFFEU_CHA0            (0x1)
+#define MCF_SEC_EUACRH_AFFEU_CHA1            (0x2)
+#define MCF_SEC_EUACRH_MDEU(x)               (((x)&0xF)<<0x8)
+#define MCF_SEC_EUACRH_MDEU_NOASSIGN         (0)
+#define MCF_SEC_EUACRH_MDEU_CHA0             (0x100)
+#define MCF_SEC_EUACRH_MDEU_CHA1             (0x200)
+#define MCF_SEC_EUACRH_RNG(x)                (((x)&0xF)<<0x18)
+#define MCF_SEC_EUACRH_RNG_NOASSIGN          (0)
+#define MCF_SEC_EUACRH_RNG_CHA0              (0x1000000)
+#define MCF_SEC_EUACRH_RNG_CHA1              (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_EUACRL */
+#define MCF_SEC_EUACRL_AESU(x)               (((x)&0xF)<<0x10)
+#define MCF_SEC_EUACRL_AESU_NOASSIGN         (0)
+#define MCF_SEC_EUACRL_AESU_CHA0             (0x10000)
+#define MCF_SEC_EUACRL_AESU_CHA1             (0x20000)
+#define MCF_SEC_EUACRL_DEU(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_SIMRH */
+#define MCF_SEC_SIMRH_AERR                   (0x8000000)
+#define MCF_SEC_SIMRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SIMRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SIMRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SIMRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SIMRL */
+#define MCF_SEC_SIMRL_TEA                    (0x40)
+#define MCF_SEC_SIMRL_DEU_DN                 (0x100)
+#define MCF_SEC_SIMRL_DEU_ERR                (0x200)
+#define MCF_SEC_SIMRL_AESU_DN                (0x1000)
+#define MCF_SEC_SIMRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SIMRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SIMRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SIMRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SIMRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SIMRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SIMRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SISRH */
+#define MCF_SEC_SISRH_AERR                   (0x8000000)
+#define MCF_SEC_SISRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SISRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SISRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SISRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SISRL */
+#define MCF_SEC_SISRL_TEA                    (0x40)
+#define MCF_SEC_SISRL_DEU_DN                 (0x100)
+#define MCF_SEC_SISRL_DEU_ERR                (0x200)
+#define MCF_SEC_SISRL_AESU_DN                (0x1000)
+#define MCF_SEC_SISRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SISRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SISRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SISRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SISRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SISRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SISRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SICRH */
+#define MCF_SEC_SICRH_AERR                   (0x8000000)
+#define MCF_SEC_SICRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SICRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SICRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SICRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SICRL */
+#define MCF_SEC_SICRL_TEA                    (0x40)
+#define MCF_SEC_SICRL_DEU_DN                 (0x100)
+#define MCF_SEC_SICRL_DEU_ERR                (0x200)
+#define MCF_SEC_SICRL_AESU_DN                (0x1000)
+#define MCF_SEC_SICRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SICRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SICRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SICRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SICRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SICRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SICRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SIDR */
+#define MCF_SEC_SIDR_VERSION(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_EUASRH */
+#define MCF_SEC_EUASRH_AFEU(x)               (((x)&0xF)<<0)
+#define MCF_SEC_EUASRH_MDEU(x)               (((x)&0xF)<<0x8)
+#define MCF_SEC_EUASRH_RNG(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_EUASRL */
+#define MCF_SEC_EUASRL_AESU(x)               (((x)&0xF)<<0x10)
+#define MCF_SEC_EUASRL_DEU(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_SMCR */
+#define MCF_SEC_SMCR_CURR_CHAN(x)            (((x)&0xF)<<0x4)
+#define MCF_SEC_SMCR_CURR_CHAN_1             (0x10)
+#define MCF_SEC_SMCR_CURR_CHAN_2             (0x20)
+#define MCF_SEC_SMCR_SWR                     (0x1000000)
+
+/* Bit definitions and macros for MCF_SEC_MEAR */
+#define MCF_SEC_MEAR_ADDRESS(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_CCCRn */
+#define MCF_SEC_CCCRn_RST                    (0x1)
+#define MCF_SEC_CCCRn_CDIE                   (0x2)
+#define MCF_SEC_CCCRn_NT                     (0x4)
+#define MCF_SEC_CCCRn_NE                     (0x8)
+#define MCF_SEC_CCCRn_WE                     (0x10)
+#define MCF_SEC_CCCRn_BURST_SIZE(x)          (((x)&0x7)<<0x8)
+#define MCF_SEC_CCCRn_BURST_SIZE_2           (0)
+#define MCF_SEC_CCCRn_BURST_SIZE_8           (0x100)
+#define MCF_SEC_CCCRn_BURST_SIZE_16          (0x200)
+#define MCF_SEC_CCCRn_BURST_SIZE_24          (0x300)
+#define MCF_SEC_CCCRn_BURST_SIZE_32          (0x400)
+#define MCF_SEC_CCCRn_BURST_SIZE_40          (0x500)
+#define MCF_SEC_CCCRn_BURST_SIZE_48          (0x600)
+#define MCF_SEC_CCCRn_BURST_SIZE_56          (0x700)
+
+/* Bit definitions and macros for MCF_SEC_CCPSRHn */
+#define MCF_SEC_CCPSRHn_STATE(x)             (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_CCPSRLn */
+#define MCF_SEC_CCPSRLn_PAIR_PTR(x)          (((x)&0xFF)<<0)
+#define MCF_SEC_CCPSRLn_EUERR                (0x100)
+#define MCF_SEC_CCPSRLn_SERR                 (0x200)
+#define MCF_SEC_CCPSRLn_DERR                 (0x400)
+#define MCF_SEC_CCPSRLn_PERR                 (0x1000)
+#define MCF_SEC_CCPSRLn_TEA                  (0x2000)
+#define MCF_SEC_CCPSRLn_SD                   (0x10000)
+#define MCF_SEC_CCPSRLn_PD                   (0x20000)
+#define MCF_SEC_CCPSRLn_SRD                  (0x40000)
+#define MCF_SEC_CCPSRLn_PRD                  (0x80000)
+#define MCF_SEC_CCPSRLn_SG                   (0x100000)
+#define MCF_SEC_CCPSRLn_PG                   (0x200000)
+#define MCF_SEC_CCPSRLn_SR                   (0x400000)
+#define MCF_SEC_CCPSRLn_PR                   (0x800000)
+#define MCF_SEC_CCPSRLn_MO                   (0x1000000)
+#define MCF_SEC_CCPSRLn_MI                   (0x2000000)
+#define MCF_SEC_CCPSRLn_STAT                 (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_CDPRn */
+#define MCF_SEC_CDPRn_CDP(x)                 (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_FRn */
+#define MCF_SEC_FRn_FETCH_ADDR(x)            (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_AFRCR */
+#define MCF_SEC_AFRCR_SR                     (0x1000000)
+#define MCF_SEC_AFRCR_MI                     (0x2000000)
+#define MCF_SEC_AFRCR_RI                     (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_AFSR */
+#define MCF_SEC_AFSR_RD                      (0x1000000)
+#define MCF_SEC_AFSR_ID                      (0x2000000)
+#define MCF_SEC_AFSR_IE                      (0x4000000)
+#define MCF_SEC_AFSR_OFR                     (0x8000000)
+#define MCF_SEC_AFSR_IFW                     (0x10000000)
+#define MCF_SEC_AFSR_HALT                    (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_AFISR */
+#define MCF_SEC_AFISR_DSE                    (0x10000)
+#define MCF_SEC_AFISR_KSE                    (0x20000)
+#define MCF_SEC_AFISR_CE                     (0x40000)
+#define MCF_SEC_AFISR_ERE                    (0x80000)
+#define MCF_SEC_AFISR_IE                     (0x100000)
+#define MCF_SEC_AFISR_OFU                    (0x2000000)
+#define MCF_SEC_AFISR_IFO                    (0x4000000)
+#define MCF_SEC_AFISR_IFE                    (0x10000000)
+#define MCF_SEC_AFISR_OFE                    (0x20000000)
+#define MCF_SEC_AFISR_AE                     (0x40000000)
+#define MCF_SEC_AFISR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AFIMR */
+#define MCF_SEC_AFIMR_DSE                    (0x10000)
+#define MCF_SEC_AFIMR_KSE                    (0x20000)
+#define MCF_SEC_AFIMR_CE                     (0x40000)
+#define MCF_SEC_AFIMR_ERE                    (0x80000)
+#define MCF_SEC_AFIMR_IE                     (0x100000)
+#define MCF_SEC_AFIMR_OFU                    (0x2000000)
+#define MCF_SEC_AFIMR_IFO                    (0x4000000)
+#define MCF_SEC_AFIMR_IFE                    (0x10000000)
+#define MCF_SEC_AFIMR_OFE                    (0x20000000)
+#define MCF_SEC_AFIMR_AE                     (0x40000000)
+#define MCF_SEC_AFIMR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_DRCR */
+#define MCF_SEC_DRCR_SR                      (0x1000000)
+#define MCF_SEC_DRCR_MI                      (0x2000000)
+#define MCF_SEC_DRCR_RI                      (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_DSR */
+#define MCF_SEC_DSR_RD                       (0x1000000)
+#define MCF_SEC_DSR_ID                       (0x2000000)
+#define MCF_SEC_DSR_IE                       (0x4000000)
+#define MCF_SEC_DSR_OFR                      (0x8000000)
+#define MCF_SEC_DSR_IFW                      (0x10000000)
+#define MCF_SEC_DSR_HALT                     (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_DISR */
+#define MCF_SEC_DISR_DSE                     (0x10000)
+#define MCF_SEC_DISR_KSE                     (0x20000)
+#define MCF_SEC_DISR_CE                      (0x40000)
+#define MCF_SEC_DISR_ERE                     (0x80000)
+#define MCF_SEC_DISR_IE                      (0x100000)
+#define MCF_SEC_DISR_KPE                     (0x200000)
+#define MCF_SEC_DISR_OFU                     (0x2000000)
+#define MCF_SEC_DISR_IFO                     (0x4000000)
+#define MCF_SEC_DISR_IFE                     (0x10000000)
+#define MCF_SEC_DISR_OFE                     (0x20000000)
+#define MCF_SEC_DISR_AE                      (0x40000000)
+#define MCF_SEC_DISR_ME                      (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_DIMR */
+#define MCF_SEC_DIMR_DSE                     (0x10000)
+#define MCF_SEC_DIMR_KSE                     (0x20000)
+#define MCF_SEC_DIMR_CE                      (0x40000)
+#define MCF_SEC_DIMR_ERE                     (0x80000)
+#define MCF_SEC_DIMR_IE                      (0x100000)
+#define MCF_SEC_DIMR_KPE                     (0x200000)
+#define MCF_SEC_DIMR_OFU                     (0x2000000)
+#define MCF_SEC_DIMR_IFO                     (0x4000000)
+#define MCF_SEC_DIMR_IFE                     (0x10000000)
+#define MCF_SEC_DIMR_OFE                     (0x20000000)
+#define MCF_SEC_DIMR_AE                      (0x40000000)
+#define MCF_SEC_DIMR_ME                      (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_MDRCR */
+#define MCF_SEC_MDRCR_SR                     (0x1000000)
+#define MCF_SEC_MDRCR_MI                     (0x2000000)
+#define MCF_SEC_MDRCR_RI                     (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_MDSR */
+#define MCF_SEC_MDSR_RD                      (0x1000000)
+#define MCF_SEC_MDSR_ID                      (0x2000000)
+#define MCF_SEC_MDSR_IE                      (0x4000000)
+#define MCF_SEC_MDSR_IFW                     (0x10000000)
+#define MCF_SEC_MDSR_HALT                    (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_MDISR */
+#define MCF_SEC_MDISR_DSE                    (0x10000)
+#define MCF_SEC_MDISR_KSE                    (0x20000)
+#define MCF_SEC_MDISR_CE                     (0x40000)
+#define MCF_SEC_MDISR_ERE                    (0x80000)
+#define MCF_SEC_MDISR_IE                     (0x100000)
+#define MCF_SEC_MDISR_IFO                    (0x4000000)
+#define MCF_SEC_MDISR_AE                     (0x40000000)
+#define MCF_SEC_MDISR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_MDIMR */
+#define MCF_SEC_MDIMR_DSE                    (0x10000)
+#define MCF_SEC_MDIMR_KSE                    (0x20000)
+#define MCF_SEC_MDIMR_CE                     (0x40000)
+#define MCF_SEC_MDIMR_ERE                    (0x80000)
+#define MCF_SEC_MDIMR_IE                     (0x100000)
+#define MCF_SEC_MDIMR_IFO                    (0x4000000)
+#define MCF_SEC_MDIMR_AE                     (0x40000000)
+#define MCF_SEC_MDIMR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGRCR */
+#define MCF_SEC_RNGRCR_SR                    (0x1000000)
+#define MCF_SEC_RNGRCR_MI                    (0x2000000)
+#define MCF_SEC_RNGRCR_RI                    (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGSR */
+#define MCF_SEC_RNGSR_RD                     (0x1000000)
+#define MCF_SEC_RNGSR_IE                     (0x4000000)
+#define MCF_SEC_RNGSR_OFR                    (0x8000000)
+#define MCF_SEC_RNGSR_HALT                   (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGISR */
+#define MCF_SEC_RNGISR_IE                    (0x100000)
+#define MCF_SEC_RNGISR_OFU                   (0x2000000)
+#define MCF_SEC_RNGISR_AE                    (0x40000000)
+#define MCF_SEC_RNGISR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGIMR */
+#define MCF_SEC_RNGIMR_IE                    (0x100000)
+#define MCF_SEC_RNGIMR_OFU                   (0x2000000)
+#define MCF_SEC_RNGIMR_AE                    (0x40000000)
+#define MCF_SEC_RNGIMR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AESRCR */
+#define MCF_SEC_AESRCR_SR                    (0x1000000)
+#define MCF_SEC_AESRCR_MI                    (0x2000000)
+#define MCF_SEC_AESRCR_RI                    (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_AESSR */
+#define MCF_SEC_AESSR_RD                     (0x1000000)
+#define MCF_SEC_AESSR_ID                     (0x2000000)
+#define MCF_SEC_AESSR_IE                     (0x4000000)
+#define MCF_SEC_AESSR_OFR                    (0x8000000)
+#define MCF_SEC_AESSR_IFW                    (0x10000000)
+#define MCF_SEC_AESSR_HALT                   (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_AESISR */
+#define MCF_SEC_AESISR_DSE                   (0x10000)
+#define MCF_SEC_AESISR_KSE                   (0x20000)
+#define MCF_SEC_AESISR_CE                    (0x40000)
+#define MCF_SEC_AESISR_ERE                   (0x80000)
+#define MCF_SEC_AESISR_IE                    (0x100000)
+#define MCF_SEC_AESISR_OFU                   (0x2000000)
+#define MCF_SEC_AESISR_IFO                   (0x4000000)
+#define MCF_SEC_AESISR_IFE                   (0x10000000)
+#define MCF_SEC_AESISR_OFE                   (0x20000000)
+#define MCF_SEC_AESISR_AE                    (0x40000000)
+#define MCF_SEC_AESISR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AESIMR */
+#define MCF_SEC_AESIMR_DSE                   (0x10000)
+#define MCF_SEC_AESIMR_KSE                   (0x20000)
+#define MCF_SEC_AESIMR_CE                    (0x40000)
+#define MCF_SEC_AESIMR_ERE                   (0x80000)
+#define MCF_SEC_AESIMR_IE                    (0x100000)
+#define MCF_SEC_AESIMR_OFU                   (0x2000000)
+#define MCF_SEC_AESIMR_IFO                   (0x4000000)
+#define MCF_SEC_AESIMR_IFE                   (0x10000000)
+#define MCF_SEC_AESIMR_OFE                   (0x20000000)
+#define MCF_SEC_AESIMR_AE                    (0x40000000)
+#define MCF_SEC_AESIMR_ME                    (0x80000000)
+
+
+#endif /* __MCF5475_SEC_H__ */

tos/vmem_test/include/MCF5475_SIU.h

@@ -0,0 +1,67 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SIU_H__
+#define __MCF5475_SIU_H__
+
+
+/*********************************************************************
+*
+* System Integration Unit (SIU)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SIU_SBCR                         (*(volatile uint32_t*)(&_MBAR[0x10]))
+#define MCF_SIU_SECSACR                      (*(volatile uint32_t*)(&_MBAR[0x38]))
+#define MCF_SIU_RSR                          (*(volatile uint32_t*)(&_MBAR[0x44]))
+#define MCF_SIU_JTAGID                       (*(volatile uint32_t*)(&_MBAR[0x50]))
+
+
+/* Bit definitions and macros for MCF_SIU_SBCR */
+#define MCF_SIU_SBCR_PIN2DSPI                (0x8000000)
+#define MCF_SIU_SBCR_DMA2CPU                 (0x10000000)
+#define MCF_SIU_SBCR_CPU2DMA                 (0x20000000)
+#define MCF_SIU_SBCR_PIN2DMA                 (0x40000000)
+#define MCF_SIU_SBCR_PIN2CPU                 (0x80000000)
+
+/* Bit definitions and macros for MCF_SIU_SECSACR */
+#define MCF_SIU_SECSACR_SEQEN                (0x1)
+
+/* Bit definitions and macros for MCF_SIU_RSR */
+#define MCF_SIU_RSR_RST                      (0x1)
+#define MCF_SIU_RSR_RSTWD                    (0x2)
+#define MCF_SIU_RSR_RSTJTG                   (0x8)
+
+/* Bit definitions and macros for MCF_SIU_JTAGID */
+#define MCF_SIU_JTAGID_JTAGID(x)             (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SIU_JTAGID */
+#define MCF_SIU_JTAGID_REV          (0xF0000000)
+#define MCF_SIU_JTAGID_PROCESSOR    (0x0FFFFFFF)
+#define MCF_SIU_JTAGID_MCF5485      (0x0800C01D)
+#define MCF_SIU_JTAGID_MCF5484      (0x0800D01D)
+#define MCF_SIU_JTAGID_MCF5483      (0x0800E01D)
+#define MCF_SIU_JTAGID_MCF5482      (0x0800F01D)
+#define MCF_SIU_JTAGID_MCF5481      (0x0801001D)
+#define MCF_SIU_JTAGID_MCF5480      (0x0801101D)
+#define MCF_SIU_JTAGID_MCF5475      (0x0801201D)
+#define MCF_SIU_JTAGID_MCF5474      (0x0801301D)
+#define MCF_SIU_JTAGID_MCF5473      (0x0801401D)
+#define MCF_SIU_JTAGID_MCF5472      (0x0801501D)
+#define MCF_SIU_JTAGID_MCF5471      (0x0801601D)
+#define MCF_SIU_JTAGID_MCF5470      (0x0801701D)
+
+#endif /* __MCF5475_SIU_H__ */

tos/vmem_test/include/MCF5475_SLT.h

@@ -0,0 +1,59 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SLT_H__
+#define __MCF5475_SLT_H__
+
+
+/*********************************************************************
+*
+* Slice Timers (SLT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SLT0_STCNT                       (*(volatile uint32_t*)(&_MBAR[0x900]))
+#define MCF_SLT0_SCR                         (*(volatile uint32_t*)(&_MBAR[0x904]))
+#define MCF_SLT0_SCNT                        (*(volatile uint32_t*)(&_MBAR[0x908]))
+#define MCF_SLT0_SSR                         (*(volatile uint32_t*)(&_MBAR[0x90C]))
+
+#define MCF_SLT1_STCNT                       (*(volatile uint32_t*)(&_MBAR[0x910]))
+#define MCF_SLT1_SCR                         (*(volatile uint32_t*)(&_MBAR[0x914]))
+#define MCF_SLT1_SCNT                        (*(volatile uint32_t*)(&_MBAR[0x918]))
+#define MCF_SLT1_SSR                         (*(volatile uint32_t*)(&_MBAR[0x91C]))
+
+#define MCF_SLT_STCNT(x)                     (*(volatile uint32_t*)(&_MBAR[0x900 + ((x)*0x10)]))
+#define MCF_SLT_SCR(x)                       (*(volatile uint32_t*)(&_MBAR[0x904 + ((x)*0x10)]))
+#define MCF_SLT_SCNT(x)                      (*(volatile int32_t*)(&_MBAR[0x908 + ((x)*0x10)]))
+#define MCF_SLT_SSR(x)                       (*(volatile uint32_t*)(&_MBAR[0x90C + ((x)*0x10)]))
+
+
+/* Bit definitions and macros for MCF_SLT_STCNT */
+#define MCF_SLT_STCNT_TC(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SLT_SCR */
+#define MCF_SLT_SCR_TEN                      (0x1000000)
+#define MCF_SLT_SCR_IEN                      (0x2000000)
+#define MCF_SLT_SCR_RUN                      (0x4000000)
+
+/* Bit definitions and macros for MCF_SLT_SCNT */
+#define MCF_SLT_SCNT_CNT(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SLT_SSR */
+#define MCF_SLT_SSR_ST                       (0x1000000)
+#define MCF_SLT_SSR_BE                       (0x2000000)
+
+
+#endif /* __MCF5475_SLT_H__ */

tos/vmem_test/include/MCF5475_SRAM.h

@@ -0,0 +1,62 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SRAM_H__
+#define __MCF5475_SRAM_H__
+
+
+/*********************************************************************
+*
+* System SRAM Module (SRAM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SRAM_SSCR                        (*(volatile uint32_t*)(&__MBAR[0x1FFC0]))
+#define MCF_SRAM_TCCR                        (*(volatile uint32_t*)(&__MBAR[0x1FFC4]))
+#define MCF_SRAM_TCCRDR                      (*(volatile uint32_t*)(&__MBAR[0x1FFC8]))
+#define MCF_SRAM_TCCRDW                      (*(volatile uint32_t*)(&__MBAR[0x1FFCC]))
+#define MCF_SRAM_TCCRSEC                     (*(volatile uint32_t*)(&__MBAR[0x1FFD0]))
+
+
+/* Bit definitions and macros for MCF_SRAM_SSCR */
+#define MCF_SRAM_SSCR_INLV                   (0x10000)
+
+/* Bit definitions and macros for MCF_SRAM_TCCR */
+#define MCF_SRAM_TCCR_BANK0_TC(x)            (((x)&0xF)<<0)
+#define MCF_SRAM_TCCR_BANK1_TC(x)            (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCR_BANK2_TC(x)            (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCR_BANK3_TC(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SRAM_TCCRDR */
+#define MCF_SRAM_TCCRDR_BANK0_TC(x)          (((x)&0xF)<<0)
+#define MCF_SRAM_TCCRDR_BANK1_TC(x)          (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCRDR_BANK2_TC(x)          (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCRDR_BANK3_TC(x)          (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SRAM_TCCRDW */
+#define MCF_SRAM_TCCRDW_BANK0_TC(x)          (((x)&0xF)<<0)
+#define MCF_SRAM_TCCRDW_BANK1_TC(x)          (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCRDW_BANK2_TC(x)          (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCRDW_BANK3_TC(x)          (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SRAM_TCCRSEC */
+#define MCF_SRAM_TCCRSEC_BANK0_TC(x)         (((x)&0xF)<<0)
+#define MCF_SRAM_TCCRSEC_BANK1_TC(x)         (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCRSEC_BANK2_TC(x)         (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCRSEC_BANK3_TC(x)         (((x)&0xF)<<0x18)
+
+
+#endif /* __MCF5475_SRAM_H__ */

tos/vmem_test/include/MCF5475_USB.h

@@ -0,0 +1,554 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_USB_H__
+#define __MCF5475_USB_H__
+
+
+/*********************************************************************
+*
+* Universal Serial Bus Interface (USB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_USB_USBAISR                      (*(volatile uint8_t *)(&__MBAR[0xB000]))
+#define MCF_USB_USBAIMR                      (*(volatile uint8_t *)(&__MBAR[0xB001]))
+#define MCF_USB_EPINFO                       (*(volatile uint8_t *)(&__MBAR[0xB003]))
+#define MCF_USB_CFGR                         (*(volatile uint8_t *)(&__MBAR[0xB004]))
+#define MCF_USB_CFGAR                        (*(volatile uint8_t *)(&__MBAR[0xB005]))
+#define MCF_USB_SPEEDR                       (*(volatile uint8_t *)(&__MBAR[0xB006]))
+#define MCF_USB_FRMNUMR                      (*(volatile uint16_t*)(&__MBAR[0xB00E]))
+#define MCF_USB_EPTNR                        (*(volatile uint16_t*)(&__MBAR[0xB010]))
+#define MCF_USB_IFUR                         (*(volatile uint16_t*)(&__MBAR[0xB014]))
+#define MCF_USB_IFR0                         (*(volatile uint16_t*)(&__MBAR[0xB040]))
+#define MCF_USB_IFR1                         (*(volatile uint16_t*)(&__MBAR[0xB042]))
+#define MCF_USB_IFR2                         (*(volatile uint16_t*)(&__MBAR[0xB044]))
+#define MCF_USB_IFR3                         (*(volatile uint16_t*)(&__MBAR[0xB046]))
+#define MCF_USB_IFR4                         (*(volatile uint16_t*)(&__MBAR[0xB048]))
+#define MCF_USB_IFR5                         (*(volatile uint16_t*)(&__MBAR[0xB04A]))
+#define MCF_USB_IFR6                         (*(volatile uint16_t*)(&__MBAR[0xB04C]))
+#define MCF_USB_IFR7                         (*(volatile uint16_t*)(&__MBAR[0xB04E]))
+#define MCF_USB_IFR8                         (*(volatile uint16_t*)(&__MBAR[0xB050]))
+#define MCF_USB_IFR9                         (*(volatile uint16_t*)(&__MBAR[0xB052]))
+#define MCF_USB_IFR10                        (*(volatile uint16_t*)(&__MBAR[0xB054]))
+#define MCF_USB_IFR11                        (*(volatile uint16_t*)(&__MBAR[0xB056]))
+#define MCF_USB_IFR12                        (*(volatile uint16_t*)(&__MBAR[0xB058]))
+#define MCF_USB_IFR13                        (*(volatile uint16_t*)(&__MBAR[0xB05A]))
+#define MCF_USB_IFR14                        (*(volatile uint16_t*)(&__MBAR[0xB05C]))
+#define MCF_USB_IFR15                        (*(volatile uint16_t*)(&__MBAR[0xB05E]))
+#define MCF_USB_IFR16                        (*(volatile uint16_t*)(&__MBAR[0xB060]))
+#define MCF_USB_IFR17                        (*(volatile uint16_t*)(&__MBAR[0xB062]))
+#define MCF_USB_IFR18                        (*(volatile uint16_t*)(&__MBAR[0xB064]))
+#define MCF_USB_IFR19                        (*(volatile uint16_t*)(&__MBAR[0xB066]))
+#define MCF_USB_IFR20                        (*(volatile uint16_t*)(&__MBAR[0xB068]))
+#define MCF_USB_IFR21                        (*(volatile uint16_t*)(&__MBAR[0xB06A]))
+#define MCF_USB_IFR22                        (*(volatile uint16_t*)(&__MBAR[0xB06C]))
+#define MCF_USB_IFR23                        (*(volatile uint16_t*)(&__MBAR[0xB06E]))
+#define MCF_USB_IFR24                        (*(volatile uint16_t*)(&__MBAR[0xB070]))
+#define MCF_USB_IFR25                        (*(volatile uint16_t*)(&__MBAR[0xB072]))
+#define MCF_USB_IFR26                        (*(volatile uint16_t*)(&__MBAR[0xB074]))
+#define MCF_USB_IFR27                        (*(volatile uint16_t*)(&__MBAR[0xB076]))
+#define MCF_USB_IFR28                        (*(volatile uint16_t*)(&__MBAR[0xB078]))
+#define MCF_USB_IFR29                        (*(volatile uint16_t*)(&__MBAR[0xB07A]))
+#define MCF_USB_IFR30                        (*(volatile uint16_t*)(&__MBAR[0xB07C]))
+#define MCF_USB_IFR31                        (*(volatile uint16_t*)(&__MBAR[0xB07E]))
+#define MCF_USB_PPCNT                        (*(volatile uint16_t*)(&__MBAR[0xB080]))
+#define MCF_USB_DPCNT                        (*(volatile uint16_t*)(&__MBAR[0xB082]))
+#define MCF_USB_CRCECNT                      (*(volatile uint16_t*)(&__MBAR[0xB084]))
+#define MCF_USB_BSECNT                       (*(volatile uint16_t*)(&__MBAR[0xB086]))
+#define MCF_USB_PIDECNT                      (*(volatile uint16_t*)(&__MBAR[0xB088]))
+#define MCF_USB_FRMECNT                      (*(volatile uint16_t*)(&__MBAR[0xB08A]))
+#define MCF_USB_TXPCNT                       (*(volatile uint16_t*)(&__MBAR[0xB08C]))
+#define MCF_USB_CNTOVR                       (*(volatile uint8_t *)(&__MBAR[0xB08E]))
+#define MCF_USB_EP0ACR                       (*(volatile uint8_t *)(&__MBAR[0xB101]))
+#define MCF_USB_EP0MPSR                      (*(volatile uint16_t*)(&__MBAR[0xB102]))
+#define MCF_USB_EP0IFR                       (*(volatile uint8_t *)(&__MBAR[0xB104]))
+#define MCF_USB_EP0SR                        (*(volatile uint8_t *)(&__MBAR[0xB105]))
+#define MCF_USB_BMRTR                        (*(volatile uint8_t *)(&__MBAR[0xB106]))
+#define MCF_USB_BRTR                         (*(volatile uint8_t *)(&__MBAR[0xB107]))
+#define MCF_USB_WVALUER                      (*(volatile uint16_t*)(&__MBAR[0xB108]))
+#define MCF_USB_WINDEXR                      (*(volatile uint16_t*)(&__MBAR[0xB10A]))
+#define MCF_USB_WLENGTHR                     (*(volatile uint16_t*)(&__MBAR[0xB10C]))
+#define MCF_USB_EP1OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB131]))
+#define MCF_USB_EP1OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB132]))
+#define MCF_USB_EP1OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB134]))
+#define MCF_USB_EP1OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB135]))
+#define MCF_USB_EP1OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB13E]))
+#define MCF_USB_EP1INACR                     (*(volatile uint8_t *)(&__MBAR[0xB149]))
+#define MCF_USB_EP1INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB14A]))
+#define MCF_USB_EP1INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB14C]))
+#define MCF_USB_EP1INSR                      (*(volatile uint8_t *)(&__MBAR[0xB14D]))
+#define MCF_USB_EP1INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB156]))
+#define MCF_USB_EP2OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB161]))
+#define MCF_USB_EP2OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB162]))
+#define MCF_USB_EP2OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB164]))
+#define MCF_USB_EP2OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB165]))
+#define MCF_USB_EP2OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB16E]))
+#define MCF_USB_EP2INACR                     (*(volatile uint8_t *)(&__MBAR[0xB179]))
+#define MCF_USB_EP2INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB17A]))
+#define MCF_USB_EP2INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB17C]))
+#define MCF_USB_EP2INSR                      (*(volatile uint8_t *)(&__MBAR[0xB17D]))
+#define MCF_USB_EP2INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB186]))
+#define MCF_USB_EP3OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB191]))
+#define MCF_USB_EP3OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB192]))
+#define MCF_USB_EP3OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB194]))
+#define MCF_USB_EP3OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB195]))
+#define MCF_USB_EP3OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB19E]))
+#define MCF_USB_EP3INACR                     (*(volatile uint8_t *)(&__MBAR[0xB1A9]))
+#define MCF_USB_EP3INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB1AA]))
+#define MCF_USB_EP3INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB1AC]))
+#define MCF_USB_EP3INSR                      (*(volatile uint8_t *)(&__MBAR[0xB1AD]))
+#define MCF_USB_EP3INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB1B6]))
+#define MCF_USB_EP4OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB1C1]))
+#define MCF_USB_EP4OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB1C2]))
+#define MCF_USB_EP4OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB1C4]))
+#define MCF_USB_EP4OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB1C5]))
+#define MCF_USB_EP4OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB1CE]))
+#define MCF_USB_EP4INACR                     (*(volatile uint8_t *)(&__MBAR[0xB1D9]))
+#define MCF_USB_EP4INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB1DA]))
+#define MCF_USB_EP4INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB1DC]))
+#define MCF_USB_EP4INSR                      (*(volatile uint8_t *)(&__MBAR[0xB1DD]))
+#define MCF_USB_EP4INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB1E6]))
+#define MCF_USB_EP5OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB1F1]))
+#define MCF_USB_EP5OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB1F2]))
+#define MCF_USB_EP5OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB1F4]))
+#define MCF_USB_EP5OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB1F5]))
+#define MCF_USB_EP5OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB1FE]))
+#define MCF_USB_EP5INACR                     (*(volatile uint8_t *)(&__MBAR[0xB209]))
+#define MCF_USB_EP5INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB20A]))
+#define MCF_USB_EP5INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB20C]))
+#define MCF_USB_EP5INSR                      (*(volatile uint8_t *)(&__MBAR[0xB20D]))
+#define MCF_USB_EP5INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB216]))
+#define MCF_USB_EP6OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB221]))
+#define MCF_USB_EP6OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB222]))
+#define MCF_USB_EP6OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB224]))
+#define MCF_USB_EP6OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB225]))
+#define MCF_USB_EP6OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB22E]))
+#define MCF_USB_EP6INACR                     (*(volatile uint8_t *)(&__MBAR[0xB239]))
+#define MCF_USB_EP6INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB23A]))
+#define MCF_USB_EP6INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB23C]))
+#define MCF_USB_EP6INSR                      (*(volatile uint8_t *)(&__MBAR[0xB23D]))
+#define MCF_USB_EP6INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB246]))
+#define MCF_USB_USBSR                        (*(volatile uint32_t*)(&__MBAR[0xB400]))
+#define MCF_USB_USBCR                        (*(volatile uint32_t*)(&__MBAR[0xB404]))
+#define MCF_USB_DRAMCR                       (*(volatile uint32_t*)(&__MBAR[0xB408]))
+#define MCF_USB_DRAMDR                       (*(volatile uint32_t*)(&__MBAR[0xB40C]))
+#define MCF_USB_USBISR                       (*(volatile uint32_t*)(&__MBAR[0xB410]))
+#define MCF_USB_USBIMR                       (*(volatile uint32_t*)(&__MBAR[0xB414]))
+#define MCF_USB_EP0STAT                      (*(volatile uint32_t*)(&__MBAR[0xB440]))
+#define MCF_USB_EP0ISR                       (*(volatile uint32_t*)(&__MBAR[0xB444]))
+#define MCF_USB_EP0IMR                       (*(volatile uint32_t*)(&__MBAR[0xB448]))
+#define MCF_USB_EP0FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB44C]))
+#define MCF_USB_EP0FDR                       (*(volatile uint32_t*)(&__MBAR[0xB450]))
+#define MCF_USB_EP0FSR                       (*(volatile uint32_t*)(&__MBAR[0xB454]))
+#define MCF_USB_EP0FCR                       (*(volatile uint32_t*)(&__MBAR[0xB458]))
+#define MCF_USB_EP0FAR                       (*(volatile uint32_t*)(&__MBAR[0xB45C]))
+#define MCF_USB_EP0FRP                       (*(volatile uint32_t*)(&__MBAR[0xB460]))
+#define MCF_USB_EP0FWP                       (*(volatile uint32_t*)(&__MBAR[0xB464]))
+#define MCF_USB_EP0LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB468]))
+#define MCF_USB_EP0LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB46C]))
+#define MCF_USB_EP1STAT                      (*(volatile uint32_t*)(&__MBAR[0xB470]))
+#define MCF_USB_EP1ISR                       (*(volatile uint32_t*)(&__MBAR[0xB474]))
+#define MCF_USB_EP1IMR                       (*(volatile uint32_t*)(&__MBAR[0xB478]))
+#define MCF_USB_EP1FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB47C]))
+#define MCF_USB_EP1FDR                       (*(volatile uint32_t*)(&__MBAR[0xB480]))
+#define MCF_USB_EP1FSR                       (*(volatile uint32_t*)(&__MBAR[0xB484]))
+#define MCF_USB_EP1FCR                       (*(volatile uint32_t*)(&__MBAR[0xB488]))
+#define MCF_USB_EP1FAR                       (*(volatile uint32_t*)(&__MBAR[0xB48C]))
+#define MCF_USB_EP1FRP                       (*(volatile uint32_t*)(&__MBAR[0xB490]))
+#define MCF_USB_EP1FWP                       (*(volatile uint32_t*)(&__MBAR[0xB494]))
+#define MCF_USB_EP1LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB498]))
+#define MCF_USB_EP1LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB49C]))
+#define MCF_USB_EP2STAT                      (*(volatile uint32_t*)(&__MBAR[0xB4A0]))
+#define MCF_USB_EP2ISR                       (*(volatile uint32_t*)(&__MBAR[0xB4A4]))
+#define MCF_USB_EP2IMR                       (*(volatile uint32_t*)(&__MBAR[0xB4A8]))
+#define MCF_USB_EP2FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB4AC]))
+#define MCF_USB_EP2FDR                       (*(volatile uint32_t*)(&__MBAR[0xB4B0]))
+#define MCF_USB_EP2FSR                       (*(volatile uint32_t*)(&__MBAR[0xB4B4]))
+#define MCF_USB_EP2FCR                       (*(volatile uint32_t*)(&__MBAR[0xB4B8]))
+#define MCF_USB_EP2FAR                       (*(volatile uint32_t*)(&__MBAR[0xB4BC]))
+#define MCF_USB_EP2FRP                       (*(volatile uint32_t*)(&__MBAR[0xB4C0]))
+#define MCF_USB_EP2FWP                       (*(volatile uint32_t*)(&__MBAR[0xB4C4]))
+#define MCF_USB_EP2LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB4C8]))
+#define MCF_USB_EP2LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB4CC]))
+#define MCF_USB_EP3STAT                      (*(volatile uint32_t*)(&__MBAR[0xB4D0]))
+#define MCF_USB_EP3ISR                       (*(volatile uint32_t*)(&__MBAR[0xB4D4]))
+#define MCF_USB_EP3IMR                       (*(volatile uint32_t*)(&__MBAR[0xB4D8]))
+#define MCF_USB_EP3FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB4DC]))
+#define MCF_USB_EP3FDR                       (*(volatile uint32_t*)(&__MBAR[0xB4E0]))
+#define MCF_USB_EP3FSR                       (*(volatile uint32_t*)(&__MBAR[0xB4E4]))
+#define MCF_USB_EP3FCR                       (*(volatile uint32_t*)(&__MBAR[0xB4E8]))
+#define MCF_USB_EP3FAR                       (*(volatile uint32_t*)(&__MBAR[0xB4EC]))
+#define MCF_USB_EP3FRP                       (*(volatile uint32_t*)(&__MBAR[0xB4F0]))
+#define MCF_USB_EP3FWP                       (*(volatile uint32_t*)(&__MBAR[0xB4F4]))
+#define MCF_USB_EP3LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB4F8]))
+#define MCF_USB_EP3LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB4FC]))
+#define MCF_USB_EP4STAT                      (*(volatile uint32_t*)(&__MBAR[0xB500]))
+#define MCF_USB_EP4ISR                       (*(volatile uint32_t*)(&__MBAR[0xB504]))
+#define MCF_USB_EP4IMR                       (*(volatile uint32_t*)(&__MBAR[0xB508]))
+#define MCF_USB_EP4FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB50C]))
+#define MCF_USB_EP4FDR                       (*(volatile uint32_t*)(&__MBAR[0xB510]))
+#define MCF_USB_EP4FSR                       (*(volatile uint32_t*)(&__MBAR[0xB514]))
+#define MCF_USB_EP4FCR                       (*(volatile uint32_t*)(&__MBAR[0xB518]))
+#define MCF_USB_EP4FAR                       (*(volatile uint32_t*)(&__MBAR[0xB51C]))
+#define MCF_USB_EP4FRP                       (*(volatile uint32_t*)(&__MBAR[0xB520]))
+#define MCF_USB_EP4FWP                       (*(volatile uint32_t*)(&__MBAR[0xB524]))
+#define MCF_USB_EP4LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB528]))
+#define MCF_USB_EP4LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB52C]))
+#define MCF_USB_EP5STAT                      (*(volatile uint32_t*)(&__MBAR[0xB530]))
+#define MCF_USB_EP5ISR                       (*(volatile uint32_t*)(&__MBAR[0xB534]))
+#define MCF_USB_EP5IMR                       (*(volatile uint32_t*)(&__MBAR[0xB538]))
+#define MCF_USB_EP5FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB53C]))
+#define MCF_USB_EP5FDR                       (*(volatile uint32_t*)(&__MBAR[0xB540]))
+#define MCF_USB_EP5FSR                       (*(volatile uint32_t*)(&__MBAR[0xB544]))
+#define MCF_USB_EP5FCR                       (*(volatile uint32_t*)(&__MBAR[0xB548]))
+#define MCF_USB_EP5FAR                       (*(volatile uint32_t*)(&__MBAR[0xB54C]))
+#define MCF_USB_EP5FRP                       (*(volatile uint32_t*)(&__MBAR[0xB550]))
+#define MCF_USB_EP5FWP                       (*(volatile uint32_t*)(&__MBAR[0xB554]))
+#define MCF_USB_EP5LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB558]))
+#define MCF_USB_EP5LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB55C]))
+#define MCF_USB_EP6STAT                      (*(volatile uint32_t*)(&__MBAR[0xB560]))
+#define MCF_USB_EP6ISR                       (*(volatile uint32_t*)(&__MBAR[0xB564]))
+#define MCF_USB_EP6IMR                       (*(volatile uint32_t*)(&__MBAR[0xB568]))
+#define MCF_USB_EP6FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB56C]))
+#define MCF_USB_EP6FDR                       (*(volatile uint32_t*)(&__MBAR[0xB570]))
+#define MCF_USB_EP6FSR                       (*(volatile uint32_t*)(&__MBAR[0xB574]))
+#define MCF_USB_EP6FCR                       (*(volatile uint32_t*)(&__MBAR[0xB578]))
+#define MCF_USB_EP6FAR                       (*(volatile uint32_t*)(&__MBAR[0xB57C]))
+#define MCF_USB_EP6FRP                       (*(volatile uint32_t*)(&__MBAR[0xB580]))
+#define MCF_USB_EP6FWP                       (*(volatile uint32_t*)(&__MBAR[0xB584]))
+#define MCF_USB_EP6LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB588]))
+#define MCF_USB_EP6LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB58C]))
+#define MCF_USB_IFR(x)                       (*(volatile uint16_t*)(&__MBAR[0xB040 + ((x)*0x2)]))
+#define MCF_USB_EPOUTACR(x)                  (*(volatile uint8_t *)(&__MBAR[0xB131 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTMPSR(x)                 (*(volatile uint16_t*)(&__MBAR[0xB132 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTIFR(x)                  (*(volatile uint8_t *)(&__MBAR[0xB134 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTSR(x)                   (*(volatile uint8_t *)(&__MBAR[0xB135 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTSFR(x)                  (*(volatile uint16_t*)(&__MBAR[0xB13E + ((x-1)*0x30)]))
+#define MCF_USB_EPINACR(x)                   (*(volatile uint8_t *)(&__MBAR[0xB149 + ((x-1)*0x30)]))
+#define MCF_USB_EPINMPSR(x)                  (*(volatile uint16_t*)(&__MBAR[0xB14A + ((x-1)*0x30)]))
+#define MCF_USB_EPINIFR(x)                   (*(volatile uint8_t *)(&__MBAR[0xB14C + ((x-1)*0x30)]))
+#define MCF_USB_EPINSR(x)                    (*(volatile uint8_t *)(&__MBAR[0xB14D + ((x-1)*0x30)]))
+#define MCF_USB_EPINSFR(x)                   (*(volatile uint16_t*)(&__MBAR[0xB156 + ((x-1)*0x30)]))
+#define MCF_USB_EPSTAT(x)                    (*(volatile uint32_t*)(&__MBAR[0xB440 + ((x)*0x30)]))
+#define MCF_USB_EPISR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB444 + ((x)*0x30)]))
+#define MCF_USB_EPIMR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB448 + ((x)*0x30)]))
+#define MCF_USB_EPFRCFGR(x)                  (*(volatile uint32_t*)(&__MBAR[0xB44C + ((x)*0x30)]))
+#define MCF_USB_EPFDR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB450 + ((x)*0x30)]))
+#define MCF_USB_EPFSR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB454 + ((x)*0x30)]))
+#define MCF_USB_EPFCR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB458 + ((x)*0x30)]))
+#define MCF_USB_EPFAR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB45C + ((x)*0x30)]))
+#define MCF_USB_EPFRP(x)                     (*(volatile uint32_t*)(&__MBAR[0xB460 + ((x)*0x30)]))
+#define MCF_USB_EPFWP(x)                     (*(volatile uint32_t*)(&__MBAR[0xB464 + ((x)*0x30)]))
+#define MCF_USB_EPLRFP(x)                    (*(volatile uint32_t*)(&__MBAR[0xB468 + ((x)*0x30)]))
+#define MCF_USB_EPLWFP(x)                    (*(volatile uint32_t*)(&__MBAR[0xB46C + ((x)*0x30)]))
+
+
+/* Bit definitions and macros for MCF_USB_USBAISR */
+#define MCF_USB_USBAISR_SETUP                (0x1)
+#define MCF_USB_USBAISR_IN                   (0x2)
+#define MCF_USB_USBAISR_OUT                  (0x4)
+#define MCF_USB_USBAISR_EPHALT               (0x8)
+#define MCF_USB_USBAISR_TRANSERR             (0x10)
+#define MCF_USB_USBAISR_ACK                  (0x20)
+#define MCF_USB_USBAISR_CTROVFL              (0x40)
+#define MCF_USB_USBAISR_EPSTALL              (0x80)
+
+/* Bit definitions and macros for MCF_USB_USBAIMR */
+#define MCF_USB_USBAIMR_SETUPEN              (0x1)
+#define MCF_USB_USBAIMR_INEN                 (0x2)
+#define MCF_USB_USBAIMR_OUTEN                (0x4)
+#define MCF_USB_USBAIMR_EPHALTEN             (0x8)
+#define MCF_USB_USBAIMR_TRANSERREN           (0x10)
+#define MCF_USB_USBAIMR_ACKEN                (0x20)
+#define MCF_USB_USBAIMR_CTROVFLEN            (0x40)
+#define MCF_USB_USBAIMR_EPSTALLEN            (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPINFO */
+#define MCF_USB_EPINFO_EPDIR                 (0x1)
+#define MCF_USB_EPINFO_EPNUM(x)              (((x)&0x7)<<0x1)
+
+/* Bit definitions and macros for MCF_USB_CFGR */
+#define MCF_USB_CFGR_Configuration_Value(x)  (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_CFGAR */
+#define MCF_USB_CFGAR_RESERVED               (0xA0)
+#define MCF_USB_CFGAR_RMTWKEUP               (0xE0)
+
+/* Bit definitions and macros for MCF_USB_SPEEDR */
+#define MCF_USB_SPEEDR_SPEED(x)              (((x)&0x3)<<0)
+
+/* Bit definitions and macros for MCF_USB_FRMNUMR */
+#define MCF_USB_FRMNUMR_FRMNUM(x)            (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPTNR */
+#define MCF_USB_EPTNR_EP1T(x)                (((x)&0x3)<<0)
+#define MCF_USB_EPTNR_EP2T(x)                (((x)&0x3)<<0x2)
+#define MCF_USB_EPTNR_EP3T(x)                (((x)&0x3)<<0x4)
+#define MCF_USB_EPTNR_EP4T(x)                (((x)&0x3)<<0x6)
+#define MCF_USB_EPTNR_EP5T(x)                (((x)&0x3)<<0x8)
+#define MCF_USB_EPTNR_EP6T(x)                (((x)&0x3)<<0xA)
+#define MCF_USB_EPTNR_EPnT1                  (0)
+#define MCF_USB_EPTNR_EPnT2                  (0x1)
+#define MCF_USB_EPTNR_EPnT3                  (0x2)
+
+/* Bit definitions and macros for MCF_USB_IFUR */
+#define MCF_USB_IFUR_ALTSET(x)               (((x)&0xFF)<<0)
+#define MCF_USB_IFUR_IFNUM(x)                (((x)&0xFF)<<0x8)
+
+/* Bit definitions and macros for MCF_USB_IFR */
+#define MCF_USB_IFR_ALTSET(x)                (((x)&0xFF)<<0)
+#define MCF_USB_IFR_IFNUM(x)                 (((x)&0xFF)<<0x8)
+
+/* Bit definitions and macros for MCF_USB_PPCNT */
+#define MCF_USB_PPCNT_PPCNT(x)               (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_DPCNT */
+#define MCF_USB_DPCNT_DPCNT(x)               (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_CRCECNT */
+#define MCF_USB_CRCECNT_CRCECNT(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_BSECNT */
+#define MCF_USB_BSECNT_BSECNT(x)             (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_PIDECNT */
+#define MCF_USB_PIDECNT_PIDECNT(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_FRMECNT */
+#define MCF_USB_FRMECNT_FRMECNT(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_TXPCNT */
+#define MCF_USB_TXPCNT_TXPCNT(x)             (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_CNTOVR */
+#define MCF_USB_CNTOVR_PPCNT                 (0x1)
+#define MCF_USB_CNTOVR_DPCNT                 (0x2)
+#define MCF_USB_CNTOVR_CRCECNT               (0x4)
+#define MCF_USB_CNTOVR_BSECNT                (0x8)
+#define MCF_USB_CNTOVR_PIDECNT               (0x10)
+#define MCF_USB_CNTOVR_FRMECNT               (0x20)
+#define MCF_USB_CNTOVR_TXPCNT                (0x40)
+
+/* Bit definitions and macros for MCF_USB_EP0ACR */
+#define MCF_USB_EP0ACR_TTYPE(x)              (((x)&0x3)<<0)
+#define MCF_USB_EP0ACR_TTYPE_CTRL            (0)
+#define MCF_USB_EP0ACR_TTYPE_ISOC            (0x1)
+#define MCF_USB_EP0ACR_TTYPE_BULK            (0x2)
+#define MCF_USB_EP0ACR_TTYPE_INT             (0x3)
+
+/* Bit definitions and macros for MCF_USB_EP0MPSR */
+#define MCF_USB_EP0MPSR_MAXPKTSZ(x)          (((x)&0x7FF)<<0)
+#define MCF_USB_EP0MPSR_ADDTRANS(x)          (((x)&0x3)<<0xB)
+
+/* Bit definitions and macros for MCF_USB_EP0IFR */
+#define MCF_USB_EP0IFR_IFNUM(x)              (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EP0SR */
+#define MCF_USB_EP0SR_HALT                   (0x1)
+#define MCF_USB_EP0SR_ACTIVE                 (0x2)
+#define MCF_USB_EP0SR_PSTALL                 (0x4)
+#define MCF_USB_EP0SR_CCOMP                  (0x8)
+#define MCF_USB_EP0SR_TXZERO                 (0x20)
+#define MCF_USB_EP0SR_INT                    (0x80)
+
+/* Bit definitions and macros for MCF_USB_BMRTR */
+#define MCF_USB_BMRTR_REC(x)                 (((x)&0x1F)<<0)
+#define MCF_USB_BMRTR_REC_DEVICE             (0)
+#define MCF_USB_BMRTR_REC_INTERFACE          (0x1)
+#define MCF_USB_BMRTR_REC_ENDPOINT           (0x2)
+#define MCF_USB_BMRTR_REC_OTHER              (0x3)
+#define MCF_USB_BMRTR_TYPE(x)                (((x)&0x3)<<0x5)
+#define MCF_USB_BMRTR_TYPE_STANDARD          (0)
+#define MCF_USB_BMRTR_TYPE_CLASS             (0x20)
+#define MCF_USB_BMRTR_TYPE_VENDOR            (0x40)
+#define MCF_USB_BMRTR_DIR                    (0x80)
+
+/* Bit definitions and macros for MCF_USB_BRTR */
+#define MCF_USB_BRTR_BREQ(x)                 (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_WVALUER */
+#define MCF_USB_WVALUER_WVALUE(x)            (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_WINDEXR */
+#define MCF_USB_WINDEXR_WINDEX(x)            (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_WLENGTHR */
+#define MCF_USB_WLENGTHR_WLENGTH(x)          (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPOUTACR */
+#define MCF_USB_EPOUTACR_TTYPE(x)            (((x)&0x3)<<0)
+#define MCF_USB_EPOUTACR_TTYPE_ISOC          (0x1)
+#define MCF_USB_EPOUTACR_TTYPE_BULK          (0x2)
+#define MCF_USB_EPOUTACR_TTYPE_INT           (0x3)
+
+/* Bit definitions and macros for MCF_USB_EPOUTMPSR */
+#define MCF_USB_EPOUTMPSR_MAXPKTSZ(x)        (((x)&0x7FF)<<0)
+#define MCF_USB_EPOUTMPSR_ADDTRANS(x)        (((x)&0x3)<<0xB)
+
+/* Bit definitions and macros for MCF_USB_EPOUTIFR */
+#define MCF_USB_EPOUTIFR_IFNUM(x)            (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPOUTSR */
+#define MCF_USB_EPOUTSR_HALT                 (0x1)
+#define MCF_USB_EPOUTSR_ACTIVE               (0x2)
+#define MCF_USB_EPOUTSR_PSTALL               (0x4)
+#define MCF_USB_EPOUTSR_CCOMP                (0x8)
+#define MCF_USB_EPOUTSR_TXZERO               (0x20)
+#define MCF_USB_EPOUTSR_INT                  (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPOUTSFR */
+#define MCF_USB_EPOUTSFR_FRMNUM(x)           (((x)&0x7FF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPINACR */
+#define MCF_USB_EPINACR_TTYPE(x)             (((x)&0x3)<<0)
+#define MCF_USB_EPINACR_TTYPE_ISOC           (0x1)
+#define MCF_USB_EPINACR_TTYPE_BULK           (0x2)
+#define MCF_USB_EPINACR_TTYPE_INT            (0x3)
+
+/* Bit definitions and macros for MCF_USB_EPINMPSR */
+#define MCF_USB_EPINMPSR_MAXPKTSZ(x)         (((x)&0x7FF)<<0)
+#define MCF_USB_EPINMPSR_ADDTRANS(x)         (((x)&0x3)<<0xB)
+
+/* Bit definitions and macros for MCF_USB_EPINIFR */
+#define MCF_USB_EPINIFR_IFNUM(x)             (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPINSR */
+#define MCF_USB_EPINSR_HALT                  (0x1)
+#define MCF_USB_EPINSR_ACTIVE                (0x2)
+#define MCF_USB_EPINSR_PSTALL                (0x4)
+#define MCF_USB_EPINSR_CCOMP                 (0x8)
+#define MCF_USB_EPINSR_TXZERO                (0x20)
+#define MCF_USB_EPINSR_INT                   (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPINSFR */
+#define MCF_USB_EPINSFR_FRMNUM(x)            (((x)&0x7FF)<<0)
+
+/* Bit definitions and macros for MCF_USB_USBSR */
+#define MCF_USB_USBSR_ISOERREP(x)            (((x)&0xF)<<0)
+#define MCF_USB_USBSR_SUSP                   (0x80)
+
+/* Bit definitions and macros for MCF_USB_USBCR */
+#define MCF_USB_USBCR_RESUME                 (0x1)
+#define MCF_USB_USBCR_APPLOCK                (0x2)
+#define MCF_USB_USBCR_RST                    (0x4)
+#define MCF_USB_USBCR_RAMEN                  (0x8)
+#define MCF_USB_USBCR_RAMSPLIT               (0x20)
+
+/* Bit definitions and macros for MCF_USB_DRAMCR */
+#define MCF_USB_DRAMCR_DADR(x)               (((x)&0x3FF)<<0)
+#define MCF_USB_DRAMCR_DSIZE(x)              (((x)&0x7FF)<<0x10)
+#define MCF_USB_DRAMCR_BSY                   (0x40000000)
+#define MCF_USB_DRAMCR_START                 (0x80000000)
+
+/* Bit definitions and macros for MCF_USB_DRAMDR */
+#define MCF_USB_DRAMDR_DDAT(x)               (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_USBISR */
+#define MCF_USB_USBISR_ISOERR                (0x1)
+#define MCF_USB_USBISR_FTUNLCK               (0x2)
+#define MCF_USB_USBISR_SUSP                  (0x4)
+#define MCF_USB_USBISR_RES                   (0x8)
+#define MCF_USB_USBISR_UPDSOF                (0x10)
+#define MCF_USB_USBISR_RSTSTOP               (0x20)
+#define MCF_USB_USBISR_SOF                   (0x40)
+#define MCF_USB_USBISR_MSOF                  (0x80)
+
+/* Bit definitions and macros for MCF_USB_USBIMR */
+#define MCF_USB_USBIMR_ISOERR                (0x1)
+#define MCF_USB_USBIMR_FTUNLCK               (0x2)
+#define MCF_USB_USBIMR_SUSP                  (0x4)
+#define MCF_USB_USBIMR_RES                   (0x8)
+#define MCF_USB_USBIMR_UPDSOF                (0x10)
+#define MCF_USB_USBIMR_RSTSTOP               (0x20)
+#define MCF_USB_USBIMR_SOF                   (0x40)
+#define MCF_USB_USBIMR_MSOF                  (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPSTAT */
+#define MCF_USB_EPSTAT_RST                   (0x1)
+#define MCF_USB_EPSTAT_FLUSH                 (0x2)
+#define MCF_USB_EPSTAT_DIR                   (0x80)
+#define MCF_USB_EPSTAT_BYTECNT(x)            (((x)&0xFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_USB_EPISR */
+#define MCF_USB_EPISR_EOF                    (0x1)
+#define MCF_USB_EPISR_EOT                    (0x4)
+#define MCF_USB_EPISR_FIFOLO                 (0x10)
+#define MCF_USB_EPISR_FIFOHI                 (0x20)
+#define MCF_USB_EPISR_ERR                    (0x40)
+#define MCF_USB_EPISR_EMT                    (0x80)
+#define MCF_USB_EPISR_FU                     (0x100)
+
+/* Bit definitions and macros for MCF_USB_EPIMR */
+#define MCF_USB_EPIMR_EOF                    (0x1)
+#define MCF_USB_EPIMR_EOT                    (0x4)
+#define MCF_USB_EPIMR_FIFOLO                 (0x10)
+#define MCF_USB_EPIMR_FIFOHI                 (0x20)
+#define MCF_USB_EPIMR_ERR                    (0x40)
+#define MCF_USB_EPIMR_EMT                    (0x80)
+#define MCF_USB_EPIMR_FU                     (0x100)
+
+/* Bit definitions and macros for MCF_USB_EPFRCFGR */
+#define MCF_USB_EPFRCFGR_DEPTH(x)            (((x)&0x1FFF)<<0)
+#define MCF_USB_EPFRCFGR_BASE(x)             (((x)&0xFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_USB_EPFDR */
+#define MCF_USB_EPFDR_RX_TXDATA(x)           (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPFSR */
+#define MCF_USB_EPFSR_EMT                    (0x10000)
+#define MCF_USB_EPFSR_ALRM                   (0x20000)
+#define MCF_USB_EPFSR_FU                     (0x40000)
+#define MCF_USB_EPFSR_FR                     (0x80000)
+#define MCF_USB_EPFSR_OF                     (0x100000)
+#define MCF_USB_EPFSR_UF                     (0x200000)
+#define MCF_USB_EPFSR_RXW                    (0x400000)
+#define MCF_USB_EPFSR_FAE                    (0x800000)
+#define MCF_USB_EPFSR_FRM(x)                 (((x)&0xF)<<0x18)
+#define MCF_USB_EPFSR_TXW                    (0x40000000)
+#define MCF_USB_EPFSR_IP                     (0x80000000)
+
+/* Bit definitions and macros for MCF_USB_EPFCR */
+#define MCF_USB_EPFCR_COUNTER(x)             (((x)&0xFFFF)<<0)
+#define MCF_USB_EPFCR_TXWMSK                 (0x40000)
+#define MCF_USB_EPFCR_OFMSK                  (0x80000)
+#define MCF_USB_EPFCR_UFMSK                  (0x100000)
+#define MCF_USB_EPFCR_RXWMSK                 (0x200000)
+#define MCF_USB_EPFCR_FAEMSK                 (0x400000)
+#define MCF_USB_EPFCR_IPMSK                  (0x800000)
+#define MCF_USB_EPFCR_GR(x)                  (((x)&0x7)<<0x18)
+#define MCF_USB_EPFCR_FRM                    (0x8000000)
+#define MCF_USB_EPFCR_TMR                    (0x10000000)
+#define MCF_USB_EPFCR_WFR                    (0x20000000)
+#define MCF_USB_EPFCR_SHAD                   (0x80000000)
+
+/* Bit definitions and macros for MCF_USB_EPFAR */
+#define MCF_USB_EPFAR_ALRMP(x)               (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPFRP */
+#define MCF_USB_EPFRP_RP(x)                  (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPFWP */
+#define MCF_USB_EPFWP_WP(x)                  (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPLRFP */
+#define MCF_USB_EPLRFP_LRFP(x)               (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPLWFP */
+#define MCF_USB_EPLWFP_LWFP(x)               (((x)&0xFFF)<<0)
+
+
+#endif /* __MCF5475_USB_H__ */

tos/vmem_test/include/MCF5475_XLB.h

@@ -0,0 +1,101 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_XLB_H__
+#define __MCF5475_XLB_H__
+
+
+/*********************************************************************
+*
+* XL Bus Arbiter (XLB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_XLB_XARB_CFG                     (*(volatile uint32_t*)(&_MBAR[0x240]))
+#define MCF_XLB_XARB_VER                     (*(volatile uint32_t*)(&_MBAR[0x244]))
+#define MCF_XLB_XARB_SR                      (*(volatile uint32_t*)(&_MBAR[0x248]))
+#define MCF_XLB_XARB_IMR                     (*(volatile uint32_t*)(&_MBAR[0x24C]))
+#define MCF_XLB_XARB_ADRCAP                  (*(volatile uint32_t*)(&_MBAR[0x250]))
+#define MCF_XLB_XARB_SIGCAP                  (*(volatile uint32_t*)(&_MBAR[0x254]))
+#define MCF_XLB_XARB_ADRTO                   (*(volatile uint32_t*)(&_MBAR[0x258]))
+#define MCF_XLB_XARB_DATTO                   (*(volatile uint32_t*)(&_MBAR[0x25C]))
+#define MCF_XLB_XARB_BUSTO                   (*(volatile uint32_t*)(&_MBAR[0x260]))
+#define MCF_XLB_XARB_PRIEN                   (*(volatile uint32_t*)(&_MBAR[0x264]))
+#define MCF_XLB_XARB_PRI                     (*(volatile uint32_t*)(&_MBAR[0x268]))
+
+
+/* Bit definitions and macros for MCF_XLB_XARB_CFG */
+#define MCF_XLB_XARB_CFG_AT                  (0x2)
+#define MCF_XLB_XARB_CFG_DT                  (0x4)
+#define MCF_XLB_XARB_CFG_BA                  (0x8)
+#define MCF_XLB_XARB_CFG_PM(x)               (((x)&0x3)<<0x5)
+#define MCF_XLB_XARB_CFG_SP(x)               (((x)&0x7)<<0x8)
+#define MCF_XLB_XARB_CFG_PLDIS               (0x80000000)
+
+/* Bit definitions and macros for MCF_XLB_XARB_VER */
+#define MCF_XLB_XARB_VER_VER(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_SR */
+#define MCF_XLB_XARB_SR_AT                   (0x1)
+#define MCF_XLB_XARB_SR_DT                   (0x2)
+#define MCF_XLB_XARB_SR_BA                   (0x4)
+#define MCF_XLB_XARB_SR_TTM                  (0x8)
+#define MCF_XLB_XARB_SR_ECW                  (0x10)
+#define MCF_XLB_XARB_SR_TTR                  (0x20)
+#define MCF_XLB_XARB_SR_TTA                  (0x40)
+#define MCF_XLB_XARB_SR_MM                   (0x80)
+#define MCF_XLB_XARB_SR_SEA                  (0x100)
+
+/* Bit definitions and macros for MCF_XLB_XARB_IMR */
+#define MCF_XLB_XARB_IMR_ATE                 (0x1)
+#define MCF_XLB_XARB_IMR_DTE                 (0x2)
+#define MCF_XLB_XARB_IMR_BAE                 (0x4)
+#define MCF_XLB_XARB_IMR_TTME                (0x8)
+#define MCF_XLB_XARB_IMR_ECWE                (0x10)
+#define MCF_XLB_XARB_IMR_TTRE                (0x20)
+#define MCF_XLB_XARB_IMR_TTAE                (0x40)
+#define MCF_XLB_XARB_IMR_MME                 (0x80)
+#define MCF_XLB_XARB_IMR_SEAE                (0x100)
+
+/* Bit definitions and macros for MCF_XLB_XARB_ADRCAP */
+#define MCF_XLB_XARB_ADRCAP_ADRCAP(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_SIGCAP */
+#define MCF_XLB_XARB_SIGCAP_TT(x)            (((x)&0x1F)<<0)
+#define MCF_XLB_XARB_SIGCAP_TBST             (0x20)
+#define MCF_XLB_XARB_SIGCAP_TSIZ(x)          (((x)&0x7)<<0x7)
+
+/* Bit definitions and macros for MCF_XLB_XARB_ADRTO */
+#define MCF_XLB_XARB_ADRTO_ADRTO(x)          (((x)&0xFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_DATTO */
+#define MCF_XLB_XARB_DATTO_DATTO(x)          (((x)&0xFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_BUSTO */
+#define MCF_XLB_XARB_BUSTO_BUSTO(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_PRIEN */
+#define MCF_XLB_XARB_PRIEN_M0                (0x1)
+#define MCF_XLB_XARB_PRIEN_M2                (0x4)
+#define MCF_XLB_XARB_PRIEN_M3                (0x8)
+
+/* Bit definitions and macros for MCF_XLB_XARB_PRI */
+#define MCF_XLB_XARB_PRI_M0P(x)              (((x)&0x7)<<0)
+#define MCF_XLB_XARB_PRI_M2P(x)              (((x)&0x7)<<0x8)
+#define MCF_XLB_XARB_PRI_M3P(x)              (((x)&0x7)<<0xC)
+
+
+#endif /* __MCF5475_XLB_H__ */

tos/vmem_test/include/bas_printf.h

@@ -0,0 +1,35 @@
+/*
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef _BAS_PRINTF_H_
+#define _BAS_PRINTF_H_
+#include <stdarg.h>
+#include <stddef.h>
+
+extern void xvsnprintf(char *str, size_t size, const char *fmt, va_list va);
+extern void xvprintf(const char *fmt, va_list va);
+extern void xprintf(const char *fmt, ...);
+extern void xsnprintf(char *str, size_t size, const char *fmt, ...);
+extern void xputchar(int c);
+extern int sprintf(char *str, const char *format, ...);
+
+
+extern void display_progress(void);
+extern void hexdump(uint8_t buffer[], int size);
+#endif /* _BAS_PRINTF_H_ */

tos/vmem_test/include/bas_string.h

@@ -0,0 +1,47 @@
+/*
+ * bas_string.h
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 26.02.2013
+ *      Author: Markus Fröschle
+ */
+
+#ifndef BAS_STRING_H_
+#define BAS_STRING_H_
+
+#include <stddef.h>
+
+extern int strncmp(const char *s1, const char *s2, size_t max);
+extern char *strcpy(char *dst, const char *src);
+char *strncpy(char *dst, const char *src, size_t max);
+extern int strcmp(const char *s1, const char *s2);
+extern size_t strlen(const char *str);
+extern char *strcat(char *dst, const char *src);
+extern char *strncat(char *dst, const char *src, size_t max);
+extern int atoi(const char *c);
+extern void *memcpy(void *dst, const void *src, size_t n);
+extern void *memset(void *s, int c, size_t n);
+extern int memcmp(const void *s1, const void *s2, size_t max);
+extern void bzero(void *s, size_t n);
+
+#define isdigit(c)	(((c) >= '0') && ((c) <= '9'))
+#define isupper(c)	((c) >= 'A' && ((c) <= 'Z'))
+#define islower(c)	((c) >= 'a' && ((c) <= 'z'))
+#define isalpha(c)	(isupper((c)) || islower(c))
+#define tolower(c)	(isupper(c) ? ((c) + 'a' - 'A') : (c))
+
+#endif /* BAS_STRING_H_ */

tos/vmem_test/include/driver_vec.h

@@ -0,0 +1,125 @@
+/*
+ * driver_vec.h
+ *
+ * Interface for exposure of BaS drivers to the OS
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 24.10.2013
+ *      Author: Markus Fröschle
+ */
+
+#ifndef _DRIVER_VEC_H_
+#define _DRIVER_VEC_H_
+
+
+enum driver_type
+{
+	END_OF_DRIVERS,		/* marks end of driver list */
+	BLOCKDEV_DRIVER,
+	CHARDEV_DRIVER,
+	VIDEO_DRIVER,
+	XHDI_DRIVER,
+	MCD_DRIVER,
+};
+
+struct generic_driver_interface
+{
+	uint32_t (*init)(void);
+	uint32_t (*read)(void *buf, size_t count);
+	uint32_t (*write)(const void *buf, size_t count);
+	uint32_t (*ioctl)(uint32_t request, ...);
+};
+
+
+/* Chained buffer descriptor */
+typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
+struct MCD_bufDesc_struct {
+	uint32_t flags;         /* flags describing the DMA */
+    uint32_t csumResult;    /* checksum from checksumming performed since last checksum reset */
+	int8_t  *srcAddr;      /* the address to move data from */
+	int8_t  *destAddr;     /* the address to move data to */
+	int8_t  *lastDestAddr; /* the last address written to */
+    uint32_t dmaSize;       /* the number of bytes to transfer independent of the transfer size */
+    MCD_bufDesc *next; /* next buffer descriptor in chain */
+    uint32_t info;          /* private information about this descriptor;  DMA does not affect it */
+};
+
+/* Progress Query struct */
+typedef volatile struct MCD_XferProg_struct {
+	int8_t *lastSrcAddr;         /* the most-recent or last, post-increment source address */
+	int8_t *lastDestAddr;        /* the most-recent or last, post-increment destination address */
+	uint32_t  dmaSize;            /* the amount of data transferred for the current buffer */
+	MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */
+} MCD_XferProg;
+
+struct dma_driver_interface
+{
+	int32_t version;
+	int32_t magic;
+	int32_t (*dma_set_initiator)(int initiator);
+	uint32_t (*dma_get_initiator)(int requestor);
+	void (*dma_free_initiator)(int requestor);
+	int32_t (*dma_set_channel)(int requestor, void (*handler)(void));
+	int (*dma_get_channel)(int requestor);
+	void (*dma_free_channel)(int requestor);
+	void (*dma_clear_channel)(int channel);
+	int (*MCD_startDma)(int channel, int8_t *srcAddr, int16_t srcIncr, int8_t *destAddr, int16_t destIncr,
+						uint32_t dmaSize, uint32_t xferSize, uint32_t initiator, int32_t priority, uint32_t flags,
+						uint32_t funcDesc);
+	int (*MCD_dmaStatus)(int channel);
+	int (*MCD_XferProgrQuery)(int channel, MCD_XferProg *progRep);
+	int (*MCD_killDma)(int channel);
+	int (*MCD_continDma)(int channel);
+	int (*MCD_pauseDma)(int channel);
+	int (*MCD_resumeDma)(int channel);
+	int (*MCD_csumQuery)(int channel, uint32_t *csum);
+	void *(*dma_malloc)(long amount);
+	int (*dma_free)(void *addr);
+};
+	
+struct xhdi_driver_interface
+{
+	uint32_t (*xhdivec)();
+};
+
+union interface
+{
+	struct generic_driver_interface *gdi;
+	struct xhdi_driver_interface *xhdi;
+	struct dma_driver_interface *dma;
+};
+
+struct generic_interface
+{
+	enum driver_type type;
+	char name[16];
+	char description[64];
+	int version;
+	int revision;
+	union interface interface;
+};
+
+struct driver_table
+{
+	uint32_t bas_version;
+	uint32_t bas_revision;
+	uint32_t (*remove_handler)();			/* calling this will disable the BaS' hook into trap #0 */
+	struct generic_interface *interfaces;
+};
+
+
+#endif /* _DRIVER_VEC_H_ */

tos/vmem_test/sources/bas_printf.c

@@ -0,0 +1,456 @@
+/*
+ * tc.printf.c: A public-domain, minimal printf/sprintf routine that prints
+ *         through the putchar() routine.  Feel free to use for
+ *         anything...  -- 7/17/87 Paul Placeway
+ */
+/*-
+ * Copyright (c) 1980, 1991 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <stdarg.h>
+#include "MCF5475.h"
+#include "bas_printf.h"
+#include "bas_string.h"
+
+/*
+ * Lexical definitions.
+ *
+ * All lexical space is allocated dynamically.
+ * The eighth/sixteenth bit of characters is used to prevent recognition,
+ * and eventually stripped.
+ */
+#define META        0200
+#define ASCII       0177
+#define QUOTE       ((char) 0200)   /* Eighth char bit used for 'ing */
+#define TRIM        0177    /* Mask to strip quote bit */
+#define UNDER       0000000 /* No extra bits to do both */
+#define BOLD        0000000 /* Bold flag */
+#define STANDOUT    META    /* Standout flag */
+#define LITERAL     0000000 /* Literal character flag */
+#define ATTRIBUTES  0200    /* The bits used for attributes */
+#define CHAR        0000177 /* Mask to mask out the character */
+
+#define INF 32766       /* should be bigger than any field to print */
+
+static char snil[] = "(nil)";
+
+void xputchar(int c)
+{
+    __asm__ __volatile__
+    (
+            ".extern        printf_helper\n\t"
+            "move.b         %0,d0\n\t"
+            "bsr            printf_helper\n\t"
+            /* output */:
+            /* input */: "r" (c)
+            /* clobber */: "d0","d2","a0","memory"
+    );
+}
+
+static void doprnt(void (*addchar)(int), const char *sfmt, va_list ap)
+{
+    char buf[128];
+    char *bp;
+    const char *f;
+    float flt;
+    long l;
+    unsigned long u;
+    int i;
+    int fmt;
+    unsigned char pad = ' ';
+    int flush_left = 0;
+    int f_width = 0;
+    int prec = INF;
+    int hash = 0;
+    int do_long = 0;
+    int sign = 0;
+    int attributes = 0;
+
+    f = sfmt;
+    for (; *f; f++)
+    {
+        if (*f != '%')
+        {
+            /* then just out the char */
+            (*addchar)((int) (((unsigned char) *f) | attributes));
+        }
+        else
+        {
+            f++; /* skip the % */
+
+            if (*f == '-')
+            { /* minus: flush left */
+                flush_left = 1;
+                f++;
+            }
+
+            if (*f == '0' || *f == '.')
+            {
+                /* padding with 0 rather than blank */
+                pad = '0';
+                f++;
+            }
+            if (*f == '*')
+            {
+                /* field width */
+                f_width = va_arg(ap, int);
+                f++;
+            }
+            else if (isdigit((unsigned char)*f))
+            {
+                f_width = atoi(f);
+                while (isdigit((unsigned char)*f))
+                    f++; /* skip the digits */
+            }
+
+            if (*f == '.')
+            { /* precision */
+                f++;
+                if (*f == '*')
+                {
+                    prec = va_arg(ap, int);
+                    f++;
+                }
+                else if (isdigit((unsigned char)*f))
+                {
+                    prec = atoi(f);
+                    while (isdigit((unsigned char)*f))
+                        f++; /* skip the digits */
+                }
+            }
+
+            if (*f == '#')
+            { /* alternate form */
+                hash = 1;
+                f++;
+            }
+
+            if (*f == 'l')
+            { /* long format */
+                do_long++;
+                f++;
+                if (*f == 'l')
+                {
+                    do_long++;
+                    f++;
+                }
+            }
+
+            fmt = (unsigned char) *f;
+            if (fmt != 'S' && fmt != 'Q' && isupper(fmt))
+            {
+                do_long = 1;
+                fmt = tolower(fmt);
+            }
+            bp = buf;
+            switch (fmt)
+            { /* do the format */
+            case 'd':
+                switch (do_long)
+                {
+                case 0:
+                    l = (long) (va_arg(ap, int));
+                    break;
+                case 1:
+                default:
+                    l = va_arg(ap, long);
+                    break;
+                }
+
+                if (l < 0)
+                {
+                    sign = 1;
+                    l = -l;
+                }
+                do
+                {
+                    *bp++ = (char) (l % 10) + '0';
+                } while ((l /= 10) > 0);
+                if (sign)
+                    *bp++ = '-';
+                f_width = f_width - (int) (bp - buf);
+                if (!flush_left)
+                    while (f_width-- > 0)
+                        (*addchar)((int) (pad | attributes));
+                for (bp--; bp >= buf; bp--)
+                    (*addchar)((int) (((unsigned char) *bp) | attributes));
+                if (flush_left)
+                    while (f_width-- > 0)
+                        (*addchar)((int) (' ' | attributes));
+                break;
+
+         case 'f':
+            /* this is actually more than stupid, but does work for now */
+            flt = (float) (va_arg(ap, double)); /* beware: va_arg() extends float to double! */
+            if (flt < 0)
+            {
+               sign = 1;
+               flt = -flt;
+            }
+            {
+               int quotient, remainder;
+
+               quotient = (int) flt;
+               remainder = (flt - quotient) * 10E5;
+
+               for (i = 0; i < 6; i++)
+               {
+                  *bp++ = (char) (remainder % 10) + '0';
+                  remainder /= 10;
+               }
+               *bp++ = '.';
+               do
+               {
+                  *bp++ = (char) (quotient % 10) + '0';
+               } while ((quotient /= 10) > 0);
+               if (sign)
+                  *bp++ = '-';
+               f_width = f_width - (int) (bp - buf);
+               if (!flush_left)
+               while (f_width-- > 0)
+                  (*addchar)((int) (pad | attributes));
+               for (bp--; bp >= buf; bp--)
+                  (*addchar)((int) (((unsigned char) *bp) | attributes));
+               if (flush_left)
+                  while (f_width-- > 0)
+                     (*addchar)((int) (' ' | attributes));
+            }
+            break;
+
+            case 'p':
+                do_long = 1;
+                hash = 1;
+                fmt = 'x';
+                /* no break */
+            case 'o':
+            case 'x':
+            case 'u':
+                switch (do_long)
+                {
+                case 0:
+                    u = (unsigned long) (va_arg(ap, unsigned int));
+                    break;
+                case 1:
+                default:
+                    u = va_arg(ap, unsigned long);
+                    break;
+                }
+                if (fmt == 'u')
+                { /* unsigned decimal */
+                    do
+                    {
+                        *bp++ = (char) (u % 10) + '0';
+                    } while ((u /= 10) > 0);
+                }
+                else if (fmt == 'o')
+                { /* octal */
+                    do
+                    {
+                        *bp++ = (char) (u % 8) + '0';
+                    } while ((u /= 8) > 0);
+                    if (hash)
+                        *bp++ = '0';
+                }
+                else if (fmt == 'x')
+                { /* hex */
+                    do
+                    {
+                        i = (int) (u % 16);
+                        if (i < 10)
+                            *bp++ = i + '0';
+                        else
+                            *bp++ = i - 10 + 'a';
+                    } while ((u /= 16) > 0);
+                    if (hash)
+                    {
+                        *bp++ = 'x';
+                        *bp++ = '0';
+                    }
+                }
+                i = f_width - (int) (bp - buf);
+                if (!flush_left)
+                    while (i-- > 0)
+                        (*addchar)((int) (pad | attributes));
+                for (bp--; bp >= buf; bp--)
+                    (*addchar)((int) (((unsigned char) *bp) | attributes));
+                if (flush_left)
+                    while (i-- > 0)
+                        (*addchar)((int) (' ' | attributes));
+                break;
+
+            case 'c':
+                i = va_arg(ap, int);
+                (*addchar)((int) (i | attributes));
+                break;
+
+            case 'S':
+            case 'Q':
+            case 's':
+            case 'q':
+                bp = va_arg(ap, char *);
+                if (!bp)
+                    bp = snil;
+                f_width = f_width - strlen((char *) bp);
+                if (!flush_left)
+                    while (f_width-- > 0)
+                        (*addchar)((int) (pad | attributes));
+                for (i = 0; *bp && i < prec; i++)
+                {
+                    if (fmt == 'q' && (*bp & QUOTE))
+                        (*addchar)((int) ('\\' | attributes));
+                    (*addchar)(
+                            (int) (((unsigned char) *bp & TRIM) | attributes));
+                    bp++;
+                }
+                if (flush_left)
+                    while (f_width-- > 0)
+                        (*addchar)((int) (' ' | attributes));
+                break;
+
+            case 'a':
+                attributes = va_arg(ap, int);
+                break;
+
+            case '%':
+                (*addchar)((int) ('%' | attributes));
+                break;
+
+            default:
+                break;
+            }
+            flush_left = 0, f_width = 0, prec = INF, hash = 0, do_long = 0;
+            sign = 0;
+            pad = ' ';
+        }
+    }
+}
+
+static char *xstring, *xestring;
+
+void xaddchar(int c)
+{
+    if (xestring == xstring)
+        *xstring = '\0';
+    else
+        *xstring++ = (char) c;
+}
+
+int sprintf(char *str, const char *format, ...)
+{
+    va_list va;
+    va_start(va, format);
+
+    xstring = str;
+
+    doprnt(xaddchar, format, va);
+    va_end(va);
+    *xstring++ = '\0';
+
+    return 0;
+}
+
+void xsnprintf(char *str, size_t size, const char *fmt, ...)
+{
+    va_list va;
+    va_start(va, fmt);
+
+    xstring = str;
+    xestring = str + size - 1;
+    doprnt(xaddchar, fmt, va);
+    va_end(va);
+    *xstring++ = '\0';
+}
+
+void xprintf(const char *fmt, ...)
+{
+    va_list va;
+    va_start(va, fmt);
+    doprnt(xputchar, fmt, va);
+    va_end(va);
+}
+
+void xvprintf(const char *fmt, va_list va)
+{
+    doprnt(xputchar, fmt, va);
+}
+
+void xvsnprintf(char *str, size_t size, const char *fmt, va_list va)
+{
+    xstring = str;
+    xestring = str + size - 1;
+    doprnt(xaddchar, fmt, va);
+    *xstring++ = '\0';
+}
+
+
+void display_progress()
+{
+    static int _progress_index;
+    char progress_char[] = "|/-\\";
+
+    xputchar(progress_char[_progress_index++ % strlen(progress_char)]);
+    xputchar('\r');
+}
+
+void hexdump(uint8_t buffer[], int size)
+{
+   int i;
+   int line = 0;
+   uint8_t *bp = buffer;
+
+   while (bp < buffer + size) {
+      uint8_t *lbp = bp;
+
+      xprintf("%08x  ", line);
+
+      for (i = 0; i < 16; i++) {
+         if (bp + i > buffer + size) {
+            break;
+         }
+         xprintf("%02x ", (uint8_t) *lbp++);
+      }
+
+      lbp = bp;
+      for (i = 0; i < 16; i++) {
+         int8_t c = *lbp++;
+
+         if (bp + i > buffer + size) {
+            break;
+         }
+         if (c > ' ' && c < '~') {
+            xprintf("%c", c);
+         } else {
+            xprintf(".");
+         }
+      }
+      xprintf("\r\n");
+
+      bp += 16;
+      line += 16;
+   }
+}

tos/vmem_test/sources/bas_string.c

@@ -0,0 +1,156 @@
+/*
+ * bas_string.c
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 26.02.2013
+ *      Author: Markus Fröschle
+ */
+
+#include "bas_types.h"
+#include <stdint.h>
+#include "bas_string.h"
+
+void *memcpy(void *dst, const void *src, size_t n)
+{
+    uint8_t *to = dst;
+
+    while (to < (uint8_t *) dst + n)
+        *to++ = * (uint8_t *) src++;
+
+    return dst;
+}
+
+void bzero(void *s, size_t n)
+{
+    size_t i;
+
+    for (i = 0; i < n; i++)
+        ((unsigned char *) s)[i] = '\0';
+}
+
+void *memset(void *s, int c, size_t n)
+{
+    uint8_t *dst = s;
+
+    do
+    {
+        *dst++ = c;
+    } while ((dst - (uint8_t *) s) < n);
+
+    return s;
+}
+
+
+int memcmp(const void *s1, const void *s2, size_t max)
+{
+    int i;
+    int cmp;
+
+    for (i = 0; i < max; i++)
+    {
+        cmp = (* (const char *) s1 - * (const char *) s2);
+        if (cmp != 0) return cmp;
+    }
+    return cmp;
+}
+
+int strcmp(const char *s1, const char *s2)
+{
+    int i;
+    int cmp;
+
+    for (i = 0; *s1++ && *s2++; i++)
+    {
+        cmp = (*s1 - *s2);
+        if (cmp != 0) return cmp;
+    }
+    return cmp;
+}
+
+int strncmp(const char *s1, const char *s2, size_t max)
+{
+    int i;
+    int cmp;
+
+    for (i = 0; i < max && *s1++ && *s2++; i++);
+    {
+        cmp = (*s1 - *s2);
+        if (cmp != 0) return cmp;
+    }
+    return cmp;
+}
+
+char *strcpy(char *dst, const char *src)
+{
+    char *ptr = dst;
+
+    while ((*dst++ = *src++) != '\0');
+    return ptr;
+}
+
+char *strncpy(char *dst, const char *src, size_t max)
+{
+    char *ptr = dst;
+
+    while ((*dst++ = *src++) != '\0' && max-- >= 0);
+    return ptr;
+}
+
+int atoi(const char *c)
+{
+    int value = 0;
+    while (isdigit(*c))
+    {
+        value *= 10;
+        value += (int) (*c - '0');
+        c++;
+    }
+    return value;
+}
+
+size_t strlen(const char *s)
+{
+    const char *start = s;
+
+    while (*s++);
+
+    return s - start - 1;
+}
+
+
+char *strcat(char *dst, const char *src)
+{
+    char *ret = dst;
+    dst = &dst[strlen(dst)];
+    while ((*dst++ = *src++) != '\0');
+    return ret;
+}
+
+char *strncat(char *dst, const char *src, size_t max)
+{
+    size_t i;
+    char *ret = dst;
+
+    dst = &dst[strlen(dst)];
+    for (i = 0; i < max && *src; i++)
+    {
+        *dst++ = *src++;
+    }
+    *dst++ = '\0';
+
+    return ret;
+}

tos/vmem_test/sources/printf_helper.S

@@ -0,0 +1,38 @@
+/*
+ * printf_helper.S
+ *
+ * assembler trampoline to let printf (compiled -mpcrel) indirectly reference __MBAR
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Copyright 2010 - 2012 F. Aschwanden
+ * Copyright 2011 - 2012 V. Riviere
+ * Copyright 2012        M. Froeschle
+ */
+
+
+			.global printf_helper
+printf_helper:
+			.extern		__MBAR
+.wait_txready:
+			move.w		__MBAR+0x8604,d2	// PSCSCR0 status register
+			btst		#10,d2				// space left in TX fifo?
+			beq.s		.wait_txready		// no, loop
+			lea			__MBAR+0x860C,a0	// PSCSTB0 transmitter buffer register
+			move.b		d0,(a0)				// send byte
+			rts
+
+// vim: set syntax=asm68k :

tos/vmem_test/sources/vmem_test.c

@@ -0,0 +1,309 @@
+#include <stdio.h>
+#include <mint/osbind.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "bas_printf.h"
+#include "MCF5475.h"
+#include "driver_vec.h"
+
+#define FPGA_CONFIG                         (1 << 2)
+#define FPGA_CONF_DONE                      (1 << 5)
+
+#define SRAM1_START     0xff101000
+#define SRAM1_END       SRAM1_START + 0x1000
+#define SAFE_STACK      SRAM1_END - 4
+
+#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory")
+
+#define SYSCLK 132000
+
+long bas_start = 0xe0000000;
+extern volatile uint32_t _VRAM[];
+
+volatile int32_t time, start, end;
+int i;
+
+void do_tests(void)
+{
+    /* read out shifter registers */
+    uint8_t * _vmem_hi = (uint8_t *) 0xff8201;
+    uint8_t * _vmem_mid = (uint8_t *) 0xff8203;
+    uint8_t * _vmem_lo = (uint8_t *) 0xff820d;
+
+    xprintf("vmem_hi = %x\r\n", *_vmem_hi);
+    xprintf("vmem_mid = %x\r\n", *_vmem_mid);
+    xprintf("vmem_lo = %x\r\n", *_vmem_lo);
+
+    /* try to write to them */
+
+    xprintf("trying to write to _vbas_ad\r\n");
+
+    *_vmem_hi = 0xd0;
+    *_vmem_mid = 0x00;
+    *_vmem_lo = 0x00;
+
+    xprintf("read back values\r\n");
+
+    xprintf("vmem_hi = %x\r\n", *_vmem_hi);
+    xprintf("vmem_mid = %x\r\n", *_vmem_mid);
+    xprintf("vmem_lo = %x\r\n", *_vmem_lo);
+
+    xprintf("read Firebee clut\r\n");
+
+    hexdump((uint8_t *) 0xf0000000, 0x400);
+
+    xprintf("set Firebee clut\r\n");
+
+    long i;
+    for (i = 0; i < 0x400; i++)
+    {
+        * (unsigned char *) (0xf0000000 + i) = (uint8_t) i;
+    }
+
+    hexdump((uint8_t *) 0xf0000000, 0x400);
+
+    xprintf("try to access Firebee FPGA memory\r\n");
+
+    xprintf("read\r\n");
+    start = MCF_SLT0_SCNT;
+    hexdump((uint8_t *) _VRAM, 64);
+    end = MCF_SLT0_SCNT;
+    time = (start - end) / (SYSCLK / 1000) / 1000;
+
+    xprintf("finished (took %f seconds).\r\n", time / 1000.0);
+
+    xprintf("write\r\n");
+    start = MCF_SLT0_SCNT;
+    for (i = 0; i < 64; i++)
+    {
+       ((uint8_t *) _VRAM)[i] = (uint32_t) i;
+    }
+    end = MCF_SLT0_SCNT;
+    time = (start - end) / (SYSCLK / 1000) / 1000;
+
+    xprintf("finished (took %f seconds).\r\n", time / 1000.0);
+
+    xprintf("read\r\n");
+    start = MCF_SLT0_SCNT;
+    hexdump((uint8_t *) _VRAM, 64);
+    end = MCF_SLT0_SCNT;
+    time = (start - end) / (SYSCLK / 1000) / 1000;
+
+    xprintf("finished (took %f seconds).\r\n", time / 1000.0);
+}
+
+/*
+ * INIT VIDEO DDR RAM
+ */
+
+void init_video_ddr(void)
+{
+    xprintf("init video RAM: ");
+
+    * (volatile uint16_t *) 0xf0000400 = 0xb;	/* set cke = 1, cs=1, config = 1 */
+    NOP();
+
+    _VRAM[0] = 0x00050400;	/* IPALL */
+    NOP();
+
+    _VRAM[0] = 0x00072000;	/* load EMR pll on */
+    NOP();
+
+    _VRAM[0] = 0x00070122;	/* load MR: reset pll, cl=2, burst=4lw */
+    NOP();
+
+    _VRAM[0] = 0x00050400;	/* IPALL */
+    NOP();
+
+    _VRAM[0] = 0x00060000;	/* auto refresh */
+    NOP();
+
+    _VRAM[0] = 0x00060000;	/* auto refresh */
+    NOP();
+
+    _VRAM[0] = 0000070022;	/* load MR dll on */
+    NOP();
+
+    * (uint32_t *) 0xf0000400 = 0x01070002; /* fifo on, refresh on, ddrcs und cke on, video dac on */
+
+    // vram control register cannot be read
+#ifdef _NOT_USED_
+    xprintf("read out the Firebee vram control register to verify correct settings: %lx\r\n", * (uint32_t *) 0xf0000400);
+    if (* (uint32_t *) 0xf0000400 != 0x01070002)
+    {
+        xprintf("initializing firebee video RAM DDR controller failed.\r\nINFO: infinite loop. Press reset.\r\n");
+        while (1);
+    }
+#endif /* _NOT_USED_ */
+    xprintf("finished\r\n");
+}
+
+void wait_pll(void)
+{
+    int32_t trgt = MCF_SLT0_SCNT - 100000;
+    do
+    {
+        ;
+    } while ((* (volatile int16_t *) 0xf0000800 < 0) && MCF_SLT0_SCNT > trgt);
+}
+
+static volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600;
+
+void init_pll(void)
+{
+    xprintf("FPGA PLL initialization: ");
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x48) = 27;     /* loopfilter  r */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x08) = 1;		/* charge pump 1 */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x00) = 12;		/* N counter high = 12 */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x40) = 12;		/* N counter low = 12 */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x114) = 1;		/* ck1 bypass */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x118) = 1;		/* ck2 bypass */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x11c) = 1;		/* ck3 bypass */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x10) = 1;		/* ck0 high  = 1 */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x50) = 1;		/* ck0 low = 1 */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x144) = 1;		/* M odd division */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x44) = 1;		/* M low = 1 */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x04) = 145;	/* M high = 145 = 146 MHz */
+
+    wait_pll();
+
+    * (volatile uint8_t *) 0xf0000800 = 0;				/* set */
+
+    xprintf("finished\r\n");
+}
+
+void wait_for_jtag(void)
+{
+    long i;
+
+    /* set supervisor stack to end of SRAM1 */
+    __asm__ __volatile__ (
+        "       move    #0x2700,sr\n\t"         /* disable interrupts */
+        "       move.l  %[stack],d0\n\t"        /* 4KB on-chip core SRAM1 */
+        "       move.l  d0,sp\n\t"              /* set stack pointer */
+        :
+        : [stack] "i" (SAFE_STACK)
+        : "d0", "cc"    /* clobber */
+    );
+
+    MCF_EPORT_EPIER = 0x0;              /* disable EPORT interrupts */
+    MCF_INTC_IMRL = 0xffffffff;
+    MCF_INTC_IMRH = 0xffffffff;         /* disable interrupt controller */
+
+    MCF_MMU_MMUCR &= ~MCF_MMU_MMUCR_EN; /* disable MMU */
+
+    xprintf("relocated supervisor stack, disabled interrupts and disabled MMU\r\n");
+
+    /*
+     * configure FEC1L port directions to enable external JTAG configuration download to FPGA
+     */
+    MCF_GPIO_PDDR_FEC1L = 0 |
+                          MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4;  /* bit 4 = LED => output */
+                                                            /* all other bits = input */
+
+    /*
+     * configure DSPI_CS3 as GPIO input to avoid the MCU driving against the FPGA blink
+     */
+    MCF_PAD_PAR_DSPI &= ~MCF_PAD_PAR_DSPI_PAR_CS3(MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3);
+    /*
+     * now that GPIO ports have been switched to input, we can poll for FPGA config
+     * started from the JTAG interface (CONF_DONE goes low) and finish (CONF_DONE goes high)
+     */
+    xprintf("waiting for JTAG configuration start\r\n");
+    while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));       /* wait for JTAG config load started */
+
+    xprintf("waiting for JTAG configuration to finish\r\n");
+    while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));     /* wait for JTAG config load finished */
+
+    xprintf("JTAG configuration finished.\r\n");
+
+    /* wait */
+    xprintf("wait a little to let things settle...\r\n");
+    for (i = 0; i < 100000L; i++);
+
+    /* initialize FPGA PLL's */
+    init_pll();
+
+    /* initialize DDR RAM controller */
+    init_video_ddr();
+
+    xprintf("disable caches\r\n");
+    __asm__ __volatile(
+                "move.l     #0x01000000,d0      \r\n"
+                "movec      d0,CACR             \r\n"
+                : /* no output */
+                : /* no input */
+                : "d0", "memory");
+    /* begin of tests */
+    do_tests();
+
+    xprintf("wait a little to let things settle...\r\n");
+    for (i = 0; i < 100000L; i++);
+
+    xprintf("INFO: endless loop now. Press reset to reboot\r\n");
+    while (1)
+        ;
+}
+
+int main(int argc, char *argv[])
+{
+    printf("\033E\r\nFPGA JTAG configuration support\r\n");
+    printf("<C> 2014 M. Froeschle\r\n");
+
+    printf("You may now savely load a new FPGA configuration through the JTAG interface\r\n"
+           "and your Firebee will reboot once finished using that new configuration.\r\n");
+    if (argc == 2)
+    {
+        /*
+         * we got an argument. This is supposed to be the address that we need to jump to after JTAG
+         * configuration has been finished. Meant to support BaS in RAM testing
+         */
+        char *addr_str = argv[1];
+        char *addr = NULL;
+        char *end = NULL;
+
+        addr = (char *) strtol(addr_str, &end, 16);
+        if (addr != NULL && addr <= (char *) 0xe0000000 && addr >= (char *) 0x10000000)
+        {
+            /*
+             * seems to be a valid address
+             */
+            bas_start = (long) addr;
+
+            printf("BaS start address set to %p\r\n", (void *) bas_start);
+        }
+        else
+        {
+            printf("\r\nNote: BaS start address %p not valid. Stick to %p.\r\n", addr, (void *) bas_start);
+        }
+    }
+    Supexec(wait_for_jtag);
+
+    return 0;       /* just to make the compiler happy, we will never return */
+}
+

tos/vmem_test/vmem_test.config

@@ -0,0 +1 @@
+// ADD PREDEFINED MACROS HERE!

tos/vmem_test/vmem_test.creator

@@ -0,0 +1 @@
+[General]

tos/vmem_test/vmem_test.files

@@ -0,0 +1,3 @@
+include/driver_vec.h
+sources/jtagwait.c
+Makefile

tos/vmem_test/vmem_test.includes

@@ -0,0 +1 @@
+include

usb/usb_mouse.c

@@ -26,12 +26,13 @@
 #include "exceptions.h"
 #include "driver_mem.h"
 
-//#define DEBUG_USBMOUSE
+#define DEBUG_USBMOUSE
 #ifdef DEBUG_USBMOUSE
 #define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
 #define dbg(format, arg...) do { ; } while (0)
 #endif /* DEBUG_USBMOUSE */
+#define err(format, arg...) do { xprintf("ERROR: %s(): " format, __FUNCTION__, ##arg); } while (0)
 
 extern void ltoa(char *buf, long n, unsigned long base);
 extern void call_mousevec(unsigned char *data, void (**mousevec)(void *));
@@ -47,65 +48,67 @@ static int usb_mouse_probe(struct usb_device *dev, unsigned int ifnum);
 /* deregistering the mouse */
 int usb_mouse_deregister(struct usb_device *dev)
 {
-	dev->irq_handle = NULL;
-	if (new != NULL)
-	{
-		driver_mem_free(new);
-		new = NULL;
-	}
-	mouse_installed = 0;
-	dbg("USB MOUSE deregister\r\n");
-	return 1;
+    dev->irq_handle = NULL;
+    if (new != NULL)
+    {
+        driver_mem_free(new);
+        new = NULL;
+    }
+    mouse_installed = 0;
+    dbg("USB MOUSE deregister\r\n");
+    return 1;
 }
 
 /* registering the mouse */
 int usb_mouse_register(struct usb_device *dev)
 {
-	if (!mouse_installed && (dev->devnum != -1) && (usb_mouse_probe(dev, 0) == 1))
-	{
-		/* Ok, we found a mouse */
-		dbg("USB MOUSE found (USB: %d, devnum: %d)\r\n", dev->usbnum, dev->devnum);
-		mouse_installed = 1;
-		dev->deregister = usb_mouse_deregister;
-		return 1;
-	}
-	/* no USB Mouse found */
-	return -1;
+    if (!mouse_installed && (dev->devnum != -1) && (usb_mouse_probe(dev, 0) == 1))
+    {
+        /* Ok, we found a mouse */
+        dbg("USB MOUSE found (USB: %d, devnum: %d)\r\n", dev->usbnum, dev->devnum);
+        mouse_installed = 1;
+        dev->deregister = usb_mouse_deregister;
+        return 1;
+    }
+    /* no USB Mouse found */
+    return -1;
 }
 
 /* search for mouse and register it if found */
 int drv_usb_mouse_init(void)
 {
-	int i;
-	int j;
+    int i;
+    int j;
 
-	/*
-	 * check if mouse is already initialized
-	 */
-	if (mouse_installed)
-	{
-		xprintf("USB mouse already initialized\r\n");
+    /*
+     * check if mouse is already initialized
+     */
+    if (mouse_installed)
+    {
+        xprintf("USB mouse already initialized\r\n");
 
-		return -1;
-	}
+        return -1;
+    }
 
-	/* scan all USB Devices */
-	for (j = 0; j < USB_MAX_BUS; j++)
-	{
-		for (i = 0; i < USB_MAX_DEVICE; i++)
-		{
-			struct usb_device *dev = usb_get_dev_index(i, j); /* get device */
+    /* scan all USB Devices */
+    for (j = 0; j < USB_MAX_BUS; j++)
+    {
+        for (i = 0; i < USB_MAX_DEVICE; i++)
+        {
+            struct usb_device *dev = usb_get_dev_index(i, j); /* get device */
 
-			if (dev == NULL)
-				break;
+            if (dev == NULL)
+            {
+                break;
+            }
 
-			xprintf("Try to register usb device %d,%d as mouse\r\n", i, j);
-			if (usb_mouse_register(dev) > 0)
-				return 1;
-		}
-	}
-	/* no USB Mouse found */
-	return -1;
+            xprintf("Try to register usb device %d,%d as mouse\r\n", i, j);
+            if (usb_mouse_register(dev) > 0)
+                return 1;
+        }
+    }
+    /* no USB Mouse found */
+    return -1;
 }
 
 /**************************************************************************
@@ -113,184 +116,186 @@ int drv_usb_mouse_init(void)
  */
 static void usb_kbd_send_code(unsigned char code)
 {
-	dbg("FIXME: usb_kbd_send_code 0x%x not implemented\r\n", code);
+    dbg("FIXME: usb_kbd_send_code 0x%x not implemented\r\n", code);
 }
 
 /* Interrupt service routine */
 static int usb_mouse_irq(struct usb_device *dev)
 {
 #ifdef CONFIG_USB_INTERRUPT_POLLING
-	int level;
+    int level;
 #endif
-	int i, change = 0;
-	if ((dev->irq_status != 0) || (dev->irq_act_len < 3) || (dev->irq_act_len > 8))
-	{
-		dbg("USB MOUSE error %lX, len %d\r\n", dev->irq_status, dev->irq_act_len);
-		return 1;
-	}
-	for (i = 0; i < dev->irq_act_len; i++)
-	{
-		if (new[i] != old[i])
-		{
-			change = 1;
-			break;
-		}
-	}
-	if (change)
-	{
-		char wheel = 0, buttons, old_buttons;
-		dbg("USB MOUSE len:%d %02X %02X %02X %02X %02X %02X\r\n", dev->irq_act_len, new[0], new[1], new[2], new[3], new[4], new[5]);
+    int i, change = 0;
+    if ((dev->irq_status != 0) || (dev->irq_act_len < 3) || (dev->irq_act_len > 8))
+    {
+        dbg("USB MOUSE error %lX, len %d\r\n", dev->irq_status, dev->irq_act_len);
+        return 1;
+    }
+    for (i = 0; i < dev->irq_act_len; i++)
+    {
+        if (new[i] != old[i])
+        {
+            change = 1;
+            break;
+        }
+    }
+    if (change)
+    {
+        char wheel = 0, buttons, old_buttons;
+        dbg("USB MOUSE len:%d %02X %02X %02X %02X %02X %02X\r\n", dev->irq_act_len, new[0], new[1], new[2], new[3], new[4], new[5]);
 #ifdef CONFIG_USB_INTERRUPT_POLLING
-		level = set_ipl(7); /* mask interrupts */
+        level = set_ipl(7); /* mask interrupts */
 #endif
-		if ((dev->irq_act_len >= 6) && (new[0] == 1)) /* report-ID */
-		{
-			buttons = new[1];
-			old_buttons = old[1];
-			new[0] = ((new[1] & 1) << 1) + ((new[1] & 2) >> 1) + 0xF8;
-			new[1] = new[2];
-			new[2] = new[3];
-			wheel = new[4];
-		}
-		else /* boot report */
-		{
-			buttons = new[0];
-			old_buttons = old[0];
-			new[0] = ((new[0] & 1) << 1) + ((new[0] & 2) >> 1) + 0xF8;
-			if (dev->irq_act_len >= 3)
-				wheel = new[3];
-		}
-		if ((buttons ^ old_buttons) & 4) /* 3rd button */
-		{
-		  if (buttons & 4)
-		  {
-				usb_kbd_send_code(0x72); /* ENTER */
-				usb_kbd_send_code(0xF2);
-			}
-		}
-		if (wheel != 0) /* actually like Eiffel */
-		{
+        if ((dev->irq_act_len >= 6) && (new[0] == 1)) /* report-ID */
+        {
+            buttons = new[1];
+            old_buttons = old[1];
+            new[0] = ((new[1] & 1) << 1) + ((new[1] & 2) >> 1) + 0xF8;
+            new[1] = new[2];
+            new[2] = new[3];
+            wheel = new[4];
+        }
+        else /* boot report */
+        {
+            buttons = new[0];
+            old_buttons = old[0];
+            new[0] = ((new[0] & 1) << 1) + ((new[0] & 2) >> 1) + 0xF8;
+            if (dev->irq_act_len >= 3)
+                wheel = new[3];
+        }
+        if ((buttons ^ old_buttons) & 4) /* 3rd button */
+        {
+          if (buttons & 4)
+          {
+                usb_kbd_send_code(0x72); /* ENTER */
+                usb_kbd_send_code(0xF2);
+            }
+        }
+        if (wheel != 0) /* actually like Eiffel */
+        {
 #define REPEAT_WHEEL 3
-			int i;
-			if (wheel > 0)
-			{
-				for (i = 0; i < REPEAT_WHEEL; i++)
-				{
-					usb_kbd_send_code(0x48); /* UP */
-					usb_kbd_send_code(0xC8);
-				}
-			}
-			else
-			{
-				for (i = 0; i < REPEAT_WHEEL; i++)
-				{
-					usb_kbd_send_code(0x50); /* DOWN */
-					usb_kbd_send_code(0xD0);
-				}
-			}
-		}
-		xprintf("FIXME: call_mousevec(new, mousevec) not implemented\r\n");
-		//if(mousevec != NULL)
-			//call_mousevec(new, mousevec);
+            int i;
+            if (wheel > 0)
+            {
+                for (i = 0; i < REPEAT_WHEEL; i++)
+                {
+                    usb_kbd_send_code(0x48); /* UP */
+                    usb_kbd_send_code(0xC8);
+                }
+            }
+            else
+            {
+                for (i = 0; i < REPEAT_WHEEL; i++)
+                {
+                    usb_kbd_send_code(0x50); /* DOWN */
+                    usb_kbd_send_code(0xD0);
+                }
+            }
+        }
+        xprintf("FIXME: call_mousevec(new, mousevec) not implemented\r\n");
+        //if(mousevec != NULL)
+            //call_mousevec(new, mousevec);
 #ifdef CONFIG_USB_INTERRUPT_POLLING
-		set_ipl(level);
+        set_ipl(level);
 #endif
-		old[0] = new[0];
-		old[1] = new[1];
-		old[2] = new[2];
-		old[3] = new[3];
-		old[4] = new[4];
-		old[5] = new[5];
-	}
-	return 1; /* install IRQ Handler again */
+        old[0] = new[0];
+        old[1] = new[1];
+        old[2] = new[2];
+        old[3] = new[3];
+        old[4] = new[4];
+        old[5] = new[5];
+    }
+    return 1; /* install IRQ Handler again */
 }
 
 /* probes the USB device dev for mouse type */
 static int usb_mouse_probe(struct usb_device *dev, unsigned int ifnum)
 {
-	struct usb_interface_descriptor *iface;
-	struct usb_endpoint_descriptor *ep;
-	int pipe;
-	int maxp;
+    struct usb_interface_descriptor *iface;
+    struct usb_endpoint_descriptor *ep;
+    int pipe;
+    int maxp;
 
-	if (dev->descriptor.bNumConfigurations != 1)
-	{
-		dbg("dev->descriptor.bNumConfigurations != 1\r\n");
+#ifdef _NOT_USED_
+    if (dev->descriptor.bNumConfigurations != 1)
+    {
+        dbg("dev->descriptor.bNumConfigurations != 1\r\n");
 
-		return 0;
-	}
+        return 0;
+    }
+#endif
 
-	iface = &dev->config.if_desc[ifnum];
+    iface = &dev->config.if_desc[ifnum];
 
-	if (iface->bInterfaceClass != USB_CLASS_HID)
-	{
-		dbg("iface->bInterfaceClass != USB_CLASS_HID (%d instead)\r\n", iface->bInterfaceClass);
+    if (iface->bInterfaceClass != USB_CLASS_HID)
+    {
+        dbg("iface->bInterfaceClass != USB_CLASS_HID (%d instead)\r\n", iface->bInterfaceClass);
 
-		return 0;
-	}
+        return 0;
+    }
 
 
-	if (iface->bInterfaceSubClass != USB_SUB_HID_BOOT)
-	{
-		dbg("iface->bInterfaceSubClass != USB_SUB_HID_BOOT (%d instead)\r\n", iface->bInterfaceSubClass);
+    if (iface->bInterfaceSubClass != USB_SUB_HID_BOOT)
+    {
+        dbg("iface->bInterfaceSubClass != USB_SUB_HID_BOOT (%d instead)\r\n", iface->bInterfaceSubClass);
 
-		return 0;
-	}
+        return 0;
+    }
 
-	if (iface->bInterfaceProtocol != USB_PROT_HID_MOUSE)
-	{
-		dbg("iface->bInterfaceProtocol != USB_PROT_HID_MOUSE (%d)\r\n", iface->bInterfaceProtocol);
+    if (iface->bInterfaceProtocol != USB_PROT_HID_MOUSE)
+    {
+        dbg("iface->bInterfaceProtocol != USB_PROT_HID_MOUSE (%d)\r\n", iface->bInterfaceProtocol);
 
-		return 0;
-	}
+        return 0;
+    }
 
-	if (iface->bNumEndpoints != 1)
-	{
-		dbg("iface->bNumEndpoints != 1\r\n");
+    if (iface->bNumEndpoints != 1)
+    {
+        dbg("iface->bNumEndpoints != 1\r\n");
 
-		return 0;
-	}
+        return 0;
+    }
 
-	ep = &iface->ep_desc[0];
+    ep = &iface->ep_desc[0];
 
-	if (!(ep->bEndpointAddress & 0x80))
-	{
-		dbg("! ep->bEndpointAddress & 0x80\r\n");
+    if (!(ep->bEndpointAddress & 0x80))
+    {
+        dbg("! ep->bEndpointAddress & 0x80\r\n");
 
-		return 0;
-	}
+        return 0;
+    }
 
-	if ((ep->bmAttributes & 3) != 3)
-	{
-		dbg("ep->bmAttributes & 3 != 3\r\n");
+    if ((ep->bmAttributes & 3) != 3)
+    {
+        dbg("ep->bmAttributes & 3 != 3\r\n");
 
-		return 0;
-	}
+        return 0;
+    }
 
-	new = (unsigned char *) driver_mem_alloc(8);
-	if (new == NULL)
-	{
-		dbg("new == NULL\r\n");
+    new = (unsigned char *) driver_mem_alloc(8);
+    if (new == NULL)
+    {
+        dbg("new == NULL\r\n");
 
-		return 0;
-	}
+        return 0;
+    }
 
-	dbg("USB MOUSE found set protocol...\r\n");
+    dbg("USB MOUSE found set protocol...\r\n");
 
-	/* ok, we found a USB Mouse, install it */
-	pipe = usb_rcvintpipe(dev, ep->bEndpointAddress);
-	maxp = usb_maxpacket(dev, pipe);
+    /* ok, we found a USB Mouse, install it */
+    pipe = usb_rcvintpipe(dev, ep->bEndpointAddress);
+    maxp = usb_maxpacket(dev, pipe);
 //	if(maxp < 6)
 //		usb_set_protocol(dev, iface->bInterfaceNumber, 0); /* boot */
 //	else
-	usb_set_protocol(dev, iface->bInterfaceNumber, 1); /* report */
-	dbg("USB MOUSE found set idle...\r\n");
-	usb_set_idle(dev, iface->bInterfaceNumber, 0, 0); /* report infinite */
-	memset(&new[0], 0, 8);
-	memset(&old[0], 0, 8);
-	dev->irq_handle = usb_mouse_irq;
-	dbg("USB MOUSE enable interrupt pipe (maxp: %d)...\r\n", maxp);
-	usb_submit_int_msg(dev, pipe, &new[0], maxp > 8 ? 8 : maxp, ep->bInterval);
-	return 1;
+    usb_set_protocol(dev, iface->bInterfaceNumber, 1); /* report */
+    dbg("USB MOUSE found set idle...\r\n");
+    usb_set_idle(dev, iface->bInterfaceNumber, 0, 0); /* report infinite */
+    memset(&new[0], 0, 8);
+    memset(&old[0], 0, 8);
+    dev->irq_handle = usb_mouse_irq;
+    dbg("USB MOUSE enable interrupt pipe (maxp: %d)...\r\n", maxp);
+    usb_submit_int_msg(dev, pipe, &new[0], maxp > 8 ? 8 : maxp, ep->bInterval);
+    return 1;
 }
 

util/wait.c

@@ -31,7 +31,7 @@
 
 uint32_t get_timer(void)
 {
-	return MCF_SLT_SCNT(0);
+    return MCF_SLT_SCNT(0);
 }
 /*
  * wait for the specified number of us on slice timer 0. Replaces the original routines that had
@@ -39,17 +39,18 @@ uint32_t get_timer(void)
  */
 void wait(uint32_t us)
 {
-	int32_t target = MCF_SLT_SCNT(0) - (us * (SYSCLK / 1000));
+    int32_t target = MCF_SLT_SCNT(0) - (us * (SYSCLK / 1000));
 
-	while (MCF_SLT_SCNT(0) - target > 0);
+    while (MCF_SLT_SCNT(0) - target > 0);
 }
+void wait_us() __attribute__ ((weak, alias("wait")));
 
 /*
  * same as above, but with milliseconds wait time
  */
 void wait_ms(uint32_t ms)
 {
-	wait(ms * 1000);
+    wait(ms * 1000);
 }
 /*
  * the same as above, with a checker function which gets called while
@@ -57,13 +58,13 @@ void wait_ms(uint32_t ms)
  */
 bool waitfor(uint32_t us, checker_func condition)
 {
-	int32_t target = MCF_SLT_SCNT(0) - (us * (SYSCLK / 1000));
-	bool res;
+    int32_t target = MCF_SLT_SCNT(0) - (us * (SYSCLK / 1000));
+    bool res;
 
-	do
-	{
-		if ((res = (*condition)()))
-			return res;
-	} while (MCF_SLT_SCNT(0) - target > 0);
-	return false;
+    do
+    {
+        if ((res = (*condition)()))
+            return res;
+    } while (MCF_SLT_SCNT(0) - target > 0);
+    return false;
 }

xhdi/xhdi_interface.c

@@ -27,7 +27,7 @@
 #include "bas_printf.h"
 
 
-unsigned long xhdi_call(uint16_t *stack)
+uint32_t xhdi_call(uint16_t *stack)
 {
 	uint16_t opcode = *stack;