version bump

include/version.h

@@ -29,7 +29,7 @@
  */
 
 #define MAJOR_VERSION	0
-#define MINOR_VERSION	84
+#define MINOR_VERSION	85
 
 
 #endif /* VERSION_H_ */

sys/BaS.c

@@ -96,20 +96,20 @@ static inline bool pic_rxready(void)
 
 void write_pic_byte(uint8_t value)
 {
-    /* Wait until the transmitter is ready or 1000us are passed */
+	/* Wait until the transmitter is ready or 1000us are passed */
 	waitfor(1000, pic_txready);
 
-    /* Transmit the byte */
-    *(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT) = value; // Really 8-bit
+	/* Transmit the byte */
+	*(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT) = value; // Really 8-bit
 }
 
 uint8_t read_pic_byte(void)
 {
-    /* Wait until a byte has been received or 1000us are passed */
+	/* Wait until a byte has been received or 1000us are passed */
 	waitfor(1000, pic_rxready);
 
-    /* Return the received byte */
-    return *(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT); // Really 8-bit
+	/* Return the received byte */
+	return *(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT); // Really 8-bit
 }
 
 void pic_init(void)
@@ -271,13 +271,13 @@ void network_init(void)
 		return;
 	}
 
-    /*
-     * Register the DMA interrupt handler
-     */
-    handler = dma_interrupt_handler;
-    vector = 112;
+	/*
+	 * Register the DMA interrupt handler
+	 */
+	handler = dma_interrupt_handler;
+	vector = 112;
 
-    if (!isr_register_handler(vector, handler, NULL,NULL))
+	if (!isr_register_handler(vector, handler, NULL,NULL))
 	{
 		dbg("%s: Error: Unable to register handler for vector %s\r\n", __FUNCTION__, vector);
 		return;
@@ -291,10 +291,10 @@ void network_init(void)
 	memcpy(nif1.hwa, mac, 6);
 	memcpy(nif1.broadcast, bc, 6);
 
-	dbg("%s: ethernet address is %02X:%02X:%02X:%02X:%02X:%02X\r\n", __FUNCTION__, 
+	dbg("%s: ethernet address is %02X:%02X:%02X:%02X:%02X:%02X\r\n", __FUNCTION__,
 				nif1.hwa[0], nif1.hwa[1], nif1.hwa[2],
 				nif1.hwa[3], nif1.hwa[4], nif1.hwa[5]);
-	
+
 	timer_init(TIMER_NETWORK, TMR_INTC_LVL, TMR_INTC_PRI);
 
 	arp_init(&arp_info);
@@ -346,16 +346,16 @@ void BaS(void)
 	MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN;			/* MMU on */
 	NOP();										/* force pipeline sync */
 	xprintf("finished\r\n");
-	
+
 	#ifdef MACHINE_FIREBEE
 	xprintf("IDE reset: ");
 	/* IDE reset */
 	* (volatile uint8_t *) (0xffff8802 - 2) = 14;
 	* (volatile uint8_t *) (0xffff8802 - 0) = 0x80;
 	wait(1);
-	
+
 	* (volatile uint8_t *) (0xffff8802 - 0) = 0;
-	
+
 	xprintf("finished\r\n");
 	xprintf("enable video: ");
 	/*
@@ -384,22 +384,22 @@ void BaS(void)
 #ifdef _NOT_USED_
 	screen_init();
 
-	    /* experimental */
-    {
-        int i;
-        uint32_t *scradr = 0xd00000;
+		/* experimental */
+	{
+		int i;
+		uint32_t *scradr = 0xd00000;
 
-        for (i = 0; i < 100; i++)
-        {
-            uint32_t *p = scradr;
-
-            for (p = scradr; p < scradr + 1024 * 150L; p++)
-            {
-				*p = 0xffffffff;
-		    }
+		for (i = 0; i < 100; i++)
+		{
+			uint32_t *p = scradr;
 
 			for (p = scradr; p < scradr + 1024 * 150L; p++)
-		    {
+			{
+				*p = 0xffffffff;
+			}
+
+			for (p = scradr; p < scradr + 1024 * 150L; p++)
+			{
 				*p = 0x0;
 			}
 		}
@@ -442,10 +442,11 @@ void BaS(void)
 
 	/* Jump into the OS */
 	typedef void void_func(void);
-	typedef struct {
+	struct rom_header
+	{
 		void *initial_sp;
 		void_func *initial_pc;
-	} ROM_HEADER;
+	};
 
 	xprintf("BaS initialization finished, enable interrupts\r\n");
 	enable_coldfire_interrupts();
@@ -454,6 +455,6 @@ void BaS(void)
 	network_init();
 
 	xprintf("call EmuTOS\r\n");
-	ROM_HEADER* os_header = (ROM_HEADER*)TOS;
+	struct rom_header *os_header = (struct rom_header *) TOS;
 	os_header->initial_pc();
 }

sys/mmu.c

@@ -24,6 +24,26 @@
  * Copyright 2013        M. Froeschle
  */
 
+#define ACR_BA(x)                   ((x) & 0xffff0000)
+#define ACR_ADMSK(x)                (((x) & 0xffff) << 16)
+#define ACR_E(x)                    (((x) & 1) << 15)
+
+#define ACR_S(x)                    (((x) & 3) << 13)
+#define ACR_S_USERMODE              0
+#define ACR_S_SUPERVISOR_MODE       1
+#define ACR_S_ALL                   2
+
+#define ACR_AMM(x)                  (((x) & 1) << 10)
+
+#define ACR_CM(x)                   (((x) & 3) << 5)
+#define ACR_CM_CACHEABLE_WT         0x0
+#define ACR_CM_CACHEABLE_CB         0x1
+#define ACR_CM_CACHE_INH_PRECISE    0x2
+#define ACR_CM_CACHE_INH_IMPRECISE  0x3
+
+#define ACR_SP(x)           (((x) & 1) << 3)
+#define ACR_W(x)            (((x) & 1) << 2)
+
 #include <stdint.h>
 #include "bas_printf.h"
 #include "bas_types.h"
@@ -42,12 +62,12 @@
 #error "unknown machine!"
 #endif /* MACHINE_FIREBEE */
 
-#define DBG_MMU
-#ifdef DBG_MMU
-#define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg);} while(0)
+//#define DEBUG_MMU
+#ifdef DEBUG_MMU
+#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg);} while(0)
 #else
 #define dbg(format, arg...) do {;} while (0)
-#endif /* DBG_MMU */
+#endif /* DEBUG_MMU */
 
 /*
  * set ASID register
@@ -59,11 +79,11 @@ inline uint32_t set_asid(uint32_t value)
 	uint32_t ret = rt_asid;
 
 	__asm__ __volatile__(
-			"movec		%[value],ASID\n\t"
-			: /* no output */
-			: [value] "r" (value)
-			:
-			);
+		"movec		%[value],ASID\n\t"
+		: /* no output */
+		: [value] "r" (value)
+		:
+	);
 
 	rt_asid = value;
 
@@ -81,11 +101,11 @@ inline uint32_t set_acr0(uint32_t value)
 	uint32_t ret = rt_acr0;
 
 	__asm__ __volatile__(
-			"movec		%[value],ACR0\n\t"
-			: /* not output */
-			: [value] "r" (value)
-			:
-			);
+		"movec		%[value],ACR0\n\t"
+		: /* not output */
+		: [value] "r" (value)
+		:
+	);
 	rt_acr0 = value;
 
 	return ret;
@@ -101,11 +121,11 @@ inline uint32_t set_acr1(uint32_t value)
 	uint32_t ret = rt_acr1;
 
 	__asm__ __volatile__(
-			"movec		%[value],ACR1\n\t"
-			: /* not output */
-			: [value] "r" (value)
-			:
-			);
+		"movec		%[value],ACR1\n\t"
+		: /* not output */
+		: [value] "r" (value)
+		:
+	);
 	rt_acr1 = value;
 
 	return ret;
@@ -122,11 +142,11 @@ inline uint32_t set_acr2(uint32_t value)
 	uint32_t ret = rt_acr2;
 
 	__asm__ __volatile__(
-			"movec		%[value],ACR2\n\t"
-			: /* not output */
-			: [value] "r" (value)
-			:
-			);
+		"movec		%[value],ACR2\n\t"
+		: /* not output */
+		: [value] "r" (value)
+		:
+	);
 	rt_acr2 = value;
 
 	return ret;
@@ -142,11 +162,11 @@ inline uint32_t set_acr3(uint32_t value)
 	uint32_t ret = rt_acr3;
 
 	__asm__ __volatile__(
-			"movec		%[value],ACR3\n\t"
-			: /* not output */
-			: [value] "r" (value)
-			:
-			);
+		"movec		%[value],ACR3\n\t"
+		: /* not output */
+		: [value] "r" (value)
+		:
+	);
 	rt_acr3 = value;
 
 	return ret;
@@ -158,375 +178,276 @@ inline uint32_t set_mmubar(uint32_t value)
 	uint32_t ret = rt_mmubar;
 
 	__asm__ __volatile__(
-			"movec		%[value],MMUBAR\n\t"
-			: /* no output */
-			: [value] "r" (value)
-			: /* no clobber */
-			);
+		"movec		%[value],MMUBAR\n\t"
+		: /* no output */
+		: [value] "r" (value)
+		: /* no clobber */
+	);
 	rt_mmubar = value;
 	NOP();
 
 	return ret;
 }
 
-
-
-/*
- * TODO: this would be nicer in an include file
- */
-extern uint8_t _SYS_SRAM[];
-#define SYS_SRAM_ADDRESS ((uint32_t) &_SYS_SRAM[0])
-extern uint8_t _SYS_SRAM_SIZE[];
-extern uint8_t _FASTRAM_END[];
-
-struct mmu_mapping
-{
-	uint32_t phys;
-	uint32_t virt;
-	uint32_t length;
-	uint32_t pagesize;
-	struct map_flags flags;
-};
-
-static struct mmu_mapping locked_map[] =
-{
-	{
-		/* Falcon video memory. Needs special care */
-		0x60d00000,
-		0xd00000,
-		0x100000,
-		MMU_PAGE_SIZE_1M,
-		{ CACHE_WRITETHROUGH, SV_USER, SCA_PAGE_ID, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
-	},
-};
-
-static int num_locked_mmu_maps = sizeof(locked_map) / sizeof(struct mmu_mapping);
-
-static struct mmu_mapping memory_map[] =
-{
-	/* map OS system vectors supervisor-protected */
-	{
-		0,
-		0,
-		0x800,
-		MMU_PAGE_SIZE_1K,
-		{ CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
-	},
-	{
-		0x800,
-		0x800,
-		0x800,
-		MMU_PAGE_SIZE_1K,
-		{ CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
-	},
-	{
-		/* when the first 4k are filled with 1k pages, we can switch to 8k pages */
-		0x1000,
-		0x1000,
-		0xff000,
-		MMU_PAGE_SIZE_8K,
-		{ CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
-	},
-	{
-		/* arrived at a 1Meg border, we can switch to 1Meg pages */
-		0x100000,
-		0x100000,
-		0xc00000,
-		MMU_PAGE_SIZE_1M,
-		{ CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
-	},
-	/* Falcon video ram left out intentionally here (see above) */
-	{
-		/* ROM */
-		0xe00000,
-		0xe00000,
-		0x100000,
-		MMU_PAGE_SIZE_1M,
-		{ CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_EXECUTE },
-	},
-	{
-		/* FASTRAM */
-		0x1000000,
-		0x1000000,
-		(uint32_t) _FASTRAM_END - 0x1000000,
-		MMU_PAGE_SIZE_1M,
-		{ CACHE_WRITETHROUGH, SV_USER, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
-	},
-	{
-		/* MBAR */
-		MBAR_ADDRESS,
-		MBAR_ADDRESS,
-		0x100000,
-		MMU_PAGE_SIZE_1M,
-		{ CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE },
-	},
-	{
-		/* RAMBAR0 */
-		RAMBAR0_ADDRESS,
-		RAMBAR0_ADDRESS,
-		(uint32_t) _RAMBAR0_SIZE,
-		MMU_PAGE_SIZE_1K,
-		{ CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
-	},
-	{
-		/* RAMBAR1 */
-		RAMBAR1_ADDRESS,
-		RAMBAR1_ADDRESS,
-		(uint32_t) _RAMBAR1_SIZE,
-		MMU_PAGE_SIZE_1K,
-		{ CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
-	},
-	{
-		/* SYSTEM SRAM */
-		SYS_SRAM_ADDRESS,
-		SYS_SRAM_ADDRESS,
-		(uint32_t) _SYS_SRAM_SIZE,
-		MMU_PAGE_SIZE_8K,
-		{ CACHE_WRITETHROUGH, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE | ACCESS_EXECUTE },
-	},
-	{
-		/* Firebee FPGA registers */
-		(uint32_t) 0xf0000000,
-		(uint32_t) 0xf0000000,
-		(uint32_t) 0x08000000,
-		MMU_PAGE_SIZE_1M,
-		{ CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE },
-	},
-	{
-		/* Falcon I/O registers */
-		(uint32_t) 0xfff00000,
-		(uint32_t) 0xfff00000,
-		(uint32_t) 0x100000,
-		MMU_PAGE_SIZE_1M,
-		{ CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE },
-	},
-	{
-		/* the same, but different virtual address */
-		(uint32_t) 0x00f00000,
-		(uint32_t) 0xfff00000,
-		(uint32_t) 0x100000,
-		MMU_PAGE_SIZE_1M,
-		{ CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE },
-	},
-	{
-		/* PCI memory */
-		(uint32_t) PCI_MEMORY_OFFSET,
-		(uint32_t) PCI_MEMORY_OFFSET,
-		(uint32_t) PCI_MEMORY_SIZE,
-		MMU_PAGE_SIZE_1M,
-		{ CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE },
-	},
-	{
-		/* PCI I/O */
-		(uint32_t) PCI_IO_OFFSET,
-		(uint32_t) PCI_IO_OFFSET,
-		(uint32_t) PCI_IO_SIZE,
-		MMU_PAGE_SIZE_1M,
-		{ CACHE_NOCACHE_PRECISE, SV_PROTECT, 0, ACCESS_READ | ACCESS_WRITE },
-	}
-};
-
-static int num_mmu_maps = sizeof(memory_map) / sizeof(struct mmu_mapping);
-
-static struct mmu_mapping *lookup_mapping(uint32_t virt)
-{
-	int i;
-
-	/*
-	 * dumb, for now
-	 */
-
-	for (i = 0; i < num_mmu_maps; i++)
-	{
-		if (virt >= memory_map[i].virt && virt <= memory_map[i].virt + memory_map[i].length - 1)
-			return &memory_map[i];
-	}
-	return NULL;
-}
-
 void mmu_init(void)
 {
 	extern uint8_t _MMUBAR[];
 	uint32_t MMUBAR = (uint32_t) &_MMUBAR[0];
-	int i;
+	extern uint8_t _TOS[];
+	uint32_t TOS = (uint32_t) &_TOS[0];
 
 	set_asid(0);			/* do not use address extension (ASID provides virtual 48 bit addresses */
 
-	/*
-	 * need to set data ACRs in a way that supervisor access to all memory regions
-	 * becomes possible. Otherways it might be that the supervisor stack ends up in an unmapped
-	 * region when further MMU TLB entries force a page steal. This would lead to a double
-	 * fault since the CPU wouldn't be able to push its exception stack frame during an access
-	 * exception
-	 */
-
 	/* set data access attributes in ACR0 and ACR1 */
+	set_acr0(ACR_W(0) |								/* read and write accesses permitted */
+			ACR_SP(0) |								/* supervisor and user mode access permitted */
+			ACR_CM(ACR_CM_CACHE_INH_PRECISE) |		/* cache inhibit, precise */
+			ACR_AMM(0) |							/* control region > 16 MB */
+			ACR_S(ACR_S_ALL) |						/* match addresses in user and supervisor mode */
+			ACR_E(1) |								/* enable ACR */
+#if defined(MACHINE_FIREBEE)
+			ACR_ADMSK(0x3f) |						/* cover 1GB area from 0xc0000000 to 0xffffffff */
+			ACR_BA(0xc0000000));					/* (equals area from 3 to 4 GB */
+#elif defined(MACHINE_M5484LITE)
+			ACR_ADMSK(0x7f) |						/* cover 2 GB area from 0x80000000 to 0xffffffff */
+			ACR_BA(0x80000000));
+#elif defined(MACHINE_M54455)
+			ACR_ADMSK(0x7f) |
+			ACR_BA(0x80000000));					/* FIXME: not determined yet */
+#else
+#error unknown machine!
+#endif /* MACHINE_FIREBEE */
 
-	set_acr0(ACR_WRITE_PROTECT(0) |			/* read and write accesses permitted */
-			ACR_SUPERVISOR_PROTECT(0) |		/* supervisor and user mode access permitted */
-			ACR_CACHE_MODE(CACHE_WRITETHROUGH) |	/* cacheable, write through */
-			ACR_ADDRESS_MASK_MODE(1) | 		/* region 13 MByte */
-			ACR_S(ACR_S_SUPERVISOR_MODE) |	/* memory only visible from supervisor mode */
-			ACR_E(1) |						/* enable ACR */
-			ACR_ADMSK(0x0a) |				/* cover 12 MByte from 0x0 */
-			ACR_BA(0));						/* start from 0x0 */
-
-	set_acr1(ACR_WRITE_PROTECT(0) |			/* read and write accesses permitted */
-			ACR_SUPERVISOR_PROTECT(0) |		/* supervisor and user mode access permitted */
-			ACR_CACHE_MODE(CACHE_WRITETHROUGH) |	/* cacheable, write through */
-			ACR_ADDRESS_MASK_MODE(0) | 		/* region > 16 MByte */
-			ACR_S(ACR_S_SUPERVISOR_MODE) |	/* memory only visible from supervisor mode */
-			ACR_E(1) |						/* enable ACR */
-			ACR_ADMSK(0x1f) |				/* cover 495 MByte from 0x1000000 */
-			ACR_BA(0x01000000));			/* all Fast RAM */
-
-
-	/*
-	 * set instruction access attributes in ACR2 and ACR3. This is the same as above, basically:
-	 * enable supervisor access to all SDRAM
-	 */
-
-	set_acr2(ACR_WRITE_PROTECT(0) |
-			ACR_SUPERVISOR_PROTECT(0) |
-			ACR_CACHE_MODE(CACHE_WRITETHROUGH) |
-			ACR_ADDRESS_MASK_MODE(1) |
-			ACR_S(ACR_S_SUPERVISOR_MODE) |
-			ACR_E(1) |
-			ACR_ADMSK(0x0c) |
-			ACR_BA(0x0));
-
-	set_acr3(ACR_WRITE_PROTECT(0) |
-			ACR_SUPERVISOR_PROTECT(0) |
-			ACR_CACHE_MODE(CACHE_WRITETHROUGH) |
-			ACR_ADDRESS_MASK_MODE(0) |
-			ACR_S(ACR_S_SUPERVISOR_MODE) |
+	// set_acr1(0x601fc000);
+	set_acr1(ACR_W(0) |
+			ACR_SP(0) |
+			ACR_CM(0) |
+#if defined(MACHINE_FIREBEE)
+			ACR_CM(ACR_CM_CACHEABLE_WT) |			/* video RAM on the Firebee */
+#elif defined(MACHINE_M5484LITE)
+			ACR_CM(ACR_CM_CACHE_INH_PRECISE) |		/* Compact Flash on the M548xLITE */
+#elif defined(MACHINE_M54455)
+			ACR_CM(ACR_CM_CACHE_INH_PRECISE) |		/* FIXME: not determined yet */
+#else
+#error unknown machine!
+#endif /* MACHINE_FIREBEE */
+			ACR_AMM(0) |
+			ACR_S(ACR_S_ALL) |
 			ACR_E(1) |
 			ACR_ADMSK(0x1f) |
-			ACR_BA(0x0f));
+			ACR_BA(0x60000000));
+
+	/* set instruction access attributes in ACR2 and ACR3 */
+
+	//set_acr2(0xe007c400);
+	set_acr2(ACR_W(0) |
+			ACR_SP(0) |
+			ACR_CM(0) |
+			ACR_CM(ACR_CM_CACHEABLE_WT) |
+			ACR_AMM(1) |
+			ACR_S(ACR_S_ALL) |
+			ACR_E(1) |
+			ACR_ADMSK(0x7) |
+			ACR_BA(0xe0000000));
+
+	/* disable ACR3 */
+	set_acr3(0x0);
 
 	set_mmubar(MMUBAR + 1);		/* set and enable MMUBAR */
 
 	/* clear all MMU TLB entries */
 	MCF_MMU_MMUOR = MCF_MMU_MMUOR_CA;
 
-	/* map locked TLB entries */
-	for (i = 0; i < num_locked_mmu_maps; i++)
-	{
-		mmu_map_page(locked_map[i].virt, locked_map[i].phys, locked_map->pagesize, locked_map->flags);
+	/* create locked TLB entries */
 
-		if (locked_map[i].flags.page_id == SCA_PAGE_ID)
-		{
-			video_tlb = 0x2000;
-			video_sbt = 0x0;
-		}
-	}
+	/*
+	 * 0x0000'0000 - 0x000F'FFFF (first MB of physical memory) locked virtual = physical
+	 */
+	MCF_MMU_MMUTR = 0x0 | 					/* virtual address */
+					MCF_MMU_MMUTR_SG |		/* shared global */
+					MCF_MMU_MMUTR_V;		/* valid */
+	MCF_MMU_MMUDR = 0x0 |					/* physical address */
+					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
+					MCF_MMU_MMUDR_CM(0x1) |	/* cacheable, copyback */
+					MCF_MMU_MMUDR_R |		/* read access enable */
+					MCF_MMU_MMUDR_W |		/* write access enable */
+					MCF_MMU_MMUDR_X | 		/* execute access enable */
+					MCF_MMU_MMUDR_LK;		/* lock entry */
+	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
+					MCF_MMU_MMUOR_UAA;		/* update allocation address field */
+	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
+					MCF_MMU_MMUOR_ACC |     /* access TLB */
+					MCF_MMU_MMUOR_UAA;      /* update allocation address field */
+
+	/*
+	 * 0x00d0'0000 - 0x00df'ffff (last megabyte of ST RAM = Falcon video memory) locked ID = 6
+	 * mapped to physical address 0x60d0'0000 (FPGA video memory)
+	 * video RAM: read write execute normal write true
+	 */
+
+	MCF_MMU_MMUTR = 0x00d00000 |			/* virtual address */
+#if defined(MACHINE_FIREBEE)
+					MCF_MMU_MMUTR_ID(SCA_PAGE_ID) |
+#endif /* MACHINE_FIREBEE */
+					MCF_MMU_MMUTR_SG |		/* shared global */
+					MCF_MMU_MMUTR_V;		/* valid */
+#if defined(MACHINE_FIREBEE)
+					/* map FPGA video memory for FireBee only */
+	MCF_MMU_MMUDR = 0x60d00000 |			/* physical address */
+#elif defined(MACHINE_M5484LITE)
+	MCF_MMU_MMUDR = 0x00d00000 |			/* physical address */
+#elif defined(MACHINE_M54455)
+	MCF_MMU_MMUDR = 0x60d00000 |			/* FIXME: not determined yet */
+#else
+#error unknown machine!
+#endif /* MACHINE_FIREBEE */
+					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
+					MCF_MMU_MMUDR_CM(0x0) |	/* cachable writethrough */
+					/* caveat: can't be supervisor protected since TOS puts the application stack there! */
+					//MCF_MMU_MMUDR_SP |		/* supervisor protect */
+					MCF_MMU_MMUDR_R |		/* read access enable */
+					MCF_MMU_MMUDR_W |		/* write access enable */
+					MCF_MMU_MMUDR_X |		/* execute access enable */
+					MCF_MMU_MMUDR_LK;		/* lock entry */
+	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
+					MCF_MMU_MMUOR_UAA;		/* update allocation address field */
+	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
+					MCF_MMU_MMUOR_ACC |     /* access TLB */
+					MCF_MMU_MMUOR_UAA;      /* update allocation address field */
+
+#if defined(MACHINE_FIREBEE)
+	video_tlb = 0x2000;						/* set page as video page */
+	video_sbt = 0x0;						/* clear time */
+#endif /* MACHINE_FIREBEE */
+
+	/*
+	 * Make the TOS (in SDRAM) read-only
+	 * This maps virtual 0x00e0'0000 - 0x00ef'ffff to the same virtual address
+	 */
+	MCF_MMU_MMUTR = TOS |					/* virtual address */
+					MCF_MMU_MMUTR_SG |		/* shared global */
+					MCF_MMU_MMUTR_V;		/* valid */
+	MCF_MMU_MMUDR = TOS |					/* physical address */
+					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
+					MCF_MMU_MMUDR_CM(0x1) |	/* cachable copyback */
+					MCF_MMU_MMUDR_R |		/* read access enable */
+					//MCF_MMU_MMUDR_W |		/* write access enable (FIXME: for now) */
+					MCF_MMU_MMUDR_X |		/* execute access enable */
+					MCF_MMU_MMUDR_LK;		/* lock entry */
+	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
+					MCF_MMU_MMUOR_UAA;		/* update allocation address field */
+	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
+					MCF_MMU_MMUOR_ACC |     /* access TLB */
+					MCF_MMU_MMUOR_UAA;      /* update allocation address field */
+
+#if MACHINE_FIREBEE
+	/*
+	 * Map FireBee I/O area (0xfff0'0000 - 0xffff'ffff physical) to the Falcon-compatible I/O
+	 * area (0x00f0'0000 - 0x00ff'ffff virtual) for the FireBee
+	 */
+
+	MCF_MMU_MMUTR = 0x00f00000 |			/* virtual address */
+					MCF_MMU_MMUTR_SG |		/* shared global */
+					MCF_MMU_MMUTR_V;		/* valid */
+	MCF_MMU_MMUDR = 0xfff00000 |			/* physical address */
+					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
+					MCF_MMU_MMUDR_CM(0x2) |	/* nocache precise */
+					MCF_MMU_MMUDR_SP |		/* supervisor protect */
+					MCF_MMU_MMUDR_R |		/* read access enable */
+					MCF_MMU_MMUDR_W |		/* write access enable */
+					MCF_MMU_MMUDR_X |		/* execute access enable */
+					MCF_MMU_MMUDR_LK;		/* lock entry */
+	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
+					MCF_MMU_MMUOR_UAA;		/* update allocation address field */
+	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
+					MCF_MMU_MMUOR_ACC |     /* access TLB */
+					MCF_MMU_MMUOR_UAA;      /* update allocation address field */
+#endif /* MACHINE_FIREBEE */
+
+	/*
+	 * Map (locked) the second last MB of physical SDRAM (this is where BaS .data and .bss reside) to the same
+	 * virtual address. This is also used when BaS is in RAM
+	 */
+
+	MCF_MMU_MMUTR = (SDRAM_START + SDRAM_SIZE - 0x00200000) |	/* virtual address */
+					MCF_MMU_MMUTR_SG |		/* shared global */
+					MCF_MMU_MMUTR_V;		/* valid */
+	MCF_MMU_MMUDR = (SDRAM_START + SDRAM_SIZE - 0x00200000) |	/* physical address */
+					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
+					MCF_MMU_MMUDR_CM(0x0) |	/* cacheable writethrough */
+					MCF_MMU_MMUDR_SP |		/* supervisor protect */
+					MCF_MMU_MMUDR_R |		/* read access enable */
+					MCF_MMU_MMUDR_W |		/* write access enable */
+					MCF_MMU_MMUDR_X |		/* execute access enable */
+					MCF_MMU_MMUDR_LK;		/* lock entry */
+	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
+					MCF_MMU_MMUOR_UAA;		/* update allocation address field */
+	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
+					MCF_MMU_MMUOR_ACC |     /* access TLB */
+					MCF_MMU_MMUOR_UAA;      /* update allocation address field */
+
+	/*
+	 * Map (locked) the very last MB of physical SDRAM (this is where the driver buffers reside) to the same
+	 * virtual address. Used uncached for drivers.
+	 */
+
+	MCF_MMU_MMUTR = (SDRAM_START + SDRAM_SIZE - 0x00100000) |	/* virtual address */
+					MCF_MMU_MMUTR_SG |		/* shared global */
+					MCF_MMU_MMUTR_V;		/* valid */
+	MCF_MMU_MMUDR = (SDRAM_START + SDRAM_SIZE - 0x00100000) |	/* physical address */
+					MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
+					MCF_MMU_MMUDR_CM(0x2) |	/* nocache precise */
+					MCF_MMU_MMUDR_SP |		/* supervisor protect */
+					MCF_MMU_MMUDR_R |		/* read access enable */
+					MCF_MMU_MMUDR_W |		/* write access enable */
+					//MCF_MMU_MMUDR_X |		/* execute access enable */
+					MCF_MMU_MMUDR_LK;		/* lock entry */
+	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
+					MCF_MMU_MMUOR_UAA;		/* update allocation address field */
+	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
+					MCF_MMU_MMUOR_ACC |     /* access TLB */
+					MCF_MMU_MMUOR_UAA;      /* update allocation address field */
 }
 
-/*
- * handle an access error
- * upper level routine called from access_exception inside exceptions.S
- */
-bool access_exception(uint32_t pc, uint32_t format_status)
+void mmutr_miss(uint32_t address)
 {
-	int fault_status;
-	uint32_t fault_address;
-	uint32_t mmu_status;
+	dbg("MMU TLB MISS at 0x%08x\r\n", address);
+	flush_and_invalidate_caches();
 
-	/*
-	 * extract fault status from format_status exception stack field
-	 */
-	fault_status = format_status & 0xc030000;
-	mmu_status = MCF_MMU_MMUSR;
-
-	/*
-	 * determine if access fault was caused by a TLB miss
-	 */
-	switch (fault_status)
+	switch (address)
 	{
-		case 0x4010000:	/* TLB miss on opword of instruction fetch */
-		case 0x4020000:	/* TLB miss on extension word of instruction fetch */
-			//fault_address = pc;
-			//break;
-		case 0x8020000:	/* TLB miss on data write */
-		case 0xc020000:	/* TLB miss on data read or read-modify-write */
-			fault_address = MCF_MMU_MMUAR;
-			/*
-			 * the following line must stay commented or we risk a double fault (debugging
-			 * output requiring itself a page mapping):
-			 */
-			// dbg("access fault - TLB miss at %p. Fault status = 0x0%x\r\n", pc, fault_status);
+		case keyctl:
+		case keybd:
+			/* do something to emulate the IKBD access */
+			dbg("IKBD access\r\n");
+			break;
+
+		case midictl:
+		case midi:
+			/* do something to emulate MIDI access */
+			dbg("MIDI ACIA access\r\n");
 			break;
 
 		default:
-			return false;
+			/* add missed page to TLB */
+			MCF_MMU_MMUTR = (address & 0xfff00000) | /* virtual aligned to 1M */
+							MCF_MMU_MMUTR_SG |		/* shared global */
+							MCF_MMU_MMUTR_V;		/* valid */
+
+			MCF_MMU_MMUDR = (address & 0xfff00000) |	/* physical aligned to 1M */
+							MCF_MMU_MMUDR_SZ(0) |	/* 1 MB page size */
+							MCF_MMU_MMUDR_CM(0x1) |	/* cacheable copyback */
+							MCF_MMU_MMUDR_R |		/* read access enable */
+							MCF_MMU_MMUDR_W |		/* write access enable */
+							MCF_MMU_MMUDR_X;		/* execute access enable */
+
+			MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
+							MCF_MMU_MMUOR_UAA;		/* update allocation address field */
+
+			MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
+							MCF_MMU_MMUOR_ACC |     /* access TLB */
+							MCF_MMU_MMUOR_UAA;      /* update allocation address field */
 	}
-
-
-	if (mmu_status & MCF_MMU_MMUSR_HIT)		/* did the last fault hit in TLB? */
-	{
-		/*
-		 * if yes, then we already mapped that page during a previous turn and this is in fact a bus error
-		 */
-		return false;
-	}
-	else
-	{
-		struct mmu_mapping *map;
-
-
-		if ((map = lookup_mapping(fault_address)) != NULL)
-		{
-			uint32_t mask;
-
-			switch (map->pagesize)
-			{
-				case MMU_PAGE_SIZE_1M:
-					mask = ~(0x100000 - 1);
-					break;
-				case MMU_PAGE_SIZE_4K:
-					mask = ~(0x1000 - 1);
-					break;
-				case MMU_PAGE_SIZE_8K:
-					mask = ~(0x2000 - 1);
-					break;
-				case MMU_PAGE_SIZE_1K:
-					mask = ~(0x400 - 1);
-					break;
-			}
-
-			mmu_map_page(fault_address & mask, fault_address & mask, map->pagesize, map->flags);
-			return true;
-		}
-	}
-	return false;
-}
-
-
-void mmu_map_page(uint32_t virt, uint32_t phys, uint32_t map_size, struct map_flags flags)
-{
-
-	/*
-	 * add page to TLB
-	 */
-	MCF_MMU_MMUTR = virt |					/* virtual address */
-		MCF_MMU_MMUTR_ID(flags.page_id) |
-		MCF_MMU_MMUTR_SG |					/* shared global */
-		MCF_MMU_MMUTR_V;					/* valid */
-
-	MCF_MMU_MMUDR = phys |					/* physical address */
-		MCF_MMU_MMUDR_SZ(map_size) |		/* 1 MB page size */
-		MCF_MMU_MMUDR_CM(flags.cache_mode) |
-		(flags.access & ACCESS_READ ? MCF_MMU_MMUDR_R : 0) |		/* read access enable */
-		(flags.access & ACCESS_WRITE ? MCF_MMU_MMUDR_W : 0) |		/* write access enable */
-		(flags.access & ACCESS_EXECUTE ? MCF_MMU_MMUDR_X : 0);		/* execute access enable */
-
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |		/* access TLB, data */
-		MCF_MMU_MMUOR_UAA;					/* update allocation address field */
-
-	MCF_MMU_MMUOR = MCF_MMU_MMUOR_ITLB | 	/* instruction */
-		MCF_MMU_MMUOR_ACC |     			/* access TLB */
-		MCF_MMU_MMUOR_UAA;      			/* update allocation address field */
-	dbg("mapped virt=%p to phys=%p\r\n", virt, phys);
 }