Markus Fröschle
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f933b5e782
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removed (most) stuck buffers
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2016-07-28 05:33:31 +00:00 |
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Markus Fröschle
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08aa845d55
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add firebee_utils_pkg
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2016-06-04 06:36:00 +00:00 |
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Markus Fröschle
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053a5a2a25
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formatting
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2016-06-03 07:43:07 +00:00 |
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Markus Fröschle
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1352e1a23d
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replace translator output with more clear VHDL
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2016-06-02 16:28:02 +00:00 |
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Markus Fröschle
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cd6d306be0
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more fixes
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2016-06-02 15:57:06 +00:00 |
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Markus Fröschle
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143c278e31
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multiple driver problem
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2016-04-28 04:34:30 +00:00 |
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Markus Fröschle
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ec52731146
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reenable nFB_TA
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2016-04-27 15:08:14 +00:00 |
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Markus Fröschle
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9141e2aa3b
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remove unneeded component declarations
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2016-04-27 11:32:14 +00:00 |
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Markus Fröschle
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8510d5aa39
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remove strange constant assignment
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2016-04-27 05:59:07 +00:00 |
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Markus Fröschle
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2157aad3c4
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fix assignment vector length
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2016-04-27 05:24:49 +00:00 |
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Markus Fröschle
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ad11bc7f96
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fix number of bits to compare
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2016-04-26 19:58:21 +00:00 |
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Markus Fröschle
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85e924cc44
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reformatting
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2016-04-26 19:34:39 +00:00 |
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Markus Fröschle
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f58bbb5f6d
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simplify and fix errors
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2016-04-26 16:39:22 +00:00 |
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Markus Fröschle
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676422b0c4
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add function f_addr_cmp()
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2016-04-26 06:14:03 +00:00 |
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Markus Fröschle
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52c7e4a4a1
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change formatting
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2016-04-25 19:09:52 +00:00 |
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Markus Fröschle
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6bd7bf2a0b
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fix timing violation at border color assignment
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2016-04-14 18:11:14 +00:00 |
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Markus Fröschle
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848f101ea1
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fix hsync len calculation for Firebee mode
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2016-04-14 05:56:39 +00:00 |
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Markus Fröschle
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0d3c010348
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make it compile again
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2016-02-10 17:06:57 +00:00 |
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Markus Fröschle
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bdeeaa2746
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cast to std_logic_vector
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2016-01-19 17:36:29 +00:00 |
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Markus Fröschle
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90a4b52bf3
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modify to use WHEN statements instead of binary logic
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2016-01-19 15:50:36 +00:00 |
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Markus Fröschle
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5c01dc00b2
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remove specialised clocks
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2016-01-19 07:27:27 +00:00 |
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Markus Fröschle
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06fe2148cf
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removed more "indirect" clocks
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2016-01-19 07:07:31 +00:00 |
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Markus Fröschle
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d531d35825
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get rid of BUFFER parameters
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2016-01-18 18:32:50 +00:00 |
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Markus Fröschle
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8758f9d374
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hold time fix test
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2016-01-18 18:15:02 +00:00 |
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Markus Fröschle
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c59958eb12
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more flexbus_register work
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2016-01-18 07:40:08 +00:00 |
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Markus Fröschle
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8136567933
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add more functionality
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2016-01-17 21:45:53 +00:00 |
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Markus Fröschle
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ef585d16c2
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start of flexbus_register implementation to simplify that
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2016-01-17 20:28:18 +00:00 |
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Markus Fröschle
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5a0a331c09
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fix 13MHz clock sdc
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2016-01-17 08:43:20 +00:00 |
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Markus Fröschle
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694d5386d1
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fix timing
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2016-01-16 21:38:17 +00:00 |
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Markus Fröschle
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45894cb3f2
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simplify processes
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2016-01-15 08:37:40 +00:00 |
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Markus Fröschle
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85b4c0f33d
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fix video base address and video counter register
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2016-01-14 22:02:44 +00:00 |
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Markus Fröschle
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e6cc4daf5c
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reformat
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2016-01-14 16:49:11 +00:00 |
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Markus Fröschle
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e8bb97b338
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reformat
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2016-01-14 07:17:08 +00:00 |
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Markus Fröschle
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d5f341d7b5
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remove unused connections
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2016-01-14 06:45:15 +00:00 |
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Markus Fröschle
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829675f564
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formatting
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2016-01-14 06:44:52 +00:00 |
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Markus Fröschle
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d410f3c8fa
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remove unused generated signals
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2016-01-13 16:43:54 +00:00 |
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Markus Fröschle
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30227f5f4e
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reactivated delay chain
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2016-01-13 15:04:24 +00:00 |
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Markus Fröschle
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014d28e80f
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reformat
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2016-01-13 13:23:46 +00:00 |
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Markus Fröschle
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7c35d1a9e6
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remove AHDL files
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2016-01-13 12:54:00 +00:00 |
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Markus Fröschle
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d3e950cb42
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finish conversion to vhdl
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2016-01-13 12:53:03 +00:00 |
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Markus Fröschle
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9901817422
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reformat internal signals
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2016-01-13 07:27:57 +00:00 |
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Markus Fröschle
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9bd96486a6
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renamed pixel_clk_i
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2016-01-13 07:16:24 +00:00 |
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Markus Fröschle
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b4666bc264
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reformat
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2016-01-12 17:11:07 +00:00 |
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Markus Fröschle
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2c9e60e5e1
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fix formatting
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2016-01-12 08:00:20 +00:00 |
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Markus Fröschle
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26e1aef29b
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reformat converted VHDL
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2016-01-12 07:14:33 +00:00 |
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Markus Fröschle
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69e2ed8cb1
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translate DDR_CTR to vhd
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2016-01-11 17:55:18 +00:00 |
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Markus Fröschle
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d281dcf94e
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add more DDR clk signals to sdc
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2016-01-11 17:05:39 +00:00 |
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Markus Fröschle
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17c41a655f
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translate interrupt_controller to vhd
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2016-01-11 16:11:04 +00:00 |
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Markus Fröschle
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5b8820e371
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replace video.bdf with video.vhd
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2016-01-11 08:43:42 +00:00 |
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Markus Fröschle
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d919644895
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reformat
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2016-01-11 07:13:36 +00:00 |
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