Markus Fröschle
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674406e4d3
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formatting
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2014-12-24 17:54:51 +00:00 |
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Markus Fröschle
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71db27849b
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started implementing SAMSUNG's Verilog DDR model in VHDL
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2014-12-23 22:30:23 +00:00 |
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Markus Fröschle
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5eac75430e
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renamed files, fixed testbench
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2014-12-23 18:20:11 +00:00 |
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Markus Fröschle
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04c32593cf
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renamed RAM model
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2014-12-21 08:33:17 +00:00 |
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Markus Fröschle
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db93ec6026
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updated testbench (not functional yet)
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2014-12-21 08:32:20 +00:00 |
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Markus Fröschle
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dd3a3e9da4
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started simulator for DDR RAM
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2014-06-16 14:35:54 +00:00 |
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