Markus Fröschle
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a7eb46e158
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used design assistant to force the fitter to put more effort into getting the timing right which removed negative slack
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2014-12-25 10:08:53 +00:00 |
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Markus Fröschle
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517599bc33
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reenabled all modules
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2014-12-24 16:11:12 +00:00 |
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Markus Fröschle
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e7e4fa4e75
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added a little bus toggling to the test bench
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2014-12-24 09:42:57 +00:00 |
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Markus Fröschle
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766d75a5d3
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fixed pin assignments for renamed pins fb_cs_n[..]
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2014-12-23 22:35:03 +00:00 |
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Markus Fröschle
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63c0a2f167
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added testbench files
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2014-12-23 18:25:15 +00:00 |
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Markus Fröschle
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5cc8c3bbbf
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fixed type inconistencies
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2014-12-23 16:44:21 +00:00 |
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Markus Fröschle
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c197609be6
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started "full fledged" testbench to analyze where fb_ta_n gets lost
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2014-12-23 14:56:53 +00:00 |
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Markus Fröschle
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85ec4c726c
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added io_register.vhd
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2014-12-22 22:14:33 +00:00 |
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Markus Fröschle
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e2c69a75f6
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changed all STD_LOGIC_VECTOR signals to UNSIGNED to ease calculations
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2014-12-22 12:09:53 +00:00 |
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Markus Fröschle
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e0a1dfedcf
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enabled flow analysis
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2014-12-22 10:05:59 +00:00 |
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Markus Fröschle
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4bb0527539
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fifo_mw never got a value assigned - fixed for testbench, but still open for toplevel
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2014-12-22 08:31:07 +00:00 |
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Markus Fröschle
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89f75bd4e8
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fixed IRQn[x] to IRQ_n[x]
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2014-12-22 06:42:16 +00:00 |
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Markus Fröschle
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2de4cceb00
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fixed assignment to the new postfixed names
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2014-12-22 06:37:25 +00:00 |
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Markus Fröschle
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ff7faf4395
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more formatting and corrections of testbench code
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2014-12-21 10:55:49 +00:00 |
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Markus Fröschle
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db93ec6026
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updated testbench (not functional yet)
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2014-12-21 08:32:20 +00:00 |
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Markus Fröschle
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132f136d3a
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relaxed timing and uncommented unneeded components in toplevel until timing issues are solved
added lots of set_false_path statements to sort out timing problems
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2014-12-20 12:26:32 +00:00 |
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Markus Fröschle
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599b23bdcf
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renamed directory hierarchy and toplevel entity
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2014-12-20 08:34:53 +00:00 |
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Markus Fröschle
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e5f37977e1
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renamed files
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2014-12-20 08:26:37 +00:00 |
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Markus Fröschle
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282c631601
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added false_path to CLK_MAIN
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2014-08-17 08:43:43 +00:00 |
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Markus Fröschle
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b73b59f372
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fixed wrong pin assignment for FB_WRn
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2014-08-17 08:42:26 +00:00 |
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Markus Fröschle
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3691c94c5c
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added constraints for global clock signals
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2014-08-14 05:30:45 +00:00 |
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Markus Fröschle
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1134454984
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disabled SignalTap
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2014-08-09 19:45:29 +00:00 |
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Markus Fröschle
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cf659204c8
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fixed formatting
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2014-08-09 19:17:09 +00:00 |
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Markus Fröschle
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e9f5ee1ed3
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added missing assignments and wrong pins for differential clock
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2014-08-09 17:34:08 +00:00 |
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Markus Fröschle
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2aee4d9c45
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fixed a bug in wiring of I_RECONFIG (data_in was connected to FB_ADR(24 downto 16) instead ot FB_AD(24 downto 16) and reformatted files
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2014-08-08 17:48:19 +00:00 |
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Markus Fröschle
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cf56eece67
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fixed a few more problems resulting from changing libraries
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2014-08-06 19:49:32 +00:00 |
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Markus Fröschle
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b40ddd37fc
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2014-08-04 20:27:57 +00:00 |
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Markus Fröschle
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4c2be14e28
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removed all dependencies to obsolete ieee.std_logic_arith and ieee.std_logic_unsigned in favour of ieee.numeric_std. There are a few things that still need to be fixed because of that, however.
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2014-08-04 17:23:47 +00:00 |
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Markus Fröschle
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fe7d35a212
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fixed typo
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2014-07-09 19:14:40 +00:00 |
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Markus Fröschle
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dd3a3e9da4
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started simulator for DDR RAM
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2014-06-16 14:35:54 +00:00 |
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Markus Fröschle
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55889b9e7b
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started memory write state machine in testbench
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2014-06-13 21:23:35 +00:00 |
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Markus Fröschle
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40e6a71e47
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started testbench bus transaction implementation
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2014-06-13 06:26:42 +00:00 |
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Markus Fröschle
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05a13bdf16
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added clock signals
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2014-06-11 17:52:44 +00:00 |
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Markus Fröschle
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8d0ede14c8
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worked on testbench
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2014-06-11 16:41:25 +00:00 |
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Markus Fröschle
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2c29f6a232
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tried less restrictive option to speed up synthesis
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2014-06-10 06:52:16 +00:00 |
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Markus Fröschle
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727aa5bce9
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initial import after removal of FPGA_quartus
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2014-06-09 20:35:29 +00:00 |
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