3 Commits

Author	SHA1	Message	Date
Markus Fröschle	71db27849b	started implementing SAMSUNG's Verilog DDR model in VHDL	2014-12-23 22:30:23 +00:00
Markus Fröschle	5eac75430e	renamed files, fixed testbench	2014-12-23 18:20:11 +00:00
Markus Fröschle	c197609be6	started "full fledged" testbench to analyze where fb_ta_n gets lost	2014-12-23 14:56:53 +00:00