5 Commits

Author	SHA1	Message	Date
Markus Fröschle	71db27849b	started implementing SAMSUNG's Verilog DDR model in VHDL	2014-12-23 22:30:23 +00:00
Markus Fröschle	5eac75430e	renamed files, fixed testbench	2014-12-23 18:20:11 +00:00
Markus Fröschle	04c32593cf	renamed RAM model	2014-12-21 08:33:17 +00:00
Markus Fröschle	db93ec6026	updated testbench (not functional yet)	2014-12-21 08:32:20 +00:00
Markus Fröschle	dd3a3e9da4	started simulator for DDR RAM	2014-06-16 14:35:54 +00:00