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more formatting and corrections of testbench code

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This commit is contained in:
Markus Fröschle
2014-12-21 10:55:49 +00:00
parent 04c32593cf
commit ff7faf4395
5 changed files with 512 additions and 510 deletions
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14
vhdl/backend/Altera/Firebee/firebee.qsf
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@@ -296,9 +296,7 @@ set_location_assignment PIN_B12 -to DACK0n
set_location_assignment PIN_T22 -to TOUT0n set_location_assignment PIN_T22 -to TOUT0n
set_location_assignment PIN_AB17 -to CLK_DDR_OUT set_location_assignment PIN_AB17 -to CLK_DDR_OUT
set_location_assignment PIN_AA17 -to CLK_DDR_OUTn set_location_assignment PIN_AA17 -to CLK_DDR_OUTn
set_location_assignment PIN_AB18 -to VCASn
set_location_assignment PIN_T18 -to VCSn set_location_assignment PIN_T18 -to VCSn
set_location_assignment PIN_W17 -to VRASn
set_location_assignment PIN_Y17 -to VWEn set_location_assignment PIN_Y17 -to VWEn
set_location_assignment PIN_AA15 -to VD_QS[0] set_location_assignment PIN_AA15 -to VD_QS[0]
set_location_assignment PIN_W15 -to VD_QS[1] set_location_assignment PIN_W15 -to VD_QS[1]
@@ -628,9 +626,7 @@ set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_D0
set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_D3 set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_D3
set_instance_assignment -name IO_STANDARD "2.5 V" -to VD_QS set_instance_assignment -name IO_STANDARD "2.5 V" -to VD_QS
set_instance_assignment -name IO_STANDARD "2.5 V" -to VWEn set_instance_assignment -name IO_STANDARD "2.5 V" -to VWEn
set_instance_assignment -name IO_STANDARD "2.5 V" -to VRASn
set_instance_assignment -name IO_STANDARD "2.5 V" -to VCSn set_instance_assignment -name IO_STANDARD "2.5 V" -to VCSn
set_instance_assignment -name IO_STANDARD "2.5 V" -to VCASn
set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC
set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to CLK_PIXEL set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to CLK_PIXEL
set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC
@@ -642,8 +638,6 @@ set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IRQn[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VCSn set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VCSn
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD_QS set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD_QS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VWEn set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VWEn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VRASn
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VCASn
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to CLK_PIXEL set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to CLK_PIXEL
set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to BLANKn set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to BLANKn
@@ -687,6 +681,12 @@ set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to CLK_DDR_OUTn
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to CLK_25M set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to CLK_25M
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ram_model.vhd -section_id ddr_ctlr_tb set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr2_ram_model.vhd -section_id ddr_ctlr_tb
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb
set_location_assignment PIN_AB18 -to VCAS_n
set_location_assignment PIN_W17 -to VRAS_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to VRAS_n
set_instance_assignment -name IO_STANDARD "2.5 V" -to VCAS_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VRAS_n
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VCAS_n
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

16
vhdl/rtl/vhdl/DDR/DDR_CTRL.vhd
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@@ -68,11 +68,11 @@ ENTITY DDR_CTRL IS
fifo_mw : IN STD_LOGIC_VECTOR (8 DOWNTO 0); fifo_mw : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
va : OUT STD_LOGIC_VECTOR (12 DOWNTO 0); -- video Adress bus at the DDR chips va : OUT STD_LOGIC_VECTOR (12 DOWNTO 0); -- video Adress bus at the DDR chips
vwen : OUT STD_LOGIC; -- video memory write enable vwe_n : OUT STD_LOGIC; -- video memory write enable
vrasn : OUT STD_LOGIC; -- video memory RAS vras_n : OUT STD_LOGIC; -- video memory RAS
VCSn : OUT STD_LOGIC; -- video memory chip SELECT vcs_n : OUT STD_LOGIC; -- video memory chip SELECT
VCKE : OUT STD_LOGIC; -- video memory clock enable VCKE : OUT STD_LOGIC; -- video memory clock enable
vcasn : OUT STD_LOGIC; -- video memory CAS vcas_n : OUT STD_LOGIC; -- video memory CAS
FB_LE : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); FB_LE : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
FB_VDOE : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); FB_VDOE : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
@@ -784,16 +784,16 @@ BEGIN
-- VIDEO RAM CONTROL REGISTER (IS IN VIDEO_MUX_CTR) -- VIDEO RAM CONTROL REGISTER (IS IN VIDEO_MUX_CTR)
-- $F0000400: BIT 0: VCKE; 1: NOT nVCS ;2:REFRESH ON , (0=fifo AND CNT CLEAR); -- $F0000400: BIT 0: VCKE; 1: NOT nVCS ;2:REFRESH ON , (0=fifo AND CNT CLEAR);
-- 3: CONFIG; 8: fifo_active; -- 3: CONFIG; 8: fifo_active;
VCSn <= NOT(video_control_register(vrcr_refresh_on)); vcs_n <= NOT(video_control_register(vrcr_refresh_on));
ddr_config <= video_control_register(3); ddr_config <= video_control_register(3);
fifo_active <= video_control_register(8); fifo_active <= video_control_register(8);
cpu_row_adr <= fb_adr(26 DOWNTO 14); cpu_row_adr <= fb_adr(26 DOWNTO 14);
cpu_ba <= fb_adr(13 DOWNTO 12); cpu_ba <= fb_adr(13 DOWNTO 12);
cpu_col_adr <= fb_adr(11 DOWNTO 2); cpu_col_adr <= fb_adr(11 DOWNTO 2);
vrasn <= NOT vras; vras_n <= NOT vras;
vcasn <= NOT vcas; vcas_n <= NOT vcas;
vwen <= NOT vwe; vwe_n <= NOT vwe;
ddrwr_d_sel1 <= '1' WHEN ddr_access = blitter ELSE '0'; ddrwr_d_sel1 <= '1' WHEN ddr_access = blitter ELSE '0';

16
vhdl/rtl/vhdl/Firebee/Firebee.vhd
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@@ -126,10 +126,10 @@ ENTITY firebee IS
va : OUT STD_LOGIC_VECTOR (12 DOWNTO 0); va : OUT STD_LOGIC_VECTOR (12 DOWNTO 0);
ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); ba : OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
VWEn : OUT STD_LOGIC; vwe_n : OUT STD_LOGIC;
VcaSn : OUT STD_LOGIC; vcas_n : OUT STD_LOGIC;
vrASn : OUT STD_LOGIC; vras_n : OUT STD_LOGIC;
VCSn : OUT STD_LOGIC; vcs_n : OUT STD_LOGIC;
clk_pixel : OUT STD_LOGIC; clk_pixel : OUT STD_LOGIC;
SYNCn : OUT STD_LOGIC; SYNCn : OUT STD_LOGIC;
@@ -809,10 +809,10 @@ BEGIN
va => va, va => va,
fb_le => fb_le, fb_le => fb_le,
CLK_33M => CLK_33M, CLK_33M => CLK_33M,
vrASn => vrASn, vras_n => vras_n,
VcaSn => VcaSn, vcas_n => vcas_n,
VWEn => VWEn, vwe_n => vwe_n,
VCSn => VCSn, vcs_n => vcs_n,
fifo_clr => fifo_clr, fifo_clr => fifo_clr,
DDRCLK0 => clk_ddr(0), DDRCLK0 => clk_ddr(0),
video_control_register => video_ram_ctr, video_control_register => video_ram_ctr,

961
vhdl/rtl/vhdl/Firebee/Firebee_pkg.vhd
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File diff suppressed because it is too large Load Diff

15
vhdl/testbenches/ddr_ctlr_tb.vhd
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@@ -34,9 +34,9 @@ ARCHITECTURE beh OF ddr_ctlr_tb IS
SIGNAL CLK_33M : STD_LOGIC := '0'; SIGNAL CLK_33M : STD_LOGIC := '0';
SIGNAL FIFO_MW : STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL FIFO_MW : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL va : STD_LOGIC_VECTOR(12 DOWNTO 0); SIGNAL va : STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL vwe_n : STD_LOGIC; SIGNAL vwe_n : STD_LOGIC;
SIGNAL vras_n : STD_LOGIC; SIGNAL vras_n : STD_LOGIC;
SIGNAL vcs_n : STD_LOGIC; SIGNAL vcs_n : STD_LOGIC;
SIGNAL vcke : STD_LOGIC; SIGNAL vcke : STD_LOGIC;
SIGNAL vcas_n : STD_LOGIC; SIGNAL vcas_n : STD_LOGIC;
SIGNAL FB_LE : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL FB_LE : STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -117,10 +117,11 @@ BEGIN
dm_rdqs(0) => data_en_l, dm_rdqs(0) => data_en_l,
dm_rdqs(1) => data_en_h, dm_rdqs(1) => data_en_h,
ba => ba, ba => ba,
addr => va (25 DOWNTO 13), addr => va,
DQ => sr_vdmp, DQ => sr_vdmp,
LDQS => data_en_l, dqs(0) => data_en_l,
UDQS => data_en_h dqs(1) => data_en_h,
odt => '0'
); );
stimulate_main_clock : process stimulate_main_clock : process
@@ -156,13 +157,13 @@ BEGIN
WHEN S1 => WHEN S1 =>
-- data phase -- data phase
FB_ALE <= '0'; FB_ALE <= '0';
FB_CS1n <= '0'; fb_cs1_n <= '0';
FB_ADR <= x"47114711"; FB_ADR <= x"47114711";
if (VIDEO_DDR_TA = '1') then if (VIDEO_DDR_TA = '1') then
bus_state <= S2; bus_state <= S2;
END if; END if;
WHEN S2 => WHEN S2 =>
FB_CS1n <= '0'; fb_cs1_n <= '0';
bus_state <= S3; bus_state <= S3;
WHEN S3 => WHEN S3 =>
FB_ADR <= STD_LOGIC_VECTOR(UNSIGNED(FB_ADR) + 4); FB_ADR <= STD_LOGIC_VECTOR(UNSIGNED(FB_ADR) + 4);