178 lines
4.6 KiB
VHDL
178 lines
4.6 KiB
VHDL
LIBRARY work;
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USE work.firebee_pkg.ALL;
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USE work.ddr2_ram_model_pkg.ALL;
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE std.textio.ALL;
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ENTITY ddr_ctlr_tb IS
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END ddr_ctlr_tb;
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ARCHITECTURE beh OF ddr_ctlr_tb IS
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SIGNAL clock : STD_LOGIC := '0'; -- main clock
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SIGNAL ddr_clk : STD_LOGIC := '0'; -- ddr clock
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SIGNAL FB_ADR : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL DDR_SYNC_66M : STD_LOGIC := '0';
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SIGNAL FB_CS1_n : STD_LOGIC;
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SIGNAL FB_OE_n : STD_LOGIC := '1'; -- only write cycles for now
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SIGNAL FB_SIZE0 : STD_LOGIC := '1';
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SIGNAL FB_SIZE1 : STD_LOGIC := '1'; -- long word access
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SIGNAL FB_ALE : STD_LOGIC := 'Z'; -- defined reset state
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SIGNAL FB_WRn : STD_LOGIC;
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SIGNAL FIFO_CLR : STD_LOGIC;
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SIGNAL VIDEO_RAM_CTR : STD_LOGIC_VECTOR(15 DOWNTO 0);
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SIGNAL BLITTER_ADR : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL BLITTER_SIG : STD_LOGIC;
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SIGNAL BLITTER_WR : STD_LOGIC;
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SIGNAL ddrclk0 : STD_LOGIC;
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SIGNAL CLK_33M : STD_LOGIC := '0';
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SIGNAL FIFO_MW : STD_LOGIC_VECTOR(8 DOWNTO 0);
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SIGNAL va : STD_LOGIC_VECTOR(12 DOWNTO 0);
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SIGNAL vwe_n : STD_LOGIC;
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SIGNAL vras_n : STD_LOGIC;
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SIGNAL vcs_n : STD_LOGIC;
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SIGNAL vcke : STD_LOGIC;
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SIGNAL vcas_n : STD_LOGIC;
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SIGNAL FB_LE : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL FB_VDOE : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL SR_FIFO_WRE : STD_LOGIC;
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SIGNAL SR_DDR_FB : STD_LOGIC;
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SIGNAL SR_DDR_WR : STD_LOGIC;
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SIGNAL SR_DDRWR_D_SEL : STD_LOGIC;
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SIGNAL sr_vdmp : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL VIDEO_DDR_TA : STD_LOGIC;
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SIGNAL SR_BLITTER_DACK : STD_LOGIC;
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SIGNAL ba : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL DDRWR_D_SEL1 : STD_LOGIC;
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SIGNAL VDM_SEL : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL DATA_IN : STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL DATA_OUT : STD_LOGIC_VECTOR(31 DOWNTO 16);
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SIGNAL data_en_h : STD_LOGIC;
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SIGNAL data_en_l : STD_LOGIC;
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TYPE bus_state_t IS (S0, S1, S2, S3); -- according to state machine description on p 17-14 of the MCF ref manual
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SIGNAL bus_state : bus_state_t := S0;
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BEGIN
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t : DDR_CTRL
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PORT map
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(
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CLK_MAIN => clock,
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DDR_SYNC_66M => DDR_SYNC_66M,
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FB_ADR => FB_ADR,
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FB_CS1_n => fb_cs1_n,
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FB_OE_n => FB_OE_n,
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FB_SIZE0 => FB_SIZE0,
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FB_SIZE1 => FB_SIZE1,
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FB_ALE => FB_ALE,
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FB_WR_n => FB_WRn,
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FIFO_CLR => FIFO_CLR,
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video_control_register => VIDEO_RAM_CTR,
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BLITTER_ADR => BLITTER_ADR,
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BLITTER_SIG => BLITTER_SIG,
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BLITTER_WR => BLITTER_WR,
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ddrclk0 => ddrclk0,
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CLK_33M => CLK_33M,
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FIFO_MW => FIFO_MW,
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va => va,
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vwe_n => vwe_n,
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vras_n => vras_n,
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vcs_n => vcs_n,
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vcke => vcke,
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vcas_n => vcas_n,
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FB_LE => FB_LE,
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FB_VDOE => FB_VDOE,
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SR_FIFO_WRE => SR_FIFO_WRE,
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SR_DDR_FB => SR_DDR_FB,
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SR_DDR_WR => SR_DDR_WR,
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SR_DDRWR_D_SEL => SR_DDRWR_D_SEL,
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sr_vdmp => sr_vdmp,
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VIDEO_DDR_TA => VIDEO_DDR_TA,
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SR_BLITTER_DACK => SR_BLITTER_DACK,
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ba => ba,
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DDRWR_D_SEL1 => DDRWR_D_SEL1,
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VDM_SEL => VDM_SEL,
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DATA_IN => DATA_IN,
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DATA_OUT => DATA_OUT,
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data_en_h => data_en_h,
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data_en_l => data_en_l
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);
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d1 : ddr2_ram_model
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PORT map
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(
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ck => ddrclk0,
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ck_n => NOT ddrclk0,
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cke => vcke,
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cs_n => vcs_n,
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ras_n => vras_n,
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cas_n => vcas_n,
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we_n => vwe_n,
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dm_rdqs(0) => data_en_l,
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dm_rdqs(1) => data_en_h,
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ba => ba,
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addr => va,
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DQ => sr_vdmp,
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dqs(0) => data_en_l,
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dqs(1) => data_en_h,
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odt => '0'
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);
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stimulate_main_clock : process
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BEGIN
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WAIT FOR 4.31 ns;
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clock <= NOT clock;
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END process;
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stimulate_33mHz_clock : process
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BEGIN
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WAIT FOR 30.3 ns;
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CLK_33M <= NOT CLK_33M;
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END process;
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stimulate_66MHz_clock : process
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BEGIN
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WAIT FOR 66.6 ns;
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DDR_SYNC_66M <= NOT DDR_SYNC_66M;
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ddrclk0 <= DDR_SYNC_66M;
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END process;
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stimulate : process
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VARIABLE adr : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
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BEGIN
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WAIT UNTIL RISING_EDGE(clock);
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CASE bus_state IS
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WHEN S0 =>
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-- address phase
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FB_ADR <= adr;
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FB_ALE <= '1';
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FB_WRn <= '0';
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bus_state <= S1;
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WHEN S1 =>
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-- data phase
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FB_ALE <= '0';
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fb_cs1_n <= '0';
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FB_ADR <= x"47114711";
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if (VIDEO_DDR_TA = '1') then
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bus_state <= S2;
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END if;
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WHEN S2 =>
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fb_cs1_n <= '0';
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bus_state <= S3;
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WHEN S3 =>
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FB_ADR <= STD_LOGIC_VECTOR(UNSIGNED(FB_ADR) + 4);
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bus_state <= S0;
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FB_WRn <= 'Z';
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WHEN others =>
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REPORT("bus_state: ");
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END CASE;
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END process;
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END beh;
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