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fixed typo

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This commit is contained in:
Markus Fröschle
2014-07-09 19:14:40 +00:00
parent 948fd2c798
commit fe7d35a212
3 changed files with 40 additions and 42 deletions
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10
vhdl/backend/Altera/Firebee/firebee.qsf
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@@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP3C40F484C6
set_global_assignment -name TOP_LEVEL_ENTITY firebee set_global_assignment -name TOP_LEVEL_ENTITY firebee
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:04:08 MAY 31, 2014" set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:04:08 MAY 31, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -608,7 +608,9 @@ set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll4:I_PLL4|altpll:al
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll4:I_PLL4|altpll:altpll_component|clk[2]" set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll4:I_PLL4|altpll:altpll_component|clk[2]"
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll4:I_PLL4|altpll:altpll_component|clk[3]" set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll4:I_PLL4|altpll:altpll_component|clk[3]"
set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[0]" set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[0]"
set_global_assignment -name SDC_FILE firebee.sdc set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ns"
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ram_model.vhd -section_id ddr_ctlr_tb
set_global_assignment -name SOURCE_FILE firebee.qsf set_global_assignment -name SOURCE_FILE firebee.qsf
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/DDR/DDR_CTRL.vhd set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/DDR/DDR_CTRL.vhd
@@ -669,8 +671,6 @@ set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/altpll1.vhd
set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee_V1/altpll1.cmp set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee_V1/altpll1.cmp
set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd
set_global_assignment -name QIP_FILE ../../../rtl/vhdl/Firebee_V1/altpll_reconfig1.qip set_global_assignment -name QIP_FILE ../../../rtl/vhdl/Firebee_V1/altpll_reconfig1.qip
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ns"
set_global_assignment -name VHDL_FILE ../../../testbenches/ddr_ram_model.vhd set_global_assignment -name VHDL_FILE ../../../testbenches/ddr_ram_model.vhd
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ram_model.vhd -section_id ddr_ctlr_tb
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

70
vhdl/rtl/vhdl/DSP/DSP.vhd
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@@ -27,44 +27,42 @@ USE ieee.std_logic_1164.all;
-- Entity Declaration -- Entity Declaration
ENTITY DSP IS ENTITY DSP IS
port( port(
CLK_33M : in std_logic; CLK_33M : in std_logic;
CLK_MAIN : in std_logic; CLK_MAIN : in std_logic;
FB_OEn : in std_logic; FB_OEn : in std_logic;
FB_WRn : in std_logic; FB_WRn : in std_logic;
FB_CS1n : in std_logic; FB_CS1n : in std_logic;
FB_CS2n : in std_logic; FB_CS2n : in std_logic;
FB_SIZE0 : in std_logic; FB_SIZE0 : in std_logic;
FB_SIZE1 : in std_logic; FB_SIZE1 : in std_logic;
FB_BURSTn : in std_logic; FB_BURSTn : in std_logic;
FB_ADR : in std_logic_vector(31 downto 0); FB_ADR : in std_logic_vector(31 downto 0);
RESETn : in std_logic; RESETn : in std_logic;
FB_CS3n : in std_logic; FB_CS3n : in std_logic;
SRCSn : buffer std_logic; SRCSn : buffer std_logic;
SRBLEn : out std_logic; SRBLEn : out std_logic;
SRBHEn : out std_logic; SRBHEn : out std_logic;
SRWEn : out std_logic; SRWEn : out std_logic;
SROEn : out std_logic; SROEn : out std_logic;
DSP_INT : out std_logic; DSP_INT : out std_logic;
DSP_TA : out std_logic; DSP_TA : out std_logic;
FB_AD_IN : in std_logic_vector(31 downto 0); FB_AD_IN : in std_logic_vector(31 downto 0);
FB_AD_OUT : out std_logic_vector(31 downto 0); FB_AD_OUT : out std_logic_vector(31 downto 0);
FB_AD_EN : out std_logic; FB_AD_EN : out std_logic;
IO_IN : in std_logic_vector(17 downto 0); IO_IN : in std_logic_vector(17 downto 0);
IO_OUT : out std_logic_vector(17 downto 0); IO_OUT : out std_logic_vector(17 downto 0);
IO_EN : out std_logic; IO_EN : out std_logic;
SRD_IN : in std_logic_vector(15 downto 0); SRD_IN : in std_logic_vector(15 downto 0);
SRD_OUT : out std_logic_vector(15 downto 0); SRD_OUT : out std_logic_vector(15 downto 0);
SRD_EN : out std_logic SRD_EN : out std_logic
); );
END DSP; END DSP;
-- Architecture Body -- Architecture Body
ARCHITECTURE DSP_architecture OF DSP IS ARCHITECTURE DSP_architecture OF DSP IS
BEGIN BEGIN
SRCSn <= '0' when FB_CS2n = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --FB_CS3n; SRCSn <= '0' when FB_CS2n = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --FB_CS3n;
SRBHEn <= '0' when FB_ADR(0 downto 0) = "0" else '1'; SRBHEn <= '0' when FB_ADR(0 downto 0) = "0" else '1';
@@ -74,10 +72,10 @@ BEGIN
DSP_INT <= '0'; DSP_INT <= '0';
DSP_TA <= '0'; DSP_TA <= '0';
IO_OUT(17 downto 0) <= FB_ADR(18 downto 1); IO_OUT(17 downto 0) <= FB_ADR(18 downto 1);
IO_EN <= '1'; IO_EN <= '1';
SRD_OUT(15 downto 0) <= FB_AD_IN(31 downto 16) when FB_WRn = '0' and SRCSn = '0' else x"0000"; SRD_OUT(15 downto 0) <= FB_AD_IN(31 downto 16) when FB_WRn = '0' and SRCSn = '0' else x"0000";
SRD_EN <= '1' when FB_WRn = '0' and SRCSn = '0' else '0'; SRD_EN <= '1' when FB_WRn = '0' and SRCSn = '0' else '0';
FB_AD_OUT(31 downto 16) <= SRD_IN(15 downto 0) when FB_OEn = '0' and SRCSn = '0' else x"0000"; FB_AD_OUT(31 downto 16) <= SRD_IN(15 downto 0) when FB_OEn = '0' and SRCSn = '0' else x"0000";
FB_AD_OUT(15 downto 0) <= SRD_IN(15 downto 0) when FB_OEn = '0' and SRCSn = '0' else x"0000"; FB_AD_OUT(15 downto 0) <= SRD_IN(15 downto 0) when FB_OEn = '0' and SRCSn = '0' else x"0000";
FB_AD_EN <= '1' when FB_OEn = '0' and SRCSn = '0' else '0'; FB_AD_EN <= '1' when FB_OEn = '0' and SRCSn = '0' else '0';
END DSP_architecture; END DSP_architecture;

2
vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd
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@@ -45,7 +45,7 @@
-- Replaced the graphical top level by a VHDL model. -- Replaced the graphical top level by a VHDL model.
-- The new toplevel is now FIREBEE_V1. -- The new toplevel is now FIREBEE_V1.
-- Replaced the graphical Video Top Level by a VHDL model -- Replaced the graphical Video Top Level by a VHDL model
-- The DDR_CTR is no DDR_CTRL. -- The DDR_CTR is now DDR_CTRL.
-- Rewritten the DDR_CTR in VHDL. -- Rewritten the DDR_CTR in VHDL.
-- Moved the DDR_CTRL to the FIREBEE_V1 top level. -- Moved the DDR_CTRL to the FIREBEE_V1 top level.
-- Moved the BLITTER to the FIREBEE_V1 top level. -- Moved the BLITTER to the FIREBEE_V1 top level.