From fe7d35a212b21929ec895427056ab6cb9228a6a8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 9 Jul 2014 19:14:40 +0000 Subject: [PATCH] fixed typo --- vhdl/backend/Altera/Firebee/firebee.qsf | 10 +-- vhdl/rtl/vhdl/DSP/DSP.vhd | 70 ++++++++++----------- vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd | 2 +- 3 files changed, 40 insertions(+), 42 deletions(-) diff --git a/vhdl/backend/Altera/Firebee/firebee.qsf b/vhdl/backend/Altera/Firebee/firebee.qsf index 17c9a48..4e017a5 100755 --- a/vhdl/backend/Altera/Firebee/firebee.qsf +++ b/vhdl/backend/Altera/Firebee/firebee.qsf @@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP3C40F484C6 set_global_assignment -name TOP_LEVEL_ENTITY firebee set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:04:08 MAY 31, 2014" -set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 @@ -608,7 +608,9 @@ set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll4:I_PLL4|altpll:al set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll4:I_PLL4|altpll:altpll_component|clk[2]" set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll4:I_PLL4|altpll:altpll_component|clk[3]" set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to "altpll1:I_PLL1|altpll:altpll_component|clk[0]" -set_global_assignment -name SDC_FILE firebee.sdc +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ns" +set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb +set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ram_model.vhd -section_id ddr_ctlr_tb set_global_assignment -name SOURCE_FILE firebee.qsf set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/DDR/DDR_CTRL.vhd @@ -669,8 +671,6 @@ set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/altpll1.vhd set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee_V1/altpll1.cmp set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd set_global_assignment -name QIP_FILE ../../../rtl/vhdl/Firebee_V1/altpll_reconfig1.qip -set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ns" set_global_assignment -name VHDL_FILE ../../../testbenches/ddr_ram_model.vhd -set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb -set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ram_model.vhd -section_id ddr_ctlr_tb +set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/vhdl/rtl/vhdl/DSP/DSP.vhd b/vhdl/rtl/vhdl/DSP/DSP.vhd index 77699b2..49aebad 100644 --- a/vhdl/rtl/vhdl/DSP/DSP.vhd +++ b/vhdl/rtl/vhdl/DSP/DSP.vhd @@ -27,44 +27,42 @@ USE ieee.std_logic_1164.all; -- Entity Declaration ENTITY DSP IS - port( - CLK_33M : in std_logic; - CLK_MAIN : in std_logic; - FB_OEn : in std_logic; - FB_WRn : in std_logic; - FB_CS1n : in std_logic; - FB_CS2n : in std_logic; - FB_SIZE0 : in std_logic; - FB_SIZE1 : in std_logic; - FB_BURSTn : in std_logic; - FB_ADR : in std_logic_vector(31 downto 0); - RESETn : in std_logic; - FB_CS3n : in std_logic; -SRCSn : buffer std_logic; - SRBLEn : out std_logic; - SRBHEn : out std_logic; - SRWEn : out std_logic; - SROEn : out std_logic; - DSP_INT : out std_logic; - DSP_TA : out std_logic; - FB_AD_IN : in std_logic_vector(31 downto 0); - FB_AD_OUT : out std_logic_vector(31 downto 0); - FB_AD_EN : out std_logic; - IO_IN : in std_logic_vector(17 downto 0); - IO_OUT : out std_logic_vector(17 downto 0); - IO_EN : out std_logic; - SRD_IN : in std_logic_vector(15 downto 0); - SRD_OUT : out std_logic_vector(15 downto 0); - SRD_EN : out std_logic - ); + port( + CLK_33M : in std_logic; + CLK_MAIN : in std_logic; + FB_OEn : in std_logic; + FB_WRn : in std_logic; + FB_CS1n : in std_logic; + FB_CS2n : in std_logic; + FB_SIZE0 : in std_logic; + FB_SIZE1 : in std_logic; + FB_BURSTn : in std_logic; + FB_ADR : in std_logic_vector(31 downto 0); + RESETn : in std_logic; + FB_CS3n : in std_logic; + SRCSn : buffer std_logic; + SRBLEn : out std_logic; + SRBHEn : out std_logic; + SRWEn : out std_logic; + SROEn : out std_logic; + DSP_INT : out std_logic; + DSP_TA : out std_logic; + FB_AD_IN : in std_logic_vector(31 downto 0); + FB_AD_OUT : out std_logic_vector(31 downto 0); + FB_AD_EN : out std_logic; + IO_IN : in std_logic_vector(17 downto 0); + IO_OUT : out std_logic_vector(17 downto 0); + IO_EN : out std_logic; + SRD_IN : in std_logic_vector(15 downto 0); + SRD_OUT : out std_logic_vector(15 downto 0); + SRD_EN : out std_logic + ); END DSP; -- Architecture Body ARCHITECTURE DSP_architecture OF DSP IS - - BEGIN SRCSn <= '0' when FB_CS2n = '0' and FB_ADR(27 downto 24) = x"4" else '1'; --FB_CS3n; SRBHEn <= '0' when FB_ADR(0 downto 0) = "0" else '1'; @@ -74,10 +72,10 @@ BEGIN DSP_INT <= '0'; DSP_TA <= '0'; IO_OUT(17 downto 0) <= FB_ADR(18 downto 1); - IO_EN <= '1'; + IO_EN <= '1'; SRD_OUT(15 downto 0) <= FB_AD_IN(31 downto 16) when FB_WRn = '0' and SRCSn = '0' else x"0000"; - SRD_EN <= '1' when FB_WRn = '0' and SRCSn = '0' else '0'; + SRD_EN <= '1' when FB_WRn = '0' and SRCSn = '0' else '0'; FB_AD_OUT(31 downto 16) <= SRD_IN(15 downto 0) when FB_OEn = '0' and SRCSn = '0' else x"0000"; - FB_AD_OUT(15 downto 0) <= SRD_IN(15 downto 0) when FB_OEn = '0' and SRCSn = '0' else x"0000"; - FB_AD_EN <= '1' when FB_OEn = '0' and SRCSn = '0' else '0'; + FB_AD_OUT(15 downto 0) <= SRD_IN(15 downto 0) when FB_OEn = '0' and SRCSn = '0' else x"0000"; + FB_AD_EN <= '1' when FB_OEn = '0' and SRCSn = '0' else '0'; END DSP_architecture; diff --git a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd b/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd index 1ac5ab3..5e42ee2 100644 --- a/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd +++ b/vhdl/rtl/vhdl/Firebee_V1/Firebee_V1_Top.vhd @@ -45,7 +45,7 @@ -- Replaced the graphical top level by a VHDL model. -- The new toplevel is now FIREBEE_V1. -- Replaced the graphical Video Top Level by a VHDL model --- The DDR_CTR is no DDR_CTRL. +-- The DDR_CTR is now DDR_CTRL. -- Rewritten the DDR_CTR in VHDL. -- Moved the DDR_CTRL to the FIREBEE_V1 top level. -- Moved the BLITTER to the FIREBEE_V1 top level.