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First full HDL version

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torlus
2014-03-03 21:04:21 +00:00
parent f378ec7051
commit efc98f83bc
367 changed files with 85885 additions and 0 deletions
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7
FPGA_quartus_GE/altddio_out3.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
set_global_assignment -name IP_TOOL_VERSION "8.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out3.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.cmp"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.ppf"]