From efc98f83bc3d4e265cc4043fd2c5964f124994ad Mon Sep 17 00:00:00 2001
From: torlus <torlus>
Date: Mon, 3 Mar 2014 21:04:21 +0000
Subject: [PATCH] First full HDL version

---
 FPGA_quartus_GE/DSP/DSP.vhd                   |    79 +
 FPGA_quartus_GE/DSP/DSP.vhd.bak               |    79 +
 FPGA_quartus_GE/DSP/dsp56k.zip                |   Bin 0 -> 39208 bytes
 FPGA_quartus_GE/DSP/src/adgen_stage.vhd       |   216 +
 FPGA_quartus_GE/DSP/src/constants_pkg.vhd     |    62 +
 FPGA_quartus_GE/DSP/src/decode_stage.vhd      |  1221 ++
 FPGA_quartus_GE/DSP/src/exec_stage_alu.vhd    |   603 +
 .../DSP/src/exec_stage_bit_modify.vhd         |    79 +
 FPGA_quartus_GE/DSP/src/exec_stage_branch.vhd |   117 +
 .../DSP/src/exec_stage_cc_flag_calc.vhd       |    75 +
 FPGA_quartus_GE/DSP/src/exec_stage_cr_mod.vhd |    72 +
 FPGA_quartus_GE/DSP/src/exec_stage_loops.vhd  |   200 +
 FPGA_quartus_GE/DSP/src/fetch_stage.vhd       |    60 +
 FPGA_quartus_GE/DSP/src/mem_control.vhd       |  1519 +++
 FPGA_quartus_GE/DSP/src/memory_management.vhd |   206 +
 FPGA_quartus_GE/DSP/src/parameter_pkg.vhd     |    10 +
 FPGA_quartus_GE/DSP/src/pipeline.vhd          |   968 ++
 FPGA_quartus_GE/DSP/src/reg_file.vhd          |   679 +
 FPGA_quartus_GE/DSP/src/types_pkg.vhd         |   167 +
 .../FalconIO_SDCard_IDE_CF.vhd                |   971 ++
 .../FalconIO_SDCard_IDE_CF.vhd.bak            |   971 ++
 .../FalconIO_SDCard_IDE_CF_pgk.vhd            |   406 +
 .../FalconIO_SDCard_IDE_CF_pgk.vhd.bak        |   406 +
 .../WF5380/wf5380_control.vhd                 |   631 +
 .../WF5380/wf5380_pkg.vhd                     |   139 +
 .../WF5380/wf5380_registers.vhd               |   265 +
 .../WF5380/wf5380_soc_top.vhd                 |   300 +
 .../WF5380/wf5380_top.vhd                     |   275 +
 .../WF_FDC1772_IP/wf1772ip_am_detector.vhd    |   253 +
 .../WF_FDC1772_IP/wf1772ip_control.vhd        |  1463 +++
 .../WF_FDC1772_IP/wf1772ip_crc_logic.vhd      |   162 +
 .../WF_FDC1772_IP/wf1772ip_digital_pll.vhd    |   426 +
 .../WF_FDC1772_IP/wf1772ip_pkg.vhd            |   232 +
 .../WF_FDC1772_IP/wf1772ip_registers.vhd      |   264 +
 .../WF_FDC1772_IP/wf1772ip_top.vhd            |   154 +
 .../WF_FDC1772_IP/wf1772ip_top_soc.vhd        |   333 +
 .../WF_FDC1772_IP/wf1772ip_transceiver.vhd    |   517 +
 .../WF_MFP68901_IP/wf68901ip_gpio.vhd         |   141 +
 .../WF_MFP68901_IP/wf68901ip_interrupts.vhd   |   391 +
 .../WF_MFP68901_IP/wf68901ip_pkg.vhd          |   263 +
 .../WF_MFP68901_IP/wf68901ip_timers.vhd       |   533 +
 .../WF_MFP68901_IP/wf68901ip_top.vhd          |   213 +
 .../WF_MFP68901_IP/wf68901ip_top_soc.vhd      |   309 +
 .../WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd   |   191 +
 .../WF_MFP68901_IP/wf68901ip_usart_rx.vhd     |   590 +
 .../WF_MFP68901_IP/wf68901ip_usart_top.vhd    |   238 +
 .../WF_MFP68901_IP/wf68901ip_usart_tx.vhd     |   387 +
 .../WF_SDC_IF/sd-card-interface.vhd           |   228 +
 .../WF_SDC_IF/sd-card-interface_soc.vhd       |   240 +
 .../WF_SDC_IF/sd-card-interface_soc.vhd.bak   |   239 +
 .../WF_SND2149_IP/wf2149ip_pkg.vhd            |    84 +
 .../WF_SND2149_IP/wf2149ip_top.vhd            |   170 +
 .../WF_SND2149_IP/wf2149ip_top_soc.vhd        |   229 +
 .../WF_SND2149_IP/wf2149ip_wave.vhd           |   533 +
 .../WF_UART6850_IP/wf6850ip_ctrl_status.vhd   |   244 +
 .../wf6850ip_ctrl_status.vhd.bak              |   244 +
 .../WF_UART6850_IP/wf6850ip_receive.vhd       |   415 +
 .../WF_UART6850_IP/wf6850ip_receive.vhd.bak   |   415 +
 .../WF_UART6850_IP/wf6850ip_top.vhd           |   135 +
 .../WF_UART6850_IP/wf6850ip_top_soc.vhd       |   255 +
 .../WF_UART6850_IP/wf6850ip_top_soc.vhd.bak   |   252 +
 .../WF_UART6850_IP/wf6850ip_transmit.vhd      |   339 +
 .../WF_UART6850_IP/wf6850ip_transmit.vhd.bak  |   339 +
 .../FalconIO_SDCard_IDE_CF/dcfifo0.bsf        |    95 +
 .../FalconIO_SDCard_IDE_CF/dcfifo0.cmp        |    28 +
 .../FalconIO_SDCard_IDE_CF/dcfifo0.qip        |     5 +
 .../FalconIO_SDCard_IDE_CF/dcfifo0.vhd        |   202 +
 .../FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak    |   202 +
 .../FalconIO_SDCard_IDE_CF/dcfifo1.bsf        |    95 +
 .../FalconIO_SDCard_IDE_CF/dcfifo1.cmp        |    28 +
 .../FalconIO_SDCard_IDE_CF/dcfifo1.qip        |     5 +
 .../FalconIO_SDCard_IDE_CF/dcfifo1.vhd        |   202 +
 .../FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak    |   202 +
 .../Interrupt_Handler/interrupt_handler.tdf   |   478 +
 .../Interrupt_Handler/interrupt_handler.v     |  3615 ++++++
 FPGA_quartus_GE/PLLJ_PLLSPE_INFO.txt          |    20 +
 FPGA_quartus_GE/UNUSED                        |    27 +
 FPGA_quartus_GE/Video/BLITTER/BLITTER.vhd     |    75 +
 FPGA_quartus_GE/Video/BLITTER/BLITTER.vhd.bak |    75 +
 FPGA_quartus_GE/Video/DDR_CTR.tdf             |   659 +
 FPGA_quartus_GE/Video/DDR_CTR.tdf.bak         |   660 +
 FPGA_quartus_GE/Video/DDR_CTR.v               |  1095 ++
 FPGA_quartus_GE/Video/DDR_CTR_BLITTER.tdf.bak |   352 +
 FPGA_quartus_GE/Video/UNUSED                  |   267 +
 .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf           |   675 +
 .../Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak       |   675 +
 FPGA_quartus_GE/Video/VIDEO_MOD_MUX_CLUTCTR.v |  1500 +++
 FPGA_quartus_GE/Video/Video.bdf               | 10651 ++++++++++++++++
 FPGA_quartus_GE/Video/altddio_bidir0.bsf      |    99 +
 FPGA_quartus_GE/Video/altddio_bidir0.inc      |    30 +
 FPGA_quartus_GE/Video/altddio_bidir0.ppf      |    16 +
 FPGA_quartus_GE/Video/altddio_bidir0.qip      |     7 +
 FPGA_quartus_GE/Video/altddio_bidir0.vhd      |   172 +
 FPGA_quartus_GE/Video/altddio_out0.bsf        |    64 +
 FPGA_quartus_GE/Video/altddio_out0.inc        |    25 +
 FPGA_quartus_GE/Video/altddio_out0.ppf        |    11 +
 FPGA_quartus_GE/Video/altddio_out0.qip        |     7 +
 FPGA_quartus_GE/Video/altddio_out0.vhd        |   136 +
 FPGA_quartus_GE/Video/altddio_out1.bsf        |    64 +
 FPGA_quartus_GE/Video/altddio_out1.inc        |    25 +
 FPGA_quartus_GE/Video/altddio_out1.ppf        |    11 +
 FPGA_quartus_GE/Video/altddio_out1.qip        |     7 +
 FPGA_quartus_GE/Video/altddio_out1.vhd        |   146 +
 FPGA_quartus_GE/Video/altddio_out2.bsf        |    64 +
 FPGA_quartus_GE/Video/altddio_out2.inc        |    25 +
 FPGA_quartus_GE/Video/altddio_out2.ppf        |    11 +
 FPGA_quartus_GE/Video/altddio_out2.qip        |     7 +
 FPGA_quartus_GE/Video/altddio_out2.vhd        |   136 +
 FPGA_quartus_GE/Video/altdpram0.bsf           |   173 +
 FPGA_quartus_GE/Video/altdpram0.inc           |    31 +
 FPGA_quartus_GE/Video/altdpram0.qip           |     6 +
 FPGA_quartus_GE/Video/altdpram0.vhd           |   273 +
 FPGA_quartus_GE/Video/altdpram1.bsf           |   173 +
 FPGA_quartus_GE/Video/altdpram1.inc           |    31 +
 FPGA_quartus_GE/Video/altdpram1.qip           |     6 +
 FPGA_quartus_GE/Video/altdpram1.vhd           |   273 +
 FPGA_quartus_GE/Video/altdpram2.bsf           |   173 +
 FPGA_quartus_GE/Video/altdpram2.inc           |    31 +
 FPGA_quartus_GE/Video/altdpram2.qip           |     6 +
 FPGA_quartus_GE/Video/altdpram2.vhd           |   273 +
 FPGA_quartus_GE/Video/lpm_bustri0.bsf         |    56 +
 FPGA_quartus_GE/Video/lpm_bustri0.inc         |    24 +
 FPGA_quartus_GE/Video/lpm_bustri0.qip         |     6 +
 FPGA_quartus_GE/Video/lpm_bustri0.vhd         |   107 +
 FPGA_quartus_GE/Video/lpm_bustri1.bsf         |    56 +
 FPGA_quartus_GE/Video/lpm_bustri1.qip         |     5 +
 FPGA_quartus_GE/Video/lpm_bustri1.vhd         |   107 +
 FPGA_quartus_GE/Video/lpm_bustri2.bsf         |    56 +
 FPGA_quartus_GE/Video/lpm_bustri2.qip         |     5 +
 FPGA_quartus_GE/Video/lpm_bustri2.vhd         |   107 +
 FPGA_quartus_GE/Video/lpm_bustri3.bsf         |    56 +
 FPGA_quartus_GE/Video/lpm_bustri3.qip         |     5 +
 FPGA_quartus_GE/Video/lpm_bustri3.vhd         |   107 +
 FPGA_quartus_GE/Video/lpm_bustri4.bsf         |    56 +
 FPGA_quartus_GE/Video/lpm_bustri4.qip         |     5 +
 FPGA_quartus_GE/Video/lpm_bustri4.vhd         |   107 +
 FPGA_quartus_GE/Video/lpm_bustri5.bsf         |    56 +
 FPGA_quartus_GE/Video/lpm_bustri5.inc         |    24 +
 FPGA_quartus_GE/Video/lpm_bustri5.qip         |     6 +
 FPGA_quartus_GE/Video/lpm_bustri5.vhd         |   107 +
 FPGA_quartus_GE/Video/lpm_bustri6.bsf         |    56 +
 FPGA_quartus_GE/Video/lpm_bustri6.qip         |     5 +
 FPGA_quartus_GE/Video/lpm_bustri6.vhd         |   107 +
 FPGA_quartus_GE/Video/lpm_bustri7.bsf         |    56 +
 FPGA_quartus_GE/Video/lpm_bustri7.qip         |     5 +
 FPGA_quartus_GE/Video/lpm_bustri7.vhd         |   107 +
 FPGA_quartus_GE/Video/lpm_compare1.bsf        |    54 +
 FPGA_quartus_GE/Video/lpm_compare1.inc        |    24 +
 FPGA_quartus_GE/Video/lpm_compare1.qip        |     6 +
 FPGA_quartus_GE/Video/lpm_compare1.vhd        |   127 +
 FPGA_quartus_GE/Video/lpm_constant0.bsf       |    42 +
 FPGA_quartus_GE/Video/lpm_constant0.qip       |     5 +
 FPGA_quartus_GE/Video/lpm_constant0.vhd       |   108 +
 FPGA_quartus_GE/Video/lpm_constant1.bsf       |    42 +
 FPGA_quartus_GE/Video/lpm_constant1.inc       |    23 +
 FPGA_quartus_GE/Video/lpm_constant1.qip       |     6 +
 FPGA_quartus_GE/Video/lpm_constant1.vhd       |   108 +
 FPGA_quartus_GE/Video/lpm_constant2.bsf       |    42 +
 FPGA_quartus_GE/Video/lpm_constant2.qip       |     5 +
 FPGA_quartus_GE/Video/lpm_constant2.vhd       |   108 +
 FPGA_quartus_GE/Video/lpm_constant3.bsf       |    42 +
 FPGA_quartus_GE/Video/lpm_constant3.qip       |     5 +
 FPGA_quartus_GE/Video/lpm_constant3.vhd       |   108 +
 FPGA_quartus_GE/Video/lpm_constant4.bsf       |    42 +
 FPGA_quartus_GE/Video/lpm_constant4.inc       |    23 +
 FPGA_quartus_GE/Video/lpm_constant4.qip       |     6 +
 FPGA_quartus_GE/Video/lpm_constant4.vhd       |   108 +
 FPGA_quartus_GE/Video/lpm_ff0.bsf             |    63 +
 FPGA_quartus_GE/Video/lpm_ff0.qip             |     5 +
 FPGA_quartus_GE/Video/lpm_ff0.vhd             |   127 +
 FPGA_quartus_GE/Video/lpm_ff1.bsf             |    56 +
 FPGA_quartus_GE/Video/lpm_ff1.qip             |     5 +
 FPGA_quartus_GE/Video/lpm_ff1.vhd             |   122 +
 FPGA_quartus_GE/Video/lpm_ff2.bsf             |    56 +
 FPGA_quartus_GE/Video/lpm_ff2.qip             |     5 +
 FPGA_quartus_GE/Video/lpm_ff2.vhd             |   122 +
 FPGA_quartus_GE/Video/lpm_ff3.bsf             |    56 +
 FPGA_quartus_GE/Video/lpm_ff3.qip             |     5 +
 FPGA_quartus_GE/Video/lpm_ff3.vhd             |   122 +
 FPGA_quartus_GE/Video/lpm_ff4.bsf             |    56 +
 FPGA_quartus_GE/Video/lpm_ff4.inc             |    24 +
 FPGA_quartus_GE/Video/lpm_ff4.qip             |     6 +
 FPGA_quartus_GE/Video/lpm_ff4.vhd             |   122 +
 FPGA_quartus_GE/Video/lpm_ff5.bsf             |    56 +
 FPGA_quartus_GE/Video/lpm_ff5.inc             |    24 +
 FPGA_quartus_GE/Video/lpm_ff5.qip             |     6 +
 FPGA_quartus_GE/Video/lpm_ff5.vhd             |   122 +
 FPGA_quartus_GE/Video/lpm_ff6.bsf             |    63 +
 FPGA_quartus_GE/Video/lpm_ff6.inc             |    25 +
 FPGA_quartus_GE/Video/lpm_ff6.qip             |     6 +
 FPGA_quartus_GE/Video/lpm_ff6.vhd             |   127 +
 FPGA_quartus_GE/Video/lpm_fifoDZ.bsf          |    79 +
 FPGA_quartus_GE/Video/lpm_fifoDZ.qip          |     5 +
 FPGA_quartus_GE/Video/lpm_fifoDZ.vhd          |   178 +
 FPGA_quartus_GE/Video/lpm_fifo_dc0.bsf        |   102 +
 FPGA_quartus_GE/Video/lpm_fifo_dc0.inc        |    30 +
 FPGA_quartus_GE/Video/lpm_fifo_dc0.qip        |     6 +
 FPGA_quartus_GE/Video/lpm_fifo_dc0.vhd        |   203 +
 FPGA_quartus_GE/Video/lpm_latch1.bsf          |    53 +
 FPGA_quartus_GE/Video/lpm_latch1.qip          |     5 +
 FPGA_quartus_GE/Video/lpm_latch1.vhd          |   110 +
 FPGA_quartus_GE/Video/lpm_mux0.bsf            |    83 +
 FPGA_quartus_GE/Video/lpm_mux0.inc            |    28 +
 FPGA_quartus_GE/Video/lpm_mux0.qip            |     6 +
 FPGA_quartus_GE/Video/lpm_mux0.vhd            |   251 +
 FPGA_quartus_GE/Video/lpm_mux1.bsf            |   111 +
 FPGA_quartus_GE/Video/lpm_mux1.inc            |    32 +
 FPGA_quartus_GE/Video/lpm_mux1.qip            |     6 +
 FPGA_quartus_GE/Video/lpm_mux1.vhd            |   271 +
 FPGA_quartus_GE/Video/lpm_mux2.bsf            |   167 +
 FPGA_quartus_GE/Video/lpm_mux2.inc            |    40 +
 FPGA_quartus_GE/Video/lpm_mux2.qip            |     6 +
 FPGA_quartus_GE/Video/lpm_mux2.vhd            |   311 +
 FPGA_quartus_GE/Video/lpm_mux3.bsf            |    60 +
 FPGA_quartus_GE/Video/lpm_mux3.qip            |     5 +
 FPGA_quartus_GE/Video/lpm_mux3.vhd            |   115 +
 FPGA_quartus_GE/Video/lpm_mux4.bsf            |    60 +
 FPGA_quartus_GE/Video/lpm_mux4.qip            |     5 +
 FPGA_quartus_GE/Video/lpm_mux4.vhd            |   125 +
 FPGA_quartus_GE/Video/lpm_mux5.bsf            |    74 +
 FPGA_quartus_GE/Video/lpm_mux5.inc            |    27 +
 FPGA_quartus_GE/Video/lpm_mux5.qip            |     6 +
 FPGA_quartus_GE/Video/lpm_mux5.vhd            |   373 +
 FPGA_quartus_GE/Video/lpm_mux6.bsf            |   111 +
 FPGA_quartus_GE/Video/lpm_mux6.inc            |    32 +
 FPGA_quartus_GE/Video/lpm_mux6.qip            |     6 +
 FPGA_quartus_GE/Video/lpm_mux6.vhd            |   335 +
 FPGA_quartus_GE/Video/lpm_muxDZ.bsf           |    76 +
 FPGA_quartus_GE/Video/lpm_muxDZ.qip           |     5 +
 FPGA_quartus_GE/Video/lpm_muxDZ.vhd           |   377 +
 FPGA_quartus_GE/Video/lpm_muxDZ2.bsf          |    60 +
 FPGA_quartus_GE/Video/lpm_muxDZ2.qip          |     5 +
 FPGA_quartus_GE/Video/lpm_muxDZ2.vhd          |   115 +
 FPGA_quartus_GE/Video/lpm_muxVDM.bsf          |   158 +
 FPGA_quartus_GE/Video/lpm_muxVDM.qip          |     5 +
 FPGA_quartus_GE/Video/lpm_muxVDM.vhd          |  2225 ++++
 FPGA_quartus_GE/Video/lpm_shiftreg0.bsf       |    70 +
 FPGA_quartus_GE/Video/lpm_shiftreg0.inc       |    26 +
 FPGA_quartus_GE/Video/lpm_shiftreg0.qip       |     6 +
 FPGA_quartus_GE/Video/lpm_shiftreg0.vhd       |   135 +
 FPGA_quartus_GE/Video/lpm_shiftreg1.bsf       |    56 +
 FPGA_quartus_GE/Video/lpm_shiftreg1.qip       |     5 +
 FPGA_quartus_GE/Video/lpm_shiftreg1.vhd       |   125 +
 FPGA_quartus_GE/Video/lpm_shiftreg2.bsf       |    56 +
 FPGA_quartus_GE/Video/lpm_shiftreg2.qip       |     5 +
 FPGA_quartus_GE/Video/lpm_shiftreg2.vhd       |   125 +
 FPGA_quartus_GE/Video/lpm_shiftreg3.bsf       |    56 +
 FPGA_quartus_GE/Video/lpm_shiftreg3.inc       |    24 +
 FPGA_quartus_GE/Video/lpm_shiftreg3.qip       |     6 +
 FPGA_quartus_GE/Video/lpm_shiftreg3.vhd       |   125 +
 FPGA_quartus_GE/Video/lpm_shiftreg4.bsf       |    56 +
 FPGA_quartus_GE/Video/lpm_shiftreg4.inc       |    24 +
 FPGA_quartus_GE/Video/lpm_shiftreg4.qip       |     6 +
 FPGA_quartus_GE/Video/lpm_shiftreg4.vhd       |   125 +
 FPGA_quartus_GE/Video/lpm_shiftreg5.bsf       |    56 +
 FPGA_quartus_GE/Video/lpm_shiftreg5.inc       |    24 +
 FPGA_quartus_GE/Video/lpm_shiftreg5.qip       |     6 +
 FPGA_quartus_GE/Video/lpm_shiftreg5.vhd       |   125 +
 FPGA_quartus_GE/Video/lpm_shiftreg6.bsf       |    56 +
 FPGA_quartus_GE/Video/lpm_shiftreg6.inc       |    24 +
 FPGA_quartus_GE/Video/lpm_shiftreg6.qip       |     6 +
 FPGA_quartus_GE/Video/lpm_shiftreg6.vhd       |   125 +
 FPGA_quartus_GE/Video/mux41_0.v               |    30 +
 FPGA_quartus_GE/Video/mux41_0.vhd             |    52 +
 FPGA_quartus_GE/Video/mux41_1.v               |    30 +
 FPGA_quartus_GE/Video/mux41_1.vhd             |    52 +
 FPGA_quartus_GE/Video/mux41_2.v               |    31 +
 FPGA_quartus_GE/Video/mux41_2.vhd             |    54 +
 FPGA_quartus_GE/Video/mux41_3.v               |    31 +
 FPGA_quartus_GE/Video/mux41_3.vhd             |    54 +
 FPGA_quartus_GE/Video/mux41_4.v               |    31 +
 FPGA_quartus_GE/Video/mux41_4.vhd             |    54 +
 FPGA_quartus_GE/Video/mux41_5.v               |    31 +
 FPGA_quartus_GE/Video/mux41_5.vhd             |    54 +
 FPGA_quartus_GE/Video/video.v                 |  1288 ++
 FPGA_quartus_GE/Video/video.vhd               |  1755 +++
 FPGA_quartus_GE/ahdl2v/DDR_CTR.tdf            |   662 +
 FPGA_quartus_GE/ahdl2v/DDR_CTR.v              |  1095 ++
 .../ahdl2v/VIDEO_MOD_MUX_CLUTCTR.tdf          |   684 +
 .../ahdl2v/VIDEO_MOD_MUX_CLUTCTR.v            |  1474 +++
 FPGA_quartus_GE/ahdl2v/interrupt_handler.tdf  |   478 +
 FPGA_quartus_GE/ahdl2v/interrupt_handler.v    |  3578 ++++++
 FPGA_quartus_GE/ahdl2v/lpm_bustri.tdf         |    78 +
 FPGA_quartus_GE/ahdl2v/lpm_bustri_BYT.inc     |    24 +
 FPGA_quartus_GE/ahdl2v/lpm_bustri_BYT.tdf     |    72 +
 FPGA_quartus_GE/ahdl2v/lpm_bustri_BYT.v       |    78 +
 FPGA_quartus_GE/ahdl2v/lpm_bustri_LONG.inc    |    24 +
 FPGA_quartus_GE/ahdl2v/lpm_bustri_LONG.tdf    |    72 +
 FPGA_quartus_GE/ahdl2v/lpm_bustri_WORD.inc    |    24 +
 FPGA_quartus_GE/ahdl2v/lpm_bustri_WORD.tdf    |    72 +
 FPGA_quartus_GE/ahdl2v/lpm_bustri_WORD.v      |    99 +
 FPGA_quartus_GE/ahdl2v/xport.exe              |   Bin 0 -> 566272 bytes
 FPGA_quartus_GE/altddio_out0.bsf              |    64 +
 FPGA_quartus_GE/altddio_out0.inc              |    25 +
 FPGA_quartus_GE/altddio_out0.ppf              |    11 +
 FPGA_quartus_GE/altddio_out0.qip              |     7 +
 FPGA_quartus_GE/altddio_out0.vhd              |   146 +
 FPGA_quartus_GE/altddio_out3.bsf              |    64 +
 FPGA_quartus_GE/altddio_out3.inc              |    25 +
 FPGA_quartus_GE/altddio_out3.ppf              |    11 +
 FPGA_quartus_GE/altddio_out3.qip              |     7 +
 FPGA_quartus_GE/altddio_out3.vhd              |   146 +
 FPGA_quartus_GE/altpll0.bsf                   |   117 +
 FPGA_quartus_GE/altpll0.inc                   |    27 +
 FPGA_quartus_GE/altpll0.ppf                   |    13 +
 FPGA_quartus_GE/altpll0.qip                   |     7 +
 FPGA_quartus_GE/altpll0.vhd                   |   477 +
 FPGA_quartus_GE/altpll1.bsf                   |   100 +
 FPGA_quartus_GE/altpll1.inc                   |    26 +
 FPGA_quartus_GE/altpll1.ppf                   |    12 +
 FPGA_quartus_GE/altpll1.qip                   |     7 +
 FPGA_quartus_GE/altpll1.vhd                   |   423 +
 FPGA_quartus_GE/altpll2.bsf                   |   117 +
 FPGA_quartus_GE/altpll2.inc                   |    27 +
 FPGA_quartus_GE/altpll2.ppf                   |    13 +
 FPGA_quartus_GE/altpll2.qip                   |     7 +
 FPGA_quartus_GE/altpll2.vhd                   |   477 +
 FPGA_quartus_GE/altpll3.bsf                   |   105 +
 FPGA_quartus_GE/altpll3.inc                   |    26 +
 FPGA_quartus_GE/altpll3.ppf                   |    12 +
 FPGA_quartus_GE/altpll3.qip                   |     7 +
 FPGA_quartus_GE/altpll3.vhd                   |   445 +
 FPGA_quartus_GE/altpll4.bsf                   |   125 +
 FPGA_quartus_GE/altpll4.inc                   |    31 +
 FPGA_quartus_GE/altpll4.mif                   |   174 +
 FPGA_quartus_GE/altpll4.ppf                   |    17 +
 FPGA_quartus_GE/altpll4.qip                   |     7 +
 FPGA_quartus_GE/altpll4.tdf                   |   298 +
 FPGA_quartus_GE/altpll_reconfig0.bsf          |   162 +
 FPGA_quartus_GE/altpll_reconfig0.qip          |     5 +
 FPGA_quartus_GE/altpll_reconfig1.bsf          |   162 +
 FPGA_quartus_GE/altpll_reconfig1.inc          |    39 +
 FPGA_quartus_GE/altpll_reconfig1.qip          |     6 +
 FPGA_quartus_GE/altpll_reconfig1.tdf          |   144 +
 .../altpll_reconfig1_pllrcfg_bju.tdf          |   583 +
 .../altpll_reconfig1_pllrcfg_t4q.tdf          |   582 +
 FPGA_quartus_GE/firebee1.bdf                  |  5837 +++++++++
 FPGA_quartus_GE/firebee1.done                 |     1 +
 FPGA_quartus_GE/firebee1.qpf                  |    30 +
 FPGA_quartus_GE/firebee1.qsf                  |   852 ++
 FPGA_quartus_GE/firebee1.qws                  |   Bin 0 -> 1252 bytes
 FPGA_quartus_GE/firebee1.rbf                  |   Bin 0 -> 416499 bytes
 FPGA_quartus_GE/firebee1.sdc                  |   179 +
 FPGA_quartus_GE/firebee1.v                    |   698 +
 FPGA_quartus_GE/firebee1.vhd                  |   861 ++
 .../firebee1_assignment_defaults.qdf          |   687 +
 FPGA_quartus_GE/firebee1_description.txt      |     0
 FPGA_quartus_GE/lpm_bustri_BYT.bsf            |    56 +
 FPGA_quartus_GE/lpm_bustri_BYT.inc            |    24 +
 FPGA_quartus_GE/lpm_bustri_BYT.qip            |     6 +
 FPGA_quartus_GE/lpm_bustri_BYT.vhd            |   107 +
 FPGA_quartus_GE/lpm_bustri_LONG.bsf           |    56 +
 FPGA_quartus_GE/lpm_bustri_LONG.inc           |    24 +
 FPGA_quartus_GE/lpm_bustri_LONG.qip           |     6 +
 FPGA_quartus_GE/lpm_bustri_LONG.vhd           |   107 +
 FPGA_quartus_GE/lpm_bustri_WORD.bsf           |    56 +
 FPGA_quartus_GE/lpm_bustri_WORD.inc           |    24 +
 FPGA_quartus_GE/lpm_bustri_WORD.qip           |     6 +
 FPGA_quartus_GE/lpm_bustri_WORD.vhd           |   107 +
 FPGA_quartus_GE/lpm_counter0.bsf              |    49 +
 FPGA_quartus_GE/lpm_counter0.qip              |     5 +
 FPGA_quartus_GE/lpm_counter0.vhd              |   126 +
 FPGA_quartus_GE/lpm_latch0.bsf                |    53 +
 FPGA_quartus_GE/lpm_latch0.qip                |     5 +
 FPGA_quartus_GE/lpm_latch0.vhd                |   110 +
 FPGA_quartus_GE/mux41.v                       |    74 +
 FPGA_quartus_GE/mux41.vhd                     |    90 +
 367 files changed, 85885 insertions(+)
 create mode 100644 FPGA_quartus_GE/DSP/DSP.vhd
 create mode 100644 FPGA_quartus_GE/DSP/DSP.vhd.bak
 create mode 100644 FPGA_quartus_GE/DSP/dsp56k.zip
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 create mode 100644 FPGA_quartus_GE/DSP/src/exec_stage_bit_modify.vhd
 create mode 100644 FPGA_quartus_GE/DSP/src/exec_stage_branch.vhd
 create mode 100644 FPGA_quartus_GE/DSP/src/exec_stage_cc_flag_calc.vhd
 create mode 100644 FPGA_quartus_GE/DSP/src/exec_stage_cr_mod.vhd
 create mode 100644 FPGA_quartus_GE/DSP/src/exec_stage_loops.vhd
 create mode 100644 FPGA_quartus_GE/DSP/src/fetch_stage.vhd
 create mode 100644 FPGA_quartus_GE/DSP/src/mem_control.vhd
 create mode 100644 FPGA_quartus_GE/DSP/src/memory_management.vhd
 create mode 100644 FPGA_quartus_GE/DSP/src/parameter_pkg.vhd
 create mode 100644 FPGA_quartus_GE/DSP/src/pipeline.vhd
 create mode 100644 FPGA_quartus_GE/DSP/src/reg_file.vhd
 create mode 100644 FPGA_quartus_GE/DSP/src/types_pkg.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.bsf
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.cmp
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.qip
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.bsf
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.cmp
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.qip
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.vhd
 create mode 100644 FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak
 create mode 100644 FPGA_quartus_GE/Interrupt_Handler/interrupt_handler.tdf
 create mode 100644 FPGA_quartus_GE/Interrupt_Handler/interrupt_handler.v
 create mode 100644 FPGA_quartus_GE/PLLJ_PLLSPE_INFO.txt
 create mode 100644 FPGA_quartus_GE/UNUSED
 create mode 100644 FPGA_quartus_GE/Video/BLITTER/BLITTER.vhd
 create mode 100644 FPGA_quartus_GE/Video/BLITTER/BLITTER.vhd.bak
 create mode 100644 FPGA_quartus_GE/Video/DDR_CTR.tdf
 create mode 100644 FPGA_quartus_GE/Video/DDR_CTR.tdf.bak
 create mode 100644 FPGA_quartus_GE/Video/DDR_CTR.v
 create mode 100644 FPGA_quartus_GE/Video/DDR_CTR_BLITTER.tdf.bak
 create mode 100644 FPGA_quartus_GE/Video/UNUSED
 create mode 100644 FPGA_quartus_GE/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
 create mode 100644 FPGA_quartus_GE/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
 create mode 100644 FPGA_quartus_GE/Video/VIDEO_MOD_MUX_CLUTCTR.v
 create mode 100644 FPGA_quartus_GE/Video/Video.bdf
 create mode 100644 FPGA_quartus_GE/Video/altddio_bidir0.bsf
 create mode 100644 FPGA_quartus_GE/Video/altddio_bidir0.inc
 create mode 100644 FPGA_quartus_GE/Video/altddio_bidir0.ppf
 create mode 100644 FPGA_quartus_GE/Video/altddio_bidir0.qip
 create mode 100644 FPGA_quartus_GE/Video/altddio_bidir0.vhd
 create mode 100644 FPGA_quartus_GE/Video/altddio_out0.bsf
 create mode 100644 FPGA_quartus_GE/Video/altddio_out0.inc
 create mode 100644 FPGA_quartus_GE/Video/altddio_out0.ppf
 create mode 100644 FPGA_quartus_GE/Video/altddio_out0.qip
 create mode 100644 FPGA_quartus_GE/Video/altddio_out0.vhd
 create mode 100644 FPGA_quartus_GE/Video/altddio_out1.bsf
 create mode 100644 FPGA_quartus_GE/Video/altddio_out1.inc
 create mode 100644 FPGA_quartus_GE/Video/altddio_out1.ppf
 create mode 100644 FPGA_quartus_GE/Video/altddio_out1.qip
 create mode 100644 FPGA_quartus_GE/Video/altddio_out1.vhd
 create mode 100644 FPGA_quartus_GE/Video/altddio_out2.bsf
 create mode 100644 FPGA_quartus_GE/Video/altddio_out2.inc
 create mode 100644 FPGA_quartus_GE/Video/altddio_out2.ppf
 create mode 100644 FPGA_quartus_GE/Video/altddio_out2.qip
 create mode 100644 FPGA_quartus_GE/Video/altddio_out2.vhd
 create mode 100644 FPGA_quartus_GE/Video/altdpram0.bsf
 create mode 100644 FPGA_quartus_GE/Video/altdpram0.inc
 create mode 100644 FPGA_quartus_GE/Video/altdpram0.qip
 create mode 100644 FPGA_quartus_GE/Video/altdpram0.vhd
 create mode 100644 FPGA_quartus_GE/Video/altdpram1.bsf
 create mode 100644 FPGA_quartus_GE/Video/altdpram1.inc
 create mode 100644 FPGA_quartus_GE/Video/altdpram1.qip
 create mode 100644 FPGA_quartus_GE/Video/altdpram1.vhd
 create mode 100644 FPGA_quartus_GE/Video/altdpram2.bsf
 create mode 100644 FPGA_quartus_GE/Video/altdpram2.inc
 create mode 100644 FPGA_quartus_GE/Video/altdpram2.qip
 create mode 100644 FPGA_quartus_GE/Video/altdpram2.vhd
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri0.bsf
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri0.inc
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri0.qip
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri0.vhd
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri1.bsf
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri1.qip
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri1.vhd
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri2.bsf
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri2.qip
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri2.vhd
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri3.bsf
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri3.qip
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri3.vhd
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri4.bsf
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri4.qip
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri4.vhd
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri5.bsf
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri5.inc
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri5.qip
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri5.vhd
 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri6.bsf
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 create mode 100644 FPGA_quartus_GE/Video/lpm_bustri6.vhd
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 create mode 100644 FPGA_quartus_GE/Video/lpm_ff2.bsf
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 create mode 100644 FPGA_quartus_GE/Video/lpm_ff3.bsf
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 create mode 100644 FPGA_quartus_GE/Video/lpm_ff4.bsf
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 create mode 100644 FPGA_quartus_GE/Video/lpm_mux6.bsf
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diff --git a/FPGA_quartus_GE/DSP/DSP.vhd b/FPGA_quartus_GE/DSP/DSP.vhd
new file mode 100644
index 0000000..26f8e2e
--- /dev/null
+++ b/FPGA_quartus_GE/DSP/DSP.vhd
@@ -0,0 +1,79 @@
+-- WARNING: Do NOT edit the input and output ports in this file in a text
+-- editor if you plan to continue editing the block that represents it in
+-- the Block Editor! File corruption is VERY likely to occur.
+
+-- Copyright (C) 1991-2008 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+
+-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
+-- Created on Tue Sep 08 16:24:57 2009
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+
+--  Entity Declaration
+
+ENTITY DSP IS
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	PORT
+	(
+		CLK33M : IN STD_LOGIC;
+		MAIN_CLK : IN STD_LOGIC;
+		nFB_OE : IN STD_LOGIC;
+		nFB_WR : IN STD_LOGIC;
+		nFB_CS1 : IN STD_LOGIC;
+		nFB_CS2 : IN STD_LOGIC;
+		FB_SIZE0 : IN STD_LOGIC;
+		FB_SIZE1 : IN STD_LOGIC;
+		nFB_BURST : IN STD_LOGIC;
+		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
+		nRSTO : IN STD_LOGIC;
+		nFB_CS3 : IN STD_LOGIC;
+		nSRCS : INOUT STD_LOGIC;
+		nSRBLE : OUT STD_LOGIC;
+		nSRBHE : OUT STD_LOGIC;
+		nSRWE : OUT STD_LOGIC;
+		nSROE : OUT STD_LOGIC;
+		DSP_INT : OUT STD_LOGIC;
+		DSP_TA : OUT STD_LOGIC;
+		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
+		IO : INOUT STD_LOGIC_VECTOR(17 downto 0);
+		SRD : INOUT STD_LOGIC_VECTOR(15 downto 0)
+	);
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+	
+END DSP;
+
+
+--  Architecture Body
+
+ARCHITECTURE DSP_architecture OF DSP IS
+
+	
+BEGIN
+	nSRCS  <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1';	--nFB_CS3;
+	nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1';
+	nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; 
+	nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1';
+	nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1';
+	DSP_INT <= '0';
+	DSP_TA <= '0';
+	IO(17 downto 0) <= FB_ADR(18 downto 1);
+	SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
+	FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
+	
+	
+END DSP_architecture;
diff --git a/FPGA_quartus_GE/DSP/DSP.vhd.bak b/FPGA_quartus_GE/DSP/DSP.vhd.bak
new file mode 100644
index 0000000..2d4811a
--- /dev/null
+++ b/FPGA_quartus_GE/DSP/DSP.vhd.bak
@@ -0,0 +1,79 @@
+-- WARNING: Do NOT edit the input and output ports in this file in a text
+-- editor if you plan to continue editing the block that represents it in
+-- the Block Editor! File corruption is VERY likely to occur.
+
+-- Copyright (C) 1991-2008 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+
+-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
+-- Created on Tue Sep 08 16:24:57 2009
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+
+--  Entity Declaration
+
+ENTITY DSP IS
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	PORT
+	(
+		CLK33M : IN STD_LOGIC;
+		MAIN_CLK : IN STD_LOGIC;
+		nFB_OE : IN STD_LOGIC;
+		nFB_WR : IN STD_LOGIC;
+		nFB_CS1 : IN STD_LOGIC;
+		nFB_CS2 : IN STD_LOGIC;
+		FB_SIZE0 : IN STD_LOGIC;
+		FB_SIZE1 : IN STD_LOGIC;
+		nFB_BURST : IN STD_LOGIC;
+		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
+		nRSTO : IN STD_LOGIC;
+		nFB_CS3 : IN STD_LOGIC;
+		nSRCS : OUT STD_LOGIC;
+		nSRBLE : OUT STD_LOGIC;
+		nSRBHE : OUT STD_LOGIC;
+		nSRWE : OUT STD_LOGIC;
+		nSROE : OUT STD_LOGIC;
+		DSP_INT : OUT STD_LOGIC;
+		DSP_TA : OUT STD_LOGIC;
+		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
+		IO : INOUT STD_LOGIC_VECTOR(17 downto 0);
+		SRD : INOUT STD_LOGIC_VECTOR(15 downto 0)
+	);
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+	
+END DSP;
+
+
+--  Architecture Body
+
+ARCHITECTURE DSP_architecture OF DSP IS
+
+	
+BEGIN
+	nSRCS  <= '0' when nFB_CS2 = '0' and FB_ADR(27 downto 24) = x"4" else '1';	--nFB_CS3;
+	nSRBHE <= '0' when FB_ADR(0 downto 0) = "0" else '1';
+	nSRBLE <= '1' when FB_ADR(0 downto 0) = "0" and FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0'; 
+	nSRWE <= '0' when nFB_WR = '0' and nSRCS = '0' and MAIN_CLK = '0' else '1';
+	nSROE <= '0' when nFB_OE = '0' and nSRCS = '0' else '1';
+	DSP_INT <= '0';
+	DSP_TA <= '0';
+	IO(17 downto 0) <= FB_ADR(18 downto 1);
+	SRD(15 downto 0) <= FB_AD(31 downto 16) when nFB_WR = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
+	FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
+	
+	
+END DSP_architecture;
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diff --git a/FPGA_quartus_GE/DSP/src/adgen_stage.vhd b/FPGA_quartus_GE/DSP/src/adgen_stage.vhd
new file mode 100644
index 0000000..1ff7e59
--- /dev/null
+++ b/FPGA_quartus_GE/DSP/src/adgen_stage.vhd
@@ -0,0 +1,216 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity adgen_stage is port(
+	activate_adgen    : in  std_logic;
+	activate_x_mem    : in  std_logic;
+	activate_y_mem    : in  std_logic;
+	activate_l_mem    : in  std_logic;
+	instr_word        : in  std_logic_vector(23 downto 0);
+	instr_array       : in  instructions_type;
+	optional_ea_word  : in  std_logic_vector(23 downto 0);
+	register_file     : in  register_file_type;
+	adgen_mode_a      : in  adgen_mode_type;
+	adgen_mode_b      : in  adgen_mode_type;
+	address_out_x     : out unsigned(BW_ADDRESS-1 downto 0);
+	address_out_y     : out unsigned(BW_ADDRESS-1 downto 0);
+	wr_R_port_A_valid : out std_logic;
+	wr_R_port_A       : out addr_wr_port_type;
+	wr_R_port_B_valid : out std_logic;
+	wr_R_port_B       : out addr_wr_port_type
+);
+end entity;
+
+
+architecture rtl of adgen_stage is
+
+	signal address_out_x_int : unsigned(BW_ADDRESS-1 downto 0);
+
+
+begin
+
+	address_out_x <= address_out_x_int;
+
+	address_generator_X: process(activate_adgen, instr_word, register_file, adgen_mode_a) is
+		variable r_reg_local : unsigned(BW_ADDRESS-1 downto 0);
+		variable n_reg_local : unsigned(BW_ADDRESS-1 downto 0);
+		variable m_reg_local : unsigned(BW_ADDRESS-1 downto 0);
+		variable op1         : unsigned(BW_ADDRESS-1 downto 0);
+		variable op2         : unsigned(BW_ADDRESS-1 downto 0);
+		variable addr_mod    : unsigned(BW_ADDRESS-1 downto 0);
+		variable new_r_reg   : unsigned(BW_ADDRESS-1 downto 0);
+		variable new_r_reg_interm : unsigned(BW_ADDRESS-1 downto 0);
+		variable modulo_bitmask : std_logic_vector(BW_ADDRESS-1 downto 0);
+		variable bit_set     : std_logic;
+	begin
+		r_reg_local := register_file.addr_r(to_integer(unsigned(instr_word(10 downto 8))));
+		n_reg_local := register_file.addr_n(to_integer(unsigned(instr_word(10 downto 8))));
+		m_reg_local := register_file.addr_m(to_integer(unsigned(instr_word(10 downto 8))));
+
+		-- select the operands for the calculation
+		case adgen_mode_a is
+			-- (Rn) - Nn
+			when POST_MIN_N =>  addr_mod := unsigned(- signed(n_reg_local));
+			-- (Rn) + Nn
+			when POST_PLUS_N => addr_mod :=   n_reg_local;
+			-- (Rn)-
+			when POST_MIN_1 =>  addr_mod := (others => '1'); -- -1
+			-- (Rn)+
+			when POST_PLUS_1 => addr_mod := to_unsigned(1, BW_ADDRESS);
+			-- (Rn)
+			when NOP =>         addr_mod := (others => '0');
+			-- (Rn + Nn)
+			when INDEXED_N =>   addr_mod := n_reg_local;
+			-- -(Rn)
+			when PRE_MIN_1 =>   addr_mod := (others => '1'); -- - 1
+			-- absolute address (appended to instruction word)
+			when ABSOLUTE =>    addr_mod := (others => '0');
+			when IMMEDIATE =>   addr_mod := (others => '0');
+		end case;
+
+		op1 := r_reg_local;
+		op2 := addr_mod;
+		-- linear addressing
+		if m_reg_local = 2**BW_ADDRESS-1 then 
+			op1 := r_reg_local;
+			op2 := addr_mod;
+		-- bit reverse operation
+		elsif m_reg_local = 0 then
+			-- reverse the input to the adder bit wise
+			-- so we just need to use a single adder
+			for i in 0 to BW_ADDRESS-1 loop
+				op1(BW_ADDRESS - 1 - i) := r_reg_local(i);
+				op2(BW_ADDRESS - 1 - i) := addr_mod(i);
+			end loop;
+		-- modulo arithmetic
+		else
+			bit_set := '0';
+			for i in BW_ADDRESS-1 downto 0 loop
+				if m_reg_local(i) = '1' then
+					bit_set := '1';
+				end if;
+				if bit_set = '1' then
+					modulo_bitmask(i) := '0';
+				else
+					modulo_bitmask(i) := '1';
+				end if;
+			end loop;
+		end if;
+
+		new_r_reg_interm := op1 + op2;
+
+		new_r_reg := new_r_reg_interm;
+		-- linear addressing
+		if m_reg_local = 2**BW_ADDRESS-1 then 
+			new_r_reg := new_r_reg_interm;
+		-- bit reverse operation
+		elsif m_reg_local = 0 then
+			for i in 0 to BW_ADDRESS-1 loop
+				new_r_reg(BW_ADDRESS - 1 - i) := new_r_reg_interm(i);
+			end loop;
+		else
+
+		end if;
+
+		-- store the updated register in the global register file
+		-- do not store when we do nothing or there is nothing to update
+		-- LUA instructions DO NOT UPDATE the source register!!
+		if (adgen_mode_a = NOP or adgen_mode_a = ABSOLUTE or adgen_mode_a = IMMEDIATE or instr_array = INSTR_LUA) then
+			wr_R_port_A_valid <= '0';
+		else
+			wr_R_port_A_valid <= '1';
+		end if;
+		wr_R_port_A.reg_number <= unsigned(instr_word(10 downto 8));
+		wr_R_port_A.reg_value  <= new_r_reg;
+
+		-- select the output of the AGU
+		case adgen_mode_a is
+			-- (Rn) - Nn
+			when POST_MIN_N =>  address_out_x_int <= r_reg_local;
+			-- (Rn) + Nn
+			when POST_PLUS_N => address_out_x_int <= r_reg_local;
+			-- (Rn)-
+			when POST_MIN_1 =>  address_out_x_int <= r_reg_local;
+			-- (Rn)+
+			when POST_PLUS_1 => address_out_x_int <= r_reg_local;
+			-- (Rn)
+			when NOP =>         address_out_x_int <= r_reg_local;
+			-- (Rn + Nn)
+			when INDEXED_N =>   address_out_x_int <= new_r_reg;
+			-- -(Rn)
+			when PRE_MIN_1 =>   address_out_x_int <= new_r_reg;
+			-- absolute address (appended to instruction word)
+			when ABSOLUTE =>    address_out_x_int <= unsigned(optional_ea_word(BW_ADDRESS-1 downto 0));
+			when IMMEDIATE =>   address_out_x_int <= r_reg_local; -- Done externally, value never used
+		end case;
+		-- LUA instructions only use the updated address!
+		if instr_array = INSTR_LUA then
+			address_out_x_int <= new_r_reg;
+		end if;
+
+	end process address_generator_X;
+
+	address_generator_Y: process(activate_adgen, activate_x_mem, activate_y_mem, activate_l_mem, instr_word,
+	                             register_file, adgen_mode_b, address_out_x_int) is
+		variable r_reg_local : unsigned(BW_ADDRESS-1 downto 0);
+		variable n_reg_local : unsigned(BW_ADDRESS-1 downto 0);
+		variable m_reg_local : unsigned(BW_ADDRESS-1 downto 0);
+		variable op2         : unsigned(BW_ADDRESS-1 downto 0);
+		variable new_r_reg   : unsigned(BW_ADDRESS-1 downto 0);
+	begin
+		r_reg_local := register_file.addr_r(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13))));
+		n_reg_local := register_file.addr_n(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13))));
+		m_reg_local := register_file.addr_m(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13))));
+
+		-- select the operands for the calculation
+		case adgen_mode_b is
+			-- (Rn) + Nn
+			when POST_PLUS_N => op2 :=   n_reg_local;
+			-- (Rn)-
+			when POST_MIN_1  => op2 := (others => '1'); -- -1
+			-- (Rn)+
+			when POST_PLUS_1 => op2 := to_unsigned(1, BW_ADDRESS);
+			-- (Rn)
+			when others      => op2 := (others => '0');
+		end case;
+
+		new_r_reg := r_reg_local + op2;
+		-- TODO: USE modifier register!
+
+		-- store the updated register in the global register file
+		-- do not store when we do nothing or there is nothing to update
+		if adgen_mode_b = NOP then
+			wr_R_port_B_valid <= '0';
+		else
+			wr_R_port_B_valid <= '1';
+		end if;
+		wr_R_port_B.reg_number <= unsigned((not instr_word(10)) & instr_word(14 downto 13));
+		wr_R_port_B.reg_value  <= new_r_reg;
+
+		-- the address for the y memory is calculated in the first AGU if the x memory is not accessed!
+		-- so use the other output as address output for the y memory!
+		-- Furthermore, use the same address for L memory accesses (X and Y memory access the same address!)
+		if (activate_y_mem = '1' and activate_x_mem = '0') or activate_l_mem = '1' then
+			address_out_y <= address_out_x_int;
+		-- in any other case use the locally computed value
+		else
+			-- select the output of the AGU
+			case adgen_mode_b is
+				-- (Rn) + Nn
+				when POST_PLUS_N => address_out_y <= r_reg_local;
+				-- (Rn)-
+				when POST_MIN_1  => address_out_y <= r_reg_local;
+				-- (Rn)+
+				when POST_PLUS_1 => address_out_y <= r_reg_local;
+				-- (Rn)
+				when others      => address_out_y <= r_reg_local;
+			end case;
+		end if;
+	end process address_generator_Y;
+
+end architecture;
diff --git a/FPGA_quartus_GE/DSP/src/constants_pkg.vhd b/FPGA_quartus_GE/DSP/src/constants_pkg.vhd
new file mode 100644
index 0000000..4b8122d
--- /dev/null
+++ b/FPGA_quartus_GE/DSP/src/constants_pkg.vhd
@@ -0,0 +1,62 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+
+
+package constants_pkg is
+
+	-------------------------
+	-- Flags in CCR register
+	-------------------------
+	constant C_FLAG : natural := 0;
+	constant V_FLAG : natural := 1;
+	constant Z_FLAG : natural := 2;
+	constant N_FLAG : natural := 3;
+	constant U_FLAG : natural := 4;
+	constant E_FLAG : natural := 5;
+	constant L_FLAG : natural := 6;
+	constant S_FLAG : natural := 7;
+
+	-------------------
+	-- Pipeline stages
+	-------------------
+	constant ST_FETCH  : natural := 0;
+	constant ST_FETCH2 : natural := 1;
+	constant ST_DECODE : natural := 2;
+	constant ST_ADGEN  : natural := 3;
+	constant ST_EXEC   : natural := 4;
+
+	----------------------
+	-- Activation signals
+	----------------------
+	constant ACT_ADGEN       : natural := 0; -- Run the address generator
+	constant ACT_ALU         : natural := 1; -- Activation of ALU results in modification of the status register
+	constant ACT_EXEC_BRA    : natural := 2; -- Branch (in execute stage)
+	constant ACT_EXEC_CR_MOD : natural := 3; -- Control Register Modification (in execute stage)
+	constant ACT_EXEC_LOOP   : natural := 4; -- Loop instruction (REP, DO)
+	constant ACT_X_MEM_RD    : natural := 5; -- Init read from X memory
+	constant ACT_Y_MEM_RD    : natural := 6; -- Init read from Y memory
+	constant ACT_P_MEM_RD    : natural := 7; -- Init read from P memory
+	constant ACT_X_MEM_WR    : natural := 8; -- Init write to  X memory
+	constant ACT_Y_MEM_WR    : natural := 9; -- Init write to  Y memory
+	constant ACT_P_MEM_WR    : natural := 10; -- Init write to P memory
+	constant ACT_REG_RD      : natural := 11; -- Read from register (6 bit addressing)
+	constant ACT_REG_WR      : natural := 12; -- Write to register (6 bit addressing)
+	constant ACT_IMM_8BIT    : natural := 13; -- 8 bit  immediate operand (in instruction word)
+	constant ACT_IMM_12BIT   : natural := 14; -- 12 bit immediate operand (in instruction word)
+	constant ACT_IMM_LONG    : natural := 15; -- 24 bit immediate operant (in optional instruction word)
+	constant ACT_X_BUS_RD    : natural := 16; -- Read  data via X-bus (from x0,x1,a,b)
+	constant ACT_X_BUS_WR    : natural := 17; -- Write data via X-bus (to   x0,x1,a,b)
+	constant ACT_Y_BUS_RD    : natural := 18; -- Read  data via Y-bus (from y0,y1,a,b)
+	constant ACT_Y_BUS_WR    : natural := 19; -- Write data via Y-bus (to   y0,y1,a,b)
+	constant ACT_L_BUS_RD    : natural := 20; -- Read  data via L-bus (from a10, b10,x,y,a,b,ab,ba)
+	constant ACT_L_BUS_WR    : natural := 21; -- Write data via L-bus (to   a10, b10,x,y,a,b,ab,ba)
+	constant ACT_BIT_MOD_WR  : natural := 22; -- Bit modify write (to set for BSET, BCLR, BCHG)
+	constant ACT_REG_WR_CC   : natural := 23; -- Write to register file conditionally (Tcc)
+	constant ACT_ALU_WR_CC   : natural := 24; -- Write ALU result conditionally (Tcc)
+	constant ACT_NORM        : natural := 25; -- NORM instruction needs special handling
+
+end package constants_pkg;
diff --git a/FPGA_quartus_GE/DSP/src/decode_stage.vhd b/FPGA_quartus_GE/DSP/src/decode_stage.vhd
new file mode 100644
index 0000000..0c62149
--- /dev/null
+++ b/FPGA_quartus_GE/DSP/src/decode_stage.vhd
@@ -0,0 +1,1221 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity decode_stage is port(
+	activate_dec    : in  std_logic;
+	instr_word      : in  std_logic_vector(23 downto 0);
+	dble_word_instr : out std_logic;
+	instr_array     : out instructions_type;
+	act_array       : out std_logic_vector(NUM_ACT_SIGNALS-1 downto 0);
+	reg_wr_addr     : out std_logic_vector(5 downto 0);
+	reg_rd_addr     : out std_logic_vector(5 downto 0);
+	x_bus_rd_addr   : out std_logic_vector(1 downto 0); 
+	x_bus_wr_addr   : out std_logic_vector(1 downto 0); 
+	y_bus_rd_addr   : out std_logic_vector(1 downto 0); 
+	y_bus_wr_addr   : out std_logic_vector(1 downto 0); 
+	l_bus_addr      : out std_logic_vector(2 downto 0); 
+	adgen_mode_a    : out adgen_mode_type;
+	adgen_mode_b    : out adgen_mode_type;
+	alu_ctrl        : out alu_ctrl_type
+);
+end entity;
+
+
+architecture rtl of decode_stage is
+
+	signal instr_array_int : instructions_type;
+--	signal activate_pm_int : std_logic;
+	type adgen_bittype_type is (NOP, SINGLE_X, SINGLE_X_SHORT, DOUBLE_X_Y);
+	-- SINGLE_X       : MMMRRR
+	-- SINGLE_X_SHORT :  MMRRR
+	-- DOUBLE_X_Y     : mmrrMMRRR
+	signal adgen_bittype : adgen_bittype_type;
+
+	signal ea_extension_available : std_logic;
+
+	signal alu_tcc_decoded : std_logic;
+	signal alu_div_decoded : std_logic;
+	signal alu_norm_decoded : std_logic;
+
+begin
+
+
+	-- output the decoded instruction
+	instr_array <= instr_array_int;
+
+	-- calculate whether this is a double word instruction
+	dble_word_instr <= '1' when ea_extension_available = '1'  or 
+	                            instr_array_int = INSTR_DO    or 
+	                            instr_array_int = INSTR_JCLR  or
+	                            instr_array_int = INSTR_JSCLR or
+	                            instr_array_int = INSTR_JSET  or
+	                            instr_array_int = INSTR_JSSET else
+	                   '0';
+
+	alu_instruction_decoder: process(instr_word, activate_dec, alu_tcc_decoded,
+	                                 alu_div_decoded, alu_norm_decoded) is
+		variable instr_word_var : std_logic_vector(23 downto 0);
+	begin
+		if activate_dec = '1' then
+			instr_word_var := instr_word;
+		else
+			instr_word_var := (others => '0');
+		end if;
+		
+		alu_ctrl.mul_op1 <= (others => '0');
+		alu_ctrl.mul_op2 <= (others => '0');
+		alu_ctrl.rotate <= '0';
+		alu_ctrl.div_instr <= '0';
+		alu_ctrl.norm_instr <= '0';
+		alu_ctrl.shift_src <= '0';
+		alu_ctrl.shift_src_sign <= (others => '0');
+		alu_ctrl.shift_mode <= ZEROS;
+		alu_ctrl.add_src_stage_1 <= (others => '0');
+		alu_ctrl.add_src_stage_2 <= (others => '0');
+		alu_ctrl.add_src_sign    <= (others => '0');
+		alu_ctrl.logic_function  <= (others => '0');
+		alu_ctrl.word_24_update  <= '0';
+		alu_ctrl.rounding_used   <= (others => '0');
+		alu_ctrl.store_result    <= '0';
+		for i in 0 to 7 loop -- by default do not touch any of the ccr flags (L;E;U;N;Z;V;C)
+			alu_ctrl.ccr_flags_ctrl(i) <= DONT_TOUCH;
+		end loop;
+		alu_ctrl.dst_accu <= instr_word_var(3); -- default value for all alu operations
+
+		-- check wether instruction that allows parallel moves 
+		-- has to be decoded, then it is an ALU operation in the 8 LSBs
+		-- Only exceptions are DIV, NORM, and Tcc
+		if instr_word_var(23 downto 20) /= "0000" then
+			-- ABS
+			if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "110" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- source/dst are the same register 
+				alu_ctrl.shift_src_sign <= "10";  -- the sign of the operand depends on the operand 
+				                                  -- negative operand will negate the content of the accu as
+				                                  -- needed by the ABS instruction
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero
+				alu_ctrl.store_result <= '1';     -- store the result
+				-- set all flags but carry
+				for i in 1 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- ADC
+			if instr_word_var(7 downto 5) = "001" and instr_word_var(2 downto 0) = "001" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= "01" & instr_word_var(4); -- X or Y
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "10"; -- add carry to result of addition
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- ADD
+			if instr_word_var(7) = '0' and instr_word_var(2 downto 0) = "000" and instr_word_var(6 downto 4) /= "000" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- ADDL
+			if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "010" then
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_LEFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) (here: A,B)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- ADDR
+			if instr_word_var(7 downto 4) = "0000" and instr_word_var(2 downto 0) = "010" then
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_RIGHT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 5) & '1'; -- source register (JJJ encoding) (here: A,B)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- AND / OR / EOR
+			if instr_word_var(7 downto 6) = "01" and (instr_word_var(2 downto 0) = "110" or -- and
+			                                          instr_word_var(2 downto 0) = "010" or -- or
+				                                      instr_word_var(2 downto 0) = "011") then -- eor
+				alu_ctrl.logic_function <= instr_word_var(2 downto 0);  -- 000: none, 110: and, 010: or, 011: eor, 111: not
+				alu_ctrl.word_24_update <= '1';  -- only accumulator bits 47 downto 24 affected?
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) (here: A,B)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set following flags
+				alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR;
+			end if;
+			-- ASL
+			if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "010" then
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_LEFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- ASR
+			if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "010" then
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_RIGHT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set following flags
+--				alu_ctrl.ccr_flags_ctrl(S_FLAG) <= MODIFY;
+--				alu_ctrl.ccr_flags_ctrl(E_FLAG) <= MODIFY;
+--				alu_ctrl.ccr_flags_ctrl(U_FLAG) <= MODIFY;
+--				alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY;
+--				alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY;
+--				alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR;
+--				alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY;
+				-- set all flags, V-flag will be cleared due to shifting
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- CLR
+			if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "011" then
+				-- Read accu
+				alu_ctrl.shift_mode <= ZEROS;
+				-- Read S
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set following flags
+				alu_ctrl.ccr_flags_ctrl(S_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(E_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(U_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR;
+			end if;
+			-- CMP
+			if instr_word_var(7) = '0' and instr_word_var(6 downto 5) /= "01" and 
+			   instr_word_var(2 downto 0) = "101" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				if instr_word_var(6) = '1' then
+					alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) x0,x1,y0,y1
+				else
+					alu_ctrl.add_src_stage_1 <= "001"; -- select opposite accu (JJJ encoding)
+				end if;
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "01"; -- with negative sign
+				alu_ctrl.store_result    <= '0';  -- do not store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- CMPM
+			if instr_word_var(7) = '0' and instr_word_var(6 downto 5) /= "01" and 
+		       instr_word_var(2 downto 0) = "111" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "10";          -- with the sign dependant sign (magnitude!)
+				-- Read S
+				if instr_word_var(6) = '1' then
+					alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) x0,x1,y0,y1
+				else
+					alu_ctrl.add_src_stage_1 <= "001"; -- select opposite accu (JJJ encoding)
+				end if;
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "10"; -- with sign dependant sign (magnitude!)
+				alu_ctrl.store_result    <= '0';  -- do not store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- LSL
+			if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "011" then
+				alu_ctrl.word_24_update <= '1';
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_LEFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand
+				-- set N,Z,V,C flags
+				for i in 0 to 3 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- LSR
+			if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "011" then
+				alu_ctrl.word_24_update <= '1';
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_RIGHT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand
+				-- set N,Z,V,C flags
+				for i in 0 to 3 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- MPY, MPYR, MAC, MACR
+			if instr_word_var(7) = '1' then
+				case instr_word_var(6 downto 4) is
+					when "000"  => alu_ctrl.mul_op1 <= "00"; alu_ctrl.mul_op2 <= "00"; -- x0,x0
+					when "001"  => alu_ctrl.mul_op1 <= "10"; alu_ctrl.mul_op2 <= "10"; -- y0,y0
+					when "010"  => alu_ctrl.mul_op1 <= "01"; alu_ctrl.mul_op2 <= "00"; -- x1,x0
+					when "011"  => alu_ctrl.mul_op1 <= "11"; alu_ctrl.mul_op2 <= "10"; -- y1,y0
+					when "100"  => alu_ctrl.mul_op1 <= "00"; alu_ctrl.mul_op2 <= "11"; -- x0,y1
+					when "101"  => alu_ctrl.mul_op1 <= "10"; alu_ctrl.mul_op2 <= "00"; -- y0,x0
+					when "110"  => alu_ctrl.mul_op1 <= "01"; alu_ctrl.mul_op2 <= "10"; -- x1,y0
+					when others => alu_ctrl.mul_op1 <= "11"; alu_ctrl.mul_op2 <= "01"; -- y1,x1
+				end case;
+				alu_ctrl.store_result    <= '1';  -- store result in accu
+				alu_ctrl.add_src_stage_2 <= "10"; -- select mul out for adder!
+				alu_ctrl.add_src_sign    <= '0' & instr_word_var(2); -- select +/-
+				alu_ctrl.rounding_used   <= '0' & instr_word_var(0); -- rounding is determined by that bit!
+				if instr_word_var(1) = '0' then -- MPY(R)
+					alu_ctrl.shift_mode <= ZEROS;
+				else -- MAC(R)
+					alu_ctrl.shift_mode <= NO_SHIFT;
+					alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+					alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				end if;
+				-- set all flags but carry!
+				for i in 1 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- NEG
+			if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "110" then
+				-- Read accu
+				alu_ctrl.shift_mode <= ZEROS;
+--				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+--				alu_ctrl.shift_src_sign <= "01";          -- with negative sign
+				-- Read Accu
+				alu_ctrl.add_src_stage_1 <= "000"; -- source register equal to dst_register
+				alu_ctrl.add_src_stage_2 <= "01"; -- select register as operand
+				alu_ctrl.add_src_sign    <= "01"; -- with negative sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags but carry!
+				for i in 1 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- NOT
+			if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "111" then
+				alu_ctrl.word_24_update <= '1';
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				alu_ctrl.logic_function  <= instr_word_var(2 downto 0); -- select not operation
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set following flags
+				alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR;
+			end if;
+			-- RND
+			if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "001" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "01"; -- normal rounding needed
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand
+				-- set all flags but carry!
+				for i in 1 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- ROL
+			if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "111" then
+				alu_ctrl.word_24_update <= '1';
+				alu_ctrl.rotate <= '1';
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_LEFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand
+				-- set the following flags
+				alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR;
+				alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY;
+			end if;
+			-- ROR
+			if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "111" then
+				alu_ctrl.word_24_update <= '1';
+				alu_ctrl.rotate <= '1';
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_RIGHT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand
+				-- set the following flags
+				alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR;
+				alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY;
+			end if;
+			-- SBC
+			if instr_word_var(7 downto 5) = "001" and instr_word_var(2 downto 0) = "101" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) X,Y
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "01"; -- with negative sign
+				alu_ctrl.rounding_used   <= "11"; -- subtract carry
+				alu_ctrl.store_result    <= '1';  -- store the result
+				-- set all flags!
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- SUB
+			if instr_word_var(7) = '0' and instr_word_var(2 downto 0) = "100" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "01"; -- with negative sign
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.store_result    <= '1';  -- store the result
+				-- set all flags!
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- SUBL
+			if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "110" then
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_LEFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "01"; -- with negative sign
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.store_result    <= '1';  -- store the result
+				-- set all flags!
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- SUBR
+			if instr_word_var(7 downto 4) = "0000" and instr_word_var(2 downto 0) = "110" then
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_RIGHT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 5) & '1'; -- source register (JJJ encoding)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "01"; -- with negative sign
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.store_result    <= '1';  -- store the result
+				-- set all flags!
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- TFR 
+			if instr_word_var(7) = '0' and instr_word_var(6 downto 5) /= "01" and 
+			   instr_word_var(6 downto 4) /= "001" and instr_word_var(2 downto 0) = "001" then
+				-- do not read accu
+				alu_ctrl.shift_mode <= ZEROS;
+				-- Read S
+				if instr_word_var(6) = '1' then
+					alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding)
+				else
+					alu_ctrl.add_src_stage_1 <= "001"; -- B,A or A,B (depending on dest. accu)
+				end if;
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "00"; -- with positive sign
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.store_result    <= '1';  -- store the result
+				-- do not set any flag at all!
+			end if;
+			-- TST
+			if instr_word_var(7 downto 4) = "0000" and instr_word_var(2 downto 0) = "011" then
+				-- do not read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;          -- no shift
+				alu_ctrl.shift_src  <= instr_word_var(3); -- read source accu
+				alu_ctrl.shift_src_sign  <= "00";         -- sign unchanged
+				-- Read S
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero
+				alu_ctrl.add_src_sign    <= "00"; -- with positive sign
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.store_result    <= '0';  -- do not store the result
+				-- set all flags but carry!
+				for i in 1 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+		end if; -- Parallel move ALU instructions
+
+		-- Tcc
+		if alu_tcc_decoded = '1' then
+			-- Read source
+			if instr_word_var(6) = '1' then
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding)
+			else
+				alu_ctrl.add_src_stage_1 <= "001"; -- B,A or A,B (depending on dest. accu)
+			end if;
+			alu_ctrl.add_src_stage_2 <= "01"; -- select the registers as source
+			-- The .store_result flag is generated in the execute stage
+			-- depending on the condition codes
+			-- do not set any flag at all!
+		end if;
+--mul_op1 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1
+--mul_op2 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1
+--shift_src  : std_logic; -- a,b
+--shift_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved
+--shift_mode : alu_shift_mode;
+--add_src_stage_1  : std_logic_vector(2 downto 0); -- x0,x1,y0,y1,x,y,a,b
+--add_src_stage_2  : std_logic_vector(1 downto 0); -- 00: 0 , 01: add_src_1, 10: mul_result, 11: reserved
+--add_src_sign   : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: div instruction!
+--logic_function : std_logic_vector(2 downto 0);  -- 000: none, 110: and, 010: or, 011: eor, 111: not
+--word_24_update : std_logic;  -- only accumulator bits 47 downto 24 affected?
+--rounding_used  : std_logic_vector(1 downto 0); -- 00: no rounding, 01: rounding, 10: add carry, 11: subtract carry
+--store_result   : std_logic; -- 0: do not update accumulator, 1: update accumulator
+--dst_accu       : std_logic; -- 0: a, 1: b
+		-- DIV
+		if alu_div_decoded = '1' then
+			alu_ctrl.store_result    <= '1';          -- do store the result
+			-- shifter operation
+			alu_ctrl.shift_mode <= SHIFT_LEFT;        -- shift left
+			alu_ctrl.shift_src  <= instr_word_var(3); -- read source accu
+			alu_ctrl.div_instr  <= '1';               -- this is THE div instruction, special handling needed
+			-- source operand loading
+			alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding)
+			alu_ctrl.add_src_stage_2 <= "01"; -- select the registers as source
+			alu_ctrl.add_src_sign    <= "11"; -- div instruction, sign dependant on D[55] XOR S[23] 
+			                                  -- if 1: positive, if 0: negative
+			alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY;
+			alu_ctrl.ccr_flags_ctrl(V_FLAG) <= MODIFY;
+			alu_ctrl.ccr_flags_ctrl(L_FLAG) <= MODIFY;
+		end if;
+		-- NORM
+		if alu_norm_decoded = '1' then
+			-- set all alu-ctrl signals to ASL/ASR already here
+			-- depending on the condition code registers the flags
+			-- will be completed in the execute stage
+			alu_ctrl.norm_instr <= '1';
+			-- Read accu
+			--alu_ctrl.shift_mode <= SHIFT_RIGHT/SHIFT_LEFT/NO_SHIFT;
+			alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+			alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+			-- Read S
+			alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand
+			alu_ctrl.add_src_sign    <= "00"; -- with original sign
+			alu_ctrl.store_result    <= '1';  -- store the result
+			alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+			-- set all flags, V-flag will be cleared due to shifting
+			for i in 0 to 7 loop
+				alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+			end loop;
+
+		end if;
+	end process;
+
+
+	instruction_decoder: process(instr_word, activate_dec) is
+		variable instr_word_var : std_logic_vector(23 downto 0);
+		procedure activate_AGU is
+		begin
+			-- check for immediate long addressing
+			if instr_word_var(13 downto 8) = "110100" then
+				act_array(ACT_IMM_LONG) <= '1';
+				act_array(ACT_X_MEM_RD) <= '0'; -- No memory accesses for Immediate addressing!
+				act_array(ACT_Y_MEM_RD) <= '0';
+				act_array(ACT_X_MEM_WR) <= '0';
+				act_array(ACT_Y_MEM_WR) <= '0';
+			else
+				act_array(ACT_ADGEN) <= '1';
+			end if;
+		end procedure activate_AGU;
+	begin
+		instr_array_int <= INSTR_NOP;
+		act_array   <= (others => '0');
+		adgen_bittype <= NOP;
+		reg_rd_addr <= (others => '0');
+		reg_wr_addr <= (others => '0');
+		x_bus_rd_addr <= (others => '0');
+		x_bus_wr_addr <= (others => '0');
+		y_bus_rd_addr <= (others => '0');
+		y_bus_wr_addr <= (others => '0');
+		l_bus_addr <= instr_word_var(19) & instr_word_var(17 downto 16);
+
+		alu_tcc_decoded <= '0';
+		alu_div_decoded <= '0';
+		alu_norm_decoded <= '0';
+
+		-- in case the decoding is not activated we insert a nop
+		if activate_dec = '1' then
+			instr_word_var := instr_word;
+		else
+			instr_word_var := (others => '0');
+		end if;
+
+		if instr_word_var(23 downto 16) = X"00" then
+			case instr_word_var(15 downto 0) is
+				when X"0000" => instr_array_int <= INSTR_NOP;
+				when X"0004" => instr_array_int <= INSTR_RTI; act_array(ACT_EXEC_BRA) <= '1';
+				when X"0005" => instr_array_int <= INSTR_ILLEGAL;
+				when X"0006" => instr_array_int <= INSTR_SWI;
+				when X"000C" => instr_array_int <= INSTR_RTS; act_array(ACT_EXEC_BRA) <= '1';
+				when X"0084" => instr_array_int <= INSTR_RESET;
+				when X"0086" => instr_array_int <= INSTR_WAIT;
+				when X"0087" => instr_array_int <= INSTR_STOP;
+				when X"008C" => instr_array_int <= INSTR_ENDDO;
+				                act_array(ACT_EXEC_LOOP) <= '1';
+				when others =>
+					act_array(ACT_EXEC_CR_MOD) <= '1'; -- modify control register
+					if instr_word_var(7 downto 2) = "101110" then
+						instr_array_int <= INSTR_ANDI;
+					elsif instr_word_var(7 downto 2) = "111110" then
+						instr_array_int <= INSTR_ORI;
+					end if;
+			end case;
+		end if;
+		---------------------------------------------------------
+		-- DIV and NORM
+		---------------------------------------------------------
+		if instr_word_var(23 downto 16) = X"01" then
+			-- DIV
+			if instr_word_var(15 downto 6) = "1000000001" and instr_word_var(2 downto 0) = "000" then
+				alu_div_decoded <= '1';
+				act_array(ACT_ALU) <= '1'; -- force ALU to update status register
+			end if;
+			-- NORM
+			if instr_word_var(15 downto 11) = "11011" and instr_word_var(7 downto 4) = "0001" and
+		   	   instr_word_var(2 downto 0) = "101" then
+				alu_norm_decoded <= '1';
+				act_array(ACT_NORM) <= '1'; -- NORM instruction decoded, 
+				                            -- special handling in exec-stage is caused
+				act_array(ACT_REG_RD) <= '1';
+				reg_rd_addr <= instr_word_var(13 downto 12) & '0' & instr_word_var(10 downto 8); -- Write same Rn
+				act_array(ACT_REG_WR) <= '1';
+				reg_wr_addr <= instr_word_var(13 downto 12) & '0' & instr_word_var(10 downto 8); -- Write same Rn
+			end if;
+		end if;
+		---------------------------------------------------------
+		-- Tcc
+		---------------------------------------------------------
+		if instr_word_var(23 downto 16) = X"02" or instr_word_var(23 downto 16) = X"03" then
+			-- Tcc S1, D1  S2, D2 (ALU/Reg file)
+			if instr_word_var(16) = '0' and instr_word_var(11 downto 7) = "00000" and
+		       instr_word_var(2 downto 0) = "000" then
+				act_array(ACT_ALU_WR_CC) <= '1';
+				alu_tcc_decoded <= '1';
+			-- Tcc S1, D1  S2, D2 (ALU/Reg file)
+			elsif instr_word_var(16) = '1' and instr_word_var(11) = '0' and 
+		   	      instr_word_var(7) = '0' then
+				act_array(ACT_ALU_WR_CC) <= '1';
+				alu_tcc_decoded <= '1';
+				act_array(ACT_REG_WR_CC) <= '1';
+				reg_rd_addr <= "010" & instr_word_var(10 downto 8); -- Read Rn
+				reg_wr_addr <= "010" & instr_word_var( 2 downto 0); -- Write to other Rn
+			end if;
+		end if;
+		---------------------------------------------------------
+		-- MOVEC and LUA instruction with registers
+		---------------------------------------------------------
+		if instr_word_var(23 downto 16) = X"04" then
+			act_array(ACT_REG_WR) <= '1';
+			-- LUA instruction
+			if instr_word_var(15 downto 13) = "010" and instr_word_var(7 downto 4) = "0001" then
+				instr_array_int <= INSTR_LUA;
+				act_array(ACT_ADGEN) <= '1';
+				adgen_bittype <= SINGLE_X_SHORT;
+				reg_wr_addr <= instr_word_var(5 downto 0);
+			end if;
+			-- MOVEC instruction (S1, D2) or (S2, D1)
+			if instr_word_var(14) = '1' and instr_word_var(7 downto 5) = "101" then
+				instr_array_int <= INSTR_MOVEC;
+				act_array(ACT_REG_RD) <= '1';
+				-- Write D1
+				if instr_word_var(15) = '1' then
+					reg_wr_addr <= instr_word_var(5 downto 0);
+					reg_rd_addr <= instr_word_var(13 downto 8);
+				-- Read S1
+				else
+					reg_wr_addr <= instr_word_var(13 downto 8);
+					reg_rd_addr <= instr_word_var(5 downto 0);
+				end if;
+			end if;
+		end if;
+		-------------------------------------------------------------------------
+		-- MOVEC instruction with memory access/absolute address
+		-------------------------------------------------------------------------
+		if instr_word_var(23 downto 16) = X"05" and 
+		   instr_word_var(7) = '0' and instr_word_var(5) = '1' then
+			
+			instr_array_int <= INSTR_MOVEC;
+			-- read from memory, write to register
+			if instr_word_var(15) = '1' then
+				act_array(ACT_REG_WR) <= '1';
+				reg_wr_addr <= instr_word_var(5 downto 0);
+				-- X Memory read?
+				if instr_word_var(6) = '0' then
+					act_array(ACT_X_MEM_RD) <= '1';
+				-- Y Memory read?
+				else
+					act_array(ACT_Y_MEM_RD) <= '1';
+				end if;
+			-- write to memory, read register
+			else
+				act_array(ACT_REG_RD) <= '1';
+				reg_rd_addr <= instr_word_var(5 downto 0);
+				-- X Memory write?
+				if instr_word_var(6) = '0' then
+					act_array(ACT_X_MEM_WR) <= '1';
+				-- Y Memory write?
+				else
+					act_array(ACT_Y_MEM_WR) <= '1';
+				end if;
+			end if;
+			-- AGU needed?
+			if instr_word_var(14) = '1' then
+				-- detect whether two word instruction!
+				adgen_bittype <= SINGLE_X;
+				-- check for immediate long addressing
+				if instr_word_var(13 downto 8) = "110100" then
+					act_array(ACT_IMM_LONG) <= '1';
+					act_array(ACT_X_MEM_RD) <= '0'; -- No memory accesses for Immediate addressing!
+					act_array(ACT_Y_MEM_RD) <= '0';
+					act_array(ACT_X_MEM_WR) <= '0';
+					act_array(ACT_Y_MEM_WR) <= '0';
+				else
+					act_array(ACT_ADGEN) <= '1';
+				end if;
+			else
+				-- X:/Y:aa short is done in the adgen-stage automatically
+			end if;
+		end if;
+		-------------------------------------------------------------------------
+		-- MOVEC instruction with immediate
+		-------------------------------------------------------------------------
+		if instr_word_var(23 downto 16) = X"05" and instr_word_var(7 downto 5) = "101" then
+			instr_array_int <= INSTR_MOVEC;
+			act_array(ACT_IMM_8BIT) <= '1';
+			act_array(ACT_REG_WR) <= '1';
+			reg_wr_addr <= instr_word_var(5 downto 0);
+		end if;
+		---------------------------------
+		-- REP or DO loop?
+		---------------------------------
+		if instr_word_var(23 downto 16) = X"06" then
+			-- Instruction encoding is the same for both except of this bit
+			if instr_word_var(5) = '1' then
+				instr_array_int <= INSTR_REP;
+			else
+				instr_array_int <= INSTR_DO;
+			end if;
+			act_array(ACT_EXEC_LOOP) <= '1';
+			-- Init reading of loop counter from memory
+			if instr_word_var(15) = '0' and instr_word_var(7) = '0' then
+				-- X/Y: ea?
+				if instr_word_var(14) = '1' then
+					act_array(ACT_ADGEN) <= '1';
+				end if;
+				-- X/Y: aa?
+				-- Done automatically in the ADGEN stage by testing whether the ADGEN unit activated or not!
+				-- If not the absolute address stored in the instruction word is used.
+				-------
+				-- only a single memory access is required
+				adgen_bittype <= SINGLE_X;
+				-- X/Y as source?
+				if instr_word_var(6) = '0' then
+					act_array(ACT_X_MEM_RD) <= '1';
+				else 
+					act_array(ACT_Y_MEM_RD) <= '1';
+				end if;
+			elsif instr_word_var(15) = '1' and instr_word_var(7) = '0' then
+				-- S (register as source)
+				reg_rd_addr <= instr_word_var(13 downto 8);
+				act_array(ACT_REG_RD) <= '1';
+				-- #xxx ,12 bit immediate
+			elsif instr_word_var(7 downto 6) = "10" and instr_word_var(4) = '0' then
+				act_array(ACT_IMM_12BIT) <= '1';
+			end if;
+		end if;
+		--------------------------------
+		-- MOVEM (Program memory move)
+		--------------------------------
+		if instr_word_var(23 downto 16) = X"07" then
+			-- read memory, write reg
+			if instr_word_var(15) = '1' then
+				act_array(ACT_REG_WR) <= '1';
+				reg_wr_addr <= instr_word_var(5 downto 0);
+				act_array(ACT_P_MEM_RD) <= '1';
+			-- read reg, write memory
+			elsif instr_word_var(15) = '0' then
+				act_array(ACT_REG_RD) <= '1';
+				reg_rd_addr <= instr_word_var(5 downto 0);
+				act_array(ACT_P_MEM_WR) <= '1';
+			end if;
+			-- AGU needed?
+			if instr_word_var(14) = '1' and instr_word_var(7 downto 6) = "10" then
+				adgen_bittype <= SINGLE_X;
+				-- activate AGU and test whether immediate data is used
+				activate_AGU;
+			elsif instr_word_var(14) = '0' and instr_word_var(7 downto 6) = "00" then
+				-- X:/Y:aa short is done in the adgen-stage automatically
+			end if;
+		end if;
+		--------------------------------
+		-- MOVEP (Peripheral memory move)
+		--------------------------------
+		if instr_word_var(23 downto 16) = "0000100-" then
+			-- TODO?? Why parallel moves in software model??
+			case instr_word_var(15 downto 0) is
+--				when "-1------1-------" => instr_array_int(INSTR_MOVEP) <= '1';
+--				when "-1------01------" => instr_array_int(INSTR_MOVEP) <= '1';
+--				when "-1------00------" => instr_array_int(INSTR_MOVEP) <= '1';
+				when others =>
+			end case;
+		end if;
+		-- BSET, BCLR, BCHG, BTST, JCLR, JSET, JSCLR, JSSET, JMP, JCC, JSCC, JSR
+		if instr_word_var(23 downto 16) = X"0A" or instr_word_var(23 downto 16) = X"0B" then
+
+			reg_rd_addr <= instr_word_var(13 downto 8);
+			reg_wr_addr <= instr_word_var(13 downto 8);
+
+			if instr_word_var(16) = '0' then
+				if instr_word_var(7) = '0' and instr_word_var(5) = '0' then
+					instr_array_int <= INSTR_BCLR;
+				elsif instr_word_var(7) = '0' and instr_word_var(5) = '1' then
+					instr_array_int <= INSTR_BSET;
+				elsif instr_word_var(7) = '1' and instr_word_var(5) = '0' then
+					instr_array_int <= INSTR_JCLR;
+				elsif instr_word_var(7) = '1' and instr_word_var(5) = '1' then
+					instr_array_int <= INSTR_JSET;
+				end if;
+			elsif instr_word_var(16) = '1' then
+				if instr_word_var(7) = '0' and instr_word_var(5) = '0' then
+					instr_array_int <= INSTR_BCHG;
+				elsif instr_word_var(7) = '0' and instr_word_var(5) = '1' then
+					instr_array_int <= INSTR_BTST;
+				elsif instr_word_var(7) = '1' and instr_word_var(5) = '0' then
+					instr_array_int <= INSTR_JSCLR;
+				elsif instr_word_var(7) = '1' and instr_word_var(5) = '1' then
+					instr_array_int <= INSTR_JSSET;
+				end if;
+			end if;
+			if instr_word_var(7) = '1' then
+				act_array(ACT_EXEC_BRA) <= '1';
+			end if;
+
+			-- memory access?
+			if instr_word_var(15) = '0' then
+				-- X:
+				if instr_word_var(6) = '0' then
+					act_array(ACT_X_MEM_RD) <= '1';
+					-- if not a jump instruction and not BTST write back the result
+					if instr_word_var(7) = '0' and not(instr_word_var(16) = '1' and instr_word_var(5) = '1') then
+						act_array(ACT_X_MEM_WR) <= '1';
+					end if;
+				-- Y:
+				else
+					act_array(ACT_Y_MEM_RD) <= '1';
+					-- if not a jump instruction and not BTST write back the result
+					if instr_word_var(7) = '0' and not(instr_word_var(16) = '1' and instr_word_var(5) = '1') then
+						act_array(ACT_Y_MEM_WR) <= '1';
+					end if;
+				end if;
+			end if;
+
+			case instr_word_var(15 downto 14) is
+				-- X:/Y: aa
+				when "00" =>
+
+				-- X:/Y: ea
+				when "01" =>
+					act_array(ACT_ADGEN) <= '1';
+					adgen_bittype <= SINGLE_X;
+
+				-- X:/Y: pp 
+				-- TODO!
+				when "10" =>
+
+				when others => -- "11"
+					if instr_word_var(7 downto 0) = "10000000" then
+						-- JMP/JSR ea
+						act_array(ACT_EXEC_BRA) <= '1';
+						act_array(ACT_ADGEN) <= '1';
+						adgen_bittype <= SINGLE_X;
+						if instr_word_var(16) = '0' then
+							instr_array_int <= INSTR_JMP;
+						elsif instr_word_var(16) = '1' then
+							instr_array_int <= INSTR_JSR;
+						end if;
+					elsif instr_word_var(7 downto 4) = "1010" then
+						-- JCC/JSCC ea
+						act_array(ACT_EXEC_BRA) <= '1';
+						act_array(ACT_ADGEN) <= '1';
+						adgen_bittype <= SINGLE_X;
+						if instr_word_var(16) = '0' then
+							instr_array_int <= INSTR_JCC;
+						elsif instr_word_var(16) = '1' then
+							instr_array_int <= INSTR_JSCC;
+						end if;
+					-- JSCLR,JSET,JCLR,JSSET,BTST,BCLR,BSET,BCHG S/D
+					else
+						act_array(ACT_REG_RD) <= '1';
+						-- if not a jump instruction and not BTST write back the result
+						if instr_word_var(7) = '0' and not(instr_word_var(16) = '1' and instr_word_var(5) = '1') then
+							act_array(ACT_REG_WR) <= '1';
+						end if;
+					end if;
+			end case;
+		end if;
+		-- JMP xxx (absoulute short)
+		if instr_word_var(23 downto 16) = X"0C" then
+			if instr_word_var(15 downto 12) = "0000" then
+				instr_array_int <= INSTR_JMP;
+				act_array(ACT_EXEC_BRA) <= '1';
+			end if;
+		end if;
+		-- JSR xxx (absolute short)
+		if instr_word_var(23 downto 16) = X"0D" then
+			if instr_word_var(15 downto 12) = "0000" then
+				instr_array_int <= INSTR_JSR;
+				act_array(ACT_EXEC_BRA) <= '1';
+			end if;
+		end if;
+		-- JCC xxx (absolute short)
+		if instr_word_var(23 downto 16) = X"0E" then
+			instr_array_int <= INSTR_JCC;
+			act_array(ACT_EXEC_BRA) <= '1';
+		end if;
+		-- JSCC xxx (absolute short)
+		if instr_word_var(23 downto 16) = X"0F" then
+			instr_array_int <= INSTR_JSCC;
+			act_array(ACT_EXEC_BRA) <= '1';
+		end if;
+
+		------------------------------------------------
+		-- PARALLEL MOVE SECTION!!
+		------------------------------------------------
+		-- Here are the ALU operations that allow for parallel moves
+		if instr_word_var(23 downto 20) /= "0000" then
+			act_array(ACT_ALU) <= '1'; -- force ALU to update status register
+		end if;
+		-- PM: I
+		if instr_word_var(23 downto 21) = "001" and instr_word_var(20 downto 18) /= "000" then
+			act_array(ACT_IMM_8BIT) <= '1';
+			act_array(ACT_REG_WR) <= '1';
+			reg_wr_addr <= '0' & instr_word_var(20 downto 16);
+		end if;
+		-- PM: R
+		if instr_word_var(23 downto 18) = "001000" then
+			act_array(ACT_REG_WR) <= '1';
+			reg_wr_addr <= '0' & instr_word_var(12 downto  8);
+			act_array(ACT_REG_RD) <= '1';
+			reg_rd_addr <= '0' & instr_word_var(17 downto 13);
+		end if;
+		-- PM: U
+		if instr_word_var(23 downto 13) = "00100000010" then
+			act_array(ACT_ADGEN) <= '1';
+			adgen_bittype <= SINGLE_X_SHORT;
+		end if;
+		-- PM: X or PM:Y
+		if instr_word_var(23 downto 22) = "01" and 
+		   -- Check whether L: type parallel move. If so do not enter this branch!
+		   not (instr_word_var(21 downto 20) = "00" and instr_word_var(18) = '0') then
+			-- read memory, write reg
+			if instr_word_var(15) = '1' then
+				act_array(ACT_REG_WR) <= '1';
+				reg_wr_addr <= '0' & instr_word_var(21 downto 20) & instr_word_var(18 downto 16); -- TODO: CHECK!!
+				-- X Memory read?
+				if instr_word_var(19) = '0' then
+					act_array(ACT_X_MEM_RD) <= '1';
+				-- Y Memory read?
+				else
+					act_array(ACT_Y_MEM_RD) <= '1';
+				end if;
+			-- read reg, write memory
+			elsif instr_word_var(15) = '0' then
+				act_array(ACT_REG_RD) <= '1';
+				reg_rd_addr <= '0' & instr_word_var(21 downto 20) & instr_word_var(18 downto 16); -- TODO: CHECK!!
+				-- X Memory write?
+				if instr_word_var(19) = '0' then
+					act_array(ACT_X_MEM_WR) <= '1';
+				-- Y Memory write?
+				else
+					act_array(ACT_Y_MEM_WR) <= '1';
+				end if;
+			end if;
+			-- AGU needed?
+			if instr_word_var(14) = '1' then
+				-- detect whether two word instruction!
+				adgen_bittype <= SINGLE_X;
+				-- activate AGU and test whether immediate data is used
+				activate_AGU;
+			else
+				-- X:/Y:aa short is done in the adgen-stage automatically
+			end if;
+		end if;
+		-- PM: X:R or R:Y (Class I)
+		if instr_word_var(23 downto 20) = "0001" then
+			adgen_bittype <= SINGLE_X;
+			-- X:R
+			if instr_word_var(14) = '0' then
+				x_bus_rd_addr <= instr_word_var(19 downto 18);
+				x_bus_wr_addr <= instr_word_var(19 downto 18);
+				y_bus_rd_addr <= '1' & instr_word_var(17);
+				y_bus_wr_addr <= '0' & instr_word_var(16); -- TODO: Check encoding, manual uses three fs!
+				-- S2,D2 in any case!
+				act_array(ACT_Y_BUS_RD) <= '1';
+				act_array(ACT_Y_BUS_WR) <= '1';
+				-- Write D1?
+				if instr_word_var(15) = '1' then
+					act_array(ACT_X_MEM_RD) <= '1';
+					act_array(ACT_X_BUS_WR) <= '1';
+				else
+				-- Read S1?
+					act_array(ACT_X_MEM_WR) <= '1';
+					act_array(ACT_X_BUS_RD) <= '1';
+				end if;
+			-- R:Y
+			elsif instr_word_var(14) = '1' then
+				x_bus_rd_addr <= '1' & instr_word_var(19);
+				x_bus_wr_addr <= '0' & instr_word_var(18);
+				y_bus_rd_addr <= instr_word_var(17 downto 16);
+				y_bus_wr_addr <= instr_word_var(17 downto 16);
+				-- S1,D1 in any case!
+				act_array(ACT_X_BUS_RD) <= '1';
+				act_array(ACT_X_BUS_WR) <= '1';
+				-- Write D1?
+				if instr_word_var(15) = '1' then
+					act_array(ACT_Y_MEM_RD) <= '1';
+					act_array(ACT_Y_BUS_WR) <= '1';
+				else
+				-- Read S1?
+					act_array(ACT_Y_MEM_WR) <= '1';
+					act_array(ACT_Y_BUS_RD) <= '1';
+				end if;
+
+			end if;
+			-- detect whether two word instruction!
+			adgen_bittype <= SINGLE_X;
+			-- activate AGU and test whether immediate data is used
+			activate_AGU;
+		end if;
+		-- PM: X:R or R:Y (Class II)
+		if instr_word_var(23 downto 17) = "0000100" and instr_word_var(14) = '0' then
+			act_array(ACT_REG_RD) <= '1';
+			-- X:R
+			if instr_word_var(15) = '0' then
+				reg_rd_addr <= "00111" & instr_word_var(16); -- read A or B
+				act_array(ACT_X_MEM_WR) <= '1'; -- and store it in X memory
+				x_bus_rd_addr <= "00"; -- read x0
+				x_bus_wr_addr <= '1' & instr_word_var(16); -- and write to A or B
+				act_array(ACT_X_BUS_RD) <= '1';
+				act_array(ACT_X_BUS_WR) <= '1';
+			-- R:Y
+			elsif instr_word_var(15) = '1' then
+				reg_rd_addr <= "00111" & instr_word_var(16); -- read A or B
+				act_array(ACT_Y_MEM_WR) <= '1'; -- and store it in Y memory
+				y_bus_rd_addr <= "00"; -- read y0
+				y_bus_wr_addr <= '1' & instr_word_var(16); -- and write to A or B
+				act_array(ACT_Y_BUS_RD) <= '1';
+				act_array(ACT_Y_BUS_WR) <= '1';
+			end if;
+			-- detect whether two word instruction!
+			adgen_bittype <= SINGLE_X;
+			-- activate AGU and test whether immediate data is used
+			activate_AGU;
+		end if;
+		-- PM: L:
+		l_bus_addr <= instr_word_var(19) & instr_word_var(17 downto 16);
+		if instr_word_var(23 downto 20) = "0100" and instr_word_var(18) = '0' then
+			-- Read S?
+			if instr_word_var(15) = '0' then
+				act_array(ACT_L_BUS_RD) <= '1';
+				act_array(ACT_X_MEM_WR) <= '1';
+				act_array(ACT_Y_MEM_WR) <= '1';
+			else -- Write D
+				act_array(ACT_L_BUS_WR) <= '1';
+				act_array(ACT_X_MEM_RD) <= '1';
+				act_array(ACT_Y_MEM_RD) <= '1';
+			end if;
+			if instr_word_var(14) = '1' then
+				adgen_bittype <= SINGLE_X;
+				activate_AGU;
+			else
+				-- L:aa automatically performed in ADGEN stage
+			end if;
+		end if;
+		-- PM: X: Y:
+		if instr_word_var(23) = '1' then
+			adgen_bittype <= DOUBLE_X_Y;
+			-- No immediate value allowed, so activate in any case!
+			act_array(ACT_ADGEN) <= '1';
+			-- S1, X:
+			if instr_word_var(15) = '0' then
+				act_array(ACT_X_BUS_RD) <= '1';
+				x_bus_rd_addr <= instr_word_var(19 downto 18);
+				act_array(ACT_X_MEM_WR) <= '1'; 
+			-- X:, D1
+			else
+				act_array(ACT_X_BUS_WR) <= '1';
+				x_bus_wr_addr <= instr_word_var(19 downto 18);
+				act_array(ACT_X_MEM_RD) <= '1'; 
+			end if;
+			-- S2, Y:
+			if instr_word_var(22) = '0' then
+				act_array(ACT_Y_BUS_RD) <= '1';
+				y_bus_rd_addr <= instr_word_var(17 downto 16);
+				act_array(ACT_Y_MEM_WR) <= '1'; 
+			-- Y:, D2
+			else
+				act_array(ACT_Y_BUS_WR) <= '1';
+				y_bus_wr_addr <= instr_word_var(17 downto 16);
+				act_array(ACT_Y_MEM_RD) <= '1'; 
+			end if;
+		end if;
+	end process;
+
+	adgen_decoder: process(adgen_bittype, instr_word) is
+	begin
+		adgen_mode_a <= NOP;
+		adgen_mode_b <= NOP;
+		ea_extension_available <= '0';
+
+		case adgen_bittype is
+			when SINGLE_X =>
+				case instr_word(13 downto 11) is
+					when "000" => adgen_mode_a <= POST_MIN_N;
+					when "001" => adgen_mode_a <= POST_PLUS_N;
+					when "010" => adgen_mode_a <= POST_MIN_1;
+					when "011" => adgen_mode_a <= POST_PLUS_1;
+					when "100" => adgen_mode_a <= NOP;
+					when "101" => adgen_mode_a <= INDEXED_N;
+					when "111" => adgen_mode_a <= PRE_MIN_1;
+					when "110" => 
+						if instr_word(10 downto 8) = "000" then
+							adgen_mode_a <= ABSOLUTE;
+							ea_extension_available <= '1';
+						elsif instr_word(10 downto 8) = "100" then
+							adgen_mode_a <= IMMEDIATE;
+							ea_extension_available <= '1';
+						else 
+							adgen_mode_a <= NOP; -- INVALID OPCODE!
+						end if;
+					when others =>
+				end case;
+			when SINGLE_X_SHORT =>
+				case instr_word(12 downto 11) is
+					when "00" => adgen_mode_a <= POST_MIN_N;
+					when "01" => adgen_mode_a <= POST_PLUS_N;
+					when "10" => adgen_mode_a <= POST_MIN_1;
+					when "11" => adgen_mode_a <= POST_PLUS_1;
+					when others => 
+				end case;
+			when DOUBLE_X_Y =>
+				case instr_word(12 downto 11) is
+					when "00" => adgen_mode_a <= NOP;
+					when "01" => adgen_mode_a <= POST_PLUS_N;
+					when "10" => adgen_mode_a <= POST_MIN_1;
+					when "11" => adgen_mode_a <= POST_PLUS_1;
+					when others =>
+				end case;
+				case instr_word(21 downto 20) is
+					when "00" => adgen_mode_b <= NOP;
+					when "01" => adgen_mode_b <= POST_PLUS_N;
+					when "10" => adgen_mode_b <= POST_MIN_1;
+					when "11" => adgen_mode_b <= POST_PLUS_1;
+					when others =>
+				end case;
+			when others =>
+		end case;
+	end process adgen_decoder;
+
+end architecture rtl;
+
diff --git a/FPGA_quartus_GE/DSP/src/exec_stage_alu.vhd b/FPGA_quartus_GE/DSP/src/exec_stage_alu.vhd
new file mode 100644
index 0000000..9f3c3b9
--- /dev/null
+++ b/FPGA_quartus_GE/DSP/src/exec_stage_alu.vhd
@@ -0,0 +1,603 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity exec_stage_alu is port(
+	alu_activate      : in  std_logic;
+	instr_word        : in  std_logic_vector(23 downto 0);
+	alu_ctrl          : in  alu_ctrl_type;
+	register_file     : in  register_file_type;
+	addr_r_in         : in  unsigned(BW_ADDRESS-1 downto 0);
+	addr_r_out        : out unsigned(BW_ADDRESS-1 downto 0);
+	modify_accu       : out std_logic;
+	dst_accu          : out std_logic;
+	modified_accu     : out signed(55 downto 0);
+	modify_sr         : out std_logic;
+	modified_sr       : out std_logic_vector(15 downto 0)
+);
+end entity;
+
+architecture rtl of exec_stage_alu is 
+
+	signal alu_shifter_out          : signed(55 downto 0);
+	signal alu_shifter_carry_out    : std_logic;
+	signal alu_shifter_overflow_out : std_logic;
+
+	signal alu_logic_conj        : signed(55 downto 0);
+	signal alu_multiplier_out    : signed(55 downto 0);
+	signal alu_src_op            : signed(55 downto 0);
+	signal alu_add_result        : signed(56 downto 0);
+	signal alu_add_carry_out     : std_logic;
+	signal alu_post_adder_result : signed(56 downto 0);
+
+	signal scaling_mode          : std_logic_vector(1 downto 0);
+
+	signal modified_accu_int     : signed(55 downto 0);
+
+	signal norm_instr_asl  : std_logic;
+	signal norm_instr_asr  : std_logic;
+	signal norm_instr_nop  : std_logic;
+	signal norm_update_ccr : std_logic; 
+
+begin
+
+
+	-- store calculated value?
+	modify_accu <= alu_ctrl.store_result;
+	modified_accu <= modified_accu_int;
+	-- for the norm instruction we first need to determine whether we have to
+	-- update the CCR register or not
+	modify_sr <= alu_activate when alu_ctrl.norm_instr = '0' else
+	             norm_update_ccr;
+	dst_accu <= alu_ctrl.dst_accu;
+
+	scaling_mode <= register_file.sr(11 downto 10);
+
+
+	calcule_ccr_flags: process(register_file, alu_ctrl, alu_shifter_carry_out,
+	                           alu_post_adder_result, modified_accu_int, alu_add_carry_out) is
+	begin
+		-- by default do not modify the flags in the status register
+		modified_sr <= register_file.sr;
+		
+		-- Carry flag generation
+		-------------------------
+		case alu_ctrl.ccr_flags_ctrl(C_FLAG) is
+			when CLEAR  => modified_sr(C_FLAG) <= '0';
+			when SET    => modified_sr(C_FLAG) <= '1';
+			when MODIFY =>
+				-- the carry flag can stem from the shifter or from the post adder
+				-- in case we shift and add only a zero to the shift result (ASL, ASR, LSL, LSR, ROL, ROR)
+				-- take the carry flag from the shifter, else from the post adder
+				if (alu_ctrl.shift_mode = SHIFT_LEFT or alu_ctrl.shift_mode = SHIFT_RIGHT) and
+				    alu_ctrl.add_src_stage_2 = "00" then -- add zero after shifting?
+					modified_sr(C_FLAG) <= alu_shifter_carry_out;
+				elsif alu_ctrl.div_instr = '1' then
+					modified_sr(C_FLAG) <= not std_logic(alu_post_adder_result(55));
+				else
+--					modified_sr(C_FLAG) <= std_logic(alu_post_adder_result(57));
+					modified_sr(C_FLAG) <= alu_add_carry_out;
+				end if;
+			when others => -- Don't touch
+		end case;
+
+		-- Overflow flag generation
+		----------------------------
+		case alu_ctrl.ccr_flags_ctrl(V_FLAG) is
+			when CLEAR  => modified_sr(V_FLAG) <= '0';
+			when SET    => modified_sr(V_FLAG) <= '1';
+			when MODIFY =>
+				-- There are two sources for the overflow flag:
+				-- 1)
+				-- in case the result cannot be represented using 56 bits set
+				-- the overflow flag. this is the case when the two MSBs of 
+				-- the 57 bit result are different
+				-- 2)
+				-- The shifter circuit performs a 56 bit left shift. In case the 
+				-- two MSBs of the operand are different set the overflow flag as well
+				if (alu_ctrl.div_instr = '0' and alu_post_adder_result(56) /= alu_post_adder_result(55)) or
+			   	   (alu_ctrl.shift_mode = SHIFT_LEFT and alu_ctrl.word_24_update = '0' and 
+				    alu_shifter_overflow_out = '1' ) then
+					modified_sr(V_FLAG) <= '1';
+				else
+					modified_sr(V_FLAG) <= '0';
+				end if;
+			when others => -- Don't touch
+		end case;
+		
+		-- Zero flag generation
+		----------------------------
+		case alu_ctrl.ccr_flags_ctrl(Z_FLAG) is
+			when CLEAR  => modified_sr(Z_FLAG) <= '0';
+			when SET    => modified_sr(Z_FLAG) <= '1';
+			when MODIFY =>
+				-- in case the result is zero set this flag
+				-- distinguish between 24 bit and 56 bit ALU operations
+				-- 24 bit instructions are LSL, LSR, ROR, ROL, OR, EOR, NOT, AND
+				if (alu_ctrl.word_24_update = '1' and modified_accu_int(47 downto 24) = 0) or
+				   (alu_ctrl.word_24_update = '0' and modified_accu_int(55 downto  0) = 0) then
+					modified_sr(Z_FLAG) <= '1';
+				else
+					modified_sr(Z_FLAG) <= '0';
+				end if;
+			when others => -- Don't touch
+		end case;
+
+		-- Negative flag generation
+		----------------------------
+		case alu_ctrl.ccr_flags_ctrl(N_FLAG) is
+			when CLEAR  => modified_sr(N_FLAG) <= '0';
+			when SET    => modified_sr(N_FLAG) <= '1';
+			when MODIFY =>
+				-- in case the result is negative set this flag
+				-- distinguish between 24 bit and 56 bit ALU operations
+				-- 24 bit instructions are LSL, LSR, ROR, ROL, OR, EOR, NOT, AND
+				if alu_ctrl.word_24_update = '1' then
+					modified_sr(N_FLAG) <= std_logic(modified_accu_int(47));
+				else
+					modified_sr(N_FLAG) <= std_logic(modified_accu_int(55));
+				end if;
+			when others => -- Don't touch
+		end case;
+
+		-- Unnormalized flag generation
+		----------------------------
+		case alu_ctrl.ccr_flags_ctrl(U_FLAG) is
+			when CLEAR  => modified_sr(U_FLAG) <= '0';
+			when SET    => modified_sr(U_FLAG) <= '1';
+			when MODIFY =>
+				-- Set unnormalized bit according to the scaling mode
+				if (scaling_mode = "00" and alu_post_adder_result(47) = alu_post_adder_result(46)) or
+				   (scaling_mode = "01" and alu_post_adder_result(48) = alu_post_adder_result(47)) or
+				   (scaling_mode = "10" and alu_post_adder_result(46) = alu_post_adder_result(45)) then
+					modified_sr(U_FLAG) <= '1';
+				else
+					modified_sr(U_FLAG) <= '0';
+				end if;
+			when others => -- Don't touch
+		end case;
+
+		-- Extension flag generation
+		----------------------------
+		case alu_ctrl.ccr_flags_ctrl(E_FLAG) is
+			when CLEAR  => modified_sr(E_FLAG) <= '0';
+			when SET    => modified_sr(E_FLAG) <= '1';
+			when MODIFY =>
+				-- Set extension flag by default
+				modified_sr(E_FLAG) <= '1';
+				-- Clear extension flag according to the scaling mode
+				case scaling_mode is
+					when "00" =>
+						if alu_post_adder_result(55 downto 47) = "111111111" or alu_post_adder_result(55 downto 47) = "000000000" then
+							modified_sr(E_FLAG) <= '0';
+						end if;
+					when "01" =>
+						if alu_post_adder_result(55 downto 48) = "11111111" or alu_post_adder_result(55 downto 48) = "00000000" then
+							modified_sr(E_FLAG) <= '0';
+						end if;
+					when "10" =>
+						if alu_post_adder_result(55 downto 46) = "1111111111" or alu_post_adder_result(55 downto 46) = "0000000000" then
+							modified_sr(E_FLAG) <= '0';
+						end if;
+					when others =>
+						modified_sr(E_FLAG) <= '0';
+				end case;
+			when others => -- Don't touch
+		end case;
+
+		-- Limit flag generation (equals overflow flag generaton!)
+		-- Clearing of the Limit flag has to be done by the user!
+		-----------------------------------------------------------
+		case alu_ctrl.ccr_flags_ctrl(L_FLAG) is
+			when CLEAR  => modified_sr(L_FLAG) <= '0';
+			when SET    => modified_sr(L_FLAG) <= '1';
+			when MODIFY =>
+				-- There are two sources for the overflow flag:
+				-- 1)
+				-- in case the result cannot be represented using 56 bits set
+				-- the overflow flag. this is the case when the two MSBs of 
+				-- the 57 bit result are different
+				-- 2)
+				-- The shifter circuit performs a 56 bit left shift. In case the 
+				-- two MSBs of the operand are different set the overflow flag as well
+				if (alu_ctrl.div_instr = '0' and alu_post_adder_result(56) /= alu_post_adder_result(55)) or
+			   	   (alu_ctrl.shift_mode = SHIFT_LEFT and alu_ctrl.word_24_update = '0' and 
+				    alu_shifter_overflow_out = '1' ) then
+					modified_sr(L_FLAG) <= '1';
+				end if;
+			when others => -- Don't touch
+		end case;
+
+		-- Scaling flag generation (DSP56002 and up)
+		--------------------------------------------
+		-- Scaling flag is not generated in the ALU, but when A or B are read to the XDB or YDB
+
+	end process;
+
+
+	src_operand_select: process(register_file, alu_ctrl) is
+	begin
+		-- decoding according similar to JJJ representation
+		case alu_ctrl.add_src_stage_1 is 
+			when "000" =>
+				-- select depending on destination accu
+				if alu_ctrl.dst_accu = '0' then
+					alu_src_op <= register_file.a;
+				else
+					alu_src_op <= register_file.b;
+				end if;
+			when "001" => -- A,B or B,A
+				-- select depending on destination accu
+				if alu_ctrl.dst_accu = '0' then
+					alu_src_op <= register_file.b;
+				else
+					alu_src_op <= register_file.a;
+				end if;
+			when "010" =>  -- X
+				alu_src_op(55 downto 48) <= (others => register_file.x1(23));
+				alu_src_op(47 downto  0) <= register_file.x1 & register_file.x0;
+			when "011" =>  -- Y
+				alu_src_op(55 downto 48) <= (others => register_file.y1(23));
+				alu_src_op(47 downto  0) <= register_file.y1 & register_file.y0;
+			when "100" =>  -- x0
+				alu_src_op(55 downto 48) <= (others => register_file.x0(23));
+				alu_src_op(47 downto 24) <= register_file.x0;
+				alu_src_op(23 downto  0) <= (others => '0');
+			when "101" =>  -- y0
+				alu_src_op(55 downto 48) <= (others => register_file.y0(23));
+				alu_src_op(47 downto 24) <= register_file.y0;
+				alu_src_op(23 downto  0) <= (others => '0');
+			when "110" =>  -- x1
+				alu_src_op(55 downto 48) <= (others => register_file.x1(23));
+				alu_src_op(47 downto 24) <= register_file.x1;
+				alu_src_op(23 downto  0) <= (others => '0');
+			when "111" =>  -- y1
+				alu_src_op(55 downto 48) <= (others => register_file.y1(23));
+				alu_src_op(47 downto 24) <= register_file.y1;
+				alu_src_op(23 downto  0) <= (others => '0');
+			when others =>
+		end case;
+	end process;
+
+	alu_logical_functions: process(alu_ctrl, alu_src_op, alu_shifter_out) is
+	begin
+		alu_logic_conj <= alu_shifter_out;
+		case alu_ctrl.logic_function is
+			when "110" =>
+				alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) and alu_src_op(47 downto 24);
+			when "010" =>
+				alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) or  alu_src_op(47 downto 24);
+			when "011" =>
+				alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) xor alu_src_op(47 downto 24);
+			when "111" =>
+				alu_logic_conj(47 downto 24) <= not alu_shifter_out(47 downto 24);
+			when others =>
+		end case;
+	end process;
+
+	alu_adder : process(alu_ctrl, alu_src_op, alu_multiplier_out, alu_shifter_out) is
+		variable add_src_op_1 : signed(56 downto 0);
+		variable add_src_op_2 : signed(56 downto 0);
+		variable carry_const  : signed(56 downto 0);
+		variable alu_shifter_out_57 : signed(56 downto 0);
+		variable alu_add_result_58  : signed(57 downto 0);
+		variable alu_add_result_interm : signed(56 downto 0);
+		variable invert_carry_flag : std_logic;
+	begin
+
+		-- by default do not invert the carry
+		invert_carry_flag := '0';
+
+		-- determine whether to use multiplier output, the operand defined above, or zeros!
+		-- resizing is done here already. Like that we can see whether an overflow
+		-- occurs due to negating the source operand
+		case alu_ctrl.add_src_stage_2 is
+			when "00" => add_src_op_1 := (others => '0');
+			when "10" => add_src_op_1 := resize(alu_multiplier_out, 57);
+			when others => add_src_op_1 := resize(alu_src_op, 57);
+		end case;
+
+		-- determine the sign for the 1st operand!
+		case alu_ctrl.add_src_sign is
+			-- normal operation
+			when "00" => add_src_op_1 := add_src_op_1;
+			-- negative sign
+			when "01" => add_src_op_1 := - add_src_op_1;
+			             invert_carry_flag := not invert_carry_flag;
+			-- change according to sign
+			-- performs - | accu | for the CMPM instruction
+			when "10" =>
+				-- we subtract in any case, so invert the carry!
+				invert_carry_flag := not invert_carry_flag;
+				if add_src_op_1(55) = '0' then 
+					add_src_op_1 := - add_src_op_1;
+				else
+					add_src_op_1 :=   add_src_op_1;
+				end if;
+			-- div instruction!
+			-- sign dependant of D[55] XOR S[23], if 1 => positive , if 0 => negative
+			-- add_src_op_1 holds S[23] (sign extension!)
+			when others => 
+				if (alu_ctrl.shift_src = '0' and add_src_op_1(55) /= register_file.a(55)) or
+			   	   (alu_ctrl.shift_src = '1' and add_src_op_1(55) /= register_file.b(55)) then 
+					add_src_op_1 :=   add_src_op_1;
+				else
+					add_src_op_1 := - add_src_op_1;
+--					invert_carry_flag := not invert_carry_flag;
+				end if;
+		end case;
+
+		alu_shifter_out_57 := resize(alu_shifter_out, 57);
+
+		-- determine the sign for the 2nd operand (coming from the shifter)!
+		case alu_ctrl.shift_src_sign is
+			-- negative sign
+			when "01" =>
+			   	add_src_op_2 := - alu_shifter_out_57;
+			-- change according to sign
+			-- this allows to build the magnitude (ABS, CMPM)
+			when "10" =>
+				if alu_shifter_out(55) = '1' then 
+					add_src_op_2 := - alu_shifter_out_57;
+				else
+					add_src_op_2 :=   alu_shifter_out_57;
+				end if;
+			when others =>
+			   	add_src_op_2 := alu_shifter_out_57;
+		end case;
+
+		-- determine whether carry flag has to be added or subtracted
+		if alu_ctrl.rounding_used = "10" then
+			-- add carry flag
+			carry_const(0) := register_file.sr(C_FLAG);
+		elsif alu_ctrl.rounding_used = "11" then
+			-- subtract carry flag
+			carry_const := (others => register_file.sr(0)); -- carry flag
+		else
+			carry_const := (others => '0');
+		end if;
+
+		-- add the values and calculate the carry bit
+		alu_add_result_interm := ('0' & add_src_op_1(55 downto 0)) + 
+		                         ('0' & add_src_op_2(55 downto 0)) +
+		                         ('0' & carry_const(55 downto 0));
+
+		-- here pops the new carry out of the adder
+		if invert_carry_flag = '0' then
+			alu_add_carry_out <= alu_add_result_interm(56);
+		else 
+			alu_add_carry_out <= not alu_add_result_interm(56);
+		end if;
+
+		-- calculate the last bit (56), in order to test for overflow later on
+		alu_add_result(55 downto 0) <= alu_add_result_interm(55 downto 0);
+--		alu_add_result(56) <= add_src_op_1(56) xor add_src_op_2(56) xor alu_add_result_interm(56);
+		alu_add_result(56) <= add_src_op_1(56) xor add_src_op_2(56) 
+		                      xor carry_const(56) xor alu_add_result_interm(56);
+
+	end process alu_adder;
+
+
+	-- Adder after the normal arithmetic adder
+	-- This adder is responsible for
+--	-- 1) carry addition
+--	-- 2) carry subtration
+	-- 3) convergent rounding
+	alu_post_adder: process(alu_add_result, scaling_mode, alu_ctrl) is
+		variable post_adder_constant : signed(56 downto 0);
+		variable testing_constant    : signed(24 downto 0);
+	begin
+		-- by default add nothing
+		post_adder_constant := (others => '0');
+
+		case alu_ctrl.rounding_used is
+			-- rounding dependant on scaling bits
+			when "01" =>
+				case scaling_mode is 
+					-- no scaling
+					when "00" => testing_constant := alu_add_result(23 downto 0) & '0';
+					-- scale down
+					when "01" => testing_constant := alu_add_result(24 downto 0);
+					-- scale up
+					when "10" => testing_constant := alu_add_result(22 downto 0) & "00";
+					when others =>
+					             testing_constant := alu_add_result(23 downto 0) & '0';
+				end case;
+
+				-- Special case!
+				if testing_constant(24) = '1' and testing_constant(23 downto 0) = X"000000" then
+					-- add depending on bit left to the rounding position
+					case scaling_mode is
+						-- no scaling
+						when "00" => post_adder_constant(23) := alu_add_result(24);
+						-- scale down
+						when "01" => post_adder_constant(24) := alu_add_result(25);
+						-- scale up
+						when "10" => post_adder_constant(22) := alu_add_result(23);
+						when others =>
+					end case;
+				else -- testing_constant /= X"1000000" 
+					-- add rounding constant depending on scaling mode
+					-- results in round up if MSB of testing constant is set, else nothing happens
+					case scaling_mode is
+						-- no scaling
+						when "00" => post_adder_constant(23) := '1';
+						-- scale down
+						when "01" => post_adder_constant(24) := '1';
+						-- scale up
+						when "10" => post_adder_constant(22) := '1';
+						when others =>
+					end case;
+				end if;
+			-- no rounding
+			when others =>
+				post_adder_constant := (others => '0');
+
+		end case;
+
+		-- Add the result of the first adder to the constant (e.g., carry flag)
+		alu_post_adder_result <= alu_add_result + post_adder_constant;
+
+		-- When rounding is used set 24 LSBs to zero!
+		if alu_ctrl.rounding_used = "01" then
+			alu_post_adder_result(23 downto 0) <= (others => '0');
+		end if;
+	end process;
+
+
+
+	alu_select_new_accu: process(alu_post_adder_result, alu_logic_conj, alu_ctrl) is
+	begin
+		if alu_ctrl.logic_function /= "000" then
+			modified_accu_int <= alu_logic_conj;
+		else
+			modified_accu_int <= alu_post_adder_result(55 downto 0);
+		end if;
+	end process;
+
+
+	-- contains the 24*24 bit fractional multiplier
+	alu_multiplier : process(register_file, alu_ctrl) is
+		variable src_op1: signed(23 downto 0);
+		variable src_op2: signed(23 downto 0);
+		variable mul_result_interm : signed(47 downto 0);
+	begin
+		-- select source operands for multiplication
+		case alu_ctrl.mul_op1 is
+			when "00"   => src_op1 := register_file.x0;
+			when "01"   => src_op1 := register_file.x1;
+			when "10"   => src_op1 := register_file.y0;
+			when others => src_op1 := register_file.y1;
+		end case;
+		case alu_ctrl.mul_op2 is
+			when "00"   => src_op2 := register_file.x0;
+			when "01"   => src_op2 := register_file.x1;
+			when "10"   => src_op2 := register_file.y0;
+			when others => src_op2 := register_file.y1;
+		end case;
+
+		-- perform integer multiplication
+		mul_result_interm := src_op1 * src_op2;
+
+		-- sign extension of result
+		alu_multiplier_out(55 downto 48) <= (others => mul_result_interm(47));
+		-- convert from two's complement representation to fractional format
+		-- signed integer multiplication delivers twice the sign bit, but only one is needed for the
+		-- fractional multiplication, so remove one and append a zero to the result
+		alu_multiplier_out(47 downto 0) <= mul_result_interm(46 downto 0) & '0';
+
+	end process alu_multiplier;
+
+
+	-- contains the data shifter
+	alu_shifter: process(register_file, alu_ctrl, norm_instr_asl, norm_instr_asr) is
+		variable src_accu : signed(55 downto 0);
+		variable shift_to_perform : alu_shift_mode;
+	begin
+		-- read source accumulator
+		if alu_ctrl.shift_src = '0' then
+			src_accu := register_file.a;
+		else
+			src_accu := register_file.b;
+		end if;
+
+		alu_shifter_carry_out <= '0';
+		alu_shifter_overflow_out <= '0';
+
+		-- NORM instruction determines the shift value just
+		-- in time, so overwrite the flag from the alu_ctrl
+ 		-- for this instruction by the calculated value
+		if alu_ctrl.norm_instr = '0' then
+			shift_to_perform := alu_ctrl.shift_mode;
+		else
+			if norm_instr_asl = '1' then
+				shift_to_perform := SHIFT_LEFT;
+			elsif norm_instr_asr = '1' then
+				shift_to_perform := SHIFT_RIGHT;
+			else
+				shift_to_perform := NO_SHIFT;
+			end if;
+		end if;
+
+		case shift_to_perform is
+			when NO_SHIFT => 
+				alu_shifter_out <= src_accu;
+			when SHIFT_LEFT => 
+				-- ASL, ADDL, DIV?
+				if alu_ctrl.word_24_update = '0' then
+					-- special handling for div instruction required
+					if alu_ctrl.div_instr = '1' then
+						alu_shifter_out <= src_accu(54 downto 0) & register_file.sr(C_FLAG);
+					else
+						alu_shifter_out <= src_accu(54 downto 0) & '0';
+					end if;
+					alu_shifter_carry_out <= src_accu(55);
+					-- detect overflow that results from left shifting 
+					-- Needed for ASL, ADDL, DIV instructions
+					if src_accu(55) /= src_accu(54) then
+						alu_shifter_overflow_out <= '1';
+					end if;
+				-- LSL/ROL?
+				elsif alu_ctrl.word_24_update = '1' then
+					alu_shifter_out(55 downto 48) <= src_accu(55 downto 48);
+					alu_shifter_out(23 downto  0) <= src_accu(23 downto  0);
+					alu_shifter_carry_out <= src_accu(47);
+					if alu_ctrl.rotate = '0' then -- LSL ?
+						alu_shifter_out(47 downto 24) <= src_accu(46 downto 24) & '0';
+					else -- ROL ?
+						alu_shifter_out(47 downto 24) <= src_accu(46 downto 24) & register_file.sr(C_FLAG);
+					end if;
+				end if;
+			when SHIFT_RIGHT => 
+				-- ASR?
+				if alu_ctrl.word_24_update = '0' then
+					alu_shifter_out <= src_accu(55) & src_accu(55 downto 1);
+					alu_shifter_carry_out <= src_accu(0);
+				-- LSR/ROR?
+				elsif alu_ctrl.word_24_update = '1' then
+					alu_shifter_out(55 downto 48) <= src_accu(55 downto 48);
+					alu_shifter_out(23 downto  0) <= src_accu(23 downto  0);
+					alu_shifter_carry_out <= src_accu(24);
+					if alu_ctrl.rotate = '0' then -- LSR
+						alu_shifter_out(47 downto 24) <= '0' & src_accu(47 downto 25);
+					else -- ROR
+						alu_shifter_out(47 downto 24) <= register_file.sr(C_FLAG) & src_accu(47 downto 25);
+					end if;
+				end if;
+			when ZEROS =>
+				alu_shifter_out <= (others => '0');
+		end case;
+	end process alu_shifter;
+
+
+	-- Special handling for NORM instruction
+ 	-- Determine which case occurs (see User's Manual for more information)
+	norm_instr_logic: process(register_file, addr_r_in) is
+	begin
+		norm_instr_asl <= '0';
+		norm_instr_asr <= '0';
+
+		-- Either left shift
+		if register_file.sr(E_FLAG) = '0' and
+		   register_file.sr(U_FLAG) = '1' and
+		   register_file.sr(Z_FLAG) = '0' then
+			norm_instr_asl <= '1';
+			norm_update_ccr <= '1';
+			addr_r_out <= addr_r_in - 1;
+		-- Or right shift
+		elsif register_file.sr(E_FLAG) = '1' then
+			norm_instr_asr <= '1';
+			norm_update_ccr <= '1';
+			addr_r_out <= addr_r_in + 1;
+		-- Or do nothing!
+		else 
+			norm_update_ccr <= '0';
+			addr_r_out <= addr_r_in;
+		end if;
+	end process;
+
+end architecture;
diff --git a/FPGA_quartus_GE/DSP/src/exec_stage_bit_modify.vhd b/FPGA_quartus_GE/DSP/src/exec_stage_bit_modify.vhd
new file mode 100644
index 0000000..68fecbb
--- /dev/null
+++ b/FPGA_quartus_GE/DSP/src/exec_stage_bit_modify.vhd
@@ -0,0 +1,79 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity exec_stage_bit_modify is port(
+	instr_word        : in  std_logic_vector(23 downto 0);
+	instr_array       : in  instructions_type;
+	src_operand       : in  std_logic_vector(23 downto 0);
+	register_file     : in  register_file_type;
+	dst_operand       : out std_logic_vector(23 downto 0);
+	bit_cond_met      : out std_logic;
+	modify_sr         : out std_logic;
+	modified_sr       : out std_logic_vector(15 downto 0)
+);
+end entity;
+
+
+architecture rtl of exec_stage_bit_modify is 
+
+	signal operand_bit : std_logic;
+	signal src_operand_32 : std_logic_vector(31 downto 0);
+
+begin
+
+	-- this is just a helper signal to prevent the simulator
+	-- to stop when accessing a bit > 23.
+	src_operand_32 <= "00000000" & src_operand;
+	-- read the bit we want to test (and modify)
+	operand_bit <= src_operand_32(to_integer(unsigned(instr_word(4 downto 0))));
+
+	-- modify the Carry flag only for the bit modify instructions!
+	modify_sr <= '1' when instr_array = INSTR_BCLR or instr_array = INSTR_BSET or instr_array = INSTR_BCHG or instr_array = INSTR_BTST else '0';
+	modified_sr <= register_file.sr(15 downto 1) & operand_bit;
+
+	bit_operation: process(instr_word, instr_array, src_operand, operand_bit) is
+		variable new_bit : std_logic;
+	begin
+		-- do nothing by default!
+		dst_operand <= src_operand;
+		bit_cond_met <= '0';
+
+		-- determine which bit to write
+		if instr_array = INSTR_BCLR then
+			new_bit := '0';
+		elsif instr_array = INSTR_BSET then
+			new_bit := '1';
+		else -- BCHG
+			new_bit := not operand_bit;
+		end if;
+
+		if instr_array = INSTR_BCLR or instr_array = INSTR_BSET or instr_array = INSTR_BCHG then
+			dst_operand(to_integer(unsigned(instr_word(4 downto 0)))) <= new_bit;
+		end if;
+
+
+		-- check for the jump instructions whether condition is met or not!
+		if instr_array = INSTR_JCLR or instr_array = INSTR_JSCLR then
+			if operand_bit = '0' then
+				bit_cond_met <= '1';
+			else
+				bit_cond_met <= '0';
+			end if;
+		end if;
+		if instr_array = INSTR_JSET or instr_array = INSTR_JSSET then
+			if operand_bit = '0' then
+				bit_cond_met <= '0';
+			else
+				bit_cond_met <= '1';
+			end if;
+		end if;
+
+	end process;
+
+
+end architecture;
diff --git a/FPGA_quartus_GE/DSP/src/exec_stage_branch.vhd b/FPGA_quartus_GE/DSP/src/exec_stage_branch.vhd
new file mode 100644
index 0000000..9b07913
--- /dev/null
+++ b/FPGA_quartus_GE/DSP/src/exec_stage_branch.vhd
@@ -0,0 +1,117 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity exec_stage_branch is port(
+	activate_exec_bra : in  std_logic;
+	instr_word        : in  std_logic_vector(23 downto 0);
+	instr_array       : in  instructions_type;
+	register_file     : in  register_file_type;
+	jump_address      : in  unsigned(BW_ADDRESS-1 downto 0);
+	bit_cond_met      : in  std_logic;
+	cc_flag_set       : in  std_logic;
+	push_stack        : out push_stack_type;
+	pop_stack         : out pop_stack_type;
+	modify_pc         : out std_logic;
+	modified_pc       : out unsigned(BW_ADDRESS-1 downto 0);
+	modify_sr         : out std_logic;
+	modified_sr       : out std_logic_vector(15 downto 0)
+);
+end entity;
+
+
+architecture rtl of exec_stage_branch is 
+
+	signal branch_condition_met : std_logic;
+	signal modify_pc_int        : std_logic;
+
+begin
+
+	modify_pc_int <= '1' when activate_exec_bra = '1' and branch_condition_met = '1' else '0';
+	modify_pc     <= modify_pc_int;
+
+	calculate_branch_condition : process(instr_word, instr_array, register_file, bit_cond_met)
+	begin
+		branch_condition_met <= '0';
+
+		-- unconditional jumps
+		if instr_array = INSTR_JMP or 
+		   instr_array = INSTR_JSR or
+		   instr_array = INSTR_RTI or
+		   instr_array = INSTR_RTS then
+			-- jump always
+			branch_condition_met <= '1';
+		end if;
+		--  then see whether the branch condition is satisfied
+		if instr_array = INSTR_JCC or instr_array = INSTR_JSCC then
+			branch_condition_met <= cc_flag_set;
+		end if;
+		-- jmp that is executed according to a certain bit condition
+		if instr_array = INSTR_JCLR or instr_array = INSTR_JSCLR or
+		   instr_array = INSTR_JSET or instr_array = INSTR_JSSET then 
+			branch_condition_met <= bit_cond_met;
+		end if;
+	end process calculate_branch_condition;
+
+
+	calculate_branch_target : process(instr_array, instr_word, jump_address)
+	begin
+		modified_pc <= jump_address;
+
+		-- address calculation is the same for the following instructions
+		if instr_array = INSTR_JMP  or 
+		   instr_array = INSTR_JCC  or 
+		   instr_array = INSTR_JSCC or
+		   instr_array = INSTR_JSR then
+			if instr_word(18) = '1' then
+				-- short jump address included in opcode (bits 11 downto 0)
+				modified_pc(11 downto 0) <= unsigned(instr_word(11 downto 0));
+			elsif instr_word(18) = '0' then
+				-- effective address defined by opcode and coming from address generator unit
+				modified_pc <= jump_address;
+			end if;
+		end if;
+
+		-- jump address contains the obligatory address of the second
+		-- instruction word
+		if instr_array = INSTR_JCLR or
+		   instr_array = INSTR_JSET or
+		   instr_array = INSTR_JSCLR or
+		   instr_array = INSTR_JSSET then
+			   modified_pc <= jump_address;
+		end if;
+
+		-- target address is stored on the stack
+		if instr_array = INSTR_RTS or
+		   instr_array = INSTR_RTI then
+			   modified_pc <= unsigned(register_file.current_ssh);
+		end if;
+	end process calculate_branch_target;
+
+	-- Subroutine functions need to store PC and SR on the stack
+	push_stack.valid <= '1' when modify_pc_int = '1' and (instr_array = INSTR_JSCC  or instr_array = INSTR_JSR or 
+	                                                      instr_array = INSTR_JSCLR or instr_array = INSTR_JSSET) else '0';
+	push_stack.content <= PC_AND_SR;
+	-- pc is set externally!
+	push_stack.pc <= (others => '0');
+
+	-- RTI/RTS instructions need to read from the stack
+	pop_stack.valid <= '1' when modify_pc_int = '1' and (instr_array = INSTR_RTI or instr_array = INSTR_RTS) else '0';
+
+	-- some instructions require to set the SR 
+	calculate_status_register : process(instr_array)
+	begin
+		modify_sr <= '0';
+		modified_sr <= (others => '0');
+		if instr_array = INSTR_RTI then
+			modify_sr <= '1';
+			modified_sr <= register_file.current_ssl;
+		end if;
+	end process calculate_status_register;
+
+
+end architecture rtl;
diff --git a/FPGA_quartus_GE/DSP/src/exec_stage_cc_flag_calc.vhd b/FPGA_quartus_GE/DSP/src/exec_stage_cc_flag_calc.vhd
new file mode 100644
index 0000000..63a0b2c
--- /dev/null
+++ b/FPGA_quartus_GE/DSP/src/exec_stage_cc_flag_calc.vhd
@@ -0,0 +1,75 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity exec_stage_cc_flag_calc is port(
+	instr_word        : in  std_logic_vector(23 downto 0);
+	instr_array       : in  instructions_type;
+	register_file     : in  register_file_type;
+	cc_flag_set       : out std_logic
+);
+end entity;
+
+
+architecture rtl of exec_stage_cc_flag_calc is
+
+
+begin
+
+	calculate_cc_flag : process(instr_word, instr_array, register_file)
+
+		variable cc_select : std_logic_vector(3 downto 0);
+
+		procedure calculate_cc_flag(cc: std_logic_vector(3 downto 0)) is
+			variable c_flag : std_logic := register_file.ccr(0);
+			variable v_flag : std_logic := register_file.ccr(1);
+			variable z_flag : std_logic := register_file.ccr(2);
+			variable n_flag : std_logic := register_file.ccr(3);
+			variable u_flag : std_logic := register_file.ccr(4);
+			variable e_flag : std_logic := register_file.ccr(5);
+			variable l_flag : std_logic := register_file.ccr(6);
+
+		begin
+			if (cc = "0000" and c_flag = '0')  or -- CC: carry clear 
+			   (cc = "1000" and c_flag = '1')  or -- CS: carry set
+			   (cc = "0101" and e_flag = '0')  or -- EC: extension clear
+			   (cc = "1010" and z_flag = '1')  or -- EQ: equal
+			   (cc = "1101" and e_flag = '1')  or -- ES: extension set
+			   (cc = "0001" and (n_flag = v_flag))  or -- GE: greater than or equal
+			   (cc = "0001" and ((n_flag xor v_flag) or z_flag) = '0')  or -- GT: greater than
+			   (cc = "0110" and l_flag = '0')  or -- LC: limit clear 
+			   (cc = "1111" and ((n_flag xor v_flag) or z_flag ) = '1')  or -- LE: less or equal
+			   (cc = "1110" and l_flag = '1')  or -- LS: limit set
+			   (cc = "1001" and (n_flag /= v_flag))  or -- LT: less than
+			   (cc = "1011" and n_flag = '1')  or -- MI: minus
+			   (cc = "0010" and z_flag = '0')  or -- NE: not equal
+			   (cc = "1100" and (( not u_flag and not  e_flag) or z_flag) = '1') or -- NR: normalized
+			   (cc = "0011" and n_flag = '0')  or -- PL: plus
+			   (cc = "0100" and (( not u_flag and not e_flag ) or z_flag) = '0')   -- NN: not normalized
+			then
+				cc_flag_set <= '1';
+			end if;
+		end procedure;
+	
+	begin
+
+		cc_flag_set <= '0';
+
+		-- Rip the flags we have to test for from the instruction word
+		if (instr_array = INSTR_JCC and instr_word(18) = '0') or
+		   (instr_array = INSTR_JSCC) then
+			   cc_select := instr_word(3 downto 0);
+		else
+			   cc_select := instr_word(15 downto 12);
+		end if;
+	
+		calculate_cc_flag(cc_select);
+
+	end process;
+
+
+end architecture;
diff --git a/FPGA_quartus_GE/DSP/src/exec_stage_cr_mod.vhd b/FPGA_quartus_GE/DSP/src/exec_stage_cr_mod.vhd
new file mode 100644
index 0000000..c236db7
--- /dev/null
+++ b/FPGA_quartus_GE/DSP/src/exec_stage_cr_mod.vhd
@@ -0,0 +1,72 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity exec_stage_cr_mod is port (
+	activate_exec_cr_mod : in  std_logic;
+	instr_word           : in  std_logic_vector(23 downto 0);
+	instr_array          : in  instructions_type;
+	register_file        : in  register_file_type;
+	modify_sr            : out std_logic;
+	modified_sr          : out std_logic_vector(15 downto 0);
+	modify_omr           : out std_logic;
+	modified_omr         : out std_logic_vector(7 downto 0)
+);
+end exec_stage_cr_mod;
+
+
+architecture rtl of exec_stage_cr_mod is
+
+begin
+
+	process(activate_exec_cr_mod, instr_word, instr_array, register_file) is
+		variable imm8 : std_logic_vector(7 downto 0);
+		variable op8  : std_logic_vector(7 downto 0);
+		variable res8 : std_logic_vector(7 downto 0);
+	begin
+		modify_sr    <= '0';
+		modify_omr   <= '0';
+		modified_sr  <= (others => '0');
+		modified_omr <= (others => '0');
+
+		imm8 := instr_word(15 downto 8);
+		if instr_word(1 downto 0) = "00" then
+			-- read MR
+			op8 := register_file.mr;
+		elsif instr_word(1 downto 0) = "01" then
+			-- read CCR
+			op8 := register_file.ccr;
+		else  -- instr_word(1 downto 0) = "10"
+			-- read OMR
+			op8 := register_file.omr;
+		end if;
+
+		if instr_array = INSTR_ANDI then
+			res8 := imm8 and op8;
+		else -- instr_array = INSTR_ORI
+			res8 := imm8 or op8;
+		end if;
+
+		-- only write the result when activated
+		if activate_exec_cr_mod = '1' then
+			if instr_word(1 downto 0) = "00" then
+				-- update MR
+				modify_sr    <= '1';
+				modified_sr  <= res8 & register_file.ccr;
+			elsif instr_word(1 downto 0) = "01" then
+				-- update CCR
+				modify_sr    <= '1';
+				modified_sr  <= register_file.mr & res8;
+			elsif instr_word(1 downto 0) = "10" then
+				-- update OMR
+				modify_omr   <= '1';
+				modified_omr <= res8;
+			end if;
+		end if;
+	end process;
+
+end architecture;
diff --git a/FPGA_quartus_GE/DSP/src/exec_stage_loops.vhd b/FPGA_quartus_GE/DSP/src/exec_stage_loops.vhd
new file mode 100644
index 0000000..cc32692
--- /dev/null
+++ b/FPGA_quartus_GE/DSP/src/exec_stage_loops.vhd
@@ -0,0 +1,200 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity exec_stage_loop is port(
+	clk, rst           : in  std_logic;
+	activate_exec_loop : in  std_logic;
+	instr_word        : in  std_logic_vector(23 downto 0);
+	instr_array       : in  instructions_type;
+	loop_iterations   : in  unsigned(15 downto 0);
+	loop_address      : in  unsigned(BW_ADDRESS-1 downto 0);
+	loop_start_address: in  unsigned(BW_ADDRESS-1 downto 0);
+	register_file     : in  register_file_type;
+	fetch_perform_enddo: in std_logic;
+	memory_stall      : in  std_logic;
+	push_stack        : out push_stack_type;
+	pop_stack         : out pop_stack_type;
+	stall_rep         : out std_logic;
+	stall_do          : out std_logic;
+	decrement_lc      : out std_logic;
+	modify_lc         : out std_logic;
+	modified_lc       : out unsigned(15 downto 0);
+	modify_la         : out std_logic;
+	modified_la       : out unsigned(15 downto 0);
+	modify_pc         : out std_logic;
+	modified_pc       : out unsigned(BW_ADDRESS-1 downto 0);
+	modify_sr         : out std_logic;
+	modified_sr       : out std_logic_vector(15 downto 0)
+);
+end entity;
+
+
+architecture rtl of exec_stage_loop is
+
+	signal rep_loop_polling : std_logic;
+	signal do_loop_polling  : std_logic;
+	signal enddo_polling    : std_logic;
+	signal lc_temp          : unsigned(15 downto 0);
+	signal rf_lc_eq_1       : std_logic;
+	signal memory_stall_t   : std_logic;
+
+begin
+
+	modified_pc <= loop_start_address;
+
+
+	-- loop counter in register file equal to 1?
+	rf_lc_eq_1 <= '1' when register_file.lc = 1 else '0';
+
+	process(activate_exec_loop, instr_array, register_file, fetch_perform_enddo,
+	        rep_loop_polling, loop_iterations, rf_lc_eq_1, loop_start_address) is
+	begin
+		stall_rep <= '0';
+		stall_do  <= '0';
+
+		modify_la <= '0';
+		modify_lc <= '0';
+		modify_pc <= '0';
+		modify_sr <= '0';
+		modified_la <= loop_address;
+		modified_lc <= loop_iterations; -- default
+		-- set the loop flag LF (bit 15) of Status register
+		modified_sr(15) <= '1';
+		modified_sr(14 downto 0) <= register_file.sr(14 downto 0);
+
+		push_stack.valid <= '0'; -- push PC and SR on the stack
+		push_stack.pc    <= loop_start_address;
+		push_stack.content <= LA_AND_LC;
+
+		pop_stack.valid <= '0';
+		decrement_lc <= '0';
+		------------------
+		-- DO instruction
+		------------------
+		if activate_exec_loop = '1' and instr_array = INSTR_DO then
+			-- first instruction of the do loop instruction?
+			if do_loop_polling = '0' then
+				stall_do <= '1';
+				modify_lc <= '1'; -- store the new loop counter
+				modify_la <= '1'; -- store the new loop address 
+				push_stack.valid <= '1'; -- push LA and LC on the stack
+				push_stack.content <= LA_AND_LC;
+			else  -- second clock cycle of the do loop instruction ?
+				push_stack.valid <= '1'; -- push PC and SR on the stack
+				push_stack.pc    <= loop_start_address;
+				push_stack.content <= PC_AND_SR;
+				-- set the PC to the first instruction of the loop
+				-- the already fetched instruction are flushed from the pipeline
+				-- this prevents problems, when the loop consists of only one or two instructions
+				modify_pc   <= '1';
+				-- set the loop flag
+				modify_sr   <= '1';
+			end if;
+		end if;
+		-----------------------------------------------
+		-- ENDDO instruction / loop end in fetch stage
+		-----------------------------------------------
+		if (activate_exec_loop = '1' and instr_array = INSTR_ENDDO) or fetch_perform_enddo = '1' or enddo_polling = '1' then
+			pop_stack.valid <= '1';
+			if enddo_polling = '0' then
+				-- only restore the LF from the stack
+				modified_sr(15) <= register_file.current_ssl(15);
+				modify_sr <= '1';
+				stall_do <= '1'; -- stall one clock cycle 
+			else
+				-- restore loop counter and loop address in second clock cycle
+				modified_lc <= unsigned(register_file.current_ssl);
+				modify_lc <= '1';
+				modified_la <= unsigned(register_file.current_ssh);
+				modify_la <= '1';
+			end if;
+		end if;
+		-------------------
+		-- REP instruction
+		-------------------
+		if activate_exec_loop = '1' and instr_array = INSTR_REP then
+			-- only do something when there are more than 1 iterations
+			-- the first execution is already on the way
+			if loop_iterations /= 1 then
+				stall_rep <= '1'; -- stall the fetch and decode stages
+				modify_lc <= '1'; -- store the loop counter
+				modified_lc <= loop_iterations - 1;
+			end if;
+		end if;
+
+		-- keep processing the single instruction
+		if rep_loop_polling = '1' then
+			stall_rep <= '1';
+			-- if the REP instruction cause a  stall do not modify the lc!
+			if memory_stall_t = '0' then
+				if rf_lc_eq_1 = '0' then
+					decrement_lc <= '1';
+				-- when the instruction to repeat caused a memory stall
+				-- do not continue!
+				else
+					-- finish the REP instruction by restoring the LC
+					stall_rep <= '0';
+					modify_lc <= '1';
+					modified_lc <= lc_temp;
+				end if;
+			end if;
+		end if;
+	end process;
+
+
+	-- process that allows to remember that we are processing a REP/DO instruction
+	-- even though the REP instruction is not available in the pipeline anymore
+	-- also store the old loop counter
+	process(clk) is
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				rep_loop_polling <= '0';
+				do_loop_polling  <= '0';
+				enddo_polling    <= '0';
+				lc_temp <= (others => '0');
+				memory_stall_t <= '0';
+			else
+				memory_stall_t <= memory_stall;
+
+				if activate_exec_loop = '1' and instr_array = INSTR_REP then
+					-- only do something when there are more than 1 iterations
+					-- the first execution is already on the way
+					if loop_iterations /= 1 then
+						rep_loop_polling <= '1';
+						lc_temp <= register_file.lc;
+					end if;
+				end if;
+				-- test whether the REP instruction has been executed
+				if rep_loop_polling = '1' and rf_lc_eq_1 = '1' and memory_stall_t = '0'  then
+					rep_loop_polling <= '0';
+				end if;
+
+				-- do loop execution takes two clock cycles
+				-- in the first  clock cycle we store loop address and loop counter on the stack
+				-- in the second clock cycle we store programm counter and status register on the stack
+				if activate_exec_loop = '1' and instr_array = INSTR_DO then
+					do_loop_polling <= '1';
+				end if;
+				-- clear the flag immediately again (only two cycles execution time!)
+				if do_loop_polling = '1' then
+					do_loop_polling <= '0';
+				end if;
+
+				-- ENDDO instructions take two clock cycles as well!
+				if (activate_exec_loop = '1' and instr_array = INSTR_ENDDO) or fetch_perform_enddo = '1' then
+					enddo_polling <= '1';
+				end if;
+				if enddo_polling = '1' then
+					enddo_polling <= '0';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end architecture;
diff --git a/FPGA_quartus_GE/DSP/src/fetch_stage.vhd b/FPGA_quartus_GE/DSP/src/fetch_stage.vhd
new file mode 100644
index 0000000..6b22f09
--- /dev/null
+++ b/FPGA_quartus_GE/DSP/src/fetch_stage.vhd
@@ -0,0 +1,60 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+
+
+entity fetch_stage is port(
+
+	pc_old        : in  unsigned(BW_ADDRESS-1 downto 0);
+	pc_new        : out unsigned(BW_ADDRESS-1 downto 0);
+	modify_pc     : in  std_logic;
+	modified_pc   : in  unsigned(BW_ADDRESS-1 downto 0);
+	register_file : in  register_file_type;
+	decrement_lc  : out std_logic;
+	perform_enddo : out std_logic
+
+);
+end fetch_stage;
+
+
+architecture rtl of fetch_stage is
+
+
+begin
+
+	pc_calculation: process(pc_old, modify_pc, modified_pc, register_file)  is
+	begin
+		decrement_lc  <= '0';
+		perform_enddo <= '0';
+
+		-- by default increment pc by one
+		pc_new <= pc_old + 1;
+		if modify_pc = '1' then
+			pc_new <= modified_pc;
+		end if;
+		-- Loop Flag set?
+		if register_file.sr(15) = '1' then
+			if register_file.la = pc_old then
+				-- Loop not finished?
+				-- => start from the beginning if necessary
+				if register_file.lc /= 1 then
+					-- if the last address was LA and the loop is not finished yet, we have to 
+					-- read now from the beginning of the loop again
+					pc_new <= unsigned(register_file.current_ssh(BW_ADDRESS-1 downto 0));
+					-- decrement loop counter
+					decrement_lc <= '1';
+				else
+					-- loop done!
+					-- => tell the loop controller in the exec stage to perform the enddo operation
+					-- (without flushing of the pipeline!)
+					perform_enddo <= '1';
+				end if;
+		   	end if;
+		end if;
+	end process pc_calculation;
+
+end architecture rtl;
+
diff --git a/FPGA_quartus_GE/DSP/src/mem_control.vhd b/FPGA_quartus_GE/DSP/src/mem_control.vhd
new file mode 100644
index 0000000..091fcf0
--- /dev/null
+++ b/FPGA_quartus_GE/DSP/src/mem_control.vhd
@@ -0,0 +1,1519 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+
+entity mem_control is
+	generic(
+		mem_type : memory_type := P_MEM
+	);
+	port(
+		clk, rst        : in std_logic;
+		rd_addr         : in unsigned(BW_ADDRESS-1 downto 0);
+		rd_en           : in std_logic;
+		data_out        : out std_logic_vector(23 downto 0);
+		data_out_valid  : out std_logic;
+		wr_addr         : in  unsigned(BW_ADDRESS-1 downto 0);
+		wr_en           : in  std_logic;
+		wr_accomplished : out std_logic;
+		data_in         : in  std_logic_vector(23 downto 0)
+	);
+end entity mem_control;
+
+
+architecture rtl of mem_control is
+
+	signal int_mem_rd_addr : std_logic_vector(7 downto 0);
+	type int_mem_type is array(0 to 255) of std_logic_vector(23 downto 0);
+	signal int_mem : int_mem_type;
+	signal int_pmem : int_mem_type := (
+-- ABS begin
+--X"0000B9",
+--X"56F400",
+--X"200000",
+--X"200026",
+--X"56F400",
+--X"E00000",
+--X"200026",
+--X"56F400",
+--X"000000",
+--X"200026",
+--X"52F400",
+--X"000080",
+--X"200026",
+-- ABS end
+
+-- ADC begin
+--X"46F400",
+--X"000000",
+--X"47F400",
+--X"000001",
+--X"20001B",
+--X"51F400",
+--X"000001",
+--X"0000B9",
+--X"0001F9",
+--X"200039",
+--X"47F400",
+--X"800000",
+--X"53F400",
+--X"000080",
+--X"200039",
+-- ADC end
+
+-- ADD begin
+--X"46F400",
+--X"000000",
+--X"47F400",
+--X"000001",
+--X"20001B",
+--X"51F400",
+--X"000001",
+--X"0000B9",
+--X"0001F9",
+--X"200038",
+--X"47F400",
+--X"800000",
+--X"53F400",
+--X"000080",
+--X"200038",
+-- ADD end
+
+-- ADDL begin
+--X"56F400",
+--X"000055",
+--X"20001B",
+--X"51F400",
+--X"000055",
+--X"0000B9",
+--X"20001A",
+--X"56F400",
+--X"0000AA",
+--X"20001A",
+--X"53F400",
+--X"000080",
+--X"20001A",
+-- ADDL end
+
+-- ADDR begin
+--X"56F400",
+--X"000055",
+--X"20001B",
+--X"51F400",
+--X"000055",
+--X"0000B9",
+--X"20000A",
+--X"56F400",
+--X"0000AA",
+--X"20000A",
+--X"53F400",
+--X"000080",
+--X"20000A",
+-- ADDR end
+
+-- AND begin
+--X"46F400",
+--X"000FFF",
+--X"57F400",
+--X"FFFFFF",
+--X"0000B9",
+--X"20005E",
+--X"46F400",
+--X"FFF000",
+--X"57F400",
+--X"FFFFFF",
+--X"0000B9",
+--X"20005E",
+--X"46F400",
+--X"000000",
+--X"57F400",
+--X"FFFFFF",
+--X"0000B9",
+--X"20005E",
+-- AND end
+
+-- EOR begin
+--X"46F400",
+--X"000FFF",
+--X"57F400",
+--X"FF00FF",
+--X"0000B9",
+--X"20005B",
+--X"46F400",
+--X"FFFFFF",
+--X"57F400",
+--X"FFFFFF",
+--X"0000B9",
+--X"20005B",
+-- EOR end
+
+-- OR begin
+--X"46F400",
+--X"000FFF",
+--X"57F400",
+--X"FF00FF",
+--X"0000B9",
+--X"20005A",
+--X"46F400",
+--X"000000",
+--X"57F400",
+--X"000000",
+--X"0000B9",
+--X"20005A",
+-- OR end
+
+-- NOT begin
+--X"46F400",
+--X"000FFF",
+--X"57F400",
+--X"7F00FF",
+--X"0000B9",
+--X"20001F",
+--X"46F400",
+--X"000000",
+--X"57F400",
+--X"FFFFFF",
+--X"0000B9",
+--X"20001F",
+-- NOT end
+
+-- ASL begin
+--X"20001B",
+--X"51F400",
+--X"0000A5",
+--X"55F400",
+--X"0000A5",
+--X"53F400",
+--X"0000A5",
+--X"0000B9",
+--X"20003A",
+-- ASL end
+
+-- ASR begin
+--X"20001B",
+--X"51F400",
+--X"0000A5",
+--X"55F400",
+--X"0000A5",
+--X"53F400",
+--X"0000A5",
+--X"0000B9",
+--X"20002A",
+-- ASR end
+
+-- CLR begin
+--X"0000B9",
+--X"56F400",
+--X"200000",
+--X"200013",
+--X"56F400",
+--X"E00000",
+--X"0000B9",
+--X"0001F9",
+--X"200013",
+-- CLR end
+
+-- CMP begin
+--X"2F2000",
+--X"262400",
+--X"0000B9",
+--X"20005D",
+--X"2F2000",
+--X"262000",
+--X"0000B9",
+--X"20005D",
+--X"2F2400",
+--X"262000",
+--X"0000B9",
+--X"20005D",
+--X"57F400",
+--X"800AAA",
+--X"262000",
+--X"0000B9",
+--X"20005D",
+--X"46F400",
+--X"800AAA",
+--X"2F2000",
+--X"0000B9",
+--X"20005D",
+-- CMP end
+
+-- CMPM begin
+--X"2F2000",
+--X"262400",
+--X"0000B9",
+--X"20005F",
+--X"2F2000",
+--X"262000",
+--X"0000B9",
+--X"20005F",
+--X"2F2400",
+--X"262000",
+--X"0000B9",
+--X"20005F",
+--X"57F400",
+--X"800AAA",
+--X"262000",
+--X"0000B9",
+--X"20005F",
+--X"46F400",
+--X"800AAA",
+--X"2F2000",
+--X"0000B9",
+--X"20005F",
+-- CMPM end
+
+-- DIV begin
+--X"00FEB9",
+--X"44F400",
+--X"600000",
+--X"56F400",
+--X"200000",
+--X"0618A0",
+--X"018040",
+--X"210E00",
+-- DIV end
+
+-- LSL begin
+--X"0000B9",
+--X"56F400",
+--X"200000",
+--X"56F400",
+--X"AAAAAA",
+--X"50F400",
+--X"BCDEFA",
+--X"0618A0",
+--X"200033",
+-- LSL end
+
+-- LSR begin
+--X"0000B9",
+--X"56F400",
+--X"200000",
+--X"56F400",
+--X"AAAAAA",
+--X"50F400",
+--X"BCDEFA",
+--X"0618A0",
+--X"200023",
+-- LSR end
+
+-- MPY begin
+--X"0000B9",
+--X"44F400",
+--X"200000",
+--X"46F400",
+--X"400000",
+--X"2000D0",
+--X"44F400",
+--X"E00000",
+--X"46F400",
+--X"B9999A",
+--X"2000D0",
+--X"44F400",
+--X"E66666",
+--X"46F400",
+--X"466666",
+--X"2000D0",
+--X"44F400",
+--X"E66666",
+--X"46F400",
+--X"466666",
+--X"2000D4",
+-- MPY end
+
+-- MAC begin
+--X"0000B9",
+--X"200013",
+--X"2A8000",
+--X"44F400",
+--X"200000",
+--X"46F400",
+--X"400000",
+--X"2000D6",
+--X"44F400",
+--X"E00000",
+--X"46F400",
+--X"B9999A",
+--X"2000D2",
+--X"44F400",
+--X"E66666",
+--X"46F400",
+--X"466666",
+--X"2000D2",
+--X"44F400",
+--X"E66666",
+--X"46F400",
+--X"466666",
+--X"2000D6",
+-- MAC end
+
+-- MACR begin
+--X"0000B9",
+--X"200013",
+--X"2E1000",
+--X"44F400",
+--X"123456",
+--X"46F400",
+--X"123456",
+--X"2000D3",
+--X"56F400",
+--X"100001",
+--X"44F400",
+--X"123456",
+--X"46F400",
+--X"123456",
+--X"2000D3",
+--X"2E1000",
+--X"50F400",
+--X"800000",
+--X"44F400",
+--X"123456",
+--X"46F400",
+--X"123456",
+--X"2000D3",
+-- MACR end
+
+-- MPYR begin
+--X"0000B9",
+--X"46F400",
+--X"654321",
+--X"200095",
+-- MPYR end
+
+-- NEG begin
+--X"0000B9",
+--X"56F400",
+--X"654321",
+--X"200036",
+--X"200013",
+--X"52F400",
+--X"000080",
+--X"200036",
+--X"56F400",
+--X"800000",
+--X"200036",
+-- NEG end
+
+-- NORM begin
+X"200013",
+X"2C0100",
+X"200003",
+X"062FA0",
+X"01DB15",
+X"200013",
+X"2EFF00",
+X"2A8400",
+X"200003",
+X"062FA0",
+X"01D915",
+X"200013",
+X"062FA0",
+X"01DA15",
+-- NORM end
+
+-- RND begin
+--X"0000B9",
+--X"54F400",
+--X"123456",
+--X"50F400",
+--X"789ABC",
+--X"200011",
+--X"54F400",
+--X"123456",
+--X"50F400",
+--X"800000",
+--X"200011",
+--X"54F400",
+--X"123455",
+--X"50F400",
+--X"800000",
+--X"200011",
+-- RND end
+
+-- ROR begin
+--X"0000B9",
+--X"56F400",
+--X"AAAAAA",
+--X"50F400",
+--X"BCDEFA",
+--X"0618A0",
+--X"200027",
+-- ROR end
+
+-- ROL begin
+--X"0000B9",
+--X"56F400",
+--X"AAAAAA",
+--X"50F400",
+--X"BCDEFA",
+--X"0618A0",
+--X"200037",
+-- ROL end
+
+
+-- SUB begin
+--X"46F400",
+--X"000000",
+--X"47F400",
+--X"000001",
+--X"20001B",
+--X"51F400",
+--X"000001",
+--X"0000B9",
+--X"0001F9",
+--X"20003C",
+--X"47F400",
+--X"800000",
+--X"53F400",
+--X"000080",
+--X"20003C",
+--X"20001B",
+--X"53F400",
+--X"000080",
+--X"47F400",
+--X"000001",
+--X"20007C",
+-- SUB end
+
+-- SUBL begin
+--X"50F400",
+--X"000000",
+--X"54F400",
+--X"000001",
+--X"20001B",
+--X"51F400",
+--X"000001",
+--X"0000B9",
+--X"0001F9",
+--X"20001E",
+--X"54F400",
+--X"800000",
+--X"53F400",
+--X"000080",
+--X"20001E",
+--X"20001B",
+--X"53F400",
+--X"000080",
+--X"54F400",
+--X"000001",
+--X"20001E",
+-- SUBL end
+
+-- SUBR begin
+--X"50F400",
+--X"000000",
+--X"54F400",
+--X"000001",
+--X"20001B",
+--X"51F400",
+--X"000001",
+--X"0000B9",
+--X"0001F9",
+--X"20000E",
+--X"54F400",
+--X"800000",
+--X"53F400",
+--X"000080",
+--X"20000E",
+--X"20001B",
+--X"53F400",
+--X"000080",
+--X"54F400",
+--X"000001",
+--X"20000E",
+-- SUBR end
+
+-- SBC begin
+--X"46F400",
+--X"000000",
+--X"47F400",
+--X"000001",
+--X"20001B",
+--X"51F400",
+--X"000001",
+--X"0000B9",
+--X"0001F9",
+--X"20003D",
+--X"47F400",
+--X"800000",
+--X"53F400",
+--X"000080",
+--X"20003D",
+--X"20001B",
+--X"53F400",
+--X"000080",
+--X"47F400",
+--X"000001",
+--X"20003D",
+-- SBC end
+
+-- TCC begin
+--X"311400",
+--X"44F400",
+--X"ABCDEF",
+--X"57F400",
+--X"123456",
+--X"0000B9",
+--X"038143",
+--X"03014A",
+--X"0004F9",
+--X"03A143",
+--X"03214A",
+-- TCC end
+
+-- TFR begin
+--X"56F400",
+--X"ABCDEF",
+--X"57F400",
+--X"123456",
+--X"21EE09",
+--X"44F400",
+--X"555555",
+--X"47F400",
+--X"AAAAAA",
+--X"21C441",
+--X"21E679",
+-- TFR end
+
+-- TST begin
+--X"20001B",
+--X"20000B",
+--X"0000B9",
+--X"0001F9",
+--X"53F400",
+--X"000080",
+--X"20000B",
+--X"53F400",
+--X"00007F",
+--X"20000B",
+-- TST end
+
+
+--X"2AFF00",
+--X"54F400",
+--X"FFFFFF",
+--X"50F400",
+--X"FFFFF2",
+--X"200026",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+X"000000",
+X"000000",
+X"000000",
+X"000000",
+X"000000",
+X"000000",
+X"000000",
+X"000000",
+X"000000",
+--X"44F400",
+--X"100010",
+--X"45F400",
+--X"100011",
+--X"0B5880",
+--X"000017",
+--X"46F400",
+--X"100026",
+--X"47F400",
+--X"100027",
+--X"425800",
+--X"435800",
+--X"420A00",
+--X"431F00",
+--X"437000",
+--X"0000A0",
+--X"427000",
+--X"00004F",
+--  X"42F800",
+--  X"43F800",
+--  X"428A00",
+--  X"439F00",
+--	"001100000100100000000000",  -- 0 move #72,r0
+--	"001110000000100000000000",  -- 1 move #8,n0
+--	"000001010000000010100000",  -- 2 move #0,m0
+--	"000001010001000010100001",  -- 3 move #16,m1
+--	"000001101110000100100000",  -- 4 rep m1
+--	"010001001100100000000000",  -- 5 move x:(r0)+n0,x0
+--	"000000000000000000000000",  -- 6
+--	"000000000000000000000000",  -- 7
+--	"000000000000000000000000",  -- 8
+--	"000000000000000000000000",  -- 9 
+--	"000000000000000000000000",  -- 10
+--	"000000000000000000000000",  -- 11
+--	"000000000000000000000000",  -- 12
+--	"000000000000000000000000",  -- 13
+--	"000000000000000000000000",  -- 14
+--	"000000000000000000000000",  -- 15
+--	"000000000000000000000000",  -- 16
+--	"000000000000000000000000",  -- 17
+--	"000000000000000000000000",  -- 18
+--	"000000000000000000000000",  -- 19
+--	"000010101101101010000000",  -- 20 -- JMP (r2)+
+--	"000000000000000000000000",  -- 20
+--	"000000000000000000000000",  -- 21
+--	"000000000000000000000000",  -- 22
+	"000000000000000000000000",  -- 23
+	"000000000000000000000000",  -- 24
+	"000000000000000000000000",  -- 25
+	"000000000000000000000000",  -- 26
+	"000000000000000000000000",  -- 27
+	"000000000000000000000000",  -- 28
+	"000000000000000000000000",  -- 29
+	"000000000000000000000000",  -- 30
+	"000000000000000000000000",  -- 31
+--	"000000000000000000000000",  -- 32
+--	"000011010000000000000000",  -- 32 -- JSR #0
+	"000010111111000010000000",  -- 32 -- JSR absolute
+	"000000000000000001000000",  -- 33 -- #64
+	"000000000000000000000000",  -- 34
+	"000000000000000000000000",  -- 35
+	"000000000000000000000000",  -- 36
+	"000000000000000000000000",  -- 37
+	"000000000000000000000000",  -- 38
+	"000000000000000000000000",  -- 39
+	"000000000000000000000000",  -- 40
+	"000000000000000000000000",  -- 41
+	"000000000000000000000000",  -- 42
+	"000000000000000000000000",  -- 43
+	"000000000000000000000000",  -- 44
+	"000000000000000000000000",  -- 45
+	"000000000000000000000000",  -- 46
+	"000000000000000000000000",  -- 47
+	"000000000000000000000000",  -- 48
+	"000000000000000000000000",  -- 49
+	"000000000000000000000000",  -- 50
+	"000000000000000000000000",  -- 51
+	"000000000000000000000000",  -- 52
+	"000000000000000000000000",  -- 53
+	"000000000000000000000000",  -- 54
+	"000000000000000000000000",  -- 55
+	"000000000000000000000000",  -- 56
+	"000000000000000000000000",  -- 57
+	"000000000000000000000000",  -- 58
+	"000000000000000000000000",  -- 59
+	"000000000000000000000000",  -- 60
+	"000000000000000000000000",  -- 61
+	"000000000000000000000000",  -- 62
+	"000000000000000000000000",  -- 63
+	"000000000000000000000000",  -- 64
+	"000000000000000000000000",  -- 65
+	"000000000000000000000000",  -- 66
+	"000000000000000000000000",  -- 67
+	"000000000000000000000000",  -- 68
+	"000000000000000000000000",  -- 69
+	"000000000000000000000100",  -- 70 -- RTI
+	"000000000000000000000000",  -- 71
+	"000000000000000000000000",  -- 72
+	"000000000000000000000000",  -- 73
+	"000000000000000000000000",  -- 74
+	"000000000000000000000000",  -- 75
+	"000000000000000000000000",  -- 76
+	"000000000000000000000000",  -- 77
+	"000000000000000000000000",  -- 78
+	"000000000000000000000000",  -- 79
+	"000000000000000000000000",  -- 80
+	"000000000000000000000000",  -- 81
+	"000000000000000000000000",  -- 82
+	"000000000000000000000000",  -- 83
+	"000000000000000000000000",  -- 84
+	"000000000000000000000000",  -- 85
+	"000000000000000000000000",  -- 86
+	"000000000000000000000000",  -- 87
+	"000000000000000000000000",  -- 88
+	"000000000000000000000000",  -- 89
+	"000000000000000000000000",  -- 90
+	"000000000000000000000000",  -- 91
+	"000000000000000000000000",  -- 92
+	"000000000000000000000000",  -- 93
+	"000000000000000000000000",  -- 94
+	"000000000000000000000000",  -- 95
+	"000000000000000000000000",  -- 96
+	"000000000000000000000000",  -- 97
+	"000000000000000000000000",  -- 98
+	"000000000000000000000000",  -- 99
+	"000000000000000000000000",  -- 100
+	"000000000000000000000000",  -- 101
+	"000000000000000000000000",  -- 102
+	"000000000000000000000000",  -- 103
+	"000000000000000000000000",  -- 104
+	"000000000000000000000000",  -- 105
+	"000000000000000000000000",  -- 106
+	"000000000000000000000000",  -- 107
+	"000000000000000000000000",  -- 108
+	"000000000000000000000000",  -- 109
+	"000000000000000000000000",  -- 110
+	"000000000000000000000000",  -- 111
+	"000000000000000000000000",  -- 112
+	"000000000000000000000000",  -- 113
+	"000000000000000000000000",  -- 114
+	"000000000000000000000000",  -- 115
+	"000000000000000000000000",  -- 116
+	"000000000000000000000000",  -- 117
+	"000000000000000000000000",  -- 118
+	"000000000000000000000000",  -- 119
+	"000000000000000000000000",  -- 120
+	"000000000000000000000000",  -- 121
+	"000000000000000000000000",  -- 122
+	"000000000000000000000000",  -- 123
+	"000000000000000000000000",  -- 124
+	"000000000000000000000000",  -- 125
+	"000000000000000000000000",  -- 126
+	"000000000000000000000000",  -- 127
+	"000000000000000000000000",  -- 128
+	"000000000000000000000000",  -- 129
+	"000000000000000000000000",  -- 130
+	"000000000000000000000000",  -- 131
+	"000000000000000000000000",  -- 132
+	"000000000000000000000000",  -- 133
+	"000000000000000000000000",  -- 134
+	"000000000000000000000000",  -- 135
+	"000000000000000000000000",  -- 136
+	"000000000000000000000000",  -- 137
+	"000000000000000000000000",  -- 138
+	"000000000000000000000000",  -- 139
+	"000000000000000000000000",  -- 140
+	"000000000000000000000000",  -- 141
+	"000000000000000000000000",  -- 142
+	"000000000000000000000000",  -- 143
+	"000000000000000000000000",  -- 144
+	"000000000000000000000000",  -- 145
+	"000000000000000000000000",  -- 146
+	"000000000000000000000000",  -- 147
+	"000000000000000000000000",  -- 148
+	"000000000000000000000000",  -- 149
+	"000000000000000000000000",  -- 150
+	"000000000000000000000000",  -- 151
+	"000000000000000000000000",  -- 152
+	"000000000000000000000000",  -- 153
+	"000000000000000000000000",  -- 154
+	"000000000000000000000000",  -- 155
+	"000000000000000000000000",  -- 156
+	"000000000000000000000000",  -- 157
+	"000000000000000000000000",  -- 158
+	"000000000000000000000000",  -- 159
+	"000000000000000000000000",  -- 160
+	"000000000000000000000000",  -- 161
+	"000000000000000000000000",  -- 162
+	"000000000000000000000000",  -- 163
+	"000000000000000000000000",  -- 164
+	"000000000000000000000000",  -- 165
+	"000000000000000000000000",  -- 166
+	"000000000000000000000000",  -- 167
+	"000000000000000000000000",  -- 168
+	"000000000000000000000000",  -- 169
+	"000000000000000000000000",  -- 170
+	"000000000000000000000000",  -- 171
+	"000000000000000000000000",  -- 172
+	"000000000000000000000000",  -- 173
+	"000000000000000000000000",  -- 174
+	"000000000000000000000000",  -- 175
+	"000000000000000000000000",  -- 176
+	"000000000000000000000000",  -- 177
+	"000000000000000000000000",  -- 178
+	"000000000000000000000000",  -- 179
+	"000000000000000000000000",  -- 180
+	"000000000000000000000000",  -- 181
+	"000000000000000000000000",  -- 182
+	"000000000000000000000000",  -- 183
+	"000000000000000000000000",  -- 184
+	"000000000000000000000000",  -- 185
+	"000000000000000000000000",  -- 186
+	"000000000000000000000000",  -- 187
+	"000000000000000000000000",  -- 188
+	"000000000000000000000000",  -- 189
+	"000000000000000000000000",  -- 190
+	"000000000000000000000000",  -- 191
+	"000000000000000000000000",  -- 192
+	"000000000000000000000000",  -- 193
+	"000000000000000000000000",  -- 194
+	"000000000000000000000000",  -- 195
+	"000000000000000000000000",  -- 196
+	"000000000000000000000000",  -- 197
+	"000000000000000000000000",  -- 198
+	"000000000000000000000000",  -- 199
+	"000000000000000000000000",  -- 200
+	"000000000000000000000000",  -- 201
+	"000000000000000000000000",  -- 202
+	"000000000000000000000000",  -- 203
+	"000000000000000000000000",  -- 204
+	"000000000000000000000000",  -- 205
+	"000000000000000000000000",  -- 206
+	"000000000000000000000000",  -- 207
+	"000000000000000000000000",  -- 208
+	"000000000000000000000000",  -- 209
+	"000000000000000000000000",  -- 210
+	"000000000000000000000000",  -- 211
+	"000000000000000000000000",  -- 212
+	"000000000000000000000000",  -- 213
+	"000000000000000000000000",  -- 214
+	"000000000000000000000000",  -- 215
+	"000000000000000000000000",  -- 216
+	"000000000000000000000000",  -- 217
+	"000000000000000000000000",  -- 218
+	"000000000000000000000000",  -- 219
+	"000000000000000000000000",  -- 220
+	"000000000000000000000000",  -- 221
+	"000000000000000000000000",  -- 222
+	"000000000000000000000000",  -- 223
+	"000000000000000000000000",  -- 224
+	"000000000000000000000000",  -- 225
+	"000000000000000000000000",  -- 226
+	"000000000000000000000000",  -- 227
+	"000000000000000000000000",  -- 228
+	"000000000000000000000000",  -- 229
+	"000000000000000000000000",  -- 230
+	"000000000000000000000000",  -- 231
+	"000000000000000000000000",  -- 232
+	"000000000000000000000000",  -- 233
+	"000000000000000000000000",  -- 234
+	"000000000000000000000000",  -- 235
+	"000000000000000000000000",  -- 236
+	"000000000000000000000000",  -- 237
+	"000000000000000000000000",  -- 238
+	"000000000000000000000000",  -- 239
+	"000000000000000000000000",  -- 240
+	"000000000000000000000000",  -- 241
+	"000000000000000000000000",  -- 242
+	"000000000000000000000000",  -- 243
+	"000000000000000000000000",  -- 244
+	"000000000000000000000000",  -- 245
+	"000000000000000000000000",  -- 246
+	"000000000000000000000000",  -- 247
+	"000000000000000000000000",  -- 248
+	"000000000000000000000000",  -- 249
+	"000000000000000000000000",  -- 250
+	"000000000000000000000000",  -- 251
+	"000000000000000000000000",  -- 252
+	"000000000000000000000000",  -- 253
+	"000000000000000000000000",  -- 254
+	"000000000000000000000000");  -- 255
+	signal int_xmem : int_mem_type := (
+--						when "11------10000000" => instr_array(JMP_INSTR)  <= '1';
+--	"000000000000111011111001",  -- 0 -- ORI #$0E, CCR
+	"000000000000000000001100",  -- 0 -- REP
+	"000000000000000000000101",  -- 1 -- ORI #$0E, MR
+	"000000000000111011111010",  -- 2 -- ORI #$0E, OMR
+	"000000000000100010111010",  -- 3 -- ANDI #$08, OMR
+--	"000010101111000010000000",  -- 1 -- JMP absolute
+--	"000000000000000000011111",  -- 2 -- #31
+--	"000011000000000000010000",  -- 3 -- JMP #16
+	"000000000000000000000000",  -- 4
+	"000000000000000000000000",  -- 5
+	"000000000000000000000000",  -- 6
+	"000000000000000000000000",  -- 7
+	"000000000000000000000000",  -- 8
+	"000000000000000000000000",  -- 9
+	"000000000000000000000000",  -- 10
+	"000000000000000000000000",  -- 11
+	"000000000000000000000000",  -- 12
+	"000000000000000000000000",  -- 13
+	"000000000000000000000000",  -- 14
+	"000000000000000000000000",  -- 15
+	"000000000000000000000000",  -- 16
+--	"000000000000000000000000",  -- 17
+	"000010101101010110100000",  -- 17 -- JCC (r5)-
+	"000000000000000000000000",  -- 18
+	"000000000000000000000000",  -- 19
+	"000010101101101010000000",  -- 20 -- JMP (r2)+
+	"000000000000000000000000",  -- 21
+	"000000000000000000000000",  -- 22
+	"000000000000000000000000",  -- 23
+	"000000000000000000000000",  -- 24
+	"000000000000000000000000",  -- 25
+	"000000000000000000000000",  -- 26
+	"000000000000000000000000",  -- 27
+	"000000000000000000000000",  -- 28
+	"000000000000000000000000",  -- 29
+	"000000000000000000000000",  -- 30
+	"000000000000000000000000",  -- 31
+--	"000000000000000000000000",  -- 32
+--	"000011010000000000000000",  -- 32 -- JSR #0
+	"000010111111000010000000",  -- 32 -- JSR absolute
+	"000000000000000001000000",  -- 33 -- #64
+	"000000000000000000000000",  -- 34
+	"000000000000000000000000",  -- 35
+	"000000000000000000000000",  -- 36
+	"000000000000000000000000",  -- 37
+	"000000000000000000000000",  -- 38
+	"000000000000000000000000",  -- 39
+	"000000000000000000000000",  -- 40
+	"000000000000000000000000",  -- 41
+	"000000000000000000000000",  -- 42
+	"000000000000000000000000",  -- 43
+	"000000000000000000000000",  -- 44
+	"000000000000000000000000",  -- 45
+	"000000000000000000000000",  -- 46
+	"000000000000000000000000",  -- 47
+	"000000000000000000000000",  -- 48
+	"000000000000000000000000",  -- 49
+	"000000000000000000000000",  -- 50
+	"000000000000000000000000",  -- 51
+	"000000000000000000000000",  -- 52
+	"000000000000000000000000",  -- 53
+	"000000000000000000000000",  -- 54
+	"000000000000000000000000",  -- 55
+	"000000000000000000000000",  -- 56
+	"000000000000000000000000",  -- 57
+	"000000000000000000000000",  -- 58
+	"000000000000000000000000",  -- 59
+	"000000000000000000000000",  -- 60
+	"000000000000000000000000",  -- 61
+	"000000000000000000000000",  -- 62
+	"000000000000000000000000",  -- 63
+	"000000000000000000000000",  -- 64
+	"000000000000000000000000",  -- 65
+	"000000000000000000000000",  -- 66
+	"000000000000000000000000",  -- 67
+	"000000000000000000000000",  -- 68
+	"000000000000000000000000",  -- 69
+	"000000000000000000000100",  -- 70 -- RTI
+	"000000000000000000000000",  -- 71
+	"000000000000000000000000",  -- 72
+	"000000000000000000000000",  -- 73
+	"000000000000000000000000",  -- 74
+	"000000000000000000000000",  -- 75
+	"000000000000000000000000",  -- 76
+	"000000000000000000000000",  -- 77
+	"000000000000000000000000",  -- 78
+	"000000000000000000000000",  -- 79
+	"000000000000000000000000",  -- 80
+	"000000000000000000000000",  -- 81
+	"000000000000000000000000",  -- 82
+	"000000000000000000000000",  -- 83
+	"000000000000000000000000",  -- 84
+	"000000000000000000000000",  -- 85
+	"000000000000000000000000",  -- 86
+	"000000000000000000000000",  -- 87
+	"000000000000000000000000",  -- 88
+	"000000000000000000000000",  -- 89
+	"000000000000000000000000",  -- 90
+	"000000000000000000000000",  -- 91
+	"000000000000000000000000",  -- 92
+	"000000000000000000000000",  -- 93
+	"000000000000000000000000",  -- 94
+	"000000000000000000000000",  -- 95
+	"000000000000000000000000",  -- 96
+	"000000000000000000000000",  -- 97
+	"000000000000000000000000",  -- 98
+	"000000000000000000000000",  -- 99
+	"000000000000000000000000",  -- 100
+	"000000000000000000000000",  -- 101
+	"000000000000000000000000",  -- 102
+	"000000000000000000000000",  -- 103
+	"000000000000000000000000",  -- 104
+	"000000000000000000000000",  -- 105
+	"000000000000000000000000",  -- 106
+	"000000000000000000000000",  -- 107
+	"000000000000000000000000",  -- 108
+	"000000000000000000000000",  -- 109
+	"000000000000000000000000",  -- 110
+	"000000000000000000000000",  -- 111
+	"000000000000000000000000",  -- 112
+	"000000000000000000000000",  -- 113
+	"000000000000000000000000",  -- 114
+	"000000000000000000000000",  -- 115
+	"000000000000000000000000",  -- 116
+	"000000000000000000000000",  -- 117
+	"000000000000000000000000",  -- 118
+	"000000000000000000000000",  -- 119
+	"000000000000000000000000",  -- 120
+	"000000000000000000000000",  -- 121
+	"000000000000000000000000",  -- 122
+	"000000000000000000000000",  -- 123
+	"000000000000000000000000",  -- 124
+	"000000000000000000000000",  -- 125
+	"000000000000000000000000",  -- 126
+	"000000000000000000000000",  -- 127
+	"000000000000000000000000",  -- 128
+	"000000000000000000000000",  -- 129
+	"000000000000000000000000",  -- 130
+	"000000000000000000000000",  -- 131
+	"000000000000000000000000",  -- 132
+	"000000000000000000000000",  -- 133
+	"000000000000000000000000",  -- 134
+	"000000000000000000000000",  -- 135
+	"000000000000000000000000",  -- 136
+	"000000000000000000000000",  -- 137
+	"000000000000000000000000",  -- 138
+	"000000000000000000000000",  -- 139
+	"000000000000000000000000",  -- 140
+	"000000000000000000000000",  -- 141
+	"000000000000000000000000",  -- 142
+	"000000000000000000000000",  -- 143
+	"000000000000000000000000",  -- 144
+	"000000000000000000000000",  -- 145
+	"000000000000000000000000",  -- 146
+	"000000000000000000000000",  -- 147
+	"000000000000000000000000",  -- 148
+	"000000000000000000000000",  -- 149
+	"000000000000000000000000",  -- 150
+	"000000000000000000000000",  -- 151
+	"000000000000000000000000",  -- 152
+	"000000000000000000000000",  -- 153
+	"000000000000000000000000",  -- 154
+	"000000000000000000000000",  -- 155
+	"000000000000000000000000",  -- 156
+	"000000000000000000000000",  -- 157
+	"000000000000000000000000",  -- 158
+	"000000000000000000000000",  -- 159
+	"000000000000000000000000",  -- 160
+	"000000000000000000000000",  -- 161
+	"000000000000000000000000",  -- 162
+	"000000000000000000000000",  -- 163
+	"000000000000000000000000",  -- 164
+	"000000000000000000000000",  -- 165
+	"000000000000000000000000",  -- 166
+	"000000000000000000000000",  -- 167
+	"000000000000000000000000",  -- 168
+	"000000000000000000000000",  -- 169
+	"000000000000000000000000",  -- 170
+	"000000000000000000000000",  -- 171
+	"000000000000000000000000",  -- 172
+	"000000000000000000000000",  -- 173
+	"000000000000000000000000",  -- 174
+	"000000000000000000000000",  -- 175
+	"000000000000000000000000",  -- 176
+	"000000000000000000000000",  -- 177
+	"000000000000000000000000",  -- 178
+	"000000000000000000000000",  -- 179
+	"000000000000000000000000",  -- 180
+	"000000000000000000000000",  -- 181
+	"000000000000000000000000",  -- 182
+	"000000000000000000000000",  -- 183
+	"000000000000000000000000",  -- 184
+	"000000000000000000000000",  -- 185
+	"000000000000000000000000",  -- 186
+	"000000000000000000000000",  -- 187
+	"000000000000000000000000",  -- 188
+	"000000000000000000000000",  -- 189
+	"000000000000000000000000",  -- 190
+	"000000000000000000000000",  -- 191
+	"000000000000000000000000",  -- 192
+	"000000000000000000000000",  -- 193
+	"000000000000000000000000",  -- 194
+	"000000000000000000000000",  -- 195
+	"000000000000000000000000",  -- 196
+	"000000000000000000000000",  -- 197
+	"000000000000000000000000",  -- 198
+	"000000000000000000000000",  -- 199
+	"000000000000000000000000",  -- 200
+	"000000000000000000000000",  -- 201
+	"000000000000000000000000",  -- 202
+	"000000000000000000000000",  -- 203
+	"000000000000000000000000",  -- 204
+	"000000000000000000000000",  -- 205
+	"000000000000000000000000",  -- 206
+	"000000000000000000000000",  -- 207
+	"000000000000000000000000",  -- 208
+	"000000000000000000000000",  -- 209
+	"000000000000000000000000",  -- 210
+	"000000000000000000000000",  -- 211
+	"000000000000000000000000",  -- 212
+	"000000000000000000000000",  -- 213
+	"000000000000000000000000",  -- 214
+	"000000000000000000000000",  -- 215
+	"000000000000000000000000",  -- 216
+	"000000000000000000000000",  -- 217
+	"000000000000000000000000",  -- 218
+	"000000000000000000000000",  -- 219
+	"000000000000000000000000",  -- 220
+	"000000000000000000000000",  -- 221
+	"000000000000000000000000",  -- 222
+	"000000000000000000000000",  -- 223
+	"000000000000000000000000",  -- 224
+	"000000000000000000000000",  -- 225
+	"000000000000000000000000",  -- 226
+	"000000000000000000000000",  -- 227
+	"000000000000000000000000",  -- 228
+	"000000000000000000000000",  -- 229
+	"000000000000000000000000",  -- 230
+	"000000000000000000000000",  -- 231
+	"000000000000000000000000",  -- 232
+	"000000000000000000000000",  -- 233
+	"000000000000000000000000",  -- 234
+	"000000000000000000000000",  -- 235
+	"000000000000000000000000",  -- 236
+	"000000000000000000000000",  -- 237
+	"000000000000000000000000",  -- 238
+	"000000000000000000000000",  -- 239
+	"000000000000000000000000",  -- 240
+	"000000000000000000000000",  -- 241
+	"000000000000000000000000",  -- 242
+	"000000000000000000000000",  -- 243
+	"000000000000000000000000",  -- 244
+	"000000000000000000000000",  -- 245
+	"000000000000000000000000",  -- 246
+	"000000000000000000000000",  -- 247
+	"000000000000000000000000",  -- 248
+	"000000000000000000000000",  -- 249
+	"000000000000000000000000",  -- 250
+	"000000000000000000000000",  -- 251
+	"000000000000000000000000",  -- 252
+	"000000000000000000000000",  -- 253
+	"000000000000000000000000",  -- 254
+	"000000000000000000000000");  -- 255
+	signal int_ymem : int_mem_type := (
+--						when "11------10000000" => instr_array(JMP_INSTR)  <= '1';
+--	"000000000000111011111001",  -- 0 -- ORI #$0E, CCR
+	"000000000000000000000001",  -- 0 -- REP
+	"000000000000000000000010",  -- 1 -- ORI #$0E, MR
+	"000000000000000000000011",  -- 2 -- ORI #$0E, OMR
+	"000000000000000000000100",  -- 3 -- ANDI #$08, OMR
+--	"000010101111000010000000",  -- 1 -- JMP absolute
+--	"000000000000000000011111",  -- 2 -- #31
+--	"000011000000000000010000",  -- 3 -- JMP #16
+	"000000000000000000000101",  -- 4
+	"000000000000000000000110",  -- 5
+	"000000000000000000000111",  -- 6
+	"000000000000000000001000",  -- 7
+	"000000000000000000001001",  -- 8
+	"000000000000000000001010",  -- 9
+	"000000000000000000001011",  -- 10
+	"000000000000000000001100",  -- 11
+	"000000000000000000001101",  -- 12
+	"000000000000000000001110",  -- 13
+	"000000000000000000001111",  -- 14
+	"000000000000000000010000",  -- 15
+	"000000000000000000010001",  -- 16
+--	"000000000000000000000000",  -- 17
+	"000010101101010110100000",  -- 17 -- JCC (r5)-
+	"000000000000000000000000",  -- 18
+	"000000000000000000000000",  -- 19
+	"000010101101101010000000",  -- 20 -- JMP (r2)+
+	"000000000000000000000000",  -- 21
+	"000000000000000000000000",  -- 22
+	"000000000000000000000000",  -- 23
+	"000000000000000000000000",  -- 24
+	"000000000000000000000000",  -- 25
+	"000000000000000000000000",  -- 26
+	"000000000000000000000000",  -- 27
+	"000000000000000000000000",  -- 28
+	"000000000000000000000000",  -- 29
+	"000000000000000000000000",  -- 30
+	"000000000000000000000000",  -- 31
+--	"000000000000000000000000",  -- 32
+--	"000011010000000000000000",  -- 32 -- JSR #0
+	"000010111111000010000000",  -- 32 -- JSR absolute
+	"000000000000000001000000",  -- 33 -- #64
+	"000000000000000000000000",  -- 34
+	"000000000000000000000000",  -- 35
+	"000000000000000000000000",  -- 36
+	"000000000000000000000000",  -- 37
+	"000000000000000000000000",  -- 38
+	"000000000000000000000000",  -- 39
+	"000000000000000000000000",  -- 40
+	"000000000000000000000000",  -- 41
+	"000000000000000000000000",  -- 42
+	"000000000000000000000000",  -- 43
+	"000000000000000000000000",  -- 44
+	"000000000000000000000000",  -- 45
+	"000000000000000000000000",  -- 46
+	"000000000000000000000000",  -- 47
+	"000000000000000000000000",  -- 48
+	"000000000000000000000000",  -- 49
+	"000000000000000000000000",  -- 50
+	"000000000000000000000000",  -- 51
+	"000000000000000000000000",  -- 52
+	"000000000000000000000000",  -- 53
+	"000000000000000000000000",  -- 54
+	"000000000000000000000000",  -- 55
+	"000000000000000000000000",  -- 56
+	"000000000000000000000000",  -- 57
+	"000000000000000000000000",  -- 58
+	"000000000000000000000000",  -- 59
+	"000000000000000000000000",  -- 60
+	"000000000000000000000000",  -- 61
+	"000000000000000000000000",  -- 62
+	"000000000000000000000000",  -- 63
+	"000000000000000000000000",  -- 64
+	"000000000000000000000000",  -- 65
+	"000000000000000000000000",  -- 66
+	"000000000000000000000000",  -- 67
+	"000000000000000000000000",  -- 68
+	"000000000000000000000000",  -- 69
+	"000000000000000000000100",  -- 70 -- RTI
+	"000000000000000000000000",  -- 71
+	"000000000000000000000000",  -- 72
+	"000000000000000000000000",  -- 73
+	"000000000000000000000000",  -- 74
+	"000000000000000000000000",  -- 75
+	"000000000000000000000000",  -- 76
+	"000000000000000000000000",  -- 77
+	"000000000000000000000000",  -- 78
+	"000000000000000000000000",  -- 79
+	"000000000000000000000000",  -- 80
+	"000000000000000000000000",  -- 81
+	"000000000000000000000000",  -- 82
+	"000000000000000000000000",  -- 83
+	"000000000000000000000000",  -- 84
+	"000000000000000000000000",  -- 85
+	"000000000000000000000000",  -- 86
+	"000000000000000000000000",  -- 87
+	"000000000000000000000000",  -- 88
+	"000000000000000000000000",  -- 89
+	"000000000000000000000000",  -- 90
+	"000000000000000000000000",  -- 91
+	"000000000000000000000000",  -- 92
+	"000000000000000000000000",  -- 93
+	"000000000000000000000000",  -- 94
+	"000000000000000000000000",  -- 95
+	"000000000000000000000000",  -- 96
+	"000000000000000000000000",  -- 97
+	"000000000000000000000000",  -- 98
+	"000000000000000000000000",  -- 99
+	"000000000000000000000000",  -- 100
+	"000000000000000000000000",  -- 101
+	"000000000000000000000000",  -- 102
+	"000000000000000000000000",  -- 103
+	"000000000000000000000000",  -- 104
+	"000000000000000000000000",  -- 105
+	"000000000000000000000000",  -- 106
+	"000000000000000000000000",  -- 107
+	"000000000000000000000000",  -- 108
+	"000000000000000000000000",  -- 109
+	"000000000000000000000000",  -- 110
+	"000000000000000000000000",  -- 111
+	"000000000000000000000000",  -- 112
+	"000000000000000000000000",  -- 113
+	"000000000000000000000000",  -- 114
+	"000000000000000000000000",  -- 115
+	"000000000000000000000000",  -- 116
+	"000000000000000000000000",  -- 117
+	"000000000000000000000000",  -- 118
+	"000000000000000000000000",  -- 119
+	"000000000000000000000000",  -- 120
+	"000000000000000000000000",  -- 121
+	"000000000000000000000000",  -- 122
+	"000000000000000000000000",  -- 123
+	"000000000000000000000000",  -- 124
+	"000000000000000000000000",  -- 125
+	"000000000000000000000000",  -- 126
+	"000000000000000000000000",  -- 127
+	"000000000000000000000000",  -- 128
+	"000000000000000000000000",  -- 129
+	"000000000000000000000000",  -- 130
+	"000000000000000000000000",  -- 131
+	"000000000000000000000000",  -- 132
+	"000000000000000000000000",  -- 133
+	"000000000000000000000000",  -- 134
+	"000000000000000000000000",  -- 135
+	"000000000000000000000000",  -- 136
+	"000000000000000000000000",  -- 137
+	"000000000000000000000000",  -- 138
+	"000000000000000000000000",  -- 139
+	"000000000000000000000000",  -- 140
+	"000000000000000000000000",  -- 141
+	"000000000000000000000000",  -- 142
+	"000000000000000000000000",  -- 143
+	"000000000000000000000000",  -- 144
+	"000000000000000000000000",  -- 145
+	"000000000000000000000000",  -- 146
+	"000000000000000000000000",  -- 147
+	"000000000000000000000000",  -- 148
+	"000000000000000000000000",  -- 149
+	"000000000000000000000000",  -- 150
+	"000000000000000000000000",  -- 151
+	"000000000000000000000000",  -- 152
+	"000000000000000000000000",  -- 153
+	"000000000000000000000000",  -- 154
+	"000000000000000000000000",  -- 155
+	"000000000000000000000000",  -- 156
+	"000000000000000000000000",  -- 157
+	"000000000000000000000000",  -- 158
+	"000000000000000000000000",  -- 159
+	"000000000000000000000000",  -- 160
+	"000000000000000000000000",  -- 161
+	"000000000000000000000000",  -- 162
+	"000000000000000000000000",  -- 163
+	"000000000000000000000000",  -- 164
+	"000000000000000000000000",  -- 165
+	"000000000000000000000000",  -- 166
+	"000000000000000000000000",  -- 167
+	"000000000000000000000000",  -- 168
+	"000000000000000000000000",  -- 169
+	"000000000000000000000000",  -- 170
+	"000000000000000000000000",  -- 171
+	"000000000000000000000000",  -- 172
+	"000000000000000000000000",  -- 173
+	"000000000000000000000000",  -- 174
+	"000000000000000000000000",  -- 175
+	"000000000000000000000000",  -- 176
+	"000000000000000000000000",  -- 177
+	"000000000000000000000000",  -- 178
+	"000000000000000000000000",  -- 179
+	"000000000000000000000000",  -- 180
+	"000000000000000000000000",  -- 181
+	"000000000000000000000000",  -- 182
+	"000000000000000000000000",  -- 183
+	"000000000000000000000000",  -- 184
+	"000000000000000000000000",  -- 185
+	"000000000000000000000000",  -- 186
+	"000000000000000000000000",  -- 187
+	"000000000000000000000000",  -- 188
+	"000000000000000000000000",  -- 189
+	"000000000000000000000000",  -- 190
+	"000000000000000000000000",  -- 191
+	"000000000000000000000000",  -- 192
+	"000000000000000000000000",  -- 193
+	"000000000000000000000000",  -- 194
+	"000000000000000000000000",  -- 195
+	"000000000000000000000000",  -- 196
+	"000000000000000000000000",  -- 197
+	"000000000000000000000000",  -- 198
+	"000000000000000000000000",  -- 199
+	"000000000000000000000000",  -- 200
+	"000000000000000000000000",  -- 201
+	"000000000000000000000000",  -- 202
+	"000000000000000000000000",  -- 203
+	"000000000000000000000000",  -- 204
+	"000000000000000000000000",  -- 205
+	"000000000000000000000000",  -- 206
+	"000000000000000000000000",  -- 207
+	"000000000000000000000000",  -- 208
+	"000000000000000000000000",  -- 209
+	"000000000000000000000000",  -- 210
+	"000000000000000000000000",  -- 211
+	"000000000000000000000000",  -- 212
+	"000000000000000000000000",  -- 213
+	"000000000000000000000000",  -- 214
+	"000000000000000000000000",  -- 215
+	"000000000000000000000000",  -- 216
+	"000000000000000000000000",  -- 217
+	"000000000000000000000000",  -- 218
+	"000000000000000000000000",  -- 219
+	"000000000000000000000000",  -- 220
+	"000000000000000000000000",  -- 221
+	"000000000000000000000000",  -- 222
+	"000000000000000000000000",  -- 223
+	"000000000000000000000000",  -- 224
+	"000000000000000000000000",  -- 225
+	"000000000000000000000000",  -- 226
+	"000000000000000000000000",  -- 227
+	"000000000000000000000000",  -- 228
+	"000000000000000000000000",  -- 229
+	"000000000000000000000000",  -- 230
+	"000000000000000000000000",  -- 231
+	"000000000000000000000000",  -- 232
+	"000000000000000000000000",  -- 233
+	"000000000000000000000000",  -- 234
+	"000000000000000000000000",  -- 235
+	"000000000000000000000000",  -- 236
+	"000000000000000000000000",  -- 237
+	"000000000000000000000000",  -- 238
+	"000000000000000000000000",  -- 239
+	"000000000000000000000000",  -- 240
+	"000000000000000000000000",  -- 241
+	"000000000000000000000000",  -- 242
+	"000000000000000000000000",  -- 243
+	"000000000000000000000000",  -- 244
+	"000000000000000000000000",  -- 245
+	"000000000000000000000000",  -- 246
+	"000000000000000000000000",  -- 247
+	"000000000000000000000000",  -- 248
+	"000000000000000000000000",  -- 249
+	"000000000000000000000000",  -- 250
+	"000000000000000000000000",  -- 251
+	"000000000000000000000000",  -- 252
+	"000000000000000000000000",  -- 253
+	"000000000000000000000000",  -- 254
+	"000000000000000000000000");  -- 255
+
+begin
+
+--	int_mem <= int_pmem when mem_type = P_MEM else
+--	           int_xmem when mem_type = X_MEM else
+--	           int_ymem when mem_type = Y_MEM;
+
+	wr_accomplished <= wr_en;
+
+	PMEM_GEN: if mem_type = P_MEM generate
+		data_out <= int_pmem(to_integer(unsigned(int_mem_rd_addr)));
+		process(clk) is
+		begin
+			if rising_edge(clk) then
+--				if rst = '1' then
+--					data_out_valid <= '0';
+--					int_mem_rd_addr <= (others => '0');
+--				else
+					int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0));
+					data_out_valid <= rd_en;
+					if wr_en = '1' then
+							int_pmem(to_integer(wr_addr)) <= data_in;
+					end if;
+--				end if;
+			end if;
+		end process;
+	end generate;
+
+	XMEM_GEN: if mem_type = X_MEM generate
+		data_out <= int_xmem(to_integer(unsigned(int_mem_rd_addr)));
+		process(clk) is
+		begin
+			if rising_edge(clk) then
+--				if rst = '1' then
+--					data_out_valid <= '0';
+--					int_mem_rd_addr <= (others => '0');
+--				else
+					int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0));
+					data_out_valid <= rd_en;
+					if wr_en = '1' then
+							int_xmem(to_integer(wr_addr)) <= data_in;
+					end if;
+--				end if;
+			end if;
+		end process;
+	end generate;
+
+	YMEM_GEN: if mem_type = Y_MEM generate
+		data_out <= int_ymem(to_integer(unsigned(int_mem_rd_addr)));
+		process(clk) is
+		begin
+			if rising_edge(clk) then
+--				if rst = '1' then
+--					data_out_valid <= '0';
+--					int_mem_rd_addr <= (others => '0');
+--				else
+					int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0));
+					data_out_valid <= rd_en;
+					if wr_en = '1' then
+							int_ymem(to_integer(wr_addr)) <= data_in;
+					end if;
+--				end if;
+			end if;
+		end process;
+	end generate;
+--	process(clk, rst) is
+--	begin
+--		if rising_edge(clk) then
+--			if rst = '1' then
+--				data_out_valid <= '0';
+--				int_mem_rd_addr <= (others => '0');
+--			else
+--				int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0));
+--				data_out_valid <= rd_en;
+--				if wr_en = '1' then
+--					if mem_type = P_MEM then
+--						int_pmem(to_integer(wr_addr)) <= data_in;
+--					elsif mem_type = X_MEM then
+--						int_xmem(to_integer(wr_addr)) <= data_in;
+--					elsif mem_type = Y_MEM then
+--						int_ymem(to_integer(wr_addr)) <= data_in;
+--					end if;
+--				end if;
+--			end if;
+--		end if;
+--	end process;
+
+end architecture rtl;
+
diff --git a/FPGA_quartus_GE/DSP/src/memory_management.vhd b/FPGA_quartus_GE/DSP/src/memory_management.vhd
new file mode 100644
index 0000000..6a25ac8
--- /dev/null
+++ b/FPGA_quartus_GE/DSP/src/memory_management.vhd
@@ -0,0 +1,206 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity memory_management is port (
+	clk, rst : in std_logic;
+	stall_flags    : in  std_logic_vector(PIPELINE_DEPTH-1 downto 0);
+	memory_stall   : out std_logic;
+	data_rom_enable: in  std_logic;
+	pmem_ctrl_in   : in  mem_ctrl_type_in;
+	pmem_ctrl_out  : out mem_ctrl_type_out;
+	xmem_ctrl_in   : in  mem_ctrl_type_in;
+	xmem_ctrl_out  : out mem_ctrl_type_out;
+	ymem_ctrl_in   : in  mem_ctrl_type_in;
+	ymem_ctrl_out  : out mem_ctrl_type_out
+);
+end memory_management;
+
+
+architecture rtl of memory_management is
+
+
+	component mem_control is 
+	generic(
+		mem_type : memory_type
+	);
+	port(
+		clk, rst        : in std_logic;
+		rd_addr         : in unsigned(BW_ADDRESS-1 downto 0);
+		rd_en           : in std_logic;
+		data_out        : out std_logic_vector(23 downto 0);
+		data_out_valid  : out std_logic;
+		wr_addr         : in  unsigned(BW_ADDRESS-1 downto 0);
+		wr_en           : in  std_logic;
+		wr_accomplished : out std_logic;
+		data_in         : in  std_logic_vector(23 downto 0)
+	);
+	end component mem_control;
+
+	signal pmem_data_out        : std_logic_vector(23 downto 0);
+	signal pmem_data_out_valid  : std_logic;
+
+	signal pmem_rd_addr   : unsigned(BW_ADDRESS-1 downto 0);
+	signal pmem_rd_en     : std_logic;
+
+	signal xmem_rd_en          : std_logic;
+	signal xmem_data_out       : std_logic_vector(23 downto 0);
+	signal xmem_data_out_valid : std_logic;
+	signal xmem_rd_polling : std_logic;
+
+	signal ymem_rd_en          : std_logic;
+	signal ymem_data_out       : std_logic_vector(23 downto 0);
+	signal ymem_data_out_valid : std_logic;
+	signal ymem_rd_polling : std_logic;
+
+	signal pmem_stall_buffer : std_logic_vector(23 downto 0);
+	signal pmem_stall_buffer_valid : std_logic;
+	signal xmem_stall_buffer : std_logic_vector(23 downto 0);
+	signal ymem_stall_buffer : std_logic_vector(23 downto 0);
+
+	signal stall_flags_d    : std_logic_vector(PIPELINE_DEPTH-1 downto 0);
+
+begin
+
+	-- here it is necessary to store the output of the pmem/xmem/ymem when the pipeline enters a stall
+	-- when the pipeline wakes up, this temporal result is inserted into the pipeline
+	stall_buffer: process(clk) is
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				pmem_stall_buffer <= (others => '0');
+				pmem_stall_buffer_valid <= '0';
+				xmem_stall_buffer <= (others => '0');
+				ymem_stall_buffer <= (others => '0');
+				stall_flags_d <= (others => '0');
+			else
+				stall_flags_d <= stall_flags;
+				if stall_flags(ST_FETCH2) = '1' and stall_flags_d(ST_FETCH2) = '0' then
+					if pmem_data_out_valid = '1' then
+						pmem_stall_buffer <= pmem_data_out;
+						pmem_stall_buffer_valid <= '1';
+					end if;
+				end if;
+				if stall_flags(ST_FETCH2) = '0' and stall_flags_d(ST_FETCH2) = '1' then
+						pmem_stall_buffer_valid <= '0';
+				end if;
+
+
+			end if;
+		end if;
+	end process stall_buffer;
+	
+	memory_stall <= '1' when ( xmem_rd_en = '1' or (xmem_rd_polling = '1' and xmem_data_out_valid = '0') ) or
+	                         ( ymem_rd_en = '1' or (ymem_rd_polling = '1' and ymem_data_out_valid = '0') ) else
+	                '0';
+
+	-------------------------------
+	-- PMEM CONTROLLER
+	-------------------------------
+	inst_pmem_ctrl : mem_control 
+	generic map(
+		mem_type => P_MEM
+	)
+	port map(
+		clk => clk,
+		rst => rst,
+		rd_addr => pmem_ctrl_in.rd_addr,
+		rd_en   => pmem_ctrl_in.rd_en,
+		data_out => pmem_data_out,
+		data_out_valid => pmem_data_out_valid,
+		wr_addr => pmem_ctrl_in.wr_addr,
+		wr_en   => pmem_ctrl_in.wr_en,
+		data_in => pmem_ctrl_in.data_in
+	);
+
+	-- In case we wake up from a stall use the buffered value
+	pmem_ctrl_out.data_out <= pmem_stall_buffer when stall_flags(ST_FETCH2) = '0' and 
+	                                                 stall_flags_d(ST_FETCH2) = '1' and 
+	                                                 pmem_stall_buffer_valid = '1'  else
+	                          pmem_data_out;
+
+	pmem_ctrl_out.data_out_valid <= pmem_stall_buffer_valid when stall_flags(ST_FETCH2) = '0' and 
+	                                                             stall_flags_d(ST_FETCH2) = '1' else
+	                                '0'                     when stall_flags(ST_FETCH2) = '1' else
+	                                pmem_data_out_valid;
+
+	-------------------------------
+	-- XMEM CONTROLLER
+	-------------------------------
+	inst_xmem_ctrl : mem_control 
+	generic map(
+		mem_type => X_MEM
+	)
+	port map(
+		clk => clk,
+		rst => rst,
+		rd_addr => xmem_ctrl_in.rd_addr,
+		rd_en   => xmem_rd_en,
+		data_out => xmem_data_out,
+		data_out_valid => xmem_data_out_valid,
+		wr_addr => xmem_ctrl_in.wr_addr,
+		wr_en   => xmem_ctrl_in.wr_en,
+		data_in => xmem_ctrl_in.data_in
+	);
+
+	xmem_rd_en <= '1' when xmem_rd_polling = '0' and xmem_ctrl_in.rd_en = '1' else '0';
+
+	xmem_ctrl_out.data_out <= xmem_data_out;
+	xmem_ctrl_out.data_out_valid <= xmem_data_out_valid;
+
+	-------------------------------
+	-- YMEM CONTROLLER
+	-------------------------------
+	inst_ymem_ctrl : mem_control 
+	generic map(
+		mem_type => Y_MEM
+	)
+	port map(
+		clk => clk,
+		rst => rst,
+		rd_addr => ymem_ctrl_in.rd_addr,
+		rd_en   => ymem_rd_en,
+		data_out => ymem_data_out,
+		data_out_valid => ymem_data_out_valid,
+		wr_addr => ymem_ctrl_in.wr_addr,
+		wr_en   => ymem_ctrl_in.wr_en,
+		data_in => ymem_ctrl_in.data_in
+	);
+
+	ymem_rd_en <= '1' when ymem_rd_polling = '0' and ymem_ctrl_in.rd_en = '1' else '0';
+
+	ymem_ctrl_out.data_out <= ymem_data_out;
+	ymem_ctrl_out.data_out_valid <= ymem_data_out_valid;
+
+	mem_stall_control: process(clk) is
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				xmem_rd_polling <= '0';
+				ymem_rd_polling <= '0';
+			else
+				if xmem_rd_en = '1' then
+					xmem_rd_polling <= '1';
+				end if;
+
+				if xmem_data_out_valid = '1' then
+					xmem_rd_polling <= '0';
+				end if;
+
+				if ymem_rd_en = '1' then
+					ymem_rd_polling <= '1';
+				end if;
+
+				if ymem_data_out_valid = '1' then
+					ymem_rd_polling <= '0';
+				end if;
+
+			end if;
+		end if;
+	end process;
+end architecture;
+
diff --git a/FPGA_quartus_GE/DSP/src/parameter_pkg.vhd b/FPGA_quartus_GE/DSP/src/parameter_pkg.vhd
new file mode 100644
index 0000000..9e3c301
--- /dev/null
+++ b/FPGA_quartus_GE/DSP/src/parameter_pkg.vhd
@@ -0,0 +1,10 @@
+
+package parameter_pkg is
+
+	constant BW_ADDRESS : natural := 16;
+
+	constant PIPELINE_DEPTH : natural := 5;
+
+	constant NUM_ACT_SIGNALS : natural := 26;
+
+end package;
diff --git a/FPGA_quartus_GE/DSP/src/pipeline.vhd b/FPGA_quartus_GE/DSP/src/pipeline.vhd
new file mode 100644
index 0000000..5b5a98e
--- /dev/null
+++ b/FPGA_quartus_GE/DSP/src/pipeline.vhd
@@ -0,0 +1,968 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity pipeline is port (
+	clk, rst : in std_logic;
+	register_file_out : out register_file_type
+
+);
+end pipeline;
+
+-- TODOs:
+-- External memory accesses
+-- ROM tables
+-- Reading from SSH flag has to modify stack pointer
+-- Memory access (x,y,p) and talling accordingly
+-- Address Generator: ring buffers are not yet supported
+
+-- List of BUGS:
+-- - Reading from address one clock cycle after writing to the same address might result in corrupted data!!
+-- - SBC instruction has errorneous carry flag calculation
+
+-- List of probable issues:
+-- - Reading from XMEM/YMEM with stalls probably results in corrupted data
+-- - ENDDO instruction probably has to flush the pipeline afterwards
+-- - Writing to memory occurs twice, when stalls occur
+
+-- Things to optimize: 
+--  - RTS/RTI could be executed in the ADGEN Stage already
+--  - DO loops always flush the pipeline. This is necessary in case we have a very short loop.
+--     The single instruction of the loop then has passed the fetch stage already without the branch
+
+
+architecture rtl of pipeline is
+
+	signal pipeline_regs : pipeline_type;
+	signal stall_flags   : std_logic_vector(PIPELINE_DEPTH-1 downto 0);
+
+	component fetch_stage is port(
+		pc_old        : in  unsigned(BW_ADDRESS-1 downto 0);
+		pc_new        : out unsigned(BW_ADDRESS-1 downto 0);
+		modify_pc     : in  std_logic;
+		modified_pc   : in  unsigned(BW_ADDRESS-1 downto 0);
+		register_file : in  register_file_type;
+		decrement_lc  : out std_logic;
+		perform_enddo : out std_logic
+	);
+	end component fetch_stage;
+
+	signal pc_old, pc_new    : unsigned(BW_ADDRESS-1 downto 0);
+	signal fetch_modify_pc   : std_logic;
+	signal fetch_modified_pc : unsigned(BW_ADDRESS-1 downto 0);
+	signal fetch_perform_enddo: std_logic;
+	signal fetch_decrement_lc: std_logic;
+
+
+	component decode_stage is port(
+		activate_dec    : in  std_logic;
+		instr_word      : in  std_logic_vector(23 downto 0);
+		dble_word_instr : out std_logic;
+		instr_array     : out instructions_type;
+		act_array       : out std_logic_vector(NUM_ACT_SIGNALS-1 downto 0);
+		reg_wr_addr     : out std_logic_vector(5 downto 0);
+		reg_rd_addr     : out std_logic_vector(5 downto 0);
+		x_bus_rd_addr   : out std_logic_vector(1 downto 0); 
+		x_bus_wr_addr   : out std_logic_vector(1 downto 0); 
+		y_bus_rd_addr   : out std_logic_vector(1 downto 0); 
+		y_bus_wr_addr   : out std_logic_vector(1 downto 0); 
+		l_bus_addr      : out std_logic_vector(2 downto 0); 
+		adgen_mode_a    : out adgen_mode_type;
+		adgen_mode_b    : out adgen_mode_type;
+		alu_ctrl        : out alu_ctrl_type
+	);
+	end component decode_stage;
+
+	signal dec_activate : std_logic;
+	signal dec_instr_word      : std_logic_vector(23 downto 0);
+	signal dec_dble_word_instr : std_logic;
+	signal dec_instr_array     : instructions_type;
+	signal dec_act_array       : std_logic_vector(NUM_ACT_SIGNALS-1 downto 0);
+	signal dec_reg_wr_addr     : std_logic_vector(5 downto 0);
+	signal dec_reg_rd_addr     : std_logic_vector(5 downto 0);
+	signal dec_x_bus_wr_addr   : std_logic_vector(1 downto 0);
+	signal dec_x_bus_rd_addr   : std_logic_vector(1 downto 0);
+	signal dec_y_bus_wr_addr   : std_logic_vector(1 downto 0);
+	signal dec_y_bus_rd_addr   : std_logic_vector(1 downto 0);
+	signal dec_l_bus_addr      : std_logic_vector(2 downto 0);
+	signal dec_adgen_mode_a    : adgen_mode_type;
+	signal dec_adgen_mode_b    : adgen_mode_type;
+	signal dec_alu_ctrl        : alu_ctrl_type;
+
+	component adgen_stage is port(
+		activate_adgen    : in  std_logic;
+		activate_x_mem    : in  std_logic;
+		activate_y_mem    : in  std_logic;
+		activate_l_mem    : in  std_logic;
+		instr_word        : in  std_logic_vector(23 downto 0);
+		instr_array       : in  instructions_type;
+		optional_ea_word  : in  std_logic_vector(23 downto 0);
+		register_file     : in  register_file_type;
+		adgen_mode_a      : in  adgen_mode_type;
+		adgen_mode_b      : in  adgen_mode_type;
+		address_out_x     : out unsigned(BW_ADDRESS-1 downto 0);
+		address_out_y     : out unsigned(BW_ADDRESS-1 downto 0);
+		wr_R_port_A_valid : out std_logic;
+		wr_R_port_A       : out addr_wr_port_type;
+		wr_R_port_B_valid : out std_logic;
+		wr_R_port_B       : out addr_wr_port_type
+	);
+	end component adgen_stage;
+
+	signal adgen_activate          : std_logic;
+	signal adgen_activate_x_mem    : std_logic;
+	signal adgen_activate_y_mem    : std_logic;
+	signal adgen_activate_l_mem    : std_logic;
+	signal adgen_instr_word        : std_logic_vector(23 downto 0);
+	signal adgen_instr_array       : instructions_type;
+	signal adgen_optional_ea_word  : std_logic_vector(23 downto 0);
+	signal adgen_register_file     : register_file_type;
+	signal adgen_mode_a            : adgen_mode_type;
+	signal adgen_mode_b            : adgen_mode_type;
+	signal adgen_address_out_x     : unsigned(BW_ADDRESS-1 downto 0);
+	signal adgen_address_out_y     : unsigned(BW_ADDRESS-1 downto 0);
+	signal adgen_wr_R_port_A_valid : std_logic;
+	signal adgen_wr_R_port_A       : addr_wr_port_type;
+	signal adgen_wr_R_port_B_valid : std_logic;
+	signal adgen_wr_R_port_B       : addr_wr_port_type;
+
+	component exec_stage_bit_modify is port(
+		instr_word        : in  std_logic_vector(23 downto 0);
+		instr_array       : in  instructions_type;
+		src_operand       : in  std_logic_vector(23 downto 0);
+		register_file     : in  register_file_type;
+		dst_operand       : out std_logic_vector(23 downto 0);
+		bit_cond_met      : out std_logic;
+		modify_sr         : out std_logic;
+		modified_sr       : out std_logic_vector(15 downto 0)
+	);
+	end component exec_stage_bit_modify;
+
+	signal exec_bit_modify_instr_word    : std_logic_vector(23 downto 0);
+	signal exec_bit_modify_instr_array   : instructions_type;
+	signal exec_bit_modify_src_operand   : std_logic_vector(23 downto 0);
+	signal exec_bit_modify_dst_operand   : std_logic_vector(23 downto 0);
+	signal exec_bit_modify_bit_cond_met  : std_logic;
+	signal exec_bit_modify_modify_sr     : std_logic;
+	signal exec_bit_modify_modified_sr   : std_logic_vector(15 downto 0);
+
+	component exec_stage_branch is port(
+		activate_exec_bra : in  std_logic;
+		instr_word        : in  std_logic_vector(23 downto 0);
+		instr_array       : in  instructions_type;
+		register_file     : in  register_file_type;
+		jump_address      : in  unsigned(BW_ADDRESS-1 downto 0);
+		bit_cond_met      : in  std_logic;
+		cc_flag_set       : in  std_logic;
+		push_stack        : out push_stack_type;
+		pop_stack         : out pop_stack_type;
+		modify_pc         : out std_logic;
+		modified_pc       : out unsigned(BW_ADDRESS-1 downto 0);
+		modify_sr         : out std_logic;
+		modified_sr       : out std_logic_vector(15 downto 0)
+	);
+	end component exec_stage_branch;
+
+	signal exec_bra_activate     : std_logic;
+	signal exec_bra_instr_word   : std_logic_vector(23 downto 0);
+	signal exec_bra_instr_array  : instructions_type;
+	signal exec_bra_jump_address : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_bra_bit_cond_met : std_logic;
+	signal exec_bra_push_stack   : push_stack_type;
+	signal exec_bra_pop_stack    : pop_stack_type;
+	signal exec_bra_modify_pc    : std_logic;
+	signal exec_bra_modified_pc  : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_bra_modify_sr    : std_logic;
+	signal exec_bra_modified_sr  : std_logic_vector(15 downto 0);
+
+	component exec_stage_cr_mod is port(
+		activate_exec_cr_mod : in  std_logic;
+		instr_word           : in  std_logic_vector(23 downto 0);
+		instr_array          : in  instructions_type;
+		register_file        : in  register_file_type;
+		modify_sr            : out std_logic;
+		modified_sr          : out std_logic_vector(15 downto 0);
+		modify_omr           : out std_logic;
+		modified_omr         : out std_logic_vector(7 downto 0)
+	);
+	end component exec_stage_cr_mod;
+
+	signal exec_cr_mod_activate     : std_logic;
+	signal exec_cr_mod_instr_word   : std_logic_vector(23 downto 0);
+	signal exec_cr_mod_instr_array  : instructions_type;
+	signal exec_cr_mod_modify_sr    : std_logic;
+	signal exec_cr_mod_modified_sr  : std_logic_vector(15 downto 0);
+	signal exec_cr_mod_modify_omr   : std_logic;
+	signal exec_cr_mod_modified_omr : std_logic_vector(7 downto 0);
+
+	component exec_stage_loop is port(
+		clk, rst           : in  std_logic;
+		activate_exec_loop : in  std_logic;
+		instr_word        : in  std_logic_vector(23 downto 0);
+		instr_array       : in  instructions_type;
+		loop_iterations   : in  unsigned(15 downto 0);
+		loop_address      : in  unsigned(BW_ADDRESS-1 downto 0);
+		loop_start_address: in  unsigned(BW_ADDRESS-1 downto 0);
+		register_file     : in  register_file_type;
+		fetch_perform_enddo: in std_logic;
+		memory_stall      : in  std_logic;
+		push_stack        : out push_stack_type;
+		pop_stack         : out pop_stack_type;
+		stall_rep         : out std_logic;
+		stall_do          : out std_logic;
+		decrement_lc      : out std_logic;
+		modify_lc         : out std_logic;
+		modified_lc       : out unsigned(15 downto 0);
+		modify_la         : out std_logic;
+		modified_la       : out unsigned(15 downto 0);
+		modify_pc         : out std_logic;
+		modified_pc       : out unsigned(BW_ADDRESS-1 downto 0);
+		modify_sr         : out std_logic;
+		modified_sr       : out std_logic_vector(15 downto 0)
+	);
+	end component exec_stage_loop;
+
+	signal exec_loop_activate : std_logic;
+	signal exec_loop_instr_word    : std_logic_vector(23 downto 0);
+	signal exec_loop_instr_array   : instructions_type;
+	signal exec_loop_iterations    : unsigned(15 downto 0);
+	signal exec_loop_address       : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_loop_start_address : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_loop_register_file : register_file_type;
+	signal exec_loop_push_stack    : push_stack_type;
+	signal exec_loop_pop_stack     : pop_stack_type;
+	signal exec_loop_stall_rep     : std_logic;
+	signal exec_loop_stall_do      : std_logic;
+	signal exec_loop_decrement_lc  : std_logic;
+	signal exec_loop_modify_lc     : std_logic;
+	signal exec_loop_modified_lc   : unsigned(15 downto 0);
+	signal exec_loop_modify_la     : std_logic;
+	signal exec_loop_modified_la   : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_loop_modify_pc     : std_logic;
+	signal exec_loop_modified_pc   : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_loop_modify_sr     : std_logic;
+	signal exec_loop_modified_sr   : std_logic_vector(BW_ADDRESS-1 downto 0);
+
+	component exec_stage_alu is port(
+		alu_activate      : in  std_logic;
+		instr_word        : in  std_logic_vector(23 downto 0);
+		alu_ctrl          : in  alu_ctrl_type;
+		register_file     : in  register_file_type;
+		addr_r_in         : in  unsigned(BW_ADDRESS-1 downto 0);
+		addr_r_out        : out unsigned(BW_ADDRESS-1 downto 0);
+		modify_accu       : out std_logic;
+		dst_accu          : out std_logic;
+		modified_accu     : out signed(55 downto 0);
+		modify_sr         : out std_logic;
+		modified_sr       : out std_logic_vector(15 downto 0)
+	);
+	end component exec_stage_alu;
+
+	signal exec_alu_activate      : std_logic;
+	signal exec_alu_instr_word    : std_logic_vector(23 downto 0);
+	signal exec_alu_ctrl          : alu_ctrl_type;
+	signal exec_alu_addr_r_in     : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_alu_addr_r_out    : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_alu_modify_accu   : std_logic;
+	signal exec_alu_dst_accu      : std_logic;
+	signal exec_alu_modified_accu : signed(55 downto 0);
+	signal exec_alu_modify_sr     : std_logic;
+	signal exec_alu_modified_sr   : std_logic_vector(15 downto 0);
+
+	signal exec_imm_8bit    : std_logic_vector(23 downto 0);
+	signal exec_imm_12bit   : std_logic_vector(23 downto 0);
+	signal exec_src_operand : std_logic_vector(23 downto 0);
+	signal exec_dst_operand : std_logic_vector(23 downto 0);
+
+	component exec_stage_cc_flag_calc is port(
+		instr_word        : in  std_logic_vector(23 downto 0);
+		instr_array       : in  instructions_type;
+		register_file     : in  register_file_type;
+		cc_flag_set       : out std_logic
+	);
+	end component exec_stage_cc_flag_calc;
+
+	signal exec_cc_flag_calc_instr_word   : std_logic_vector(23 downto 0);
+	signal exec_cc_flag_calc_instr_array  : instructions_type;
+	signal exec_cc_flag_set : std_logic;
+
+	component reg_file is port(
+		clk, rst          : in  std_logic;
+		register_file     : out register_file_type;
+		wr_R_port_A_valid : in  std_logic;
+		wr_R_port_A       : in  addr_wr_port_type;
+		wr_R_port_B_valid : in  std_logic;
+		wr_R_port_B       : in  addr_wr_port_type;
+		alu_wr_valid      : in  std_logic;
+		alu_wr_addr       : in  std_logic;
+		alu_wr_data       : in  signed(55 downto 0);
+		reg_wr_addr       : in  std_logic_vector(5 downto 0);
+		reg_wr_addr_valid : in  std_logic;
+		reg_wr_data       : in  std_Logic_vector(23 downto 0);
+		reg_rd_addr       : in  std_logic_vector(5 downto 0);
+		reg_rd_data       : out std_Logic_vector(23 downto 0);
+		X_bus_rd_addr     : in  std_logic_vector(1 downto 0);
+		X_bus_data_out    : out std_logic_vector(23 downto 0);
+		X_bus_wr_addr     : in  std_logic_vector(1 downto 0);
+		X_bus_wr_valid    : in  std_logic;
+		X_bus_data_in     : in  std_logic_vector(23 downto 0);
+		Y_bus_rd_addr     : in  std_logic_vector(1 downto 0);
+		Y_bus_data_out    : out std_logic_vector(23 downto 0);
+		Y_bus_wr_addr     : in  std_logic_vector(1 downto 0);
+		Y_bus_wr_valid    : in  std_logic;
+		Y_bus_data_in     : in  std_logic_vector(23 downto 0);
+		L_bus_rd_addr     : in  std_logic_vector(2 downto 0);
+		L_bus_rd_valid    : in  std_logic;
+		L_bus_wr_addr     : in  std_logic_vector(2 downto 0);
+		L_bus_wr_valid    : in  std_logic;
+		push_stack        : in  push_stack_type;
+		pop_stack         : in  pop_stack_type;
+		set_sr            : in  std_logic;
+		new_sr            : in  std_logic_vector(15 downto 0);
+		set_omr           : in  std_logic;
+		new_omr           : in  std_logic_vector(7 downto 0);
+		set_lc            : in  std_logic;
+		new_lc            : in  unsigned(15 downto 0);
+		dec_lc            : in  std_logic;
+		set_la            : in  std_logic;
+		new_la            : in  unsigned(BW_ADDRESS-1 downto 0)
+	);
+	end component reg_file;
+
+	signal register_file        : register_file_type;
+	signal rf_wr_R_port_A_valid : std_logic;
+	signal rf_wr_R_port_B_valid : std_logic;
+	signal rf_reg_wr_addr       : std_logic_vector(5 downto 0);
+	signal rf_reg_wr_addr_valid : std_logic;
+	signal rf_reg_wr_data       : std_logic_vector(23 downto 0);
+	signal rf_reg_rd_addr       : std_logic_vector(5 downto 0);
+	signal rf_reg_rd_data       : std_logic_vector(23 downto 0);
+	signal rf_X_bus_rd_addr     : std_logic_vector(1 downto 0);
+	signal rf_X_bus_data_out    : std_logic_vector(23 downto 0);
+	signal rf_X_bus_wr_addr     : std_logic_vector(1 downto 0);
+	signal rf_X_bus_wr_valid    : std_logic;
+	signal rf_X_bus_data_in     : std_logic_vector(23 downto 0);
+	signal rf_Y_bus_rd_addr     : std_logic_vector(1 downto 0);
+	signal rf_Y_bus_data_out    : std_logic_vector(23 downto 0);
+	signal rf_Y_bus_wr_addr     : std_logic_vector(1 downto 0);
+	signal rf_Y_bus_wr_valid    : std_logic;
+	signal rf_Y_bus_data_in     : std_logic_vector(23 downto 0);
+	signal rf_L_bus_rd_addr     : std_logic_vector(2 downto 0);
+	signal rf_L_bus_rd_valid    : std_logic;
+	signal rf_L_bus_wr_addr     : std_logic_vector(2 downto 0);
+	signal rf_L_bus_wr_valid    : std_logic;
+	signal push_stack           : push_stack_type;
+	signal pop_stack            : pop_stack_type;
+	signal rf_set_sr            : std_logic;
+	signal rf_new_sr            : std_logic_vector(15 downto 0);
+	signal rf_set_omr           : std_logic;
+	signal rf_new_omr           : std_logic_vector(7 downto 0);
+	signal rf_dec_lc            : std_logic;
+	signal rf_set_lc            : std_logic;
+	signal rf_new_lc            : unsigned(15 downto 0);
+	signal rf_set_la            : std_logic;
+	signal rf_new_la            : unsigned(BW_ADDRESS-1 downto 0);
+	signal rf_alu_wr_valid      : std_logic;
+
+	component memory_management is port (
+		clk, rst : in std_logic;
+		stall_flags    : in  std_logic_vector(PIPELINE_DEPTH-1 downto 0);
+		memory_stall   : out std_logic;
+		data_rom_enable: in  std_logic;
+		pmem_ctrl_in   : in  mem_ctrl_type_in;
+		pmem_ctrl_out  : out mem_ctrl_type_out;
+		xmem_ctrl_in   : in  mem_ctrl_type_in;
+		xmem_ctrl_out  : out mem_ctrl_type_out;
+		ymem_ctrl_in   : in  mem_ctrl_type_in;
+		ymem_ctrl_out  : out mem_ctrl_type_out
+	);
+	end component memory_management;
+
+	signal memory_stall   : std_logic;
+	signal pmem_ctrl_in   : mem_ctrl_type_in;
+	signal pmem_ctrl_out  : mem_ctrl_type_out;
+	signal xmem_ctrl_in   : mem_ctrl_type_in;
+	signal xmem_ctrl_out  : mem_ctrl_type_out;
+	signal ymem_ctrl_in   : mem_ctrl_type_in;
+	signal ymem_ctrl_out  : mem_ctrl_type_out;
+
+	signal pmem_data_out       : std_logic_vector(23 downto 0);
+	signal pmem_data_out_valid : std_logic;
+	signal xmem_data_out       : std_logic_vector(23 downto 0);
+	signal xmem_data_out_valid : std_logic;
+	signal ymem_data_out       : std_logic_vector(23 downto 0);
+	signal ymem_data_out_valid : std_logic;
+
+begin
+	register_file_out <= register_file;
+
+	-- merge all stall sources
+	stall_flags(ST_FETCH)  <= '1' when exec_loop_stall_rep   = '1' or 
+	                                   memory_stall = '1' or
+	                                   exec_loop_stall_do    = '1' else '0';
+	stall_flags(ST_FETCH2) <= '1' when exec_loop_stall_rep = '1' or 
+	                                   memory_stall = '1' or
+	                                   exec_loop_stall_do = '1' else '0';
+	stall_flags(ST_DECODE) <= '1' when exec_loop_stall_rep = '1' or
+	                                   memory_stall = '1' or
+	                                   exec_loop_stall_do = '1' else '0';
+	stall_flags(ST_ADGEN)   <= exec_loop_stall_do;
+--	stall_flags(ST_ADGEN)  <= '1' when memory_stall = '1' or
+--	                                   exec_loop_stall_do = '1' else '0';
+--	stall_flags(ST_EXEC)   <= '0';
+	stall_flags(ST_EXEC)   <= exec_loop_stall_do;
+--	stall_flags(ST_EXEC)   <= '1' when memory_stall = '1' or
+--	                                   exec_loop_stall_do = '1' else '0';
+
+	shift_pipeline: process(clk, rst) is
+		procedure flush_pipeline_stage(stage: natural) is
+		begin
+			pipeline_regs(stage).pc <= (others => '1');
+			pipeline_regs(stage).instr_word <= (others => '0');
+			pipeline_regs(stage).act_array   <= (others => '0');
+			pipeline_regs(stage).instr_array <= INSTR_NOP;
+			pipeline_regs(stage).dble_word_instr <= '0';
+			pipeline_regs(stage).dec_activate <= '0';
+			pipeline_regs(stage).adgen_mode_a <= NOP;
+			pipeline_regs(stage).adgen_mode_b <= NOP;
+			pipeline_regs(stage).reg_wr_addr  <= (others => '0');
+			pipeline_regs(stage).reg_rd_addr  <= (others => '0');
+			pipeline_regs(stage).x_bus_rd_addr  <= (others => '0');
+			pipeline_regs(stage).x_bus_wr_addr  <= (others => '0');
+			pipeline_regs(stage).y_bus_rd_addr  <= (others => '0');
+			pipeline_regs(stage).y_bus_wr_addr  <= (others => '0');
+			pipeline_regs(stage).l_bus_addr     <= (others => '0');
+			pipeline_regs(stage).adgen_address_x <= (others => '0');
+			pipeline_regs(stage).adgen_address_y <= (others => '0');
+			pipeline_regs(stage).RAM_out_x <= (others => '0');
+			pipeline_regs(stage).RAM_out_y <= (others => '0');
+			pipeline_regs(stage).alu_ctrl.store_result <= '0';
+		end procedure flush_pipeline_stage;
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				for i in 0 to PIPELINE_DEPTH-1 loop
+					flush_pipeline_stage(i);
+				end loop;
+			else
+				-- shift the pipeline registers when no stall applies
+				for i in 1 to PIPELINE_DEPTH-1 loop
+					if stall_flags(i) = '0' then
+						-- do not copy the pipeline registers from a stalled pipeline stage
+						-- for REP we do not flush
+--						if stall_flags(i-1) = '1' then
+						if (stall_flags(i-1) = '1' and exec_loop_stall_rep = '0') or
+						   (i = ST_ADGEN and memory_stall = '1' and exec_loop_stall_rep = '1') then
+							flush_pipeline_stage(i);
+						else
+							pipeline_regs(i) <= pipeline_regs(i-1);
+						end if;
+					end if;
+				end loop;
+				-- FETCH Pipeline Registers 
+				if stall_flags(ST_FETCH) = '0' then
+					pipeline_regs(ST_FETCH).pc <= pc_new;
+					pipeline_regs(ST_FETCH).dec_activate <= '1';
+				end if;
+
+				-- FETCH2 Pipeline Registers
+				if stall_flags(ST_FETCH2) = '0' then
+					-- Normal pipeline operation?
+					-- Buffering of RAM output when stalling is performed in the memory management
+					if pmem_data_out_valid = '1' then
+						pipeline_regs(ST_FETCH2).instr_word <= pmem_data_out;
+					end if;
+				end if;
+
+				-- DECODE Pipeline registers
+				if stall_flags(ST_DECODE) = '0' then
+					pipeline_regs(ST_DECODE).act_array   <= dec_act_array;
+					pipeline_regs(ST_DECODE).instr_array <= dec_instr_array;
+					pipeline_regs(ST_DECODE).dble_word_instr <= dec_dble_word_instr;
+					pipeline_regs(ST_DECODE).reg_wr_addr     <= dec_reg_wr_addr;
+					pipeline_regs(ST_DECODE).reg_rd_addr     <= dec_reg_rd_addr;
+					pipeline_regs(ST_DECODE).x_bus_wr_addr   <= dec_x_bus_wr_addr;
+					pipeline_regs(ST_DECODE).x_bus_rd_addr   <= dec_x_bus_rd_addr;
+					pipeline_regs(ST_DECODE).y_bus_wr_addr   <= dec_y_bus_wr_addr;
+					pipeline_regs(ST_DECODE).y_bus_rd_addr   <= dec_y_bus_rd_addr;
+					pipeline_regs(ST_DECODE).l_bus_addr      <= dec_l_bus_addr;
+					pipeline_regs(ST_DECODE).adgen_mode_a    <= dec_adgen_mode_a;
+					pipeline_regs(ST_DECODE).adgen_mode_b    <= dec_adgen_mode_b;
+					pipeline_regs(ST_DECODE).alu_ctrl        <= dec_alu_ctrl;
+				end if;
+
+				-- ADGEN Pipeline registers
+				if stall_flags(ST_ADGEN) = '0' then
+					pipeline_regs(ST_ADGEN).adgen_address_x <= adgen_address_out_x;
+					pipeline_regs(ST_ADGEN).adgen_address_y <= adgen_address_out_y;
+				end if;
+				if xmem_data_out_valid = '1' then
+					pipeline_regs(ST_ADGEN).RAM_out_x <= xmem_data_out;
+				end if;
+				if ymem_data_out_valid = '1' then
+					pipeline_regs(ST_ADGEN).RAM_out_y <= ymem_data_out;
+				end if;
+
+				-- EXEC Pipeline stuff
+				if exec_bra_modify_pc = '1' or exec_loop_modify_pc = '1' then
+					-- clear the following pipeline stages,
+					-- since we modified the pc. 
+					-- Do not flush ST_FETCH - it will hold the correct pc.
+					flush_pipeline_stage(ST_FETCH2);
+					flush_pipeline_stage(ST_DECODE);
+					flush_pipeline_stage(ST_ADGEN);
+				end if;
+			end if;
+		end if;
+	end process shift_pipeline;
+
+	-------------------------------
+	-- FETCH STAGE INSTANTIATION
+	-------------------------------
+	inst_fetch_stage: fetch_stage port map(
+		pc_old => pc_old,
+		pc_new => pc_new,
+		modify_pc => fetch_modify_pc,
+		modified_pc => fetch_modified_pc,
+		register_file => register_file,
+		decrement_lc  => fetch_decrement_lc,
+		perform_enddo => fetch_perform_enddo
+	);
+
+	pc_old <= pipeline_regs(ST_FETCH).pc;
+
+	fetch_modify_pc <= '1' when exec_bra_modify_pc = '1' or exec_loop_modify_pc = '1' else '0';
+	fetch_modified_pc <= exec_bra_modified_pc when exec_bra_modify_pc = '1' else
+	                     exec_loop_modified_pc;
+
+	-------------------------------
+	-- DECODE STAGE INSTANTIATION
+	-------------------------------
+	inst_decode_stage : decode_stage port map(
+		activate_dec    => dec_activate,
+		instr_word      => dec_instr_word,
+		dble_word_instr => dec_dble_word_instr,
+		instr_array     => dec_instr_array,
+		act_array       => dec_act_array,
+		reg_wr_addr     => dec_reg_wr_addr,
+		reg_rd_addr     => dec_reg_rd_addr,
+		x_bus_wr_addr   => dec_x_bus_wr_addr,
+		x_bus_rd_addr   => dec_x_bus_rd_addr,
+		y_bus_wr_addr   => dec_y_bus_wr_addr,
+		y_bus_rd_addr   => dec_y_bus_rd_addr,
+		l_bus_addr      => dec_l_bus_addr,
+		adgen_mode_a    => dec_adgen_mode_a,
+		adgen_mode_b    => dec_adgen_mode_b,
+		alu_ctrl        => dec_alu_ctrl
+	);
+
+	dec_instr_word <= pipeline_regs(ST_DECODE-1).instr_word;
+	-- do not decode, when we have no valid instruction. This can happen when
+	--  1) the pipeline just started its operation
+	--  2) the pipeline was flushed due to a jump
+	--  3) we are processing a instruction that consists of two words
+	dec_activate   <= '1' when pipeline_regs(ST_DECODE-1).dec_activate = '1' and pipeline_regs(ST_DECODE).dble_word_instr = '0' else '0';
+
+	-------------------------------
+	-- AGU STAGE INSTANTIATION
+	-------------------------------
+	inst_adgen_stage: adgen_stage port map(
+		activate_adgen    => adgen_activate,
+		activate_x_mem    => adgen_activate_x_mem,
+		activate_y_mem    => adgen_activate_y_mem,
+		activate_l_mem    => adgen_activate_l_mem,
+		instr_word        => adgen_instr_word,
+		instr_array       => adgen_instr_array,
+		optional_ea_word  => adgen_optional_ea_word,
+		register_file     => register_file,
+		adgen_mode_a      => adgen_mode_a,
+		adgen_mode_b      => adgen_mode_b,
+		address_out_x     => adgen_address_out_x,
+		address_out_y     => adgen_address_out_y,
+		wr_R_port_A_valid => adgen_wr_R_port_A_valid,
+		wr_R_port_A       => adgen_wr_R_port_A,
+		wr_R_port_B_valid => adgen_wr_R_port_B_valid,
+		wr_R_port_B       => adgen_wr_R_port_B
+	);
+
+	adgen_activate          <= pipeline_regs(ST_ADGEN-1).act_array(ACT_ADGEN);
+	adgen_activate_x_mem    <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_X_MEM_RD) = '1' or 
+	                                    pipeline_regs(ST_ADGEN-1).act_array(ACT_X_MEM_WR) = '1' else '0';
+	adgen_activate_y_mem    <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_Y_MEM_RD) = '1' or 
+	                                    pipeline_regs(ST_ADGEN-1).act_array(ACT_Y_MEM_WR) = '1' else '0';
+	adgen_activate_l_mem    <= '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_L_BUS_RD) = '1' or 
+	                                    pipeline_regs(ST_ADGEN-1).act_array(ACT_L_BUS_WR) = '1' else '0';
+	adgen_instr_word        <= pipeline_regs(ST_ADGEN-1).instr_word;
+	adgen_instr_array       <= pipeline_regs(ST_ADGEN-1).instr_array;
+	adgen_optional_ea_word  <= pipeline_regs(ST_ADGEN-2).instr_word;
+	adgen_mode_a            <= pipeline_regs(ST_ADGEN-1).adgen_mode_a;
+	adgen_mode_b            <= pipeline_regs(ST_ADGEN-1).adgen_mode_b;
+
+	-------------------------------
+	-- EXECUTE STAGE INSTANTIATIONS
+	-------------------------------
+	inst_exec_stage_alu: exec_stage_alu port map(
+		alu_activate  => exec_alu_activate,
+		instr_word    => exec_alu_instr_word,
+		alu_ctrl      => exec_alu_ctrl,
+		register_file => register_file,
+		addr_r_in     => exec_alu_addr_r_in,
+		addr_r_out    => exec_alu_addr_r_out,
+		modify_accu   => exec_alu_modify_accu,
+		dst_accu      => exec_alu_dst_accu,
+		modified_accu => exec_alu_modified_accu,
+		modify_sr     => exec_alu_modify_sr,
+		modified_sr   => exec_alu_modified_sr
+	);
+
+	exec_alu_activate   <= pipeline_regs(ST_EXEC-1).act_array(ACT_ALU);
+	exec_alu_instr_word <= pipeline_regs(ST_EXEC-1).instr_word;
+	exec_alu_ctrl       <= pipeline_regs(ST_EXEC-1).alu_ctrl;
+
+	exec_alu_addr_r_in <= unsigned(rf_reg_rd_data(BW_ADDRESS-1 downto 0));
+
+	inst_exec_stage_bit_modify: exec_stage_bit_modify port map(
+		instr_word     => exec_bit_modify_instr_word,
+		instr_array    => exec_bit_modify_instr_array,
+		src_operand    => exec_bit_modify_src_operand,
+		register_file  => register_file,
+		dst_operand    => exec_bit_modify_dst_operand,
+		bit_cond_met   => exec_bit_modify_bit_cond_met,
+		modify_sr      => exec_bit_modify_modify_sr,
+		modified_sr    => exec_bit_modify_modified_sr
+	);
+
+	exec_bit_modify_instr_word   <= pipeline_regs(ST_EXEC-1).instr_word;
+	exec_bit_modify_instr_array  <= pipeline_regs(ST_EXEC-1).instr_array;
+	exec_bit_modify_src_operand  <= exec_src_operand;
+
+	-- Writing to the register file using the 6 bit addressing scheme
+	-- sources are:
+	-- 1) X-RAM output
+	-- 2) Y-RAM output
+	-- 3) register file itself
+	-- 4) short immediate value (8 bit stored in instruction word)
+	-- 5) long immediate value (from optional effective address extension)
+	-- 5) address generated by the address generation unit (LUA instr)
+	exec_src_operand <= pipeline_regs(ST_EXEC-1).RAM_out_x  when pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_RD)  = '1' else
+	                    pipeline_regs(ST_EXEC-1).RAM_out_y  when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_RD)  = '1' else
+	                    rf_reg_rd_data                      when pipeline_regs(ST_EXEC-1).act_array(ACT_REG_RD)    = '1' else
+	                    exec_imm_8bit                       when pipeline_regs(ST_EXEC-1).act_array(ACT_IMM_8BIT)  = '1' else
+	                    exec_imm_12bit                      when pipeline_regs(ST_EXEC-1).act_array(ACT_IMM_12BIT) = '1' else
+	                    pipeline_regs(ST_EXEC-2).instr_word when pipeline_regs(ST_EXEC-1).act_array(ACT_IMM_LONG)  = '1' else
+	                    std_logic_vector(resize(pipeline_regs(ST_EXEC-1).adgen_address_x, 24)); -- for LUA instr.
+
+	-- Destination for the register file using the 6 bit addressing scheme.
+	-- Either read the bit modified version of the read value
+	-- or use the modified Rn in case of a NORM instruction
+--	exec_dst_operand <= exec_bit_modify_dst_operand;
+	exec_dst_operand <= exec_bit_modify_dst_operand when pipeline_regs(ST_EXEC-1).act_array(ACT_NORM) = '0' else
+	                    std_logic_vector(resize(exec_alu_addr_r_out,24));
+
+	-- Unit to check whether cc (in Jcc, JScc, Tcc, ...) is true
+	inst_exec_stage_cc_flag_calc: exec_stage_cc_flag_calc port map(
+		instr_word        => exec_cc_flag_calc_instr_word,
+		instr_array       => exec_cc_flag_calc_instr_array,
+		register_file     => register_file,
+		cc_flag_set       => exec_cc_flag_set
+	);
+
+	exec_cc_flag_calc_instr_word   <= pipeline_regs(ST_EXEC-1).instr_word;
+	exec_cc_flag_calc_instr_array  <= pipeline_regs(ST_EXEC-1).instr_array;
+
+
+	inst_exec_stage_branch : exec_stage_branch port map(
+		activate_exec_bra => exec_bra_activate,
+		instr_word        => exec_bra_instr_word,
+		instr_array       => exec_bra_instr_array,
+		register_file     => register_file,
+		jump_address      => exec_bra_jump_address,
+		bit_cond_met      => exec_bra_bit_cond_met,
+		cc_flag_set       => exec_cc_flag_set,
+		push_stack        => exec_bra_push_stack,
+		pop_stack         => exec_bra_pop_stack,
+		modify_pc         => exec_bra_modify_pc,
+		modified_pc       => exec_bra_modified_pc,
+		modify_sr         => exec_bra_modify_sr,
+		modified_sr       => exec_bra_modified_sr
+	);
+
+	exec_bra_activate     <= pipeline_regs(ST_EXEC-1).act_array(ACT_EXEC_BRA);
+	exec_bra_instr_word   <= pipeline_regs(ST_EXEC-1).instr_word;
+	exec_bra_instr_array  <= pipeline_regs(ST_EXEC-1).instr_array;
+	exec_bra_jump_address <= pipeline_regs(ST_EXEC-1).adgen_address_x when pipeline_regs(ST_EXEC-1).dble_word_instr = '0' else
+	                         unsigned(pipeline_regs(ST_EXEC-2).instr_word(BW_ADDRESS-1 downto 0));
+	exec_bra_bit_cond_met <= exec_bit_modify_bit_cond_met;
+
+	inst_exec_stage_cr_mod : exec_stage_cr_mod port map(
+		activate_exec_cr_mod => exec_cr_mod_activate,
+		instr_word           => exec_cr_mod_instr_word,
+		instr_array          => exec_cr_mod_instr_array,
+		register_file        => register_file,
+		modify_sr            => exec_cr_mod_modify_sr,
+		modified_sr          => exec_cr_mod_modified_sr,
+		modify_omr           => exec_cr_mod_modify_omr,
+		modified_omr         => exec_cr_mod_modified_omr
+	);
+
+	exec_cr_mod_activate    <= pipeline_regs(ST_EXEC-1).act_array(ACT_EXEC_CR_MOD);
+	exec_cr_mod_instr_word  <= pipeline_regs(ST_EXEC-1).instr_word;
+	exec_cr_mod_instr_array <= pipeline_regs(ST_EXEC-1).instr_array;
+
+	inst_exec_stage_loop: exec_stage_loop port map(
+		clk                => clk,
+		rst                => rst,
+		activate_exec_loop => exec_loop_activate,
+		instr_word         => exec_loop_instr_word,
+		instr_array        => exec_loop_instr_array,
+		loop_iterations    => exec_loop_iterations,
+		loop_address       => exec_loop_address,
+		loop_start_address => exec_loop_start_address,
+		register_file      => register_file,
+		fetch_perform_enddo=> fetch_perform_enddo,
+		memory_stall       => memory_stall,
+		push_stack         => exec_loop_push_stack,
+		pop_stack          => exec_loop_pop_stack,
+		stall_rep          => exec_loop_stall_rep,
+		stall_do           => exec_loop_stall_do,
+		modify_lc          => exec_loop_modify_lc,
+		decrement_lc       => exec_loop_decrement_lc,
+		modified_lc        => exec_loop_modified_lc,
+		modify_la          => exec_loop_modify_la,
+		modified_la        => exec_loop_modified_la,
+		modify_pc          => exec_loop_modify_pc,
+		modified_pc        => exec_loop_modified_pc,
+		modify_sr          => exec_loop_modify_sr,
+		modified_sr        => exec_loop_modified_sr
+	);
+
+	exec_loop_activate    <= pipeline_regs(ST_EXEC-1).act_array(ACT_EXEC_LOOP);
+	exec_loop_instr_word  <= pipeline_regs(ST_EXEC-1).instr_word;
+	exec_loop_instr_array <= pipeline_regs(ST_EXEC-1).instr_array;
+	exec_loop_iterations  <= unsigned(exec_src_operand(15 downto 0));
+	-- from which source is our operand?
+	--  - XMEM
+	--  - YMEM
+	--  - Any register
+	--  - Immediate (from instruction word)
+--	exec_src_operand      <= unsigned(pipeline_regs(ST_EXEC-1).RAM_out_x(BW_ADDRESS-1 downto 0)) when 
+--	                                  pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_RD) = '1' else
+--	                         unsigned(pipeline_regs(ST_EXEC-1).RAM_out_y(BW_ADDRESS-1 downto 0)) when 
+--	                                  pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_RD) = '1' else
+--	                         unsigned(rf_reg_rd_data(15 downto 0)) when
+--	                                  pipeline_regs(ST_EXEC-1).act_array(ACT_REG_RD) = '1' else
+--	                         "00000000" & unsigned(pipeline_regs(ST_EXEC-1).instr_word(15 downto 8));
+
+	-- Loop address is given by the second instruction word of the DO instruction.
+	-- This address is available one previous stage within the pipeline
+	exec_loop_address     <= unsigned(pipeline_regs(ST_EXEC-2).instr_word(BW_ADDRESS-1 downto 0)) - 1; 
+	-- one more stage before we find the programm counter of the first instruction to be executed in a DO loop
+	exec_loop_start_address <= unsigned(pipeline_regs(ST_EXEC-3).pc);
+
+	-- For the 8 bit immediate is can be either a fractional (registers x0,x1,y0,y1,a,b) or an unsigned (the rest)
+	exec_imm_8bit(23 downto 16) <= (others => '0') when rf_reg_wr_addr(5 downto 2) /= "0001" and rf_reg_wr_addr(5 downto 1) /= "00111" else
+	                               pipeline_regs(ST_EXEC-1).instr_word(15 downto 8);
+	exec_imm_8bit(15 downto  8) <= (others => '0');
+	exec_imm_8bit( 7 downto  0) <= (others => '0') when rf_reg_wr_addr(5 downto 2) = "0001" or rf_reg_wr_addr(5 downto 1) = "00111" else
+	                               pipeline_regs(ST_EXEC-1).instr_word(15 downto 8);
+	-- The 12 bit immediate stems from the instruction word
+	exec_imm_12bit(23 downto 12) <= (others => '0');
+	exec_imm_12bit(11 downto  0) <= pipeline_regs(ST_EXEC-1).instr_word(3 downto 0) & pipeline_regs(ST_EXEC-1).instr_word(15 downto 8);
+	-----------------
+	-- REGISTER FILE 
+	-----------------
+	inst_reg_file: reg_file port map(
+		clk                => clk,
+		rst                => rst,
+		register_file      => register_file,
+		wr_R_port_A_valid  => rf_wr_R_port_A_valid,
+		wr_R_port_A        => adgen_wr_R_port_A,
+		wr_R_port_B_valid  => rf_wr_R_port_B_valid,
+		wr_R_port_B        => adgen_wr_R_port_B,
+		reg_wr_addr        => rf_reg_wr_addr,
+		reg_wr_addr_valid  => rf_reg_wr_addr_valid,
+		reg_wr_data        => rf_reg_wr_data,
+		reg_rd_addr        => rf_reg_rd_addr,
+		reg_rd_data        => rf_reg_rd_data,
+		alu_wr_valid       => rf_alu_wr_valid,
+		alu_wr_addr        => exec_alu_dst_accu,
+		alu_wr_data        => exec_alu_modified_accu,
+		X_bus_rd_addr      => rf_X_bus_rd_addr, 
+		X_bus_data_out     => rf_X_bus_data_out,
+		X_bus_wr_addr      => rf_X_bus_wr_addr ,
+		X_bus_wr_valid     => rf_X_bus_wr_valid,
+		X_bus_data_in      => rf_X_bus_data_in ,
+		Y_bus_rd_addr      => rf_Y_bus_rd_addr ,
+		Y_bus_data_out     => rf_Y_bus_data_out,
+		Y_bus_wr_addr      => rf_Y_bus_wr_addr ,
+		Y_bus_wr_valid     => rf_Y_bus_wr_valid,
+		Y_bus_data_in      => rf_Y_bus_data_in ,
+		L_bus_rd_addr      => rf_L_bus_rd_addr ,
+		L_bus_rd_valid     => rf_L_bus_rd_valid,
+		L_bus_wr_addr      => rf_L_bus_wr_addr ,
+		L_bus_wr_valid     => rf_L_bus_wr_valid,
+		push_stack         => push_stack,
+		pop_stack          => pop_stack,
+		set_sr             => rf_set_sr,
+		new_sr             => rf_new_sr,
+		set_omr            => rf_set_omr,
+		new_omr            => rf_new_omr,
+		set_la             => rf_set_la,
+		new_la             => rf_new_la,
+		dec_lc             => rf_dec_lc,
+		set_lc             => rf_set_lc,
+		new_lc             => rf_new_lc
+	);
+
+	-----------------
+	-- BUSES (X,Y,L)
+	-----------------
+	rf_X_bus_wr_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_X_BUS_WR);
+	rf_X_bus_wr_addr  <= pipeline_regs(ST_EXEC-1).x_bus_wr_addr;
+	rf_X_bus_rd_addr  <= pipeline_regs(ST_EXEC-1).x_bus_rd_addr;
+	rf_X_bus_data_in  <= rf_X_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_X_BUS_RD) = '1' else
+	                     pipeline_regs(ST_EXEC-1).RAM_out_x; -- when pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_RD) = '1' else
+
+	rf_Y_bus_wr_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_Y_BUS_WR);
+	rf_Y_bus_wr_addr  <= pipeline_regs(ST_EXEC-1).y_bus_wr_addr;
+	rf_Y_bus_rd_addr  <= pipeline_regs(ST_EXEC-1).y_bus_rd_addr;
+	rf_Y_bus_data_in  <= rf_Y_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_BUS_RD) = '1' else
+	                     pipeline_regs(ST_EXEC-1).RAM_out_y; -- when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_RD) = '1' else
+
+	rf_L_bus_wr_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_WR);
+	rf_L_bus_rd_valid <= pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_RD);
+	rf_L_bus_wr_addr  <= pipeline_regs(ST_EXEC-1).l_bus_addr; -- equal to bits in instruction word
+	rf_L_bus_rd_addr  <= pipeline_regs(ST_EXEC-1).l_bus_addr; -- could be simplified by taking these bits..
+
+	-- writing to the R registers within the ADGEN stage has to be prevented when
+	-- 1) a jump is currently being executed (which is detected in the exec stage)
+	-- 2) stall cycles occur. In this case the write will happen in the last cycle, when we stop stalling.
+	-- 3) a memory access results in a stall (e.g. caused by the instruction to REP)
+	rf_wr_R_port_A_valid <= '0' when stall_flags(ST_ADGEN) = '1' or 
+	                                 exec_bra_modify_pc = '1' or
+	                                 memory_stall = '1' else
+	                        adgen_wr_R_port_A_valid;
+	rf_wr_R_port_B_valid <= '0' when stall_flags(ST_ADGEN) = '1' or 
+	                                 exec_bra_modify_pc = '1' or
+	                                 memory_stall = '1' else
+	                        adgen_wr_R_port_B_valid;
+
+
+	rf_reg_wr_addr <= pipeline_regs(ST_EXEC-1).reg_wr_addr;
+	-- can be set due to
+	-- 1) normal write operation (e.g., move)
+	-- 2) conditional move (Tcc)
+	rf_reg_wr_addr_valid <= '1'              when pipeline_regs(ST_EXEC-1).act_array(ACT_REG_WR) = '1' else
+	                        exec_cc_flag_set when pipeline_regs(ST_EXEC-1).act_array(ACT_REG_WR_CC) = '1' else '0';
+	rf_reg_wr_data <= exec_dst_operand;
+
+	rf_reg_rd_addr <= pipeline_regs(ST_EXEC-1).reg_rd_addr;
+
+	-- Writing from the ALU can depend on the condition code (Tcc) instruction
+	rf_alu_wr_valid <= exec_cc_flag_set when pipeline_regs(ST_EXEC-1).act_array(ACT_ALU_WR_CC) = '1' else
+	                   exec_alu_modify_accu;
+
+	push_stack.valid   <= '1' when exec_bra_push_stack.valid = '1' or exec_loop_push_stack.valid = '1' else '0';
+	push_stack.content <= exec_bra_push_stack.content when exec_bra_push_stack.valid = '1' else
+	                      exec_loop_push_stack.content;
+	-- for jump to subroutine store the pc of the subsequent instruction
+	push_stack.pc <= pipeline_regs(ST_EXEC-2).pc when exec_bra_push_stack.valid = '1' and pipeline_regs(ST_EXEC-1).dble_word_instr = '0' else
+	                 pipeline_regs(ST_EXEC-3).pc when exec_bra_push_stack.valid = '1' and pipeline_regs(ST_EXEC-1).dble_word_instr = '1' else
+					 exec_loop_push_stack.pc     when exec_loop_push_stack.valid = '1' else
+	                 (others => '0');
+
+	pop_stack.valid <= '1' when exec_bra_pop_stack.valid = '1' or exec_loop_pop_stack.valid = '1' else '0';
+
+	rf_set_sr <= '1' when exec_bra_modify_sr = '1' or 
+	                      exec_cr_mod_modify_sr = '1' or 
+	                      exec_loop_modify_sr = '1' or 
+	                      exec_alu_modify_sr = '1' or 
+	                      exec_bit_modify_modify_sr = '1' else '0';
+	rf_new_sr <= exec_bra_modified_sr    when exec_bra_modify_sr = '1'    else 
+	             exec_cr_mod_modified_sr when exec_cr_mod_modify_sr = '1' else
+				 exec_loop_modified_sr   when exec_loop_modify_sr = '1' else
+				 exec_alu_modified_sr    when exec_alu_modify_sr = '1' else
+	             exec_bit_modify_modified_sr; -- when exec_bit_modify_modify_sr = '1' else
+
+	rf_set_omr <= exec_cr_mod_modify_omr;
+	rf_new_omr <= exec_cr_mod_modified_omr;
+	rf_set_lc <= exec_loop_modify_lc;
+	rf_new_lc <= exec_loop_modified_lc;
+	rf_set_la <= exec_loop_modify_la;
+	rf_new_la <= exec_loop_modified_la;
+
+	rf_dec_lc <= '1' when exec_loop_decrement_lc = '1' or fetch_decrement_lc = '1' else '0';
+
+	---------------------
+	-- MEMORY MANAGEMENT 
+	---------------------
+	MMU_inst: memory_management port map (
+		clk => clk,
+		rst => rst,
+		stall_flags   => stall_flags,
+		memory_stall  => memory_stall,
+		data_rom_enable => register_file.omr(2),
+		pmem_ctrl_in  => pmem_ctrl_in,
+		pmem_ctrl_out => pmem_ctrl_out,
+		xmem_ctrl_in  => xmem_ctrl_in,
+		xmem_ctrl_out => xmem_ctrl_out,
+		ymem_ctrl_in  => ymem_ctrl_in,
+		ymem_ctrl_out => ymem_ctrl_out
+	);
+
+	------------------
+	-- Program Memory
+	------------------
+	pmem_ctrl_in.rd_addr <= pc_new;
+	pmem_ctrl_in.rd_en   <= '1' when stall_flags(ST_FETCH) = '0' else '0';
+	-- TODO: Writing to PMEM!
+	pmem_ctrl_in.wr_addr <= (others => '0');
+	pmem_ctrl_in.wr_en   <= '0';
+	pmem_ctrl_in.data_in <= (others => '0');
+
+	pmem_data_out       <= pmem_ctrl_out.data_out;
+	pmem_data_out_valid <= pmem_ctrl_out.data_out_valid;
+
+
+	------------------
+	-- X Memory
+	------------------
+	-- Either take the result of the AGU or use the short absolute value stored in the instruction word
+	xmem_ctrl_in.rd_addr <= adgen_address_out_x when pipeline_regs(ST_ADGEN-1).act_array(ACT_ADGEN) = '1' else
+	                        "0000000000" &  unsigned(pipeline_regs(ST_ADGEN-1).instr_word(13 downto 8));
+	xmem_ctrl_in.rd_en   <=  '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_X_MEM_RD) = '1' else '0';
+	-- Either take the result of the AGU or use the absolute value stored in the instruction word
+	xmem_ctrl_in.wr_addr <= pipeline_regs(ST_EXEC-1).adgen_address_x when pipeline_regs(ST_EXEC-1).act_array(ACT_ADGEN) = '1' else
+	                        "0000000000" & unsigned(pipeline_regs(ST_EXEC-1).instr_word(13 downto 8));
+	xmem_ctrl_in.wr_en   <= '1' when pipeline_regs(ST_EXEC-1).act_array(ACT_X_MEM_WR) = '1' else '0';
+	xmem_ctrl_in.data_in <= rf_X_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_X_BUS_RD) = '1' or 
+	                                               pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_RD) = '1'  else
+	                        exec_dst_operand;
+
+	xmem_data_out       <= xmem_ctrl_out.data_out;
+	xmem_data_out_valid <= xmem_ctrl_out.data_out_valid;
+
+	------------------
+	-- Y Memory
+	------------------
+	-- Either take the result of the AGU or use the absolute value stored in the instruction word
+	ymem_ctrl_in.rd_addr <= adgen_address_out_y when pipeline_regs(ST_ADGEN-1).act_array(ACT_ADGEN) = '1' else
+	                        "0000000000" &  unsigned(pipeline_regs(ST_ADGEN-1).instr_word(13 downto 8));
+	ymem_ctrl_in.rd_en   <=  '1' when pipeline_regs(ST_ADGEN-1).act_array(ACT_Y_MEM_RD) = '1' else '0';
+	-- Either take the result of the AGU or use the absolute value stored in the instruction word
+	ymem_ctrl_in.wr_addr <= pipeline_regs(ST_EXEC-1).adgen_address_y when pipeline_regs(ST_EXEC-1).act_array(ACT_ADGEN) = '1' else
+	                        "0000000000" & unsigned(pipeline_regs(ST_EXEC-1).instr_word(13 downto 8));
+	ymem_ctrl_in.wr_en   <= '1' when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_MEM_WR) = '1' else '0';
+	ymem_ctrl_in.data_in <= rf_Y_bus_data_out when pipeline_regs(ST_EXEC-1).act_array(ACT_Y_BUS_RD) = '1' or
+	                                               pipeline_regs(ST_EXEC-1).act_array(ACT_L_BUS_RD) = '1'  else
+	                        exec_dst_operand;
+
+	ymem_data_out       <= ymem_ctrl_out.data_out;
+	ymem_data_out_valid <= ymem_ctrl_out.data_out_valid;
+
+
+end architecture rtl;
diff --git a/FPGA_quartus_GE/DSP/src/reg_file.vhd b/FPGA_quartus_GE/DSP/src/reg_file.vhd
new file mode 100644
index 0000000..7f3244c
--- /dev/null
+++ b/FPGA_quartus_GE/DSP/src/reg_file.vhd
@@ -0,0 +1,679 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity reg_file is port(
+	clk, rst          : in  std_logic;
+	register_file     : out register_file_type;
+	wr_R_port_A_valid : in  std_logic;
+	wr_R_port_A       : in  addr_wr_port_type;
+	wr_R_port_B_valid : in  std_logic;
+	wr_R_port_B       : in  addr_wr_port_type;
+	alu_wr_valid      : in  std_logic;
+	alu_wr_addr       : in  std_logic;
+	alu_wr_data       : in  signed(55 downto 0);
+	reg_wr_addr       : in  std_logic_vector(5 downto 0);
+	reg_wr_addr_valid : in  std_logic;
+	reg_wr_data       : in  std_Logic_vector(23 downto 0);
+	reg_rd_addr       : in  std_logic_vector(5 downto 0);
+	reg_rd_data       : out std_Logic_vector(23 downto 0);
+	X_bus_rd_addr     : in  std_logic_vector(1 downto 0);
+	X_bus_data_out    : out std_logic_vector(23 downto 0);
+	X_bus_wr_addr     : in  std_logic_vector(1 downto 0);
+	X_bus_wr_valid    : in  std_logic;
+	X_bus_data_in     : in  std_logic_vector(23 downto 0);
+	Y_bus_rd_addr     : in  std_logic_vector(1 downto 0);
+	Y_bus_data_out    : out std_logic_vector(23 downto 0);
+	Y_bus_wr_addr     : in  std_logic_vector(1 downto 0);
+	Y_bus_wr_valid    : in  std_logic;
+	Y_bus_data_in     : in  std_logic_vector(23 downto 0);
+	L_bus_rd_addr     : in  std_logic_vector(2 downto 0);
+	L_bus_rd_valid    : in  std_logic;
+	L_bus_wr_addr     : in  std_logic_vector(2 downto 0);
+	L_bus_wr_valid    : in  std_logic;
+	push_stack        : in  push_stack_type;
+	pop_stack         : in  pop_stack_type;
+	set_sr            : in  std_logic;
+	new_sr            : in  std_logic_vector(15 downto 0);
+	set_omr           : in  std_logic;
+	new_omr           : in  std_logic_vector(7 downto 0);
+	dec_lc            : in  std_logic;
+	set_lc            : in  std_logic;
+	new_lc            : in  unsigned(15 downto 0);
+	set_la            : in  std_logic;
+	new_la            : in  unsigned(BW_ADDRESS-1 downto 0)
+);
+end entity;
+
+
+architecture rtl of reg_file is
+
+	signal addr_r : addr_array;
+	signal addr_m : addr_array;
+	signal addr_n : addr_array;
+
+	signal loop_address : unsigned(BW_ADDRESS-1 downto 0);
+	signal loop_counter : unsigned(15 downto 0);
+
+	-- condition code register
+	signal ccr : std_logic_vector(7 downto 0);
+	-- mode register
+	signal mr  : std_logic_vector(7 downto 0);
+	-- status register = mode register + condition code register
+	signal sr  : std_logic_vector(15 downto 0);
+	-- operation mode register
+	signal omr : std_logic_vector(7 downto 0);
+
+	signal stack_pointer    : unsigned(5 downto 0);
+	signal system_stack_ssh : stack_array_type;
+	signal system_stack_ssl : stack_array_type;
+
+	signal x0 : signed(23 downto 0);
+	signal x1 : signed(23 downto 0);
+	signal y0 : signed(23 downto 0);
+	signal y1 : signed(23 downto 0);
+
+	signal a0 : signed(23 downto 0);
+	signal a1 : signed(23 downto 0);
+	signal a2 : signed(7 downto 0);
+
+	signal b0 : signed(23 downto 0);
+	signal b1 : signed(23 downto 0);
+	signal b2 : signed(7 downto 0);
+	
+	signal limited_a1 : signed(23 downto 0);
+	signal limited_b1 : signed(23 downto 0);
+	signal limited_a0 : signed(23 downto 0);
+	signal limited_b0 : signed(23 downto 0);
+	signal set_limiting_flag  : std_logic;
+	signal X_bus_rd_limited_a : std_logic;
+	signal X_bus_rd_limited_b : std_logic;
+	signal Y_bus_rd_limited_a : std_logic;
+	signal Y_bus_rd_limited_b : std_logic;
+	signal reg_rd_limited_a   : std_logic;
+	signal reg_rd_limited_b   : std_logic;
+	signal rd_limited_a       : std_logic;
+	signal rd_limited_b       : std_logic;
+
+begin
+
+
+
+	sr <= mr & ccr;
+
+	register_file.addr_r <= addr_r;
+	register_file.addr_n <= addr_n;
+	register_file.addr_m <= addr_m;
+	register_file.lc <= loop_counter;
+	register_file.la <= loop_address;
+	register_file.ccr <= ccr;
+	register_file.mr <= mr;
+	register_file.sr <= sr;
+	register_file.omr <= omr;
+	register_file.stack_pointer <= stack_pointer;
+	register_file.current_ssh <= system_stack_ssh(to_integer(stack_pointer(3 downto 0)));
+	register_file.current_ssl <= system_stack_ssl(to_integer(stack_pointer(3 downto 0)));
+	register_file.a  <= a2 & a1 & a0;
+	register_file.b  <= b2 & b1 & b0;
+	register_file.x0 <= x0;
+	register_file.x1 <= x1;
+	register_file.y0 <= y0;
+	register_file.y1 <= y1;
+
+
+	global_register_file: process(clk) is
+		variable stack_pointer_plus_1 : unsigned(3 downto 0);
+		variable reg_addr : integer range 0 to 7;
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				addr_r <= (others => (others => '0'));
+				addr_n <= (others => (others => '0'));
+				addr_m <= (others => (others => '1'));
+				ccr    <= (others => '0');
+				mr     <= (others => '0');
+				omr    <= (others => '0');
+				system_stack_ssl <= (others => (others => '0'));
+				system_stack_ssh <= (others => (others => '0'));
+				stack_pointer    <= (others => '0');
+				loop_counter <= (others => '0');
+				loop_address <= (others => '0');
+				x0 <= (others => '0');
+				x1 <= (others => '0');
+				y0 <= (others => '0');
+				y1 <= (others => '0');
+				a0 <= (others => '0');
+				a1 <= (others => '0');
+				a2 <= (others => '0');
+				b0 <= (others => '0');
+				b1 <= (others => '0');
+				b2 <= (others => '0');
+			else
+				reg_addr := to_integer(unsigned(reg_wr_addr(2 downto 0)));
+				-----------------------------------------------------------------------
+				-- General write port to register file using 6 bit addressing scheme
+				-----------------------------------------------------------------------
+				if reg_wr_addr_valid = '1' then
+					case reg_wr_addr(5 downto 3) is
+						-- X0, X1, Y0, Y1
+						when "000" =>
+							case reg_wr_addr(2 downto 0) is
+								when "100" =>
+									x0 <= signed(reg_wr_data);
+								when "101" =>
+									x1 <= signed(reg_wr_data);
+								when "110" =>
+									y0 <= signed(reg_wr_data);
+								when "111" =>
+									y1 <= signed(reg_wr_data);
+								when others =>
+							end case;
+
+						-- A0, B0, A2, B2, A1, B1, A, B
+						when "001" =>
+							case reg_wr_addr(2 downto 0) is
+								when "000" =>
+									a0 <= signed(reg_wr_data);
+								when "001" =>
+									b0 <= signed(reg_wr_data);
+								when "010" =>
+									a2 <= signed(reg_wr_data(7 downto 0));
+								when "011" =>
+									b2 <= signed(reg_wr_data(7 downto 0));
+								when "100" =>
+									a1 <= signed(reg_wr_data);
+								when "101" =>
+									b1 <= signed(reg_wr_data);
+								when "110" =>
+									a2 <= (others => reg_wr_data(23));
+									a1 <= signed(reg_wr_data);
+									a0 <= (others => '0');
+								when "111" =>
+									b2 <= (others => reg_wr_data(23));
+									b1 <= signed(reg_wr_data);
+									b0 <= (others => '0');
+								when others =>
+							end case;
+
+						-- R0-R7
+						when "010" =>
+							addr_r(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0));
+
+						-- N0-N7
+						when "011" =>
+							addr_n(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0));
+
+						-- M0-M7
+						when "100" =>
+							addr_m(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0));
+
+						-- SR, OMR, SP, SSH, SSL, LA, LC
+						when "111" =>
+							case reg_wr_addr(2 downto 0) is
+								-- SR
+								when "001" =>
+									mr  <= reg_wr_data(15 downto 8);
+									ccr <= reg_wr_data( 7 downto 0);
+
+								-- OMR
+								when "010" =>
+									omr  <= reg_wr_data(7 downto 0);
+
+								-- SP
+								when "011" =>
+									stack_pointer <= unsigned(reg_wr_data(5 downto 0));
+
+								-- SSH
+								when "100" =>
+									system_stack_ssh(to_integer(stack_pointer_plus_1)) <= reg_wr_data(BW_ADDRESS-1 downto 0);
+									-- increase stack after writing
+									stack_pointer(3 downto 0) <= stack_pointer_plus_1;
+									-- test whether stack is full, if so set the stack error flag (SE)
+									if stack_pointer(3 downto 0) = "1111" then
+										stack_pointer(4) <= '1';
+									end if;
+
+								-- SSL
+								when "101" =>
+									system_stack_ssl(to_integer(stack_pointer)) <= reg_wr_data(BW_ADDRESS-1 downto 0);
+
+								-- LA
+								when "110" =>
+									loop_address <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0));
+
+								-- LC
+								when "111" =>
+									loop_counter <= unsigned(reg_wr_data(15 downto 0));
+
+								when others =>
+							end case;
+						when others =>
+					end case;
+				end if;
+
+				----------------
+				-- X BUS Write
+				----------------
+				if X_bus_wr_valid = '1' then
+					case X_bus_wr_addr is
+						when "00" =>
+							x0 <= signed(X_bus_data_in);
+						when "01" =>
+							x1 <= signed(X_bus_data_in);
+						when "10" =>
+							a2 <= (others => X_bus_data_in(23));
+							a1 <= signed(X_bus_data_in);
+							a0 <= (others => '0');
+						when others =>
+							b2 <= (others => X_bus_data_in(23));
+							b1 <= signed(X_bus_data_in);
+							b0 <= (others => '0');
+					end case;
+				end if;
+				----------------
+				-- Y BUS Write
+				----------------
+				if Y_bus_wr_valid = '1' then
+					case Y_bus_wr_addr is
+						when "00" =>
+							y0 <= signed(Y_bus_data_in);
+						when "01" =>
+							y1 <= signed(Y_bus_data_in);
+						when "10" =>
+							a2 <= (others => Y_bus_data_in(23));
+							a1 <= signed(Y_bus_data_in);
+							a0 <= (others => '0');
+						when others =>
+							b2 <= (others => Y_bus_data_in(23));
+							b1 <= signed(Y_bus_data_in);
+							b0 <= (others => '0');
+					end case;
+				end if;
+				------------------
+				-- L BUS Write
+				------------------
+				if L_bus_wr_valid = '1' then
+					case L_bus_wr_addr is
+						-- A10
+						when "000" =>
+							a1 <= signed(X_bus_data_in);
+							a0 <= signed(Y_bus_data_in);
+						-- B10
+						when "001" =>
+							b1 <= signed(X_bus_data_in);
+							b0 <= signed(Y_bus_data_in);
+						-- X
+						when "010" =>
+							x1 <= signed(X_bus_data_in);
+							x0 <= signed(Y_bus_data_in);
+						-- Y
+						when "011" =>
+							y1 <= signed(X_bus_data_in);
+							y0 <= signed(Y_bus_data_in);
+						-- A
+						when "100" =>
+							a2 <= (others => X_bus_data_in(23));
+							a1 <= signed(X_bus_data_in);
+							a0 <= signed(Y_bus_data_in);
+						-- B
+						when "101" =>
+							b2 <= (others => X_bus_data_in(23));
+							b1 <= signed(X_bus_data_in);
+							b0 <= signed(Y_bus_data_in);
+						-- AB
+						when "110" =>
+							a2 <= (others => X_bus_data_in(23));
+							a1 <= signed(X_bus_data_in);
+							a0 <= (others => '0');
+							b2 <= (others => Y_bus_data_in(23));
+							b1 <= signed(Y_bus_data_in);
+							b0 <= (others => '0');
+						-- BA
+						when others =>
+							a2 <= (others => Y_bus_data_in(23));
+							a1 <= signed(Y_bus_data_in);
+							a0 <= (others => '0');
+							b2 <= (others => X_bus_data_in(23));
+							b1 <= signed(X_bus_data_in);
+							b0 <= (others => '0');
+					end case;
+				end if;
+
+				---------------------
+				-- STATUS REGISTERS
+				---------------------
+				if set_sr = '1' then
+					ccr <= new_sr( 7 downto 0);
+					mr  <= new_sr(15 downto 8);
+				end if;
+				if set_omr = '1' then
+					omr <= new_omr;
+				end if;
+				-- data limiter active?
+				-- listing this statement after the set_sr test results
+				-- in the correct behaviour for ALU operations with parallel move
+				if set_limiting_flag = '1' then
+					ccr(6) <= '1';
+				end if;
+
+				--------------------
+				-- LOOP REGISTERS 
+				--------------------
+				if set_la = '1' then
+					loop_address <= new_la;
+				end if;
+				if set_lc = '1' then
+					loop_counter <= new_lc;
+				end if;
+				if dec_lc = '1' then
+					loop_counter <= loop_counter - 1;
+				end if;
+
+				---------------------
+				-- ADDRESS REGISTER
+				---------------------
+				if wr_R_port_A_valid = '1' then
+					addr_r(to_integer(wr_R_port_A.reg_number)) <= wr_R_port_A.reg_value;
+				end if;
+				if wr_R_port_B_valid = '1' then
+					addr_r(to_integer(wr_R_port_B.reg_number)) <= wr_R_port_B.reg_value;
+				end if;
+
+				-------------------------
+				-- ALU ACCUMULATOR WRITE
+				-------------------------
+				if alu_wr_valid = '1' then
+					if alu_wr_addr = '0' then
+						a2 <= alu_wr_data(55 downto 48);
+						a1 <= alu_wr_data(47 downto 24);
+						a0 <= alu_wr_data(23 downto  0);
+					else
+						b2 <= alu_wr_data(55 downto 48);
+						b1 <= alu_wr_data(47 downto 24);
+						b0 <= alu_wr_data(23 downto  0);
+					end if;
+				end if;
+
+				---------------------
+				-- STACK CONTROLLER 
+				---------------------
+				stack_pointer_plus_1 := stack_pointer(3 downto 0) + 1;
+				if push_stack.valid = '1' then
+					-- increase stack after writing
+					stack_pointer(3 downto 0) <= stack_pointer_plus_1;
+					-- test whether stack is full, if so set the stack error flag (SE)
+					if stack_pointer(3 downto 0) = "1111" then
+						stack_pointer(4) <= '1';
+					end if;
+					case push_stack.content is
+						when PC =>
+							system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(push_stack.pc);
+
+						when PC_AND_SR =>
+							system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(push_stack.pc);
+							system_stack_ssl(to_integer(stack_pointer_plus_1)) <= SR;
+
+						when LA_AND_LC =>
+							system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(loop_address);
+							system_stack_ssl(to_integer(stack_pointer_plus_1)) <= std_logic_vector(loop_counter);
+
+					end case;
+				end if;
+
+				-- decrease stack pointer
+				if pop_stack.valid = '1' then
+					stack_pointer(3 downto 0) <= stack_pointer(3 downto 0) - 1;
+					-- if stack is empty set the underflow flag (bit 5, UF) and the stack error flag (bit 4, SE)
+					if stack_pointer(3 downto 0) = "0000" then
+						stack_pointer(5) <= '1';
+						stack_pointer(4) <= '1';
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+
+	x_bus_rd_port: process(X_bus_rd_addr,x0,x1,a1,b1,limited_a1,limited_b1,
+	                       L_bus_rd_addr,L_bus_rd_valid,y1) is
+	begin
+		X_bus_rd_limited_a <= '0';
+		X_bus_rd_limited_b <= '0';
+		case X_bus_rd_addr is
+			when "00" =>   X_bus_data_out <= std_logic_vector(x0);
+			when "01" =>   X_bus_data_out <= std_logic_vector(x1);
+			when "10" =>   X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1';
+			when others => X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1';
+		end case;
+		if L_bus_rd_valid = '1' then
+			case L_bus_rd_addr is
+				when "000" =>  X_bus_data_out <= std_logic_vector(a1);
+				when "001" =>  X_bus_data_out <= std_logic_vector(b1);
+				when "010" =>  X_bus_data_out <= std_logic_vector(x1);
+				when "011" =>  X_bus_data_out <= std_logic_vector(y1);
+				when "100" =>  X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1';
+				when "101" =>  X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1';
+				when "110" =>  X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1';
+				when others => X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1';
+			end case;
+		end if;
+	end process x_bus_rd_port;
+
+	y_bus_rd_port: process(Y_bus_rd_addr,y0,y1,a1,b1,limited_a1,limited_b1,
+	                       L_bus_rd_addr,L_bus_rd_valid,a0,b0,x0,limited_a0,limited_b0) is
+	begin
+		Y_bus_rd_limited_a <= '0';
+		Y_bus_rd_limited_b <= '0';
+		case Y_bus_rd_addr is
+			when "00" =>   Y_bus_data_out <= std_logic_vector(y0);
+			when "01" =>   Y_bus_data_out <= std_logic_vector(y1);
+			when "10" =>   Y_bus_data_out <= std_logic_vector(limited_a1); Y_bus_rd_limited_a <= '1';
+			when others => Y_bus_data_out <= std_logic_vector(limited_b1); Y_bus_rd_limited_b <= '1';
+		end case;
+		if L_bus_rd_valid = '1' then
+			case L_bus_rd_addr is
+				when "000" =>  Y_bus_data_out <= std_logic_vector(a0);
+				when "001" =>  Y_bus_data_out <= std_logic_vector(b0);
+				when "010" =>  Y_bus_data_out <= std_logic_vector(x0);
+				when "011" =>  Y_bus_data_out <= std_logic_vector(y0);
+				when "100" =>  Y_bus_data_out <= std_logic_vector(limited_a0); Y_bus_rd_limited_a <= '1';
+				when "101" =>  Y_bus_data_out <= std_logic_vector(limited_b0); Y_bus_rd_limited_b <= '1';
+				when "110" =>  Y_bus_data_out <= std_logic_vector(limited_b1); Y_bus_rd_limited_b <= '1';
+				when others => Y_bus_data_out <= std_logic_vector(limited_a1); Y_bus_rd_limited_a <= '1';
+			end case;
+		end if;
+	end process y_bus_rd_port;
+
+
+	reg_rd_port: process(reg_rd_addr, x0,x1,y0,y1,a0,a1,a2,b0,b1,b2,
+	                     omr,ccr,mr,addr_r,addr_n,addr_m,stack_pointer,
+	                     loop_address,loop_counter,system_stack_ssl,system_stack_ssh) is
+		variable reg_addr : integer range 0 to 7;
+	begin
+		reg_addr := to_integer(unsigned(reg_rd_addr(2 downto 0)));
+		reg_rd_data <= (others => '0');
+		reg_rd_limited_a <= '0';
+		reg_rd_limited_b <= '0';
+
+		case reg_rd_addr(5 downto 3) is
+			-- X0, X1, Y0, Y1
+			when "000" =>
+				case reg_rd_addr(2 downto 0) is
+					when "100" =>
+						reg_rd_data <= std_logic_vector(x0);
+					when "101" =>
+						reg_rd_data <= std_logic_vector(x1);
+					when "110" =>
+						reg_rd_data <= std_logic_vector(y0);
+					when "111" =>
+						reg_rd_data <= std_logic_vector(y1);
+					when others =>
+				end case;
+
+			-- A0, B0, A2, B2, A1, B1, A, B
+			when "001" =>
+				case reg_rd_addr(2 downto 0) is
+					when "000" =>
+						reg_rd_data <= std_logic_vector(a0);
+					when "001" =>
+						reg_rd_data <= std_logic_vector(b0);
+					when "010" =>
+						-- MSBs are read as zero!
+						reg_rd_data(23 downto 8) <= (others => '0');
+						reg_rd_data(7 downto 0) <= std_logic_vector(a2);
+					when "011" =>
+						-- MSBs are read as zero!
+						reg_rd_data(23 downto 8) <= (others => '0');
+						reg_rd_data(7 downto 0) <= std_logic_vector(b2);
+					when "100" =>
+						reg_rd_data <= std_logic_vector(a1);
+					when "101" =>
+						reg_rd_data <= std_logic_vector(b1);
+					when "110" =>
+						reg_rd_data <= std_logic_vector(limited_a1);
+						reg_rd_limited_a <= '1';
+					when "111" =>
+						reg_rd_data <= std_logic_vector(limited_b1);
+						reg_rd_limited_b <= '1';
+					when others =>
+				end case;
+
+			-- R0-R7
+			when "010" =>
+				reg_rd_data <= std_logic_vector(resize(addr_r(reg_addr), 24));
+
+			-- N0-N7
+			when "011" =>
+				reg_rd_data <= std_logic_vector(resize(addr_n(reg_addr), 24));
+
+			-- M0-M7
+			when "100" =>
+				reg_rd_data <= std_logic_vector(resize(addr_m(reg_addr), 24));
+
+			-- SR, OMR, SP, SSH, SSL, LA, LC
+			when "111" =>
+				case reg_wr_addr(2 downto 0) is
+					-- SR
+					when "001" =>
+						reg_rd_data(23 downto 16) <= (others => '0');
+						reg_rd_data(15 downto  0) <= mr & ccr;
+
+					-- OMR
+					when "010" =>
+						reg_rd_data(23 downto 8) <= (others => '0');
+						reg_rd_data( 7 downto 0) <= omr;
+
+					-- SP
+					when "011" =>
+						reg_rd_data(23 downto 6) <= (others => '0');
+						reg_rd_data(5 downto 0) <= std_logic_vector(stack_pointer);
+
+					-- SSH
+					when "100" =>
+-- TODO!
+--						system_stack_ssh(to_integer(stack_pointer_plus_1)) <= reg_wr_data(BW_ADDRESS-1 downto 0);
+--						-- increase stack after writing
+--						stack_pointer(3 downto 0) <= stack_pointer_plus_1;
+--						-- test whether stack is full, if so set the stack error flag (SE)
+--						if stack_pointer(3 downto 0) = "1111" then
+--							stack_pointer(4) <= '1';
+--						end if;
+
+					-- SSL
+					when "101" =>
+						reg_rd_data <= (others => '0');
+						reg_rd_data(BW_ADDRESS-1 downto 0) <= std_logic_vector(system_stack_ssl(to_integer(stack_pointer)));
+
+					-- LA
+					when "110" =>
+						reg_rd_data <= (others => '0');
+						reg_rd_data(BW_ADDRESS-1 downto 0) <= std_logic_vector(loop_address);
+
+					-- LC
+					when "111" =>
+						reg_rd_data <= (others => '0');
+						reg_rd_data(15 downto 0) <= std_logic_vector(loop_counter);
+
+					when others =>
+				end case;
+			when others =>
+		end case;
+	end process;
+
+	rd_limited_a <= '1' when reg_rd_limited_a = '1' or X_bus_rd_limited_a = '1' or Y_bus_rd_limited_a = '1' else '0';
+	rd_limited_b <= '1' when reg_rd_limited_b = '1' or X_bus_rd_limited_b = '1' or Y_bus_rd_limited_b = '1' else '0';
+
+	data_shifter_limiter: process(a2,a1,a0,b2,b1,b0,sr,rd_limited_a,rd_limited_b) is
+		variable scaled_a : signed(55 downto 0);
+		variable scaled_b : signed(55 downto 0);
+	begin
+
+		set_limiting_flag <= '0';
+		-----------------
+		-- DATA SCALING
+		-----------------
+		-- test against scaling bits S1, S0
+		case sr(11 downto 10) is
+			-- scale down (right shift)
+			when "01" =>
+				scaled_a := a2(7) & a2 & a1 & a0(23 downto 1);
+				scaled_b := b2(7) & b2 & b1 & b0(23 downto 1);
+			-- scale up (arithmetic left shift)
+			when "10" =>
+				scaled_a := a2(6 downto 0) & a1 & a0 & '0';
+				scaled_b := b2(6 downto 0) & b1 & b0 & '0';
+			-- "00" do not scale!
+			when others =>
+				scaled_a := a2 & a1 & a0;
+				scaled_b := b2 & b1 & b0;
+		end case;
+
+		-- only sign extension stored in a2?
+		-- Yes: No limiting needed!
+		if scaled_a(55 downto 47) = "111111111" or scaled_a(55 downto 47) = "000000000" then
+			limited_a1 <= scaled_a(47 downto 24);
+			limited_a0 <= scaled_a(23 downto  0);
+		else
+			-- positive value in a?
+			if scaled_a(55) = '0' then
+				limited_a1 <= X"7FFFFF";
+				limited_a0 <= X"FFFFFF";
+			-- negative value in a?
+			else
+				limited_a1 <= X"800000";
+				limited_a0 <= X"000000";
+			end if;
+			-- set the limit flag in the status register
+			if rd_limited_a = '1' then
+				set_limiting_flag <= '1';
+			end if;
+		end if;
+		-- only sign extension stored in b2?
+		-- Yes: No limiting needed!
+		if scaled_b(55 downto 47) = "111111111" or scaled_b(55 downto 47) = "000000000" then
+			limited_b1 <= scaled_b(47 downto 24);
+			limited_b0 <= scaled_b(23 downto  0);
+		else
+			-- positive value in b?
+			if scaled_b(55) = '0' then
+				limited_b1 <= X"7FFFFF";
+				limited_b0 <= X"FFFFFF";
+			-- negative value in b?
+			else
+				limited_b1 <= X"800000";
+				limited_b0 <= X"000000";
+			end if;
+			-- set the limit flag in the status register
+			if rd_limited_b = '1' then
+				set_limiting_flag <= '1';
+			end if;
+		end if;
+
+	end process;
+
+
+end architecture rtl;
diff --git a/FPGA_quartus_GE/DSP/src/types_pkg.vhd b/FPGA_quartus_GE/DSP/src/types_pkg.vhd
new file mode 100644
index 0000000..131f7fa
--- /dev/null
+++ b/FPGA_quartus_GE/DSP/src/types_pkg.vhd
@@ -0,0 +1,167 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+
+
+
+package types_pkg is
+
+	-- the different addressing modes
+	type adgen_mode_type is (NOP, POST_MIN_N, POST_PLUS_N, POST_MIN_1, POST_PLUS_1, INDEXED_N, PRE_MIN_1, ABSOLUTE, IMMEDIATE);
+	------------------------
+	-- Decoded instructions
+	------------------------
+	type instructions_type is (
+	INSTR_NOP     ,
+	INSTR_RTI     ,
+	INSTR_ILLEGAL ,
+	INSTR_SWI     ,
+	INSTR_RTS     ,
+	INSTR_RESET   ,
+	INSTR_WAIT    ,
+	INSTR_STOP    ,
+	INSTR_ENDDO   ,
+	INSTR_ANDI    ,
+	INSTR_ORI     ,
+	INSTR_DIV     ,
+	INSTR_NORM    ,
+	INSTR_LUA     ,
+	INSTR_MOVEC   ,
+	INSTR_REP     ,
+	INSTR_DO      ,
+	INSTR_MOVEM   ,
+	INSTR_MOVEP   ,
+	INSTR_PM_MOVEM,
+	INSTR_BCLR    ,
+	INSTR_BSET    ,
+	INSTR_JCLR    ,
+	INSTR_JSET    ,
+	INSTR_JMP     ,
+	INSTR_JCC     ,
+	INSTR_BCHG    ,
+	INSTR_BTST    ,
+	INSTR_JSCLR   ,
+	INSTR_JSSET   ,
+	INSTR_JSR     ,
+	INSTR_JSCC    );
+
+	type addr_array is array(0 to 7) of unsigned(BW_ADDRESS-1 downto 0);
+
+	type alu_shift_mode is (NO_SHIFT, SHIFT_LEFT, SHIFT_RIGHT, ZEROS);
+	type alu_ccr_flag is (DONT_TOUCH, CLEAR, MODIFY, SET);
+	type alu_ccr_flag_array is array(7 downto 0) of alu_ccr_flag;
+
+	type alu_ctrl_type is record
+		mul_op1 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1
+		mul_op2 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1
+		shift_src  : std_logic; -- a,b
+		shift_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved
+		shift_mode : alu_shift_mode;
+		rotate     : std_logic;  -- 0: logical shift, 1: rotate shift
+		add_src_stage_1  : std_logic_vector(2 downto 0); -- x0,x1,y0,y1,x,y,a,b
+		add_src_stage_2  : std_logic_vector(1 downto 0); -- 00: 0 , 01: add_src_1, 10: mul_result, 11: reserved
+		add_src_sign   : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved
+		logic_function : std_logic_vector(2 downto 0);  -- 000: none, 001: and, 010: or, 011: eor, 100: not
+		word_24_update : std_logic;  -- only accumulator bits 47 downto 24 affected?
+		rounding_used  : std_logic_vector(1 downto 0); -- 00: no rounding, 01: rounding, 10: add carry, 11: subtract carry
+		store_result   : std_logic; -- 0: do not update accumulator, 1: update accumulator
+		dst_accu       : std_logic; -- 0: a, 1: b
+		div_instr      : std_logic; -- DIV instruction? Special ALU operations needed!
+		norm_instr     : std_logic; -- NORM instruction? Special ALU operations needed!
+		ccr_flags_ctrl : alu_ccr_flag_array;
+	end record;
+
+	type pipeline_signals is record
+		instr_word: std_logic_vector(23 downto 0);
+		pc        : unsigned(BW_ADDRESS-1 downto 0);
+		dble_word_instr : std_logic;
+		instr_array     : instructions_type;
+		act_array       : std_logic_vector(NUM_ACT_SIGNALS-1 downto 0);
+		dec_activate    : std_logic;
+		adgen_mode_a    : adgen_mode_type;
+		adgen_mode_b    : adgen_mode_type;
+		reg_wr_addr     : std_logic_vector(5 downto 0);
+		reg_rd_addr     : std_logic_vector(5 downto 0);
+		x_bus_rd_addr   : std_logic_vector(1 downto 0);
+		x_bus_wr_addr   : std_logic_vector(1 downto 0);
+		y_bus_rd_addr   : std_logic_vector(1 downto 0);
+		y_bus_wr_addr   : std_logic_vector(1 downto 0);
+		l_bus_addr      : std_logic_vector(2 downto 0);
+		adgen_address_x : unsigned(BW_ADDRESS-1 downto 0);
+		adgen_address_y : unsigned(BW_ADDRESS-1 downto 0);
+		RAM_out_x       : std_logic_vector(23 downto 0);
+		RAM_out_y       : std_logic_vector(23 downto 0);
+		alu_ctrl        : alu_ctrl_type;
+	end record;
+
+	type pipeline_type is array(0 to PIPELINE_DEPTH-1) of pipeline_signals;
+
+
+	type register_file_type is record 
+		a            : signed(55 downto 0);
+		b            : signed(55 downto 0);
+		x0           : signed(23 downto 0);
+		x1           : signed(23 downto 0);
+		y0           : signed(23 downto 0);
+		y1           : signed(23 downto 0);
+		la           : unsigned(BW_ADDRESS-1 downto 0);
+		lc           : unsigned(15 downto 0);
+		addr_r       : addr_array;
+		addr_n       : addr_array;
+		addr_m       : addr_array;
+		ccr          : std_logic_vector(7 downto 0);
+		mr           : std_logic_vector(7 downto 0);
+		sr           : std_logic_vector(15 downto 0);
+		omr          : std_logic_vector(7 downto 0);
+		stack_pointer    : unsigned(5 downto 0);
+--		system_stack_ssh : stack_array_type;
+--		system_stack_ssl : stack_array_type;
+		current_ssh      : std_logic_vector(BW_ADDRESS-1 downto 0);
+		current_ssl      : std_logic_vector(BW_ADDRESS-1 downto 0);
+
+	end record;
+
+	type addr_wr_port_type is record
+--		write_valid : std_logic;
+		reg_number  : unsigned(2 downto 0);
+		reg_value   : unsigned(15 downto 0);
+	end record;
+
+	type mem_ctrl_type_in is record
+		rd_addr   : unsigned(BW_ADDRESS-1 downto 0);
+		rd_en     : std_logic;
+		wr_addr   : unsigned(BW_ADDRESS-1 downto 0);
+		wr_en     : std_logic;
+		data_in   : std_logic_vector(23 downto 0);
+	end record;
+
+	type mem_ctrl_type_out is record
+		data_out       : std_logic_vector(23 downto 0);
+		data_out_valid : std_logic;
+	end record;
+
+	type memory_type is (X_MEM, Y_MEM, P_MEM);
+	---------------
+	-- STACK TYPES
+	---------------
+	type stack_array_type is array(0 to 15) of std_logic_vector(BW_ADDRESS-1 downto 0);
+
+	type push_stack_content_type is (PC, PC_AND_SR, LA_AND_LC);
+
+	type push_stack_type is record
+		valid   : std_logic;
+		pc      : unsigned(BW_ADDRESS-1 downto 0);
+		content : push_stack_content_type;
+	end record;
+
+--	type pop_stack_content_type is (PC, PC_AND_SR, SR, LA_AND_LC);
+
+--	type pop_stack_type is std_logic;
+	type pop_stack_type is record
+		valid : std_logic;
+--		content : pop_stack_content_type;
+	end record;
+
+end package types_pkg;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
new file mode 100644
index 0000000..b2b8dbb
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
@@ -0,0 +1,971 @@
+-- WARNING: Do NOT edit the input and output ports in this file in a text
+-- editor if you plan to continue editing the block that represents it in
+-- the Block Editor! File corruption is VERY likely to occur.
+
+-- Copyright (C) 1991-2008 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+
+-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
+-- Created on Tue Sep 08 16:24:20 2009
+
+library work;
+use work.FalconIO_SDCard_IDE_CF_pkg.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+
+--  Entity Declaration
+
+
+--  Entity Declaration
+
+ENTITY FalconIO_SDCard_IDE_CF IS
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	PORT
+	(
+		CLK33M : IN STD_LOGIC;
+		MAIN_CLK : IN STD_LOGIC;
+		CLK2M : IN STD_LOGIC;
+		CLK500k : IN STD_LOGIC;
+		nFB_CS1 : IN STD_LOGIC;
+		FB_SIZE0 : IN STD_LOGIC;
+		FB_SIZE1 : IN STD_LOGIC;
+		nFB_BURST : IN STD_LOGIC;
+		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
+		LP_BUSY : IN STD_LOGIC;
+		nACSI_DRQ : IN STD_LOGIC;
+		nACSI_INT : IN STD_LOGIC;
+		nSCSI_DRQ : IN STD_LOGIC;
+		nSCSI_MSG : IN STD_LOGIC;
+		MIDI_IN : IN STD_LOGIC;
+		RxD : IN STD_LOGIC;
+		CTS : IN STD_LOGIC;
+		RI : IN STD_LOGIC;
+		DCD : IN STD_LOGIC;
+		AMKB_RX : IN STD_LOGIC;
+		PIC_AMKB_RX : IN STD_LOGIC;
+		IDE_RDY : IN STD_LOGIC;
+		IDE_INT : IN STD_LOGIC;
+		WP_CS_CARD : IN STD_LOGIC;
+		nINDEX : IN STD_LOGIC;
+		TRACK00 : IN STD_LOGIC;
+		nRD_DATA : IN STD_LOGIC;
+		nDCHG : IN STD_LOGIC;
+		SD_DATA0 : IN STD_LOGIC;
+		SD_DATA1 : IN STD_LOGIC;
+		SD_DATA2 : IN STD_LOGIC;
+		SD_CARD_DEDECT : IN STD_LOGIC;
+		SD_WP : IN STD_LOGIC;
+		nDACK0 : IN STD_LOGIC;
+		nFB_WR : INOUT STD_LOGIC;
+		WP_CF_CARD : IN STD_LOGIC;
+		nWP : IN STD_LOGIC;
+		nFB_CS2 : IN STD_LOGIC;
+		nRSTO : IN STD_LOGIC;
+		HD_DD : IN STD_LOGIC;
+		nSCSI_C_D : IN STD_LOGIC;
+		nSCSI_I_O : IN STD_LOGIC;
+		CLK2M4576 : IN STD_LOGIC;
+		nFB_OE : IN STD_LOGIC;
+		VSYNC : IN STD_LOGIC;
+		HSYNC : IN STD_LOGIC;
+		DSP_INT : IN STD_LOGIC;
+		nBLANK : IN STD_LOGIC;
+		FDC_CLK : IN STD_LOGIC;
+		FB_ALE : IN STD_LOGIC;
+		ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24);
+		nIDE_CS1 : OUT STD_LOGIC;
+		nIDE_CS0 : OUT STD_LOGIC;
+		LP_STR : OUT STD_LOGIC;
+		LP_DIR : OUT STD_LOGIC;
+		nACSI_ACK : OUT STD_LOGIC;
+		nACSI_RESET : OUT STD_LOGIC;
+		nACSI_CS : OUT STD_LOGIC;
+		ACSI_DIR : OUT STD_LOGIC;
+		ACSI_A1 : OUT STD_LOGIC;
+		nSCSI_ACK : OUT STD_LOGIC;
+		nSCSI_ATN : OUT STD_LOGIC;
+		SCSI_DIR : OUT STD_LOGIC;
+		SD_CLK : OUT STD_LOGIC;
+		YM_QA : OUT STD_LOGIC;
+		YM_QC : OUT STD_LOGIC;
+		YM_QB : OUT STD_LOGIC;
+		nSDSEL : OUT STD_LOGIC;
+		STEP : OUT STD_LOGIC;
+		MOT_ON : OUT STD_LOGIC;
+		nRP_LDS : OUT STD_LOGIC;
+		nRP_UDS : OUT STD_LOGIC;
+		nROM4 : OUT STD_LOGIC;
+		nROM3 : OUT STD_LOGIC;
+		nCF_CS1 : OUT STD_LOGIC;
+		nCF_CS0 : OUT STD_LOGIC;
+		nIDE_RD : INOUT STD_LOGIC;
+		nIDE_WR : INOUT STD_LOGIC;
+		AMKB_TX : OUT STD_LOGIC;
+		IDE_RES : OUT STD_LOGIC;
+		DTR : OUT STD_LOGIC;
+		RTS : OUT STD_LOGIC;
+		TxD : OUT STD_LOGIC;
+		MIDI_OLR : OUT STD_LOGIC;
+		MIDI_TLR : OUT STD_LOGIC;
+		nDREQ0 : OUT STD_LOGIC;
+		DSA_D : OUT STD_LOGIC;
+		nMFP_INT : OUT STD_LOGIC;
+		FALCON_IO_TA : OUT STD_LOGIC;
+		STEP_DIR : OUT STD_LOGIC;
+		WR_DATA : OUT STD_LOGIC;
+		WR_GATE : OUT STD_LOGIC;
+		DMA_DRQ : OUT STD_LOGIC;
+		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
+		LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
+		ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
+		SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
+		SCSI_PAR : INOUT STD_LOGIC;
+		nSCSI_SEL : INOUT STD_LOGIC;
+		nSCSI_BUSY : INOUT STD_LOGIC;
+		nSCSI_RST : INOUT STD_LOGIC;
+		SD_CD_DATA3 : INOUT STD_LOGIC;
+		SD_CDM_D1 : INOUT STD_LOGIC
+	);
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+	
+END FalconIO_SDCard_IDE_CF;
+
+
+--  Architecture Body
+
+ARCHITECTURE FalconIO_SDCard_IDE_CF_architecture OF FalconIO_SDCard_IDE_CF IS
+-- system
+signal SYS_CLK					: STD_LOGIC;
+signal RESETn					: STD_LOGIC;
+signal FB_B0					: STD_LOGIC;	-- UPPER BYT BEI 16BIT BUS
+signal FB_B1					: STD_LOGIC;	-- LOWER BYT BEI 16BIT BUS
+signal BYT						: STD_LOGIC;	-- WENN BYT -> 1
+signal LONG						: STD_LOGIC;	-- WENN  -> 1
+-- KEYBOARD MIDI
+signal ACIA_CS_I				: STD_LOGIC;
+signal IRQ_KEYBDn				: STD_LOGIC;
+signal IRQ_MIDIn				: STD_LOGIC;
+signal KEYB_RxD					: STD_LOGIC;
+signal AMKB_REG					: STD_LOGIC_VECTOR(4 downto 0);
+signal MIDI_OUT					: STD_LOGIC;
+signal DATA_OUT_ACIA_I			: STD_LOGIC_VECTOR(7 downto 0);
+signal DATA_OUT_ACIA_II			: STD_LOGIC_VECTOR(7 downto 0);
+-- MFP
+signal MFP_CS					: STD_LOGIC;
+signal MFP_INTACK				: STD_LOGIC;
+signal LDS						: STD_LOGIC;
+signal DTACK_OUT_MFPn			: STD_LOGIC;
+signal IRQ_ACIAn				: STD_LOGIC;
+signal DINTn					: STD_LOGIC;
+signal DATA_OUT_MFP				: STD_LOGIC_VECTOR(7 downto 0);
+signal TDO						: STD_LOGIC;
+-- SOUND
+signal SNDCS					: STD_LOGIC;
+signal SNDCS_I					: STD_LOGIC;
+signal SNDIR_I					: STD_LOGIC;
+signal LP_DIR_X					: STD_LOGIC;
+signal DA_OUT_X					: STD_LOGIC_VECTOR(7 downto 0);
+signal LP_D_X					: STD_LOGIC_VECTOR(7 downto 0);
+-- DIV
+signal SUB_BUS					: STD_LOGIC;	-- SUB BUS MIT ROM-PORT, CF UND IDE
+signal ROM_CS					: STD_LOGIC;
+-- DMA UND FLOPPY
+signal DMA_DATEN_CS				: STD_LOGIC;
+signal DMA_MODUS_CS				: STD_LOGIC;
+signal DMA_MODUS				: STD_LOGIC_VECTOR(15 downto 0);
+signal WDC_BSL_CS				: STD_LOGIC;
+signal WDC_BSL					: STD_LOGIC_VECTOR(1 DOWNTO 0);
+signal HD_DD_OUT				: STD_LOGIC;
+signal FDCS_In					: STD_LOGIC;
+signal CA0						: STD_LOGIC;
+signal CA1						: STD_LOGIC;
+signal CA2						: STD_LOGIC;
+signal FDINT					: STD_LOGIC;
+signal FDRQ						: STD_LOGIC;
+signal CD_OUT_FDC				: STD_LOGIC_VECTOR(7 downto 0);
+signal CD_IN_FDC				: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_TOP_CS				: STD_LOGIC;
+signal DMA_TOP					: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_HIGH_CS				: STD_LOGIC;
+signal DMA_HIGH					: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_MID_CS				: STD_LOGIC;
+signal DMA_MID					: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_LOW_CS				: STD_LOGIC;
+signal DMA_LOW					: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_DIRM_CS				: STD_LOGIC;
+signal DMA_ADR_CS				: STD_LOGIC;
+signal DMA_STATUS				: STD_LOGIC_VECTOR(2 downto 0);
+signal DMA_DIR_OLD				: STD_LOGIC;
+signal DMA_BYT_CNT_CS			: STD_LOGIC;
+signal DMA_BYT_CNT				: STD_LOGIC_VECTOR(31 downto 0);
+signal CLR_FIFO					: STD_LOGIC;
+signal DMA_DRQ_I				: STD_LOGIC;
+signal DMA_DRQ_REG				: STD_LOGIC_VECTOR(1 downto 0);
+signal DMA_DRQQ					: STD_LOGIC;
+signal DMA_DRQ_Q				: STD_LOGIC;
+signal RDF_DOUT					: STD_LOGIC_VECTOR(31 downto 0);
+signal RDF_AZ					: STD_LOGIC_VECTOR(9 downto 0);
+signal RDF_RDE					: STD_LOGIC;
+signal RDF_WRE					: STD_LOGIC;
+signal RDF_DIN					: STD_LOGIC_VECTOR(7 downto 0);
+signal WRF_DOUT					: STD_LOGIC_VECTOR(7 downto 0);
+signal WRF_AZ					: STD_LOGIC_VECTOR(9 downto 0);
+signal WRF_RDE					: STD_LOGIC;
+signal WRF_WRE					: STD_LOGIC;
+signal nFDC_WR					: STD_LOGIC;
+type FCF_STATES is(	FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7);
+signal FCF_STATE				: FCF_STATES;
+signal NEXT_FCF_STATE			: FCF_STATES;
+signal DMA_REQ					: STD_LOGIC;
+signal FDC_CS					: STD_LOGIC;
+signal FCF_CS					: STD_LOGIC;
+signal FCF_APH					: STD_LOGIC;
+signal DMA_AZ_CS				: STD_LOGIC;
+signal DMA_ACTIV				: STD_LOGIC;
+signal DMA_ACTIV_NEW			: STD_LOGIC;
+signal FDC_OUT					: STD_LOGIC_VECTOR(7 downto 0);
+-- SCSI
+signal SCSI_CS					: STD_LOGIC;
+signal SCSI_CSn					: STD_LOGIC;
+signal SCSI_DOUT				: STD_LOGIC_VECTOR(7 downto 0);
+signal nSCSI_DACK				: STD_LOGIC;
+signal SCSI_DRQ					: STD_LOGIC;
+signal SCSI_INT					: STD_LOGIC;
+signal DB_OUTn					: STD_LOGIC_VECTOR(7 downto 0);
+signal DB_EN					: STD_LOGIC;
+signal DBP_OUTn					: STD_LOGIC;
+signal DBP_EN					: STD_LOGIC;
+signal RST_OUTn					: STD_LOGIC;
+signal RST_EN					: STD_LOGIC;
+signal BSY_OUTn					: STD_LOGIC;
+signal BSY_EN					: STD_LOGIC;
+signal SEL_OUTn					: STD_LOGIC;
+signal SEL_EN					: STD_LOGIC;
+-- IDE
+signal nnIDE_RES				: STD_LOGIC;
+signal IDE_CF_CS				: STD_LOGIC;
+signal IDE_CF_TA				: STD_LOGIC;
+signal NEXT_nIDE_RD				: STD_LOGIC;
+signal NEXT_nIDE_WR				: STD_LOGIC;
+type CMD_STATES is(	IDLE, T1, T6, T7);
+signal CMD_STATE				: CMD_STATES;
+signal NEXT_CMD_STATE			: CMD_STATES;
+
+	
+BEGIN
+LONG  <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0';
+BYT   <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
+FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0';
+FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0';
+
+FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1' 
+				 or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';
+SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1'    ELSE
+           '1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE
+           '1' when nFB_WR = '0' and nIDE_WR = '0'   ELSE '0';
+nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1'; 
+nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1'; 
+nDREQ0 <= '0';
+----------------------------------------------------------------------------
+-- SD
+----------------------------------------------------------------------------
+SD_CLK <= 'Z';
+SD_CD_DATA3 <= 'Z';
+SD_CDM_D1 <= 'Z';
+----------------------------------------------------------------------------
+-- IDE
+----------------------------------------------------------------------------
+CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
+	begin
+		if nRSTO = '0' then
+			CMD_STATE <= IDLE;
+		elsif rising_edge(MAIN_CLK) then
+				CMD_STATE <= NEXT_CMD_STATE; 	-- go to next
+				nIDE_RD   <= NEXT_nIDE_RD; 		-- go to next
+				nIDE_WR   <= NEXT_nIDE_WR; 		-- go to next
+			else
+				CMD_STATE <= CMD_STATE; 		-- halten
+				nIDE_RD   <= nIDE_RD;			-- halten
+				nIDE_WR   <= nIDE_WR;			-- halten
+			end if;
+	end process CMD_REG;
+
+	CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA)
+	begin
+		case CMD_STATE is
+			when IDLE =>
+				IDE_CF_TA <= '0';
+				if  IDE_CF_CS = '1' then
+					NEXT_nIDE_RD <= not nFB_WR;
+					NEXT_nIDE_WR <=     nFB_WR;
+					NEXT_CMD_STATE <= T1;
+				else
+					NEXT_nIDE_RD <= '1';
+					NEXT_nIDE_WR <= '1';
+					NEXT_CMD_STATE <= IDLE; 		 
+				end if;
+			when T1 =>
+				IDE_CF_TA <= '0';
+				NEXT_nIDE_RD <= not nFB_WR;
+				NEXT_nIDE_WR <=     nFB_WR;
+				NEXT_CMD_STATE <= T6;
+			when T6 =>
+				IF IDE_RDY = '1' then
+					IDE_CF_TA <= '1';
+					NEXT_nIDE_RD <= '1';
+					NEXT_nIDE_WR <= '1';
+					NEXT_CMD_STATE <= T7;
+				else
+					IDE_CF_TA <= '0';
+					NEXT_nIDE_RD <= not nFB_WR;
+					NEXT_nIDE_WR <=     nFB_WR;
+					NEXT_CMD_STATE <= T6;
+				end if;
+			when T7 => 
+				IDE_CF_TA <= '0';
+				NEXT_nIDE_RD <= '1';
+				NEXT_nIDE_WR <= '1';
+				NEXT_CMD_STATE <= IDLE;
+		end case;
+	end process CMD_DECODER;
+	
+IDE_RES <= not nnIDE_RES and nRSTO;
+IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0';				-- FFF0'0000/80
+nCF_CS0   <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else 				-- FFFO'0000-FFF0'001F
+			 '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; 			-- FFFO'0040-FFF0'005F
+nCF_CS1   <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else	 			-- FFF0'0020-FFF0'003F
+			 '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; 			-- FFFO'0060-FFF0'007F
+nIDE_CS0  <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else				-- FFF0'0040-FFF0'005F 
+			 '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; 			-- FFFO'0000-FFF0'001F
+nIDE_CS1  <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else				-- FFF0'0060-FFF0'007F 
+			 '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; 			-- FFFO'0020-FFF0'003F
+-----------------------------------------------------------------------------------------------------------------------------------------
+-- ACSI, SCSI UND FLOPPY WD1772 
+-------------------------------------------------------------------------------------------------------------------------------------------
+-- daten read fifo
+	RDF: dcfifo0
+		port map(
+			aclr				=> CLR_FIFO,
+			data				=> RDF_DIN,
+			rdclk				=> MAIN_CLK,
+			rdreq				=> RDF_RDE,
+			wrclk				=> FDC_CLK,
+			wrreq				=> RDF_WRE,
+			q					=> RDF_DOUT,
+			wrusedw				=> RDF_AZ
+	);
+FCF_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0';		-- F002'0110 LONG ONLY
+FCF_APH <= '1' when FB_ALE = '1' and FB_AD(31 downto 0)  = x"F0020110" and LONG = '1' else '0';		-- ADRESSPHASE F0020110 LONG ONLY
+RDF_RDE <= '1' when FCF_APH = '1' and nFB_WR = '1' else '0';										-- AKTIVIEREN IN ADRESSPHASE
+FB_AD <= RDF_DOUT(7 downto 0) & RDF_DOUT(15 downto 8) & RDF_DOUT(23 downto 16) & RDF_DOUT(31 downto 24) when FCF_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";	 
+RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT;
+-- daten write fifo
+	WRF: dcfifo1
+		port map(
+			aclr				=> CLR_FIFO,
+			data				=> FB_AD(7 downto 0) & FB_AD(15 downto 8) & FB_AD(23 downto 16) & FB_AD(31 downto 24),
+			rdclk				=> FDC_CLK,
+			rdreq				=> WRF_RDE,
+			wrclk				=> MAIN_CLK,
+			wrreq				=> WRF_WRE,
+			q					=> WRF_DOUT,
+			rdusedw				=> WRF_AZ
+	);
+CD_IN_FDC <=  WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); 							-- BEI DMA WRITE <-FIFO SONST <-FB
+DMA_AZ_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0';										-- F002'010C LONG
+FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
+DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
+-- FIFO WRITE: GENAU 1 MAIN_CLK  -------------------------------------------------------------------------
+	process(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH)
+	begin
+		if nRSTO = '0' THEN
+			WRF_WRE <= '0';
+		elsif rising_edge(MAIN_CLK) then
+				IF FCF_APH = '1' and nFB_WR = '0' then
+					WRF_WRE <= '1';
+				else
+					WRF_WRE <= '0';
+				end if;
+			else
+				WRF_WRE <= WRF_WRE;
+			end if;
+	END PROCESS;
+ 
+FCF_REG: process(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV)
+	begin
+		if nRSTO = '0' then
+			FCF_STATE <= FCF_IDLE;
+			DMA_ACTIV <= '0';
+		elsif rising_edge(FDC_CLK) then
+				FCF_STATE <= NEXT_FCF_STATE; 			-- go to next
+				DMA_ACTIV <= DMA_ACTIV_NEW;
+			else
+				FCF_STATE <= FCF_STATE; 					-- halten
+				DMA_ACTIV <= DMA_ACTIV;
+			end if;
+	end process FCF_REG;
+
+FDC_REG: process(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC)
+	begin
+		if nRSTO = '0' then
+			FDC_OUT <= x"00";
+		elsif rising_edge(FDC_CLK) and FDCS_In = '0' then
+				FDC_OUT <= CD_OUT_FDC; 						-- set
+			else
+				FDC_OUT <= FDC_OUT; 						-- halten
+			end if;
+	end process FDC_REG;
+
+DMA_REQ <= '1' when ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' else '0';
+FDC_CS   <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and FB_B1 = '1' else '0';
+SCSI_CS  <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_B1 = '1' else '0';
+
+	FCF_DECODER: process(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn)
+	begin
+		case FCF_STATE is
+			when FCF_IDLE =>
+				SCSI_CSn <= '1';
+				FDCS_In <= '1';
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				nSCSI_DACK <= '1';
+				if DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' then 	 
+					DMA_ACTIV_NEW <= DMA_REQ;
+					NEXT_FCF_STATE <= FCF_T0;
+				else
+					DMA_ACTIV_NEW <= '0';
+					NEXT_FCF_STATE <= FCF_IDLE; 		 
+				end if;
+			when FCF_T0 =>
+				SCSI_CSn <= '1';
+				FDCS_In <= '1';
+				RDF_WRE <= '0';
+				nSCSI_DACK <= '1';
+				DMA_ACTIV_NEW <= DMA_REQ;
+				WRF_RDE <= DMA_MODUS(8) and DMA_REQ;				-- WRITE -> READ FROM FIFO
+				if 	DMA_REQ = '0' and DMA_ACTIV = '1' THEN			-- spike?
+					NEXT_FCF_STATE <= FCF_IDLE;						-- ja -> zum start
+				else
+					NEXT_FCF_STATE <= FCF_T1;
+				end if;
+			when FCF_T1 =>
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				DMA_ACTIV_NEW <= DMA_ACTIV;
+				SCSI_CSn <= not SCSI_CS;
+				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
+				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
+				NEXT_FCF_STATE <= FCF_T2;
+			when FCF_T2 =>
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				DMA_ACTIV_NEW <= DMA_ACTIV;
+				SCSI_CSn <= not SCSI_CS;
+				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
+				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
+				NEXT_FCF_STATE <= FCF_T3;
+			when FCF_T3 =>
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				DMA_ACTIV_NEW <= DMA_ACTIV;
+				SCSI_CSn <= not SCSI_CS;
+				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
+				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
+				NEXT_FCF_STATE <= FCF_T6;
+			when FCF_T6 =>
+				WRF_RDE <= '0';
+				DMA_ACTIV_NEW <= DMA_ACTIV;
+				SCSI_CSn <= not SCSI_CS;
+				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
+				nSCSI_DACK <= DMA_MODUS(7)  and DMA_ACTIV;
+				RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV;		-- READ -> WRITE IN FIFO
+				NEXT_FCF_STATE <= FCF_T7;
+			when FCF_T7 =>
+				SCSI_CSn <= '1';
+				FDCS_In <= '1';
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				nSCSI_DACK <= '1';
+				DMA_ACTIV_NEW <= '0';
+				if FDC_CS = '1' and DMA_REQ = '0'  then 	 
+					NEXT_FCF_STATE <= FCF_T7;
+				else
+					NEXT_FCF_STATE <= FCF_IDLE; 		 
+				end if;
+		end case;
+	end process FCF_DECODER;
+
+	I_FDC: WF1772IP_TOP_SOC
+		port map(
+            CLK					=> FDC_CLK,
+			RESETn				=> nRSTO,
+			CSn					=> FDCS_In,
+			RWn					=> nFDC_WR,
+			A1					=> CA2,
+			A0					=> CA1,
+			DATA_IN				=> CD_IN_FDC,
+			DATA_OUT			=> CD_OUT_FDC,
+--			DATA_EN				=> CD_EN_FDC,
+			RDn					=> nRD_DATA,
+			TR00n				=> TRACK00,
+			IPn					=> nINDEX,
+			WPRTn				=> nWP,
+			DDEn				=> '0', -- Fixed to MFM.
+			HDTYPE				=> HD_DD_OUT,  
+			MO					=> MOT_ON,
+			WG					=> WR_GATE,
+			WD					=> WR_DATA,
+			STEP				=> STEP,
+			DIRC				=> STEP_DIR,
+			DRQ					=> DMA_DRQ_I,
+			INTRQ				=> FDINT 
+		);
+DMA_DATEN_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C302" else '0';						-- F8604/2 
+DMA_MODUS_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C303" else '0';						-- F8606/2
+WDC_BSL_CS   <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C307" else '0';						-- F860E/2
+HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0);
+nFDC_WR <= (not DMA_MODUS(8)) when DMA_ACTIV = '1' else nFB_WR;
+CA0 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(0);
+CA1 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(1);
+CA2 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(2);
+FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1'                               and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(23 downto 16) <= FDC_OUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and nFB_OE = '0' else
+                     SCSI_DOUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and nFB_OE = '0' else 
+      DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1'           and nFB_OE = '0' else "ZZZZZZZZ";
+--- WDC BSL REGISTER -------------------------------------------------------
+	process(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1)
+	begin
+		if nRSTO = '0' THEN
+			WDC_BSL <= "00";
+		elsif rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' then
+			IF FB_B0 = '1' THEN
+				WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24);
+			else
+				WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0);
+			end if;
+		end if;
+	END PROCESS;
+--- DMA MODUS REGISTER -------------------------------------------------------
+	process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1)
+	begin
+		if nRSTO = '0' THEN
+			DMA_MODUS <= x"0000";
+		elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' then
+			IF FB_B0 = '1' THEN
+				DMA_MODUS(15 downto 8) <= FB_AD(31 downto 24);
+			else
+				DMA_MODUS(15 downto 8) <= DMA_MODUS(15 downto 8);
+			end if;
+			IF FB_B1 = '1' THEN
+				DMA_MODUS(7 downto 0) <= FB_AD(23 downto 16);
+			else
+				DMA_MODUS(7 downto 0) <= DMA_MODUS(7 downto 0);
+			end if;
+		else
+			DMA_MODUS <= DMA_MODUS;
+		end if;
+	END PROCESS;
+-- BYT COUNTER, SECTOR COUNTER ----------------------------------------------------
+	process(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO)
+	begin
+		if nRSTO = '0' or CLR_FIFO = '1' THEN
+			DMA_BYT_CNT <= x"00000000";													 
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' then
+				DMA_BYT_CNT(31 downto 17) <= "000000000000000";
+				DMA_BYT_CNT(16 downto 9) <= FB_AD(23 downto 16);
+				DMA_BYT_CNT(8 downto 0) <= "000000000";
+			elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' then
+					DMA_BYT_CNT <= FB_AD;
+				else
+					DMA_BYT_CNT <= DMA_BYT_CNT;
+				end if;
+	END PROCESS;
+--------------------------------------------------------------------
+FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+DMA_STATUS(0) <= '1';													-- DMA OK
+DMA_STATUS(1) <= '1' when DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' else '0';					-- WENN byts UND NICHT MINUS
+DMA_STATUS(2) <= '0' when DMA_DRQ_I = '1' or SCSI_DRQ = '1' else '0'; 
+DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ >  15 and DMA_MODUS(6) = '0' else 
+            '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' else '0';
+DMA_DRQ <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
+-- DMA REQUEST: SPIKES AUSFILTERN  ------------------------------------------
+	process(FDC_CLK, nRSTO, DMA_DRQ_REG)
+	begin
+		if nRSTO = '0' THEN
+			DMA_DRQ_REG <= "00";
+		elsif rising_edge(FDC_CLK) then
+				DMA_DRQ_REG(0) <= DMA_DRQQ;
+				DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ;
+			else
+				DMA_DRQ_REG <= DMA_DRQ_REG;
+			end if;
+	END PROCESS;
+-- DMA ADRESSE ------------------------------------------------------
+	process(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS)
+	begin
+		if nRSTO = '0' THEN
+			DMA_TOP <= x"00";
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') then
+				DMA_TOP <= FB_AD(31 downto 24);
+			else 
+				DMA_TOP <= DMA_TOP;
+			end if;
+	END PROCESS;
+	process(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS)
+	begin
+		if nRSTO = '0' THEN
+			DMA_HIGH <= x"00";
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') then
+				DMA_HIGH <= FB_AD(23 downto 16);
+			else
+				DMA_HIGH <= DMA_HIGH;
+			end if;
+	END PROCESS;
+	process(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR)
+	begin
+		DMA_MID <= DMA_MID;
+		if nRSTO = '0' THEN
+			DMA_MID <= x"00";
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then
+				if DMA_MID_CS = '1' then
+					DMA_MID <= FB_AD(23 downto 16);
+				elsif DMA_ADR_CS = '1' then
+						DMA_MID <= FB_AD(15 downto 8);
+					end if;
+			end if;
+	END PROCESS;
+	process(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR)
+	begin
+		DMA_LOW <= DMA_LOW;
+		if nRSTO = '0' THEN
+			DMA_LOW <= x"00";
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then
+				if DMA_LOW_CS = '1'then
+					DMA_LOW <= FB_AD(23 downto 16);
+				elsif DMA_ADR_CS = '1' then
+						DMA_LOW <= FB_AD(7 downto 0);
+					end if;
+			end if;
+	END PROCESS;
+--------------------------------------------------------------------------------------------
+DMA_TOP_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0';			-- F8608/2
+DMA_HIGH_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0';			-- F8609/2		
+DMA_MID_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0';			-- F860B/2		
+DMA_LOW_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0';			-- F860D/2	
+FB_AD(31 downto 24) <= DMA_TOP  when DMA_TOP_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(23 downto 16) <= DMA_HIGH when DMA_HIGH_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(23 downto 16) <= DMA_MID  when DMA_MID_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(23 downto 16) <= DMA_LOW  when DMA_LOW_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
+-- DIRECTZUGRIFF
+DMA_DIRM_CS <= '1' when nFB_CS2 = '0' and     FB_ADR(26 downto 0) = x"20100" else '0';						-- F002'0100 WORD 
+DMA_ADR_CS  <= '1' when nFB_CS2 = '0' and     FB_ADR(26 downto 0) = x"20104" else '0';						-- F002'0104 LONG 
+DMA_BYT_CNT_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20108" else '0';						-- F002'0108 LONG 
+FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
+FB_AD(31 downto 16) <= DMA_MODUS when DMA_DIRM_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+FB_AD <= DMA_BYT_CNT when DMA_BYT_CNT_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
+-- DMA RW TOGGLE ------------------------------------------
+	process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD)
+	begin
+		if nRSTO = '0' THEN
+			DMA_DIR_OLD <= '0';
+		elsif rising_edge(MAIN_CLK) and  DMA_MODUS_CS = '0' then
+				DMA_DIR_OLD <= DMA_MODUS(8);
+			else
+				DMA_DIR_OLD <= DMA_DIR_OLD;
+			end if;
+	END PROCESS;
+CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD;	
+-- SCSI ----------------------------------------------------------------------------------
+    I_SCSI: WF5380_TOP_SOC
+        port map(
+            CLK					=> FDC_CLK,
+            RESETn				=> nRSTO,
+			ADR			        => CA2 & CA1 & CA0,
+			DATA_IN		        => CD_IN_FDC,	
+			DATA_OUT			=> SCSI_DOUT,
+			--DATA_EN			: out bit;
+            -- Bus and DMA controls:
+			CSn			        => '1',			--SCSI_CSn,  ABGESCHALTET
+			RDn		            => (not nFDC_WR) or (not SCSI_CS),
+			WRn	                =>      nFDC_WR  or (not SCSI_CS),
+            EOPn                => '1',
+			DACKn	            => nSCSI_DACK,
+			DRQ		            => SCSI_DRQ,
+			INT		            => SCSI_INT,
+--            READY                	=> 
+            -- SCSI bus:
+            DB_INn		        => SCSI_D,
+            DB_OUTn		        => DB_OUTn,
+            DB_EN               => DB_EN,
+            DBP_INn		        => SCSI_PAR,
+            DBP_OUTn	        => DBP_OUTn,
+            DBP_EN              => DBP_EN,				-- wenn 1 dann output
+            RST_INn             => nSCSI_RST,
+            RST_OUTn            => RST_OUTn,
+            RST_EN              => RST_EN,
+            BSY_INn             => nSCSI_BUSY,
+            BSY_OUTn            => BSY_OUTn,
+            BSY_EN              => BSY_EN,
+            SEL_INn             => nSCSI_SEL,
+            SEL_OUTn            => SEL_OUTn,
+            SEL_EN              => SEL_EN,
+            ACK_INn             => '1',
+            ACK_OUTn            => nSCSI_ACK,
+--            ACK_EN              => ACK_EN,
+            ATN_INn             => '1',
+            ATN_OUTn            => nSCSI_ATN,
+--            ATN_EN              => ATN_EN,
+            REQ_INn             => nSCSI_DRQ,
+--            REQ_OUTn            => REQ_OUTn,
+--            REQ_EN              => REQ_EN,
+            IOn_IN              => nSCSI_I_O,
+--            IOn_OUT             => IOn_OUT,
+--            IO_EN               => IO_EN,
+            CDn_IN              => nSCSI_C_D,
+--            CDn_OUT             => CDn_OUT,
+--            CD_EN               => CD_EN,
+            MSG_INn             => nSCSI_MSG
+--            MSG_OUTn            => MSG_OUTn,
+--            MSG_EN              => MSG_EN
+        );              
+-- SCSI ACSI ---------------------------------------------------------------
+SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ";
+SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1';	--ABGESCHALTET
+SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z';
+nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z';
+nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z';
+nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z';
+ACSI_DIR <= '0';
+ACSI_D <= "ZZZZZZZZ";
+nACSI_CS <= '1';
+ACSI_A1 <= CA1;
+nACSI_RESET <= nRSTO;
+nACSI_ACK <= '1';
+----------------------------------------------------------------------------
+-- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns
+----------------------------------------------------------------------------
+ROM_CS <= '1' when nFB_CS1 = '0' and nFB_WR = '1' and FB_ADR(19 downto 17) = x"5" else '0';		-- FFF A'0000/2'0000
+nROM4 <= '0' when ROM_CS = '1' and FB_ADR(16) = '0' else '1';
+nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1';
+----------------------------------------------------------------------------
+-- ACIA KEYBOARD
+----------------------------------------------------------------------------
+	I_ACIA_KEYBOARD: WF6850IP_TOP_SOC
+	  port map(
+			CLK					=> MAIN_CLK,
+			RESETn				=> nRSTO,
+
+			CS2n				=> FB_ADR(2),
+			CS1					=> '1',
+			CS0					=> ACIA_CS_I,
+            E					=> ACIA_CS_I,
+			RWn					=> nFB_WR,
+			RS					=> FB_ADR(1),
+
+			DATA_IN				=> FB_AD(31 downto 24),
+			DATA_OUT			=> DATA_OUT_ACIA_I,
+--			DATA_EN				=> DATA_EN_ACIA_I,
+
+			TXCLK				=> CLK500k,
+			RXCLK				=> CLK500k,
+			RXDATA				=> KEYB_RxD,
+
+			CTSn				=> '0',
+			DCDn				=> '0',
+        
+			IRQn				=> IRQ_KEYBDn,
+			TXDATA				=> AMKB_TX
+			--RTSn				=> -- Not used.
+		);                                              
+ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0';		-- FFC00-FFC07 FFC00/8
+KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0';				-- TASTATUR DATEN VOM PIC(PS2) OR NORMAL
+FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ";
+-- AMKB_TX: SPIKES AUSFILTERN  ------------------------------------------
+	process(CLK2M, AMKB_RX, AMKB_REG)
+	begin
+		if rising_edge(CLK2M) then
+			IF AMKB_RX = '0' THEN
+				IF AMKB_REG < 16 THEN
+					AMKB_REG <= "00000";
+				ELSE
+					AMKB_REG <= AMKB_REG - 1;
+				END IF;
+			ELSE
+				IF AMKB_REG > 15 THEN
+					AMKB_REG <= "11111";
+				ELSE
+					AMKB_REG <= AMKB_REG + 1;
+				END IF;
+			END IF;
+		ELSE
+			AMKB_REG <= AMKB_REG;
+		end if;
+	END PROCESS;
+----------------------------------------------------------------------------
+-- ACIA MIDI
+----------------------------------------------------------------------------
+	I_ACIA_MIDI: WF6850IP_TOP_SOC
+		port map(
+			CLK					=> MAIN_CLK,
+			RESETn				=> nRSTO,
+
+			CS2n				=> '0',
+			CS1					=> FB_ADR(2),
+			CS0					=> ACIA_CS_I,
+            E					=> ACIA_CS_I,
+			RWn					=> nFB_WR,
+			RS					=> FB_ADR(1),
+
+			DATA_IN				=> FB_AD(31 downto 24),
+			DATA_OUT			=> DATA_OUT_ACIA_II,
+--			DATA_EN				=> DATA_EN_ACIA_II,
+
+			TXCLK				=> CLK500k,
+			RXCLK				=> CLK500k,
+			RXDATA				=> MIDI_IN,
+			CTSn				=> '0',
+			DCDn				=> '0',
+        
+			IRQn				=> IRQ_MIDIn,
+			TXDATA				=> MIDI_OUT
+			--RTSn				=> -- Not used.
+	    );                                              
+MIDI_TLR <= MIDI_OUT;
+MIDI_OLR <= MIDI_OUT;
+FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+----------------------------------------------------------------------------
+-- MFP
+----------------------------------------------------------------------------
+	I_MFP: WF68901IP_TOP_SOC
+		port map(  
+			-- System control:
+			CLK					=> MAIN_CLK,
+			RESETn				=> nRSTO,
+			-- Asynchronous bus control:
+			DSn					=> not LDS,
+			CSn					=> not MFP_CS,
+			RWn					=> nFB_WR,
+ 			DTACKn				=> DTACK_OUT_MFPn,
+			-- Data and Adresses:
+			RS					=> FB_ADR(5 downto 1),
+			DATA_IN				=> FB_AD(23 downto 16),
+			DATA_OUT			=> DATA_OUT_MFP,
+--			DATA_EN				=> DATA_EN_MFP,
+            GPIP_IN(7)			=> not DMA_DRQ_Q,
+            GPIP_IN(6)			=> not RI,
+			GPIP_IN(5)			=> DINTn,
+			GPIP_IN(4)			=> IRQ_ACIAn,
+			GPIP_IN(3)			=> DSP_INT,
+            GPIP_IN(2)			=> not CTS,
+            GPIP_IN(1)			=> not DCD,
+            GPIP_IN(0)			=> LP_BUSY,
+			-- GPIP_OUT			=>, -- Not used; all GPIPs are direction input.
+			-- GPIP_EN			=>, -- Not used; all GPIPs are direction input.
+			-- Interrupt control:
+			IACKn				=> not MFP_INTACK,
+			IEIn				=> '0',
+			-- IEOn				=>, -- Not used.
+			IRQn				=> nMFP_INT,
+			-- Timers and timer control:
+			XTAL1				=> CLK2M4576,
+            TAI					=> '0',
+			TBI				    => nBLANK,
+            -- TAO				=>,
+			-- TBO				=>,
+            -- TCO				=>,
+			TDO					=> TDO,
+			-- Serial I/O control:
+			RC					=> TDO,
+			TC					=> TDO,
+			SI					=> RxD, 
+			SO					=> TxD
+			-- SO_EN			=> MFP_SO_EN
+			-- DMA control:
+			-- RRn				=>,
+			-- TRn				=>
+		);
+
+MFP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0';		-- FFA00/40
+MFP_INTACK <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; 	--F002'0000
+LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0';
+FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ";
+FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ";
+DINTn <= '0' when IDE_INT = '1' AND ACP_CONF(28) = '1' else
+         '0' when FDINT = '1' else
+         '0' when SCSI_INT = '1' AND ACP_CONF(28) = '1' else '1';
+-- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN  ------------------------------------------
+	process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn)
+	begin
+		if nRSTO = '0' THEN
+			IRQ_ACIAn <= '1';
+		elsif rising_edge(MAIN_CLK) then
+				IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn;
+			else
+				IRQ_ACIAn <= IRQ_ACIAn;
+			end if;
+	END PROCESS;
+----------------------------------------------------------------------------
+-- Sound
+----------------------------------------------------------------------------
+ 	I_SOUND: WF2149IP_TOP_SOC
+		port map(
+			SYS_CLK				=> MAIN_CLK,
+			RESETn				=> nRSTO,
+
+			WAV_CLK				=> CLK2M,
+			SELn				=> '1',
+
+			BDIR				=> SNDIR_I,
+			BC2					=> '1',
+			BC1					=> SNDCS_I,
+
+			A9n					=> '0',
+			A8					=> '1',
+			DA_IN				=> FB_AD(31 downto 24),
+			DA_OUT 				=> DA_OUT_X,
+
+			IO_A_IN				=> x"00", -- All port pins are dedicated outputs.
+			IO_A_OUT(7)			=> nnIDE_RES,
+            IO_A_OUT(6)			=> LP_DIR_X,
+			IO_A_OUT(5)			=> LP_STR,
+			IO_A_OUT(4)			=> DTR,
+			IO_A_OUT(3)			=> RTS,
+--			IO_A_OUT(2)			=> FDD_D1SEL,
+			IO_A_OUT(1)			=> DSA_D,
+			IO_A_OUT(0)			=> nSDSEL,
+			-- IO_A_EN			=>, -- Not required.
+			IO_B_IN				=> LP_D,
+			IO_B_OUT			=> LP_D_X,
+ --			IO_B_EN				=> IO_B_EN,
+
+			OUT_A				=> YM_QA,
+			OUT_B				=> YM_QB,
+			OUT_C				=> YM_QC
+		);
+
+SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0';		-- 8800-8803 F8800/4
+SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0';
+SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0';
+FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ";
+LP_DIR <= LP_DIR_X;
+
+END FalconIO_SDCard_IDE_CF_architecture;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak
new file mode 100644
index 0000000..a339eda
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd.bak
@@ -0,0 +1,971 @@
+-- WARNING: Do NOT edit the input and output ports in this file in a text
+-- editor if you plan to continue editing the block that represents it in
+-- the Block Editor! File corruption is VERY likely to occur.
+
+-- Copyright (C) 1991-2008 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+
+-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
+-- Created on Tue Sep 08 16:24:20 2009
+
+library work;
+use work.FalconIO_SDCard_IDE_CF_pkg.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+
+--  Entity Declaration
+
+
+--  Entity Declaration
+
+ENTITY FalconIO_SDCard_IDE_CF IS
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	PORT
+	(
+		CLK33M : IN STD_LOGIC;
+		MAIN_CLK : IN STD_LOGIC;
+		CLK2M : IN STD_LOGIC;
+		CLK500k : IN STD_LOGIC;
+		nFB_CS1 : IN STD_LOGIC;
+		FB_SIZE0 : IN STD_LOGIC;
+		FB_SIZE1 : IN STD_LOGIC;
+		nFB_BURST : IN STD_LOGIC;
+		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
+		LP_BUSY : IN STD_LOGIC;
+		nACSI_DRQ : IN STD_LOGIC;
+		nACSI_INT : IN STD_LOGIC;
+		nSCSI_DRQ : IN STD_LOGIC;
+		nSCSI_MSG : IN STD_LOGIC;
+		MIDI_IN : IN STD_LOGIC;
+		RxD : IN STD_LOGIC;
+		CTS : IN STD_LOGIC;
+		RI : IN STD_LOGIC;
+		DCD : IN STD_LOGIC;
+		AMKB_RX : IN STD_LOGIC;
+		PIC_AMKB_RX : IN STD_LOGIC;
+		IDE_RDY : IN STD_LOGIC;
+		IDE_INT : IN STD_LOGIC;
+		WP_CS_CARD : IN STD_LOGIC;
+		nINDEX : IN STD_LOGIC;
+		TRACK00 : IN STD_LOGIC;
+		nRD_DATA : IN STD_LOGIC;
+		nDCHG : IN STD_LOGIC;
+		SD_DATA0 : IN STD_LOGIC;
+		SD_DATA1 : IN STD_LOGIC;
+		SD_DATA2 : IN STD_LOGIC;
+		SD_CARD_DEDECT : IN STD_LOGIC;
+		SD_WP : IN STD_LOGIC;
+		nDACK0 : IN STD_LOGIC;
+		nFB_WR : INOUT STD_LOGIC;
+		WP_CF_CARD : IN STD_LOGIC;
+		nWP : IN STD_LOGIC;
+		nFB_CS2 : IN STD_LOGIC;
+		nRSTO : IN STD_LOGIC;
+		HD_DD : IN STD_LOGIC;
+		nSCSI_C_D : IN STD_LOGIC;
+		nSCSI_I_O : IN STD_LOGIC;
+		CLK2M4576 : IN STD_LOGIC;
+		nFB_OE : IN STD_LOGIC;
+		VSYNC : IN STD_LOGIC;
+		HSYNC : IN STD_LOGIC;
+		DSP_INT : IN STD_LOGIC;
+		nBLANK : IN STD_LOGIC;
+		FDC_CLK : IN STD_LOGIC;
+		FB_ALE : IN STD_LOGIC;
+		ACP_CONF : IN STD_LOGIC_VECTOR(31 downto 24);
+		nIDE_CS1 : OUT STD_LOGIC;
+		nIDE_CS0 : OUT STD_LOGIC;
+		LP_STR : OUT STD_LOGIC;
+		LP_DIR : OUT STD_LOGIC;
+		nACSI_ACK : OUT STD_LOGIC;
+		nACSI_RESET : OUT STD_LOGIC;
+		nACSI_CS : OUT STD_LOGIC;
+		ACSI_DIR : OUT STD_LOGIC;
+		ACSI_A1 : OUT STD_LOGIC;
+		nSCSI_ACK : OUT STD_LOGIC;
+		nSCSI_ATN : OUT STD_LOGIC;
+		SCSI_DIR : OUT STD_LOGIC;
+		SD_CLK : OUT STD_LOGIC;
+		YM_QA : OUT STD_LOGIC;
+		YM_QC : OUT STD_LOGIC;
+		YM_QB : OUT STD_LOGIC;
+		nSDSEL : OUT STD_LOGIC;
+		STEP : OUT STD_LOGIC;
+		MOT_ON : OUT STD_LOGIC;
+		nRP_LDS : OUT STD_LOGIC;
+		nRP_UDS : OUT STD_LOGIC;
+		nROM4 : OUT STD_LOGIC;
+		nROM3 : OUT STD_LOGIC;
+		nCF_CS1 : OUT STD_LOGIC;
+		nCF_CS0 : OUT STD_LOGIC;
+		nIDE_RD : INOUT STD_LOGIC;
+		nIDE_WR : INOUT STD_LOGIC;
+		AMKB_TX : OUT STD_LOGIC;
+		IDE_RES : OUT STD_LOGIC;
+		DTR : OUT STD_LOGIC;
+		RTS : OUT STD_LOGIC;
+		TxD : OUT STD_LOGIC;
+		MIDI_OLR : OUT STD_LOGIC;
+		MIDI_TLR : OUT STD_LOGIC;
+		nDREQ0 : OUT STD_LOGIC;
+		DSA_D : OUT STD_LOGIC;
+		nMFP_INT : OUT STD_LOGIC;
+		FALCON_IO_TA : OUT STD_LOGIC;
+		STEP_DIR : OUT STD_LOGIC;
+		WR_DATA : OUT STD_LOGIC;
+		WR_GATE : OUT STD_LOGIC;
+		DMA_DRQ : OUT STD_LOGIC;
+		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0);
+		LP_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
+		ACSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
+		SCSI_D : INOUT STD_LOGIC_VECTOR(7 downto 0);
+		SCSI_PAR : INOUT STD_LOGIC;
+		nSCSI_SEL : INOUT STD_LOGIC;
+		nSCSI_BUSY : INOUT STD_LOGIC;
+		nSCSI_RST : INOUT STD_LOGIC;
+		SD_CD_DATA3 : INOUT STD_LOGIC;
+		SD_CDM_D1 : INOUT STD_LOGIC
+	);
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+	
+END FalconIO_SDCard_IDE_CF;
+
+
+--  Architecture Body
+
+ARCHITECTURE FalconIO_SDCard_IDE_CF_architecture OF FalconIO_SDCard_IDE_CF IS
+-- system
+signal SYS_CLK					: STD_LOGIC;
+signal RESETn					: STD_LOGIC;
+signal FB_B0					: STD_LOGIC;	-- UPPER BYT BEI 16BIT BUS
+signal FB_B1					: STD_LOGIC;	-- LOWER BYT BEI 16BIT BUS
+signal BYT						: STD_LOGIC;	-- WENN BYT -> 1
+signal LONG						: STD_LOGIC;	-- WENN  -> 1
+-- KEYBOARD MIDI
+signal ACIA_CS_I				: STD_LOGIC;
+signal IRQ_KEYBDn				: STD_LOGIC;
+signal IRQ_MIDIn				: STD_LOGIC;
+signal KEYB_RxD					: STD_LOGIC;
+signal AMKB_REG					: STD_LOGIC_VECTOR(4 downto 0);
+signal MIDI_OUT					: STD_LOGIC;
+signal DATA_OUT_ACIA_I			: STD_LOGIC_VECTOR(7 downto 0);
+signal DATA_OUT_ACIA_II			: STD_LOGIC_VECTOR(7 downto 0);
+-- MFP
+signal MFP_CS					: STD_LOGIC;
+signal MFP_INTACK				: STD_LOGIC;
+signal LDS						: STD_LOGIC;
+signal DTACK_OUT_MFPn			: STD_LOGIC;
+signal IRQ_ACIAn				: STD_LOGIC;
+signal DINTn					: STD_LOGIC;
+signal DATA_OUT_MFP				: STD_LOGIC_VECTOR(7 downto 0);
+signal TDO						: STD_LOGIC;
+-- SOUND
+signal SNDCS					: STD_LOGIC;
+signal SNDCS_I					: STD_LOGIC;
+signal SNDIR_I					: STD_LOGIC;
+signal LP_DIR_X					: STD_LOGIC;
+signal DA_OUT_X					: STD_LOGIC_VECTOR(7 downto 0);
+signal LP_D_X					: STD_LOGIC_VECTOR(7 downto 0);
+-- DIV
+signal SUB_BUS					: STD_LOGIC;	-- SUB BUS MIT ROM-PORT, CF UND IDE
+signal ROM_CS					: STD_LOGIC;
+-- DMA UND FLOPPY
+signal DMA_DATEN_CS				: STD_LOGIC;
+signal DMA_MODUS_CS				: STD_LOGIC;
+signal DMA_MODUS				: STD_LOGIC_VECTOR(15 downto 0);
+signal WDC_BSL_CS				: STD_LOGIC;
+signal WDC_BSL					: STD_LOGIC_VECTOR(1 DOWNTO 0);
+signal HD_DD_OUT				: STD_LOGIC;
+signal FDCS_In					: STD_LOGIC;
+signal CA0						: STD_LOGIC;
+signal CA1						: STD_LOGIC;
+signal CA2						: STD_LOGIC;
+signal FDINT					: STD_LOGIC;
+signal FDRQ						: STD_LOGIC;
+signal CD_OUT_FDC				: STD_LOGIC_VECTOR(7 downto 0);
+signal CD_IN_FDC				: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_TOP_CS				: STD_LOGIC;
+signal DMA_TOP					: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_HIGH_CS				: STD_LOGIC;
+signal DMA_HIGH					: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_MID_CS				: STD_LOGIC;
+signal DMA_MID					: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_LOW_CS				: STD_LOGIC;
+signal DMA_LOW					: STD_LOGIC_VECTOR(7 downto 0);
+signal DMA_DIRM_CS				: STD_LOGIC;
+signal DMA_ADR_CS				: STD_LOGIC;
+signal DMA_STATUS				: STD_LOGIC_VECTOR(2 downto 0);
+signal DMA_DIR_OLD				: STD_LOGIC;
+signal DMA_BYT_CNT_CS			: STD_LOGIC;
+signal DMA_BYT_CNT				: STD_LOGIC_VECTOR(31 downto 0);
+signal CLR_FIFO					: STD_LOGIC;
+signal DMA_DRQ_I				: STD_LOGIC;
+signal DMA_DRQ_REG				: STD_LOGIC_VECTOR(1 downto 0);
+signal DMA_DRQQ					: STD_LOGIC;
+signal DMA_DRQ_Q				: STD_LOGIC;
+signal RDF_DOUT					: STD_LOGIC_VECTOR(31 downto 0);
+signal RDF_AZ					: STD_LOGIC_VECTOR(9 downto 0);
+signal RDF_RDE					: STD_LOGIC;
+signal RDF_WRE					: STD_LOGIC;
+signal RDF_DIN					: STD_LOGIC_VECTOR(7 downto 0);
+signal WRF_DOUT					: STD_LOGIC_VECTOR(7 downto 0);
+signal WRF_AZ					: STD_LOGIC_VECTOR(9 downto 0);
+signal WRF_RDE					: STD_LOGIC;
+signal WRF_WRE					: STD_LOGIC;
+signal nFDC_WR					: STD_LOGIC;
+type FCF_STATES is(	FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7);
+signal FCF_STATE				: FCF_STATES;
+signal NEXT_FCF_STATE			: FCF_STATES;
+signal DMA_REQ					: STD_LOGIC;
+signal FDC_CS					: STD_LOGIC;
+signal FCF_CS					: STD_LOGIC;
+signal FCF_APH					: STD_LOGIC;
+signal DMA_AZ_CS				: STD_LOGIC;
+signal DMA_ACTIV				: STD_LOGIC;
+signal DMA_ACTIV_NEW			: STD_LOGIC;
+signal FDC_OUT					: STD_LOGIC_VECTOR(7 downto 0);
+-- SCSI
+signal SCSI_CS					: STD_LOGIC;
+signal SCSI_CSn					: STD_LOGIC;
+signal SCSI_DOUT				: STD_LOGIC_VECTOR(7 downto 0);
+signal nSCSI_DACK				: STD_LOGIC;
+signal SCSI_DRQ					: STD_LOGIC;
+signal SCSI_INT					: STD_LOGIC;
+signal DB_OUTn					: STD_LOGIC_VECTOR(7 downto 0);
+signal DB_EN					: STD_LOGIC;
+signal DBP_OUTn					: STD_LOGIC;
+signal DBP_EN					: STD_LOGIC;
+signal RST_OUTn					: STD_LOGIC;
+signal RST_EN					: STD_LOGIC;
+signal BSY_OUTn					: STD_LOGIC;
+signal BSY_EN					: STD_LOGIC;
+signal SEL_OUTn					: STD_LOGIC;
+signal SEL_EN					: STD_LOGIC;
+-- IDE
+signal nnIDE_RES				: STD_LOGIC;
+signal IDE_CF_CS				: STD_LOGIC;
+signal IDE_CF_TA				: STD_LOGIC;
+signal NEXT_nIDE_RD				: STD_LOGIC;
+signal NEXT_nIDE_WR				: STD_LOGIC;
+type CMD_STATES is(	IDLE, T1, T6, T7);
+signal CMD_STATE				: CMD_STATES;
+signal NEXT_CMD_STATE			: CMD_STATES;
+
+	
+BEGIN
+LONG  <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '0' else '0';
+BYT   <= '1' when FB_SIZE1 = '0' and FB_SIZE0 = '1' else '0';
+FB_B0 <= '1' when FB_ADR(0) = '0' or BYT = '0' else '0';
+FB_B1 <= '1' when FB_ADR(0) = '1' or BYT = '0' else '0';
+
+FALCON_IO_TA <= '1' when SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1' 
+				 or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' else '0';
+SUB_BUS <= '1' when nFB_WR = '1' and ROM_CS = '1'    ELSE
+           '1' when nFB_WR = '1' and IDE_CF_CS = '1' ELSE
+           '1' when nFB_WR = '0' and nIDE_WR = '0'   ELSE '0';
+nRP_UDS <= '0' when SUB_BUS = '1' and FB_B0 = '1' else '1'; 
+nRP_LDS <= '0' when SUB_BUS = '1' and FB_B1 = '1' else '1'; 
+nDREQ0 <= '0';
+----------------------------------------------------------------------------
+-- SD
+----------------------------------------------------------------------------
+SD_CLK <= 'Z';
+SD_CD_DATA3 <= 'Z';
+SD_CDM_D1 <= 'Z';
+----------------------------------------------------------------------------
+-- IDE
+----------------------------------------------------------------------------
+CMD_REG: process(nRSTO, MAIN_CLK, CMD_STATE, NEXT_CMD_STATE)
+	begin
+		if nRSTO = '0' then
+			CMD_STATE <= IDLE;
+		elsif rising_edge(MAIN_CLK) then
+				CMD_STATE <= NEXT_CMD_STATE; 	-- go to next
+				nIDE_RD   <= NEXT_nIDE_RD; 		-- go to next
+				nIDE_WR   <= NEXT_nIDE_WR; 		-- go to next
+			else
+				CMD_STATE <= CMD_STATE; 		-- halten
+				nIDE_RD   <= nIDE_RD;			-- halten
+				nIDE_WR   <= nIDE_WR;			-- halten
+			end if;
+	end process CMD_REG;
+
+	CMD_DECODER: process(CMD_STATE, NEXT_CMD_STATE, NEXT_nIDE_RD, NEXT_nIDE_WR, IDE_RDY, IDE_CF_TA)
+	begin
+		case CMD_STATE is
+			when IDLE =>
+				IDE_CF_TA <= '0';
+				if  IDE_CF_CS = '1' then
+					NEXT_nIDE_RD <= not nFB_WR;
+					NEXT_nIDE_WR <=     nFB_WR;
+					NEXT_CMD_STATE <= T1;
+				else
+					NEXT_nIDE_RD <= '1';
+					NEXT_nIDE_WR <= '1';
+					NEXT_CMD_STATE <= IDLE; 		 
+				end if;
+			when T1 =>
+				IDE_CF_TA <= '0';
+				NEXT_nIDE_RD <= not nFB_WR;
+				NEXT_nIDE_WR <=     nFB_WR;
+				NEXT_CMD_STATE <= T6;
+			when T6 =>
+				IF IDE_RDY = '1' then
+					IDE_CF_TA <= '1';
+					NEXT_nIDE_RD <= '1';
+					NEXT_nIDE_WR <= '1';
+					NEXT_CMD_STATE <= T7;
+				else
+					IDE_CF_TA <= '0';
+					NEXT_nIDE_RD <= not nFB_WR;
+					NEXT_nIDE_WR <=     nFB_WR;
+					NEXT_CMD_STATE <= T6;
+				end if;
+			when T7 => 
+				IDE_CF_TA <= '0';
+				NEXT_nIDE_RD <= '1';
+				NEXT_nIDE_WR <= '1';
+				NEXT_CMD_STATE <= IDLE;
+		end case;
+	end process CMD_DECODER;
+	
+IDE_RES <= not nnIDE_RES and nRSTO;
+IDE_CF_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 7) = x"0" else '0';				-- FFF0'0000/80
+nCF_CS0   <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"0" else 				-- FFFO'0000-FFF0'001F
+			 '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"2" else '1'; 			-- FFFO'0040-FFF0'005F
+nCF_CS1   <= '0' when ACP_CONF(31) = '0' and FB_ADR(19 downto 5) = x"1" else	 			-- FFF0'0020-FFF0'003F
+			 '0' when ACP_CONF(31) = '1' and FB_ADR(19 downto 5) = x"3" else '1'; 			-- FFFO'0060-FFF0'007F
+nIDE_CS0  <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"2" else				-- FFF0'0040-FFF0'005F 
+			 '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"0" else '1'; 			-- FFFO'0000-FFF0'001F
+nIDE_CS1  <= '0' when ACP_CONF(30) = '0' and FB_ADR(19 downto 5) = x"3" else				-- FFF0'0060-FFF0'007F 
+			 '0' when ACP_CONF(30) = '1' and FB_ADR(19 downto 5) = x"1" else '1'; 			-- FFFO'0020-FFF0'003F
+-----------------------------------------------------------------------------------------------------------------------------------------
+-- ACSI, SCSI UND FLOPPY WD1772 
+-------------------------------------------------------------------------------------------------------------------------------------------
+-- daten read fifo
+	RDF: dcfifo0
+		port map(
+			aclr				=> CLR_FIFO,
+			data				=> RDF_DIN,
+			rdclk				=> MAIN_CLK,
+			rdreq				=> RDF_RDE,
+			wrclk				=> FDC_CLK,
+			wrreq				=> RDF_WRE,
+			q					=> RDF_DOUT,
+			wrusedw				=> RDF_AZ
+	);
+FCF_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"0020110" and LONG = '1' else '0';		-- F002'0110 LONG ONLY
+FCF_APH <= '1' when FB_ALE = '1' and FB_AD(31 downto 0)  = x"F0020110" and LONG = '1' else '0';		-- ADRESSPHASE F0020110 LONG ONLY
+RDF_RDE <= '1' when FCF_APH = '1' and nFB_WR = '1' else '0';										-- AKTIVIEREN IN ADRESSPHASE
+FB_AD <= RDF_DOUT(7 downto 0) & RDF_DOUT(15 downto 8) & RDF_DOUT(23 downto 16) & RDF_DOUT(31 downto 24) when FCF_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";	 
+RDF_DIN <= CD_OUT_FDC when DMA_MODUS(7) = '1' else SCSI_DOUT;
+-- daten write fifo
+	WRF: dcfifo1
+		port map(
+			aclr				=> CLR_FIFO,
+			data				=> FB_AD(7 downto 0) & FB_AD(15 downto 8) & FB_AD(23 downto 16) & FB_AD(31 downto 24),
+			rdclk				=> FDC_CLK,
+			rdreq				=> WRF_RDE,
+			wrclk				=> MAIN_CLK,
+			wrreq				=> WRF_WRE,
+			q					=> WRF_DOUT,
+			rdusedw				=> WRF_AZ
+	);
+CD_IN_FDC <=  WRF_DOUT when DMA_ACTIV = '1' and DMA_MODUS(8) = '1' else FB_AD(23 downto 16); 							-- BEI DMA WRITE <-FIFO SONST <-FB
+DMA_AZ_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"002010C" else '0';										-- F002'010C LONG
+FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ when DMA_AZ_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
+DMA_DRQ_Q <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
+-- FIFO WRITE: GENAU 1 MAIN_CLK  -------------------------------------------------------------------------
+	process(MAIN_CLK, nRSTO, WRF_WRE, nFB_WR, FCF_APH)
+	begin
+		if nRSTO = '0' THEN
+			WRF_WRE <= '0';
+		elsif rising_edge(MAIN_CLK) then
+				IF FCF_APH = '1' and nFB_WR = '0' then
+					WRF_WRE <= '1';
+				else
+					WRF_WRE <= '0';
+				end if;
+			else
+				WRF_WRE <= WRF_WRE;
+			end if;
+	END PROCESS;
+ 
+FCF_REG: process(nRSTO, FDC_CLK, FCF_STATE, NEXT_FCF_STATE, DMA_ACTIV)
+	begin
+		if nRSTO = '0' then
+			FCF_STATE <= FCF_IDLE;
+			DMA_ACTIV <= '0';
+		elsif rising_edge(FDC_CLK) then
+				FCF_STATE <= NEXT_FCF_STATE; 			-- go to next
+				DMA_ACTIV <= DMA_ACTIV_NEW;
+			else
+				FCF_STATE <= FCF_STATE; 					-- halten
+				DMA_ACTIV <= DMA_ACTIV;
+			end if;
+	end process FCF_REG;
+
+FDC_REG: process(nRSTO, FDC_CLK, FDC_OUT, FDCS_In, CD_OUT_FDC)
+	begin
+		if nRSTO = '0' then
+			FDC_OUT <= x"00";
+		elsif rising_edge(FDC_CLK) and FDCS_In = '0' then
+				FDC_OUT <= CD_OUT_FDC; 						-- set
+			else
+				FDC_OUT <= FDC_OUT; 						-- halten
+			end if;
+	end process FDC_REG;
+
+DMA_REQ <= '1' when ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' else '0';
+FDC_CS   <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and FB_B1 = '1' else '0';
+SCSI_CS  <= '1' when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and FB_B1 = '1' else '0';
+
+	FCF_DECODER: process(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn)
+	begin
+		case FCF_STATE is
+			when FCF_IDLE =>
+				SCSI_CSn <= '1';
+				FDCS_In <= '1';
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				nSCSI_DACK <= '1';
+				if DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' then 	 
+					DMA_ACTIV_NEW <= DMA_REQ;
+					NEXT_FCF_STATE <= FCF_T0;
+				else
+					DMA_ACTIV_NEW <= '0';
+					NEXT_FCF_STATE <= FCF_IDLE; 		 
+				end if;
+			when FCF_T0 =>
+				SCSI_CSn <= '1';
+				FDCS_In <= '1';
+				RDF_WRE <= '0';
+				nSCSI_DACK <= '1';
+				DMA_ACTIV_NEW <= DMA_REQ;
+				WRF_RDE <= DMA_MODUS(8) and DMA_REQ;				-- WRITE -> READ FROM FIFO
+				if 	DMA_REQ = '0' and DMA_ACTIV = '1' THEN			-- spike?
+					NEXT_FCF_STATE <= FCF_IDLE;						-- ja -> zum start
+				else
+					NEXT_FCF_STATE <= FCF_T1;
+				end if;
+			when FCF_T1 =>
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				DMA_ACTIV_NEW <= DMA_ACTIV;
+				SCSI_CSn <= not SCSI_CS;
+				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
+				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
+				NEXT_FCF_STATE <= FCF_T2;
+			when FCF_T2 =>
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				DMA_ACTIV_NEW <= DMA_ACTIV;
+				SCSI_CSn <= not SCSI_CS;
+				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
+				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
+				NEXT_FCF_STATE <= FCF_T3;
+			when FCF_T3 =>
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				DMA_ACTIV_NEW <= DMA_ACTIV;
+				SCSI_CSn <= not SCSI_CS;
+				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
+				nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
+				NEXT_FCF_STATE <= FCF_T6;
+			when FCF_T6 =>
+				WRF_RDE <= '0';
+				DMA_ACTIV_NEW <= DMA_ACTIV;
+				SCSI_CSn <= not SCSI_CS;
+				FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
+				nSCSI_DACK <= DMA_MODUS(7)  and DMA_ACTIV;
+				RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV;		-- READ -> WRITE IN FIFO
+				NEXT_FCF_STATE <= FCF_T7;
+			when FCF_T7 =>
+				SCSI_CSn <= '1';
+				FDCS_In <= '1';
+				RDF_WRE <= '0';
+				WRF_RDE <= '0';
+				nSCSI_DACK <= '1';
+				DMA_ACTIV_NEW <= '0';
+				if FDC_CS = '1' and DMA_REQ = '0'  then 	 
+					NEXT_FCF_STATE <= FCF_T7;
+				else
+					NEXT_FCF_STATE <= FCF_IDLE; 		 
+				end if;
+		end case;
+	end process FCF_DECODER;
+
+	I_FDC: WF1772IP_TOP_SOC
+		port map(
+            CLK					=> FDC_CLK,
+			RESETn				=> nRSTO,
+			CSn					=> FDCS_In,
+			RWn					=> nFDC_WR,
+			A1					=> CA2,
+			A0					=> CA1,
+			DATA_IN				=> CD_IN_FDC,
+			DATA_OUT			=> CD_OUT_FDC,
+--			DATA_EN				=> CD_EN_FDC,
+			RDn					=> nRD_DATA,
+			TR00n				=> TRACK00,
+			IPn					=> nINDEX,
+			WPRTn				=> nWP,
+			DDEn				=> '0', -- Fixed to MFM.
+			HDTYPE				=> HD_DD_OUT,  
+			MO					=> MOT_ON,
+			WG					=> WR_GATE,
+			WD					=> WR_DATA,
+			STEP				=> STEP,
+			DIRC				=> STEP_DIR,
+			DRQ					=> DMA_DRQ_I,
+			INTRQ				=> FDINT 
+		);
+DMA_DATEN_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C302" else '0';						-- F8604/2 
+DMA_MODUS_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C303" else '0';						-- F8606/2
+WDC_BSL_CS   <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C307" else '0';						-- F860E/2
+HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0);
+nFDC_WR <= (not DMA_MODUS(8)) when DMA_ACTIV = '1' else nFB_WR;
+CA0 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(0);
+CA1 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(1);
+CA2 <= '1' when DMA_ACTIV = '1' ELSE DMA_MODUS(2);
+FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1'                               and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(23 downto 16) <= FDC_OUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "00" and nFB_OE = '0' else
+                     SCSI_DOUT when DMA_DATEN_CS = '1' and DMA_MODUS(4 downto 3) = "01" and nFB_OE = '0' else 
+      DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1'           and nFB_OE = '0' else "ZZZZZZZZ";
+--- WDC BSL REGISTER -------------------------------------------------------
+	process(MAIN_CLK, nRSTO, WDC_BSL_CS, WDC_BSL, nFB_WR, FB_B0, FB_B1)
+	begin
+		if nRSTO = '0' THEN
+			WDC_BSL <= "00";
+		elsif rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' then
+			IF FB_B0 = '1' THEN
+				WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24);
+			else
+				WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0);
+			end if;
+		end if;
+	END PROCESS;
+--- DMA MODUS REGISTER -------------------------------------------------------
+	process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, nFB_WR, FB_B0, FB_B1)
+	begin
+		if nRSTO = '0' THEN
+			DMA_MODUS <= x"0000";
+		elsif rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' then
+			IF FB_B0 = '1' THEN
+				DMA_MODUS(15 downto 8) <= FB_AD(31 downto 24);
+			else
+				DMA_MODUS(15 downto 8) <= DMA_MODUS(15 downto 8);
+			end if;
+			IF FB_B1 = '1' THEN
+				DMA_MODUS(7 downto 0) <= FB_AD(23 downto 16);
+			else
+				DMA_MODUS(7 downto 0) <= DMA_MODUS(7 downto 0);
+			end if;
+		else
+			DMA_MODUS <= DMA_MODUS;
+		end if;
+	END PROCESS;
+-- BYT COUNTER, SECTOR COUNTER ----------------------------------------------------
+	process(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO)
+	begin
+		if nRSTO = '0' or CLR_FIFO = '1' THEN
+			DMA_BYT_CNT <= x"00000000";													 
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' then
+				DMA_BYT_CNT(31 downto 17) <= "000000000000000";
+				DMA_BYT_CNT(16 downto 9) <= FB_AD(23 downto 16);
+				DMA_BYT_CNT(8 downto 0) <= "000000000";
+			elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' then
+					DMA_BYT_CNT <= FB_AD;
+				else
+					DMA_BYT_CNT <= DMA_BYT_CNT;
+				end if;
+	END PROCESS;
+--------------------------------------------------------------------
+FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+DMA_STATUS(0) <= '1';													-- DMA OK
+DMA_STATUS(1) <= '1' when DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' else '0';					-- WENN byts UND NICHT MINUS
+DMA_STATUS(2) <= '0' when DMA_DRQ_I = '1' or SCSI_DRQ = '1' else '0'; 
+DMA_DRQQ <= '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ >  15 and DMA_MODUS(6) = '0' else 
+            '1' when DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' else '0';
+DMA_DRQ <= '1' when DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' else '0';
+-- DMA REQUEST: SPIKES AUSFILTERN  ------------------------------------------
+	process(FDC_CLK, nRSTO, DMA_DRQ_REG)
+	begin
+		if nRSTO = '0' THEN
+			DMA_DRQ_REG <= "00";
+		elsif rising_edge(FDC_CLK) then
+				DMA_DRQ_REG(0) <= DMA_DRQQ;
+				DMA_DRQ_REG(1) <= DMA_DRQ_REG(0) and DMA_DRQQ;
+			else
+				DMA_DRQ_REG <= DMA_DRQ_REG;
+			end if;
+	END PROCESS;
+-- DMA ADRESSE ------------------------------------------------------
+	process(MAIN_CLK, nRSTO, DMA_TOP_CS, DMA_TOP, nFB_WR, DMA_ADR_CS)
+	begin
+		if nRSTO = '0' THEN
+			DMA_TOP <= x"00";
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') then
+				DMA_TOP <= FB_AD(31 downto 24);
+			else 
+				DMA_TOP <= DMA_TOP;
+			end if;
+	END PROCESS;
+	process(MAIN_CLK, nRSTO, DMA_HIGH_CS, DMA_HIGH, nFB_WR, DMA_ADR_CS)
+	begin
+		if nRSTO = '0' THEN
+			DMA_HIGH <= x"00";
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') then
+				DMA_HIGH <= FB_AD(23 downto 16);
+			else
+				DMA_HIGH <= DMA_HIGH;
+			end if;
+	END PROCESS;
+	process(MAIN_CLK, nRSTO, DMA_MID_CS, DMA_MID, nFB_WR)
+	begin
+		DMA_MID <= DMA_MID;
+		if nRSTO = '0' THEN
+			DMA_MID <= x"00";
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then
+				if DMA_MID_CS = '1' then
+					DMA_MID <= FB_AD(23 downto 16);
+				elsif DMA_ADR_CS = '1' then
+						DMA_MID <= FB_AD(15 downto 8);
+					end if;
+			end if;
+	END PROCESS;
+	process(MAIN_CLK, nRSTO, DMA_LOW_CS, DMA_LOW, nFB_WR)
+	begin
+		DMA_LOW <= DMA_LOW;
+		if nRSTO = '0' THEN
+			DMA_LOW <= x"00";
+		elsif rising_edge(MAIN_CLK) and nFB_WR = '0' then
+				if DMA_LOW_CS = '1'then
+					DMA_LOW <= FB_AD(23 downto 16);
+				elsif DMA_ADR_CS = '1' then
+						DMA_LOW <= FB_AD(7 downto 0);
+					end if;
+			end if;
+	END PROCESS;
+--------------------------------------------------------------------------------------------
+DMA_TOP_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C304" and FB_B0 = '1' else '0';			-- F8608/2
+DMA_HIGH_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 1) = x"7C304" and FB_B1 = '1' else '0';			-- F8609/2		
+DMA_MID_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C305" and FB_B1 = '1' else '0';			-- F860B/2		
+DMA_LOW_CS <= '1' when nFB_CS1 = '0'  and FB_ADR(19 downto 1) = x"7C306" and FB_B1 = '1' else '0';			-- F860D/2	
+FB_AD(31 downto 24) <= DMA_TOP  when DMA_TOP_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(23 downto 16) <= DMA_HIGH when DMA_HIGH_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(23 downto 16) <= DMA_MID  when DMA_MID_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(23 downto 16) <= DMA_LOW  when DMA_LOW_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZ";
+-- DIRECTZUGRIFF
+DMA_DIRM_CS <= '1' when nFB_CS2 = '0' and     FB_ADR(26 downto 0) = x"20100" else '0';						-- F002'0100 WORD 
+DMA_ADR_CS  <= '1' when nFB_CS2 = '0' and     FB_ADR(26 downto 0) = x"20104" else '0';						-- F002'0104 LONG 
+DMA_BYT_CNT_CS  <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20108" else '0';						-- F002'0108 LONG 
+FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
+FB_AD(31 downto 16) <= DMA_MODUS when DMA_DIRM_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ";
+FB_AD <= DMA_BYT_CNT when DMA_BYT_CNT_CS = '1'  and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
+-- DMA RW TOGGLE ------------------------------------------
+	process(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD)
+	begin
+		if nRSTO = '0' THEN
+			DMA_DIR_OLD <= '0';
+		elsif rising_edge(MAIN_CLK) and  DMA_MODUS_CS = '0' then
+				DMA_DIR_OLD <= DMA_MODUS(8);
+			else
+				DMA_DIR_OLD <= DMA_DIR_OLD;
+			end if;
+	END PROCESS;
+CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD;	
+-- SCSI ----------------------------------------------------------------------------------
+    I_SCSI: WF5380_TOP_SOC
+        port map(
+            CLK					=> FDC_CLK,
+            RESETn				=> nRSTO,
+			ADR			        => CA2 & CA1 & CA0,
+			DATA_IN		        => CD_IN_FDC,	
+			DATA_OUT			=> SCSI_DOUT,
+			--DATA_EN			: out bit;
+            -- Bus and DMA controls:
+			CSn			        => '1',			--SCSI_CSn,  ABGESCHALTET
+			RDn		            => (not nFDC_WR) or (not SCSI_CS),
+			WRn	                =>      nFDC_WR  or (not SCSI_CS),
+            EOPn                => '1',
+			DACKn	            => nSCSI_DACK,
+			DRQ		            => SCSI_DRQ,
+			INT		            => SCSI_INT,
+--            READY                	=> 
+            -- SCSI bus:
+            DB_INn		        => SCSI_D,
+            DB_OUTn		        => DB_OUTn,
+            DB_EN               => DB_EN,
+            DBP_INn		        => SCSI_PAR,
+            DBP_OUTn	        => DBP_OUTn,
+            DBP_EN              => DBP_EN,				-- wenn 1 dann output
+            RST_INn             => nSCSI_RST,
+            RST_OUTn            => RST_OUTn,
+            RST_EN              => RST_EN,
+            BSY_INn             => nSCSI_BUSY,
+            BSY_OUTn            => BSY_OUTn,
+            BSY_EN              => BSY_EN,
+            SEL_INn             => nSCSI_SEL,
+            SEL_OUTn            => SEL_OUTn,
+            SEL_EN              => SEL_EN,
+            ACK_INn             => '1',
+            ACK_OUTn            => nSCSI_ACK,
+--            ACK_EN              => ACK_EN,
+            ATN_INn             => '1',
+            ATN_OUTn            => nSCSI_ATN,
+--            ATN_EN              => ATN_EN,
+            REQ_INn             => nSCSI_DRQ,
+--            REQ_OUTn            => REQ_OUTn,
+--            REQ_EN              => REQ_EN,
+            IOn_IN              => nSCSI_I_O,
+--            IOn_OUT             => IOn_OUT,
+--            IO_EN               => IO_EN,
+            CDn_IN              => nSCSI_C_D,
+--            CDn_OUT             => CDn_OUT,
+--            CD_EN               => CD_EN,
+            MSG_INn             => nSCSI_MSG
+--            MSG_OUTn            => MSG_OUTn,
+--            MSG_EN              => MSG_EN
+        );              
+-- SCSI ACSI ---------------------------------------------------------------
+SCSI_D <= DB_OUTn when DB_EN = '1' else "ZZZZZZZZ";
+SCSI_DIR <= '1'; --'0' when DB_EN = '1' else '1';	--ABGESCHALTET
+SCSI_PAR <= DBP_OUTn when DBP_EN = '1' else 'Z';
+nSCSI_RST <= RST_OUTn when RST_EN = '1' else 'Z';
+nSCSI_BUSY <= BSY_OUTn when BSY_EN = '1' else 'Z';
+nSCSI_SEL <= SEL_OUTn when SEL_EN = '1' else 'Z';
+ACSI_DIR <= '0';
+ACSI_D <= "ZZZZZZZZ";
+nACSI_CS <= '1';
+ACSI_A1 <= CA1;
+nACSI_RESET <= nRSTO;
+nACSI_ACK <= '1';
+----------------------------------------------------------------------------
+-- ROM-PORT TA KOMMT FROM DEFAULT TA = 16 BUSCYCLEN = 500ns
+----------------------------------------------------------------------------
+ROM_CS <= '1' when nFB_CS1 = '0' and nFB_WR = '1' and FB_ADR(19 downto 17) = x"5" else '0';		-- FFF A'0000/2'0000
+nROM4 <= '0' when ROM_CS = '1' and FB_ADR(16) = '0' else '1';
+nROM3 <= '0' when ROM_CS = '1' and FB_ADR(16) = '1' else '1';
+----------------------------------------------------------------------------
+-- ACIA KEYBOARD
+----------------------------------------------------------------------------
+	I_ACIA_KEYBOARD: WF6850IP_TOP_SOC
+	  port map(
+			CLK					=> MAIN_CLK,
+			RESETn				=> nRSTO,
+
+			CS2n				=> FB_ADR(2),
+			CS1					=> '1',
+			CS0					=> ACIA_CS_I,
+            E					=> ACIA_CS_I,
+			RWn					=> nFB_WR,
+			RS					=> FB_ADR(1),
+
+			DATA_IN				=> FB_AD(31 downto 24),
+			DATA_OUT			=> DATA_OUT_ACIA_I,
+--			DATA_EN				=> DATA_EN_ACIA_I,
+
+			TXCLK				=> CLK500k,
+			RXCLK				=> CLK500k,
+			RXDATA				=> KEYB_RxD,
+
+			CTSn				=> '0',
+			DCDn				=> '0',
+        
+			IRQn				=> IRQ_KEYBDn,
+			TXDATA				=> AMKB_TX
+			--RTSn				=> -- Not used.
+		);                                              
+ACIA_CS_I <= '1' when nFB_CS1 = '0'and FB_ADR(19 downto 3) = x"1FF80" else '0';		-- FFC00-FFC07 FFC00/8
+KEYB_RxD <= '1' when AMKB_REG(3) = '1' or PIC_AMKB_RX = '0' else '0';				-- TASTATUR DATEN VOM PIC(PS2) OR NORMAL
+FB_AD(31 downto 24) <= DATA_OUT_ACIA_I when ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' else "ZZZZZZZZ";
+-- AMKB_TX: SPIKES AUSFILTERN  ------------------------------------------
+	process(CLK2M, AMKB_RX, AMKB_REG)
+	begin
+		if rising_edge(CLK2M) then
+			IF AMKB_RX = '0' THEN
+				IF AMKB_REG < 16 THEN
+					AMKB_REG <= "00000";
+				ELSE
+					AMKB_REG <= AMKB_REG - 1;
+				END IF;
+			ELSE
+				IF AMKB_REG > 15 THEN
+					AMKB_REG <= "11111";
+				ELSE
+					AMKB_REG <= AMKB_REG + 1;
+				END IF;
+			END IF;
+		ELSE
+			AMKB_REG <= AMKB_REG;
+		end if;
+	END PROCESS;
+----------------------------------------------------------------------------
+-- ACIA MIDI
+----------------------------------------------------------------------------
+	I_ACIA_MIDI: WF6850IP_TOP_SOC
+		port map(
+			CLK					=> MAIN_CLK,
+			RESETn				=> nRSTO,
+
+			CS2n				=> '0',
+			CS1					=> FB_ADR(2),
+			CS0					=> ACIA_CS_I,
+            E					=> ACIA_CS_I,
+			RWn					=> nFB_WR,
+			RS					=> FB_ADR(1),
+
+			DATA_IN				=> FB_AD(31 downto 24),
+			DATA_OUT			=> DATA_OUT_ACIA_II,
+--			DATA_EN				=> DATA_EN_ACIA_II,
+
+			TXCLK				=> CLK500k,
+			RXCLK				=> CLK500k,
+			RXDATA				=> MIDI_IN,
+			CTSn				=> '0',
+			DCDn				=> '0',
+        
+			IRQn				=> IRQ_MIDIn,
+			TXDATA				=> MIDI_OUT
+			--RTSn				=> -- Not used.
+	    );                                              
+MIDI_TLR <= MIDI_OUT;
+MIDI_OLR <= MIDI_OUT;
+FB_AD(31 downto 24) <= DATA_OUT_ACIA_II when ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+----------------------------------------------------------------------------
+-- MFP
+----------------------------------------------------------------------------
+	I_MFP: WF68901IP_TOP_SOC
+		port map(  
+			-- System control:
+			CLK					=> MAIN_CLK,
+			RESETn				=> nRSTO,
+			-- Asynchronous bus control:
+			DSn					=> not LDS,
+			CSn					=> not MFP_CS,
+			RWn					=> nFB_WR,
+ 			DTACKn				=> DTACK_OUT_MFPn,
+			-- Data and Adresses:
+			RS					=> FB_ADR(5 downto 1),
+			DATA_IN				=> FB_AD(23 downto 16),
+			DATA_OUT			=> DATA_OUT_MFP,
+--			DATA_EN				=> DATA_EN_MFP,
+            GPIP_IN(7)			=> not DMA_DRQ_Q,
+            GPIP_IN(6)			=> not RI,
+			GPIP_IN(5)			=> DINTn,
+			GPIP_IN(4)			=> IRQ_ACIAn,
+			GPIP_IN(3)			=> DSP_INT,
+            GPIP_IN(2)			=> not CTS,
+            GPIP_IN(1)			=> not DCD,
+            GPIP_IN(0)			=> LP_BUSY,
+			-- GPIP_OUT			=>, -- Not used; all GPIPs are direction input.
+			-- GPIP_EN			=>, -- Not used; all GPIPs are direction input.
+			-- Interrupt control:
+			IACKn				=> not MFP_INTACK,
+			IEIn				=> '0',
+			-- IEOn				=>, -- Not used.
+			IRQn				=> nMFP_INT,
+			-- Timers and timer control:
+			XTAL1				=> CLK2M4576,
+            TAI					=> '0',
+			TBI				    => nBLANK,
+            -- TAO				=>,
+			-- TBO				=>,
+            -- TCO				=>,
+			TDO					=> TDO,
+			-- Serial I/O control:
+			RC					=> TDO,
+			TC					=> TDO,
+			SI					=> RxD, 
+			SO					=> TxD
+			-- SO_EN			=> MFP_SO_EN
+			-- DMA control:
+			-- RRn				=>,
+			-- TRn				=>
+		);
+
+MFP_CS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 6) = x"3FE8" else '0';		-- FFA00/40
+MFP_INTACK <= '1' when nFB_CS2 = '0' and FB_ADR(26 downto 0) = x"20000" else '0'; 	--F002'0000
+LDS <= '1' when MFP_CS = '1' or MFP_INTACK = '1' else '0';
+FB_AD(23 downto 16) <= DATA_OUT_MFP when MFP_CS = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(31 downto 10) <= "0000000000000000000000" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZ";
+FB_AD(9 downto 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+FB_AD(1 downto 0) <= "00" when MFP_INTACK = '1' and nFB_OE = '0' else "ZZ";
+DINTn <= '0' when IDE_INT = '1' AND ACP_CONFIG[28] = '1' else
+         '0' when FDINT = '1' else
+         '0' when SCSI_INT = '1' AND ACP_CONFIG[28] = '1' else '1';
+-- TASTATUR UND KEYBOARD INTERRUPT: SPIKES AUSFILTERN  ------------------------------------------
+	process(MAIN_CLK,nRSTO,IRQ_ACIAn,IRQ_KEYBDn,IRQ_MIDIn)
+	begin
+		if nRSTO = '0' THEN
+			IRQ_ACIAn <= '1';
+		elsif rising_edge(MAIN_CLK) then
+				IRQ_ACIAn <= IRQ_KEYBDn and IRQ_MIDIn;
+			else
+				IRQ_ACIAn <= IRQ_ACIAn;
+			end if;
+	END PROCESS;
+----------------------------------------------------------------------------
+-- Sound
+----------------------------------------------------------------------------
+ 	I_SOUND: WF2149IP_TOP_SOC
+		port map(
+			SYS_CLK				=> MAIN_CLK,
+			RESETn				=> nRSTO,
+
+			WAV_CLK				=> CLK2M,
+			SELn				=> '1',
+
+			BDIR				=> SNDIR_I,
+			BC2					=> '1',
+			BC1					=> SNDCS_I,
+
+			A9n					=> '0',
+			A8					=> '1',
+			DA_IN				=> FB_AD(31 downto 24),
+			DA_OUT 				=> DA_OUT_X,
+
+			IO_A_IN				=> x"00", -- All port pins are dedicated outputs.
+			IO_A_OUT(7)			=> nnIDE_RES,
+            IO_A_OUT(6)			=> LP_DIR_X,
+			IO_A_OUT(5)			=> LP_STR,
+			IO_A_OUT(4)			=> DTR,
+			IO_A_OUT(3)			=> RTS,
+--			IO_A_OUT(2)			=> FDD_D1SEL,
+			IO_A_OUT(1)			=> DSA_D,
+			IO_A_OUT(0)			=> nSDSEL,
+			-- IO_A_EN			=>, -- Not required.
+			IO_B_IN				=> LP_D,
+			IO_B_OUT			=> LP_D_X,
+ --			IO_B_EN				=> IO_B_EN,
+
+			OUT_A				=> YM_QA,
+			OUT_B				=> YM_QB,
+			OUT_C				=> YM_QC
+		);
+
+SNDCS <= '1' when nFB_CS1 = '0' and FB_ADR(19 downto 2) = x"3E200" else '0';		-- 8800-8803 F8800/4
+SNDCS_I <= '1' when SNDCS = '1' and FB_ADR (1 downto 1) = "0" else '0';
+SNDIR_I <= '1' when SNDCS = '1' and nFB_WR = '0' else '0';
+FB_AD(31 downto 24) <= DA_OUT_X when SNDCS_I = '1' and nFB_OE = '0' else "ZZZZZZZZ";
+LP_D <= LP_D_X when LP_DIR_X = '0' else "ZZZZZZZZ";
+LP_DIR <= LP_DIR_X;
+
+END FalconIO_SDCard_IDE_CF_architecture;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
new file mode 100644
index 0000000..edef447
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
@@ -0,0 +1,406 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- Atari Coldfire IP Core				                          ----
+----                                                              ----
+---- This file is part of the Atari Coldfire project.             ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2009 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 1.0 Initial Release, 20090925.
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package FalconIO_SDCard_IDE_CF_PKG is
+	component WF25915IP_TOP_V1_SOC -- GLUE.
+		port (
+		    -- Clock system:
+			GL_CLK		: in std_logic; -- Originally 8MHz.
+			GL_CLK_016	: in std_logic; -- One sixteenth of GL_CLK.
+			
+            -- Core address select:
+            GL_ROMSEL_FC_E0n    : in std_logic;
+            EN_RAM_14MB         : in std_logic;
+			-- Adress decoder outputs:
+			GL_ROM_6n	: out std_logic;	-- STE.
+			GL_ROM_5n	: out std_logic;	-- STE.
+			GL_ROM_4n	: out std_logic;	-- ST.
+			GL_ROM_3n	: out std_logic;	-- ST.
+			GL_ROM_2n	: out std_logic;
+			GL_ROM_1n	: out std_logic;
+			GL_ROM_0n	: out std_logic;
+			
+			GL_ACIACS	: out std_logic;
+			GL_MFPCSn	: out std_logic;
+			GL_SNDCSn	: out std_logic;
+			GL_FCSn		: out std_logic;
+
+			GL_STE_SNDCS	: out std_logic; 	-- STE: Sound chip select.
+			GL_STE_SNDIR	: out std_logic; 	-- STE: Data flow direction control.
+
+			GL_STE_RTCCSn	: out std_logic; 	--STE only.
+			GL_STE_RTC_WRn	: out std_logic; 	--STE only.
+			GL_STE_RTC_RDn	: out std_logic;	--STE only.
+
+			-- 6800 peripheral control, 
+			GL_VPAn			: out std_logic;
+			GL_VMAn 		: in std_logic;
+			
+			GL_DMA_SYNC		: in std_logic;
+			GL_DEVn			: out std_logic;
+			GL_RAMn			: out std_logic;
+			GL_DMAn			: out std_logic;
+			
+			-- Interrupt system:
+			-- Comment out GL_AVECn for CPUs which do not provide the VMAn signal.
+			GL_AVECn		: out std_logic;
+			GL_STE_FDINT	: in std_logic; 	-- Floppy disk interrupt; STE only.
+			GL_STE_HDINTn	: in std_logic; 	-- Hard disk interrupt; STE only.
+			GL_MFPINTn		: in std_logic; 	-- ST.
+			GL_STE_EINT3n	: in std_logic; 	--STE only.
+			GL_STE_EINT5n	: in std_logic; 	--STE only.
+			GL_STE_EINT7n	: in std_logic; 	--STE only.
+			GL_STE_DINTn	: out std_logic; 	-- Disk interrupt (floppy or hard disk); STE only.
+			GL_IACKn		: out std_logic; 	-- ST.
+			GL_STE_IPL2n	: out std_logic; 	--STE only.
+			GL_STE_IPL1n	: out std_logic; 	--STE only.
+			GL_STE_IPL0n	: out std_logic; 	--STE only.
+			
+			-- Video timing:
+			GL_BLANKn		: out std_logic;
+			GL_DE			: out std_logic;
+			GL_MULTISYNC	: in std_logic_vector(3 downto 2);
+            GL_VIDEO_HIMODE : out std_logic;
+			GL_HSYNC_INn	: in std_logic;
+			GL_HSYNC_OUTn	: out std_logic;
+			GL_VSYNC_INn	: in std_logic;
+			GL_VSYNC_OUTn	: out std_logic;
+			GL_SYNC_OUT_EN	: out std_logic;
+			
+			-- Bus arstd_logicration control:
+			GL_RDY_INn		: in std_logic;
+			GL_RDY_OUTn		: out std_logic;
+			GL_BRn			: out std_logic;
+			GL_BGIn			: in std_logic;
+			GL_BGOn			: out std_logic;
+			GL_BGACK_INn	: in std_logic;
+			GL_BGACK_OUTn	: out std_logic;
+
+			-- Adress and data bus:
+			GL_ADDRESS		: in std_logic_vector(23 downto 1);
+			-- ST: put the data bus to 1 downto 0. 
+			-- STE: put the data out bus to 15 downto 0. 
+			GL_DATA_IN		: in std_logic_vector(7 downto 0);
+			GL_DATA_OUT		: out std_logic_vector(15 downto 0);
+			GL_DATA_EN		: out std_logic;
+			
+			-- Asynchronous bus control:
+			GL_RWn_IN		: in std_logic;
+			GL_RWn_OUT		: out std_logic;
+			GL_AS_INn		: in std_logic;
+			GL_AS_OUTn		: out std_logic;
+			GL_UDS_INn		: in std_logic;
+			GL_UDS_OUTn		: out std_logic;
+			GL_LDS_INn		: in std_logic;
+			GL_LDS_OUTn		: out std_logic;
+			GL_DTACK_INn	: in std_logic;
+			GL_DTACK_OUTn	: out std_logic;
+			GL_CTRL_EN		: out std_logic;
+			
+			-- System control:
+			GL_RESETn		: in std_logic;
+			GL_BERRn		: out std_logic;
+			
+			-- Processor function codes:
+			GL_FC	: in std_logic_vector(2 downto 0);
+
+			-- STE enhancements:
+			GL_STE_FDDS		: out std_logic; 		-- Floppy type select (HD or DD).
+			GL_STE_FCCLK	: out std_logic; 		-- Floppy controller clock select.
+			GL_STE_JOY_RHn	: out std_logic; 		-- Read only FF9202 high byte.
+			GL_STE_JOY_RLn	: out std_logic; 		-- Read only FF9202 low byte.
+			GL_STE_JOY_WL	: out std_logic; 		-- Write only FF9202 low byte.
+			GL_STE_JOY_WEn	: out std_logic; 		-- Write only FF9202 output enable.
+			GL_STE_BUTTONn	: out std_logic; 		-- Read only FF9000 low byte.		
+			GL_STE_PAD0Xn	: in std_logic; 		-- Counter input for the Paddle 0X.
+			GL_STE_PAD0Yn	: in std_logic; 		-- Counter input for the Paddle 0Y.
+			GL_STE_PAD1Xn	: in std_logic; 		-- Counter input for the Paddle 1X.
+			GL_STE_PAD1Yn	: in std_logic; 		-- Counter input for the Paddle 1Y.
+			GL_STE_PADRSTn	: out std_logic; 		-- Paddle monoflops reset.
+			GL_STE_PENn		: in std_logic; 		-- Input of the light pen.
+			GL_STE_SCCn		: out std_logic;	-- Select signal for the STE or TT SCC chip.
+			GL_STE_CPROGn	: out std_logic	-- Select signal for the STE's cache processor.
+			);
+	end component WF25915IP_TOP_V1_SOC;
+
+    component WF5380_TOP_SOC
+        port (
+            CLK			: in std_logic;
+            RESETn	    : in std_logic;
+            ADR			: in std_logic_vector(2 downto 0);
+            DATA_IN		: in std_logic_vector(7 downto 0);
+            DATA_OUT	: out std_logic_vector(7 downto 0);
+            DATA_EN		: out std_logic;
+            CSn			: in std_logic;
+            RDn		    : in std_logic;
+            WRn	        : in std_logic;
+            EOPn        : in std_logic;
+            DACKn	    : in std_logic;
+            DRQ		    : out std_logic;
+            INT		    : out std_logic;
+            READY       : out std_logic;
+            DB_INn		: in std_logic_vector(7 downto 0);
+            DB_OUTn		: out std_logic_vector(7 downto 0);
+            DB_EN       : out std_logic;
+            DBP_INn		: in std_logic;
+            DBP_OUTn	: out std_logic;
+            DBP_EN      : out std_logic;
+            RST_INn     : in std_logic;
+            RST_OUTn    : out std_logic;
+            RST_EN      : out std_logic;
+            BSY_INn     : in std_logic;
+            BSY_OUTn    : out std_logic;
+            BSY_EN      : out std_logic;
+            SEL_INn     : in std_logic;
+            SEL_OUTn    : out std_logic;
+            SEL_EN      : out std_logic;
+            ACK_INn     : in std_logic;
+            ACK_OUTn    : out std_logic;
+            ACK_EN      : out std_logic;
+            ATN_INn     : in std_logic;
+            ATN_OUTn    : out std_logic;
+            ATN_EN      : out std_logic;
+            REQ_INn     : in std_logic;
+            REQ_OUTn    : out std_logic;
+            REQ_EN      : out std_logic;
+            IOn_IN      : in std_logic;
+            IOn_OUT     : out std_logic;
+            IO_EN       : out std_logic;
+            CDn_IN      : in std_logic;
+            CDn_OUT     : out std_logic;
+            CD_EN       : out std_logic;
+            MSG_INn     : in std_logic;
+            MSG_OUTn    : out std_logic;
+            MSG_EN      : out std_logic
+        );
+    end component WF5380_TOP_SOC;
+
+	component WF1772IP_TOP_SOC -- FDC.
+		port (
+			CLK			: in std_logic; -- 16MHz clock!
+			RESETn		: in std_logic;
+			CSn			: in std_logic;
+			RWn			: in std_logic;
+			A1, A0		: in std_logic;
+			DATA_IN		: in std_logic_vector(7 downto 0);
+			DATA_OUT	: out std_logic_vector(7 downto 0);
+			DATA_EN		: out std_logic;
+			RDn			: in std_logic;
+			TR00n		: in std_logic;
+			IPn			: in std_logic;
+			WPRTn		: in std_logic;
+			DDEn		: in std_logic;
+			HDTYPE		: in std_logic; -- '0' = DD disks, '1' = HD disks.
+			MO			: out std_logic;
+			WG			: out std_logic;
+			WD			: out std_logic;
+			STEP		: out std_logic;
+			DIRC		: out std_logic;
+			DRQ			: out std_logic;
+			INTRQ		: out std_logic
+		);
+	end component WF1772IP_TOP_SOC;
+
+	component WF68901IP_TOP_SOC -- MFP.
+		port (  -- System control:
+				CLK			: in std_logic;
+				RESETn		: in std_logic;
+				
+				-- Asynchronous bus control:
+				DSn			: in std_logic;
+				CSn			: in std_logic;
+				RWn			: in std_logic;
+				DTACKn		: out std_logic;
+				
+				-- Data and Adresses:
+				RS			: in std_logic_vector(5 downto 1);
+				DATA_IN		: in std_logic_vector(7 downto 0);
+				DATA_OUT	: out std_logic_vector(7 downto 0);
+				DATA_EN		: out std_logic;
+				GPIP_IN		: in std_logic_vector(7 downto 0);
+				GPIP_OUT	: out std_logic_vector(7 downto 0);
+				GPIP_EN		: out std_logic_vector(7 downto 0);
+				
+				-- Interrupt control:
+				IACKn		: in std_logic;
+				IEIn		: in std_logic;
+				IEOn		: out std_logic;
+				IRQn		: out std_logic;
+				
+				-- Timers and timer control:
+				XTAL1		: in std_logic; -- Use an oszillator instead of a quartz.
+				TAI			: in std_logic;
+				TBI			: in std_logic;
+				TAO			: out std_logic;			
+				TBO			: out std_logic;			
+				TCO			: out std_logic;			
+				TDO			: out std_logic;			
+				
+				-- Serial I/O control:
+				RC			: in std_logic;
+				TC			: in std_logic;
+				SI			: in std_logic;
+				SO			: out std_logic;
+				SO_EN		: out std_logic;
+				
+				-- DMA control:
+				RRn			: out std_logic;
+				TRn			: out std_logic			
+		);
+	end component WF68901IP_TOP_SOC;
+
+	component WF2149IP_TOP_SOC -- Sound.
+		port(
+			
+			SYS_CLK		: in std_logic; -- Read the inforation in the header!
+			RESETn   	: in std_logic;
+
+			WAV_CLK		: in std_logic; -- Read the inforation in the header!
+			SELn		: in std_logic;
+			
+			BDIR		: in std_logic;
+			BC2, BC1	: in std_logic;
+
+			A9n, A8		: in std_logic;
+			DA_IN		: in std_logic_vector(7 downto 0);
+			DA_OUT		: out std_logic_vector(7 downto 0);
+			DA_EN		: out std_logic;
+			
+			IO_A_IN		: in std_logic_vector(7 downto 0);
+			IO_A_OUT	: out std_logic_vector(7 downto 0);
+			IO_A_EN		: out std_logic;
+			IO_B_IN		: in std_logic_vector(7 downto 0);
+			IO_B_OUT	: out std_logic_vector(7 downto 0);
+			IO_B_EN		: out std_logic;
+
+			OUT_A		: out std_logic; -- Analog (PWM) outputs.
+			OUT_B		: out std_logic;
+			OUT_C		: out std_logic
+		);
+	end component WF2149IP_TOP_SOC;
+
+	component WF6850IP_TOP_SOC -- ACIA.
+	  port (
+			CLK					: in std_logic;
+	        RESETn				: in std_logic;
+
+	        CS2n, CS1, CS0		: in std_logic;
+	        E		       		: in std_logic;   
+	        RWn              	: in std_logic;
+	        RS					: in std_logic;
+
+	        DATA_IN		        : in std_logic_vector(7 downto 0);   
+	        DATA_OUT	        : out std_logic_vector(7 downto 0);   
+			DATA_EN				: out std_logic;
+
+	        TXCLK				: in std_logic;
+	        RXCLK				: in std_logic;
+	        RXDATA				: in std_logic;
+	        CTSn				: in std_logic;
+	        DCDn				: in std_logic;
+	        
+	        IRQn				: out std_logic;
+	        TXDATA				: out std_logic;   
+	        RTSn				: out std_logic
+	       );                                              
+	end component WF6850IP_TOP_SOC;
+
+	component WF_SD_CARD
+		port (
+			RESETn			: in std_logic;
+			CLK				: in std_logic;
+			ACSI_A1			: in std_logic;
+			ACSI_CSn		: in std_logic;
+			ACSI_ACKn		: in std_logic;
+			ACSI_INTn		: out std_logic;
+			ACSI_DRQn		: out std_logic;
+			ACSI_D_IN		: in std_logic_vector(7 downto 0);
+			ACSI_D_OUT		: out std_logic_vector(7 downto 0);
+			ACSI_D_EN		: out std_logic;
+			MC_DO			: in std_logic;
+			MC_PIO_DMAn		: in std_logic;
+			MC_RWn			: in std_logic;
+			MC_CLR_CMD		: in std_logic;
+			MC_DONE			: out std_logic;
+			MC_GOT_CMD		: out std_logic;
+			MC_D_IN			: in std_logic_vector(7 downto 0);
+			MC_D_OUT		: out std_logic_vector(7 downto 0);
+			MC_D_EN			: out std_logic
+	      );
+	end component WF_SD_CARD;
+
+	component dcfifo0 
+		PORT (
+			aclr			: IN STD_LOGIC ;
+			data			: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			rdclk			: IN STD_LOGIC ;
+			rdreq			: IN STD_LOGIC ;
+			wrclk			: IN STD_LOGIC ;
+			wrreq			: IN STD_LOGIC ;
+			q				: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			wrusedw			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0) 
+	);
+	end component dcfifo0;
+	
+	component dcfifo1
+		PORT (
+			aclr			: IN STD_LOGIC ;
+			data			: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			rdclk			: IN STD_LOGIC ;
+			rdreq			: IN STD_LOGIC ;
+			wrclk			: IN STD_LOGIC ;
+			wrreq			: IN STD_LOGIC ;
+			q				: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			rdusedw			: OUT STD_LOGIC_VECTOR (9 DOWNTO 0) 
+		);
+	end component;
+
+
+end FalconIO_SDCard_IDE_CF_PKG;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak
new file mode 100644
index 0000000..4f42cf2
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd.bak
@@ -0,0 +1,406 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- Atari Coldfire IP Core				                          ----
+----                                                              ----
+---- This file is part of the Atari Coldfire project.             ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2009 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 1.0 Initial Release, 20090925.
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package FalconIO_SDCard_IDE_CF_PKG is
+	component WF25915IP_TOP_V1_SOC -- GLUE.
+		port (
+		    -- Clock system:
+			GL_CLK		: in std_logic; -- Originally 8MHz.
+			GL_CLK_016	: in std_logic; -- One sixteenth of GL_CLK.
+			
+            -- Core address select:
+            GL_ROMSEL_FC_E0n    : in std_logic;
+            EN_RAM_14MB         : in std_logic;
+			-- Adress decoder outputs:
+			GL_ROM_6n	: out std_logic;	-- STE.
+			GL_ROM_5n	: out std_logic;	-- STE.
+			GL_ROM_4n	: out std_logic;	-- ST.
+			GL_ROM_3n	: out std_logic;	-- ST.
+			GL_ROM_2n	: out std_logic;
+			GL_ROM_1n	: out std_logic;
+			GL_ROM_0n	: out std_logic;
+			
+			GL_ACIACS	: out std_logic;
+			GL_MFPCSn	: out std_logic;
+			GL_SNDCSn	: out std_logic;
+			GL_FCSn		: out std_logic;
+
+			GL_STE_SNDCS	: out std_logic; 	-- STE: Sound chip select.
+			GL_STE_SNDIR	: out std_logic; 	-- STE: Data flow direction control.
+
+			GL_STE_RTCCSn	: out std_logic; 	--STE only.
+			GL_STE_RTC_WRn	: out std_logic; 	--STE only.
+			GL_STE_RTC_RDn	: out std_logic;	--STE only.
+
+			-- 6800 peripheral control, 
+			GL_VPAn			: out std_logic;
+			GL_VMAn 		: in std_logic;
+			
+			GL_DMA_SYNC		: in std_logic;
+			GL_DEVn			: out std_logic;
+			GL_RAMn			: out std_logic;
+			GL_DMAn			: out std_logic;
+			
+			-- Interrupt system:
+			-- Comment out GL_AVECn for CPUs which do not provide the VMAn signal.
+			GL_AVECn		: out std_logic;
+			GL_STE_FDINT	: in std_logic; 	-- Floppy disk interrupt; STE only.
+			GL_STE_HDINTn	: in std_logic; 	-- Hard disk interrupt; STE only.
+			GL_MFPINTn		: in std_logic; 	-- ST.
+			GL_STE_EINT3n	: in std_logic; 	--STE only.
+			GL_STE_EINT5n	: in std_logic; 	--STE only.
+			GL_STE_EINT7n	: in std_logic; 	--STE only.
+			GL_STE_DINTn	: out std_logic; 	-- Disk interrupt (floppy or hard disk); STE only.
+			GL_IACKn		: out std_logic; 	-- ST.
+			GL_STE_IPL2n	: out std_logic; 	--STE only.
+			GL_STE_IPL1n	: out std_logic; 	--STE only.
+			GL_STE_IPL0n	: out std_logic; 	--STE only.
+			
+			-- Video timing:
+			GL_BLANKn		: out std_logic;
+			GL_DE			: out std_logic;
+			GL_MULTISYNC	: in std_logic_vector(3 downto 2);
+            GL_VIDEO_HIMODE : out std_logic;
+			GL_HSYNC_INn	: in std_logic;
+			GL_HSYNC_OUTn	: out std_logic;
+			GL_VSYNC_INn	: in std_logic;
+			GL_VSYNC_OUTn	: out std_logic;
+			GL_SYNC_OUT_EN	: out std_logic;
+			
+			-- Bus arstd_logicration control:
+			GL_RDY_INn		: in std_logic;
+			GL_RDY_OUTn		: out std_logic;
+			GL_BRn			: out std_logic;
+			GL_BGIn			: in std_logic;
+			GL_BGOn			: out std_logic;
+			GL_BGACK_INn	: in std_logic;
+			GL_BGACK_OUTn	: out std_logic;
+
+			-- Adress and data bus:
+			GL_ADDRESS		: in std_logic_vector(23 downto 1);
+			-- ST: put the data bus to 1 downto 0. 
+			-- STE: put the data out bus to 15 downto 0. 
+			GL_DATA_IN		: in std_logic_vector(7 downto 0);
+			GL_DATA_OUT		: out std_logic_vector(15 downto 0);
+			GL_DATA_EN		: out std_logic;
+			
+			-- Asynchronous bus control:
+			GL_RWn_IN		: in std_logic;
+			GL_RWn_OUT		: out std_logic;
+			GL_AS_INn		: in std_logic;
+			GL_AS_OUTn		: out std_logic;
+			GL_UDS_INn		: in std_logic;
+			GL_UDS_OUTn		: out std_logic;
+			GL_LDS_INn		: in std_logic;
+			GL_LDS_OUTn		: out std_logic;
+			GL_DTACK_INn	: in std_logic;
+			GL_DTACK_OUTn	: out std_logic;
+			GL_CTRL_EN		: out std_logic;
+			
+			-- System control:
+			GL_RESETn		: in std_logic;
+			GL_BERRn		: out std_logic;
+			
+			-- Processor function codes:
+			GL_FC	: in std_logic_vector(2 downto 0);
+
+			-- STE enhancements:
+			GL_STE_FDDS		: out std_logic; 		-- Floppy type select (HD or DD).
+			GL_STE_FCCLK	: out std_logic; 		-- Floppy controller clock select.
+			GL_STE_JOY_RHn	: out std_logic; 		-- Read only FF9202 high byte.
+			GL_STE_JOY_RLn	: out std_logic; 		-- Read only FF9202 low byte.
+			GL_STE_JOY_WL	: out std_logic; 		-- Write only FF9202 low byte.
+			GL_STE_JOY_WEn	: out std_logic; 		-- Write only FF9202 output enable.
+			GL_STE_BUTTONn	: out std_logic; 		-- Read only FF9000 low byte.		
+			GL_STE_PAD0Xn	: in std_logic; 		-- Counter input for the Paddle 0X.
+			GL_STE_PAD0Yn	: in std_logic; 		-- Counter input for the Paddle 0Y.
+			GL_STE_PAD1Xn	: in std_logic; 		-- Counter input for the Paddle 1X.
+			GL_STE_PAD1Yn	: in std_logic; 		-- Counter input for the Paddle 1Y.
+			GL_STE_PADRSTn	: out std_logic; 		-- Paddle monoflops reset.
+			GL_STE_PENn		: in std_logic; 		-- Input of the light pen.
+			GL_STE_SCCn		: out std_logic;	-- Select signal for the STE or TT SCC chip.
+			GL_STE_CPROGn	: out std_logic	-- Select signal for the STE's cache processor.
+			);
+	end component WF25915IP_TOP_V1_SOC;
+
+    component WF5380_TOP_SOC
+        port (
+            CLK			: in std_logic;
+            RESETn	    : in std_logic;
+            ADR			: in std_logic_vector(2 downto 0);
+            DATA_IN		: in std_logic_vector(7 downto 0);
+            DATA_OUT	: out std_logic_vector(7 downto 0);
+            DATA_EN		: out std_logic;
+            CSn			: in std_logic;
+            RDn		    : in std_logic;
+            WRn	        : in std_logic;
+            EOPn        : in std_logic;
+            DACKn	    : in std_logic;
+            DRQ		    : out std_logic;
+            INT		    : out std_logic;
+            READY       : out std_logic;
+            DB_INn		: in std_logic_vector(7 downto 0);
+            DB_OUTn		: out std_logic_vector(7 downto 0);
+            DB_EN       : out std_logic;
+            DBP_INn		: in std_logic;
+            DBP_OUTn	: out std_logic;
+            DBP_EN      : out std_logic;
+            RST_INn     : in std_logic;
+            RST_OUTn    : out std_logic;
+            RST_EN      : out std_logic;
+            BSY_INn     : in std_logic;
+            BSY_OUTn    : out std_logic;
+            BSY_EN      : out std_logic;
+            SEL_INn     : in std_logic;
+            SEL_OUTn    : out std_logic;
+            SEL_EN      : out std_logic;
+            ACK_INn     : in std_logic;
+            ACK_OUTn    : out std_logic;
+            ACK_EN      : out std_logic;
+            ATN_INn     : in std_logic;
+            ATN_OUTn    : out std_logic;
+            ATN_EN      : out std_logic;
+            REQ_INn     : in std_logic;
+            REQ_OUTn    : out std_logic;
+            REQ_EN      : out std_logic;
+            IOn_IN      : in std_logic;
+            IOn_OUT     : out std_logic;
+            IO_EN       : out std_logic;
+            CDn_IN      : in std_logic;
+            CDn_OUT     : out std_logic;
+            CD_EN       : out std_logic;
+            MSG_INn     : in std_logic;
+            MSG_OUTn    : out std_logic;
+            MSG_EN      : out std_logic
+        );
+    end component WF5380_TOP_SOC;
+
+	component WF1772IP_TOP_SOC -- FDC.
+		port (
+			CLK			: in std_logic; -- 16MHz clock!
+			RESETn		: in std_logic;
+			CSn			: in std_logic;
+			RWn			: in std_logic;
+			A1, A0		: in std_logic;
+			DATA_IN		: in std_logic_vector(7 downto 0);
+			DATA_OUT	: out std_logic_vector(7 downto 0);
+			DATA_EN		: out std_logic;
+			RDn			: in std_logic;
+			TR00n		: in std_logic;
+			IPn			: in std_logic;
+			WPRTn		: in std_logic;
+			DDEn		: in std_logic;
+			HDTYPE		: in std_logic; -- '0' = DD disks, '1' = HD disks.
+			MO			: out std_logic;
+			WG			: out std_logic;
+			WD			: out std_logic;
+			STEP		: out std_logic;
+			DIRC		: out std_logic;
+			DRQ			: out std_logic;
+			INTRQ		: out std_logic
+		);
+	end component WF1772IP_TOP_SOC;
+
+	component WF68901IP_TOP_SOC -- MFP.
+		port (  -- System control:
+				CLK			: in std_logic;
+				RESETn		: in std_logic;
+				
+				-- Asynchronous bus control:
+				DSn			: in std_logic;
+				CSn			: in std_logic;
+				RWn			: in std_logic;
+				DTACKn		: out std_logic;
+				
+				-- Data and Adresses:
+				RS			: in std_logic_vector(5 downto 1);
+				DATA_IN		: in std_logic_vector(7 downto 0);
+				DATA_OUT	: out std_logic_vector(7 downto 0);
+				DATA_EN		: out std_logic;
+				GPIP_IN		: in std_logic_vector(7 downto 0);
+				GPIP_OUT	: out std_logic_vector(7 downto 0);
+				GPIP_EN		: out std_logic_vector(7 downto 0);
+				
+				-- Interrupt control:
+				IACKn		: in std_logic;
+				IEIn		: in std_logic;
+				IEOn		: out std_logic;
+				IRQn		: out std_logic;
+				
+				-- Timers and timer control:
+				XTAL1		: in std_logic; -- Use an oszillator instead of a quartz.
+				TAI			: in std_logic;
+				TBI			: in std_logic;
+				TAO			: out std_logic;			
+				TBO			: out std_logic;			
+				TCO			: out std_logic;			
+				TDO			: out std_logic;			
+				
+				-- Serial I/O control:
+				RC			: in std_logic;
+				TC			: in std_logic;
+				SI			: in std_logic;
+				SO			: out std_logic;
+				SO_EN		: out std_logic;
+				
+				-- DMA control:
+				RRn			: out std_logic;
+				TRn			: out std_logic			
+		);
+	end component WF68901IP_TOP_SOC;
+
+	component WF2149IP_TOP_SOC -- Sound.
+		port(
+			
+			SYS_CLK		: in std_logic; -- Read the inforation in the header!
+			RESETn   	: in std_logic;
+
+			WAV_CLK		: in std_logic; -- Read the inforation in the header!
+			SELn		: in std_logic;
+			
+			BDIR		: in std_logic;
+			BC2, BC1	: in std_logic;
+
+			A9n, A8		: in std_logic;
+			DA_IN		: in std_logic_vector(7 downto 0);
+			DA_OUT		: out std_logic_vector(7 downto 0);
+			DA_EN		: out std_logic;
+			
+			IO_A_IN		: in std_logic_vector(7 downto 0);
+			IO_A_OUT	: out std_logic_vector(7 downto 0);
+			IO_A_EN		: out std_logic;
+			IO_B_IN		: in std_logic_vector(7 downto 0);
+			IO_B_OUT	: out std_logic_vector(7 downto 0);
+			IO_B_EN		: out std_logic;
+
+			OUT_A		: out std_logic; -- Analog (PWM) outputs.
+			OUT_B		: out std_logic;
+			OUT_C		: out std_logic
+		);
+	end component WF2149IP_TOP_SOC;
+
+	component WF6850IP_TOP_SOC -- ACIA.
+	  port (
+			CLK					: in std_logic;
+	        RESETn				: in std_logic;
+
+	        CS2n, CS1, CS0		: in std_logic;
+	        E		       		: in std_logic;   
+	        RWn              	: in std_logic;
+	        RS					: in std_logic;
+
+	        DATA_IN		        : in std_logic_vector(7 downto 0);   
+	        DATA_OUT	        : out std_logic_vector(7 downto 0);   
+			DATA_EN				: out std_logic;
+
+	        TXCLK				: in std_logic;
+	        RXCLK				: in std_logic;
+	        RXDATA				: in std_logic;
+	        CTSn				: in std_logic;
+	        DCDn				: in std_logic;
+	        
+	        IRQn				: out std_logic;
+	        TXDATA				: out std_logic;   
+	        RTSn				: out std_logic
+	       );                                              
+	end component WF6850IP_TOP_SOC;
+
+	component WF_SD_CARD
+		port (
+			RESETn			: in std_logic;
+			CLK				: in std_logic;
+			ACSI_A1			: in std_logic;
+			ACSI_CSn		: in std_logic;
+			ACSI_ACKn		: in std_logic;
+			ACSI_INTn		: out std_logic;
+			ACSI_DRQn		: out std_logic;
+			ACSI_D_IN		: in std_logic_vector(7 downto 0);
+			ACSI_D_OUT		: out std_logic_vector(7 downto 0);
+			ACSI_D_EN		: out std_logic;
+			MC_DO			: in std_logic;
+			MC_PIO_DMAn		: in std_logic;
+			MC_RWn			: in std_logic;
+			MC_CLR_CMD		: in std_logic;
+			MC_DONE			: out std_logic;
+			MC_GOT_CMD		: out std_logic;
+			MC_D_IN			: in std_logic_vector(7 downto 0);
+			MC_D_OUT		: out std_logic_vector(7 downto 0);
+			MC_D_EN			: out std_logic
+	      );
+	end component WF_SD_CARD;
+
+	component dcfifo0 
+		PORT (
+			aclr			: IN STD_LOGIC ;
+			data			: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			rdclk			: IN STD_LOGIC ;
+			rdreq			: IN STD_LOGIC ;
+			wrclk			: IN STD_LOGIC ;
+			wrreq			: IN STD_LOGIC ;
+			q				: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			wrusedw			: OUT STD_LOGIC_VECTOR (5 DOWNTO 0) 
+	);
+	end component dcfifo0;
+	
+	component dcfifo1
+		PORT (
+			aclr			: IN STD_LOGIC ;
+			data			: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			rdclk			: IN STD_LOGIC ;
+			rdreq			: IN STD_LOGIC ;
+			wrclk			: IN STD_LOGIC ;
+			wrreq			: IN STD_LOGIC ;
+			q				: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			rdusedw			: OUT STD_LOGIC_VECTOR (5 DOWNTO 0) 
+		);
+	end component;
+
+
+end FalconIO_SDCard_IDE_CF_PKG;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
new file mode 100644
index 0000000..4453332
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
@@ -0,0 +1,631 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WF5380 IP Core                                               ----
+----                                                              ----
+---- Description:                                                 ----
+---- This model provides an asynchronous SCSI interface compa-    ----
+---- tible to the DP5380 from National Semiconductor and others.  ----
+----                                                              ----
+---- This file is the 5380's system controller.                   ----
+----                                                              ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2009 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K9A  2009/06/20 WF
+--   Initial Release.
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF5380_CONTROL is
+	port (
+        -- System controls:
+		CLK			: in bit;
+		RESETn	    : in bit; -- System reset.
+		
+        -- System controls:
+        BSY_INn     : in bit; -- SCSI BSY_INn bit.
+        BSY_OUTn    : out bit; -- SCSI BSY_INn bit.
+        DATA_EN     : out bit; -- Enable the SCSI data lines.
+        SEL_INn     : in bit; -- SCSI SEL_INn bit.
+        ARB_EN      : in bit; -- Arbitration enable.
+        BSY_DISn    : in bit; -- BSY monitoring enable.
+		RSTn	    : in bit; -- SCSI reset.
+        
+        ARB         : out bit; -- Arbitration flag.
+        AIP         : out bit; -- Arbitration in progress flag.
+        LA          : out bit; -- Lost arbitration flag.
+
+        ACK_INn     : in bit;
+        ACK_OUTn    : out bit;
+        REQ_INn     : in bit;
+        REQ_OUTn    : out bit;
+
+        DACKn       : in bit; -- Data acknowledge.
+        READY       : out bit;
+        DRQ         : out bit; -- Data request.
+
+        TARG        : in bit; -- Target mode indicator.
+        BLK         : in bit; -- Block mode indicator.
+        PINT_EN     : in bit; -- Parity interrupt enable.
+        SPER        : in bit; -- Parity error.
+        SER_ID      : in bit; -- SER matches ODR bits.
+        RPI         : in bit; -- Reset interrupts.
+        DMA_EN      : in bit; -- DMA mode enable.
+		SDS         : in bit; -- Start DMA send, write only.
+		SDT         : in bit; -- Start DMA target receive, write only.
+		SDI         : in bit; -- Start DMA initiator receive, write only.
+        EOP_EN      : in bit; -- EOP interrupt enable.
+        EOPn        : in bit; -- End of process indicator.
+        PHSM        : in bit; -- Phase match flag.
+
+        INT         : out bit; -- Interrupt.
+        IDR_WR      : out bit; -- Write input data register during DMA.
+        ODR_WR      : out bit; -- Write output data register, during DMA.
+        CHK_PAR     : out bit; -- Check Parity during DMA operation.
+        BSY_ERR     : out bit; -- Busy monitoring error.
+        DMA_SND     : out bit; -- Indicates direction of target DMA.
+        DMA_ACTIVE  : out bit -- DMA is active.
+    );
+end entity WF5380_CONTROL;
+	
+architecture BEHAVIOUR of WF5380_CONTROL is
+type CTRL_STATES is (IDLE, WAIT_800ns, WAIT_2200ns, DMA_SEND, DMA_TARG_RCV, DMA_INIT_RCV);
+type DMA_STATES is (IDLE, DMA_STEP_1, DMA_STEP_2, DMA_STEP_3, DMA_STEP_4);
+signal CTRL_STATE       : CTRL_STATES;
+signal NEXT_CTRL_STATE  : CTRL_STATES;
+signal DMA_STATE        : DMA_STATES;
+signal NEXT_DMA_STATE   : DMA_STATES;
+signal BUS_FREE         : bit;
+signal DELAY_800ns      : boolean;
+signal DELAY_2200ns     : boolean;
+signal DMA_ACTIVE_I     : bit;
+signal EOP_In           : bit;
+begin
+    IN_BUFFER: process
+    -- This buffer shall prevent some signals against
+    -- setup hold effects and thus the state machine
+    -- against unpredictable behaviour.
+    begin
+        wait until CLK = '1' and CLK' event;
+        EOP_In <= EOPn;
+    end process IN_BUFFER;
+
+    STATE_REGISTERS: process(RESETn, CLK)
+    -- This is the controller's state machine register.
+    variable BSY_LOCK   : boolean;
+    begin
+        if RESETn = '0' then
+            CTRL_STATE <= IDLE;
+            DMA_STATE <= IDLE;
+        elsif CLK = '1' and CLK' event then
+            if RSTn = '0' then -- SCSI reset.
+                CTRL_STATE <= IDLE;
+                DMA_STATE <= IDLE;
+            else
+                CTRL_STATE <= NEXT_CTRL_STATE;
+                DMA_STATE <= NEXT_DMA_STATE;
+            end if;
+            --
+            if DMA_EN = '0' then
+                DMA_STATE <= IDLE;
+            end if;
+        end if;
+    end process STATE_REGISTERS;
+
+    CTRL_DECODER: process(CTRL_STATE, ARB_EN, BUS_FREE, DELAY_800ns, SEL_INn, DMA_ACTIVE_I, SDS, SDT, SDI)
+    -- This is the controller's state machine decoder.
+    variable BSY_LOCK   : boolean;
+    begin
+        -- Defaults.
+        DMA_SND <= '0';
+        --
+        case CTRL_STATE is
+            when IDLE =>
+                if ARB_EN = '1' and BUS_FREE = '1' then
+                    NEXT_CTRL_STATE <= WAIT_800ns;
+                else
+                    NEXT_CTRL_STATE <= IDLE;
+                end if;
+            when WAIT_800ns =>
+                if DELAY_800ns = true then
+                    NEXT_CTRL_STATE <= WAIT_2200ns;
+                else
+                    NEXT_CTRL_STATE <= WAIT_800ns;
+                end if;
+            when WAIT_2200ns =>
+                -- In this state the delay is provided by the
+                -- microprocessor and is at least 2.2us. The
+                -- delay is released by deasserting SELn.
+                if SEL_INn = '1' and SDS = '1' then
+                    NEXT_CTRL_STATE <= DMA_SEND;
+                elsif SEL_INn = '1' and SDT = '1' then
+                    NEXT_CTRL_STATE <= DMA_TARG_RCV;
+                elsif SEL_INn = '1' and SDI = '1' then
+                    NEXT_CTRL_STATE <= DMA_INIT_RCV;
+                else
+                    NEXT_CTRL_STATE <= WAIT_2200ns;
+                end if;
+            when DMA_SEND =>
+                if DMA_ACTIVE_I = '0' then
+                    NEXT_CTRL_STATE <= IDLE;
+                else
+                    NEXT_CTRL_STATE <= DMA_SEND;
+                end if;
+                --
+                DMA_SND <= '1';
+            when DMA_TARG_RCV =>
+                if DMA_ACTIVE_I = '0' then
+                    NEXT_CTRL_STATE <= IDLE;
+                else
+                    NEXT_CTRL_STATE <= DMA_TARG_RCV;
+                end if;
+            when DMA_INIT_RCV =>
+                if DMA_ACTIVE_I = '0' then
+                    NEXT_CTRL_STATE <= IDLE;
+                else
+                    NEXT_CTRL_STATE <= DMA_INIT_RCV;
+                end if;
+        end case;
+    end process CTRL_DECODER;
+
+    DMA_DECODER: process(CTRL_STATE, DMA_STATE, TARG, BLK, DACKn, REQ_INn, ACK_INn)
+    -- This is the DMA state machine decoder.
+    begin
+        -- Defaults:
+        IDR_WR <= '0';
+        ODR_WR <= '0';
+        CHK_PAR <= '0';
+        --
+        case DMA_STATE is
+            when IDLE =>
+                if CTRL_STATE = DMA_SEND then
+                    NEXT_DMA_STATE <= DMA_STEP_1;
+                elsif CTRL_STATE = DMA_INIT_RCV then
+                    NEXT_DMA_STATE <= DMA_STEP_1;
+                elsif CTRL_STATE = DMA_TARG_RCV then
+                    NEXT_DMA_STATE <= DMA_STEP_1;
+                else
+                    NEXT_DMA_STATE <= IDLE;
+                end if;
+        when DMA_STEP_1 =>
+            -- Initiator modes:
+            if CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' and DACKn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for DACKn asserted.
+                ODR_WR <= '1';
+            elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and DACKn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for DACKn asserted.
+                ODR_WR <= '1';
+            elsif CTRL_STATE = DMA_INIT_RCV and BLK = '0' and REQ_INn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for REQn asserted.
+                IDR_WR <= '1';
+            elsif CTRL_STATE = DMA_INIT_RCV and BLK = '1' and REQ_INn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for REQn asserted.
+                IDR_WR <= '1';
+            -- Target modes:
+            elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' and DACKn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for DACKn asserted.
+                ODR_WR <= '1';
+            elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and DACKn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for DACKn asserted.
+                ODR_WR <= '1';
+            elsif CTRL_STATE = DMA_TARG_RCV and BLK = '0' and ACK_INn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for ACKn asserted.
+                IDR_WR <= '1';
+            elsif CTRL_STATE = DMA_TARG_RCV and BLK = '1' and ACK_INn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_2; -- Wait for ACKn asserted.
+                IDR_WR <= '1';
+            else
+                NEXT_DMA_STATE <= DMA_STEP_1;
+            end if;
+        when DMA_STEP_2 =>
+            -- Initiator modes:
+            if CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' and DACKn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for DACKn deasserted.
+            elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and DACKn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for DACKn deasserted.
+            elsif CTRL_STATE = DMA_INIT_RCV and BLK = '0' and REQ_INn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for REQn deasserted.
+            elsif CTRL_STATE = DMA_INIT_RCV and BLK = '1' and REQ_INn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for REQn deasserted.
+            -- Target modes:
+            elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' and DACKn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for DACKn deasserted.
+            elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and DACKn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for DACKn deasserted.
+            elsif CTRL_STATE = DMA_TARG_RCV and BLK = '0' and ACK_INn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for ACKn deasserted.
+            elsif CTRL_STATE = DMA_TARG_RCV and BLK = '1' and ACK_INn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_3; -- Wait for ACKn deasserted.
+            else
+                NEXT_DMA_STATE <= DMA_STEP_2;
+            end if;
+        when DMA_STEP_3 =>
+            -- Initiator modes:
+            if CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' and REQ_INn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_4; -- Wait REQn asserted.
+            elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and REQ_INn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_4; -- Wait REQn asserted.
+            elsif CTRL_STATE = DMA_INIT_RCV and BLK = '0' and DACKn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_4; -- Wait DACKn asserted.
+                CHK_PAR <= '1';
+            elsif CTRL_STATE = DMA_INIT_RCV and BLK = '1' and DACKn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_4; -- Wait DACKn asserted.
+                CHK_PAR <= '1';
+            -- Target modes:
+            elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' and ACK_INn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_4; -- Wait ACKn asserted.
+            elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' and ACK_INn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_4; -- Wait ACKn asserted.
+            elsif CTRL_STATE = DMA_TARG_RCV and BLK = '0' and DACKn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_4; -- Wait DACKn asserted.
+                CHK_PAR <= '1';
+            elsif CTRL_STATE = DMA_TARG_RCV and BLK = '1' and DACKn = '0' then
+                NEXT_DMA_STATE <= DMA_STEP_4; -- Wait DACKn asserted.
+                CHK_PAR <= '1';
+            else
+                NEXT_DMA_STATE <= DMA_STEP_3;
+            end if;
+        when DMA_STEP_4 =>
+            -- Initiator modes:
+            if CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' and REQ_INn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_1; -- Wait REQn deasserted.
+            elsif CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and REQ_INn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_1; -- Wait REQn deasserted.
+            elsif CTRL_STATE = DMA_INIT_RCV and BLK = '0' and DACKn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_1; -- Wait DACKn deasserted.
+            elsif CTRL_STATE = DMA_INIT_RCV and BLK = '1' and DACKn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_1; -- Wait DACKn deasserted.
+            -- Target modes:
+            elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' and ACK_INn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_1; -- Wait ACKn deasserted.
+            elsif CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' and ACK_INn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_1; -- Wait ACKn deasserted.
+            elsif CTRL_STATE = DMA_TARG_RCV and BLK = '0' and DACKn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_1; -- Wait DACKn deasserted.
+            elsif CTRL_STATE = DMA_TARG_RCV and BLK = '1' and DACKn = '1' then
+                NEXT_DMA_STATE <= DMA_STEP_1; -- Wait DACKn deasserted.
+            else
+                NEXT_DMA_STATE <= DMA_STEP_4;
+            end if;
+        end case;
+    end process DMA_DECODER;
+
+    P_REQn: process(DMA_STATE, CTRL_STATE, TARG, BLK)
+    -- This logic controls the REQn output in target mode.
+    begin
+        if DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '0' then
+            REQ_OUTn <= '0';
+        elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '1' then
+            REQ_OUTn <= '0';
+        elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' then
+            REQ_OUTn <= '0';
+        elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' then
+            REQ_OUTn <= '0';
+        else
+            REQ_OUTn <= '1';
+        end if;
+    end process P_REQn;
+    
+    P_ACKn: process(DMA_STATE, CTRL_STATE, TARG, BLK)
+    -- This logic controls the ACKn output in initiator mode.
+    begin
+        if DMA_STATE = DMA_STEP_2 and CTRL_STATE = DMA_INIT_RCV and BLK = '0' then
+            ACK_OUTn <= '0';
+        elsif DMA_STATE = DMA_STEP_2 and CTRL_STATE = DMA_INIT_RCV and BLK = '1' then
+            ACK_OUTn <= '0';
+        elsif DMA_STATE = DMA_STEP_4 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' then
+            ACK_OUTn <= '0';
+        elsif DMA_STATE = DMA_STEP_4 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' then
+            ACK_OUTn <= '0';
+        else
+            ACK_OUTn <= '1';
+        end if;
+    end process P_ACKn;
+
+    P_READY: process(DMA_STATE, CTRL_STATE, TARG, BLK)
+    -- This logic controls the READY output in initiator and target block mode.
+    begin
+        if DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' then
+            READY <= '1';
+        elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '1' then
+            READY <= '1';
+        elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' then
+            READY <= '1';
+        elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_INIT_RCV and BLK = '1' then
+            READY <= '1';
+        else
+            READY <= '0';
+        end if;
+    end process P_READY;
+    
+    P_DRQ: process(RESETn, CLK)
+    -- This flip flop controls the DRQ flag during all initiator and all target modes
+    -- for both block mode and non block mode operation.
+    variable LOCK   : boolean;
+    begin
+        if RESETn = '0' then
+            DRQ <= '0';
+            LOCK := false;
+        elsif CLK = '1' and CLK' event then
+            -- Initiator modes:
+            if DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '0' then
+                DRQ <= '1';
+            elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_SEND and TARG = '0' and BLK = '1' and LOCK = false then
+                DRQ <= '1';
+                LOCK := true;
+            elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_INIT_RCV and BLK = '0' then
+                DRQ <= '1';
+            elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_INIT_RCV and BLK = '1' then
+                DRQ <= '1';
+                LOCK := true;
+            -- Target modes:
+            elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '0' then
+                DRQ <= '1';
+            elsif DMA_STATE = DMA_STEP_3 and CTRL_STATE = DMA_SEND and TARG = '1' and BLK = '1' then
+                DRQ <= '1';
+                LOCK := true;
+            elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '0' then
+                DRQ <= '1';
+            elsif DMA_STATE = DMA_STEP_1 and CTRL_STATE = DMA_TARG_RCV and BLK = '1' then
+                DRQ <= '1';
+                LOCK := true;
+            elsif DACKn = '0' and LOCK = false then
+                DRQ <= '0';
+            elsif EOPn = '0' and DACKn = '0' then
+                DRQ <= '0';
+                LOCK := false;
+            end if;
+        end if;
+    end process P_DRQ;
+
+    P_BUSFREE: process(RESETn, CLK)
+    -- This is the logic for the bus free signal.
+    -- A bus free is valid if the BSY_INn signal is
+    -- at least 437.5ns inactive ans SEL_INn is inactive.
+    -- The delay are 7 clock cycles of 16MHz.
+    variable TMP    : std_logic_vector(2 downto 0);
+    begin
+        if RESETn = '0' then
+            BUS_FREE <= '0';
+            TMP := "000";
+        elsif CLK = '1' and CLK' event then
+            if BSY_INn = '1' and TMP < x"111" then
+                TMP := TMP + '1';
+            elsif BSY_INn = '0' then
+                TMP := "000";
+            end if;
+            --
+            if RSTn = '0' then -- SCSI reset.
+                BUS_FREE <= '0';
+            elsif SEL_INn = '1' and TMP = "111" then
+                BUS_FREE <= '1';
+            else
+                BUS_FREE <= '0';
+            end if;
+        end if;
+    end process P_BUSFREE;
+
+    DELAY_800: process(RESETn, CLK)
+    -- This is the delay of 812.5ns.
+    -- It is derived from 13 16MHz clock cycles.
+    variable TMP    : std_logic_vector(3 downto 0);
+    begin
+        if RESETn = '0' then
+            DELAY_800ns <= false;
+            TMP := x"0";
+        elsif CLK = '1' and CLK' event then
+            if CTRL_STATE /= WAIT_800ns then
+                TMP := x"0";
+            elsif TMP <= x"D" then
+                TMP := TMP + '1';
+            end if;
+            --
+            if TMP = x"D" then
+                DELAY_800ns <= true;
+            else
+                DELAY_800ns <= false;
+            end if;
+        end if;
+    end process DELAY_800;
+
+    P_ARB: process(RESETn, CLK)
+    -- This flip flop controls the ARB flag read back
+    -- by the microcontroller.
+    begin
+        if RESETn = '0' then
+            ARB <= '0';
+        elsif CLK = '1' and CLK' event then
+            if CTRL_STATE /= WAIT_800ns and NEXT_CTRL_STATE = WAIT_800ns then
+                ARB <= '1';
+            elsif ARB_EN = '0' then
+                ARB <= '0';
+            end if;
+        end if;
+    end process P_ARB;
+
+    P_AIP: process(RESETn, CLK)
+    -- This flip flop controls the AIP flag read back
+    -- by the microcontroller.
+    begin
+        if RESETn = '0' then
+            AIP <= '0';
+        elsif CLK = '1' and CLK' event then
+            if CTRL_STATE = WAIT_800ns and NEXT_CTRL_STATE /= WAIT_800ns then
+                AIP <= '1';
+            elsif ARB_EN = '0' then
+                AIP <= '0';
+            end if;
+        end if;
+    end process P_AIP;
+    
+    P_BSY: process
+    -- This flip flop controls the BSYn output
+    -- to the SCSI bus.
+    begin
+        wait until CLK = '1' and CLK' event;
+        if RESETn = '0' then
+            BSY_OUTn <= '1';
+        elsif CTRL_STATE = WAIT_800ns and NEXT_CTRL_STATE /= WAIT_800ns then
+            BSY_OUTn <= '0';
+        elsif ARB_EN = '0' then
+            BSY_OUTn <= '1';
+        end if;
+    end process P_BSY;
+    
+    P_DATA_EN: process(RESETn, CLK)
+    -- This flip flop controls the data enable
+    -- of the SCSI bus.
+    begin
+        if RESETn = '0' then
+            DATA_EN <= '0';
+        elsif CLK = '1' and CLK' event then
+            if CTRL_STATE = WAIT_800ns and NEXT_CTRL_STATE /= WAIT_800ns then
+                DATA_EN <= '1';
+            elsif ARB_EN = '0' then
+                DATA_EN <= '0';
+            end if;
+        end if;
+    end process P_DATA_EN;
+    
+    P_LA: process(RESETn, CLK)
+    -- This flip flop controls the LA
+    -- (lost arbitration) flag.
+    begin
+        if RESETn = '0' then
+            LA <= '0';
+        elsif CLK = '1' and CLK' event then
+            if (CTRL_STATE = WAIT_800ns or CTRL_STATE = WAIT_2200ns) and SEL_INn = '0' then
+                LA <= '1';
+            elsif ARB_EN = '0' then
+                LA <= '0';
+            end if;
+        end if;
+    end process P_LA;
+
+    P_DMA_ACTIVE: process(RESETn, CLK, DMA_ACTIVE_I)
+    -- This is the Flip Flop indicating if there is DMA
+    -- operation.
+    begin
+        if RESETn = '0' then
+            DMA_ACTIVE_I <= '0';
+        elsif CLK = '1' and CLK' event then
+            if DMA_EN = '1' and SDS = '1' then
+                DMA_ACTIVE_I <= '1'; -- Start DMA send.
+            elsif DMA_EN = '1' and SDT = '1' then
+                DMA_ACTIVE_I <= '1'; -- Start DMA target receive.
+            elsif DMA_EN = '1' and SDI = '1' then
+                DMA_ACTIVE_I <= '1'; -- Start DMA initiator receive.
+            elsif DMA_EN = '0' then
+                DMA_ACTIVE_I <= '0'; -- Halt DMA via DMA flag in MR2.
+            elsif EOP_In = '0' then
+                DMA_ACTIVE_I <= '0'; -- Halt DMA via EOPn.
+            elsif PHSM = '0' then
+                DMA_ACTIVE_I <= '0'; -- Halt DMA via phase mismatch.
+            end if;
+        end if;
+        --
+        DMA_ACTIVE <= DMA_ACTIVE_I;
+    end process P_DMA_ACTIVE;
+
+    INTERRUPTS: process(RESETn, CLK)
+    -- This is the logic for all DP5380's interrupt sources.
+    -- A busy interrupt occurs if the BSY_INn signal is at 
+    -- least 437.5ns inactive. The delay are 7 clock cycles
+    -- of 16MHz. This logic also provides the respective 
+    -- error flags for the BSR.
+    variable TMP    : std_logic_vector(2 downto 0);
+    begin
+        if RESETn = '0' then
+            INT <= '0';
+            BSY_ERR <= '0';
+            TMP := "000";
+        elsif CLK = '1' and CLK' event then
+            if SPER = '1' and PINT_EN = '1' then
+                INT <= '1'; -- Parity interrupt.
+            elsif RPI = '0' then -- Reset interrupts.
+                INT <= '0';
+            end if;
+            --
+            if EOP_In = '0' and CTRL_STATE = DMA_SEND then
+                BSY_ERR <= '1'; -- End of DMA error.
+            elsif EOP_In = '0' and CTRL_STATE = DMA_TARG_RCV then
+                BSY_ERR <= '1'; -- End of DMA error.
+            elsif EOP_In = '0' and CTRL_STATE = DMA_INIT_RCV then
+                BSY_ERR <= '1'; -- End of DMA error.
+            elsif DMA_EN = '0' then -- Reset error.
+                INT <= '0';
+            end if;
+            --
+            if EOP_EN = '1' and EOP_In = '0' and CTRL_STATE = DMA_SEND then
+                INT <= '1'; -- End of DMA interrupt.
+            elsif EOP_EN = '1' and EOP_In = '0' and CTRL_STATE = DMA_TARG_RCV then
+                INT <= '1'; -- End of DMA interrupt.
+            elsif EOP_EN = '1' and EOP_In = '0' and CTRL_STATE = DMA_INIT_RCV then
+                INT <= '1'; -- End of DMA interrupt.
+            elsif DMA_EN = '0' then -- Reset interrupt.
+                INT <= '0';
+            end if;
+
+            --
+            if PHSM = '0' then
+                INT <= '1'; -- Phase mismatch interrupt.
+            elsif DMA_EN = '0' then -- Reset interrupts.
+                INT <= '0';
+            end if;
+            --
+            if SEL_INn = '0' and BSY_INn = '1' and SER_ID = '1' then
+                INT <= '1'; -- (Re)Selection interrupt.
+            elsif RPI = '1' then -- Reset interrupts.
+                INT <= '0';
+            end if;
+            --
+            if BSY_INn = '1' and TMP < x"111" then
+                TMP := TMP + '1'; -- Bus settle delay.
+            elsif BSY_INn = '0' then
+                TMP := "000";
+            end if;
+            --
+            if BSY_DISn = '1' and BSY_INn = '1' and TMP = x"111" then
+                INT <= '1'; -- Busy monitoring interrupt.
+                BSY_ERR <= '1';
+            elsif RPI = '1' then -- Reset interrupts.
+                INT <= '0';
+                BSY_ERR <= '0';
+            end if;
+            --
+        end if;
+    end process INTERRUPTS;
+end BEHAVIOUR;
\ No newline at end of file
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
new file mode 100644
index 0000000..57cf305
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
@@ -0,0 +1,139 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WF5380 IP Core                                               ----
+----                                                              ----
+---- Description:                                                 ----
+---- This model provides an asynchronous SCSI interface compa-    ----
+---- tible to the DP5380 from National Semiconductor and others.  ----
+----                                                              ----
+---- This file is the package file of the ip core.                ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2009 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K9A  2009/06/20 WF
+--   Initial Release.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package WF5380_PKG is
+    component WF5380_REGISTERS
+        port (
+            CLK			: in bit;
+            RESETn	    : in bit;
+            ADR			: in bit_vector(2 downto 0);
+            DATA_IN		: in bit_vector(7 downto 0);
+            DATA_OUT	: out bit_vector(7 downto 0);
+            DATA_EN		: out bit;
+            CSn			: in bit;
+            RDn		    : in bit;
+            WRn	        : in bit;
+            RSTn	    : in bit;
+            RST         : out bit;
+            ARB_EN      : out bit;
+            DMA_ACTIVE  : in bit;
+            DMA_EN      : out bit;
+            BSY_DISn    : out bit;
+            EOP_EN      : out bit;
+            PINT_EN     : out bit;
+            SPER        : out bit;
+            TARG        : out bit;
+            BLK         : out bit;
+            DMA_DIS     : in bit;
+            IDR_WR      : in bit;
+            ODR_WR      : in bit;
+            CHK_PAR     : in bit;
+            AIP         : in bit;
+            ARB         : in bit;
+            LA          : in bit;
+            CSD         : in bit_vector(7 downto 0);
+            CSB         : in bit_vector(7 downto 0);
+            BSR         : in bit_vector(7 downto 0);
+            ODR_OUT     : out bit_vector(7 downto 0);
+            ICR_OUT     : out bit_vector(7 downto 0);
+            TCR_OUT     : out bit_vector(3 downto 0);
+            SER_OUT     : out bit_vector(7 downto 0);
+            SDS         : out bit;
+            SDT         : out bit;
+            SDI         : out bit;
+            RPI         : out bit
+        );
+    end component;
+
+    component WF5380_CONTROL
+        port (
+            CLK			: in bit;
+            RESETn	    : in bit;
+            BSY_INn     : in bit;
+            BSY_OUTn    : out bit;
+            DATA_EN     : out bit;
+            SEL_INn     : in bit;
+            ARB_EN      : in bit;
+            BSY_DISn    : in bit;
+            RSTn	    : in bit;
+            ARB         : out bit;
+            AIP         : out bit;
+            LA          : out bit;
+            ACK_INn     : in bit;
+            ACK_OUTn    : out bit;
+            REQ_INn     : in bit;
+            REQ_OUTn    : out bit;
+            DACKn       : in bit;
+            READY       : out bit;
+            DRQ         : out bit;
+            TARG        : in bit;
+            BLK         : in bit;
+            PINT_EN     : in bit;
+            SPER        : in bit;
+            SER_ID      : in bit;
+            RPI         : in bit;
+            DMA_EN      : in bit;
+            SDS         : in bit;
+            SDT         : in bit;
+            SDI         : in bit;
+            EOP_EN      : in bit;
+            EOPn        : in bit;
+            PHSM        : in bit;
+            INT         : out bit;
+            IDR_WR      : out bit;
+            ODR_WR      : out bit;
+            CHK_PAR     : out bit;
+            BSY_ERR     : out bit;
+            DMA_SND     : out bit;
+            DMA_ACTIVE  : out bit
+        );
+    end component;
+end WF5380_PKG;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
new file mode 100644
index 0000000..2c21c12
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
@@ -0,0 +1,265 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WF5380 IP Core                                               ----
+----                                                              ----
+---- Description:                                                 ----
+---- This model provides an asynchronous SCSI interface compa-    ----
+---- tible to the DP5380 from National Semiconductor and others.  ----
+----                                                              ----
+---- This file is the 5380's register model.                      ----
+----                                                              ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Register description (for more information see the DP5380    ----
+---- data sheet:                                                  ----
+----   ODR (address 0) Output data register, write only.          ----
+----   CSD (address 0) Current SCSI data, read only.              ----
+----   ICR (address 1) Initiator command register, read/write.    ----
+----   MR2 (address 2) Mode register 2, read/write.               ----
+----   TCR (address 3) Target command register, read/write.       ----
+----   SER (address 4) Select enable register, write only.        ----
+----   CSB (address 4) Current SCSI bus status, read only.        ----
+----   BSR (address 5) Start DMA send, write only.                ----
+----   SDS (address 5) Bus and status, read only.                 ----
+----   SDT (address 6) Start DMA target receive, write only.      ----
+----   IDR (address 6) Input data register, read only.            ----
+----   SDI (address 7) Start DMA initiator recive, write only.    ----
+----   RPI (address 7) Reset parity / interrupts, read only.      ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2009 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K9A  2009/06/20 WF
+--   Initial Release.
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF5380_REGISTERS is
+	port (
+        -- System controls:
+		CLK			: in bit;
+		RESETn	    : in bit; -- System reset.
+		
+		-- Address and data:
+		ADR			: in bit_vector(2 downto 0);
+		DATA_IN		: in bit_vector(7 downto 0);
+		DATA_OUT	: out bit_vector(7 downto 0);
+		DATA_EN		: out bit;
+
+		-- Bus and DMA controls:
+		CSn			: in bit;
+		RDn		    : in bit;
+		WRn	        : in bit;
+
+        -- Core controls:
+		RSTn	    : in bit; -- SCSI reset.
+		RST         : out bit; -- Programmed SCSI reset.
+        ARB_EN      : out bit; -- Arbitration enable.
+        DMA_ACTIVE  : in bit; -- DMA is running.
+        DMA_EN      : out bit; -- DMA mode enable.
+        BSY_DISn    : out bit; -- BSY monitoring enable.
+        EOP_EN      : out bit; -- EOP interrupt enable.
+        PINT_EN     : out bit; -- Parity interrupt enable.
+        SPER        : out bit; -- Parity error.
+        TARG        : out bit; -- Target mode.
+        BLK         : out bit; -- Block DMA mode.
+        DMA_DIS     : in bit; -- Reset the DMA_EN by this signal.
+        IDR_WR      : in bit; -- Write input data register during DMA.
+        ODR_WR      : in bit; -- Write output data register, during DMA.
+        CHK_PAR     : in bit; -- Check Parity during DMA operation.
+        AIP         : in bit; -- Arbitration in progress.
+        ARB         : in bit; -- Arbitration.
+        LA          : in bit; -- Lost arbitration.
+
+        CSD         : in bit_vector(7 downto 0); -- SCSI data.
+        CSB         : in bit_vector(7 downto 0); -- Current SCSI bus status.
+        BSR         : in bit_vector(7 downto 0); -- Bus and status.
+
+        ODR_OUT     : out bit_vector(7 downto 0); -- This is the ODR register.
+        ICR_OUT     : out bit_vector(7 downto 0); -- This is the ICR register.
+        TCR_OUT     : out bit_vector(3 downto 0); -- This is the TCR register.
+        SER_OUT     : out bit_vector(7 downto 0); -- This is the SER register.
+        
+		SDS         : out bit; -- Start DMA send, write only.
+		SDT         : out bit; -- Start DMA target receive, write only.
+		SDI         : out bit; -- Start DMA initiator receive, write only.
+		RPI         : out bit
+    );
+end entity WF5380_REGISTERS;
+	
+architecture BEHAVIOUR of WF5380_REGISTERS is
+signal ICR  : bit_vector(7 downto 0); -- Initiator command register, read/write.
+signal IDR  : bit_vector(7 downto 0); -- Input data register.
+signal MR2  : bit_vector(7 downto 0); -- Mode register 2, read/write.
+signal ODR  : bit_vector(7 downto 0); -- Output data register, write only.
+signal SER  : bit_vector(7 downto 0); -- Select enable register, write only.
+signal TCR  : bit_vector(3 downto 0); -- Target command register, read/write.
+begin
+    REGISTERS: process(RESETn, CLK)
+    -- This process reflects all registers in the 5380.
+    variable BSY_LOCK   : boolean;
+    begin
+        if RESETn = '0' then
+            ODR <= (others => '0');
+            ICR <= (others => '0');
+            MR2 <= (others => '0');
+            TCR <= (others => '0');
+            SER <= (others => '0');
+            BSY_LOCK  := false;
+        elsif CLK = '1' and CLK' event then
+            if RSTn = '0' then -- SCSI reset.
+                ODR <= (others => '0');
+                ICR(6 downto 0) <= (others => '0');
+                MR2(7) <= '0';
+                MR2(5 downto 0) <= (others => '0');
+                TCR <= (others => '0');
+                SER <= (others => '0');
+                BSY_LOCK  := false;
+            elsif ADR = "000" and CSn = '0' and WRn = '0' then
+                ODR <= DATA_IN;
+            elsif ADR = "001" and CSn = '0' and WRn = '0' then
+                ICR <= DATA_IN;
+            elsif ADR = "010" and CSn = '0' and WRn = '0' then
+                MR2 <= DATA_IN;
+            elsif ADR = "011" and CSn = '0' and WRn = '0' then
+                TCR <= DATA_IN(3 downto 0);
+            elsif ADR = "100" and CSn = '0' and WRn = '0' then
+                SER <= DATA_IN;
+            end if;
+            --
+            if ODR_WR = '1' then
+                ODR <= DATA_IN;
+            end if;
+            --
+            -- This reset function is edge triggered on the 'Monitor Busy'
+            -- MR2(2).
+            if MR2(2) = '1' and BSY_LOCK = false then
+                ICR(5 downto 0) <= "000000";
+                BSY_LOCK := true;
+            elsif MR2(2) = '0' then
+                BSY_LOCK := false;
+            end if;
+            --
+            if DMA_DIS = '1' then
+                MR2(1) <= '0';
+            end if;
+        end if;
+    end process REGISTERS;
+    
+    IDR_REGISTER: process(RESETn, CLK)
+    begin
+        if RESETn = '0' then
+            IDR <= x"00";
+        elsif CLK = '1' and CLK' event then
+            if RSTn = '0' or ICR(7) = '1' then
+                IDR <= x"00"; -- SCSI reset.
+            elsif IDR_WR = '1' then
+                IDR <= CSD;
+            end if;
+        end if;
+    end process IDR_REGISTER;
+    
+    PARITY: process(RESETn, CLK)
+    -- This is the parity generating logic with it's related
+    -- error generation.
+	variable PAR_VAR : bit;
+	variable LOCK : boolean;
+    begin
+        if RESETn = '0' then
+            SPER <= '0';
+            LOCK := false;
+        elsif CLK = '1' and CLK' event then
+            -- Parity checked during 'Read from CSD' 
+            -- (registered I/O and selection/reselection):
+            if ADR = "000" and CSn = '0' and RDn = '0' and LOCK = false then
+                for i in 1 to 7 loop
+                    PAR_VAR := CSD(i) xor CSD(i-1);
+                end loop;
+                SPER <= not PAR_VAR;
+                LOCK := true;
+            end if;
+            --
+            -- Parity checking during DMA operation:
+            if DMA_ACTIVE = '1' and CHK_PAR = '1' then
+                for i in 1 to 7 loop
+                    PAR_VAR := IDR(i) xor IDR(i-1);
+                end loop;
+                SPER <= not PAR_VAR;
+                LOCK := true;
+            end if;
+            --
+            -- Reset parity flag:
+            if MR2(5) <= '0' then -- MR2(5) = PCHK (disabled).
+                SPER <= '0';
+            elsif ADR = "111" and CSn = '0' and RDn = '0' then -- Reset parity/interrupts.
+                SPER <= '0';
+                LOCK := false;
+            end if;
+        end if;
+    end process PARITY;
+
+    DATA_EN <= '1' when ADR < "101" and CSn = '0' and WRn = '0' else '0';
+
+    SDS <= '1' when ADR = "101" and CSn = '0' and WRn = '0' else '0';
+    SDT <= '1' when ADR = "110" and CSn = '0' and WRn = '0' else '0';
+    SDI <= '1' when ADR = "111" and CSn = '0' and WRn = '0' else '0';
+    
+    ICR_OUT <= ICR;
+    TCR_OUT <= TCR;
+    SER_OUT <= SER;
+    ODR_OUT <= ODR;
+    
+    ARB_EN  <= MR2(0);
+    DMA_EN  <= MR2(1);
+    BSY_DISn  <= MR2(2);
+    EOP_EN  <= MR2(3);
+    PINT_EN <= MR2(4);
+    TARG    <= MR2(6);
+    BLK     <= MR2(7);
+    
+    RST     <= ICR(7);
+       
+    -- Readback, unused bit positions are read back zero.
+    DATA_OUT <= CSD when ADR = "000" and CSn = '0' and RDn = '0' else -- Current SCSI data.
+                ICR(7) & AIP & LA & ICR(4 downto 0) when ADR = "001" and CSn = '0' and RDn = '0' else
+                MR2 when ADR = "010" and CSn = '0' and RDn = '0' else
+                x"0" & TCR when ADR = "011" and CSn = '0' and RDn = '0' else
+                CSB when ADR = "100" and CSn = '0' and RDn = '0' else -- Current SCSI bus status.
+                BSR when ADR = "101" and CSn = '0' and RDn = '0' else -- Bus and status.
+                IDR when ADR = "110" and CSn = '0' and RDn = '0' else x"00"; -- Input data register.
+
+    RPI <= '1' when ADR = "111" and CSn = '0' and RDn = '0' else '0'; -- Reset parity/interrupts.
+end BEHAVIOUR;
\ No newline at end of file
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
new file mode 100644
index 0000000..abc0400
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
@@ -0,0 +1,300 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WF5380 IP Core                                               ----
+----                                                              ----
+---- Description:                                                 ----
+---- This model provides an asynchronous SCSI interface compa-    ----
+---- tible to the DP5380 from National Semiconductor and others.  ----
+----                                                              ----
+---- Some remarks to the required input clock:                    ----
+---- This core is provided for a 16MHz input clock. To use other  ----
+---- frequencies, it is necessary to modify the following proces- ----
+---- ses in the control file section:                             ----
+---- P_BUSFREE, DELAY_800, INTERRUPTS.                            ----
+----                                                              ----
+---- This file is the top level file without tree state buses for ----
+---- use in 'systems on chip' designs.                            ----
+----                                                              ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2009 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K9A  2009/06/20 WF
+--   Initial Release.
+-- 
+
+library work;
+use work.wf5380_pkg.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF5380_TOP_SOC is
+	port (
+        -- System controls:
+		CLK			: in bit; -- Use a 16MHz Clock.
+		RESETn	    : in bit;
+		
+		-- Address and data:
+		ADR			: in bit_vector(2 downto 0);
+		DATA_IN		: in bit_vector(7 downto 0);
+		DATA_OUT	: out bit_vector(7 downto 0);
+		DATA_EN		: out bit;
+
+		-- Bus and DMA controls:
+		CSn			: in bit;
+		RDn		    : in bit;
+		WRn	        : in bit;
+		EOPn        : in bit;
+		DACKn	    : in bit;
+		DRQ		    : out bit;
+		INT		    : out bit;
+		READY       : out bit;
+		
+		-- SCSI bus:
+		DB_INn		: in bit_vector(7 downto 0);
+		DB_OUTn		: out bit_vector(7 downto 0);
+		DB_EN       : out bit;
+		DBP_INn		: in bit;
+		DBP_OUTn	: out bit;
+		DBP_EN      : out bit;
+		RST_INn     : in bit;
+		RST_OUTn    : out bit;
+		RST_EN      : out bit;
+		BSY_INn     : in bit;
+		BSY_OUTn    : out bit;
+		BSY_EN      : out bit;
+		SEL_INn     : in bit;
+		SEL_OUTn    : out bit;
+		SEL_EN      : out bit;
+		ACK_INn     : in bit;
+		ACK_OUTn    : out bit;
+		ACK_EN      : out bit;
+		ATN_INn     : in bit;
+		ATN_OUTn    : out bit;
+		ATN_EN      : out bit;
+		REQ_INn     : in bit;
+		REQ_OUTn    : out bit;
+		REQ_EN      : out bit;
+		IOn_IN      : in bit;
+		IOn_OUT     : out bit;
+		IO_EN       : out bit;
+		CDn_IN      : in bit;
+		CDn_OUT     : out bit;
+		CD_EN       : out bit;
+		MSG_INn     : in bit;
+		MSG_OUTn    : out bit;
+		MSG_EN      : out bit
+	);
+end entity WF5380_TOP_SOC;
+	
+architecture STRUCTURE of WF5380_TOP_SOC is
+signal ACK_OUT_CTRLn    : bit;
+signal AIP              : bit;
+signal ARB              : bit;
+signal ARB_EN           : bit;
+signal BLK              : bit;
+signal BSR              : bit_vector(7 downto 0);
+signal BSY_DISn         : bit;
+signal BSY_ERR          : bit;
+signal BSY_OUT_CTRLn    : bit;
+signal CHK_PAR          : bit;
+signal CSD              : bit_vector(7 downto 0);
+signal CSB              : bit_vector(7 downto 0);
+signal DATA_EN_CTRL     : bit;
+signal DB_EN_I          : bit;
+signal DMA_ACTIVE       : bit;
+signal DMA_EN           : bit;
+signal DMA_DIS          : bit;
+signal DMA_SND          : bit;
+signal DRQ_I            : bit;
+signal EDMA             : bit;
+signal EOP_EN           : bit;
+signal ICR              : bit_vector(7 downto 0);
+signal IDR_WR           : bit;
+signal INT_I            : bit;
+signal LA               : bit;
+signal ODR              : bit_vector(7 downto 0);
+signal ODR_WR           : bit;
+signal PCHK             : bit;
+signal PHSM             : bit;
+signal PINT_EN          : bit;
+signal REQ_OUT_CTRLn    : bit;
+signal RPI              : bit;
+signal RST              : bit;
+signal SDI              : bit;
+signal SDS              : bit;
+signal SDT              : bit;
+signal SER              : bit_vector(7 downto 0);
+signal SER_ID           : bit;
+signal SPER             : bit;
+signal TARG             : bit;
+signal TCR              : bit_vector(3 downto 0);
+begin
+    EDMA <= '1' when EOPn = '0' and DACKn = '0' and RDn = '0' else
+            '1' when EOPn = '0' and DACKn = '0' and WRn = '0' else '0';
+
+    PHSM <= '1' when DMA_ACTIVE = '0' else -- Always true, if there is no DMA.
+            '1' when DMA_ACTIVE = '1' and REQ_INn = '0' and CDn_In = TCR(1) and IOn_IN = TCR(0) and MSG_INn = TCR(2) else '0'; -- Phasematch.
+
+    DMA_DIS <= '1' when DMA_ACTIVE = '1' and BSY_INn = '1' else '0';
+
+    SER_ID <= '1' when SER /= x"00" and SER = not CSD else '0';
+
+    DRQ <= DRQ_I;
+    INT <= INT_I;
+
+    -- Pay attention: the SCSI bus is driven with inverted signals.
+    ACK_OUTn <= ACK_OUT_CTRLn when DMA_ACTIVE = '1' else not ICR(4); -- Valid in initiator mode.
+    REQ_OUTn <= REQ_OUT_CTRLn when DMA_ACTIVE = '1' else not TCR(3);  -- Valid in Target mode.
+    BSY_OUTn <= '0' when BSY_OUT_CTRLn = '0' and TARG = '0' else -- Valid in initiator mode.
+                '0' when ICR(3) = '1' else '1';
+    ATN_OUTn <= not ICR(1); -- Valid in initiator mode.
+    SEL_OUTn <= not ICR(2); -- Valid in initiator mode.
+    IOn_OUT <= not TCR(0);  -- Valid in Target mode.
+    CDn_OUT <= not TCR(1);  -- Valid in Target mode.
+    MSG_OUTn <= not TCR(2);  -- Valid in Target mode.
+    RST_OUTn <= not RST;
+
+    DB_OUTn <= not ODR;
+    DBP_OUTn <= not SPER; 
+
+    CSD <= not DB_INn;
+    CSB <= not RST_INn & not BSY_INn & not REQ_INn & not MSG_INn & not CDn_IN & not IOn_IN & not SEL_INn & not DBP_INn;
+    BSR <= EDMA & DRQ_I & SPER & INT_I & PHSM & BSY_ERR & not ATN_INn & not ACK_INn;
+
+    -- Hi impedance control:
+    ATN_EN <= '1' when TARG = '0' else '0'; -- Initiator mode.
+    SEL_EN <= '1' when TARG = '0' else '0'; -- Initiator mode.
+    BSY_EN <= '1' when TARG = '0' else '0'; -- Initiator mode.
+    ACK_EN <= '1' when TARG = '0' else '0'; -- Initiator mode.
+    IO_EN <= '1' when TARG = '1' else '0'; -- Target mode.
+    CD_EN <= '1' when TARG = '1' else '0'; -- Target mode.
+    MSG_EN <= '1' when TARG = '1' else '0'; -- Target mode.
+    REQ_EN <= '1' when TARG = '1' else '0'; -- Target mode.
+    RST_EN <= '1' when RST = '1' else '0'; -- Open drain control.
+    
+    -- Data enables:
+    DB_EN_I <= '1' when DATA_EN_CTRL = '1' else -- During Arbitration.
+               '1' when ICR(0) = '1' and TARG = '1' and DMA_SND = '1' else -- Target 'Send' mode.
+               '1' when ICR(0) = '1' and TARG = '0' and IOn_IN = '0' and PHSM = '1' else 
+               '1' when ICR(6) = '1' else '0'; -- Test mode enable.
+
+    DB_EN <= DB_EN_I;
+    DBP_EN <= DB_EN_I;
+
+    I_REGISTERS: WF5380_REGISTERS
+        port map(
+            CLK			=> CLK,
+            RESETn	    => RESETn,
+            ADR			=> ADR,
+            DATA_IN		=> DATA_IN,
+            DATA_OUT	=> DATA_OUT,
+            DATA_EN		=> DATA_EN,
+            CSn			=> CSn,
+            RDn		    => RDn,
+            WRn	        => WRn,
+            RSTn	    => RST_INn,
+            RST         => RST,
+            ARB_EN      => ARB_EN,
+            DMA_ACTIVE  => DMA_ACTIVE,
+            DMA_EN      => DMA_EN,
+            BSY_DISn    => BSY_DISn,
+            EOP_EN      => EOP_EN,
+            PINT_EN     => PINT_EN,
+            SPER        => SPER,
+            TARG        => TARG,
+            BLK         => BLK,
+            DMA_DIS     => DMA_DIS,
+            IDR_WR      => IDR_WR,
+            ODR_WR      => ODR_WR,
+            CHK_PAR     => CHK_PAR,
+            AIP         => AIP,
+            ARB         => ARB,
+            LA          => LA,
+            CSD         => CSD,
+            CSB         => CSB,
+            BSR         => BSR,
+            ODR_OUT     => ODR,
+            ICR_OUT     => ICR,
+            TCR_OUT     => TCR,
+            SER_OUT     => SER,
+            SDS         => SDS,
+            SDT         => SDT,
+            SDI         => SDI,
+            RPI         => RPI
+        );
+
+    I_CONTROL: WF5380_CONTROL
+        port map(
+            CLK			=> CLK,
+            RESETn	    => RESETn,
+            BSY_INn     => BSY_INn,
+            BSY_OUTn    => BSY_OUT_CTRLn,
+            DATA_EN     => DATA_EN_CTRL,
+            SEL_INn     => SEL_INn,
+            ARB_EN      => ARB_EN,
+            BSY_DISn    => BSY_DISn,
+            RSTn	    => RST_INn,
+            ARB         => ARB,
+            AIP         => AIP,
+            LA          => LA,
+            ACK_INn     => ACK_INn,
+            ACK_OUTn    => ACK_OUT_CTRLn,
+            REQ_INn     => REQ_INn,
+            REQ_OUTn    => REQ_OUT_CTRLn,
+            DACKn       => DACKn,
+            READY       => READY,
+            DRQ         => DRQ_I,
+            TARG        => TARG,
+            BLK         => BLK,
+            PINT_EN     => PINT_EN,
+            SPER        => SPER,
+            SER_ID      => SER_ID,
+            RPI         => RPI,
+            DMA_EN      => DMA_EN,
+            SDS         => SDS,
+            SDT         => SDT,
+            SDI         => SDI,
+            EOP_EN      => EOP_EN,
+            EOPn        => EOPn,
+            PHSM        => PHSM,
+            INT         => INT_I,
+            IDR_WR      => IDR_WR,
+            ODR_WR      => ODR_WR,
+            CHK_PAR     => CHK_PAR,
+            BSY_ERR     => BSY_ERR,
+            DMA_SND     => DMA_SND,
+            DMA_ACTIVE  => DMA_ACTIVE
+        );
+end STRUCTURE;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
new file mode 100644
index 0000000..bfb31fb
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
@@ -0,0 +1,275 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WF5380 IP Core                                               ----
+----                                                              ----
+---- Description:                                                 ----
+---- This model provides an asynchronous SCSI interface compa-    ----
+---- tible to the DP5380 from National Semiconductor and others.  ----
+----                                                              ----
+---- This file is the top level file with tree state buses.       ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2009 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K9A  2009/06/20 WF
+--   Initial Release.
+-- 
+
+library work;
+use work.wf5380_pkg.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF5380_TOP is
+	port (
+        -- System controls:
+		CLK			: in bit;
+		RESETn	    : in bit;
+		
+		-- Address and data:
+		ADR			: in std_logic_vector(2 downto 0);
+		DATA		: inout std_logic_vector(7 downto 0);
+
+		-- Bus and DMA controls:
+		CSn			: in bit;
+		RDn		    : in bit;
+		WRn	        : in bit;
+		EOPn        : in bit;
+		DACKn	    : in bit;
+		DRQ		    : out bit;
+		INT		    : out bit;
+		READY       : out bit;
+		
+		-- SCSI bus:
+		DBn		    : inout std_logic_vector(7 downto 0);
+		DBPn        : inout std_logic;
+		RSTn        : inout std_logic;
+		BSYn        : inout std_logic;
+		SELn        : inout std_logic;
+		ACKn        : inout std_logic;
+		ATNn        : inout std_logic;
+		REQn        : inout std_logic;
+		IOn         : inout std_logic;
+		CDn         : inout std_logic;
+		MSGn        : inout std_logic
+	);
+end entity WF5380_TOP;
+	
+architecture STRUCTURE of WF5380_TOP is
+component WF5380_TOP_SOC
+	port (
+        -- System controls:
+		CLK			: in bit;
+		RESETn	    : in bit;
+		ADR			: in bit_vector(2 downto 0);
+		DATA_IN		: in bit_vector(7 downto 0);
+		DATA_OUT	: out bit_vector(7 downto 0);
+		DATA_EN		: out bit;
+		CSn			: in bit;
+		RDn		    : in bit;
+		WRn	        : in bit;
+		EOPn        : in bit;
+		DACKn	    : in bit;
+		DRQ		    : out bit;
+		INT		    : out bit;
+		READY       : out bit;
+		DB_INn		: in bit_vector(7 downto 0);
+		DB_OUTn		: out bit_vector(7 downto 0);
+		DB_EN       : out bit;
+		DBP_INn		: in bit;
+		DBP_OUTn	: out bit;
+		DBP_EN      : out bit;
+		RST_INn     : in bit;
+		RST_OUTn    : out bit;
+		RST_EN      : out bit;
+		BSY_INn     : in bit;
+		BSY_OUTn    : out bit;
+		BSY_EN      : out bit;
+		SEL_INn     : in bit;
+		SEL_OUTn    : out bit;
+		SEL_EN      : out bit;
+		ACK_INn     : in bit;
+		ACK_OUTn    : out bit;
+		ACK_EN      : out bit;
+		ATN_INn     : in bit;
+		ATN_OUTn    : out bit;
+		ATN_EN      : out bit;
+		REQ_INn     : in bit;
+		REQ_OUTn    : out bit;
+		REQ_EN      : out bit;
+		IOn_IN      : in bit;
+		IOn_OUT     : out bit;
+		IO_EN       : out bit;
+		CDn_IN      : in bit;
+		CDn_OUT     : out bit;
+		CD_EN       : out bit;
+		MSG_INn     : in bit;
+		MSG_OUTn    : out bit;
+		MSG_EN      : out bit
+	);
+end component;
+--
+signal ADR_IN       : bit_vector(2 downto 0);
+signal DATA_IN      : bit_vector(7 downto 0);
+signal DATA_OUT     : bit_vector(7 downto 0);
+signal DATA_EN      : bit;
+signal DB_INn	    : bit_vector(7 downto 0);
+signal DB_OUTn	    : bit_vector(7 downto 0);
+signal DB_EN        : bit;
+signal DBP_INn	    : bit;
+signal DBP_OUTn	    : bit;
+signal DBP_EN       : bit;
+signal RST_INn      : bit;
+signal RST_OUTn     : bit;
+signal RST_EN       : bit;
+signal BSY_INn      : bit;
+signal BSY_OUTn     : bit;
+signal BSY_EN       : bit;
+signal SEL_INn      : bit;
+signal SEL_OUTn     : bit;
+signal SEL_EN       : bit;
+signal ACK_INn      : bit;
+signal ACK_OUTn     : bit;
+signal ACK_EN       : bit;
+signal ATN_INn      : bit;
+signal ATN_OUTn     : bit;
+signal ATN_EN       : bit;
+signal REQ_INn      : bit;
+signal REQ_OUTn     : bit;
+signal REQ_EN       : bit;
+signal IOn_IN       : bit;
+signal IOn_OUT      : bit;
+signal IO_EN        : bit;
+signal CDn_IN       : bit;
+signal CDn_OUT      : bit;
+signal CD_EN        : bit;
+signal MSG_INn      : bit;
+signal MSG_OUTn     : bit;
+signal MSG_EN       : bit;
+begin
+    ADR_IN <= To_BitVector(ADR);
+
+    DATA_IN <= To_BitVector(DATA);
+    DATA <= To_StdLogicVector(DATA_OUT) when DATA_EN = '1' else (others => 'Z');
+
+    DB_INn <= To_BitVector(DBn);
+    DBn <= To_StdLogicVector(DB_OUTn) when DB_EN = '1' else (others => 'Z');
+
+    DBP_INn <= To_Bit(DBPn);
+
+    RST_INn <= To_Bit(RSTn);
+    BSY_INn <= To_Bit(BSYn);
+    SEL_INn <= To_Bit(SELn);
+    ACK_INn <= To_Bit(ACKn);
+    ATN_INn <= To_Bit(ATNn);
+    REQ_INn <= To_Bit(REQn);
+    IOn_IN <= To_Bit(IOn);
+    CDn_IN <= To_Bit(CDn);
+    MSG_INn <= To_Bit(MSGn);
+
+    DBPn <= '1' when DBP_OUTn = '1' and DBP_EN = '1' else
+            '0' when DBP_OUTn = '0' and DBP_EN = '1' else 'Z';
+    RSTn <= '1' when RST_OUTn = '1' and RST_EN = '1'else
+            '0' when RST_OUTn = '0' and RST_EN = '1' else 'Z';
+    BSYn <= '1' when BSY_OUTn = '1' and BSY_EN = '1' else
+            '0' when BSY_OUTn = '0' and BSY_EN = '1' else 'Z';
+    SELn <= '1' when SEL_OUTn = '1' and SEL_EN = '1' else
+            '0' when SEL_OUTn = '0' and SEL_EN = '1' else 'Z';
+    ACKn <= '1' when ACK_OUTn = '1' and ACK_EN = '1' else
+            '0' when ACK_OUTn = '0' and ACK_EN = '1' else 'Z';
+    ATNn <= '1' when ATN_OUTn = '1' and ATN_EN = '1' else
+            '0' when ATN_OUTn = '0' and ATN_EN = '1' else 'Z';
+    REQn <= '1' when REQ_OUTn = '1' and REQ_EN = '1' else
+            '0' when REQ_OUTn = '0' and REQ_EN = '1' else 'Z';
+    IOn <=  '1' when IOn_OUT = '1' and IO_EN = '1' else
+            '0' when IOn_OUT = '0' and IO_EN = '1' else 'Z';
+    CDn <=  '1' when CDn_OUT = '1' and CD_EN = '1' else
+            '0' when CDn_OUT = '0' and CD_EN = '1' else 'Z';
+    MSGn <= '1' when MSG_OUTn = '1' and MSG_EN = '1' else
+            '0' when MSG_OUTn = '0' and MSG_EN = '1' else 'Z';
+
+    I_5380: WF5380_TOP_SOC
+        port map(
+            CLK			=> CLK,
+            RESETn	    => RESETn,
+            ADR			=> ADR_IN,
+            DATA_IN		=> DATA_IN,
+            DATA_OUT	=> DATA_OUT,
+            DATA_EN		=> DATA_EN,
+            CSn			=> CSn,
+            RDn		    => RDn,
+            WRn	        => WRn,
+            EOPn        => EOPn,
+            DACKn	    => DACKn,
+            DRQ		    => DRQ,
+            INT		    => INT,
+            READY       => READY,
+            DB_INn		=> DB_INn,
+            DB_OUTn		=> DB_OUTn,
+            DB_EN       => DB_EN,
+            DBP_INn     => DBP_INn,
+            DBP_OUTn    => DBP_OUTn,
+            DBP_EN      => DBP_EN,
+            RST_INn     => RST_INn,
+            RST_OUTn    => RST_OUTn,
+            RST_EN      => RST_EN,
+            BSY_INn     => BSY_INn,
+            BSY_OUTn    => BSY_OUTn,
+            BSY_EN      => BSY_EN,
+            SEL_INn     => SEL_INn,
+            SEL_OUTn    => SEL_OUTn,
+            SEL_EN      => SEL_EN,
+            ACK_INn     => ACK_INn,
+            ACK_OUTn    => ACK_OUTn,
+            ACK_EN      => ACK_EN,
+            ATN_INn     => ATN_INn,
+            ATN_OUTn    => ATN_OUTn,
+            ATN_EN      => ATN_EN,
+            REQ_INn     => REQ_INn,
+            REQ_OUTn    => REQ_OUTn,
+            REQ_EN      => REQ_EN,
+            IOn_IN      => IOn_IN,
+            IOn_OUT     => IOn_OUT,
+            IO_EN       => IO_EN,
+            CDn_IN      => CDn_IN,
+            CDn_OUT     => CDn_OUT,
+            CD_EN       => CD_EN,
+            MSG_INn     => MSG_INn,
+            MSG_OUTn    => MSG_OUTn,
+            MSG_EN      => MSG_EN
+        );
+end STRUCTURE;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
new file mode 100644
index 0000000..10a86f9
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
@@ -0,0 +1,253 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WD1772 compatible floppy disk controller IP Core.            ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Floppy disk controller with all features of the Western      ----
+---- Digital WD1772-02 controller.                                ----
+----                                                              ----
+---- Address mark detector file. This part detects the address    ----
+---- mark in the incoming data stream in FM and also in MFM mode  ----
+---- and provides therewith synchronisation information for the   ----
+---- control state machine and for the data separator in the      ----
+---- transceiver unit.                                            ----
+----                                                              ----
+------------------------------- Some theory -------------------------------------
+---- Frequency modulation FM:                                                ----
+---- The frequency modulation works as follows:                              ----
+---- 1. every first pulse of the clock and data line is a clock.             ----
+---- 2. every second pulse is a data.                                        ----
+---- 3. a logic 1 is represented by two consecutive pulses (clock and data). ----
+---- 4. a logic 0 is represented by one clock pulse and no data pulse.       ----
+---- 5. Hence there are a maximum of two pulses per data bit.                ----
+---- 6. one clock and one data pulse come together in one bit cell.          ----
+---- 7. the duration of a bit cell in FM is 4 microseconds.                  ----
+---- 8. an ID address mark is represented as data FE with clock C7.          ----
+---- 9. a DATA address mark is represented as data FB with clock C7.         ----
+---- Examples:                                                               ----
+---- Binary data 1 1 0 0 1 0 1 1 is represented in FM as follows:            ----
+----            1111101011101111                                             ----
+---- the FE data           1 1 1 1 1 1 1 0 is represented as follows:        ----
+----                      1111111111111110                                   ----
+---- with C7 clock mask   1 1 0 0 0 1 1 1 which masks the clock pulses there ----
+---- results:             1111010101111110 this is the ID address mark.      ----
+---- the FB data           1 1 1 1 1 0 1 1 is represented as follows:        ----
+----                      1111111111101111                                   ----
+---- with C7 clock mask   1 1 0 0 0 1 1 1 which masks the clock pulses there ----
+---- results:             1111010101101111 this is the DATA address mark.    ----
+---- the F8 data           1 1 1 1 1 0 0 0 is represented as follows:        ----
+----                      1111111111101010                                   ----
+---- with C7 clock mask   1 1 0 0 0 1 1 1 which masks the clock pulses there ----
+---- results:             1111010101101010 this is the deleted DATA mark.    ----
+----                                                                         ----
+----                                                                         ----
+---- Modified frequency modulation MFM:                                      ----
+---- The modified frequency modulation works as follows:                     ----
+---- 1. every first pulse of the clock and data line is a clock.             ----
+---- 2. every second pulse is a data.                                        ----
+---- 3. a logic 1 is represented by no clock but a data pulse.               ----
+---- 4. a logic 0 is represented by a clock pulse and no data pulse if       ---- 
+---- following a 0.                                                          ----
+---- 5. a logic 0 is represented by no pulse if following a 1.               ----
+---- 6. Hence there are a maximum of one pulse per data bit.                 ----
+---- 7. one clock and one data pulse form together one bit cell.             ----
+---- 8. the duration of a bit cell in MFM is 2 microseconds.                 ----
+---- 9. an address mark sync is represented as data A1 with missing clock    ----
+---- pulse between bit 4 and 5.                                              ----
+---- Examples:                                                               ----
+---- Binary data FE 1 1 1 1 1 1 1 0 is represented in MFM as follows:        ----
+----               0101010101010100 this is the ID address mark.             ----
+---- Binary data FB 1 1 1 1 1 0 1 1 is represented in MFM as follows:        ----
+----               0101010101000101 this is the DATA address mark.           ----
+---- Binary data F8 1 1 1 1 1 0 0 0 is represented in MFM as follows:        ----
+----               0101010101001010 this is the deleted DATA address mark.   ----
+---- the A1 data           1 0 1 0 0 0 0 1 is represented as follows:        ----
+----                      0100010010101001                                   ----
+---- with the missing clock pulse between bits 4 and 5 there results:        ----
+---- results:             0100010010001001 this is the address mark sync.    ----
+----                                                                         ----
+---- Both MFM and FM are during read and write shifted with most significant ----
+---- bit (MSB) first. During the FM address marks are written without a      ----
+---- SYNC pulse the MFM coded data requires a synchronisation (A1 with       ----
+---- missing clock pulse because at the beginning of the data stream it is   ----
+---- not defined wether a clock pulse or a data pulse appears first. In FM   ----
+---- coding the first pulse is in any case a clock pulse.                    ----
+---------------------------------------------------------------------------------
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2006A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/05 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF1772IP_AM_DETECTOR is
+	port(
+		-- System control
+		CLK				: in bit;
+		RESETn			: in bit;
+
+		-- Controls:
+		DDEn		    : in bit;
+		
+		-- Serial data and clock:
+		DATA			: in bit;
+		DATA_STRB		: in bit;
+
+		-- Address mark detector:
+		ID_AM		: out bit; -- ID address mark strobe.
+		DATA_AM		: out bit; -- Data address mark strobe.
+		DDATA_AM	: out bit -- Deleted data address mark strobe.
+	);
+end WF1772IP_AM_DETECTOR;
+
+architecture BEHAVIOR of WF1772IP_AM_DETECTOR is
+signal SHIFT		: bit_vector(15 downto 0);
+signal SYNC			: boolean;
+signal ID_AM_I		: bit;
+signal DATA_AM_I	: bit;
+signal DDATA_AM_I	: bit;
+begin
+	SHIFTREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SHIFT <= (others => '0');
+		elsif CLK = '1' and CLK' event then
+			if DATA_STRB = '1' then
+				-- MSB first leads to a shift left operation.
+				SHIFT <= SHIFT(14 downto 0) & DATA;
+            elsif DDEn = '0' and SHIFT = "0100010010001001" then -- This is the synchronisation in MFM.
+				SHIFT <= (others => '0');
+			end if;
+		end if;
+	end process SHIFTREG;
+
+	MFM_SYNCLOCK: process(RESETn, CLK)
+	-- The SYNC pulse is generated in MFM mode only when the sync character
+	-- appears in the shift register (A1 sync mark, see file header).
+	-- After the sync character is detected, the sync time counter is loaded
+	-- with a value of 17. During counting the following 17 read clock pulses
+	-- down, the SYNC is true. After exactly 16 pulses the address mark is 
+	-- detected if the pattern in the shift register fits one of the address 
+	-- marks. The address mark pulses are valid for one read clock cycle until 
+	-- SYNC  goes low again. This mechanism is used to detect the correct address 
+	-- marks in the MFM data stream during the type III read track command. 
+	-- This is an improvement over the original WD1772 chip.
+	variable TMP : std_logic_vector(4 downto 0);
+	begin
+		if RESETn = '0' then
+			TMP := "00000";
+		elsif CLK = '1' and CLK' event then
+			if SHIFT = "0100010010001001" and DDEn = '0' then
+                TMP := "10001"; -- Load sync time counter.
+			elsif DATA_STRB = '1' and TMP > "00000" then
+				TMP := TMP - '1';
+			end if;
+		end if;
+		case TMP is
+			when "00000" => SYNC <= false;
+			when others => SYNC <= true;
+		end case;
+	end process MFM_SYNCLOCK;
+
+	-- The addressmark is nominally valid for one data pulse cycle (1us, 2us, 4us).
+	-- The pulse is shorter due to the fact that the detected address marks change the
+	-- state of the control state machine and so clear the address mark shift register...
+	ID_AM_I <=	 '1' when DDEn = '1' and SHIFT = "1111010101111110" else
+				 '1' when DDEn = '0' and SHIFT = "0101010101010100" and SYNC = true else '0';
+	DATA_AM_I <= '1' when DDEn = '1' and SHIFT = "1111010101101111" else
+				 -- Normal data address mark...
+				 '1' when DDEn = '0' and SHIFT = "0101010101000101"  and SYNC = true else '0';
+	DDATA_AM_I <= 	'1' when DDEn = '1' and SHIFT = "1111010101101010" else
+					-- ... and deleted address mark in MFM mode:
+					'1' when DDEn = '0' and SHIFT = "0101010101001010"  and SYNC = true else '0';
+					
+	ADRMARK_STROBES: process(RESETn, CLK)
+	-- ... nevertheless The controller and the transceiver require ID address mark strobes 
+	-- and DATA address mark strobes. Therefore this process provides these strobe
+	-- signals independant of any 'feedbacks' like pulse shortening by the controller
+	-- state machine itself.
+	variable ID_AM_LOCK, DATA_AM_LOCK, DDATA_AM_LOCK	: boolean;
+	begin
+		if RESETn = '0' then
+			ID_AM_LOCK := false;
+			DATA_AM_LOCK := false;
+			ID_AM <= '0';
+			DATA_AM <= '0';
+		elsif CLK = '1' and CLK' event then
+			-- ID address mark:
+			if ID_AM_I = '1' and ID_AM_LOCK = false then
+				ID_AM <= '1';
+				ID_AM_LOCK := true;
+			elsif ID_AM_I = '0' then
+				ID_AM <= '0';
+				ID_AM_LOCK := false;
+			else
+				ID_AM <= '0';
+			end if;
+			-- Data address mark:
+			if DATA_AM_I = '1' and DATA_AM_LOCK = false then
+				DATA_AM <= '1';
+				DATA_AM_LOCK := true;
+			elsif DATA_AM_I = '0' then
+				DATA_AM <= '0';
+				DATA_AM_LOCK := false;
+			else
+				DATA_AM <= '0';
+			end if;
+			-- Deleted data address mark:
+			if DDATA_AM_I = '1' and DDATA_AM_LOCK = false then
+				DDATA_AM <= '1';
+				DDATA_AM_LOCK := true;
+			elsif DDATA_AM_I = '0' then
+				DDATA_AM <= '0';
+				DDATA_AM_LOCK := false;
+			else
+				DDATA_AM <= '0';
+			end if;
+		end if;
+	end process ADRMARK_STROBES;
+end architecture BEHAVIOR;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
new file mode 100644
index 0000000..ce4c346
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
@@ -0,0 +1,1463 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WD1772 compatible floppy disk controller IP Core.            ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Floppy disk controller with all features of the Western      ----
+---- Digital WD1772-02 controller.                                ----
+----                                                              ----
+---- This is file the control unit providing all signals for the  ----
+---- data processing units like registers, addressmark detector,  ----
+---- data separator, CRC redundancy checker or transceiver.       ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2006A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/05 WF
+--   Modified Source to compile with the Xilinx ISE.
+--   Fixed the polarity of the precompensation flag.
+--   The flag is no active '0'. Thanks to Jorma
+--   Oksanen for the information.
+-- Revision 2K8A  2008/02/26 WF
+--   Fixed a bug in the 6ms delay. Thanks to Lyndon Amsdon.
+-- Revision 2K8B  2008/12/24 WF
+--   Bugfixes to avoid hanging state machine.
+--   Changed DELAY_30MS to DELAY_15MS, which is the correct value. Thanks to L. Amsdon for the information.
+--   Removed CRC_BUSY.
+--   Fixed a bug in the Delay for the state T2_VERIFY_AM.
+-- Revision 2K9A  2009/06/20 WF
+--   Fix to provide correct LOST_DATA_TR00 flag during seek command.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF1772IP_CONTROL is
+	port(
+		-- System control:
+		CLK		: in bit;
+		RESETn	: in bit;
+
+		-- Chip control signals:
+		A1, A0	: in bit;
+		RWn		: in bit;
+		CSn		: in bit;
+		DDEn	: in bit;
+
+		-- Registers:
+		DR	: in bit_vector(7 downto 0); -- Data register.
+		CMD	: in std_logic_vector(7 downto 0); -- Command register.
+		DSR	: in std_logic_vector(7 downto 0); -- Shift register.
+		TR	: in std_logic_vector(7 downto 0); -- Track register.
+		SR	: in std_logic_vector(7 downto 0); -- Sector register.
+
+		-- Status flags:
+		MO				: buffer bit; -- Motor on status flag.
+		WR_PR			: out bit; -- Write protect status flag.
+		SPINUP_RECTYPE	: out bit; -- Spin up / record type status flag.
+        SEEK_RNF		: out bit; -- Seek error / record not found status flag.
+		CRC_ERRFLAG		: out bit; -- CRC status flag.
+		LOST_DATA_TR00	: out bit; -- Status flag indicates lost data or track 00 position.
+        DRQ				: out bit; -- Data request.
+		DRQ_IPn			: out bit; -- Data request status flag.
+		BUSY			: buffer bit; -- BUSY status flag.
+
+		-- Address mark detector controls:
+		AM_2_DISK	: out bit;	-- Enables / disables the address mark detector.
+		ID_AM		: in bit; 	-- Address mark of the ID field
+		DATA_AM		: in bit; 	-- Address mark of the data field
+		DDATA_AM	: in bit; 	-- Address mark of a deleted data field
+
+		-- CRC unit controls:
+		CRC_ERR		: in bit; 	-- CRC decoder's error.
+		CRC_PRES	: out bit;	-- Preset CRC during write operations.
+
+		-- Track register controls:
+		TR_PRES		: out bit;	-- Set x"FF".
+		TR_CLR		: out bit;	-- Clear.
+		TR_INC		: out bit;	-- Increment.
+		TR_DEC		: out bit;	-- Decrement.
+
+		-- Sector register control:
+		SR_LOAD		: out bit; -- Load.
+		SR_INC		: out bit; -- Increment.
+		-- The TRACK_NR is required during the type III command
+		--  'Read Address'. TRACK_NR is the content of the TRACKMEM.
+		TRACK_NR	: out std_logic_vector(7 downto 0);
+
+		-- DATA register control:
+		DR_CLR		: out bit; -- Clear.
+		DR_LOAD		: out bit; -- LOAD.
+
+		-- Shift register control:
+		SHFT_LOAD_ND	: out bit; -- Load normal data.
+		SHFT_LOAD_SD	: out bit; -- Load special data.
+
+		-- Transceiver controls:
+		CRC_2_DISK	: out bit;	-- Cause the Transceiver to write out CRC data.
+		DSR_2_DISK	: out bit;	-- Cause the Transceiver to write normal data.
+		FF_2_DISK	: out bit;	-- Cause the Transceiver to write x"FF" bytes.
+		PRECOMP_EN	: out bit; 	-- Enables the write precompensation.
+
+		-- Miscellaneous Controls:
+		DATA_STRB 	: in bit;	-- Data strobe (read and write operation)
+		WPRTn		: in bit; 	-- Write protect flag
+		IPn			: in bit; 	-- Index pulse flag
+		TRACK00n	: in bit; 	-- Track zero flag
+		DISK_RWn	: out bit;  -- This signal reflects the data direction.
+		DIRC		: out bit;	-- Step direction control.
+		STEP		: out bit;	-- Step pulse.
+		WG			: out bit;	-- Write gate control.
+		INTRQ		: out bit 	-- Interrupt request flag.
+	);
+end WF1772IP_CONTROL;
+
+architecture BEHAVIOR of WF1772IP_CONTROL is
+-- The control state machine for the three command types I, II and III 
+-- (10 commands) has 73 states:
+type CMD_STATES is(	IDLE, INIT, SPINUP, DELAY_15MS, DECODE, T1_SEEK_RESTORE, T1_STEPPING, 
+					T1_LOAD_SHFT, T1_COMP_TR_DSR, T1_CHECK_DIR, T1_HEAD_CTRL, T1_STEP, T1_TRAP, T1_STEP_DELAY,
+					T1_SPINDOWN, T1_SCAN_TRACK, T1_SCAN_CRC, T1_VERIFY_DELAY, T1_VERIFY_CRC, T2_RD_WR_SECT, 
+					T2_INIT, T2_SCAN_TRACK, T2_SCAN_SECT, T2_SCAN_LEN, T2_VERIFY_CRC_1, T2_VERIFY_AM, T2_FIRSTBYTE, 
+					T2_LOAD_DATA, T2_NEXTBYTE, T2_VERIFY_DRQ_1, T2_RDSTAT, T2_VERIFY_CRC_2, 
+					T2_MULTISECT, T2_DELAY_B2, T2_SET_DRQ, T2_DELAY_B8, T2_VERIFY_DRQ_2, 
+					T2_DELAY_B1, T2_CHECK_MODE, T2_DELAY_B11, T2_WR_LEADIN, T2_WR_AM, 
+					T2_LOAD_SHFT, T2_WR_BYTE, T2_VERIFY_DRQ_3, T2_DATALOST, T2_WRSTAT, T2_WR_CRC, 
+					T2_WR_FF, T3_WR, T3_DELAY_B3, T3_VERIFY_DRQ, T3_CHECK_INDEX_1, T3_LOAD_SHFT, 
+					T3_WR_DATA, T3_CHECK_INDEX_2, T3_DATALOST, T3_RD_TRACK, T3_SHIFT, 
+					T3_CHECK_INDEX_3, T3_DETECT_AM, T3_CHECK_BYTE, T3_CHECK_DR, T3_LOAD_DATA_1, 
+					T3_SET_DRQ_1, T3_RD_ADR, T3_VERIFY_AM, T3_SHIFT_ADR, T3_LOAD_DATA_2, 
+					T3_SET_DRQ_2, T3_CHECK_RD, T3_LOAD_SR, T3_VERIFY_CRC);
+signal CMD_STATE		: CMD_STATES;
+signal NEXT_CMD_STATE	: CMD_STATES;
+signal DATA_WR			: boolean;
+signal DATA_RD			: boolean;
+signal CMD_WR			: boolean;
+signal STAT_RD			: boolean;
+signal DELAY			: boolean;
+signal DRQ_I            : bit;
+signal INDEX_CNT		: boolean;
+signal DIR				: bit;
+signal INDEX_MARK		: bit;
+signal STEP_TRAP		: boolean;
+signal TYPE_IV_BREAK	: boolean;
+signal BYTE_RDY			: boolean;
+signal SECT_LEN 		: std_logic_vector(10 downto 0);
+signal TRACKMEM			: std_logic_vector(7 downto 0);
+signal T3_TRADR			: boolean;
+signal T3_DATATYPE		: bit_vector(7 downto 0);
+begin
+	-- The Forced interrupt stops any command at the end of an internal micro instruction.
+	-- Forced interrupt waits until ALU operations in progress are complete (CRC calculations,
+	-- compares etc.). the TYPE_IV_BREAK controls this behavior.
+    TYPE_IV_BREAK <= true when CMD(7 downto 4) = x"D" and DELAY = true else false;
+
+	CMD_REG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			CMD_STATE <= IDLE;
+		elsif CLK = '1' and CLK' event then
+			if TYPE_IV_BREAK = true then
+				CMD_STATE <= IDLE; -- Forced interrupt break.
+			else
+				CMD_STATE <= NEXT_CMD_STATE; -- Normal operation.
+			end if;
+		end if;
+	end process CMD_REG;
+
+	CMD_DECODER: process(CMD_STATE, CMD, DSR, TR, SR, INDEX_CNT, IPn, INDEX_MARK, DELAY, DIR, MO, CMD_WR, DRQ_I, 
+						 DDEn, CRC_ERR, TRACK00n, STEP_TRAP, ID_AM, DATA_AM, DDATA_AM, WPRTn, SECT_LEN, BYTE_RDY,
+						 T3_TRADR)
+	begin
+		case CMD_STATE is
+			--------------------------------------------------------------------
+			------------------ type1, -2, -3 command stuff ---------------------
+			--------------------------------------------------------------------
+			when IDLE =>
+				-- The write access to the command register indicates a new command.
+				-- Any command received (type1, -2 or -3 but not type4):
+				if CMD_WR = true and CMD /= x"FF" and CMD(7 downto 4) /= "1101" then
+					NEXT_CMD_STATE <= INIT;
+				else
+					NEXT_CMD_STATE <= IDLE; -- No CMD detected.
+				end if;
+			when INIT =>
+				-- The process goes on when the CMD_WR flag is released.
+				if CMD_WR = false and CMD(3) = '0' and MO = '0' then
+					-- Do not enter the SPINUP sequence 
+					-- when the motor is already on (MO = '1').
+					NEXT_CMD_STATE <= SPINUP;
+				elsif CMD_WR = false then
+					-- Proceed with the DELAY_15MS when the motor was
+					-- already on or when the SPINUP sequence is
+					-- disabled (CMD(3) = '1').
+					NEXT_CMD_STATE <= DELAY_15MS;
+				else
+					NEXT_CMD_STATE <= INIT;
+				end if;
+			when SPINUP =>
+				if INDEX_CNT = true then -- proceed after 6 revolutions
+					NEXT_CMD_STATE <= DELAY_15MS;
+				else
+					NEXT_CMD_STATE <= SPINUP;
+				end if;
+			when DELAY_15MS =>
+				if CMD(7) = '0' then -- No delay for type1 commands.
+					NEXT_CMD_STATE <= DECODE;
+				elsif CMD(7) = '1' and CMD(2) = '0' then -- Delay for type2 and -3 disabled.
+					NEXT_CMD_STATE <= DECODE;
+				elsif CMD(7) = '1' and CMD(2) = '1' and DELAY = true then -- Delay enabled by CMD(2).
+					NEXT_CMD_STATE <= DECODE;
+				else
+					NEXT_CMD_STATE <= DELAY_15MS;
+				end if;
+			when DECODE =>
+				case CMD(7 downto 5) is 
+					when "000" => -- 'restore', 'seek'.
+						NEXT_CMD_STATE <= T1_SEEK_RESTORE;
+					when "001" |"010" | "011" => -- 'step', 'step in', 'step out'.
+						NEXT_CMD_STATE <= T1_STEPPING;
+					when "100" | "101" => -- 'read sector', 'write sector'
+						NEXT_CMD_STATE <= T2_RD_WR_SECT;
+					when "110" => -- 'read address'.
+						-- "110" is also used by the 'force interrupt'.
+						-- There will result no wrong encoding because
+						-- the 'force intterrupt' is predecoded in IDLE.
+						NEXT_CMD_STATE <= T3_RD_ADR;
+					when "111" => -- 'read track', 'write track'.
+						case CMD(4) is
+							when '0' =>	NEXT_CMD_STATE <= T3_RD_TRACK;
+							when '1' => NEXT_CMD_STATE <= T3_WR;
+							when others => NEXT_CMD_STATE <= T3_WR; -- Dummy for U, X, Z, W, H, L, -.
+						end case;
+					when others => 
+						-- The following NEXT_CMD_STATE is chosen to compile fine with
+						-- the Xilinx ISE not to produce a latch.
+						NEXT_CMD_STATE <= IDLE; -- Never true due to IDLE preselection.
+				end case;
+			--------------------------------------------------------------------
+			------------------ special type1 command stuff ---------------------
+			--------------------------------------------------------------------
+			when T1_SEEK_RESTORE =>
+				-- In this state, the data register and the track register are updated, if the
+				-- command is a RESTORE. The update is done further down with the track register
+				-- and the data register controls.
+				NEXT_CMD_STATE <= T1_LOAD_SHFT;
+			when T1_STEPPING =>
+				if CMD(4) = '1' then -- '1' means update track register.
+					NEXT_CMD_STATE <= T1_CHECK_DIR;
+				else
+					NEXT_CMD_STATE <= T1_HEAD_CTRL;
+				end if;
+			when T1_LOAD_SHFT =>
+				NEXT_CMD_STATE <= T1_COMP_TR_DSR;
+			when T1_COMP_TR_DSR =>
+				if DSR = TR then
+					NEXT_CMD_STATE <= T1_VERIFY_DELAY;
+				else
+					-- The direction control is done further down.
+					NEXT_CMD_STATE <= T1_CHECK_DIR;
+				end if;
+			when T1_CHECK_DIR =>
+				-- Track register modifications are done in
+				-- statements further down.
+				-- The delay is to provide the timing of the WD1772 which is DIR to step =
+				-- 24us in MFM mode and 48us in FM mode.
+				if DELAY = true then
+					NEXT_CMD_STATE <= T1_HEAD_CTRL;
+				else
+					NEXT_CMD_STATE <= T1_CHECK_DIR;
+				end if;
+			when T1_HEAD_CTRL =>
+				if TRACK00n = '0' and DIR = '0' then
+					NEXT_CMD_STATE <= T1_VERIFY_DELAY;
+				else
+					NEXT_CMD_STATE <= T1_STEP;
+				end if;
+			when T1_STEP =>
+				NEXT_CMD_STATE <= T1_TRAP;
+			when T1_TRAP =>
+				if STEP_TRAP = true then
+					NEXT_CMD_STATE <= IDLE; -- Break due to seek error.
+				else
+					NEXT_CMD_STATE <= T1_STEP_DELAY;
+				end if;
+			when T1_STEP_DELAY =>
+				-- The delay in here is according to the CMD(1 downto 0) as follows:
+				-- "11" = 3ms, "10" = 2ms, "01" = 12ms, "00" = 6ms.				
+				if DELAY = true then
+					case CMD(7 downto 5) is
+						when "001" | "010" | "011" => -- STEP - STEP IN - STEP OUT.
+							NEXT_CMD_STATE <= T1_VERIFY_DELAY;
+						when others => -- Seek or restore command.
+							NEXT_CMD_STATE <= T1_LOAD_SHFT;
+					end case;
+				else
+					NEXT_CMD_STATE <= T1_STEP_DELAY;
+				end if;
+			when T1_VERIFY_DELAY =>
+				if CMD(2) = '0' then -- No verify.
+					NEXT_CMD_STATE <= IDLE;
+				else
+					if DELAY = true then -- Wait, if verify is active.
+						NEXT_CMD_STATE <= T1_SPINDOWN;
+					else
+						NEXT_CMD_STATE <= T1_VERIFY_DELAY;
+					end if;
+				end if;
+			when T1_SPINDOWN => -- Detect ID address mark in here.
+				if INDEX_CNT = true then
+					NEXT_CMD_STATE <= IDLE; -- Break due to timeout.
+				elsif ID_AM = '1' then -- Addressmark found.
+					NEXT_CMD_STATE <= T1_SCAN_TRACK;
+				else
+					NEXT_CMD_STATE <= T1_SPINDOWN;
+				end if;
+			when T1_SCAN_TRACK =>
+				if DELAY = true then
+					-- Track found if shift register (DSR) equals track register (TR).
+					if DSR = TR then
+						NEXT_CMD_STATE <= T1_SCAN_CRC;
+					else
+						NEXT_CMD_STATE <= T1_SPINDOWN;
+					end if;
+				else
+					NEXT_CMD_STATE <= T1_SCAN_TRACK;
+				end if;
+			when T1_SCAN_CRC =>
+				-- Scan the rest of the data header for correct CRC generation (3 Bytes).
+				-- Sector number side select byte and data length byte.
+				if DELAY = true then
+					NEXT_CMD_STATE <= T1_VERIFY_CRC;
+				else
+					NEXT_CMD_STATE <= T1_SCAN_CRC;
+				end if;
+			when T1_VERIFY_CRC =>
+                -- The CRC logic starts during T1_SPINDOWN (missing clock transitions).
+                if DELAY = true then
+                    if CRC_ERR = '1' then
+                        NEXT_CMD_STATE <= T1_SPINDOWN; -- CRC error.
+                    else
+                        NEXT_CMD_STATE <= IDLE; -- Operation finished.
+                    end if;		
+                else
+                    NEXT_CMD_STATE <= T1_VERIFY_CRC; -- Wait until CRC logic is ready.
+                end if;
+			--------------------------------------------------------------------
+			------------------ special type2 command stuff ---------------------
+			--------------------------------------------------------------------
+			when T2_RD_WR_SECT =>
+				if CMD(7 downto 5) = "101" and WPRTn = '0' then
+					NEXT_CMD_STATE <= IDLE; -- Break due to write protected disk.
+				else
+					NEXT_CMD_STATE <= T2_INIT;
+				end if;
+			when T2_INIT =>
+				if INDEX_CNT = true then
+					NEXT_CMD_STATE <= IDLE; -- Break due to timeout.
+				elsif ID_AM = '0' then
+					NEXT_CMD_STATE <= T2_INIT; -- Wait for address mark.
+				else -- INDEX_CNT = false and ID_AM = '1' -> ID address mark detected
+					NEXT_CMD_STATE <= T2_SCAN_TRACK;
+				end if;
+			when T2_SCAN_TRACK =>
+				-- Track found if shift register (DSR) equals track register (TR).
+				if DELAY = true then
+					if DSR = TR then
+						NEXT_CMD_STATE <= T2_SCAN_SECT;
+					else
+						NEXT_CMD_STATE <= T2_INIT;
+					end if;
+				else
+					NEXT_CMD_STATE <= T2_SCAN_TRACK;
+				end if;
+			when T2_SCAN_SECT =>
+				-- Sector found if shift register (DSR) equals sector register (SR).
+				if DELAY = true then
+					if DSR = SR then
+						NEXT_CMD_STATE <= T2_SCAN_LEN;
+					else
+						NEXT_CMD_STATE <= T2_INIT;
+					end if;
+				else
+					NEXT_CMD_STATE <= T2_SCAN_SECT;
+				end if;
+			when T2_SCAN_LEN =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_VERIFY_CRC_1;
+				else
+					NEXT_CMD_STATE <= T2_SCAN_LEN;
+				end if;
+			when T2_VERIFY_CRC_1 =>
+				-- The CRC logic starts after T2_INIT (missing clock transitions).
+				if DELAY = true then
+					if CRC_ERR = '1' then
+						NEXT_CMD_STATE <= T2_INIT; -- CRC error.
+					elsif CRC_ERR = '0' and CMD(7 downto 5) = "101" then
+						NEXT_CMD_STATE <= T2_DELAY_B2; -- Comand is a write.
+					else -- Command is a read.
+						NEXT_CMD_STATE <= T2_VERIFY_AM;
+					end if;
+				else
+					NEXT_CMD_STATE <= T2_VERIFY_CRC_1; -- Wait until CRC logic is ready.
+				end if;
+			when T2_VERIFY_AM =>
+				if DATA_AM = '1' or DDATA_AM = '1' then -- Data address mark detected, go on.
+					NEXT_CMD_STATE <= T2_FIRSTBYTE;
+				elsif DELAY = false then -- Stay in this state.
+					NEXT_CMD_STATE <= T2_VERIFY_AM;
+				else
+					NEXT_CMD_STATE <= T2_INIT; -- No addressmark detected.
+				end if;
+			when T2_FIRSTBYTE =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_LOAD_DATA;
+				else
+					NEXT_CMD_STATE <= T2_FIRSTBYTE;
+				end if;
+			when T2_LOAD_DATA =>
+				NEXT_CMD_STATE <= T2_NEXTBYTE;
+			when T2_NEXTBYTE =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_VERIFY_DRQ_1;
+				else
+					NEXT_CMD_STATE <= T2_NEXTBYTE;
+				end if;
+			when T2_VERIFY_DRQ_1 =>
+				NEXT_CMD_STATE <= T2_RDSTAT;
+			when T2_RDSTAT =>
+				if SECT_LEN = "00000000000" then
+					NEXT_CMD_STATE <= T2_VERIFY_CRC_2;
+				else
+					NEXT_CMD_STATE <= T2_LOAD_DATA;
+				end if;
+			when T2_VERIFY_CRC_2 =>
+				-- The CRC logic starts after T2_VERIFY_AM (missing clock transitions).
+				if DELAY = true then
+					if CRC_ERR = '1' then
+						NEXT_CMD_STATE <= IDLE; -- Break due to CRC error.
+					else
+						NEXT_CMD_STATE <= T2_MULTISECT;
+					end if;
+				else
+					NEXT_CMD_STATE <= T2_VERIFY_CRC_2; -- Wait until CRC logic is ready.
+				end if;
+			when T2_MULTISECT =>
+				if  CMD(4) = '1' then
+					NEXT_CMD_STATE <= T2_RD_WR_SECT;
+				else
+					NEXT_CMD_STATE <= IDLE; -- Operation finished.
+				end if;
+			when T2_DELAY_B2 =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_SET_DRQ;
+				else
+					NEXT_CMD_STATE <= T2_DELAY_B2;
+				end if;
+			when T2_SET_DRQ =>
+				NEXT_CMD_STATE <= T2_DELAY_B8;
+			when T2_DELAY_B8 =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_VERIFY_DRQ_2;
+				else
+					NEXT_CMD_STATE <= T2_DELAY_B8;
+				end if;
+			when T2_VERIFY_DRQ_2 =>
+				if DRQ_I = '0' then
+					NEXT_CMD_STATE <= T2_DELAY_B1;
+				else
+					NEXT_CMD_STATE <= IDLE; -- Break due to lost data (no new data by host).
+				end if;
+			when T2_DELAY_B1 => 
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_CHECK_MODE;
+				else
+					NEXT_CMD_STATE <= T2_DELAY_B1;
+				end if;
+			when T2_CHECK_MODE =>
+				if DDEn = '1' then -- FM mode
+					NEXT_CMD_STATE <= T2_WR_LEADIN;
+				else
+					NEXT_CMD_STATE <= T2_DELAY_B11;
+				end if;
+			when T2_DELAY_B11 =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_WR_LEADIN;
+				else
+					NEXT_CMD_STATE <= T2_DELAY_B11;
+				end if;
+			when T2_WR_LEADIN =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_WR_AM;
+				else
+					NEXT_CMD_STATE <= T2_WR_LEADIN;
+				end if;
+			when T2_WR_AM => -- Write data address mark.
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_LOAD_SHFT;
+				else
+					NEXT_CMD_STATE <= T2_WR_AM;
+				end if;
+			when T2_LOAD_SHFT =>
+					NEXT_CMD_STATE <= T2_WR_BYTE;
+			when T2_WR_BYTE =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_VERIFY_DRQ_3;
+				else
+					NEXT_CMD_STATE <= T2_WR_BYTE;
+				end if;
+			when T2_VERIFY_DRQ_3 =>
+				if DRQ_I = '0' then
+					NEXT_CMD_STATE <= T2_WRSTAT;
+				else
+					NEXT_CMD_STATE <= T2_DATALOST;
+				end if;
+			when T2_DATALOST =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_WRSTAT;
+				else
+					NEXT_CMD_STATE <= T2_DATALOST;
+				end if;
+			when T2_WRSTAT =>
+				if SECT_LEN = "00000000000" then
+					NEXT_CMD_STATE <= T2_WR_CRC; -- Write operation finished.
+				else
+					NEXT_CMD_STATE <= T2_LOAD_SHFT;
+				end if;
+			when T2_WR_CRC =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_WR_FF;
+				else
+					NEXT_CMD_STATE <= T2_WR_CRC;
+				end if;
+			when T2_WR_FF =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T2_MULTISECT;
+				else
+					NEXT_CMD_STATE <= T2_WR_FF;
+				end if;
+			--------------------------------------------------------------------
+			---------------- type3 write track command stuff -------------------
+			--------------------------------------------------------------------
+			when T3_WR =>
+				if WPRTn = '0' then
+					NEXT_CMD_STATE <= IDLE; -- Break due to write protected disk.
+				else
+					NEXT_CMD_STATE <= T3_DELAY_B3;
+				end if;
+			when T3_DELAY_B3 =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T3_VERIFY_DRQ;
+				else
+					NEXT_CMD_STATE <= T3_DELAY_B3;
+				end if;
+			when T3_VERIFY_DRQ =>
+				if DRQ_I = '0' then
+					NEXT_CMD_STATE <= T3_CHECK_INDEX_1;
+				else
+					NEXT_CMD_STATE <= IDLE; -- Break due to lost data (no new data by host).
+				end if;				
+			when T3_CHECK_INDEX_1 =>
+				if IPn = '0' then
+					NEXT_CMD_STATE <= T3_LOAD_SHFT;
+				else
+					NEXT_CMD_STATE <= T3_CHECK_INDEX_1;
+				end if;				
+			when T3_LOAD_SHFT =>
+				NEXT_CMD_STATE <= T3_WR_DATA;
+			when T3_WR_DATA =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T3_CHECK_INDEX_2;
+				else
+					NEXT_CMD_STATE <= T3_WR_DATA;
+				end if;
+			when T3_CHECK_INDEX_2 =>
+				if INDEX_MARK = '1' then
+					NEXT_CMD_STATE <= IDLE; -- End of track reached.
+				elsif DRQ_I = '0' then -- New data has been loaded.
+					NEXT_CMD_STATE <= T3_LOAD_SHFT; -- Fetch new data.
+				else
+					NEXT_CMD_STATE <= T3_DATALOST; -- Fill in nullbyte.
+				end if;
+			when T3_DATALOST =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T3_CHECK_INDEX_2;
+				else
+					NEXT_CMD_STATE <= T3_DATALOST;
+				end if;
+			--------------------------------------------------------------------
+			--------------- type3 read track command stuff --------------------
+			--------------------------------------------------------------------
+			when T3_RD_TRACK =>
+				-- wait for index pulse:
+				if IPn = '0' then
+					NEXT_CMD_STATE <= T3_SHIFT;
+				else
+					NEXT_CMD_STATE <= T3_RD_TRACK;
+				end if;
+			when T3_SHIFT =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T3_CHECK_INDEX_3;
+				else
+					NEXT_CMD_STATE <= T3_SHIFT;
+				end if;
+			when T3_CHECK_INDEX_3 =>
+				if INDEX_MARK = '1' then
+					NEXT_CMD_STATE <= IDLE; -- End of track reached.
+				else
+					NEXT_CMD_STATE <= T3_DETECT_AM;
+				end if;
+			when T3_DETECT_AM => -- Detect for ID address mark.
+				if ID_AM = '1' then
+					NEXT_CMD_STATE <= T3_CHECK_DR;
+				else
+					NEXT_CMD_STATE <= T3_CHECK_BYTE;
+				end if;
+			when T3_CHECK_BYTE =>
+				if BYTE_RDY = true then
+					NEXT_CMD_STATE <= T3_CHECK_DR;
+				else
+					NEXT_CMD_STATE <= T3_SHIFT;
+				end if;
+			when T3_CHECK_DR =>
+				NEXT_CMD_STATE <= T3_LOAD_DATA_1;
+			when T3_LOAD_DATA_1 =>
+				NEXT_CMD_STATE <= T3_SET_DRQ_1;
+			when T3_SET_DRQ_1 =>
+				NEXT_CMD_STATE <= T3_SHIFT;
+			--------------------------------------------------------------------
+			---------------- type3 read address command stuff ------------------
+			--------------------------------------------------------------------
+			when T3_RD_ADR =>
+				-- check for 6 index holes
+				if INDEX_CNT = true then
+					NEXT_CMD_STATE <= IDLE; -- Break due to timeout.
+				else
+					NEXT_CMD_STATE <= T3_VERIFY_AM;
+				end if;
+			when T3_VERIFY_AM => -- Check for existing ID address mark
+				if ID_AM = '1' then
+					NEXT_CMD_STATE <= T3_SHIFT_ADR;
+				else
+					NEXT_CMD_STATE <= T3_RD_ADR;
+				end if;
+			when T3_SHIFT_ADR =>
+				if DELAY = true then
+					NEXT_CMD_STATE <= T3_LOAD_DATA_2;
+				else
+					NEXT_CMD_STATE <= T3_SHIFT_ADR;
+				end if;
+			when T3_LOAD_DATA_2 =>
+				NEXT_CMD_STATE <= T3_SET_DRQ_2;
+			when T3_SET_DRQ_2 =>
+				NEXT_CMD_STATE <= T3_CHECK_RD;
+			when T3_CHECK_RD =>
+				if T3_TRADR = true then
+					NEXT_CMD_STATE <= T3_LOAD_SR;
+				else
+					NEXT_CMD_STATE <= T3_SHIFT_ADR;
+				end if;
+			when T3_LOAD_SR =>
+				NEXT_CMD_STATE <= T3_VERIFY_CRC;
+			when T3_VERIFY_CRC =>
+				-- The CRC logic starts during T3_VERIFY_AM (missing clock transitions).
+				if DELAY = true then
+					NEXT_CMD_STATE <= IDLE; -- Operation finished (with or without CRC error).
+				else
+					NEXT_CMD_STATE <= T3_VERIFY_CRC; -- Wait until CRC logic is ready.
+				end if;
+		end case;
+	end process CMD_DECODER;
+
+	P_DELAY: process(RESETn, CLK, CMD_STATE, T3_DATATYPE, DDEn, CMD)
+	-- This process is responsible to control the DELAY signal in the different command
+	-- states of the main state machine. These states finish, if the signal DELAY is
+	-- asserted. The condition for asserted DELAY is the correct number of data strobes
+	-- which are supervised by the DATA_STRB inputs.
+	-- Another condition is a time delay required in the following states:
+	-- In DELAY_15MS there is a delay of 30ms.
+	-- In T1_STEP_PULSE the delay is according to the CMD(1 downto 0) as follows: 
+	-- "11" = 3ms, "10" = 2ms, "01" = 12ms, "00" = 6ms.
+	-- In T1_VERIFY_DELAY there is a delay of 30ms.
+	variable DELCNT : std_logic_vector(19 downto 0);
+	begin
+		if RESETn = '0' then
+			DELCNT := (others => '0');
+		elsif CLK = '1' and CLK' event then
+			-- Reset the delay right after it occurs:
+			if DELAY = true then
+				DELCNT := (others => '0');
+			elsif DATA_AM = '1' or DDATA_AM = '1' then -- Reset in command state T2_VERIFY_AM.
+				DELCNT := (others => '0');
+			else
+				case CMD_STATE is
+					-- Time delays work on CLK edges.
+					when DELAY_15MS | T1_CHECK_DIR | T1_STEP_DELAY | T1_VERIFY_DELAY =>
+						DELCNT := DELCNT + '1';
+					-- Bit count delays work on data strobes.
+					-- Read from disk operation:
+                    when T1_SCAN_TRACK | T1_SCAN_CRC | T1_VERIFY_CRC | T2_SCAN_TRACK | T2_SCAN_SECT |
+						 T2_SCAN_LEN | T2_VERIFY_CRC_1 | T2_VERIFY_AM  | T2_FIRSTBYTE |
+						 T2_NEXTBYTE | T2_VERIFY_CRC_2 | T3_SHIFT | T3_SHIFT_ADR | T3_VERIFY_CRC =>
+						if DATA_STRB = '1' then
+							DELCNT := DELCNT + '1';
+						end if;
+					-- Write to disk operation:
+					when T2_DELAY_B2 | T2_DELAY_B8 | T2_WR_LEADIN |
+						 T2_WR_AM | T2_DELAY_B1 |T2_DELAY_B11 | T2_WR_BYTE | T2_DATALOST |
+						 T2_WR_CRC | T2_WR_FF | T3_DELAY_B3 | T3_WR_DATA | T3_DATALOST   =>
+						if DATA_STRB = '1' then
+							DELCNT := DELCNT + '1';
+						end if;
+					when others =>
+						DELCNT := (others => '0'); -- Clear the delay counter if not used.
+				end case;
+			end if;
+		end if;
+
+		case CMD_STATE is
+			when DELAY_15MS | T1_VERIFY_DELAY =>
+				case DELCNT is
+                    --when x"75300" => DELAY <= true; -- 30ms
+                    when x"3A980" => DELAY <= true; -- 15ms, thanks to L. Amsdon.
+					when others => DELAY <= false;
+				end case;
+			when T1_CHECK_DIR =>
+				if DDEn = '1' and DELCNT = x"00300" then -- 48us in FM
+					DELAY <= true;
+				elsif DDEn = '0' and DELCNT = x"00180" then -- 24us in MFM.
+					DELAY <= true;
+				else
+					DELAY <= false;
+				end if;
+			when T1_STEP_DELAY =>
+				if CMD(1 downto 0) = "11" and DELCNT >= x"0BB80" then -- 3ms
+					DELAY <= true;
+				elsif CMD(1 downto 0) = "10" and DELCNT >= x"07D00" then -- 2ms
+					DELAY <= true;
+				elsif CMD(1 downto 0) = "01" and DELCNT >= x"2EE00"  then -- 12ms
+					DELAY <= true;
+				elsif CMD(1 downto 0) = "00" and DELCNT >= x"17700" then -- 6ms
+					DELAY <= true;
+				else
+					DELAY <= false;
+				end if;			
+			when T1_SCAN_TRACK | T2_SCAN_TRACK | T2_SCAN_LEN | T2_FIRSTBYTE | T2_NEXTBYTE |
+							T2_WR_BYTE | T2_DATALOST | T2_WR_FF | T3_DATALOST | T3_SHIFT_ADR =>
+				case DELCNT is
+					when x"00008" => DELAY <= true; -- The delay in this case is 8 bit times.
+					when others => DELAY <= false;
+				end case;
+			when T1_SCAN_CRC =>
+				case DELCNT is
+                    when x"00018" => DELAY <= true; -- Scan for 3 bytes.
+					when others => DELAY <= false;
+				end case;
+			when T2_WR_AM =>
+				if DDEn = '1' and DELCNT = x"00008" then -- Wait for 8 address mark bits (FM mode).
+					DELAY <= true;
+				elsif DDEn = '0' and DELCNT = x"00020" then -- Wait for 32 sync and address mark bits (MFM mode).
+					DELAY <= true;
+				else
+					DELAY <= false;
+				end if;
+			when T2_VERIFY_AM =>
+                if DDEn = '1' and DELCNT >= x"00148" then -- FM mode.
+					DELAY <= true; -- (11+6+1)+1 = 19 Byte Times, plus 10 Byte times uncertainty.
+                elsif DDEn = '0' and DELCNT >= x"00188" then -- MFM mode.
+					DELAY <= true; -- (22+12+3+1)+1 = 39 Byte Times, plus 10 Byte times uncertainty.
+				else
+					DELAY <= false;
+				end if;
+			when T2_WR_LEADIN =>
+				if DDEn = '1' and DELCNT = x"00030" then -- Scan for 48 zero bits in FM mode.
+					DELAY <= true;
+				elsif DDEn = '0' and DELCNT = x"00060" then -- Scan for 96 zero bits in MFM mode.
+					DELAY <= true;
+				else
+					DELAY <= false;
+				end if;
+			when T2_DELAY_B1 =>
+				case DELCNT is
+					when x"00008" => DELAY <= true; -- Delay is 1 byte.
+					when others => DELAY <= false;
+				end case;
+			when T3_DELAY_B3 =>
+				case DELCNT is
+					when x"00018" => DELAY <= true; -- Delay is 3 bytes.
+					when others => DELAY <= false;
+				end case;
+			when T2_DELAY_B8 =>
+				case DELCNT is
+					when x"00040" => DELAY <= true; -- Delay is 8 bytes.
+					when others => DELAY <= false;
+				end case;
+			when T2_DELAY_B11 =>
+				case DELCNT is
+					when x"00058" => DELAY <= true; -- Delay is 11 bytes.
+					when others => DELAY <= false;
+				end case;
+			when T2_VERIFY_CRC_2 =>
+				-- In this state the original WD1772 state machine causes the CRC data to appear 1 byte
+				-- too early. The reason is the construction of the states T2_LOAD_DATA and T2_NEXTBYTE
+				-- where the length counter and the DRQ flag are serviced in T2_LOAD_DATA. Therefore the
+				-- delay is only 1 byte instead of 2.
+				case DELCNT is
+					when x"00008" => DELAY <= true; -- Scan for 2 bytes but wait only 1 byte.
+					when others => DELAY <= false;
+				end case;
+            when T1_VERIFY_CRC | T2_SCAN_SECT | T2_VERIFY_CRC_1 | T2_DELAY_B2 | T2_WR_CRC | T3_VERIFY_CRC =>
+				case DELCNT is
+            when x"00010" => DELAY <= true; -- Scan for 2 bytes (e. g. side and sector in T2_SCAN_SECT).
+					when others => DELAY <= false;
+				end case;
+			when T3_WR_DATA =>
+				if T3_DATATYPE = x"F7" and DELCNT = x"00010" then -- Wait for 16 CRC bits.
+					DELAY <= true;
+				elsif T3_DATATYPE /= x"F7" and DELCNT = x"00008" then -- Wait for 8 data bits.
+					DELAY <= true;
+				else
+					DELAY <= false;
+				end if;
+			when T3_SHIFT =>
+				case DELCNT is
+					when x"00001" => DELAY <= true; -- Scan just one data bit.
+					when others => DELAY <= false;
+				end case;
+			when others =>
+				DELAY <= false;
+			end case;
+	end process P_DELAY;
+
+	INDEX_COUNTER: process(RESETn, CLK, CMD_STATE)
+	-- This process is intended to control some command states via the index pulse behavior.
+	-- In the original WD177x there is foreseen a delay of several index pulses (about 1s). 
+	-- It is achieved by counting the index pulses of the disk. This encounters problems, 
+	-- if the disk is not inserted. For this reason there is additionally to the index counter 
+	-- a timeout which is active if there are no index pulses.
+	variable CNT : std_logic_vector(3 downto 0);
+	variable TIMEOUT : std_logic_vector(27 downto 0);
+	variable LOCK : boolean;
+	begin
+		if RESETn = '0' then
+			CNT := x"0";
+			TIMEOUT := (others => '0');
+			LOCK := false;
+		elsif CLK = '1' and CLK' event then
+			case CMD_STATE is
+				-- Be aware that there must sometimes checked several states for the presence of IPn!
+                when SPINUP | T1_SPINDOWN | T1_SCAN_TRACK | T1_SCAN_CRC | T1_VERIFY_CRC |
+                              T2_INIT | T2_SCAN_TRACK | T2_SCAN_SECT |T2_SCAN_LEN | T2_VERIFY_CRC_1 | T3_RD_ADR | T3_VERIFY_AM =>
+					if IPn = '0' and LOCK = false then -- Count the index pulses.
+						CNT := CNT + '1';
+						LOCK := true;
+					elsif IPn = '1' then
+						LOCK := false;
+					end if;
+					--
+					if TIMEOUT < x"17FFFFF" then -- Timeout of about 1.5s.
+						TIMEOUT := TIMEOUT + '1';
+					end if;
+				when others =>
+					CNT := x"0";
+					TIMEOUT := (others => '0');
+			end case;
+		end if;
+		--
+		if CMD_STATE = SPINUP and (CNT = "110" or TIMEOUT = x"17FFFFF") then -- 6 pulses or timeout.
+			INDEX_CNT <= true;
+		elsif CMD_STATE = T1_SPINDOWN and (CNT = "110" or TIMEOUT = x"17FFFFF") then -- 6 pulses or timeout.
+			INDEX_CNT <= true;
+		elsif CMD_STATE = T2_INIT and (CNT = "101" or TIMEOUT = x"17FFFFF") then -- 5 pulses or timeout.
+			INDEX_CNT <= true;
+		elsif CMD_STATE = T3_RD_ADR and (CNT = "110" or TIMEOUT = x"17FFFFF") then -- 6 pulses or timeout.
+			INDEX_CNT <= true;
+		else
+			INDEX_CNT <= false;
+		end if;
+	end process INDEX_COUNTER;
+
+	P_INDEX_MARK: process
+	-- This process controls the occurence of an index pulse during read track
+	-- and write track commands. The flag INDEX_MARK is cleared at the
+	-- beginning of these two commands during the first check for an index
+	-- pulse and is set right after the next index pulse occurs, which means
+	-- track processing has completed.
+	variable LOCK: boolean;
+	begin
+		wait until CLK = '1' and CLK' event;
+		if CMD_STATE = T3_RD_TRACK and IPn = '0' then
+			INDEX_MARK <= '0'; -- Reset the flag.
+			LOCK := true;
+		elsif CMD_STATE = T3_CHECK_INDEX_1 and IPn = '0' then
+			INDEX_MARK <= '0'; -- Reset the flag.
+			LOCK := true;
+		elsif IPn = '0' and LOCK = false then
+			INDEX_MARK <= '1'; -- Index pulse has passed.
+			LOCK := true;
+		elsif IPn = '1' then
+			LOCK := false;
+		end if;
+	end process P_INDEX_MARK;
+	
+	P_T3_DATATYPE: process(RESETn, CLK)
+	-- In type 3 write track command, it is necessary to store the information, which data
+	-- has to be written to disk (in command state T3_WR_DATA. This information is sampled
+	-- in the command state T3_LOAD_SHFT which preceeds the command state T3_WR_DATA.
+	begin
+		if RESETn = '0' then
+			T3_DATATYPE <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if CMD_STATE = T3_LOAD_SHFT then
+				T3_DATATYPE <= DR;
+			end if;
+		end if;
+	end process P_T3_DATATYPE;
+	
+	CNT_T3BYTES: process(RESETn, CLK, CMD_STATE)
+	-- This process counts the bytes read in the type III read address
+	-- command during the command states T3_SHIFT_ADR, T3_LOAD_DATA2,
+	-- T3_SET_DRQ_2 and T3_CHECK_RD.
+	variable CNT 	: std_logic_vector(2 downto 0);
+	begin
+		if RESETn = '0' then
+			CNT := "000";
+		elsif CLK = '1' and CLK' event then
+			case CMD_STATE is
+				when T3_VERIFY_AM =>
+					CNT := "000"; -- Clear the counter right befor the count operation.
+				when T3_SET_DRQ_2 =>
+					CNT := CNT + '1'; -- Increment after each read cycle.
+				when others =>
+					null;
+			end case;
+		end if;
+		case CNT is
+			when "100" => T3_TRADR <= true;
+			when others => T3_TRADR <= false;
+		end case;
+	end process CNT_T3BYTES;
+
+	BYTEASMBLY: process(RESETn, CLK)
+	-- This process controls the condition in the CMD_STATE T3_CHECK_DR.
+	-- Therefore the bits shifted into the DSR in command state T3_SHIFT are counted.
+	-- The count condition is entering the command state T3_CHECK_INDEX_3. The clear
+	-- condition is either the command state IDLE or the command state T3_CHECK_DR.
+	variable CNT : std_logic_vector(3 downto 0);
+	begin
+		if RESETn = '0' then
+			CNT := x"0";
+		elsif CLK = '1' and CLK' event then
+			case CMD_STATE is
+				when IDLE => CNT := x"0";
+				when T3_CHECK_INDEX_3 => CNT := CNT + '1';
+				when T3_CHECK_DR => CNT := (others => '0');
+				when others => null;
+			end case;
+		end if;
+		case CNT is
+			when x"8" => BYTE_RDY <= true;
+			when others => BYTE_RDY <= false;
+		end case;
+	end process BYTEASMBLY;
+
+	P_DIR: process(RESETn, CLK, DIR)
+	-- This portion of code is responsible to control the right stepping
+	-- direction in type I commands.
+	begin
+		if RESETn = '0' then
+			DIR <= '0';
+		elsif CLK = '1' and CLK' event then
+			if CMD_STATE = DECODE and CMD(7 downto 5) = "010" then -- Step in.
+				DIR <= '1';
+			elsif CMD_STATE = DECODE and CMD(7 downto 5) = "011" then -- Step out.
+				DIR <= '0';
+			elsif CMD_STATE = T1_COMP_TR_DSR and DSR > TR then -- Seek.
+				DIR <= '1';
+			elsif CMD_STATE = T1_COMP_TR_DSR and DSR < TR then -- Seek.
+				DIR <= '0';
+			end if;
+		end if;
+		DIRC <= DIR; -- Copy signal to the output.
+	end process P_DIR;
+
+	P_DRQ: process(RESETn, CLK, DRQ_I)
+	begin
+		if RESETn = '0' then
+			DRQ_I <= '0';
+		elsif CLK = '1' and CLK' event then
+			case CMD_STATE is
+				when INIT =>
+					DRQ_I <= '0';
+				when T2_LOAD_DATA | T2_SET_DRQ | T2_LOAD_SHFT =>
+					DRQ_I <= '1';
+				when T3_WR | T3_LOAD_SHFT | T3_SET_DRQ_1 | T3_SET_DRQ_2 =>
+					DRQ_I <= '1';
+				when others =>
+					null;
+			end case;
+			-- The data request bit is also cleared by reading or writing the
+			-- data register (direct memory access operation).
+			if (DATA_RD = true or DATA_WR = true) then
+				DRQ_I <= '0';
+			end if;
+		end if;
+		--
+        DRQ <= DRQ_I; -- Copy to entity.
+		--
+	end process P_DRQ;
+
+	-- The DRQ_IPn detects the index pulse during type I commands and a forced interrupt or 
+	-- DRQ during type II and III commands.
+	-- The index pulse flag is active high and can be used for the detection of an inserted disk.
+	DRQ_IPn <=  not IPn when CMD(7) = '0' else
+				not IPn when CMD(7 downto 4) = x"D" and BUSY = '0' else DRQ_I;
+
+	P_BUSY: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			BUSY <= '0';
+		elsif CLK = '1' and CLK' event then
+			-- During forced interrupt, the busy flag is reset when the command
+			-- state machine enters the IDLE state.
+			if CMD_STATE = INIT then
+				BUSY <= '1'; -- set BUSY flag for all command types I ... III.
+			elsif CMD_STATE = IDLE then
+				BUSY <= '0'; -- Reset BUSY after entering IDLE in any case.
+			end if;
+		end if;
+	end process P_BUSY;
+
+	P_SEEK_RNF: process(RESETn, CLK)
+	-- Seek error or record not found error flag.
+	begin
+		if RESETn = '0' then
+			SEEK_RNF <= '0';
+		elsif CLK = '1' and CLK' event then
+			if CMD_STATE = INIT then
+				SEEK_RNF <= '0'; -- Clear the flag for all command types I ... III.
+			elsif CMD_STATE = T1_TRAP and STEP_TRAP = true then
+				SEEK_RNF <= '1'; -- Seek error (SEEK).
+			elsif CMD_STATE = T1_SPINDOWN and INDEX_CNT = true then
+				SEEK_RNF <= '1'; -- Seek error (SEEK).
+			elsif CMD_STATE = T2_INIT and INDEX_CNT = true then
+				SEEK_RNF <= '1'; -- Record not found (RNF).
+			elsif CMD_STATE = T3_RD_ADR and INDEX_CNT = true then
+				SEEK_RNF <= '1'; -- Record not found (RNF).
+			end if;
+		end if;
+	end process P_SEEK_RNF;
+
+	P_INTRQ: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			INTRQ <= '0';
+		elsif CLK = '1' and CLK' event then
+			-- Interrupt reset conditions:
+			if STAT_RD = true and CMD /= x"D8" then
+				-- No clear during immediately forced interrupt.
+				INTRQ <= '0'; -- Clear the flag when status register is read.
+			elsif CMD_WR = true and CMD = x"D0" then
+				-- Clear with the next write access to the command register after the
+				-- forced interrupt x"D0" was written.
+				INTRQ <= '0';
+			elsif CMD_STATE = INIT and CMD(7 downto 6) /= "11" then
+				INTRQ <= '0'; -- Clear the flag for type I and type II commands during start of execution.
+            -- Interrupt set conditions.
+			elsif CMD = x"D8" and CMD_STATE = IDLE then
+				INTRQ <= '1'; -- Force interrupt immediately (after the break took affect).
+			elsif CMD = x"D4" and IPn = '0' and CMD_STATE = IDLE then
+				INTRQ <= '1'; -- Force interrupt on next index pulse (after the break took affect).
+			elsif CMD_STATE = T1_TRAP and STEP_TRAP = true then
+				INTRQ <= '1'; -- Indicate interrupt request due to seek error.
+			elsif CMD_STATE = T1_VERIFY_DELAY and CMD(2) = '0' then
+				INTRQ <= '1'; -- Indicate interrupt: command finished or interrupted.
+			elsif CMD_STATE = T1_SPINDOWN and INDEX_CNT = true then
+				INTRQ <= '1'; -- Indicate interrupt request, reason: seek error.
+			elsif CMD_STATE = T1_VERIFY_CRC and CRC_ERR = '0' then
+				INTRQ <= '1'; -- Indicate interrupt request; command correct, no CRC error.
+			elsif CMD_STATE = T2_RD_WR_SECT and CMD(7 downto 5) = "101" and WPRTn = '0' then
+				INTRQ <= '1'; -- Indicate interrupt request because disk is write protected.
+			elsif CMD_STATE = T2_INIT and INDEX_CNT = true then
+				INTRQ <= '1'; -- Indicate interrupt request, reason: timeout.
+			elsif CMD_STATE = T2_VERIFY_CRC_2 and DELAY = true and CRC_ERR = '1' then
+				INTRQ <= '1'; -- Indicate interrupt request due to CRC error.
+			elsif CMD_STATE = T2_MULTISECT and CMD(4) = '0' then
+				INTRQ <= '1'; -- Indicate interrupt request, command correct finished.
+			elsif CMD_STATE = T2_VERIFY_DRQ_2 and DRQ_I = '1' then
+				INTRQ <= '1'; -- Indicate interrupt request, reason: lost data.
+			elsif CMD_STATE = T3_WR and WPRTn = '0' then
+				INTRQ <= '1'; -- Indicate interrupt request, reason: disk is write protected.
+			elsif CMD_STATE = T3_VERIFY_DRQ and DRQ_I = '1' then
+				INTRQ <= '1'; -- Indicate interrupt request due to lost data.
+			elsif CMD_STATE = T3_CHECK_INDEX_2 and INDEX_MARK = '1' then
+				INTRQ <= '1'; -- Indicate interrupt request, reason: command finished correctly.
+            elsif CMD_STATE = T3_CHECK_INDEX_3 and INDEX_MARK = '1' then
+				INTRQ <= '1'; -- Indicate interrupt request, reason: command finished correctly.
+			elsif CMD_STATE = T3_RD_ADR and INDEX_CNT = true then
+				INTRQ <= '1'; -- Indicate interrupt request because record was not found.
+			elsif CMD_STATE = T3_VERIFY_CRC then
+				INTRQ <= '1'; -- Indicate interrupt request; command finished with or without CRC error.
+			end if;
+		end if;
+	end process P_INTRQ;
+
+	P_LOST_DATA_TR00: process(RESETn, CLK)
+	-- Logic for the status bit number 2:
+	-- The TRACK00 flag is used to detect wether a floppy disk drive
+	-- is connected or not.
+	begin
+		if RESETn = '0' then
+			LOST_DATA_TR00 <= '0';
+		elsif CLK = '1' and CLK' event then
+			if CMD(7 downto 4) = x"D" and BUSY = '0' then -- Forced interrupt.
+				LOST_DATA_TR00 <= not TRACK00n;
+			elsif CMD_STATE = INIT then
+				LOST_DATA_TR00 <= '0';
+            elsif CMD_STATE = T1_VERIFY_DELAY then
+				LOST_DATA_TR00 <= not TRACK00n;
+			elsif CMD_STATE = T2_VERIFY_DRQ_1 and DRQ_I = '1' then
+				LOST_DATA_TR00 <= '1';
+			elsif CMD_STATE = T2_VERIFY_DRQ_2 and DRQ_I = '1' then
+				LOST_DATA_TR00 <= '1';
+			elsif CMD_STATE = T2_VERIFY_DRQ_3 and DRQ_I = '1' then
+				LOST_DATA_TR00 <= '1';
+			elsif CMD_STATE = T3_VERIFY_DRQ and DRQ_I = '1' then
+				LOST_DATA_TR00 <= '1';
+			elsif CMD_STATE = T3_DATALOST then
+				LOST_DATA_TR00 <= '1';
+			elsif CMD_STATE = T3_CHECK_DR and DRQ_I = '1' then
+				LOST_DATA_TR00 <= '1';
+			end if;
+		end if;
+	end process P_LOST_DATA_TR00;
+
+	MOTORSWITCH: process(RESETn, CLK)
+	variable INDEXCNT	: std_logic_vector(3 downto 0);
+	variable LOCK		: boolean;
+	begin
+		if RESETn = '0' then
+			MO <= '0';
+			INDEXCNT := x"0";
+			LOCK := false;
+		elsif CLK = '1' and CLK' event then
+			if CMD_STATE /= IDLE then
+				INDEXCNT := x"9"; -- Initialise the index counter.
+				LOCK := false;
+			elsif LOCK = false and IPn = '0' and INDEXCNT > x"0" then
+				INDEXCNT := INDEXCNT - '1'; -- Count the index pulses in the IDLE state.
+				LOCK := true;
+			elsif IPn = '1' then
+				LOCK := false;
+			end if;
+            --
+            if CMD_STATE = INIT and CMD_WR = false then
+				MO <= '1'; -- Start the motor for all command types I ... III in this state.
+			elsif INDEXCNT = x"0" then
+				MO <= '0'; -- The motor stops after 9 index pulses in idle state.
+			end if;
+		end if;
+	end process MOTORSWITCH;
+
+	WRITE_PROTECT: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			WR_PR <= '0';
+		elsif CLK = '1' and CLK' event then
+			if CMD_STATE = INIT and CMD(7) = '1' then
+				WR_PR <= '0'; -- Clear the flag for type II and type III  commands.
+			elsif CMD_STATE = T2_RD_WR_SECT and WPRTn = '0' then
+				WR_PR <= '1';
+			elsif CMD_STATE = T3_WR and WPRTn = '0' then
+				WR_PR <= '1';
+			end if;
+		end if;
+	end process WRITE_PROTECT;
+
+	RECTYPE_SPINUP: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SPINUP_RECTYPE <= '0';
+		elsif CLK = '1' and CLK' event then
+			if CMD_STATE = INIT then
+				SPINUP_RECTYPE <= '0'; -- Clear the flag for type II...III  commands.
+			elsif CMD_STATE = SPINUP and CMD(7) = '0' and INDEX_CNT = true then
+				SPINUP_RECTYPE <= '1'; -- SPINUP SEQUENCE for type I commands has finished.
+			elsif CMD_STATE = T2_VERIFY_AM and (DATA_AM = '1' or DDATA_AM = '1') then
+				case DSR is
+					when x"F8" => SPINUP_RECTYPE <= '1'; -- Deleted data address mark.
+					when x"FB" => SPINUP_RECTYPE <= '0'; -- Normal data address mark.
+					when others => null; -- Forbidden, should never appear.
+				end case;
+			end if;
+		end if;
+	end process RECTYPE_SPINUP;
+
+	WRITEGATE: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			WG <= '0';
+		elsif CLK = '1' and CLK' event then
+			case CMD_STATE is
+				when T2_WR_LEADIN | T3_LOAD_SHFT =>
+					WG <= '1';
+				when T2_MULTISECT | IDLE =>
+					WG <= '0';
+				when others =>
+					null;
+			end case;
+		end if;
+	end process WRITEGATE;
+
+	RESTORE_TRAP: process(RESETn, CLK)
+	-- This process is responsible to supervise the RESTORE command.
+	-- If after 255 stepping pulses no TRACK00n was not detected, the
+	-- RESTORE command is terminated and the interrupt request and the
+	-- seek error are set.
+	variable STEP_CNT : std_logic_vector(7 downto 0);
+	begin
+		if RESETn = '0' then
+			STEP_CNT := (others => '0');
+		elsif CLK = '1' and CLK' event then
+			if CMD_STATE = IDLE then
+				STEP_CNT := x"00";
+			elsif CMD(7 downto 4) /= "0000" then -- No RESTORE command.
+				STEP_CNT := x"00";
+			elsif CMD_STATE = T1_STEP and STEP_CNT < x"FF" then
+				STEP_CNT := STEP_CNT + '1';
+			end if;
+		end if;
+		--
+		case STEP_CNT is
+			when x"FF" => STEP_TRAP <= true;
+			when others => STEP_TRAP <= false;
+		end case;
+	end process RESTORE_TRAP;
+
+	STEPPULSE: process(RESETn, CLK)
+	-- The step pulse duration is in the original WD1772 4us in MFM mode and 8 us.
+	-- in FM mode This process is responsible to provide the correct pulse lengths.
+	variable CNT : std_logic_vector(7 downto 0);
+	begin
+		if RESETn = '0' then
+			CNT := (others => '0');
+		elsif CLK = '1' and CLK' event then
+			if CMD_STATE = T1_STEP then
+				case DDEn is
+					when '1' => CNT := x"80"; --Start counter for FM step pulse.
+                    when '0' => CNT := x"40"; --Start counter for MFM step pulse.
+				end case;
+			elsif CNT > x"00" then
+				CNT := CNT -1; -- Count 63 or 127 CLK cycles ...
+			end if;
+			case CNT is
+				when x"00" => STEP <= '0';
+				when others => STEP <= '1'; --...result in 3.875us or 7.75us pulse.
+			end case;
+		end if;
+	end process STEPPULSE;
+
+	TRACK_MEM: process(RESETn, CLK, TRACKMEM)
+	-- This process is necessary to store the actual track number in the
+	-- type III command 'read address' because the track number is written
+	-- to the sector register some byte times after the detection of the 
+	-- track number from disk.
+	begin
+		if RESETn = '0' then
+			TRACKMEM <= x"00";
+		elsif CLK = '1' and CLK' event then
+			case CMD_STATE is
+				when IDLE =>
+					TRACKMEM <= x"00"; -- Clear the Track memory.
+				when T3_LOAD_DATA_2 =>
+					TRACKMEM <= DSR; -- Store the actual track number.
+				when others =>
+					null;
+			end case;
+		end if;
+		TRACK_NR <= TRACKMEM; -- Output the TRACKMEM.
+	end process TRACK_MEM;
+
+	SECT_LENGTH: process(RESETn, CLK, SECT_LEN)
+	-- This process supervises the read sector and write sector
+	-- commands. If the sector read or write are equal to the
+	-- sector length, the commands read sector and write sector
+	-- are ready.
+	begin
+		if RESETn = '0' then
+			SECT_LEN <= "00000000000";
+		elsif CLK = '1' and CLK' event then
+			case CMD_STATE is
+				when T2_SCAN_LEN =>
+					-- Bring in the correct sector length.
+					case DSR(1 downto 0) is
+						when "00" => SECT_LEN <= "00010000000"; -- 128 Byte per sector.
+						when "01" => SECT_LEN <= "00100000000"; -- 256 Byte per sector.
+						when "10" => SECT_LEN <= "01000000000"; -- 512 Byte per sector.
+						when "11" => SECT_LEN <= "10000000000"; -- 1024 Byte per sector.
+						when others => SECT_LEN <= "10000000000"; -- Dummy for U, X, Z, W, H, L, -.
+					end case;
+				when T2_LOAD_DATA | T2_LOAD_SHFT =>
+					SECT_LEN <= SECT_LEN - '1';
+				when others =>
+					null;
+			end case;
+		end if;
+	end process SECT_LENGTH;
+
+	P_CRC_ERR: process(RESETn, CLK)
+	-- This code checks the CRC status in the right command states
+	-- and sets or resets the CRC error status flag.
+	begin
+		if RESETn = '0' then
+			CRC_ERRFLAG <= '0';
+		elsif CLK = '1' and CLK' event then
+			case CMD_STATE is
+				when INIT =>
+					if CMD(7) = '0' then
+						CRC_ERRFLAG <= '0'; -- Reset for type I commands only.
+					end if;
+				when T1_VERIFY_CRC | T2_VERIFY_CRC_1  =>
+					if CRC_ERR = '1' and DELAY = true then
+						CRC_ERRFLAG <= '1'; -- Set CRC error flag...
+					elsif CRC_ERR = '0' and DELAY = true then
+						CRC_ERRFLAG <= '0'; -- ... or reset CRC error flag.
+					end if;
+				when T2_VERIFY_CRC_2 | T3_VERIFY_CRC =>
+					if CRC_ERR = '1' and DELAY = true then
+						-- Set CRC error flag but no reset in here.
+						-- The CRC is already reset by the previous checks.
+						CRC_ERRFLAG <= '1';
+					end if;
+				when others =>
+					null;
+			end case;
+		end if;
+	end process P_CRC_ERR;
+
+    CMD_WR <= true when CSn = '0' and A1 = '0' and A0 = '0' and RWn = '0' else false; -- Command register write.
+	STAT_RD <= true when CSn = '0' and A1 = '0' and A0 = '0' and RWn = '1' else false; -- Status register read.
+	DATA_WR <= true when CSn = '0' and A1 = '1' and A0 = '1' and RWn = '0' else false; -- Data register write.
+	DATA_RD <= true when CSn = '0' and A1 = '1' and A0 = '1' and RWn = '1' else false; -- Data register read.
+
+	-- Track register arithmetics controls:
+	TR_PRES <= '1' when CMD_STATE = T1_SEEK_RESTORE and CMD(7 downto 4) = "0000" else '0'; -- Restore command.
+	TR_CLR 	<= '1' when CMD_STATE = T1_HEAD_CTRL and TRACK00n = '0' and DIR = '0' else '0';
+	TR_INC	<= '1' when CMD_STATE = T1_CHECK_DIR and DELAY = true and DIR = '1' else '0';
+	TR_DEC	<= '1' when CMD_STATE = T1_CHECK_DIR and DELAY = true and DIR = '0' else '0';
+
+	-- Sector register arithmetics:
+	SR_INC	<= '1' when CMD_STATE = T2_MULTISECT and CMD(4) = '1' else '0'; -- Multi sector enabled.
+	SR_LOAD <= '1' when CMD_STATE = T3_LOAD_SR else '0';
+
+	-- Data register arithmetics controls:
+	DR_CLR 	<= 	'1' when CMD_STATE = T1_SEEK_RESTORE and CMD(7 downto 4) = "0000" else '0'; -- Restore command.
+	DR_LOAD <= 	'1' when CMD_STATE = T2_LOAD_DATA else
+				'1' when CMD_STATE = T3_LOAD_DATA_1 else
+				'1' when CMD_STATE = T3_LOAD_DATA_2 else '0';
+	
+	-- Shift register arithmetics controls:
+	-- During type I and type II commands all characters are allowed as data.
+	-- During the type III write track command, there are some special characters
+	-- which may not appear as normal data. See the register file for more information.
+	SHFT_LOAD_SD <= '1' when CMD_STATE = T3_LOAD_SHFT else '0'; -- Special data.
+	SHFT_LOAD_ND <= '1' when CMD_STATE = T1_LOAD_SHFT else 
+				 	'1' when CMD_STATE = T2_LOAD_SHFT else '0'; -- Normal data.
+	
+	P_CRC_PRES: process(RESETn, CLK)
+	-- CRC preset during write sector and write track commands.
+	variable LOCK : boolean;
+	begin
+		if RESETn = '0' then
+			CRC_PRES <= '0';
+			LOCK := false;
+		elsif CLK = '1' and CLK' event then
+			-- In write track command, the CRC is initialised at the beginning of the
+			-- first A1 data and released during shifting the CRC out.
+			if CMD_STATE = T2_WR_AM and LOCK = false then
+				CRC_PRES <= '1'; -- Write sector command.
+				LOCK := true;
+			elsif CMD_STATE = T3_LOAD_SHFT and DR = x"F5" and LOCK = false then -- x"F5" means write A1.
+				CRC_PRES <= '1'; -- Write track command.
+				LOCK := true;
+			elsif CMD_STATE = T2_WR_CRC then
+				CRC_PRES <= '0'; -- Write sector command.
+				LOCK := false;
+			elsif CMD_STATE = T3_LOAD_SHFT and DR = x"F7" then
+				CRC_PRES <= '0'; -- Write track command.
+				LOCK := false;
+			else
+				CRC_PRES <= '0';
+			end if;
+		end if;
+	end process P_CRC_PRES;
+	
+	-- Write control signals:
+	AM_2_DISK <= 	'1' when CMD_STATE = T2_WR_AM else '0';
+	FF_2_DISK <= 	'1' when CMD_STATE = T2_WR_FF else '0';
+	DSR_2_DISK <= 	'1' when CMD_STATE = T2_WR_BYTE else
+					'1' when CMD_STATE = T3_WR_DATA and T3_DATATYPE /= x"F7" else '0'; -- not during CRC.
+	CRC_2_DISK <= 	'1' when CMD_STATE = T2_WR_CRC else 
+					'1' when CMD_STATE = T3_WR_DATA and T3_DATATYPE = x"F7" else '0';
+
+	-- Write precompensation control:
+	PRECOMP_EN <= 	'1' when CMD(7 downto 4) = x"A" and CMD(1) = '0' else -- Write single sector.
+					'1' when CMD(7 downto 4) = x"B" and CMD(1) = '0' else -- Write multiple sector.
+					'1' when CMD(7 downto 4) = x"F" and CMD(1) = '0' else '0'; -- Write track.
+
+	-- Disk data flow direction:
+	DISK_RWn <= -- Write sector command:
+				'0' when CMD_STATE = T2_WR_LEADIN else
+				'0' when CMD_STATE = T2_WR_AM else
+				'0' when CMD_STATE = T2_LOAD_SHFT else
+				'0' when CMD_STATE = T2_WR_BYTE else
+				'0' when CMD_STATE = T2_VERIFY_DRQ_3 else
+				'0' when CMD_STATE = T2_DATALOST else
+				'0' when CMD_STATE = T2_WRSTAT else
+				'0' when CMD_STATE = T2_WR_CRC else
+				'0' when CMD_STATE = T2_WR_FF else
+				-- Write track command:
+				'0' when CMD_STATE = T3_LOAD_SHFT else
+				'0' when CMD_STATE = T3_WR_DATA else
+				'0' when CMD_STATE = T3_CHECK_INDEX_2 else
+				'0' when CMD_STATE = T3_DATALOST else '1';
+end BEHAVIOR;
\ No newline at end of file
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
new file mode 100644
index 0000000..54b2060
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
@@ -0,0 +1,162 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WD1772 compatible floppy disk controller IP Core.            ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Floppy disk controller with all features of the Western      ----
+---- Digital WD1772-02 controller.                                ----
+----                                                              ----
+---- The CRC cyclic redundancy checker unit. Further description  ----
+---- see below.                                                   ----
+----                                                              ----
+---- Working principle of the CRC generator and verify unit:      ----
+---- During read operation:                                       ----
+---- The CRC generator is switched on via after the detection of  ----
+---- the address ID of the data ID mark. The CRC generation last  ----
+---- in case of the address ID until the lenght byte is read.     ----
+---- In case of generation after the data address mark the CRC    ----
+---- generator is activated until the last data byte is read.     ----
+---- The number of data bytes to be read depends on the LENGHT    ----
+---- information in the header file. After generation of the CRC  ----
+---- the CRC_GEN is switched off and the VERIFY procedure begins  ----
+---- by activating CRC_VERIFY. The previously generated CRC is    ----
+---- then compared (serially) with the two consecutive read CRC   ----
+---- bytes. The CRC error appeas, when the comparision fails.     ----
+---- During write operation:                                      ----
+---- The CRC generator is switched on via after the detection of  ----
+---- the address ID of the data ID mark. The CRC generation last  ----
+---- in case of the address ID until the lenght byte is read.     ----
+---- In case of generation after the data address mark the CRC    ----
+---- generator is activated until the last data byte is read.     ----
+---- The number of data bytes to be read depends on the LENGHT    ----
+---- information in the header file. After the generation of the  ----
+---- two CRC bytes, the write out process begins by activating    ----
+---- CRC_SHFTOUT. The CRC data appears in this case serially on   ----
+---- the CRC_SDOUT.                                               ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2006A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/05 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K9A  2009/06/20 WF
+--   CRC_SHIFT has now synchronous reset to meeet preset behaviour.
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF1772IP_CRC_LOGIC is
+	port(
+		-- System control
+		CLK				: in bit;
+		RESETn			: in bit;
+		DISK_RWn		: in bit;
+
+		-- Preset controls:
+		DDEn		: in bit;
+		ID_AM		: in bit;
+		DATA_AM		: in Bit;
+		DDATA_AM	: in Bit;
+		
+		-- CRC unit:
+		SD			: in bit; -- Serial data input.
+		CRC_STRB	: in bit; -- Data strobe.
+		CRC_2_DISK	: in bit; -- Forces the unit to flush the CRC remainder.
+		CRC_PRES	: in bit; -- Presets the CRC unit during write to disk.
+		CRC_SDOUT	: out bit; -- Serial data output.
+		CRC_ERR		: out bit -- Indicates CRC error.
+	);
+end WF1772IP_CRC_LOGIC;
+
+architecture BEHAVIOR of WF1772IP_CRC_LOGIC is
+signal CRC_SHIFT	: bit_vector(15 downto 0);
+begin
+	P_CRC: process
+	-- The shift register is initialised with appropriate values in HD or DD mode.
+	-- In theory the shift register should be preset to ones. Due to a latency of one byte 
+	-- in FM mode or 4 bytes in MFM mode it is necessary to preset the shift register with 
+	-- the CRC values of this ID address mark, data address mark and the A1 sync bytes. The 
+	-- latency is caused by the addressmark detector which needs one or 4 byte time(s) for 
+	-- detection. The CRC unit therefore starts with every detection of an address mark and
+	-- ends if the CRC unit is flushed.
+	begin 
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' then
+			CRC_SHIFT <= (others => '1');
+		elsif CRC_2_DISK = '1' then
+			if CRC_STRB = '1' then
+				CRC_SHIFT <= CRC_SHIFT(14 downto 0) & '0';
+			end if;
+		elsif CRC_PRES = '1' then -- Preset during write sector or write track command.
+			CRC_SHIFT <= x"FFFF";
+		elsif DDEn = '1' and ID_AM = '1' then -- DD mode and ID address mark detected.
+			CRC_SHIFT <= x"EF21"; -- The CRC-CCITT for data x"FE" is x"EF21"
+		elsif DDEn = '1' and DATA_AM = '1' then -- DD mode and data address mark detected.
+			CRC_SHIFT <= x"BF84"; -- The CRC-CCITT for data x"FB" is x"BF84"
+		elsif DDEn = '1' and DDATA_AM = '1' then -- DD mode and deleted data address mark detected.
+			CRC_SHIFT <= x"8FE7"; -- The CRC-CCITT for data x"F8" is x"8FE7"
+		elsif DDEn = '0' and ID_AM = '1' then -- HD mode and ID address mark detected.
+			CRC_SHIFT <= x"B230"; -- The CRC-CCITT for data x"A1A1A1FE" is x"B230"
+		elsif DDEn = '0' and DATA_AM = '1' then -- HD mode and data address mark detected.
+			CRC_SHIFT <= x"E295"; -- The CRC-CCITT for data x"A1A1A1FB" is x"E295"
+		elsif DDEn = '0' and DDATA_AM = '1' then -- HD mode and deleted data address mark detected.
+			CRC_SHIFT <= x"D2F6"; -- The CRC-CCITT for data x"A1A1A1F8" is x"D2F6"
+		elsif CRC_STRB = '1' then
+			-- CRC-CCITT (xFFFF):
+			-- the polynomial is G(x) = x^16 + x^12 + x^5 + 1
+			-- In this mode the CRC is encoded. In read from disk mode, the encoding works as CRC
+			-- verification. In this operating condition the ID or the data field is compared 
+			-- against the CRC checksum. if there are no errors, the shift register's value is 
+			-- x"0000" after the last bit of the checksum is shifted in. In write to disk mode the
+			-- CRC linear feedback shift register (lfsr) works to generate the CRC remainder of the
+			-- ID or data field.
+			CRC_SHIFT <= CRC_SHIFT(14 downto 12) & (CRC_SHIFT(15) xor CRC_SHIFT(11) xor SD) &
+						 CRC_SHIFT(10 downto 5) & (CRC_SHIFT(15) xor CRC_SHIFT(4) xor SD) &
+						 CRC_SHIFT(3 downto 0) & (CRC_SHIFT(15) xor SD);
+		end if;
+	end process P_CRC;
+
+	CRC_SDOUT <= CRC_SHIFT(15);
+    CRC_ERR <= '0' when CRC_SHIFT = x"0000" else '1';
+end architecture BEHAVIOR;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
new file mode 100644
index 0000000..95ce08c
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
@@ -0,0 +1,426 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WD1772 compatible floppy disk controller IP Core.            ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Floppy disk controller with all features of the Western      ----
+---- Digital WD1772-02 controller.                                ----
+----                                                              ----
+---- The digital PLL is responsible to detect the incoming serial ----
+---- data stream and provide a system clock synchronous signal    ----
+---- containing the data and clock information.                   ----
+---- To understand how the code works in detail refer to the free ----
+---- US patent no. 4,780,844.                                     ----
+----                                                              ----
+---- Attention: The settings for TOP and BOTTOM, which control    ----
+---- the PLL frequency and for PHASE_CORR which control the PLL   ----
+---- phase are rather critical for a good read condition! To test ----
+---- the PLL in the WD1772 compatible core do the following:      ----
+---- Sample on an oscilloscope on one channel the falling edge of ----
+---- the RDn pulse and on the other channel the PLL_DSTRB. The    ----
+---- RDn must be located exactly between the PLL_DSTRB pulses.    ----
+---- Otherwise, the parameters TOP, BOTTOM and PHASE_CORR have to ----
+---- be optimized.                                                ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2006A  2006/06/03 WF
+--   Initial Release: the MFM portion for HD and DD floppies is tested.
+--   The FM mode (DDEn = '1') is not completely tested due to lack of FM
+--   drives.
+-- Revision 2K6B  2006/11/05 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K7B  2006/12/29 WF
+--   Introduced several improvements based on a very good examination
+--   of the pll code by Jean Louis-Guerin.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K8B  2008/12/24 WF
+--   Improvement of the INPORT process.
+--   Bugfix of the FREQ_AMOUNT counter: now stops if its value is zero.
+--   Several changes concerning the PLL parameters to improve the
+--     stability of the PLL.
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF1772IP_DIGITAL_PLL is
+	generic(
+		-- The valid range of the period counter of the PLL is given by the TOP and BOTTOM 
+		-- limits. The counter range is therefore BOTTOM <= counter value <= TOP.
+		-- The generic PHASE_CORR is responsible fo the center setting of PLL_DSTRB concerning
+		-- the RDn period.
+		-- The nominal frequency setting is 128. So it is recommended to use TOP and BOTTOM
+		-- settings symmetrically around 128. If TOP = BOTTOM = 128, the frequency control 
+        -- is disabled. TOP + PHASE_CORR may not exceed a value of 255. BOTTOM - PHASE_CORR
+        -- may not drop below zero.
+        TOP			: integer range 0 to 255 := 152; -- +18.0%
+        BOTTOM		: integer range 0 to 255 := 104; -- -18.0%
+        PHASE_CORR	: integer range 0 to 128 := 75
+	);
+	port(
+		-- System control
+		CLK		: in bit; -- 16MHz clock.
+		RESETn	: in bit;
+
+		-- Controls
+		DDEn		: in bit; -- Double density enable.
+		HDTYPE		: in bit; -- This control is '1' when HD disks are inserted.
+		DISK_RWn	: in bit; -- Read write control.
+
+		-- Data and clock lines
+		RDn			: in bit; -- Read signal from the disk.
+		PLL_D		: out bit; -- Synchronous read signal.
+		PLL_DSTRB	: out bit -- Read strobe.
+	);
+end WF1772IP_DIGITAL_PLL;
+
+architecture BEHAVIOR of WF1772IP_DIGITAL_PLL is
+signal RD_In				: bit;
+signal UP, DOWN				: bit;
+signal PHASE_DECREASE		: bit;
+signal PHASE_INCREASE		: bit;
+signal HI_STOP, LOW_STOP	: bit;
+signal PER_CNT				: std_logic_vector(7 downto 0);
+signal ADDER_IN				: std_logic_vector(7 downto 0);
+signal ADDER_MSBs			: bit_vector(2 downto 0);
+signal RD_PULSE				: bit;
+signal ROLL_OVER			: bit;
+signal HISTORY_REG			: bit_vector(1 downto 0);
+signal ERROR_HISTORY		: integer range 0 to 2;
+begin
+	INPORT: process
+	-- This process is necessary due to the poor quality of the rising
+	-- edge of RDn. Let it work on the negative clock edge.
+	begin
+        wait until CLK = '0' and CLK' event;
+         RD_In <= RDn;
+	end process INPORT;
+
+	EDGEDETECT: process(RESETn, CLK)
+    -- This process forms a falling edge detector for the incoming
+	-- data read port. The output (RD_PULSE) goes high for exactly
+	-- one clock period after the RDn is low and the positive
+	-- clock edge is detected.
+	variable LOCK : boolean;
+	begin
+		if RESETn = '0' then
+			RD_PULSE <= '0';
+			LOCK := false;
+        elsif CLK = '1' and CLK' event then
+			if DISK_RWn = '0' then -- Disable detector in write mode.
+				RD_PULSE <= '0';
+            elsif RD_In = '0' and LOCK = false then
+				RD_PULSE <= '1'; -- READ_PULSE is inverted against RDn
+				LOCK := true;
+            elsif RD_In = '1' then
+				LOCK := false;
+				RD_PULSE <= '0';
+			else
+				RD_PULSE <= '0';
+			end if;
+		end if;
+	end process EDGEDETECT;
+
+	PERIOD_CNT: process(RESETn, CLK)
+	-- This process provides the nominal variable added to the adder. To achieve a good 
+    -- settling time of the PLL in all cases, the period counter is controlled via the DDEn
+    -- and HDTYPE flags respective to its added value. Be aware, that in case of adding "10"
+    -- or "11", the TOP value may be exceeded or the period counter may drop below the BOTTOM
+	-- value. The higher the value added, the faster will be the settling time of phase locked
+	-- loop .
+	begin
+		if RESETn = '0' then
+			PER_CNT <= "10000000"; -- Initial value is 128.
+		elsif CLK = '1' and CLK' event then
+            if UP = '1' then
+                PER_CNT <= PER_CNT + '1';
+            elsif DOWN = '1' then
+                PER_CNT <= PER_CNT - '1';
+			end if;
+		end if;
+	end process PERIOD_CNT;
+
+    HI_STOP <= 	'1' when PER_CNT >= TOP else '0';
+    LOW_STOP <= '1' when PER_CNT <= BOTTOM else '0';
+
+	ADDER_IN <= -- This DISK_RWn = '0' implementation keeps the last phase information
+				-- of the PLL in read from disk mode. It should be a good solution concer-
+				-- ning alternative read write cycles.
+				"10000000" when DISK_RWn = '0' else -- Nominal value for write to disk. 
+                PER_CNT + PHASE_CORR when PHASE_INCREASE = '1' else -- Phase lags.
+                PER_CNT - PHASE_CORR when PHASE_DECREASE = '1' else -- Phase leeds.
+				PER_CNT; -- No phase correction;
+
+	ADDER: process(RESETn, CLK, DDEn, HDTYPE)
+	-- Clock adjustment: The clock cycle is 62.5ns for the 16MHz system clock. 
+	-- The offset (LSBs) of the adder input is chosen to be conform with the required
+	-- rollover period in the different DDEn and HDTYPE modi as follows:
+	-- With a nominal adder input term of 128:
+	-- The adder rolls over every 4us for DDEn = 1 and HDTYPE = 0.
+	-- The adder rolls over every 2us for DDEn = 1 and HDTYPE = 1.
+	-- The adder rolls over every 2us for DDEn = 0 and HDTYPE = 0.
+	-- The adder rolls over every 1us for DDEn = 0 and HDTYPE = 1.
+	-- The given times are the half of a data period time in MFM or FM.
+	variable ADDER_DATA	: std_logic_vector(12 downto 0);
+	begin
+		if RESETn = '0' then
+			ADDER_DATA := (others => '0');
+		elsif CLK = '1' and CLK' event then
+			ADDER_DATA := ADDER_DATA + ADDER_IN;
+		end if;
+		--
+		case DDEn & HDTYPE is
+			when "01" => -- MFM mode using HD disks, results in 1us inspection period:
+				ADDER_MSBs <= To_BitVector(ADDER_DATA(10 downto 8));
+			when "00" => -- MFM mode using DD disks, results in 2us inspection period:
+				ADDER_MSBs <= To_BitVector(ADDER_DATA(11 downto 9));
+			when "11" => -- FM mode using HD disks, results in 2us inspection period:
+				ADDER_MSBs <= To_BitVector(ADDER_DATA(11 downto 9));
+			when "10" => -- FM mode using DD disks, results in 4us inspection period:
+				ADDER_MSBs <= To_BitVector(ADDER_DATA(12 downto 10));
+		end case;
+	end process ADDER;
+
+	ROLLOVER: process(RESETn, CLK)
+	-- This process forms a falling edge detector for the detection
+	-- of the adder's rollover time. The output goes low for exactly
+	-- one clock period after the rollover is detected and the positive
+	-- clock edge appears.
+	variable LOCK : boolean;
+	begin
+		if RESETn = '0' then
+			ROLL_OVER <= '0';
+			LOCK := false;
+		elsif CLK = '1' and CLK' event then
+			if ADDER_MSBs /= "111" and LOCK = false then
+				ROLL_OVER <= '1';
+				LOCK := true;
+			elsif ADDER_MSBs = "111" then
+				LOCK := false;
+				ROLL_OVER <= '0';
+			else
+				ROLL_OVER <= '0';
+			end if;
+		end if;
+	end process ROLLOVER;
+	PLL_DSTRB <= ROLL_OVER;
+
+	DATA_FLIP_FLOP: process(RESETn, CLK, RD_PULSE)
+	-- This flip-flop is responsible for 'catching' the read pulses of the
+	-- serial data input. 
+	begin
+		if RESETn = '0' then
+			PLL_D <= '0'; -- Asynchronous reset.
+		elsif CLK = '1' and CLK' event then
+			if RD_PULSE = '1' then
+				PLL_D <= '1'; -- Read pulse detected.
+			elsif ROLL_OVER = '1' then
+				PLL_D <= '0';
+			end if;
+		end if;
+	end process DATA_FLIP_FLOP;
+
+	WIN_HISTORY: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			HISTORY_REG <= "00";
+		elsif CLK = '1' and CLK' event then
+			if RD_PULSE = '1' then
+				HISTORY_REG <= ADDER_MSBs(2) & HISTORY_REG(1);
+			end if;
+		end if;
+	end process WIN_HISTORY;
+	
+	-- Error history:
+	-- This signal indicates the number of consequtive levels of the adder's
+	-- MSB and the history register as shown in the following table. The default
+	-- setting of 0 was added to compile with the Xilinx ISE.
+	ERROR_HISTORY <= 	2 when ADDER_MSBs(2) = '0' and HISTORY_REG = "00" else -- Speed strongly up.
+						1 when ADDER_MSBs(2) = '0' and HISTORY_REG = "01" else -- Speed up.
+						0 when ADDER_MSBs(2) = '0' and HISTORY_REG = "10" else -- o.k.
+						0 when ADDER_MSBs(2) = '0' and HISTORY_REG = "11" else -- Now adjusted.
+						0 when ADDER_MSBs(2) = '1' and HISTORY_REG = "00" else -- Now adjusted.
+						0 when ADDER_MSBs(2) = '1' and HISTORY_REG = "01" else -- o.k.
+						1 when ADDER_MSBs(2) = '1' and HISTORY_REG = "10" else -- Slow down.
+						2 when ADDER_MSBs(2) = '1' and HISTORY_REG = "11" else 0; -- Slow strongly down.
+
+	FREQUENCY_DECODER: process(RESETn, CLK, HI_STOP, LOW_STOP)
+	-- The frequency decoder controls the period of the data inspection window respective to the
+	-- ERROR_HISTORY for the 11 bit adder is as follows:
+	-- ERROR_HISTORY = 0: 
+	--						-> no correction necessary <-
+	-- ERROR_HISTORY = 1:
+	-- MSBs input:			7	6	5	4	3	2	1	0
+	-- Correction output:  -3  -2  -1   0   0  +1  +2  +3
+	-- ERROR_HISTORY = 2:
+	-- MSBs input:			7	6	5	4	3	2	1	0
+	-- Correction output:  -4  -3  -2  -1  +1  +2  +3  +4
+	-- The most significant bit of the FREQ_AMOUNT controls incrementation or decrementation
+	-- of the adder (0 is up).
+	variable FREQ_AMOUNT: std_logic_vector(3 downto 0);
+	begin
+		if RESETn = '0' then
+			FREQ_AMOUNT := "0000";
+		elsif CLK = '1' and CLK' event then
+            if RD_PULSE = '1' then -- Load the frequency amount register.
+				case ERROR_HISTORY is
+					when 2 =>
+						case ADDER_MSBs is
+							when "000" => FREQ_AMOUNT := "0100";
+							when "001" => FREQ_AMOUNT := "0011";
+							when "010" => FREQ_AMOUNT := "0010";
+							when "011" => FREQ_AMOUNT := "0001";
+							when "100" => FREQ_AMOUNT := "1001";
+							when "101" => FREQ_AMOUNT := "1010";
+							when "110" => FREQ_AMOUNT := "1011";
+							when "111" => FREQ_AMOUNT := "1100";
+						end case;
+					when 1 =>
+						case ADDER_MSBs is
+							when "000" => FREQ_AMOUNT := "0011";
+							when "001" => FREQ_AMOUNT := "0010";
+							when "010" => FREQ_AMOUNT := "0001";
+							when "011" => FREQ_AMOUNT := "0000";
+							when "100" => FREQ_AMOUNT := "1000";
+							when "101" => FREQ_AMOUNT := "1001";
+							when "110" => FREQ_AMOUNT := "1010";
+							when "111" => FREQ_AMOUNT := "1011";
+						end case;
+					when others =>
+						FREQ_AMOUNT := "0000";
+				end case;
+            elsif FREQ_AMOUNT(2 downto 0) > "000" then
+				FREQ_AMOUNT := FREQ_AMOUNT - '1'; -- Modify the frequency amount register.
+			end if;
+		end if;
+		--
+		if FREQ_AMOUNT(3) = '0' and FREQ_AMOUNT(2 downto 0) /= "000" and HI_STOP = '0' then
+		-- FREQ_AMOUNT(3) = '0' means Frequency is too low. Count up when counter is not at HI_STOP.
+			UP <= '1';
+			DOWN <= '0';
+		elsif FREQ_AMOUNT(3) = '1' and FREQ_AMOUNT (2 downto 0) /= "000" and LOW_STOP = '0' then
+		-- FREQ_AMOUNT(3) = '1' means Frequency is too high. Count down when counter is not at LOW_STOP.
+			UP <= '0';
+			DOWN <= '1';
+		else
+			UP <= '0';
+			DOWN <= '0';
+		end if;
+	end process FREQUENCY_DECODER;
+
+	PHASE_DECODER: process(RESETn, CLK)
+	-- The phase decoder depends on the value of ADDER_MSBs. If the phase leeds, the most significant bit
+	-- of PHASE_AMOUNT indicates with a '0', that the next rollover should appear earlier. In case of a
+	-- phase lag, the next rollover should come later (indicated by a '1' of the most significant bit of
+	-- PHASE_AMOUNT).
+	-- This implementation gives the freedom to adjust the phase amount individually for every mode
+	-- depending on DDEn and HDTYPE.
+	variable PHASE_AMOUNT: std_logic_vector(5 downto 0);
+	begin
+		if RESETn = '0' then
+			PHASE_AMOUNT := "000000";
+		elsif CLK = '1' and CLK' event then
+            if RD_PULSE = '1' and DDEn = '1' and HDTYPE = '0' then -- FM mode, single density.
+				case ADDER_MSBs is -- Multiplier: 4.
+					when "000" => PHASE_AMOUNT := "010000";
+					when "001" => PHASE_AMOUNT := "001101";
+					when "010" => PHASE_AMOUNT := "001000";
+					when "011" => PHASE_AMOUNT := "000100";
+					when "100" => PHASE_AMOUNT := "100100";
+					when "101" => PHASE_AMOUNT := "101000";
+					when "110" => PHASE_AMOUNT := "101100";
+					when "111" => PHASE_AMOUNT := "110000";
+				end case;
+			elsif RD_PULSE = '1' and DDEn = '1' and HDTYPE = '1' then -- FM mode, double density
+				case ADDER_MSBs is -- Multiplier: 2.
+					when "000" => PHASE_AMOUNT := "001000";
+					when "001" => PHASE_AMOUNT := "000110";
+					when "010" => PHASE_AMOUNT := "000100";
+					when "011" => PHASE_AMOUNT := "000010";
+					when "100" => PHASE_AMOUNT := "100010";
+					when "101" => PHASE_AMOUNT := "100100";
+					when "110" => PHASE_AMOUNT := "100110";
+					when "111" => PHASE_AMOUNT := "101000";
+				end case;
+            elsif RD_PULSE = '1' and DDEn = '0' and HDTYPE = '0' then -- MFM mode, single density
+				case ADDER_MSBs is -- Multiplier: 2.
+					when "000" => PHASE_AMOUNT := "000110";
+					when "001" => PHASE_AMOUNT := "000100";
+					when "010" => PHASE_AMOUNT := "000011";
+					when "011" => PHASE_AMOUNT := "000010";
+					when "100" => PHASE_AMOUNT := "100010";
+					when "101" => PHASE_AMOUNT := "100011";
+					when "110" => PHASE_AMOUNT := "100100";
+					when "111" => PHASE_AMOUNT := "100110";
+				end case;
+			elsif RD_PULSE = '1' and DDEn = '0' and HDTYPE = '1' then -- MFM mode, double density.
+				case ADDER_MSBs is -- Multiplier: 1.
+					when "000" => PHASE_AMOUNT := "000100";
+					when "001" => PHASE_AMOUNT := "000011";
+					when "010" => PHASE_AMOUNT := "000010";
+					when "011" => PHASE_AMOUNT := "000001";
+					when "100" => PHASE_AMOUNT := "100001";
+					when "101" => PHASE_AMOUNT := "100010";
+					when "110" => PHASE_AMOUNT := "100011";
+					when "111" => PHASE_AMOUNT := "100100";
+				end case;
+			else -- Modify phase amount register:
+                if PHASE_AMOUNT(4 downto 0) > x"0" then
+                    PHASE_AMOUNT := PHASE_AMOUNT - 1;
+				end if;
+			end if;
+		end if;
+		--
+        if PHASE_AMOUNT(5) = '0' and PHASE_AMOUNT(4 downto 0) > x"0" then
+		-- PHASE_AMOUNT(5) = '0' means, that the phase leeds.
+			PHASE_INCREASE <= '1'; -- Speed phase up, accelerate next rollover.
+			PHASE_DECREASE <= '0';
+        elsif PHASE_AMOUNT(5) = '1' and PHASE_AMOUNT(4 downto 0) > x"0" then
+		-- PHASE_AMOUNT(5) = '1' means, that the phase lags.
+			PHASE_INCREASE <= '0';
+			PHASE_DECREASE <= '1'; -- Speed phase down, delay of next rollover.
+		else
+			PHASE_INCREASE <= '0';
+			PHASE_DECREASE <= '0';
+		end if;
+	end process PHASE_DECODER;
+end architecture BEHAVIOR;
\ No newline at end of file
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd
new file mode 100644
index 0000000..b365b3d
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd
@@ -0,0 +1,232 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WD1772 compatible floppy disk controller IP Core.            ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Floppy disk controller with all features of the Western      ----
+---- Digital WD1772-02 controller.                                ----
+----                                                              ----
+---- This is the package file containing the component            ----
+---- declarations.                                                ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2006A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/05 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--   Removed CRC_BUSY.
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package WF1772IP_PKG is
+-- component declarations:
+component WF1772IP_AM_DETECTOR
+	port(
+		CLK			: in bit;
+		RESETn		: in bit;
+		DDEn		: in bit;
+		DATA		: in bit;
+		DATA_STRB	: in bit;
+		ID_AM		: out bit;
+		DATA_AM		: out bit;
+		DDATA_AM	: out bit
+	);
+end component;
+
+component WF1772IP_CONTROL
+	port(
+		CLK				: in bit;
+		RESETn			: in bit;
+		A1, A0			: in bit;
+		RWn				: in bit;
+		CSn				: in bit;
+		DDEn			: in bit;
+		DR				: in bit_vector(7 downto 0);
+		CMD				: in std_logic_vector(7 downto 0);
+		DSR				: in std_logic_vector(7 downto 0);
+		TR				: in std_logic_vector(7 downto 0);
+		SR				: in std_logic_vector(7 downto 0);
+		MO				: out bit;
+		WR_PR			: out bit;
+		SPINUP_RECTYPE	: out bit;
+		SEEK_RNF		: out bit;
+		CRC_ERRFLAG		: out bit;
+		LOST_DATA_TR00	: out bit;
+		DRQ				: out bit;
+		DRQ_IPn			: out bit;
+		BUSY			: out bit;
+		AM_2_DISK		: out bit;
+		ID_AM			: in bit;
+		DATA_AM			: in bit;
+		DDATA_AM		: in bit;
+		CRC_ERR			: in bit;
+		CRC_PRES		: out bit;
+		TR_PRES			: out bit;
+		TR_CLR			: out bit;
+		TR_INC			: out bit;
+		TR_DEC			: out bit;
+		SR_LOAD			: out bit;
+		SR_INC			: out bit;
+		TRACK_NR		: out std_logic_vector(7 downto 0);
+		DR_CLR			: out bit;
+		DR_LOAD			: out bit;
+		SHFT_LOAD_SD	: out bit;
+		SHFT_LOAD_ND	: out bit;
+		CRC_2_DISK		: out bit;
+		DSR_2_DISK		: out bit;
+		FF_2_DISK		: out bit;
+		PRECOMP_EN		: out bit;
+		DATA_STRB 		: in bit;
+		DISK_RWn		: out bit;
+		WPRTn			: in bit;
+		TRACK00n		: in bit;
+		IPn				: in bit;
+		DIRC			: out bit;
+		STEP			: out bit;
+		WG				: out bit;
+		INTRQ			: out bit
+	);
+end component;
+
+component WF1772IP_CRC_LOGIC
+	port(
+		CLK			: in bit;
+		RESETn		: in bit;
+		DDEn		: in bit;
+		DISK_RWn	: in bit;
+		ID_AM		: in bit;
+		DATA_AM		: in bit;
+		DDATA_AM	: in bit;
+		SD			: in bit;
+		CRC_STRB	: in bit;
+		CRC_2_DISK	: in bit;
+		CRC_PRES	: in bit;
+		CRC_SDOUT	: out bit;
+		CRC_ERR		: out bit
+	);
+end component;
+
+component WF1772IP_DIGITAL_PLL
+	port(
+		CLK			: in bit;
+		RESETn		: in bit;
+		DDEn		: in bit;
+		HDTYPE		: in bit;
+		DISK_RWn	: in bit;
+		RDn			: in bit;
+		PLL_D		: out bit;
+		PLL_DSTRB	: out bit
+	);
+end component;
+
+component WF1772IP_REGISTERS
+	port(
+		CLK				: in bit;
+		RESETn			: in bit;
+		CSn				: in bit;
+		ADR				: in bit_vector(1 downto 0);
+		RWn				: in bit;
+		DATA_IN			: in std_logic_vector (7 downto 0);
+		DATA_OUT		: out std_logic_vector (7 downto 0);
+		DATA_EN			: out bit;
+		CMD				: out std_logic_vector(7 downto 0);
+		SR				: out std_logic_vector(7 downto 0);
+		TR				: out std_logic_vector(7 downto 0);
+		DSR				: out std_logic_vector(7 downto 0);
+		DR				: out bit_vector(7 downto 0);
+		SD_R			: in bit;
+		DATA_STRB		: in bit;
+		DR_CLR			: in bit;
+		DR_LOAD			: in bit;
+		TR_PRES			: in bit;
+		TR_CLR			: in bit;
+		TR_INC			: in bit;
+		TR_DEC			: in bit;
+		TRACK_NR 		: in std_logic_vector(7 downto 0);
+		SR_LOAD			: in bit;
+		SR_INC			: in bit;
+		SHFT_LOAD_SD	: in bit;
+		SHFT_LOAD_ND	: in bit;
+		MOTOR_ON		: in bit;
+		WRITE_PROTECT	: in bit;
+		SPINUP_RECTYPE	: in bit;
+		SEEK_RNF		: in bit;
+		CRC_ERRFLAG		: in bit;
+		LOST_DATA_TR00	: in bit;
+		DRQ				: in bit;
+		DRQ_IPn			: in bit;
+		BUSY			: in bit;
+		DDEn			: in bit
+	);
+end component;
+
+component WF1772IP_TRANSCEIVER
+	port(
+		CLK				: in bit;
+		RESETn			: in bit;
+		DDEn			: in bit;
+		HDTYPE			: in bit;
+		ID_AM			: in bit;
+		DATA_AM			: in bit;
+		DDATA_AM		: in bit;
+		SHFT_LOAD_SD	: in bit;
+		DR				: in bit_vector(7 downto 0);
+		PRECOMP_EN		: in bit;
+		AM_TYPE			: in bit;
+		AM_2_DISK		: in bit;
+		CRC_2_DISK		: in bit;
+		DSR_2_DISK		: in bit;
+		FF_2_DISK		: in bit;
+		SR_SDOUT		: in std_logic;
+		CRC_SDOUT		: in bit;
+		WRn				: out bit;
+		PLL_DSTRB		: in bit;
+		PLL_D			: in bit;
+		WDATA 			: out bit;
+		DATA_STRB 		: out bit;
+		SD_R			: out bit
+	);
+end component;
+end WF1772IP_PKG;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd
new file mode 100644
index 0000000..7556fe5
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd
@@ -0,0 +1,264 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WD1772 compatible floppy disk controller IP Core.            ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Floppy disk controller with all features of the Western      ----
+---- Digital WD1772-02 controller.                                ----
+----                                                              ----
+---- This file models all the five WD1772 registers: DATA-,       ----
+---- COMMAND-, SECTOR-, TRACK- and STATUS register as also the    ----
+---- shift register.                                              ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2006A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/05 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF1772IP_REGISTERS is
+	port(
+		-- System control:
+		CLK			: in bit;
+		RESETn		: in bit;
+
+		-- Bus interface:
+		CSn			: in bit;
+		ADR			: in bit_vector(1 downto 0);
+		RWn			: in bit;
+		DATA_IN		: in std_logic_vector (7 downto 0);
+		DATA_OUT	: out std_logic_vector (7 downto 0);
+		DATA_EN		: out bit;
+
+		-- FDC data:
+		CMD			: out std_logic_vector(7 downto 0); -- Command register.
+		SR			: out std_logic_vector(7 downto 0); -- Sector register.
+		TR			: out std_logic_vector(7 downto 0); -- Track register.
+		DSR			: out std_logic_vector(7 downto 0); -- Data shift register.
+		DR			: out bit_vector(7 downto 0); -- Data register.
+
+		-- Serial data and clock strobes (in and out):
+		DATA_STRB	: in bit; -- Strobe for the incoming data.
+		SD_R		: in bit; -- Serial data input.
+		
+		-- DATA register control:
+		DR_CLR		: in bit; -- Clear.
+		DR_LOAD		: in bit; -- LOAD.
+
+		-- Track register controls:
+		TR_PRES		: in bit;	-- Set x"FF".
+		TR_CLR		: in bit;	-- Clear.
+		TR_INC		: in bit;	-- Increment.
+		TR_DEC		: in bit;	-- Decrement.
+
+		-- Sector register control:
+		TRACK_NR 	: in std_logic_vector(7 downto 0);
+		SR_LOAD		: in bit; -- Load.
+		SR_INC		: in bit; -- Increment.
+
+		-- Shift register control:
+		SHFT_LOAD_SD	: in bit;
+		SHFT_LOAD_ND	: in bit;
+
+		-- Status register stuff
+		MOTOR_ON		: in bit;
+		WRITE_PROTECT	: in bit;
+		SPINUP_RECTYPE	: in bit; -- Disk is on speed / data mark status.
+		SEEK_RNF		: in bit; -- Seek error / record not found status flag.
+		CRC_ERRFLAG		: in bit; -- CRC status flag.
+		LOST_DATA_TR00	: in bit;
+		DRQ				: in bit;
+		DRQ_IPn			: in bit;
+		BUSY			: in bit;
+
+		-- Others:
+		DDEn			: in bit
+	);
+end WF1772IP_REGISTERS;
+
+architecture BEHAVIOR of WF1772IP_REGISTERS is
+-- Remark: In the original data sheet 'WD17X-00' there is the following statement:
+-- "After any register is written to, the same register cannot be read from until
+-- 16us in MFM or 32us in FMMM have elapsed." If this is a hint for a hardware read
+-- lock ... this lock is not implemented in this code.
+signal SHIFT_REG	: std_logic_vector(7 downto 0);
+signal DATA_REG		: std_logic_vector(7 downto 0);
+signal COMMAND_REG	: std_logic_vector(7 downto 0);
+signal SECTOR_REG	: std_logic_vector(7 downto 0);
+signal TRACK_REG	: std_logic_vector(7 downto 0);
+signal STATUS_REG	: bit_vector(7 downto 0);
+signal SD_R_I		: std_logic;
+begin
+	-- Type conversion To_Std_Logic:
+	SD_R_I <= '1' when SD_R = '1' else '0';
+
+	P_SHIFTREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SHIFT_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if SHFT_LOAD_ND = '1' then
+				SHIFT_REG <= DATA_REG; -- Load data register stuff.
+			elsif SHFT_LOAD_SD = '1' and DDEn = '1' then
+				SHIFT_REG <= DATA_REG; -- Normal data in FM mode.
+			elsif SHFT_LOAD_SD = '1' and DDEn = '0' then -- MFM mode:
+				case DATA_REG is
+					when x"F5" => SHIFT_REG <= x"A1"; -- Special character.
+					when x"F6" => SHIFT_REG <= x"C2"; -- Special character.
+					when others => SHIFT_REG <= DATA_REG; -- Normal MFM data.
+				end case;
+			elsif DATA_STRB = '1' then -- Shift left during read from disk or write to disk.
+				SHIFT_REG <= SHIFT_REG(6 downto 0) & SD_R_I; -- for write operation SD_R_I is a dummy.
+			end if;
+		end if;
+	end process P_SHIFTREG;
+	DSR <= SHIFT_REG;
+
+	DATAREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DATA_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if CSn = '0' and ADR = "11" and RWn = '0' then
+				DATA_REG <= DATA_IN; -- Write bus data to register
+			elsif DR_LOAD = '1' and DRQ = '0' then
+				DATA_REG <= SHIFT_REG; -- Correct data loaded to shift register.
+			elsif DR_LOAD = '1' and DRQ = '1' then
+				DATA_REG <= x"00"; -- Dummy byte due to lost data loaded to shift register.
+			elsif DR_CLR = '1' then
+				DATA_REG <= (others => '0');
+			end if;
+		end if;
+	end process DATAREG;
+	-- Data register buffered for further data processing.
+	DR <= To_BitVector(DATA_REG);
+
+	SECTORREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SECTOR_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+            if CSn = '0' and ADR = "10" and RWn = '0' and BUSY = '0' then
+				SECTOR_REG <= DATA_IN; -- Write to register when device is not busy.
+			elsif SR_LOAD = '1' then
+				-- Load the track number to the sector register in the type III command
+				-- 'Read Address'.
+				SECTOR_REG <= TRACK_NR;
+			elsif SR_INC = '1' then
+				SECTOR_REG <= SECTOR_REG + '1';
+			end if;
+		end if;
+	end process SECTORREG;
+	SR <= SECTOR_REG;
+
+	TRACKREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			TRACK_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if CSn = '0' and ADR = "01" and RWn = '0' and BUSY = '0' then
+				TRACK_REG <= DATA_IN; -- Write to register when device is busy.
+			elsif TR_PRES = '1' then
+				TRACK_REG <= (others => '1'); -- Preset the track register.
+			elsif TR_CLR = '1' then
+				TRACK_REG <= (others => '0'); -- Reset the track register.
+			elsif TR_INC = '1' then
+				TRACK_REG <= TRACK_REG + '1'; -- Increment register contents.
+			elsif TR_DEC = '1' then
+				TRACK_REG <= TRACK_REG - '1'; -- Decrement register contents.
+			end if;
+		end if;
+	end process TRACKREG;
+	TR <= TRACK_REG;
+
+	COMMANDREG: process(RESETn, CLK)
+	-- The command register is write only.
+	begin
+		if RESETn = '0' then
+			COMMAND_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if CSn = '0' and ADR = "00" and RWn = '0' and BUSY = '0' then
+				COMMAND_REG <= DATA_IN; -- Write to register when device is not busy.
+			-- Write 'force interrupt' to register even when device is busy:
+			elsif CSn = '0' and ADR = "00" and RWn = '0' and DATA_IN(7 downto 4) = x"D" then
+				COMMAND_REG <= DATA_IN;
+			end if;
+		end if;
+	end process COMMANDREG;
+	CMD <= COMMAND_REG;
+
+	STATUSREG: process(RESETn, CLK)
+	-- The status register is read only to the data bus.
+	begin
+		-- Status register wiring:
+		if RESETn = '0' then
+			STATUS_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			STATUS_REG(7) <= MOTOR_ON;
+			STATUS_REG(6) <= WRITE_PROTECT;
+			STATUS_REG(5) <= SPINUP_RECTYPE;
+			STATUS_REG(4) <= SEEK_RNF;
+			STATUS_REG(3) <= CRC_ERRFLAG;
+			STATUS_REG(2) <= LOST_DATA_TR00;
+			STATUS_REG(1) <= DRQ_IPn;
+			STATUS_REG(0) <= BUSY;
+		end if;
+	end process STATUSREG;
+	-- Read from track, sector or data register:
+	-- The register data after writing to the track register is valid at least
+	-- after 32us in FM mode and after 16us in MFM mode.
+	-- Read from status register. This register is read only:
+	-- Be aware, that the status register data bits 7 to 1 after writing 
+	-- the command regsiter are valid at least after 64us in FM mode or 32us in MFM mode and
+	-- the bit 0 (BUSY) is valid after 48us in FM mode or 24us in MFM mode.
+	DATA_OUT <= TRACK_REG when CSn = '0' and ADR = "01" and RWn = '1' else
+				SECTOR_REG when CSn = '0' and ADR = "10" and RWn = '1' else
+				DATA_REG when CSn = '0' and ADR = "11" and RWn = '1' else
+				To_StdLogicVector(STATUS_REG) when CSn = '0' and ADR = "00" and RWn = '1' else (others => '0');
+	DATA_EN <= '1' when CSn = '0' and RWn = '1' else '0';
+end architecture BEHAVIOR;
\ No newline at end of file
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
new file mode 100644
index 0000000..71ef3f3
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
@@ -0,0 +1,154 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WD1772 compatible floppy disk controller IP Core.            ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Floppy disk controller with all features of the Western      ----
+---- Digital WD1772-02 controller.                                ----
+----                                                              ----
+---- This is the top level file.                                  ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- - Test of the FM portion of the code (if there is any need). ----
+---- - Test of the read track command.                            ----
+---- - Test of the read address command.                          ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2006A  2006/06/03 WF
+--   Initial Release: the MFM portion for HD and DD floppies is tested.
+--   The FM mode (DDEn = '1') is not completely tested due to the lack 
+--   of FM drives.
+-- Revision 2K6B  2006/11/05 WF
+--   Modified Source to compile with the Xilinx ISE.
+--   Fixed the polarity of the precompensation flag.
+--   The flag is no active '0'. Thanks to Jorma
+--   Oksanen for the information.
+-- Revision 2K7B  2006/12/29 WF
+--   Introduced several improvements based on a very good examination
+--   of the pll code by Jean Louis-Guerin.
+-- Revision 2K8B  2008/12/24 WF
+--   Rewritten this top level file as a wrapper for the top_soc file.
+
+library work;
+use work.WF1772IP_PKG.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF1772IP_TOP is
+	port (
+		CLK			: in bit; -- 16MHz clock!
+		MRn			: in bit;
+		CSn			: in bit;
+		RWn			: in bit;
+		A1, A0		: in bit;
+		DATA		: inout std_logic_vector(7 downto 0);
+		RDn			: in bit;
+		TR00n		: in bit;
+		IPn			: in bit;
+		WPRTn		: in bit;
+		DDEn		: in bit;
+		HDTYPE		: in bit; -- '0' = DD disks, '1' = HD disks.
+		MO			: out bit;
+		WG			: out bit;
+		WD			: out bit;
+		STEP		: out bit;
+		DIRC		: out bit;
+		DRQ			: out bit;
+		INTRQ		: out bit
+	);
+end entity WF1772IP_TOP;
+	
+architecture STRUCTURE of WF1772IP_TOP is
+component WF1772IP_TOP_SOC
+	port (
+		CLK			: in bit;
+		RESETn		: in bit;
+		CSn			: in bit;
+		RWn			: in bit;
+		A1, A0		: in bit;
+		DATA_IN		: in std_logic_vector(7 downto 0);
+		DATA_OUT	: out std_logic_vector(7 downto 0);
+		DATA_EN		: out bit;
+		RDn			: in bit;
+		TR00n		: in bit;
+		IPn			: in bit;
+		WPRTn		: in bit;
+		DDEn		: in bit;
+		HDTYPE		: in bit;
+		MO			: out bit;
+		WG			: out bit;
+		WD			: out bit;
+		STEP		: out bit;
+		DIRC		: out bit;
+		DRQ			: out bit;
+		INTRQ		: out bit
+	);
+end component;
+signal DATA_OUT : std_logic_vector(7 downto 0);
+signal DATA_EN  : bit;
+begin
+    DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z');
+
+    I_1772: WF1772IP_TOP_SOC
+        port map(
+            CLK         => CLK,
+            RESETn      => MRn,
+            CSn         => CSn,
+            RWn         => RWn,
+            A1          => A1,
+            A0          => A0,
+            DATA_IN     => DATA,
+            DATA_OUT    => DATA_OUT,
+            DATA_EN     => DATA_EN,
+            RDn         => RDn,
+            TR00n       => TR00n,
+            IPn         => IPn,
+            WPRTn       => WPRTn,
+            DDEn        => DDEn,
+            HDTYPE      => HDTYPE,
+            MO          => MO,
+            WG          => WG,
+            WD          => WD,
+            STEP        => STEP,
+            DIRC        => DIRC,
+            DRQ         => DRQ,
+            INTRQ       => INTRQ
+        );
+end architecture STRUCTURE;
\ No newline at end of file
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
new file mode 100644
index 0000000..9cfd111
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
@@ -0,0 +1,333 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WD1772 compatible floppy disk controller IP Core.            ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Floppy disk controller with all features of the Western      ----
+---- Digital WD1772-02 controller.                                ----
+----                                                              ----
+---- Top level file for use in systems on programmable chips.     ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- - Test of the FM portion of the code (if there is any need). ----
+---- - Test of the read track command.                            ----
+---- - Test of the read address command.                          ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2006A  2006/06/03 WF
+--   Initial Release: the MFM portion for HD and DD floppies is tested.
+--   The FM mode (DDEn = '1') is not completely tested due to the lack 
+--   of FM drives.
+-- Revision 2K6B  2006/11/05 WF
+--   Modified Source to compile with the Xilinx ISE.
+--   Fixed the polarity of the precompensation flag.
+--   The flag is no active '0'. Thanks to Jorma Oksanen for the information.
+--   Top level file provided for SOC (systems on programmable chips).
+-- Revision 2K7B  2006/12/29 WF
+--   Introduced several improvements based on a very good examination
+--   of the pll code by Jean Louis-Guerin.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K8B  2008/12/24 WF
+--   Bugfixes in the controller due to hanging state machine.
+--   Removed CRC_BUSY.
+--
+
+library work;
+use work.WF1772IP_PKG.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF1772IP_TOP_SOC is
+	port (
+		CLK			: in bit; -- 16MHz clock!
+		RESETn		: in bit;
+		CSn			: in bit;
+		RWn			: in bit;
+		A1, A0		: in bit;
+		DATA_IN		: in std_logic_vector(7 downto 0);
+		DATA_OUT	: out std_logic_vector(7 downto 0);
+		DATA_EN		: out bit;
+		RDn			: in bit;
+		TR00n		: in bit;
+		IPn			: in bit;
+		WPRTn		: in bit;
+		DDEn		: in bit;
+		HDTYPE		: in bit; -- '0' = DD disks, '1' = HD disks.
+		MO			: out bit;
+		WG			: out bit;
+		WD			: out bit;
+		STEP		: out bit;
+		DIRC		: out bit;
+		DRQ			: out bit;
+		INTRQ		: out bit
+	);
+end entity WF1772IP_TOP_SOC;
+	
+architecture STRUCTURE of WF1772IP_TOP_SOC is
+signal DATA_OUT_REG		: std_logic_vector(7 downto 0);
+signal DATA_EN_REG		: bit;
+signal CMD_I			: std_logic_vector(7 downto 0);
+signal DR_I				: bit_vector(7 downto 0);
+signal DSR_I			: std_logic_vector(7 downto 0);
+signal TR_I				: std_logic_vector(7 downto 0);
+signal SR_I				: std_logic_vector(7 downto 0);
+signal ID_AM_I			: bit;
+signal DATA_AM_I		: bit;
+signal DDATA_AM_I		: bit;
+signal AM_TYPE_I		: bit;
+signal AM_2_DISK_I		: bit;
+signal DATA_STRB_I		: bit;
+signal BUSY_I			: bit;
+signal DRQ_I			: bit;
+signal DRQ_IPn_I		: bit;
+signal LD_TR00_I		: bit;
+signal SP_RT_I			: bit;
+signal SEEK_RNF_I		: bit;
+signal WR_PR_I			: bit;
+signal MO_I				: bit;
+signal PLL_DSTRB_I		: bit;
+signal PLL_D_I			: bit;
+signal CRC_SD_I			: bit;
+signal CRC_ERR_I		: bit;
+signal CRC_PRES_I		: bit;
+signal CRC_ERRFLAG_I	: bit;
+signal SD_R_I			: bit;
+signal CRC_SDOUT_I		: bit;
+signal SHFT_LOAD_SD_I	: bit;
+signal SHFT_LOAD_ND_I	: bit;
+signal WR_In			: bit;
+signal TR_PRES_I		: bit;
+signal TR_CLR_I			: bit;
+signal TR_INC_I			: bit;
+signal TR_DEC_I			: bit;
+signal SR_LOAD_I		: bit;
+signal SR_INC_I			: bit;
+signal DR_CLR_I			: bit;
+signal DR_LOAD_I		: bit;
+signal TRACK_NR_I		: std_logic_vector(7 downto 0);
+signal CRC_2_DISK_I		: bit;
+signal DSR_2_DISK_I		: bit;
+signal FF_2_DISK_I		: bit;
+signal PRECOMP_EN_I		: bit;
+signal DISK_RWn_I		: bit;
+signal WDATA_I			: bit;
+begin
+	-- Three state data bus:
+	DATA_OUT <= DATA_OUT_REG when DATA_EN_REG = '1' else (others => '0');
+	DATA_EN <= DATA_EN_REG;
+
+	-- Some signals copied to the outputs:
+    WD <= not WR_In;
+	MO <= MO_I;
+	DRQ <= DRQ_I;
+
+	-- Write deleted data address mark in MFM mode in 'Write Sector' command in
+	-- case of asserted command bit 0.
+	AM_TYPE_I <= '0' when CMD_I(7 downto 5) = "101" and CMD_I(0) = '1' else '1';
+
+	-- The CRC unit is used during read from disk and write to disk.
+	-- This is the data multiplexer for the data stream to encode.
+	CRC_SD_I <= SD_R_I when DISK_RWn_I = '1' else WDATA_I;
+
+	I_CONTROL: WF1772IP_CONTROL
+		port map(
+            CLK				=> CLK,
+			RESETn			=> RESETn,
+			A1				=> A0,
+			A0				=> A1,
+			RWn				=> RWn,
+			CSn				=> CSn,
+			DDEn			=> DDEn,
+			DR				=> DR_I,
+			CMD				=> CMD_I,
+			DSR				=> DSR_I,
+			TR				=> TR_I,
+			SR				=> SR_I,
+			MO				=> MO_I,
+			WR_PR			=> WR_PR_I,
+			SPINUP_RECTYPE	=> SP_RT_I,
+			SEEK_RNF		=> SEEK_RNF_I,
+			CRC_ERRFLAG		=> CRC_ERRFLAG_I,
+			LOST_DATA_TR00	=> LD_TR00_I,
+			DRQ				=> DRQ_I,
+			DRQ_IPn			=> DRQ_IPn_I,
+			BUSY			=> BUSY_I,
+			AM_2_DISK		=> AM_2_DISK_I,
+			ID_AM			=> ID_AM_I,
+			DATA_AM			=> DATA_AM_I,
+			DDATA_AM		=> DDATA_AM_I,
+			CRC_ERR			=> CRC_ERR_I,
+			CRC_PRES		=> CRC_PRES_I,
+			TR_PRES			=> TR_PRES_I,
+			TR_CLR			=> TR_CLR_I,
+			TR_INC			=> TR_INC_I,
+			TR_DEC			=> TR_DEC_I,
+			SR_LOAD			=> SR_LOAD_I,
+			SR_INC			=> SR_INC_I,
+			TRACK_NR		=> TRACK_NR_I,
+			DR_CLR			=> DR_CLR_I,
+			DR_LOAD			=> DR_LOAD_I,
+			SHFT_LOAD_SD	=> SHFT_LOAD_SD_I,
+			SHFT_LOAD_ND	=> SHFT_LOAD_ND_I,
+			CRC_2_DISK		=> CRC_2_DISK_I,
+			DSR_2_DISK		=> DSR_2_DISK_I,
+			FF_2_DISK		=> FF_2_DISK_I,
+			PRECOMP_EN		=> PRECOMP_EN_I,
+			DATA_STRB		=> DATA_STRB_I,
+			DISK_RWn		=> DISK_RWn_I,
+			WPRTn			=> WPRTn,
+			TRACK00n		=> TR00n,
+			IPn				=> IPn,
+			DIRC			=> DIRC,
+			STEP			=> STEP,
+			WG				=> WG,
+			INTRQ			=> INTRQ
+		);
+
+	I_REGISTERS: WF1772IP_REGISTERS
+		port map(
+			CLK				=> CLK,
+			RESETn			=> RESETn,
+			CSn				=> CSn,
+			ADR(1)			=> A1,
+			ADR(0)			=> A0,
+			RWn				=> RWn,
+			DATA_IN			=> DATA_IN,
+			DATA_OUT		=> DATA_OUT_REG,
+			DATA_EN			=> DATA_EN_REG,
+			CMD				=> CMD_I,
+			TR				=> TR_I,
+			SR				=> SR_I,
+			DSR				=> DSR_I,
+			DR				=> DR_I,
+			SD_R			=> SD_R_I,
+			DATA_STRB		=> DATA_STRB_I,
+			DR_CLR			=> DR_CLR_I,
+			DR_LOAD			=> DR_LOAD_I,
+			TR_PRES			=> TR_PRES_I,
+			TR_CLR			=> TR_CLR_I,
+			TR_INC			=> TR_INC_I,
+			TR_DEC			=> TR_DEC_I,
+			TRACK_NR		=> TRACK_NR_I,
+			SR_LOAD			=> SR_LOAD_I,
+			SR_INC			=> SR_INC_I,
+			SHFT_LOAD_SD	=> SHFT_LOAD_SD_I,
+			SHFT_LOAD_ND	=> SHFT_LOAD_ND_I,
+			MOTOR_ON		=> MO_I,
+			WRITE_PROTECT	=> WR_PR_I,
+			SPINUP_RECTYPE	=> SP_RT_I,
+			SEEK_RNF		=> SEEK_RNF_I,
+			CRC_ERRFLAG		=> CRC_ERRFLAG_I,
+			LOST_DATA_TR00	=> LD_TR00_I,
+			DRQ				=> DRQ_I,
+			DRQ_IPn			=> DRQ_IPn_I,
+			BUSY			=> BUSY_I,
+			DDEn			=> DDEn
+		);
+
+	I_DIGITAL_PLL: WF1772IP_DIGITAL_PLL
+		port map(
+			CLK			=> CLK,
+			RESETn		=> RESETn,
+			DDEn		=> DDEn,
+			HDTYPE 		=> HDTYPE,
+			DISK_RWn	=> DISK_RWn_I,
+			RDn			=> RDn,
+			PLL_D		=> PLL_D_I,
+			PLL_DSTRB	=> PLL_DSTRB_I
+		);
+
+	I_AM_DETECTOR: WF1772IP_AM_DETECTOR
+		port map(
+			CLK			=> CLK,
+			RESETn		=> RESETn,
+			DDEn		=> DDEn,
+			DATA		=> PLL_D_I,
+			DATA_STRB	=> PLL_DSTRB_I,
+			ID_AM		=> ID_AM_I,
+			DATA_AM		=> DATA_AM_I,
+			DDATA_AM	=> DDATA_AM_I
+		);
+
+	I_CRC_LOGIC: WF1772IP_CRC_LOGIC
+		port map(
+			CLK			=> CLK,
+			RESETn		=> RESETn,
+			DDEn		=> DDEn,
+			DISK_RWn	=> DISK_RWn_I,
+			ID_AM		=> ID_AM_I,
+			DATA_AM		=> DATA_AM_I,
+			DDATA_AM	=> DDATA_AM_I,
+			SD			=> CRC_SD_I,
+			CRC_STRB	=> DATA_STRB_I,
+			CRC_2_DISK	=> CRC_2_DISK_I,
+			CRC_PRES	=> CRC_PRES_I,
+			CRC_SDOUT	=> CRC_SDOUT_I,
+			CRC_ERR		=> CRC_ERR_I
+		);
+
+	I_TRANSCEIVER: WF1772IP_TRANSCEIVER
+		port map(
+			CLK				=> CLK,
+			RESETn			=> RESETn,
+			DDEn			=> DDEn,
+			HDTYPE 			=> HDTYPE,
+			ID_AM			=> ID_AM_I,
+			DATA_AM			=> DATA_AM_I,
+			DDATA_AM		=> DDATA_AM_I,
+			SHFT_LOAD_SD	=> SHFT_LOAD_SD_I,
+			DR				=> DR_I,
+			PRECOMP_EN		=> PRECOMP_EN_I,
+			AM_TYPE			=> AM_TYPE_I,
+			AM_2_DISK		=> AM_2_DISK_I,
+			CRC_2_DISK		=> CRC_2_DISK_I,
+			DSR_2_DISK		=> DSR_2_DISK_I,
+			FF_2_DISK		=> FF_2_DISK_I,
+			SR_SDOUT		=> DSR_I(7),
+			CRC_SDOUT		=> CRC_SDOUT_I,
+			WRn				=> WR_In,
+			WDATA			=> WDATA_I,
+			PLL_DSTRB		=> PLL_DSTRB_I,
+			PLL_D			=> PLL_D_I,
+			DATA_STRB		=> DATA_STRB_I,
+			SD_R			=> SD_R_I
+		);
+end architecture STRUCTURE;
\ No newline at end of file
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
new file mode 100644
index 0000000..c836716
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
@@ -0,0 +1,517 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- WD1772 compatible floppy disk controller IP Core.            ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Floppy disk controller with all features of the Western      ----
+---- Digital WD1772-02 controller.                                ----
+----                                                              ----
+---- The transceiver unit contains on the one hand the receiver   ----
+---- part which strips off the clock signal from the data stream  ----
+---- and on the other hand the transmitter unit which provides in ----
+---- the different modes (FM and MFM) all functions which are     ----
+---- necessary to send data, CRC bytes, 'FF', '00' or the address ----
+---- marks.                                                       ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2006A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/05 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K9A  2009/06/20 WF
+--   MFM_In and MASK_SHFT have now synchronous reset to meet preset requirement.
+-- 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF1772IP_TRANSCEIVER is
+	port(
+		-- System control
+		CLK		: in bit; -- must be 16MHz
+		RESETn	: in bit;
+
+		-- Data and Control:
+		HDTYPE			: in bit; -- Floppy type HD or DD.
+		DDEn			: in bit; -- Double density select (FM or MFM).
+		ID_AM			: in bit; -- ID addressmark strobe.
+		DATA_AM			: in Bit; -- Data addressmark strobe.
+		DDATA_AM		: in Bit; -- Deleted data addressmark strobe.
+		SHFT_LOAD_SD	: in bit; -- Indication for shift register load time.
+		DR				: in bit_vector(7 downto 0); -- Content of the data register.
+
+		-- Data strobes:
+		PLL_DSTRB	: in bit; -- Clock strobe for RD serial data input.
+		DATA_STRB 	: buffer bit;
+		
+		-- Data strobe and data for the CRC during write operation:
+		WDATA 		: buffer bit;
+
+		-- Encoder (logic to disk):
+		PRECOMP_EN	: in bit; -- control signal for MFM write precompensation.
+		AM_TYPE		: in bit; -- Write deleted address mark in MFM mode when 0.
+		AM_2_DISK	: in bit;
+		DSR_2_DISK	: in bit;
+		FF_2_DISK	: in bit;
+		CRC_2_DISK	: in bit;
+		SR_SDOUT	: in std_logic; -- encoder's data input from the shift register (serial).
+		CRC_SDOUT	: in bit; -- encoder's data input from the CRC unit (serial).
+		WRn			: out bit; -- write output for the MFM drive containing clock and data.
+
+		-- Decoder (disk to logic):
+		PLL_D		: in bit; -- Serial data input.
+		SD_R		: out bit -- Serial (decoded) data output.
+	);
+end WF1772IP_TRANSCEIVER;
+
+architecture BEHAVIOR of WF1772IP_TRANSCEIVER is
+type MFM_STATES is (A_00, B_01, C_10);
+type PRECOMP_VALUES is (EARLY, NOMINAL, LATE);
+type DEC_STATES is (CLK_PHASE, DATA_PHASE);
+
+signal MFM_STATE		: MFM_STATES;
+signal NEXT_MFM_STATE	: MFM_STATES;
+signal PRECOMP			: PRECOMP_VALUES;
+signal DEC_STATE		: DEC_STATES;
+signal NEXT_DEC_STATE	: DEC_STATES;
+
+signal FM_In			: bit;
+
+signal CLKMASK 			: bit; -- Control for suppression of FM clock transitions.
+
+signal MFM_10_STRB		: bit;
+signal MFM_01_STRB		: bit;
+
+signal WR_CNT 			: std_logic_vector(3 downto 0);
+signal MFM_In			: bit;
+
+signal AM_SHFT			: bit_vector(31 downto 0);
+
+begin
+	-- #######################  encoder stuff  ###########################
+	ADRMARK: process(RESETn, CLK)
+	-- This process provides the address mark data for both FM and MFM in
+	-- write to disk mode. In FM only one byte is written where in MFM
+	-- 3 sync bytes x"A1" and one data address mark is written. 
+	-- In this process only the data address mark is provided. The only way
+	-- writing the ID address mark is the write track command.
+	begin
+		if RESETn = '0' then
+			AM_SHFT <= (others => '0');
+		elsif CLK = '1' and CLK' event then
+			if AM_2_DISK = '1' and DATA_STRB = '1' then
+				AM_SHFT <= AM_SHFT (30 downto 0) & '0'; -- Shift out.
+			elsif AM_2_DISK = '0' and DDEn = '1'  and AM_TYPE = '0' then -- FM mode.
+				AM_SHFT <= x"F8000000"; -- Load deleted FM address mark.
+			elsif AM_2_DISK = '0' and DDEn = '1'  and AM_TYPE = '1' then -- FM mode.
+				AM_SHFT <= x"FB000000"; -- Load normal FM address mark.
+			elsif AM_2_DISK = '0' and DDEn = '0' and AM_TYPE = '0' then -- MFM mode deleted data mark.
+				AM_SHFT <= x"A1A1A1F8"; -- Load MFM syncs and address mark.
+			elsif AM_2_DISK = '0' and DDEn = '0' and AM_TYPE = '1' then -- Default: MFM mode normal data mark.
+				AM_SHFT <= x"A1A1A1FB"; -- Load MFM syncs and address mark.
+			end if;
+		end if;
+	end process ADRMARK;
+
+	-- Input multiplexer:
+	WDATA <= 	AM_SHFT(31) when AM_2_DISK = '1' else -- Address mark data data.
+				To_Bit(SR_SDOUT) when DSR_2_DISK = '1' else -- Shift register data.
+				CRC_SDOUT when CRC_2_DISK = '1' else -- CRC data.
+				'1' when FF_2_DISK = '1' else '0'; -- Write zeros is default.
+
+	-- Output multiplexer:
+	WRn <= 	'0' when FM_In = '0' and DDEn = '1' else -- FM portion.
+			'0' when MFM_In = '0' and DDEn = '0' else '1'; -- MFM portion and default.
+
+	CLK_MASK: process(CLK)
+	-- This part of software controls the suppression of the clock pulses
+	-- during transmission of several FM special characters. During writing
+	-- 'normal' data to the disk, only 8 mask bits of the shift register are
+	-- used. During writing MFM sync and address mark bits, the register is
+	-- used with 32 mask bits.
+	variable MASK_SHFT	: bit_vector(23 downto 0);
+	variable LOCK		: boolean;
+	begin
+		if CLK = '1' and CLK' event then
+			if RESETn = '0' then
+				MASK_SHFT := (others => '1');
+				LOCK := false;
+			-- Load the mask shift register just in time when the shift register is
+			-- loaded with valid data from the data register.
+			elsif SHFT_LOAD_SD = '1' and DDEn = '1' then -- FM mode.
+				case DR is
+					when x"F8" | x"F9" | x"FA" | x"FB" | x"FE" => MASK_SHFT := x"C7FFFF";
+					when x"FC" => MASK_SHFT := x"D7FFFF";
+					when x"F5" | x"F6" => MASK_SHFT := (others => '0'); -- Not allowed.
+					when others => MASK_SHFT := x"FFFFFF"; -- Normal data.
+				end case;
+			elsif SHFT_LOAD_SD = '1' and DDEn = '0' then -- MFM mode.
+				case DR is
+					when x"F5" => MASK_SHFT := x"FBFFFF"; -- Suppress clock pulse between bits 4 and 5.
+					when x"F6" => MASK_SHFT := x"F7FFFF"; -- Suppress clock pulse between bits 3 and 4.
+					when others => MASK_SHFT := x"FFFFFF"; -- Normal data.
+				end case;
+			elsif AM_2_DISK = '1' and DDEn = '1' and LOCK = false then -- FM mode.
+				MASK_SHFT := x"C7FFFF"; -- Load just once per AM_2_DISK rising edge.
+				LOCK := true;
+			elsif AM_2_DISK = '1' and DDEn = '0' and LOCK = false then -- MFM mode.
+				MASK_SHFT := x"FBFBFB"; -- Three syncs with suppressed clock pulse then transparent mask.
+				LOCK := true;
+			elsif DATA_STRB = '1' then  -- shift as long as transmission is active
+				-- The Shift register is shifted left. After shifting the clockmasks out it is
+				-- transparent due to the '1's filled up from the left.
+				MASK_SHFT := MASK_SHFT(22 downto 0) & '1'; -- Shift left.
+			elsif AM_2_DISK = '0' then
+				LOCK := false; -- Release the lock after address mark has been written.
+			end if;
+		end if;
+		CLKMASK <= MASK_SHFT(23);
+	end process CLK_MASK;
+
+	FM_ENCODER: process (RESETn, DATA_STRB, CLK)
+	-- For DD type floppies the data rate is 125kBps. Therefore there are 128 16-MHz clocks cycles
+	-- per FM bit. 
+	-- For HD type floppies the data rate is 250kBps. Therefore there are 64 16-MHz clocks cycles
+	-- per FM bit. 
+	-- The FM write pulse width is 1.375us for DD and 0.750us HD type floppies.
+	-- This process provides the FM encoded signal. The first pulse is in any case the clock
+	-- pulse and the second pulse is due to data. The FM encoding is very simple and therefore
+	-- self explaining.
+	variable CNT : std_logic_vector(7 downto 0);
+	begin
+		if RESETn = '0' then
+			FM_In <= '1';
+			CNT := x"00";
+		elsif CLK = '1' and CLK' event then
+			-- In case of HD type floppies the counter reaches a value of b"0100000"
+			-- In case of DD type floppies the counter reaches a value of b"1000000"
+			if DATA_STRB = '1' then
+				CNT := x"00";
+			else
+				CNT := CNT + '1';
+			end if;
+			-- The flux reversal pulses are centered between the DATA_STRB pulses.
+			-- In detail: the clock pulse appears in the middle of the first half
+			-- of the DATA_STRB period and the data pulse appears in the middle of
+			-- the second half.
+			case HDTYPE is
+				when '0' => -- DD type floppies:
+					if CNT > "00010101" and CNT <= "00101011" then
+						FM_In <= not CLKMASK; -- FM clock.
+					elsif CNT > "01010101" and CNT <= "01101011" then
+						FM_In <= not WDATA; -- FM data.
+					else
+						FM_In <= '1';
+					end if;
+				when '1' => -- HD type floppies:
+					if CNT > "00001010" and CNT <= "00010110" then
+						FM_In <= not CLKMASK; -- FM clock.
+					elsif CNT > "00101010" and CNT <= "00110110" then
+						FM_In <= not WDATA; -- FM data.
+					else
+						FM_In <= '1';
+					end if;
+			end case;
+		end if;
+	end process FM_ENCODER;
+	
+	MFM_ENCODE_REG: process(RESETn, CLK)
+	-- This process is the first portion of the more complicated MFM encoder. It can be interpreted
+	-- as a Moore machine. This part is the current state register.
+	begin
+		if RESETn = '0' then
+			MFM_STATE <= A_00;
+		elsif CLK = '1' and CLK' event then
+			MFM_STATE <= NEXT_MFM_STATE;
+		end if;
+	end process MFM_ENCODE_REG;
+
+	MFM_ENCODE_LOGIC: process(MFM_STATE, WDATA, DATA_STRB)
+	-- Rules for Encoding:
+		-- transitions are never located at the mid point of a 'zero'.
+		-- transistions are always located at the mid point of a '1'.
+		-- no transitions at the borders of a '1'.
+		-- transitions appear between two adjacent 'zeros'.
+	-- states are as follows:
+	-- A_00: idle state, no transition.
+	-- B_01: transistion between the MFM clock edges.
+	-- C_10: transition on the leading MFM clock edges.
+	-- The timing of the MFM output is done in the process MFM_WR_OUT.
+	begin
+		case MFM_STATE is
+			when A_00 =>
+				if WDATA = '0' and DATA_STRB = '1' then
+					NEXT_MFM_STATE <= C_10;
+				elsif  WDATA = '1' and DATA_STRB = '1' then
+					NEXT_MFM_STATE <= B_01;
+				else
+					NEXT_MFM_STATE <= A_00; -- Stay, if there is no strobe.
+				end if;
+			when C_10 =>
+				if WDATA = '0' and DATA_STRB = '1' then
+					NEXT_MFM_STATE <= C_10;
+				elsif  WDATA = '1' and DATA_STRB = '1' then
+					NEXT_MFM_STATE <= B_01;
+				else
+					NEXT_MFM_STATE <= C_10; -- Stay, if there is no strobe.
+				end if;
+			when B_01 =>
+				if WDATA = '0' and DATA_STRB = '1' then
+					NEXT_MFM_STATE <= A_00;
+				elsif  WDATA = '1' and DATA_STRB = '1' then
+					NEXT_MFM_STATE <= B_01;
+				else
+					NEXT_MFM_STATE <= B_01; -- Stay, if there is no strobe.
+				end if;
+		end case;
+	end process MFM_ENCODE_LOGIC;
+
+	MFM_PRECOMPENSATION: process(RESETn, CLK)
+	-- The write pattern is adjusted in the MFM write timing process as follows:
+	-- after DATA_STRB (the duty cycle of this strobe is exactly one CLK) the
+	-- incoming data is bufferd in WRITEPATTERN. After the following DATA_STRB
+	-- the WDATA is shifted through WRITEPATTERN. After further DATA_STRBs the
+	-- WRITEPATTERN consists of previous, current and next WDATA like this:
+	-- WRITEPATTERN(3) is the second previous WDATA.
+	-- WRITEPATTERN(2) is the previous WDATA.
+	-- WRITEPATTERN(1) is the current WDATA to be sent.
+	-- WRITEPATTERN(0) is the next WDATA to be sent.
+	variable WRITEPATTERN : bit_vector(3 downto 0);
+	begin
+		if RESETn = '0' then
+			PRECOMP <= NOMINAL;
+			WRITEPATTERN := "0000";
+		elsif CLK = '1' and CLK' event then
+			if DATA_STRB = '1' then
+				WRITEPATTERN := WRITEPATTERN(2 downto 0) & WDATA; -- shift left
+			end if;
+			if PRECOMP_EN = '0' then
+				PRECOMP <= NOMINAL; -- no precompensation
+			else
+				case WRITEPATTERN is
+					when "1110" | "0110" => PRECOMP <= EARLY;
+					when "1011" | "0011" => PRECOMP <= LATE;
+					when "0001" => PRECOMP <= EARLY;
+					when "1000" => PRECOMP <= LATE;
+					when others => PRECOMP <= NOMINAL;
+				end case;
+			end if;
+		end if;
+	end process MFM_PRECOMPENSATION;
+
+	MFM_STROBES: process (RESETn, DATA_STRB, CLK)
+	-- For the MFM frequency is 250 kBps for DD type floppies, there are 64 
+	-- 16 MHz clock cycles per MFM bit and for HD type floppies, which have
+	-- 500 kBps there are 32 16MHz clock pulses for one MFM bit.
+	-- The MFM state machine (Moore) switches on the DATA_STRB. 
+	-- During one cycle there are the two further strobes MFM_10_STRB and 
+	-- MFM_01_STRB which control the MFM output in the process MFM_WR_OUT.
+	-- The strobes are centered in the middle of the first half and in the
+	-- middle of the second half of the DATA_STRB cycle.
+	variable CNT : std_logic_vector(5 downto 0);
+	begin
+		if RESETn = '0' then
+			CNT := "000000";
+		elsif CLK = '1' and CLK' event then
+			if DATA_STRB = '1' then
+				CNT := (others => '0');
+			else
+				CNT := CNT + '1';
+			end if;
+			if HDTYPE = '1' then
+				case CNT is
+					-- encoder timing for MFM and HD type floppies.
+				when "000100" => MFM_10_STRB <= '1'; MFM_01_STRB <= '0'; -- Pulse centered in the first half.
+				when "010100" => MFM_10_STRB <= '0'; MFM_01_STRB <= '1'; -- Pulse centered in the second half.
+					when others =>  MFM_10_STRB <= '0'; MFM_01_STRB <= '0';
+				end case;
+			else
+				case CNT is
+					-- encoder timing for MFM and DD type floppies.
+				when "001010" => MFM_10_STRB <= '1'; MFM_01_STRB <= '0'; -- Pulse centered in the first half.
+				when "101000" => MFM_10_STRB <= '0'; MFM_01_STRB <= '1'; -- Pulse centered in the second half.
+					when others =>  MFM_10_STRB <= '0'; MFM_01_STRB <= '0';
+				end case;
+			end if;
+		end if;
+	end process MFM_STROBES;
+
+	-- MFM_WR_TIMING generates the timing for the write pulses which are 
+	-- required by a MFM device like floppy disk drive. The pulse timing 
+	-- meets the timing of the MFM data with pulse width of 700ns +/- 100ns 
+	-- depending on write precompensation.
+	-- The original WD1772 (CLK = 8MHz) data timing was as follows:
+	-- The output is asserted as long as CNT is active; in detail
+	-- this are 4,5; 5,5 or 6,5 CLK cycles depending on the write
+	-- precompensation.
+	-- The new design which works with a 16MHz clock requires the following
+	-- timing: 9; 11 or 13 CLK cycles depending on the writeprecompensation
+	-- for DD floppies and 5; 6 or 7 CLK cycles depending on the write
+	-- precompensation for HD floppies.
+	-- To meet the timing requirements of half clocks
+	-- the WRn is controlled by the following three processes where the one
+	-- syncs on the positive clock edge and the other on the negative.
+	-- For more information on the WTn timing see the datasheet of the
+	-- WD177x floppy disc controller.
+
+	MFM_WR_TIMING: process(RESETn, CLK)
+	variable CLKMASK_MFM	: bit;
+	begin
+		if RESETn = '0' then
+			WR_CNT <= x"F";
+		elsif CLK = '1' and CLK' event then
+			if DATA_STRB = '1' then
+				-- The CLKMASK_MFM is synchronised to DATA_STRB. This brings one strobe latency.
+				-- The timing in connection with the data is correct because the MFM encoder state machine
+				-- causes the data to be 1 DATA_STRB late too.
+				CLKMASK_MFM := CLKMASK;
+			end if;
+			if MFM_STATE = C_10 and MFM_10_STRB = '1' and CLKMASK_MFM = '1' then
+				WR_CNT <= x"0";
+			elsif MFM_STATE =  B_01 and MFM_01_STRB = '1' then
+				WR_CNT <= x"0";
+			elsif WR_CNT < x"F" then
+				WR_CNT <= WR_CNT + '1';
+			end if;
+		end if;
+	end process MFM_WR_TIMING;
+
+	MFM_WR_OUT: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' then
+			MFM_In <= '1';
+		else
+			case HDTYPE is
+				when '1' => -- HD type.
+					if PRECOMP = EARLY and WR_CNT > x"0" and WR_CNT <= x"9" then
+						MFM_In <= '0'; -- 9,0 clock cycles for WRn --> early timing
+					elsif PRECOMP = NOMINAL and WR_CNT > x"0" and WR_CNT <= x"8" then
+						MFM_In <= '0'; -- 8,0 clock cycles for WRn --> nominal timing
+					elsif PRECOMP = LATE and WR_CNT > x"0" and WR_CNT <= x"7" then
+						MFM_In <= '0'; -- 7,0 clock cycles for WRn --> late timing
+					else
+						MFM_In <= '1';
+					end if;
+				when '0' => -- DD type.
+					if PRECOMP = EARLY and WR_CNT > x"0" and WR_CNT <= x"D" then
+						MFM_In <= '0'; -- 13,0 clock cycles for WRn --> early timing
+					elsif PRECOMP = NOMINAL and WR_CNT > x"0" and WR_CNT <= x"B" then
+						MFM_In <= '0'; -- 11,0 clock cycles for WRn --> nominal timing
+					elsif PRECOMP = LATE and WR_CNT > x"0" and WR_CNT <= x"9" then
+						MFM_In <= '0'; -- 9,0 clock cycles for WRn --> late timing
+					else
+						MFM_In <= '1';
+					end if;
+			end case;
+		end if;
+	end process MFM_WR_OUT;
+
+	-- #######################  Decoder stuff  ###########################
+	-- The decoding of the serial FM or MFM encoded data stream
+	-- is done in the following two processes (Moore machine).
+	-- The decoder works in principle like a simple toggle Flip-Flop.
+	-- It is important to synchronise it in a way, that the clock
+	-- pulses are separated from the data pulses. The principle
+	-- works for both FM and MFM data due to the digital phase
+	-- locked loop, which delivers the serial data and the clock
+	-- strobe. In general this decoder can be understood as the
+	-- data separator where the digital phase locked loop provides
+	-- the FM or the MFM decoding. The data separation lives from
+	-- the fact, that FM and also MFM encoded signals consist of a
+	-- mixture of alternating data and clock pulses. 
+	-- FM works as follows:
+	-- every first pulse of the FM signal is a clock pulse and every
+	-- second pulse is a logic '1' of the data. A missing second 
+	-- pulse represents a logic '0' of the data.
+	-- MFM works as follows:
+	-- every first pulse of the MFM signal is a clock pulse. The coding
+	-- principle causes clock pulses to be absent in some conditions.
+	-- Every second pulse is a logic '1' of the data. A missing second 
+	-- pulse represents a logic '0' of the data.
+	-- So FM and MFM compared, the data is represented directly by the
+	-- second pulses and the data separator has to look only for these.
+	-- The missing MFM clock pulses do not cause a problem because the
+	-- digital PLL used in conjunction with this data separator fills
+	-- up the clock pulses and delivers a PLL_DSTRB containing aequidistant
+	-- clock strobes and data strobes.
+
+	DEC_REG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DEC_STATE <= CLK_PHASE;
+		elsif CLK = '1' and CLK' event then
+			DEC_STATE <= NEXT_DEC_STATE;
+		end if;
+	end process DEC_REG;
+
+	DEC_LOGIC: process(DEC_STATE, ID_AM, DATA_AM, DDATA_AM, PLL_DSTRB, PLL_D)
+	begin
+		case DEC_STATE is
+			when CLK_PHASE =>
+				if PLL_DSTRB = '1' then
+					NEXT_DEC_STATE <= DATA_PHASE;
+				else
+					NEXT_DEC_STATE <= CLK_PHASE;
+				end if;
+				DATA_STRB <= '0'; -- Inactive during clock pulse time.
+				SD_R <= '0'; -- Inactive during clock pulse time.
+			when DATA_PHASE =>
+				if ID_AM = '1' or DATA_AM = '1' or DDATA_AM = '1' then
+					-- Here the state machine is synchronised
+					-- to separate data and clock pulses correctly.
+					NEXT_DEC_STATE <= CLK_PHASE;
+				elsif PLL_DSTRB = '1' then
+					NEXT_DEC_STATE <= CLK_PHASE;
+				else
+					NEXT_DEC_STATE <= DATA_PHASE;
+				end if;
+				-- During the data phase valid data appears at SD.
+				-- The data is valid during DATA_STRB.
+				DATA_STRB <= PLL_DSTRB;
+				SD_R <= PLL_D;
+		end case;
+	end process DEC_LOGIC;
+end architecture BEHAVIOR;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
new file mode 100644
index 0000000..7660aa2
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
@@ -0,0 +1,141 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- MC68901 compatible multi function port core.                 ----
+----                                                              ----
+---- This are the SUSKA MFP IP core's general purpose I/Os.       ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF68901IP_GPIO is
+	port (  -- System control:
+			CLK			: in bit;
+			RESETn		: in bit;
+			
+			-- Asynchronous bus control:
+			DSn			: in bit;
+			CSn			: in bit;
+			RWn			: in bit;
+			
+			-- Data and Adresses:
+			RS			: in bit_vector(5 downto 1);
+			DATA_IN		: in bit_vector(7 downto 0);
+			DATA_OUT	: out bit_vector(7 downto 0);
+			DATA_OUT_EN	: out bit;
+
+			-- Timer controls:
+			AER_4		: out bit;
+			AER_3		: out bit;
+
+			GPIP_IN		: in bit_vector(7 downto 0);
+			GPIP_OUT	: out bit_vector(7 downto 0);
+			GPIP_OUT_EN	: buffer bit_vector(7 downto 0);
+			GP_INT		: out bit_vector(7 downto 0)
+	);
+end entity WF68901IP_GPIO;
+
+architecture BEHAVIOR of WF68901IP_GPIO is
+signal GPDR		: bit_vector(7 downto 0);
+signal DDR		: bit_vector(7 downto 0);
+signal AER		: bit_vector(7 downto 0);
+signal GPDR_I	: bit_vector(7 downto 0);
+begin
+	-- These two bits control the timers A and B pulse width operation and the
+	-- timers A and B event count operation.
+	AER_4 <= AER(4);
+	AER_3 <= AER(3);
+	-- This statement provides 8 XOR units setting the desired interrupt polarity.
+	-- While the level control is done here, the edge triggering is provided by
+	-- the interrupt control hardware. The level control is individually for each
+	-- GPIP port pin. The interrupt edge trigger unit must operate in any case on
+	-- the low to high transistion of the respective port pin.
+	GP_INT <= AER xnor GPIP_IN;
+	
+	GPIO_REGISTERS: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			GPDR <= (others => '0');
+			DDR <= (others => '0');
+			AER <= (others => '0');
+		elsif CLK = '1' and CLK' event then
+			if 	CSn = '0' and DSn = '0' and RWn = '0' then
+				case RS is
+					when "00000"	=> GPDR <= DATA_IN;
+					when "00001"	=> AER <= DATA_IN;
+					when "00010"	=> DDR <= DATA_IN;
+					when others		=> null;
+				end case;
+			end if;
+		end if;
+	end process GPIO_REGISTERS;
+	GPIP_OUT <= GPDR; -- Port outputs.
+	GPIP_OUT_EN <= DDR; -- The DDR is capable to control bitwise the GPIP.
+	DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS <= "00010" else '0';
+	DATA_OUT <= DDR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00010" else
+				AER when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00001" else
+				GPDR_I when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00000" else (others => '0');
+	
+	P_GPDR: process(GPIP_IN, GPIP_OUT_EN, GPDR)
+	-- Read back control: Read the port pins, if the data direction is configured as input.
+	-- Read the respective GPDR register bit, if the data direction is configured as output.
+	begin
+		for i in 7 downto 0 loop
+			if GPIP_OUT_EN(i) = '1' then -- Port is configured output.
+				GPDR_I(i) <= GPDR(i);
+			else
+				GPDR_I(i) <= GPIP_IN(i); -- Port is configured input.
+			end if;
+		end loop;
+	end process P_GPDR;
+end architecture BEHAVIOR;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd
new file mode 100644
index 0000000..91417f8
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd
@@ -0,0 +1,391 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- MC68901 compatible multi function port core.                 ----
+----                                                              ----
+---- This is the SUSKA MFP IP core interrupt logic file.          ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/06/03 WF
+--   Fixed Pending register logic.
+-- Revision 2K9A  2009/06/20 WF
+--   Fixed interrupt polarity for TA_I and TB_I.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF68901IP_INTERRUPTS is
+	port (  -- System control:
+			CLK			: in bit;
+			RESETn		: in bit;
+			
+			-- Asynchronous bus control:
+			DSn			: in bit;
+			CSn			: in bit;
+			RWn			: in bit;
+			
+			-- Data and Adresses:
+			RS			: in bit_vector(5 downto 1);
+			DATA_IN		: in bit_vector(7 downto 0);
+			DATA_OUT	: out bit_vector(7 downto 0);
+			DATA_OUT_EN	: out bit;
+
+			-- Interrupt control:
+			IACKn		: in bit;
+			IEIn		: in bit;
+			IEOn		: out bit;
+			IRQn		: out bit;
+			
+			-- Interrupt sources:
+			GP_INT		: in bit_vector(7 downto 0);
+
+			AER_4		: in bit;
+			AER_3		: in bit;
+			TAI			: in bit;
+			TBI			: in bit;
+			TA_PWM		: in bit;
+			TB_PWM		: in bit;
+			TIMER_A_INT	: in bit;
+			TIMER_B_INT	: in bit;
+			TIMER_C_INT	: in bit;
+			TIMER_D_INT	: in bit;
+
+			RCV_ERR		: in bit;
+			TRM_ERR		: in bit;
+			RCV_BUF_F	: in bit;
+			TRM_BUF_E	: in bit
+	);
+end entity WF68901IP_INTERRUPTS;
+
+architecture BEHAVIOR of WF68901IP_INTERRUPTS is
+-- Interrupt state machine:
+type INT_STATES is (SCAN, REQUEST, VECTOR_OUT);
+signal INT_STATE : INT_STATES;
+-- The registers:
+signal IERA			: bit_vector(7 downto 0);
+signal IERB			: bit_vector(7 downto 0);
+signal IPRA			: bit_vector(7 downto 0);
+signal IPRB			: bit_vector(7 downto 0);
+signal ISRA			: bit_vector(7 downto 0);
+signal ISRB			: bit_vector(7 downto 0);
+signal IMRA			: bit_vector(7 downto 0);
+signal IMRB			: bit_vector(7 downto 0);
+signal VR			: bit_vector(7 downto 3);
+-- Interconnect:
+signal VECT_NUMBER	: bit_vector(7 downto 0);
+signal INT_SRC		: bit_vector(15 downto 0);
+signal INT_SRC_EDGE	: bit_vector(15 downto 0);
+signal INT_ENA		: bit_vector(15 downto 0);
+signal INT_MASK		: bit_vector(15 downto 0);
+signal INT_PENDING	: bit_vector(15 downto 0);
+signal INT_SERVICE	: bit_vector(15 downto 0);
+signal INT_PASS		: bit_vector(15 downto 0);
+signal INT_OUT		: bit_vector(15 downto 0);
+signal GP_INT_4		: bit;
+signal GP_INT_3		: bit;
+begin
+	-- Interrupt source for the GPI_4 and GPI_3 is normally the respective port pin.
+	-- But when the timers operate in their PWM modes, the GPI_4 and GPI_3 are associated
+	-- to timer A and timer B.
+	-- The xor logic provides polarity control for the interrupt transition. Be aware,
+	-- that the PWM signals cause an interrupt on the opposite transition like the
+	-- respective GPIP port pins (with the same AER settings).
+    --GP_INT_4 <= GP_INT(4) when TA_PWM = '0' else TAI xor AER_4;
+    --GP_INT_3 <= GP_INT(3) when TB_PWM = '0' else TBI xor AER_3;
+    GP_INT_4 <= GP_INT(4) when TA_PWM = '0' else TAI xnor AER_4; -- This should be correct.
+    GP_INT_3 <= GP_INT(3) when TB_PWM = '0' else TBI xnor AER_3;
+
+
+	-- Interrupt source priority sorted (15 = highest):
+    INT_SRC <= 	GP_INT(7 downto 6) & TIMER_A_INT & RCV_BUF_F & RCV_ERR & TRM_BUF_E & TRM_ERR & TIMER_B_INT & 
+    GP_INT(5) & GP_INT_4 & TIMER_C_INT & TIMER_D_INT & GP_INT_3 & GP_INT(2 downto 0);
+
+	INT_ENA 	<= IERA & IERB;
+	INT_MASK 	<= IMRA & IMRB;
+	INT_PENDING <= IPRA & IPRB;
+	INT_SERVICE <= ISRA & ISRB;
+	INT_OUT 	<= INT_PENDING and INT_MASK; -- Masking:
+
+	-- Enable the daisy chain, if there is no pending interrupt and
+	-- the interrupt state machine is not in service.
+	IEOn <= '0' when INT_OUT = x"0000" and INT_STATE = SCAN else '1';
+
+	-- Interrupt request:
+	IRQn <= '0' when INT_OUT /= x"0000" and INT_STATE = REQUEST else '1';
+
+	EDGE_ENA: process(RESETn, CLK)
+	-- These are the 16 edge detectors of the 16 interrupt input sources. This
+	-- process also provides the disabling or enabling via the IERA and IERB registers.
+	variable LOCK : bit_vector(15 downto 0);
+	begin
+		if RESETn = '0' then
+			INT_SRC_EDGE <= x"0000";
+			LOCK := x"0000";
+		elsif CLK = '1' and CLK' event then
+			for i in 15 downto 0 loop
+				if INT_SRC(i) = '1' and INT_ENA(i) = '1' and LOCK(i) = '0' then
+					LOCK(i) := '1';
+					INT_SRC_EDGE(i) <= '1';
+				elsif INT_SRC(i) = '0' then
+					LOCK(i) := '0';
+					INT_SRC_EDGE(i) <= '0';
+				else
+					INT_SRC_EDGE(i) <= '0';
+				end if;
+			end loop;
+		end if;
+	end process EDGE_ENA;
+	
+	INT_REGISTERS: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			IERA <= (others => '0');
+			IERB <= (others => '0');
+			IPRA <= (others => '0');
+			IPRB <= (others => '0');
+			ISRA <= (others => '0');
+			ISRB <= (others => '0');
+			IMRA <= (others => '0');
+			IMRB <= (others => '0');
+		elsif CLK = '1' and CLK' event then
+			if 	CSn = '0' and DSn = '0' and RWn = '0' then
+				case RS is
+					when "00011"	=> IERA <= DATA_IN; -- Enable A.
+					when "00100"	=> IERB <= DATA_IN; -- Enable B.
+					when "00101"	=>
+						-- Only a '0' can be written to the pending register.
+						for i in 7 downto 0 loop
+							if DATA_IN(i) = '0' then
+								IPRA(i) <= '0'; -- Pending A.
+							end if;
+						end loop;
+					when "00110"	=>
+						-- Only a '0' can be written to the pending register.
+						for i in 7 downto 0 loop
+							if DATA_IN(i) = '0' then
+								IPRB(i) <= '0'; -- Pending B.
+							end if;
+						end loop;
+					when "00111"	=> 
+						-- Only a '0' can be written to the in service register.
+						for i in 7 downto 0 loop
+							if DATA_IN(i) = '0' then
+								ISRA(i) <= '0'; -- In Service A.
+							end if;
+						end loop;
+					when "01000"	=>
+						-- Only a '0' can be written to the in service register.
+						for i in 7 downto 0 loop
+							if DATA_IN(i) = '0' then
+								ISRB(i) <= '0'; -- In Service B.
+							end if;
+						end loop;
+					when "01001"	=> IMRA <= DATA_IN; -- Mask A.
+					when "01010"	=> IMRB <= DATA_IN; -- Mask B.
+					when "01011"	=> VR <= DATA_IN(7 downto 3); -- Vector register.
+					when others		=> null;
+				end case;
+			end if;
+
+			-- Pending register:
+			-- set and clear bit logic.
+			for i in 15 downto 8 loop
+				if INT_SRC_EDGE(i) = '1' then
+					IPRA(i-8) <= '1';
+				elsif INT_ENA(i) = '0' then
+					IPRA(i-8) <= '0'; -- Clear by disabling the channel.
+				elsif INT_PASS(i) = '1' then
+					IPRA(i-8) <= '0'; -- Clear by passing the interrupt.
+				end if;
+			end loop;
+			for i in 7 downto 0 loop
+				if INT_SRC_EDGE(i) = '1' then
+					IPRB(i) <= '1';
+				elsif INT_ENA(i) = '0' then
+					IPRB(i) <= '0'; -- Clear by disabling the channel.
+				elsif INT_PASS(i) = '1' then
+					IPRB(i) <= '0'; -- Clear by passing the interrupt.
+				end if;
+			end loop;
+
+			-- In-Service register:
+			-- Set bit logic, VR(3) is the service register enable.
+			for i in 15 downto 8 loop
+				if INT_OUT(i) = '1' and INT_PASS(i) = '1' and VR(3) = '1' then
+					ISRA(i-8) <= '1';
+				end if;
+			end loop;
+			for i in 7 downto 0 loop
+				if INT_OUT(i) = '1' and INT_PASS(i) = '1' and VR(3) = '1' then
+					ISRB(i) <= '1';
+				end if;
+			end loop;
+		end if;
+	end process INT_REGISTERS;
+	DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS > "00010" and RS <= "01011" else 																	 '1' when INT_STATE = VECTOR_OUT else '0';
+
+	DATA_OUT <= IERA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00011" else
+				IERB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00100" else
+				IPRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00101" else
+				IPRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00110" else
+				ISRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00111" else
+				ISRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01000" else
+				IMRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01001" else
+				IMRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01010" else
+				VR & "000" when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01011" else
+				VECT_NUMBER when INT_STATE = VECTOR_OUT else x"00";
+
+	P_INT_STATE	: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			INT_STATE <= SCAN;
+		elsif CLK = '1' and CLK' event then
+			case INT_STATE is
+				when SCAN =>
+					INT_PASS <= x"0000";
+					-- Automatic End of Interrupt mode. Service register disabled.
+					-- The MFP does not respond for an interrupt acknowledge cycle for an uninitialized
+					-- vector number (VR(7 downto 4) = x"0").
+					if INT_OUT /= x"0000" and VR(7 downto 4) /= x"0" and VR(3) = '0' and IEIn = '0' then
+						INT_STATE <= REQUEST; -- Non masked interrupt is pending.
+					-- The following 16 are the Software end of interrupt mode. Service register enabled.
+					-- The MFP does not respond for an interrupt acknowledge cycle for an uninitialized
+					-- vector number (VR(7 downto 4) = x"0"). The interrupts are prioritized.
+					elsif INT_OUT /= x"0000" and VR(7 downto 4) /= x"0" and VR(3) = '1' and IEIn = '0' then
+						if INT_OUT (15) = '1' and INT_SERVICE(15) = '0' then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (14) = '1' and INT_SERVICE(15 downto 14) = "00" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (13) = '1' and INT_SERVICE(15 downto 13) = "000" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (12) = '1' and INT_SERVICE(15 downto 12) = x"0" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (11) = '1' and INT_SERVICE(15 downto 11) = x"0" & '0' then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (10) = '1' and INT_SERVICE(15 downto 10) = x"0" & "00" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (9) = '1' and INT_SERVICE(15 downto 9) = x"0" & "000" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (8) = '1' and INT_SERVICE(15 downto 8) = x"00" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (7) = '1' and INT_SERVICE(15 downto 7) = x"00" & '0' then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (6) = '1' and INT_SERVICE(15 downto 6) = x"00" & "00" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (5) = '1' and INT_SERVICE(15 downto 5) = x"00" & "000" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (4) = '1' and INT_SERVICE(15 downto 4) = x"000" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (3) = '1' and INT_SERVICE(15 downto 3) = x"000" & '0' then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (2) = '1' and INT_SERVICE(15 downto 2) = x"000" & "00" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (1) = '1' and INT_SERVICE(15 downto 1) = x"000" & "000" then
+							INT_STATE <= REQUEST;
+						elsif INT_OUT (0) = '1' and INT_SERVICE(15 downto 0) = x"0000" then
+							INT_STATE <= REQUEST;
+						else
+							INT_STATE <= SCAN; -- Wait for interrupt.
+						end if;
+					else
+						INT_STATE <= SCAN;
+					end if;
+				when REQUEST =>
+					if IACKn = '0' and DSn = '0' then -- Vectored interrupt mode.
+						INT_STATE <= VECTOR_OUT; -- Non masked interrupt is pending.
+						if INT_OUT(15) = '1' then 
+							INT_PASS(15) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"F"; -- GPI 7.
+						elsif INT_OUT(14) = '1' then 
+							INT_PASS(14) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"E"; -- GPI 6.
+						elsif INT_OUT(13) = '1' then 
+							INT_PASS(13) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"D"; -- TIMER A.
+						elsif INT_OUT(12) = '1' then 
+							INT_PASS(12) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"C"; -- Receive buffer full.
+						elsif INT_OUT(11) = '1' then 
+							INT_PASS(11) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"B"; -- Receiver error.
+						elsif INT_OUT(10) = '1' then 
+							INT_PASS(10) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"A"; -- Transmit buffer empty.
+						elsif INT_OUT(9) = '1' then 
+							INT_PASS(9) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"9"; -- Transmit error.
+						elsif INT_OUT(8) = '1' then 
+							INT_PASS(8) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"8"; -- Timer B.
+						elsif INT_OUT(7) = '1' then 
+							INT_PASS(7) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"7"; -- GPI 5.
+						elsif INT_OUT(6) = '1' then 
+							INT_PASS(6) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"6"; -- GPI 4.
+						elsif INT_OUT(5) = '1' then 
+							INT_PASS(5) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"5"; -- Timer C.
+						elsif INT_OUT(4) = '1' then 
+							INT_PASS(4) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"4"; -- Timer D.
+						elsif INT_OUT(3) = '1' then 
+							INT_PASS(3) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"3"; -- GPI 3.
+						elsif INT_OUT(2) = '1' then 
+							INT_PASS(2) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"2"; -- GPI 2.
+						elsif INT_OUT(1) = '1' then 
+							INT_PASS(1) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"1"; -- GPI 1.
+						elsif INT_OUT(0) = '1' then 
+							INT_PASS(0) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"0"; -- GPI 0.
+						end if;
+					 -- Polled interrupt mode: End of interrupt by writing to the pending registers.
+					elsif CSn = '0' and DSn = '0' and RWn = '0' and (RS = "00101" or RS = "00110") then
+						INT_STATE <= SCAN;
+					else
+						INT_STATE <= REQUEST; -- Wait.
+					end if;
+				when VECTOR_OUT =>
+					INT_PASS <= x"0000";
+					if DSn = '1' or IACKn = '1' then
+						INT_STATE <= SCAN; -- Finished.
+					else
+						INT_STATE <= VECTOR_OUT; -- Wait for processor to read the vector.
+					end if;
+			end case;
+		end if;
+	end process P_INT_STATE;
+end architecture BEHAVIOR;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd
new file mode 100644
index 0000000..73c0cdc
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd
@@ -0,0 +1,263 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- MC68901 compatible multi function port core.                 ----
+----                                                              ----
+---- This is the package file containing the component            ----
+---- declarations.                                                ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package WF68901IP_PKG is
+component WF68901IP_USART_TOP
+	port (  CLK			: in bit;
+			RESETn		: in bit;
+			DSn			: in bit;
+			CSn			: in bit;
+			RWn			: in bit;
+			RS			: in bit_vector(5 downto 1);
+			DATA_IN		: in bit_vector(7 downto 0);
+			DATA_OUT	: out bit_vector(7 downto 0);
+			DATA_OUT_EN	: out bit;
+			RC			: in bit;
+			TC			: in bit;
+			SI			: in bit;
+			SO			: out bit;
+			SO_EN		: out bit;
+			RX_ERR_INT	: out bit;
+			RX_BUFF_INT	: out bit;
+			TX_ERR_INT	: out bit;
+			TX_BUFF_INT	: out bit;
+			RRn			: out bit;
+			TRn			: out bit			
+	);
+end component;
+
+component WF68901IP_USART_CTRL
+	port (
+		CLK				: in bit;
+        RESETn			: in bit;
+        DSn				: in bit;
+        CSn				: in bit;   
+        RWn     		: in bit;
+        RS				: in bit_vector(5 downto 1);
+        DATA_IN			: in bit_vector(7 downto 0);   
+        DATA_OUT		: out bit_vector(7 downto 0);   
+		DATA_OUT_EN		: out bit;
+		RX_SAMPLE		: in bit;
+        RX_DATA			: in bit_vector(7 downto 0);   
+        TX_DATA			: out bit_vector(7 downto 0);   
+        SCR_OUT			: out bit_vector(7 downto 0);   
+		BF				: in bit;
+		BE				: in bit;
+		FE				: in bit;
+		OE				: in bit;
+		UE				: in bit;
+		PE				: in bit;
+		M_CIP			: in bit;
+		FS_B			: in bit;
+		TX_END			: in bit;
+		CL				: out bit_vector(1 downto 0);
+		ST				: out bit_vector(1 downto 0);
+		FS_CLR			: out bit;
+		RSR_READ		: out bit;
+		TSR_READ		: out bit;
+		UDR_READ		: out bit;
+		UDR_WRITE		: out bit;
+		LOOPBACK		: out bit;
+		SDOUT_EN		: out bit;
+		SD_LEVEL		: out bit;
+		CLK_MODE		: out bit;
+		RE				: out bit;
+		TE				: out bit;
+		P_ENA			: out bit;
+		P_EOn			: out bit;
+		SS				: out bit;
+		BR				: out bit
+	);                                              
+end component;
+
+component WF68901IP_USART_TX
+	port (
+		CLK			: in bit;
+        RESETn		: in bit;
+		SCR			: in bit_vector(7 downto 0);
+		TX_DATA		: in bit_vector(7 downto 0);
+        SDATA_OUT	: out bit;
+        TXCLK		: in bit;
+		CL			: in bit_vector(1 downto 0);
+		ST			: in bit_vector(1 downto 0);
+		TE			: in bit;
+		BR			: in bit;
+		P_ENA		: in bit;
+		P_EOn		: in bit;
+		UDR_WRITE	: in bit;
+		TSR_READ	: in bit;
+		CLK_MODE	: in bit;
+		TX_END		: out bit;
+		UE			: out bit;
+		BE			: out bit
+	);                                              
+end component;
+
+component WF68901IP_USART_RX
+	port (
+		CLK			: in bit;
+        RESETn		: in bit;
+		SCR			: in bit_vector(7 downto 0);
+		RX_SAMPLE	: out bit;
+        RX_DATA	  	: out bit_vector(7 downto 0);   
+        RXCLK		: in bit;
+        SDATA_IN	: in bit;
+		CL			: in bit_vector(1 downto 0);
+		ST			: in bit_vector(1 downto 0);
+		P_ENA		: in bit;
+		P_EOn		: in bit;
+		CLK_MODE	: in bit;
+		RE			: in bit;
+		FS_CLR		: in bit;
+		SS			: in bit;
+		RSR_READ	: in bit;
+		UDR_READ	: in bit;
+		M_CIP		: out bit;
+		FS_B		: out bit;
+		BF			: out bit;
+		OE			: out bit;
+		PE			: out bit;
+		FE			: out bit
+	);                                              
+end component;
+
+component WF68901IP_INTERRUPTS
+	port ( 	
+		CLK			: in bit;
+		RESETn		: in bit;
+		DSn			: in bit;
+		CSn			: in bit;
+		RWn			: in bit;
+		RS			: in bit_vector(5 downto 1);
+		DATA_IN		: in bit_vector(7 downto 0);
+		DATA_OUT	: out bit_vector(7 downto 0);
+		DATA_OUT_EN	: out bit;
+		IACKn		: in bit;
+		IEIn		: in bit;
+		IEOn		: out bit;
+		IRQn		: out bit;
+		GP_INT		: in bit_vector(7 downto 0);
+		AER_4		: in bit;
+		AER_3		: in bit;
+		TAI			: in bit;
+		TBI			: in bit;
+		TA_PWM		: in bit;
+		TB_PWM		: in bit;
+		TIMER_A_INT	: in bit;
+		TIMER_B_INT	: in bit;
+		TIMER_C_INT	: in bit;
+		TIMER_D_INT	: in bit;
+		RCV_ERR		: in bit;
+		TRM_ERR		: in bit;
+		RCV_BUF_F	: in bit;
+		TRM_BUF_E	: in bit
+	);
+end component;
+
+component WF68901IP_GPIO
+	port (  
+		CLK			: in bit;
+		RESETn		: in bit;
+		DSn			: in bit;
+		CSn			: in bit;
+		RWn			: in bit;
+		RS			: in bit_vector(5 downto 1);
+		DATA_IN		: in bit_vector(7 downto 0);
+		DATA_OUT	: out bit_vector(7 downto 0);
+		DATA_OUT_EN	: out bit;
+		AER_4		: out bit;
+		AER_3		: out bit;
+		GPIP_IN		: in bit_vector(7 downto 0);
+		GPIP_OUT	: out bit_vector(7 downto 0);
+		GPIP_OUT_EN	: out bit_vector(7 downto 0);
+		GP_INT		: out bit_vector(7 downto 0)
+	);
+end component;
+
+component WF68901IP_TIMERS
+	port (  
+		CLK			: in bit;
+		RESETn		: in bit;
+		DSn			: in bit;
+		CSn			: in bit;
+		RWn			: in bit;
+		RS			: in bit_vector(5 downto 1);
+		DATA_IN		: in bit_vector(7 downto 0);
+		DATA_OUT	: out bit_vector(7 downto 0);
+		DATA_OUT_EN	: out bit;
+		XTAL1		: in bit;
+		TAI			: in bit;
+		TBI			: in bit;
+		AER_4		: in bit;
+		AER_3		: in bit;
+		TA_PWM		: out bit;
+		TB_PWM		: out bit;
+		TAO			: out bit;			
+		TBO			: out bit;			
+		TCO			: out bit;			
+		TDO			: out bit;
+		TIMER_A_INT	: out bit;
+		TIMER_B_INT	: out bit;
+		TIMER_C_INT	: out bit;
+		TIMER_D_INT	: out bit
+	);
+end component;
+
+end WF68901IP_PKG;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd
new file mode 100644
index 0000000..b339af5
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd
@@ -0,0 +1,533 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- MC68901 compatible multi function port core.                 ----
+----                                                              ----
+---- This is the SUSKA MFP IP core timers logic file.             ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B	2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K7A	2006/12/28 WF
+--   The timer is modified to work on the CLK instead
+--   of XTAL1. This modification is done to provide
+--   a synchronous design.
+-- Revision 2K8A	2008/02/29 WF
+--   Fixed a serious prescaler bug.
+-- Revision 2K9A 20090620 WF
+--   Introduced timer readback registers.
+--   TIMER_x_INT is now a strobe.
+--   Minor improvements.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF68901IP_TIMERS is
+	port (  -- System control:
+			CLK			: in bit;
+			RESETn		: in bit;
+			
+			-- Asynchronous bus control:
+			DSn			: in bit;
+			CSn			: in bit;
+			RWn			: in bit;
+			
+			-- Data and Adresses:
+			RS			: in bit_vector(5 downto 1);
+			DATA_IN		: in bit_vector(7 downto 0);
+			DATA_OUT	: out bit_vector(7 downto 0);
+			DATA_OUT_EN	: out bit;
+
+			-- Timers and timer control:
+			XTAL1		: in bit; -- Use an oszillator instead of a quartz.
+			TAI			: in bit;
+			TBI			: in bit;
+			AER_4		: in bit;
+			AER_3		: in bit;
+			TA_PWM		: out bit; -- Indicates, that timer A is in PWM mode (used in Interrupt logic).
+			TB_PWM		: out bit; -- Indicates, that timer B is in PWM mode (used in Interrupt logic).
+			TAO			: buffer bit;
+			TBO			: buffer bit;
+			TCO			: buffer bit;
+			TDO			: buffer bit;
+			TIMER_A_INT	: out bit;
+			TIMER_B_INT	: out bit;
+			TIMER_C_INT	: out bit;
+			TIMER_D_INT	: out bit
+	);
+end entity WF68901IP_TIMERS;
+
+architecture BEHAVIOR of WF68901IP_TIMERS is
+signal XTAL1_S		: bit;
+signal XTAL_STRB	: bit;
+signal TACR			: bit_vector(4 downto 0); -- Timer A control register.
+signal TBCR			: bit_vector(4 downto 0); -- Timer B control register.
+signal TCDCR		: bit_vector(5 downto 0); -- Timer C and D control register.
+signal TADR			: bit_vector(7 downto 0); -- Timer A data register.
+signal TBDR			: bit_vector(7 downto 0); -- Timer B data register.
+signal TCDR			: bit_vector(7 downto 0); -- Timer C data register.
+signal TDDR			: bit_vector(7 downto 0); -- Timer D data register.
+signal TIMER_A 		: std_logic_vector(7 downto 0); -- Timer A count register.
+signal TIMER_B 		: std_logic_vector(7 downto 0); -- Timer B count register.
+signal TIMER_C 		: std_logic_vector(7 downto 0); -- Timer C count register.
+signal TIMER_D 		: std_logic_vector(7 downto 0); -- Timer D count register.
+signal TIMER_R_A    : bit_vector(7 downto 0); -- Timer A readback register.
+signal TIMER_R_B    : bit_vector(7 downto 0); -- Timer B readback register.
+signal TIMER_R_C    : bit_vector(7 downto 0); -- Timer C readback register.
+signal TIMER_R_D    : bit_vector(7 downto 0); -- Timer D readback register.
+signal A_CNTSTRB	: bit;
+signal B_CNTSTRB	: bit;
+signal C_CNTSTRB	: bit;
+signal D_CNTSTRB	: bit;
+signal TAI_I		: bit;
+signal TBI_I		: bit;
+signal TAI_STRB		: bit; -- Strobe for the event counter mode.
+signal TBI_STRB		: bit; -- Strobe for the event counter mode.
+signal TAO_I		: bit; -- Timer A output signal.
+signal TBO_I		: bit; -- Timer A output signal.
+begin
+	SYNC: process
+	-- This process provides a 'clean' XTAL1.
+	-- Without this sync, the edge detector for
+	-- XTAL_STRB does not work properly.
+	begin
+		wait until CLK = '1' and CLK' event;
+		XTAL1_S <= XTAL1;
+        -- Polarity control for the event counter and the PWM mode:
+        TAI_I <= TAI xnor AER_4;
+        TBI_I <= TBI xnor AER_3;
+	end process SYNC;
+	
+	-- Output enables for timer A and timer B:
+	-- The outputs are held low for asserted reset flags in the control registers TACR
+	-- and TBCR but also during a write operation to these registers.
+	TAO <=	'0' when TACR(4) = '1' else
+			'0' when CSn = '0' and DSn = '0' and RWn = '0' and RS = "01100" else TAO_I;
+	TBO <=	'0' when TBCR(4) = '1' else
+			'0' when CSn = '0' and DSn = '0' and RWn = '0' and RS = "01101" else TBO_I;
+
+	-- Control outputs for the PWM modi of the timers A and B. These
+	-- controls are used in the interrupt logic to select the interrupt
+	-- sources GPIP4 or TAI repective GPIP3 or TBI.
+	TA_PWM <= '1' when TACR(3 downto 0) > x"8" else '0';
+	TB_PWM <= '1' when TBCR(3 downto 0) > x"8" else '0';
+
+	TIMER_REGISTERS: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			TACR <= (others => '0');
+			TBCR <= (others => '0');
+			TCDCR <= (others => '0');
+			-- TADR <= Do not clear during reset!
+			-- TBDR <= Do not clear during reset!
+			-- TCDR <= Do not clear during reset!
+			-- TDDR <= Do not clear during reset!
+		elsif CLK = '1' and CLK' event then
+			if CSn = '0' and DSn = '0' and RWn = '0' then
+				case RS is
+					when "01100"	=> TACR <= DATA_IN(4 downto 0);
+					when "01101"	=> TBCR <= DATA_IN(4 downto 0);
+					when "01110"	=> TCDCR <= DATA_IN(6 downto 4) & DATA_IN(2 downto 0);
+					when "01111"	=> TADR <= DATA_IN;
+					when "10000"	=> TBDR <= DATA_IN;
+					when "10001"	=> TCDR <= DATA_IN;
+					when "10010"	=> TDDR <= DATA_IN;
+					when others		=> null;
+				end case;
+			end if;
+		end if;
+	end process TIMER_REGISTERS;
+
+    TIMER_READBACK	: process(RESETn, CLK)
+    -- This process provides the readback information for the
+    -- timers A to D. The information read is the information
+    -- last clocked into the timer read register when the DSn
+    -- pin had last gone high prior to the current read cycle.
+    variable READ_A : boolean;
+    variable READ_B : boolean;
+    variable READ_C : boolean;
+    variable READ_D : boolean;
+    begin
+        if RESETn = '0' then
+            TIMER_R_A <= x"00";
+            TIMER_R_B <= x"00";
+            TIMER_R_C <= x"00";
+            TIMER_R_D <= x"00";
+        elsif CLK = '1' and CLK' event then
+            if DSn = '0' and RS = "01111" then
+                READ_A := true;
+            elsif DSn = '0' and RS = "10000" then
+                READ_B := true;
+            elsif DSn = '0' and RS = "10001" then
+                READ_C := true;
+            elsif DSn = '0' and RS = "10010" then
+                READ_D := true;
+            elsif DSn = '1' and READ_A = true then
+                TIMER_R_A <= To_BitVector(TIMER_A);
+                READ_A := false;
+            elsif DSn = '1' and READ_B = true then
+                TIMER_R_B <= To_BitVector(TIMER_B);
+                READ_B := false;
+            elsif DSn = '1' and READ_C = true then
+                TIMER_R_C <= To_BitVector(TIMER_C);
+                READ_C := false;
+            elsif DSn = '1' and READ_D = true then
+                TIMER_R_D <= To_BitVector(TIMER_D);
+                READ_D := false;
+            end if;
+        end if;
+    end process TIMER_READBACK;
+
+	DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS > "01011" and RS <= "10010" else '0';
+	DATA_OUT <= "000" & TACR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01100" else
+				"000" & TBCR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01101" else
+				'0' & TCDCR(5 downto 3) & '0' & TCDCR(2 downto 0) when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01110" else
+				TIMER_R_A when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01111" else
+				TIMER_R_B when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10000" else
+				TIMER_R_C when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10001" else
+				TIMER_R_D when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10010" else (others => '0');
+
+	XTAL_STROBE: process(RESETn, CLK)
+	-- This process provides a strobe with 1 clock cycle
+	-- (CLK) length after every rising edge of XTAL1.
+	variable LOCK : boolean;
+	begin
+		if RESETn = '0' then
+			XTAL_STRB <= '0';
+		elsif CLK = '1' and CLK' event then
+            if XTAL1_S = '1' and LOCK = false then
+				XTAL_STRB <= '1';
+				LOCK := true;
+			elsif XTAL1_S = '0' then
+				XTAL_STRB <= '0';
+				LOCK := false;
+			else
+				XTAL_STRB <= '0';
+			end if;
+		end if;
+	end process XTAL_STROBE;
+
+	TAI_STROBE: process(RESETn, CLK)
+	variable LOCK : boolean;
+	begin
+		if RESETn = '0' then
+			TAI_STRB <= '0';
+		elsif CLK = '1' and CLK' event then
+            if TAI_I = '1' and XTAL_STRB = '1' and LOCK = false then
+				LOCK := true;
+				TAI_STRB <= '1';
+			elsif TAI_I = '0' then
+				LOCK := false;
+				TAI_STRB <= '0';
+			else
+				TAI_STRB <= '0';
+			end if;
+		end if;
+	end process TAI_STROBE;
+
+	TBI_STROBE: process(RESETn, CLK)
+	variable LOCK : boolean;
+	begin
+		if RESETn = '0' then
+			TBI_STRB <= '0';
+		elsif CLK = '1' and CLK' event then
+            if TBI_I = '1' and XTAL_STRB = '1' and LOCK = false then
+				LOCK := true;
+				TBI_STRB <= '1';
+			elsif TBI_I = '0' then
+				LOCK := false;
+				TBI_STRB <= '0';
+			else
+				TBI_STRB <= '0';
+			end if;
+		end if;
+	end process TBI_STROBE;
+
+	PRESCALE_A: process
+	-- The prescalers work even if the RESETn is asserted.
+	variable PRESCALE : std_logic_vector(7 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		A_CNTSTRB <= '0';
+		if PRESCALE > x"00" and XTAL_STRB = '1' then
+			PRESCALE := PRESCALE - '1';
+		elsif XTAL_STRB = '1' then
+			case TACR(2 downto 0) is
+				when "111" => PRESCALE := x"C7"; -- Prescaler = 200.
+				when "110" => PRESCALE := x"63"; -- Prescaler = 100.
+				when "101" => PRESCALE := x"3F"; -- Prescaler = 64.
+				when "100" => PRESCALE := x"31"; -- Prescaler = 50.
+				when "011" => PRESCALE := x"0F"; -- Prescaler = 16.
+				when "010" => PRESCALE := x"09"; -- Prescaler = 10.
+				when "001" => PRESCALE := x"03"; -- Prescaler = 4.
+				when "000" => PRESCALE := x"00"; -- Timer stopped or event count mode.
+			end case;
+			A_CNTSTRB <= '1';
+		end if;
+	end process PRESCALE_A;
+
+	PRESCALE_B: process
+	-- The prescalers work even if the RESETn is asserted.
+	variable PRESCALE : std_logic_vector(7 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		B_CNTSTRB <= '0';
+		if PRESCALE > x"00" and XTAL_STRB = '1' then
+			PRESCALE := PRESCALE - '1';
+		elsif XTAL_STRB = '1' then
+			case TBCR(2 downto 0) is
+				when "111" => PRESCALE := x"C7"; -- Prescaler = 200.
+				when "110" => PRESCALE := x"63"; -- Prescaler = 100.
+				when "101" => PRESCALE := x"3F"; -- Prescaler = 64.
+				when "100" => PRESCALE := x"31"; -- Prescaler = 50.
+				when "011" => PRESCALE := x"0F"; -- Prescaler = 16.
+				when "010" => PRESCALE := x"09"; -- Prescaler = 10.
+				when "001" => PRESCALE := x"03"; -- Prescaler = 4.
+				when "000" => PRESCALE := x"00"; -- Timer stopped or event count mode.
+			end case;
+			B_CNTSTRB <= '1';
+		end if;
+	end process PRESCALE_B;
+
+	PRESCALE_C: process
+	-- The prescalers work even if the RESETn is asserted.
+	variable PRESCALE : std_logic_vector(7 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		C_CNTSTRB <= '0';
+		if PRESCALE > x"00" and XTAL_STRB = '1' then
+			PRESCALE := PRESCALE - '1';
+		elsif XTAL_STRB = '1' then
+			case TCDCR(5 downto 3) is
+				when "111" => PRESCALE := x"C7"; -- Prescaler = 200.
+				when "110" => PRESCALE := x"63"; -- Prescaler = 100.
+				when "101" => PRESCALE := x"3F"; -- Prescaler = 64.
+				when "100" => PRESCALE := x"31"; -- Prescaler = 50.
+				when "011" => PRESCALE := x"0F"; -- Prescaler = 16.
+				when "010" => PRESCALE := x"09"; -- Prescaler = 10.
+				when "001" => PRESCALE := x"03"; -- Prescaler = 4.
+				when "000" => PRESCALE := x"00"; -- Timer stopped.
+			end case;
+			C_CNTSTRB <= '1';
+		end if;
+	end process PRESCALE_C;
+
+	PRESCALE_D: process
+	-- The prescalers work even if the RESETn is asserted.
+	variable PRESCALE : std_logic_vector(7 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		D_CNTSTRB <= '0';
+		if PRESCALE > x"00" and XTAL_STRB = '1' then
+			PRESCALE := PRESCALE - '1';
+		elsif XTAL_STRB = '1' then
+			case TCDCR(2 downto 0) is
+				when "111" => PRESCALE := x"C7"; -- Prescaler = 200.
+				when "110" => PRESCALE := x"63"; -- Prescaler = 100.
+				when "101" => PRESCALE := x"3F"; -- Prescaler = 64.
+				when "100" => PRESCALE := x"31"; -- Prescaler = 50.
+				when "011" => PRESCALE := x"0F"; -- Prescaler = 16.
+				when "010" => PRESCALE := x"09"; -- Prescaler = 10.
+				when "001" => PRESCALE := x"03"; -- Prescaler = 4.
+				when "000" => PRESCALE := x"00"; -- Timer stopped.
+			end case;
+			D_CNTSTRB <= '1';
+		end if;
+	end process PRESCALE_D;
+
+	TIMERA: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			-- Do not clear the timer registers during system reset.
+			TAO_I <= '0';
+			TIMER_A_INT <= '0';
+		elsif CLK = '1' and CLK' event then
+            TIMER_A_INT <= '0';
+            --
+			if CSn = '0' and DSn = '0' and RWn = '0' and RS = "01111" and TACR(3 downto 0) = x"0" then
+				-- The timer is reloaded simultaneously to it's timer data register, if it is off.
+				-- The loading works asynchronous due to the possibly low XTAL1 clock.
+				TIMER_A <= To_StdLogicVector(DATA_IN);
+			else
+				case TACR(3 downto 0) is
+					when x"0" => -- Timer is off.
+                        TAO_I <= '0';
+					when x"1" | x"2" | x"3" | x"4" | x"5" | x"6" | x"7" => -- Delay counter mode.
+						if A_CNTSTRB = '1' and TIMER_A /= x"01" then -- Count.
+							TIMER_A <= TIMER_A - '1';
+						elsif A_CNTSTRB = '1' and TIMER_A = x"01" then -- Reload.
+							TIMER_A <= To_StdLogicVector(TADR);
+							TAO_I <= not TAO_I; -- Toggle the timer A output pin.
+							TIMER_A_INT <= '1';
+						end if;
+					when x"8" => -- Event count operation.
+						if TAI_STRB = '1' and TIMER_A /= x"01" then -- Count.
+							TIMER_A <= TIMER_A - '1';
+						elsif TAI_STRB = '1' and TIMER_A = x"01" then -- Reload.
+							TIMER_A <= To_StdLogicVector(TADR);
+							TAO_I <= not TAO_I; -- Toggle the timer A output pin.
+							TIMER_A_INT <= '1';
+						end if;
+					when x"9" | x"A" | x"B" | x"C" | x"D" | x"E" | x"F" => -- PWM mode.
+						if TAI_I = '1' and A_CNTSTRB = '1' and TIMER_A /= x"01" then -- Count.
+							TIMER_A <= TIMER_A - '1';
+						elsif TAI_I = '1' and A_CNTSTRB = '1' and TIMER_A = x"01" then -- Reload.
+							TIMER_A <= To_StdLogicVector(TADR);
+							TAO_I <= not TAO_I; -- Toggle the timer A output pin.
+							TIMER_A_INT <= '1';
+						end if;
+				end case;					
+			end if;
+		end if;
+	end process TIMERA;
+
+	TIMERB: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			-- Do not clear the timer registers during system reset.
+			TBO_I <= '0';
+			TIMER_B_INT <= '0';
+		elsif CLK = '1' and CLK' event then
+            TIMER_B_INT <= '0';
+            --
+			if CSn = '0' and DSn = '0' and RWn = '0' and RS = "10000" and TBCR(3 downto 0) = x"0" then
+				-- The timer is reloaded simultaneously to it's timer data register, if it is off.
+				-- The loading works asynchronous due to the possibly low XTAL1 clock.
+				TIMER_B <= To_StdLogicVector(DATA_IN);
+			else
+				case TBCR(3 downto 0) is
+					when x"0" => -- Timer is off.
+                        TBO_I <= '0';
+					when x"1" | x"2" | x"3" | x"4" | x"5" | x"6" | x"7" => -- Delay counter mode.
+						if B_CNTSTRB = '1' and TIMER_B /= x"01" then -- Count.
+							TIMER_B <= TIMER_B - '1';
+						elsif B_CNTSTRB = '1' and TIMER_B = x"01" then -- Reload.
+							TIMER_B <= To_StdLogicVector(TBDR);
+							TBO_I <= not TBO_I; -- Toggle the timer B output pin.
+							TIMER_B_INT <= '1';
+						end if;
+					when x"8" => -- Event count operation.
+						if TBI_STRB = '1' and TIMER_B /= x"01" then -- Count.
+							TIMER_B <= TIMER_B - '1';
+						elsif TBI_STRB = '1' and TIMER_B = x"01" then -- Reload.
+							TIMER_B <= To_StdLogicVector(TBDR);
+							TBO_I <= not TBO_I; -- Toggle the timer B output pin.
+							TIMER_B_INT <= '1';
+						end if;
+					when x"9" | x"A" | x"B" | x"C" | x"D" | x"E" | x"F" => -- PWM mode.
+						if TBI_I = '1' and B_CNTSTRB = '1' and TIMER_B /= x"01" then -- Count.
+							TIMER_B <= TIMER_B - '1';
+						elsif TBI_I = '1' and B_CNTSTRB = '1' and TIMER_B = x"01" then -- Reload.
+							TIMER_B <= To_StdLogicVector(TBDR);
+							TBO_I <= not TBO_I; -- Toggle the timer B output pin.
+							TIMER_B_INT <= '1';
+						end if;
+				end case;					
+			end if;
+		end if;
+	end process TIMERB;
+
+	TIMERC: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			-- Do not clear the timer registers during system reset.
+			TCO <= '0';
+			TIMER_C_INT <= '0';
+		elsif CLK = '1' and CLK' event then
+            TIMER_C_INT <= '0';
+            --
+			if 	CSn = '0' and DSn = '0' and RWn = '0' and RS = "10001" and TCDCR(5 downto 3) = "000" then
+				-- The timer is reloaded simultaneously to it's timer data register, if it is off.
+				-- The loading works asynchronous due to the possibly low XTAL1 clock.
+				TIMER_C <= To_StdLogicVector(DATA_IN);
+			else
+				case TCDCR(5 downto 3) is
+					when "000" => -- Timer is off.
+                        TCO <= '0';
+					when others => -- Delay counter mode.
+						if C_CNTSTRB = '1' and TIMER_C /= x"01" then -- Count.
+							TIMER_C <= TIMER_C - '1';
+						elsif C_CNTSTRB = '1' and TIMER_C = x"01" then -- Reload.
+							TIMER_C <= To_StdLogicVector(TCDR);
+							TCO <= not TCO; -- Toggle the timer C output pin.
+							TIMER_C_INT <= '1';
+						end if;
+				end case;					
+			end if;
+		end if;
+	end process TIMERC;
+
+	TIMERD: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			-- Do not clear the timer registers during system reset.
+			TDO <= '0';
+			TIMER_D_INT <= '0';
+		elsif CLK = '1' and CLK' event then
+            TIMER_D_INT <= '0';
+            --
+ 			if 	CSn = '0' and DSn = '0' and RWn = '0' and RS = "10010" and TCDCR(2 downto 0) = "000" then
+				-- The timer is reloaded simultaneously to it's timer data register, if it is off.
+				-- The loading works asynchronous due to the possibly low XTAL1 clock.
+				TIMER_D <= To_StdLogicVector(DATA_IN);
+			else
+				case TCDCR(2 downto 0) is
+					when "000" => -- Timer is off.
+                        TDO <= '0';
+					when others => -- Delay counter mode.
+						if D_CNTSTRB = '1' and TIMER_D /= x"01" then -- Count.
+							TIMER_D <= TIMER_D - '1';
+						elsif D_CNTSTRB = '1' and TIMER_D = x"01" then -- Reload.
+							TIMER_D <= To_StdLogicVector(TDDR);
+							TDO <= not TDO; -- Toggle the timer D output pin.
+							TIMER_D_INT <= '1';
+						end if;
+				end case;					
+			end if;
+		end if;
+	end process TIMERD;
+end architecture BEHAVIOR;
\ No newline at end of file
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd
new file mode 100644
index 0000000..783ba56
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd
@@ -0,0 +1,213 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- MC68901 compatible multi function port core.                 ----
+----                                                              ----
+---- This is the SUSKA MFP IP core top level file.                ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B	2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K7A	2006/12/28 WF
+--   The timer is modified to work on the CLK instead
+--   of XTAL1. This modification is done to provide
+--   a synchronous design.
+-- Revision 2K8B  2008/12/24 WF
+--   Rewritten this top level file as a wrapper for the top_soc file.
+--
+
+use work.wf68901ip_pkg.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF68901IP_TOP is
+	port (  -- System control:
+			CLK			: in bit;
+			RESETn		: in bit;
+			
+			-- Asynchronous bus control:
+			DSn			: in bit;
+			CSn			: in bit;
+			RWn			: in bit;
+			DTACKn		: out std_logic;
+			
+			-- Data and Adresses:
+			RS			: in bit_vector(5 downto 1);
+			DATA		: inout std_logic_vector(7 downto 0);
+			GPIP		: inout std_logic_vector(7 downto 0);
+			
+			-- Interrupt control:
+			IACKn		: in bit;
+			IEIn		: in bit;
+			IEOn		: out bit;
+			IRQn		: out std_logic;
+			
+			-- Timers and timer control:
+			XTAL1		: in bit; -- Use an oszillator instead of a quartz.
+			TAI			: in bit;
+			TBI			: in bit;
+			TAO			: out bit;			
+			TBO			: out bit;			
+			TCO			: out bit;			
+			TDO			: out bit;			
+			
+			-- Serial I/O control:
+			RC			: in bit;
+			TC			: in bit;
+			SI			: in bit;
+			SO			: out std_logic;
+			
+			-- DMA control:
+			RRn			: out bit;
+			TRn			: out bit			
+	);
+end entity WF68901IP_TOP;
+
+architecture STRUCTURE of WF68901IP_TOP is
+component WF68901IP_TOP_SOC
+	port(CLK			: in bit;
+         RESETn		    : in bit;
+         DSn			: in bit;
+         CSn			: in bit;
+         RWn			: in bit;
+         DTACKn		    : out bit;
+         RS			    : in bit_vector(5 downto 1);
+         DATA_IN		: in std_logic_vector(7 downto 0);
+         DATA_OUT	    : out std_logic_vector(7 downto 0);
+         DATA_EN		: out bit;
+         GPIP_IN		: in bit_vector(7 downto 0);
+         GPIP_OUT	    : out bit_vector(7 downto 0);
+         GPIP_EN		: out bit_vector(7 downto 0);
+         IACKn		    : in bit;
+         IEIn		    : in bit;
+         IEOn		    : out bit;
+         IRQn		    : out bit;
+         XTAL1		    : in bit;
+         TAI			: in bit;
+         TBI			: in bit;
+         TAO			: out bit;			
+         TBO			: out bit;			
+         TCO			: out bit;			
+         TDO			: out bit;			
+         RC			    : in bit;
+         TC			    : in bit;
+         SI			    : in bit;
+         SO			    : out bit;
+         SO_EN		    : out bit;
+         RRn			: out bit;
+         TRn			: out bit			
+	);
+end component;
+--
+signal DTACK_In         : bit;
+signal IRQ_In           : bit;
+signal DATA_OUT         : std_logic_vector(7 downto 0);
+signal DATA_EN          : bit;
+signal GPIP_IN          : bit_vector(7 downto 0);
+signal GPIP_OUT         : bit_vector(7 downto 0);
+signal GPIP_EN          : bit_vector(7 downto 0);
+signal SO_I             : bit;
+signal SO_EN            : bit;
+begin
+    DTACKn <= '0' when DTACK_In = '0' else 'Z'; -- Open drain.
+    IRQn <= '0' when IRQ_In = '0' else 'Z'; -- Open drain.
+
+    DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z');
+
+    GPIP_IN <= To_BitVector(GPIP);
+
+	P_GPIP_OUT: process(GPIP_OUT, GPIP_EN)
+	begin
+		for i in 7 downto 0 loop
+			if GPIP_EN(i) = '1' then
+				case GPIP_OUT(i) is
+					when '0' => GPIP(i) <= '0';
+					when others => GPIP(i) <= '1';
+				end case;
+			else
+				GPIP(i) <= 'Z';
+			end if;
+		end loop;
+	end process P_GPIP_OUT;
+
+    SO <= '0' when SO_I = '0' and SO_EN = '1' else
+          '1' when SO_I = '1' and SO_EN = '1' else 'Z';
+
+    I_MFP: WF68901IP_TOP_SOC
+        port map(CLK            => CLK,
+                 RESETn         => RESETn,
+                 DSn            => DSn,
+                 CSn            => CSn,
+                 RWn            => RWn,
+                 DTACKn         => DTACK_In,
+                 RS             => RS,
+                 DATA_IN        => DATA,
+                 DATA_OUT       => DATA_OUT,
+                 DATA_EN        => DATA_EN,
+                 GPIP_IN        => GPIP_IN,
+                 GPIP_OUT       => GPIP_OUT,
+                 GPIP_EN        => GPIP_EN,
+                 IACKn          => IACKn,
+                 IEIn           => IEIn,
+                 IEOn           => IEOn,
+                 IRQn           => IRQ_In,
+                 XTAL1          => XTAL1,
+                 TAI            => TAI,
+                 TBI            => TBI,
+                 TAO            => TAO,
+                 TBO            => TBO,
+                 TCO            => TCO,
+                 TDO            => TDO,
+                 RC             => RC,
+                 TC             => TC,
+                 SI             => SI,
+                 SO             => SO_I,
+                 SO_EN          => SO_EN,
+                 RRn            => RRn,
+                 TRn            => TRn
+        );
+end architecture STRUCTURE;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd
new file mode 100644
index 0000000..1e559d9
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd
@@ -0,0 +1,309 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- MC68901 compatible multi function port core.                 ----
+----                                                              ----
+---- This is the SUSKA MFP IP core top level file.                ----
+---- Top level file for use in systems on programmable chips.     ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+--   Top level file provided for SOC (systems on programmable chips).
+-- Revision 2K7A  2006/12/28 WF
+--   The timer is modified to work on the CLK instead
+--   of XTAL1. This modification is done to provide
+--   a synchronous design.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K9A  2009/06/20 WF
+--   DTACK_OUTn has now synchronous reset to meet preset requirement.
+--
+--
+
+use work.wf68901ip_pkg.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF68901IP_TOP_SOC is
+	port (  -- System control:
+			CLK			: in bit;
+			RESETn		: in bit;
+			
+			-- Asynchronous bus control:
+			DSn			: in bit;
+			CSn			: in bit;
+			RWn			: in bit;
+			DTACKn		: out bit;
+			
+			-- Data and Adresses:
+			RS			: in bit_vector(5 downto 1);
+			DATA_IN		: in std_logic_vector(7 downto 0);
+			DATA_OUT	: out std_logic_vector(7 downto 0);
+			DATA_EN		: out bit;
+			GPIP_IN		: in bit_vector(7 downto 0);
+			GPIP_OUT	: out bit_vector(7 downto 0);
+			GPIP_EN		: out bit_vector(7 downto 0);
+			
+			-- Interrupt control:
+			IACKn		: in bit;
+			IEIn		: in bit;
+			IEOn		: out bit;
+			IRQn		: out bit;
+			
+			-- Timers and timer control:
+			XTAL1		: in bit; -- Use an oszillator instead of a quartz.
+			TAI			: in bit;
+			TBI			: in bit;
+			TAO			: out bit;			
+			TBO			: out bit;			
+			TCO			: out bit;			
+			TDO			: out bit;			
+			
+			-- Serial I/O control:
+			RC			: in bit;
+			TC			: in bit;
+			SI			: in bit;
+			SO			: out bit;
+			SO_EN		: out bit;
+			
+			-- DMA control:
+			RRn			: out bit;
+			TRn			: out bit			
+	);
+end entity WF68901IP_TOP_SOC;
+
+architecture STRUCTURE of WF68901IP_TOP_SOC is
+signal DATA_IN_I				: bit_vector(7 downto 0);
+signal DTACK_In					: bit;
+signal DTACK_LOCK				: boolean;
+signal DTACK_OUTn				: bit;
+signal RX_ERR_INT_I				: bit;
+signal TX_ERR_INT_I				: bit;
+signal RX_BUFF_INT_I			: bit;
+signal TX_BUFF_INT_I			: bit;
+signal DATA_OUT_USART_I			: bit_vector(7 downto 0);
+signal DATA_OUT_EN_USART_I		: bit;
+signal DATA_OUT_INT_I			: bit_vector(7 downto 0);
+signal DATA_OUT_EN_INT_I		: bit;
+signal DATA_OUT_GPIO_I			: bit_vector(7 downto 0);
+signal DATA_OUT_EN_GPIO_I		: bit;
+signal DATA_OUT_TIMERS_I		: bit_vector(7 downto 0);
+signal DATA_OUT_EN_TIMERS_I		: bit;
+signal SO_I						: bit;
+signal SO_EN_I					: bit;
+signal GPIP_IN_I				: bit_vector(7 downto 0);
+signal GPIP_OUT_I				: bit_vector(7 downto 0);
+signal GPIP_EN_I				: bit_vector(7 downto 0);
+signal GP_INT_I					: bit_vector(7 downto 0);
+signal TIMER_A_INT_I			: bit;
+signal TIMER_B_INT_I			: bit;
+signal TIMER_C_INT_I			: bit;
+signal TIMER_D_INT_I			: bit;
+signal IRQ_In					: bit;
+signal AER_4_I					: bit;
+signal AER_3_I					: bit;
+signal TA_PWM_I					: bit;
+signal TB_PWM_I					: bit;
+begin
+	-- Interrupt request (open drain):
+	IRQn <= IRQ_In;
+
+	-- Serial data output:
+	SO <= 	SO_I;
+	SO_EN <= SO_EN_I and RESETn;
+
+	-- General purpose port:
+	GPIP_IN_I	<= GPIP_IN;
+	GPIP_OUT <= GPIP_OUT_I;
+	GPIP_EN <= GPIP_EN_I;
+
+	DATA_IN_I <= To_BitVector(DATA_IN);
+	DATA_EN <= DATA_OUT_EN_USART_I or DATA_OUT_EN_INT_I or DATA_OUT_EN_GPIO_I or DATA_OUT_EN_TIMERS_I;
+	-- Output data multiplexer:
+	DATA_OUT <= To_StdLogicVector(DATA_OUT_USART_I) when DATA_OUT_EN_USART_I = '1' else
+				To_StdLogicVector(DATA_OUT_INT_I) when DATA_OUT_EN_INT_I = '1' else
+				To_StdLogicVector(DATA_OUT_GPIO_I) when DATA_OUT_EN_GPIO_I = '1' else
+				To_StdLogicVector(DATA_OUT_TIMERS_I) when DATA_OUT_EN_TIMERS_I = '1' else (others => '1');
+
+	-- Data acknowledge handshake is provided by the following statement and the consecutive two
+	-- processes. For more information refer to the M68000 family reference manual.
+	DTACK_In <= '0' when CSn = '0' and DSn = '0' and RS <= "10111" else -- Read and write operation.
+				'0' when IACKn = '0' and DSn = '0' and IEIn = '0' else '1'; -- Interrupt vector data acknowledge.
+
+	P_DTACK_LOCK: process
+	-- This process releases a data acknowledge detect, one rising clock
+	-- edge after the DTACK_In occured. This is necessary to ensure write
+	-- data to registers for there is one rising clock edge required.
+	begin
+		wait until CLK = '1' and CLK' event;
+		if DTACK_In = '0' then
+			DTACK_LOCK <= false;
+		else
+			DTACK_LOCK <= true;
+		end if;
+	end process P_DTACK_LOCK;
+
+	DTACK_OUT: process
+	-- The DTACKn port pin is released on the falling clock edge after the data
+	-- acknowledge detect (DTACK_LOCK) is asserted. The DTACKn is deasserted
+	-- immediately when there is no further register access DTACK_In = '1';
+	begin
+		wait until CLK = '0' and CLK' event;
+		if RESETn = '0' then
+			DTACK_OUTn <= '1';
+		elsif DTACK_In = '1' then
+			DTACK_OUTn <= '1';
+		elsif DTACK_LOCK = false then
+			DTACK_OUTn <= '0';
+		end if;
+	end process DTACK_OUT;
+	DTACKn <= '0' when DTACK_OUTn = '0' else '1';
+
+	I_USART: WF68901IP_USART_TOP
+		port map(
+			CLK				=> CLK,
+			RESETn			=> RESETn,
+			DSn				=> DSn,
+			CSn				=> CSn,
+			RWn				=> RWn,
+			RS				=> RS,
+			DATA_IN			=> DATA_IN_I,
+			DATA_OUT		=> DATA_OUT_USART_I,
+			DATA_OUT_EN		=> DATA_OUT_EN_USART_I,
+			RC				=> RC,
+			TC				=> TC,
+			SI				=> SI,
+			SO				=> SO_I,
+			SO_EN			=> SO_EN_I,
+			RX_ERR_INT		=> RX_ERR_INT_I,
+			RX_BUFF_INT		=> RX_BUFF_INT_I,
+			TX_ERR_INT		=> TX_ERR_INT_I,
+			TX_BUFF_INT		=> TX_BUFF_INT_I,
+			RRn				=> RRn,
+			TRn				=> TRn
+		);
+
+	I_INTERRUPTS: WF68901IP_INTERRUPTS
+		port map(
+			CLK				=> CLK,
+			RESETn			=> RESETn,
+			DSn				=> DSn,
+			CSn				=> CSn,
+			RWn				=> RWn,
+			RS				=> RS,
+			DATA_IN			=> DATA_IN_I,
+			DATA_OUT		=> DATA_OUT_INT_I,
+			DATA_OUT_EN		=> DATA_OUT_EN_INT_I,
+			IACKn			=> IACKn,
+			IEIn			=> IEIn,
+			IEOn			=> IEOn,
+			IRQn			=> IRQ_In,
+			GP_INT			=> GP_INT_I,
+			AER_4			=> AER_4_I,
+			AER_3			=> AER_3_I,
+			TAI				=> TAI,
+			TBI				=> TBI,
+			TA_PWM 			=> TA_PWM_I,
+			TB_PWM 			=> TB_PWM_I,
+			TIMER_A_INT		=> TIMER_A_INT_I,
+			TIMER_B_INT		=> TIMER_B_INT_I,
+			TIMER_C_INT		=> TIMER_C_INT_I,
+			TIMER_D_INT		=> TIMER_D_INT_I,
+			RCV_ERR			=> RX_ERR_INT_I,
+			TRM_ERR			=> TX_ERR_INT_I,
+			RCV_BUF_F		=> RX_BUFF_INT_I,
+			TRM_BUF_E		=> TX_BUFF_INT_I
+     	 );
+
+	I_GPIO: WF68901IP_GPIO
+		port map(  
+			CLK				=> CLK,
+			RESETn			=> RESETn,
+			DSn				=> DSn,
+			CSn				=> CSn,
+			RWn				=> RWn,
+			RS				=> RS,
+			DATA_IN			=> DATA_IN_I,
+			DATA_OUT		=> DATA_OUT_GPIO_I,
+			DATA_OUT_EN		=> DATA_OUT_EN_GPIO_I,
+			AER_4			=> AER_4_I,
+			AER_3			=> AER_3_I,
+			GPIP_IN			=> GPIP_IN_I,
+			GPIP_OUT		=> GPIP_OUT_I,
+			GPIP_OUT_EN		=> GPIP_EN_I,
+			GP_INT			=> GP_INT_I
+      	);
+
+	I_TIMERS: WF68901IP_TIMERS
+		port map(
+			CLK				=> CLK,
+			RESETn			=> RESETn,
+			DSn				=> DSn,
+			CSn				=> CSn,
+			RWn				=> RWn,
+			RS				=> RS,
+			DATA_IN			=> DATA_IN_I,
+			DATA_OUT		=> DATA_OUT_TIMERS_I,
+			DATA_OUT_EN		=> DATA_OUT_EN_TIMERS_I,
+			XTAL1			=> XTAL1,
+			AER_4			=> AER_4_I,
+			AER_3			=> AER_3_I,
+			TAI				=> TAI,
+			TBI				=> TBI,
+			TAO				=> TAO,
+			TBO				=> TBO,
+			TCO				=> TCO,
+			TDO				=> TDO,
+			TA_PWM 			=> TA_PWM_I,
+			TB_PWM 			=> TB_PWM_I,
+			TIMER_A_INT		=> TIMER_A_INT_I,
+			TIMER_B_INT		=> TIMER_B_INT_I,
+			TIMER_C_INT		=> TIMER_C_INT_I,
+			TIMER_D_INT		=> TIMER_D_INT_I
+      	);
+end architecture STRUCTURE;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
new file mode 100644
index 0000000..8e7c3cc
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
@@ -0,0 +1,191 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- This is the SUSKA MFP IP core USART control file.            ----
+----                                                              ----
+---- Control unit and status logic.                               ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF68901IP_USART_CTRL is
+	port (
+		-- System Control:
+		CLK				: in bit;
+        RESETn			: in bit;
+
+		-- Bus control:
+        DSn				: in bit;
+        CSn				: in bit;   
+        RWn     		: in bit;
+        RS				: in bit_vector(5 downto 1);
+        DATA_IN			: in bit_vector(7 downto 0);   
+        DATA_OUT		: out bit_vector(7 downto 0);   
+		DATA_OUT_EN		: out bit;
+
+		-- USART data register
+		RX_SAMPLE		: in bit;
+        RX_DATA			: in bit_vector(7 downto 0);
+        TX_DATA			: out bit_vector(7 downto 0);   
+        SCR_OUT			: out bit_vector(7 downto 0);   
+
+		-- USART control inputs:
+		BF				: in bit;
+		BE				: in bit;
+		FE				: in bit;
+		OE				: in bit;
+		UE				: in bit;
+		PE				: in bit;
+		M_CIP			: in bit;
+		FS_B			: in bit;
+		TX_END			: in bit;
+
+		-- USART control outputs:
+		CL				: out bit_vector(1 downto 0);
+		ST				: out bit_vector(1 downto 0);
+		FS_CLR			: out bit;
+		UDR_WRITE		: out bit;
+		UDR_READ		: out bit;
+		RSR_READ		: out bit;
+		TSR_READ		: out bit;
+		LOOPBACK		: out bit;
+		SDOUT_EN		: out bit;
+		SD_LEVEL		: out bit;
+		CLK_MODE		: out bit;
+		RE				: out bit;
+		TE				: out bit;
+		P_ENA			: out bit;
+		P_EOn			: out bit;
+		SS				: out bit;
+		BR				: out bit
+       );                                              
+end entity WF68901IP_USART_CTRL;
+
+architecture BEHAVIOR of WF68901IP_USART_CTRL is
+signal SCR	: bit_vector(7 downto 0); -- Synchronous data register.
+signal UCR	: bit_vector(7 downto 1); -- USART control register.
+signal RSR	: bit_vector(7 downto 0); -- Receiver status register.
+signal TSR	: bit_vector(7 downto 0); -- Transmitter status register.
+signal UDR	: bit_vector(7 downto 0); -- USART data register.
+begin
+	USART_REGISTERS: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SCR <= (others => '0');
+			UCR <= (others => '0');
+			RSR <= (others => '0');
+			-- TSR and UDR are not cleared during an asserted RESETn
+		elsif CLK = '1' and CLK' event then
+			-- Loading via receiver shift register
+			-- has priority over data buss access:
+			if RX_SAMPLE = '1' then
+				UDR <= RX_DATA;
+			elsif 	CSn = '0' and DSn = '0' and RWn = '0' then
+				case RS is
+					when "10011"	=> SCR <= DATA_IN;
+					when "10100"	=> UCR <= DATA_IN(7 downto 1);
+					when "10101"	=> RSR(1 downto 0) <= DATA_IN(1 downto 0); -- Only the two LSB are read/write.
+					when "10110"	=> TSR(5) <= DATA_IN(5); TSR(3 downto 0) <= DATA_IN(3 downto 0);
+					when "10111"	=> UDR <= DATA_IN;
+					when others		=> null;
+				end case;
+			end if;
+			RSR(7 downto 2) <= BF & OE & PE & FE & FS_B & M_CIP;
+			TSR(7 downto 6) <= BE & UE;
+			TSR(4) <= TX_END;
+			TX_DATA <= UDR;		
+		end if;
+	end process USART_REGISTERS;
+	DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS >= "10011" and RS <= "10111" else '0';
+	DATA_OUT <= SCR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10011" else
+				UCR & '0' when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10100" else
+				RSR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10101" else
+				TSR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10110" else
+				UDR when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10111" else x"00";
+
+	UDR_WRITE 	<= '1' when CSn = '0' and DSn = '0' and RWn = '0' and RS = "10111" else '0';
+	UDR_READ 	<= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10111" else '0';
+	RSR_READ 	<= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10101" else '0';
+	TSR_READ 	<= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS = "10110" else '0';
+	FS_CLR		<= '1' when CSn = '0' and DSn = '0' and RWn = '0' and RS = "10011" else '0';
+
+	RE <= '1' when RSR(0) = '1' else -- Receiver enable.
+		  '1' when TSR(5) = '1' and TX_END = '1' else '0'; -- Auto Turnaround.
+	SS <= RSR(1); -- Synchronous strip enable.
+	BR <= TSR(3); -- Send break.
+	TE <= TSR(0); -- Transmitter enable.
+
+	SCR_OUT <= SCR;
+
+	CLK_MODE <= UCR(7); -- Clock mode.
+	CL <= UCR(6 downto 5); -- Character length.
+	ST <= UCR(4 downto 3); -- Start/Stop configuration.
+	P_ENA <= UCR(2); -- Parity enable.
+	P_EOn <= UCR(1); -- Even or odd parity.
+	
+	SOUT_CONFIG: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		-- Do not change the output configuration until the transmitter is disabled and
+		-- current character has been transmitted (TX_END = '1').
+		if TX_END = '1' then
+			case TSR(2 downto 1) is
+				when "00" => LOOPBACK <= '0'; SD_LEVEL <= '0'; SDOUT_EN <= '0';
+				when "01" => LOOPBACK <= '0'; SD_LEVEL <= '0'; SDOUT_EN <= '1';
+				when "10" => LOOPBACK <= '0'; SD_LEVEL <= '1'; SDOUT_EN <= '1';
+				when "11" => LOOPBACK <= '1'; SD_LEVEL <= '1'; SDOUT_EN <= '1';
+			end case;			
+		end if;
+	end process SOUT_CONFIG;
+end architecture BEHAVIOR;
+
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
new file mode 100644
index 0000000..eb00a11
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
@@ -0,0 +1,590 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- This is the SUSKA MFP IP core USART receiver file.           ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B	2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K9A  2009/06/20 WF
+-- Process P_STARTBIT has now synchronous reset to meet preset requirement.
+-- Process P_SAMPLE has now synchronous reset to meet preset requirement.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF68901IP_USART_RX is
+  port (
+		CLK			: in bit;
+        RESETn		: in bit;
+
+		SCR			: in bit_vector(7 downto 0); -- Synchronous character. 
+		RX_SAMPLE	: buffer bit; -- Flag indicating valid shift register data.
+        RX_DATA		: out bit_vector(7 downto 0); -- Received data.
+
+        RXCLK		: in bit; -- Receiver clock.
+        SDATA_IN	: in bit; -- Serial data input.
+
+		CL			: in bit_vector(1 downto 0); -- Character length.
+		ST			: in bit_vector(1 downto 0); -- Start and stop bit configuration.
+		P_ENA		: in bit; -- Parity enable.
+		P_EOn		: in bit; -- Even or odd parity.
+		CLK_MODE	: in bit; -- Clock mode configuration bit.
+		RE			: in bit; -- Receiver enable.
+		FS_CLR		: in bit; -- Clear the Found/Search flag for resynchronisation purpose.
+		SS			: in bit; -- Synchronous strip enable.
+		UDR_READ	: in bit; -- Flag indicating reading the data register.
+		RSR_READ	: in bit; -- Flag indicating reading the receiver status register.
+
+		M_CIP		: out bit; -- Match/Character in progress.
+		FS_B		: buffer bit; -- Find/Search or Break detect flag.
+		BF			: out bit; -- Buffer full.
+		OE			: out bit; -- Overrun error.
+		PE			: out bit; -- Parity error.
+		FE			: out bit  -- Framing error.
+       );                                              
+end entity WF68901IP_USART_RX;
+
+architecture BEHAVIOR of WF68901IP_USART_RX is
+type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC);
+signal RCV_STATE, RCV_NEXT_STATE	: RCV_STATES;
+signal SDATA_DIV16					: bit;
+signal SDATA_IN_I					: bit;
+signal SDATA_EDGE					: bit;
+signal SHIFT_REG					: bit_vector(7 downto 0);
+signal CLK_STRB						: bit;
+signal CLK_2_STRB					: bit;
+signal BITCNT						: std_logic_vector(2 downto 0);
+signal BREAK						: boolean;
+signal RDRF							: bit;
+signal STARTBIT						: boolean;
+begin
+	BF <= RDRF; -- Buffer full = Receiver Data Register Full.
+	RX_SAMPLE <= '1' when RCV_STATE = SYNC and ST /= "00" else -- Asynchronous mode:
+			     -- Synchronous modes:
+				 '1' when RCV_STATE = SYNC and ST = "00" and SS = '0' else
+			     '1' when RCV_STATE = SYNC and ST = "00" and SS = '1' and SHIFT_REG /= SCR else '0';
+
+	-- Data multiplexer for the received data:
+	RX_DATA <= 	"000" & SHIFT_REG(7 downto 3) when RX_SAMPLE = '1' and CL = "11" else -- 5 databits.
+				"00" & SHIFT_REG(7 downto 2) when RX_SAMPLE = '1' and CL = "10" else -- 6 databits.
+				'0' & SHIFT_REG(7 downto 1) when RX_SAMPLE = '1' and CL = "01" else -- 6 databits.
+				SHIFT_REG when RX_SAMPLE = '1' and CL = "00" else x"00"; -- 8 databits.
+
+	P_SAMPLE: process
+	-- This process provides the 'valid transition logic' of the originally MC68901. For further
+	-- details see the 'M68000 FAMILY REFERENCE MANUAL'.
+	variable LOW_FLT		: std_logic_vector(1 downto 0);
+	variable HI_FLT			: std_logic_vector(1 downto 0);
+	variable CLK_LOCK		: boolean;
+	variable EDGE_LOCK		: boolean;
+	variable TIMER			: std_logic_vector(2 downto 0);
+	variable TIMER_LOCK		: boolean;
+	variable NEW_SDATA 		: bit;
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' or RE = '0' then
+			-- The reset condition assumes the SDATA_IN logic high. Otherwise
+			-- one not valid SDATA_EDGE pulse occurs during system startup.
+			CLK_LOCK := true;
+			EDGE_LOCK := true;
+			HI_FLT := "11";
+			LOW_FLT := "11";
+			SDATA_EDGE <= '0';
+			NEW_SDATA := '1';
+		-- Positive or negative edge detector for the incoming data.
+		-- Any transition must be valid for at least three receiver clock
+		-- cycles. The TIMER locking inhibits detecting four receiver
+		-- clock cycles after a valid transition.
+		elsif RXCLK = '1' and SDATA_IN = '0' and CLK_LOCK = false and LOW_FLT > "00" then
+			CLK_LOCK := true;
+			EDGE_LOCK := false;
+			HI_FLT := "00";
+			LOW_FLT := LOW_FLT - '1';
+		elsif RXCLK = '1' and SDATA_IN = '1' and CLK_LOCK = false and HI_FLT < "11" then
+			CLK_LOCK := true;
+			EDGE_LOCK := false;
+			LOW_FLT := "11";
+			HI_FLT := HI_FLT + '1';
+		elsif RXCLK = '1' and EDGE_LOCK = false and LOW_FLT = "00" then
+			EDGE_LOCK := true;
+			SDATA_EDGE <= '1'; -- Falling edge detected.
+			NEW_SDATA := '0';
+		elsif RXCLK = '1' and EDGE_LOCK = false and HI_FLT = "11" then
+			EDGE_LOCK := true;
+			SDATA_EDGE <= '1'; -- Rising edge detected.
+			NEW_SDATA := '1';
+		elsif RXCLK = '1' and CLK_LOCK = false then
+			CLK_LOCK := true;
+			SDATA_EDGE <= '0';
+		elsif RXCLK = '0' then
+			CLK_LOCK := false;
+		end if;
+		--
+		if RESETn = '0' or RE = '0' then
+			-- The reset condition assumes the SDATA_IN logic high. Otherwise
+			-- one not valid SDATA_EDGE pulse occurs during system startup.
+			TIMER := "111";
+			TIMER_LOCK := true;
+			SDATA_DIV16 <= '1';
+		-- The timer controls the SDATA in a way, that after a detected valid
+		-- Transistion, the serial data is sampled on the 8th receiver clock
+		-- edge after the initial valid transition occured.
+		elsif RXCLK = '1' and SDATA_EDGE = '1' and TIMER_LOCK = false then
+			TIMER_LOCK := true;
+			TIMER := "000"; -- Resynchronisation.
+		elsif RXCLK = '1' and TIMER = "011" and TIMER_LOCK = false then
+			TIMER_LOCK := true;
+			SDATA_DIV16 <= NEW_SDATA; -- Scan the new data.
+			TIMER := TIMER + '1'; -- Timing is active.
+		elsif RXCLK = '1' and TIMER < "111" and TIMER_LOCK = false then
+			TIMER_LOCK := true;
+			TIMER := TIMER + '1'; -- Timing is active.
+		elsif RXCLK = '0' then
+			TIMER_LOCK := false;
+		end if;
+	end process P_SAMPLE;
+
+	P_START_BIT: process(CLK)
+	-- This is the valid start bit logic of the original MC68901 multi function
+	-- port's USART receiver.
+	variable TMP	: std_logic_vector(2 downto 0);
+	variable LOCK 	: boolean;
+	begin
+		if CLK = '1' and CLK' event then
+			if RESETn = '0' then
+				TMP := "000";
+				LOCK := true;
+			elsif RE = '0' or RCV_STATE /= IDLE then -- Start bit logic disabled.
+				TMP := "000";
+				LOCK := true;
+			elsif SDATA_EDGE = '1' then
+				TMP := "000"; -- (Re)-Initialize.
+				LOCK := false; -- Start counting.
+			elsif RXCLK = '1' and SDATA_IN = '0' and TMP < "111" and LOCK = false then
+				LOCK := true;
+				TMP := TMP + '1'; -- Count 8 low bits to declare start condition valid.
+			elsif RXCLK = '0' then
+				LOCK := false;
+			end if;
+		end if;
+
+		case TMP is
+			when "111" => STARTBIT <= true;
+			when others => STARTBIT <= false;
+		end case;
+	end process P_START_BIT;
+
+	SDATA_IN_I <= 	SDATA_IN when CLK_MODE = '0' else -- Clock div by 1 mode.
+					SDATA_IN when ST = "00" else SDATA_DIV16; -- Synchronous mode.
+
+	CLKDIV: process
+	variable CLK_LOCK	: boolean;
+	variable STRB_LOCK	: boolean;
+	variable CLK_DIVCNT	: std_logic_vector(4 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		if CLK_MODE = '0' then -- Divider off.
+			if RXCLK = '1' and STRB_LOCK = false then
+				CLK_STRB <= '1';
+				STRB_LOCK := true;
+			elsif RXCLK = '0' then
+				CLK_STRB <= '0';
+				STRB_LOCK := false;
+			else
+				CLK_STRB <= '0';
+			end if;
+			CLK_2_STRB <= '0'; -- No 1 1/2 stop bits in no div by 16 mode.
+		elsif SDATA_EDGE = '1' then
+CLK_DIVCNT := "01100"; -- Div by 16 mode.
+			CLK_STRB <= '0'; -- Default.
+			CLK_2_STRB <= '0'; -- Default.
+		else
+			CLK_STRB <= '0'; -- Default.
+			CLK_2_STRB <= '0'; -- Default.
+			if CLK_DIVCNT > "00000" and RXCLK = '1' and CLK_LOCK = false then
+				CLK_DIVCNT := CLK_DIVCNT - '1';
+				CLK_LOCK := true;
+				if CLK_DIVCNT = "01000" then
+					-- This strobe is asserted at half of the clock cycle.
+					-- It is used for the stop bit timing.
+					CLK_2_STRB <= '1';
+				end if;
+			elsif CLK_DIVCNT = "00000" then
+				CLK_DIVCNT := "10000"; -- Div by 16 mode.
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				end if;
+			elsif RXCLK = '0' then
+				CLK_LOCK := false;
+				STRB_LOCK := false;
+			end if;
+		end if;
+	end process CLKDIV;
+	
+	SHIFTREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SHIFT_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if RE = '0' then
+				SHIFT_REG <= x"00";
+			elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then
+				SHIFT_REG <= SDATA_IN_I & SHIFT_REG(7 downto 1); -- Shift right.
+			end if;
+		end if;
+	end process SHIFTREG;	
+
+	P_M_CIP: process(RESETn, CLK)
+	-- In Synchronous mode this flag indicates wether a synchronous character M_CIP = '1' 
+	-- or another character (M_CIP = '0') is transferred to the receive buffer.
+	-- In asynchronous mode the flag indicates sampling condition.
+	begin
+		if RESETn = '0' then
+			M_CIP <= '0';
+		elsif CLK = '0' and CLK' event then
+			if RE = '0' then
+				M_CIP <= '0';
+			elsif ST = "00" then -- Synchronous mode.
+				if RCV_STATE = SYNC and SHIFT_REG = SCR and RDRF = '0' then
+					M_CIP <= '1'; -- SCR transferred.
+				elsif RCV_STATE = SYNC and RDRF = '0' then
+					M_CIP <= '0'; -- No SCR transferred.
+				end if;
+			else -- Asynchronous mode.
+				case RCV_STATE is
+					when SAMPLE | PARITY | STOP1 | STOP2 => M_CIP <= '1'; -- Sampling.
+					when others => M_CIP <= '0'; -- No Sampling.
+				end case;
+			end if;
+		end if;
+	end process P_M_CIP;
+
+	BREAK_DETECT: process(RESETn, CLK)
+	-- A break condition occurs, if there is no  STOP1 bit and the
+	-- shift register contains zero data.
+	begin
+		if RESETn = '0' then
+			BREAK <= false;
+		elsif CLK = '1' and CLK' event then
+			if RE = '0' then
+				BREAK <= false;
+			elsif CLK_STRB = '1' then
+				if RCV_STATE = STOP1 and SDATA_IN_I = '0' and SHIFT_REG = x"00" then
+					BREAK <= true; -- Break detected (empty shift register and no stop bit).
+				elsif RCV_STATE = STOP1 and SDATA_IN_I = '1' then
+					BREAK <= false; -- UPDATE.
+				elsif RCV_STATE = STOP1 and SDATA_IN_I = '0' and SHIFT_REG /= x"00" then
+					BREAK <= false; -- UPDATE, but framing error.
+				end if;
+			end if;
+		end if;
+	end process BREAK_DETECT;
+
+	P_FS_B: process(RESETn, CLK)
+	-- In the synchronous mode, this process provides the flag detecting the synchronous 
+	-- character. In the asynchronous mode, the flag indicates a break condition.
+	variable FS_B_I		: bit;
+	variable FIRST_READ	: boolean;
+	begin
+		if RESETn = '0' then
+			FS_B <= '0';
+			FIRST_READ := false;
+			FS_B_I := '0';
+		elsif CLK = '0' and CLK' event then
+			if RE = '0' then
+				FS_B <= '0';
+				FS_B_I := '0';
+			else
+				if ST = "00" then -- Synchronous operation.
+					if FS_CLR = '1' then
+						FS_B <= '0'; -- Clear during writing to the SCR.
+					elsif SHIFT_REG = SCR then
+						FS_B <= '1'; -- SCR detected.
+					end if;
+				else -- Asynchronous operation.
+					if RX_SAMPLE = '1' and BREAK = true then -- Break condition detected.
+						FS_B_I := '1'; -- Update.
+					elsif RX_SAMPLE = '1' then -- No break condition.
+						FS_B_I := '0'; -- Update.
+					elsif RSR_READ = '1' and FS_B_I = '1' then
+						-- If a break condition was detected, the concerning flag is
+						-- set when the valid data word in the receiver data
+						-- register is read. Thereafter the break flag is reset
+						-- and the break condition disappears after a second read
+						-- (in time) of the receiver status register.
+						if FIRST_READ = false then
+							FS_B <= '1';
+							FIRST_READ := true;
+						else
+							FS_B <= '0';
+							FIRST_READ := false;
+						end if;
+					end if;
+				end if;
+			end if;
+		end if;
+	end process P_FS_B;
+
+	P_BITCNT: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RCV_STATE = SAMPLE and CLK_STRB = '1' and ST /= "00" then -- Asynchronous mode.
+			BITCNT <= BITCNT + '1';
+		elsif RCV_STATE = SAMPLE and CLK_STRB = '1' and ST = "00" and FS_B = '1' then -- Synchronous mode.
+			BITCNT <= BITCNT + '1'; -- Count, if matched data found (FS_B = '1').
+		elsif RCV_STATE /= SAMPLE then
+			BITCNT <= (others => '0');
+		end if;
+	end process P_BITCNT;
+
+	BUFFER_FULL: process(RESETn, CLK)
+	-- Receive data register full flag.
+	begin
+		if RESETn = '0' then
+			RDRF <= '0';
+		elsif CLK = '1' and CLK' event then
+			if RE = '0' then
+				RDRF <= '0';
+			elsif RX_SAMPLE = '1' then
+				RDRF <= '1'; -- Data register is full until now!
+			elsif UDR_READ = '1' then
+				RDRF <= '0'; -- After reading the data register ...
+			end if;
+		end if;
+	end process BUFFER_FULL;
+	
+	OVERRUN: process(RESETn, CLK)
+	variable OE_I		: bit;
+	variable FIRST_READ	: boolean;
+	begin
+		if RESETn = '0' then
+			OE_I := '0';
+			OE <= '0';
+			FIRST_READ := false;
+		elsif CLK = '1' and CLK' event then
+			if RESETn = '0' then
+				OE_I := '0';
+				OE <= '0';
+				FIRST_READ := false;
+			elsif CLK_STRB = '1' and RCV_STATE = SYNC and BREAK = false then
+				-- Overrun appears if RDRF is '1' in this state and there
+				-- is no break condition.
+				OE_I := RDRF;
+			end if;
+			if RSR_READ = '1' and OE_I = '1' then
+				-- if an overrun was detected, the concerning flag is
+				-- set when the valid data word in the receiver data
+				-- register is read. Thereafter the RDRF flag is reset
+				-- and the overrun disappears (OE_I goes low) after 
+				-- a second read (in time) of the receiver data register.
+				if FIRST_READ = false then
+					OE <= '1';
+					FIRST_READ := true;
+				else
+					OE <= '0';
+					FIRST_READ := false;
+				end if;
+			end if;
+		end if;
+	end process OVERRUN;
+	
+	PARITY_TEST: process(RESETn, CLK)
+	variable PAR_TMP	: bit;
+	variable P_ERR		: bit;
+	begin
+		if RESETn = '0' then
+			PE <= '0';
+		elsif CLK = '1' and CLK' event then
+			if RE = '0' then
+				PE <= '0';
+			elsif RX_SAMPLE = '1' then
+				PE <= P_ERR; -- Update on load shift register to data register.
+			elsif CLK_STRB = '1' then -- Sample parity on clock strobe.
+				P_ERR := '0'; -- Initialise.
+				if RCV_STATE = PARITY then
+				    for i in 1 to 7 loop
+				        if i = 1 then
+				            PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
+				        else
+				            PAR_TMP := PAR_TMP xor SHIFT_REG(i);
+				        end if;
+				    end loop;
+					if P_ENA = '1' and P_EOn = '1' then -- Even parity.
+				    	P_ERR := PAR_TMP xor SDATA_IN_I;
+					elsif P_ENA = '1' and P_EOn = '0' then -- Odd parity.
+						P_ERR := not PAR_TMP xor SDATA_IN_I;
+					elsif P_ENA = '0' then -- No parity.
+						P_ERR := '0';		
+					end if;
+				end if;
+			end if;
+		end if;
+	end process PARITY_TEST;
+
+	FRAME_ERR: process(RESETn, CLK)
+	-- This module detects a framing error
+	-- during stop bit 1 and stop bit 2.
+	variable FE_I: bit;
+	begin
+		if RESETn = '0' then
+			FE_I := '0';
+			FE <= '0';
+		elsif CLK = '1' and CLK' event then
+			if RE = '0' then
+				FE_I := '0';
+				FE <= '0';
+			elsif CLK_STRB = '1' then
+				if RCV_STATE = STOP1 and SDATA_IN_I = '0' and SHIFT_REG /= x"00" then
+					FE_I := '1';
+				elsif RCV_STATE = STOP2 and SDATA_IN_I = '0' and SHIFT_REG /= x"00" then
+					FE_I := '1';
+				elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
+					FE_I := '0'; -- Error resets when correct data appears.
+				end if;
+			end if;
+			if RCV_STATE = SYNC then
+				FE <= FE_I; -- Update the FE every SYNC time.
+			end if;
+		end if;
+	end process FRAME_ERR;
+
+	RCV_STATEREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			RCV_STATE <= IDLE;
+		elsif CLK = '1' and CLK' event then
+			if RE = '0' then
+				RCV_STATE <= IDLE;
+			else
+				RCV_STATE <= RCV_NEXT_STATE;
+			end if;
+		end if;
+	end process RCV_STATEREG;
+	
+	RCV_STATEDEC: process(RCV_STATE, SDATA_IN_I, BITCNT, CLK_STRB, STARTBIT,
+						  CLK_2_STRB, ST, CLK_MODE, CL, P_ENA, SHIFT_REG)
+	begin
+		case RCV_STATE is
+			when IDLE =>
+				if ST = "00" then
+					RCV_NEXT_STATE <= SAMPLE; -- Synchronous mode.
+				elsif SDATA_IN_I = '0' and CLK_MODE = '0' then
+					RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode.
+				elsif STARTBIT = true and CLK_MODE = '1' then
+					RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode.
+				else
+					RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-)
+				end if;
+			when WAIT_START =>
+				-- This state delays the sample process by one CLK_STRB pulse
+				-- to eliminate the start bit.
+				if CLK_STRB = '1' then
+					RCV_NEXT_STATE <= SAMPLE;
+				else
+					RCV_NEXT_STATE <= WAIT_START;
+				end if;
+			when SAMPLE =>
+				if CLK_STRB = '1' then
+					if CL = "11"  and BITCNT < "100" then
+						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 5 data bits.
+					elsif CL = "10" and BITCNT < "101" then
+						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 6 data bits.
+					elsif CL = "01" and BITCNT < "110" then
+						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits.
+					elsif CL = "00" and BITCNT < "111" then
+						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits.
+					elsif ST = "00" and P_ENA = '0' then -- Synchronous mode (no stop bits).
+						RCV_NEXT_STATE <= IDLE; -- No parity check enabled.
+					elsif P_ENA = '0' then
+						RCV_NEXT_STATE <= STOP1; -- No parity check enabled.
+					else
+						RCV_NEXT_STATE <= PARITY; -- Parity enabled.
+					end if;
+				else
+					RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode.
+				end if;
+			when PARITY =>
+				if CLK_STRB = '1' then
+					if ST = "00" then -- Synchronous mode (no stop bits).
+						RCV_NEXT_STATE <= IDLE;
+					else
+						RCV_NEXT_STATE <= STOP1;
+					end if;
+				else
+					RCV_NEXT_STATE <= PARITY;
+				end if;				
+			when STOP1 =>
+				if CLK_STRB = '1' then
+					if SHIFT_REG > x"00" and SDATA_IN_I = '0' then -- No Stop bit after non zero data.
+						RCV_NEXT_STATE <= SYNC; -- Framing error detected.
+					elsif ST = "11" or ST = "10" then
+						RCV_NEXT_STATE <= STOP2; -- More than one stop bits selected.
+					else
+						RCV_NEXT_STATE <= SYNC; -- One stop bit selected.
+					end if;
+				else
+					RCV_NEXT_STATE <= STOP1;
+				end if;				
+			when STOP2 =>
+				if CLK_2_STRB = '1'  and ST = "10" then
+					RCV_NEXT_STATE <= SYNC; -- One and a half stop bits selected.
+				elsif CLK_STRB = '1' then
+					RCV_NEXT_STATE <= SYNC; -- Two stop bits selected.
+				else
+					RCV_NEXT_STATE <= STOP2;
+				end if;				
+			when SYNC =>
+				RCV_NEXT_STATE <= IDLE;
+		end case;
+	end process RCV_STATEDEC;
+end architecture BEHAVIOR;
+
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd
new file mode 100644
index 0000000..fd06bf1
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd
@@ -0,0 +1,238 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- MC68901 compatible multi function port core.                 ----
+----                                                              ----
+---- This is the SUSKA MFP IP core USART top level file.          ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+
+use work.wf68901ip_pkg.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF68901IP_USART_TOP is
+	port (  -- System control:
+			CLK			: in bit;
+			RESETn		: in bit;
+			
+			-- Asynchronous bus control:
+			DSn			: in bit;
+			CSn			: in bit;
+			RWn			: in bit;
+			
+			-- Data and Adresses:
+			RS			: in bit_vector(5 downto 1);
+			DATA_IN		: in bit_vector(7 downto 0);
+			DATA_OUT	: out bit_vector(7 downto 0);
+			DATA_OUT_EN	: out bit;
+
+			-- Serial I/O control:
+			RC			: in bit; -- Receiver clock.
+			TC			: in bit; -- Transmitter clock.
+			SI			: in bit; -- Serial input.
+			SO			: out bit; -- Serial output.
+			SO_EN		: out bit; -- Serial output enable.
+			
+			-- Interrupt channels:
+			RX_ERR_INT	: out bit; -- Receiver errors.
+			RX_BUFF_INT	: out bit; -- Receiver buffer full.
+			TX_ERR_INT	: out bit; -- Transmitter errors.
+			TX_BUFF_INT	: out bit; -- Transmitter buffer empty.
+
+			-- DMA control:
+			RRn			: out bit;
+			TRn			: out bit			
+	);
+end entity WF68901IP_USART_TOP;
+
+architecture STRUCTURE of WF68901IP_USART_TOP is
+	signal BF_I				: bit;
+	signal BE_I				: bit;
+	signal FE_I				: bit;
+	signal OE_I				: bit;
+	signal UE_I				: bit;
+	signal PE_I				: bit;
+	signal LOOPBACK_I		: bit;
+	signal SD_LEVEL_I		: bit;
+	signal SDATA_IN_I		: bit;
+	signal SDATA_OUT_I		: bit;
+	signal RXCLK_I			: bit;
+	signal CLK_MODE_I		: bit;
+	signal SCR_I			: bit_vector(7 downto 0);
+	signal RX_SAMPLE_I		: bit;
+	signal RX_DATA_I		: bit_vector(7 downto 0);
+	signal TX_DATA_I		: bit_vector(7 downto 0);
+	signal CL_I				: bit_vector(1 downto 0);
+	signal ST_I				: bit_vector(1 downto 0);
+	signal P_ENA_I			: bit;
+	signal P_EOn_I			: bit;
+	signal RE_I				: bit;
+	signal TE_I				: bit;
+	signal FS_CLR_I			: bit;
+	signal SS_I				: bit;
+	signal M_CIP_I			: bit;
+	signal FS_B_I			: bit;
+	signal BR_I				: bit;
+	signal UDR_READ_I		: bit;
+	signal UDR_WRITE_I		: bit;
+	signal RSR_READ_I		: bit;
+	signal TSR_READ_I		: bit;
+	signal TX_END_I			: bit;
+begin
+	SO <= SDATA_OUT_I when TE_I = '1' else SD_LEVEL_I;
+	-- Loopback mode:
+	SDATA_IN_I 	<= 	SDATA_OUT_I when LOOPBACK_I = '1' and TE_I = '1' else 	  -- Loopback, transmitter enabled.
+					'1' 		when LOOPBACK_I = '1' and TE_I = '0' else SI; -- Loopback, transmitter disabled.
+
+	RXCLK_I 	<= 	TC when LOOPBACK_I = '1' else RC;
+	RRn <= '0' when BF_I = '1' and PE_I = '0' and FE_I = '0' else '1';
+	TRn <= not BE_I;
+
+	-- Interrupt sources:
+	RX_ERR_INT 	<= OE_I or PE_I or FE_I or FS_B_I;
+	RX_BUFF_INT	<= BF_I;
+	TX_ERR_INT 	<= UE_I or TX_END_I;
+	TX_BUFF_INT <= BE_I;
+
+	I_USART_CTRL: WF68901IP_USART_CTRL
+	port map(
+			CLK				=> CLK,
+	        RESETn			=> RESETn,
+			DSn				=> DSn,
+			CSn				=> CSn,
+	        RWn     		=> RWn,
+	        RS				=> RS,
+			DATA_IN			=> DATA_IN,
+			DATA_OUT		=> DATA_OUT,
+			DATA_OUT_EN		=> DATA_OUT_EN,
+			LOOPBACK		=> LOOPBACK_I,
+			SDOUT_EN		=> SO_EN,
+			SD_LEVEL		=> SD_LEVEL_I,
+			CLK_MODE		=> CLK_MODE_I,
+			RE				=> RE_I,
+			TE				=> TE_I,
+			P_ENA			=> P_ENA_I,
+			P_EOn			=> P_EOn_I,
+			BF				=> BF_I,
+			BE				=> BE_I,
+			FE				=> FE_I,
+			OE				=> OE_I,
+			UE				=> UE_I,
+			PE				=> PE_I,
+			M_CIP			=> M_CIP_I,	
+			FS_B			=> FS_B_I,
+			SCR_OUT			=> SCR_I,
+			TX_DATA			=> TX_DATA_I,
+			RX_SAMPLE		=> RX_SAMPLE_I,
+			RX_DATA			=> RX_DATA_I,
+			SS				=> SS_I,
+			BR				=> BR_I,
+			CL				=> CL_I,
+			ST				=> ST_I,
+			FS_CLR			=> FS_CLR_I,
+			UDR_READ		=> UDR_READ_I,
+			UDR_WRITE		=> UDR_WRITE_I,
+			RSR_READ		=> RSR_READ_I,
+			TSR_READ		=> TSR_READ_I,
+			TX_END			=> TX_END_I
+	);                                              
+
+	I_USART_RECEIVE: WF68901IP_USART_RX
+	port map (
+			CLK				=> CLK,
+	        RESETn			=> RESETn,
+			SCR				=> SCR_I,
+			RX_SAMPLE		=> RX_SAMPLE_I,
+			RX_DATA			=> RX_DATA_I,
+			CL				=> CL_I,
+			ST				=> ST_I,
+			P_ENA			=> P_ENA_I,
+			P_EOn			=> P_EOn_I,
+			CLK_MODE		=> CLK_MODE_I,
+			RE				=> RE_I,
+			FS_CLR			=> FS_CLR_I,
+			SS				=> SS_I,
+			RXCLK			=> RXCLK_I,
+			SDATA_IN		=> SDATA_IN_I,
+			RSR_READ		=> RSR_READ_I,
+			UDR_READ		=> UDR_READ_I,
+			M_CIP			=> M_CIP_I,	
+			FS_B			=> FS_B_I,
+			BF				=> BF_I,
+			OE				=> OE_I,
+			PE				=> PE_I,
+			FE				=> FE_I
+	);                                              
+
+	I_USART_TRANSMIT: WF68901IP_USART_TX
+	port map (
+			CLK				=> CLK,
+	        RESETn			=> RESETn,
+			SCR				=> SCR_I,
+			TX_DATA			=> TX_DATA_I,
+	        SDATA_OUT		=> SDATA_OUT_I,
+	        TXCLK			=> TC,
+			CL				=> CL_I,
+			ST				=> ST_I,
+			TE				=> TE_I,
+			BR				=> BR_I,
+			P_ENA			=> P_ENA_I,
+			P_EOn			=> P_EOn_I,
+			UDR_WRITE		=> UDR_WRITE_I,
+			TSR_READ		=> TSR_READ_I,
+			CLK_MODE		=> CLK_MODE_I,
+			TX_END			=> TX_END_I,
+			UE				=> UE_I,
+			BE				=> BE_I
+	);                  
+end architecture STRUCTURE;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
new file mode 100644
index 0000000..8de27f3
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
@@ -0,0 +1,387 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI MFP compatible IP Core					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- This is the SUSKA MFP IP core USART transmitter file.        ----
+----                                                              ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B	2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K9A  2009/06/20 WF
+--   TDRE has now synchronous reset to meet preset requirement.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF68901IP_USART_TX is
+  port (
+		CLK			: in bit;
+        RESETn		: in bit;
+
+		SCR			: in bit_vector(7 downto 0); -- Synchronous character.
+		TX_DATA		: in bit_vector(7 downto 0); -- Normal data.
+
+        SDATA_OUT	: out bit; -- Serial data output.
+        TXCLK		: in bit;  -- Transmitter clock.
+
+		CL			: in bit_vector(1 downto 0); -- Character length.
+		ST			: in bit_vector(1 downto 0); -- Start and stop bit configuration.
+		TE			: in bit; -- Transmitter enable.
+		BR			: in bit; -- BREAK character send enable (all '0' without stop bit).
+		P_ENA		: in bit; -- Parity enable.
+		P_EOn		: in bit; -- Even or odd parity.
+		UDR_WRITE	: in bit; -- Flag indicating writing the data register.
+		TSR_READ	: in bit; -- Flag indicating reading the transmitter status register.
+		CLK_MODE	: in bit; -- Transmitter clock mode.
+
+		TX_END		: out bit; -- End of transmission flag.
+		UE			: out bit; -- Underrun Flag.
+		BE			: out bit  -- Buffer empty flag.
+       );                                              
+end entity WF68901IP_USART_TX;
+
+architecture BEHAVIOR of WF68901IP_USART_TX is
+type TR_STATES is (IDLE, CHECK_BREAK, LOAD_SHFT, START, SHIFTOUT, PARITY, STOP1, STOP2);
+signal TR_STATE, TR_NEXT_STATE	: TR_STATES;
+signal CLK_STRB		: bit;
+signal CLK_2_STRB	: bit;
+signal SHIFT_REG	: bit_vector(7 downto 0);
+signal BITCNT		: std_logic_vector(2 downto 0);
+signal PARITY_I		: bit;
+signal TDRE			: bit;
+signal BREAK		: bit;
+begin
+	BE <= TDRE; -- Buffer empty flag.
+	
+	-- The default condition in this statement is to ensure
+	-- to cover all possibilities for example if there is a
+	-- one hot decoding of the state machine with wrong states
+	-- (e.g. not one of the given here).
+	SDATA_OUT <= 	'0'				when BREAK = '1'			else
+					'1' 			when TR_STATE = IDLE 		else
+					'1' 			when TR_STATE = LOAD_SHFT 	else
+					'0' 			when TR_STATE = START 		else
+					SHIFT_REG(0) 	when TR_STATE = SHIFTOUT 	else
+					PARITY_I		when TR_STATE = PARITY 		else
+					'1'				when TR_STATE = STOP1 		else
+					'1'				when TR_STATE = STOP2 		else '1';
+
+	P_BREAK : process(RESETn, CLK)
+	-- This process is responsible to control the BREAK signal. After the break request
+	-- is asserted via BR, the break character will be sent after the current transmission has
+	-- finished. The BREAK character is sent until the BR is disabled.
+	variable LOCK : boolean;
+	begin
+		if RESETn = '0' then
+			BREAK <= '0';
+		elsif CLK = '1' and CLK' event then
+			-- Break is only available in the asynchronous mode (ST /= "00").
+			-- The LOCK mechanism is reponsible for sending the BREAK character just once.
+			if TE = '1' and BR = '1' and ST /= "00" and TR_STATE = IDLE and LOCK = false then
+				BREAK <= '1'; -- Break for the case that there is no current transmission.
+				LOCK := true;
+			elsif BR = '1' and ST /= "00" and TR_STATE = STOP1 then
+				BREAK <= '0'; -- Break character sent.
+			elsif BR = '0' then
+				BREAK <= '0';
+				LOCK := false;
+			else
+				BREAK <= '0';	
+			end if;
+		end if;
+	end process P_BREAK;
+
+	CLKDIV: process
+	variable CLK_LOCK	: boolean;
+	variable STRB_LOCK	: boolean;
+	variable CLK_DIVCNT	: std_logic_vector(4 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		if CLK_MODE = '0' then -- Divider off.
+			if TXCLK = '0' and STRB_LOCK = false then  -- Works on negative TXCLK edge.
+				CLK_STRB <= '1';
+				STRB_LOCK := true;
+			elsif TXCLK = '1' then
+				CLK_STRB <= '0';
+				STRB_LOCK := false;
+			else
+				CLK_STRB <= '0';
+			end if;
+			CLK_2_STRB <= '0'; -- No 1 1/2 stop bits in no div by 16 mode.
+		elsif TR_STATE = IDLE then
+			CLK_DIVCNT := "10000"; -- Div by 16 mode.
+			CLK_STRB <= '0';
+		else
+			CLK_STRB <= '0'; -- Default.
+			CLK_2_STRB <= '0'; -- Default.
+			-- Works on negative TXCLK edge:
+			if CLK_DIVCNT > "00000" and TXCLK = '0' and CLK_LOCK = false then
+				CLK_DIVCNT := CLK_DIVCNT - '1';
+				CLK_LOCK := true;
+				if CLK_DIVCNT = "01000" then
+					-- This strobe is asserted at half of the clock cycle.
+					-- It is used for the stop bit timing.
+					CLK_2_STRB <= '1';
+				end if;
+			elsif CLK_DIVCNT = "00000" then
+				CLK_DIVCNT := "10000"; -- Div by 16 mode.
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				end if;
+			elsif TXCLK = '1' then
+				CLK_LOCK := false;
+				STRB_LOCK := false;
+			end if;
+		end if;
+	end process CLKDIV;
+
+	SHIFTREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SHIFT_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if TR_STATE = LOAD_SHFT and TDRE = '1' then -- Lost data ...
+				case ST is
+					when "00" => -- Synchronous mode.
+						SHIFT_REG <= SCR; -- Send the synchronous character.
+					when others => -- Asynchronous mode.
+						SHIFT_REG <= x"5A"; -- Load the shift register with a mark (underrun).
+				end case;
+			elsif TR_STATE = LOAD_SHFT then
+				-- Load 'normal' data if there is no break condition:
+				case CL is
+					when "11" => SHIFT_REG <= "000" & TX_DATA(4 downto 0); -- 5 databits.
+					when "10" => SHIFT_REG <= "00" & TX_DATA(5 downto 0); -- 6 databits.
+					when "01" => SHIFT_REG <= '0' & TX_DATA(6 downto 0); -- 7 databits.
+					when "00" => SHIFT_REG <= TX_DATA; -- 8 databits.
+				end case;
+			elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then
+				SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right.
+			end if;
+		end if;
+	end process SHIFTREG;	
+
+	P_BITCNT: process
+	-- Counter for the data bits transmitted.
+	begin
+		wait until CLK = '1' and CLK' event;
+		if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
+			BITCNT <= BITCNT + '1';
+		elsif TR_STATE /= SHIFTOUT then
+			BITCNT <= "000";
+		end if;
+	end process P_BITCNT;
+
+	BUFFER_EMPTY: process
+	-- Transmit data register empty flag.
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' then
+			TDRE <= '1';
+		elsif TE = '0' then
+			TDRE <= '1';
+		elsif TR_STATE = START and BREAK = '0' then
+			-- Data has been loaded to the shift register,
+			-- thus data register is free again.
+			-- If the BREAK flag is enabled, the BE flag
+			-- respective TDRE flag cannot be set.
+			TDRE <= '1';
+		elsif  UDR_WRITE = '1' then
+			TDRE <= '0';
+		end if;
+	end process BUFFER_EMPTY;
+
+	UNDERRUN: process(RESETn, CLK)
+	variable LOCK	: boolean;
+	begin
+		if RESETn = '0' then
+			UE <= '0';
+			LOCK := false;
+		elsif CLK = '1' and CLK' event then
+			if TE = '0' then
+				UE <= '0';
+				LOCK := false;
+			elsif CLK_STRB = '1' and TR_STATE = START then
+				-- Underrun appears if TDRE is '0' at the end of this state.
+				UE <= TDRE; -- Never true for enabled BREAK flag. See alos process BUFFER_EMPTY.
+				LOCK := true;
+			elsif CLK_STRB = '1' then
+				LOCK := false; -- Disables clearing UE one transmit clock cycle.
+			elsif TSR_READ = '1' and LOCK = false then
+				UE <= '0';
+			end if;
+		end if;
+	end process UNDERRUN;
+	
+	P_TX_END: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			TX_END <= '0';
+		elsif CLK = '1' and CLK' event then
+			if TE = '1' then -- Transmitter enabled.
+				TX_END <= '0';
+			elsif TE = '0' and TR_STATE = IDLE then
+				TX_END <= '1';
+			end if;
+		end if;
+	end process P_TX_END;
+	
+	PARITY_GEN: process
+	variable PAR_TMP	: bit;
+	begin
+		wait until CLK = '1' and CLK' event;
+		if TR_STATE = START then -- Calculate the parity during the start phase.
+		    for i in 1 to 7 loop
+		        if i = 1 then
+		            PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
+		        else
+		            PAR_TMP := PAR_TMP xor SHIFT_REG(i);
+		        end if;
+		    end loop;
+			if P_ENA = '1' and P_EOn = '1' then -- Even parity.
+				PARITY_I <= PAR_TMP;
+			elsif P_ENA = '1' and P_EOn = '0' then -- Odd parity.
+				PARITY_I <= not PAR_TMP;
+			else -- No parity.
+				PARITY_I <= '0';		
+			end if;
+		end if;
+	end process PARITY_GEN;
+
+	TR_STATEREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			TR_STATE <= IDLE;
+		elsif CLK = '1' and CLK' event then
+			TR_STATE <= TR_NEXT_STATE;
+		end if;
+	end process TR_STATEREG;
+	
+	TR_STATEDEC: process(TR_STATE, CLK_STRB, CLK_2_STRB, BITCNT, TDRE, BREAK, TE, ST, P_ENA, CL, BR)
+	begin
+		case TR_STATE is
+			when IDLE =>
+				-- This IDLE state is just one clock cycle and is required to give the
+				-- break process time to set the BREAK flag.
+				TR_NEXT_STATE <= CHECK_BREAK;
+			when CHECK_BREAK =>
+				if BREAK = '1' then -- Send break character.
+					-- Do not load any data to the shift register, go directly
+					-- to the START state.
+					TR_NEXT_STATE <= START;
+				-- Start enabled transmitter, if the data register is not empty.
+				 -- Do not send any further data for the case of an asserted BR flag.
+				elsif TE = '1' and TDRE = '0' and BR = '0' then
+					TR_NEXT_STATE <= LOAD_SHFT;
+				else
+					TR_NEXT_STATE <= IDLE; -- Go back, scan for BREAK.
+				end if;
+			when LOAD_SHFT =>
+				TR_NEXT_STATE <= START;
+			when START => -- Send the start bit.
+				if CLK_STRB = '1' then
+					TR_NEXT_STATE <= SHIFTOUT;
+				else
+					TR_NEXT_STATE <= START;
+				end if;
+			when SHIFTOUT =>
+				if CLK_STRB = '1' then
+					if BITCNT < "100" and CL = "11" then
+						TR_NEXT_STATE <= SHIFTOUT; -- Transmit 5 data bits.
+					elsif BITCNT < "101" and CL = "10" then
+						TR_NEXT_STATE <= SHIFTOUT; -- Transmit 6 data bits.
+					elsif BITCNT < "110" and CL = "01" then
+						TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data bits.
+					elsif BITCNT < "111" and CL = "00" then
+						TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data bits.
+					elsif P_ENA = '0' and BREAK = '1' then
+						TR_NEXT_STATE <= IDLE; -- Break condition, no parity check enabled, no stop bits.
+					elsif P_ENA = '0' and ST = "00" then
+						TR_NEXT_STATE <= IDLE; -- Synchronous mode, no parity check enabled.
+					elsif P_ENA = '0' then
+						TR_NEXT_STATE <= STOP1; -- Asynchronous mode, no parity check enabled.
+					else
+						TR_NEXT_STATE <= PARITY; -- Parity enabled.
+					end if;
+				else
+					TR_NEXT_STATE <= SHIFTOUT;
+				end if;
+			when PARITY =>
+				if CLK_STRB = '1' then
+					if ST = "00" then -- Synchronous mode (no stop bits).
+						TR_NEXT_STATE <= IDLE;
+					elsif BREAK = '1' then -- No stop bits during break condition.
+						TR_NEXT_STATE <= IDLE;
+					else
+						TR_NEXT_STATE <= STOP1;
+					end if;
+				else
+					TR_NEXT_STATE <= PARITY;
+				end if;				
+			when STOP1 =>
+				if CLK_STRB = '1' and (ST = "11" or ST = "10") then
+					TR_NEXT_STATE <= STOP2; -- More than one stop bits selected.
+				elsif CLK_STRB = '1' then
+					TR_NEXT_STATE <= IDLE; -- One stop bits selected.
+				else
+					TR_NEXT_STATE <= STOP1;
+				end if;				
+			when STOP2 =>
+				if CLK_2_STRB = '1' and ST = "10" then
+					TR_NEXT_STATE <= IDLE; -- One and a half stop bits selected.
+				elsif CLK_STRB = '1' then
+					TR_NEXT_STATE <= IDLE; -- Two stop bits detected.
+				else
+					TR_NEXT_STATE <= STOP2;
+				end if;				
+		end case;
+	end process TR_STATEDEC;
+end architecture BEHAVIOR;
+
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface.vhd
new file mode 100644
index 0000000..685fc02
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface.vhd
@@ -0,0 +1,228 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI IP Core peripheral Add-On				              ----
+----                                                              ----
+---- This file is part of the FPGA-ATARI project.                 ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- This hardware provides an interface to connect to a SD-Card. ----
+----                                                              ----
+---- This interface is based on the project 'SatanDisk' of        ----
+---- Miroslav Nohaj 'Jookie'. The code is an interpretation of    ----
+---- the original code, written in VERILOG. It is provided for    ----
+---- the use in a system on programmable chips (SOPC).            ----
+----                                                              ----
+---- Timing: Use a clock frequency of 16MHz for this component.   ----
+----         Use the same clock frequency for the connected AVR   ----
+----         microcontroller.                                     ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2007 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+---- This hardware works with the original ATARI                  ----
+---- hard dik driver.                                             ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 1.0  2007/01/05 WF
+--   Initial Release.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF_SD_CARD is
+	port (
+		-- System:
+		RESETn			: in bit;
+		CLK				: in bit; -- 16MHz, see above.
+
+		-- ACSI section:		
+		ACSI_A1			: in bit;
+		ACSI_CSn		: in bit;
+		ACSI_ACKn		: in bit;
+		ACSI_INTn		: out bit;
+		ACSI_DRQn		: out bit;
+		ACSI_D			: inout std_logic_vector(7 downto 0);
+
+		-- Microcontroller interface:
+		MC_D			: inout std_logic_vector(7 downto 0);
+		MC_DO			: in bit;
+		MC_PIO_DMAn		: in bit;
+		MC_RWn			: in bit;
+		MC_CLR_CMD		: in bit;
+		MC_DONE			: out bit;
+		MC_GOT_CMD		: out bit
+      );
+end WF_SD_CARD;
+
+architecture BEHAVIOR of WF_SD_CARD is
+signal DATA_REG		: std_logic_vector(7 downto 0);
+signal D0_REG		: bit;
+signal INT_REG		: bit;
+signal DRQ_REG		: bit;
+signal DONE_REG		: bit;
+signal GOT_CMD_REG	: bit;
+signal HOLD			: bit;
+signal PREV_CSn		: bit;
+signal PREV_ACKn	: bit;
+begin
+	MC_D <= DATA_REG when MC_RWn = '0' and DONE_REG = '1' else (others => 'Z');
+	ACSI_D <= DATA_REG when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else (others => 'Z');
+	ACSI_INTn <= INT_REG;
+	ACSI_DRQn <= DRQ_REG;
+	MC_DONE <= DONE_REG;
+	MC_GOT_CMD <= GOT_CMD_REG;
+
+	P_DATA: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DATA_REG <= (others => '0');
+		elsif CLK = '1' and CLK' event then
+			if D0_REG = '0' and MC_DO = '1' and MC_RWn = '1' then
+				DATA_REG <= MC_D;  -- Read from AVR to ACSI.
+			end if;
+			--			
+			if PREV_CSn = '0' and ACSI_CSn = '0' and MC_RWn = '0' and DONE_REG = '0' then
+				DATA_REG <= ACSI_D; -- Write from ACSI to AVR.
+			elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and MC_RWn = '0' and DONE_REG = '0' then
+				DATA_REG <= ACSI_D; -- Write from ACSI to AVR.
+			end if;
+		end if;
+	end process P_DATA;
+	
+	P_SYNC: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		PREV_CSn <= ACSI_CSn;
+		PREV_ACKn <= ACSI_ACKn;
+	end process P_SYNC;
+
+	P_INT_DRQ: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			INT_REG <= '1'; -- No interrupt.
+			DRQ_REG <= '1'; -- No data request.
+		elsif CLK = '1' and CLK' event then
+			if D0_REG = '0' and MC_DO = '1' and MC_PIO_DMAn = '1' then -- Positive MC_DO edge.
+				INT_REG <= '0'; -- Release an interrupt.
+				DRQ_REG <= '1';
+			elsif D0_REG = '0' and MC_DO = '1' then
+				INT_REG <= '1';
+				DRQ_REG <= '0'; -- Release a data request.
+			end if;
+			--
+			if MC_CLR_CMD = '1' then -- Clear done.
+				INT_REG <= '1'; -- Restore INT_REG.
+				DRQ_REG <= '1'; -- Restore DRQ_REG.
+			end if;
+			--
+			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
+				if ACSI_CSn = '0' then
+					INT_REG <= '1';
+				end if;
+				--
+				if ACSI_ACKn = '0' then
+					DRQ_REG <= '1';
+				end if;
+			end if;
+		end if;
+	end process P_INT_DRQ;
+				
+	P_HOLD: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			HOLD <= '0';
+		elsif CLK = '1' and CLK' event then
+			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
+				HOLD <= '1';
+			elsif PREV_CSn = '1' and ACSI_CSn = '1' then -- If signal is high.
+				HOLD <= '0';
+			elsif PREV_ACKn = '1' and ACSI_ACKn = '1' then -- If signal is high.
+				HOLD <= '0';
+			elsif PREV_CSn = '0' and ACSI_CSn = '1' then -- Rising edge.
+				HOLD <= '1';
+			elsif PREV_ACKn = '0' and ACSI_ACKn = '1' then -- Rising edge.
+				HOLD <= '1';
+			elsif MC_CLR_CMD = '1' then -- Clear done.
+				HOLD <= '0';
+			end if;
+		end if;
+	end process P_HOLD;
+
+	P_DONE: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DONE_REG <= '0';
+		elsif CLK = '1' and CLK' event then
+			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
+				DONE_REG <= '1';
+			elsif MC_CLR_CMD = '1' then -- Clear done.
+				DONE_REG <= '0';
+			elsif D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge.
+				DONE_REG <= '0';
+			elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge.
+				DONE_REG <= '0';
+			end if;
+		end if;
+	end process P_DONE;
+
+	P_DO_REG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			D0_REG <= '0';
+		elsif CLK = '1' and CLK' event then
+			if D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge.
+				D0_REG <= MC_DO;
+			elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge.
+				D0_REG <= MC_DO;
+			end if;
+		end if;
+	end process P_DO_REG;
+
+	P_GOT_CMD: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			GOT_CMD_REG <= '0';
+		elsif CLK = '1' and CLK' event then
+			if PREV_CSn = '0' and ACSI_CSn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then
+				GOT_CMD_REG <= '1'; -- If command was received.
+			elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then
+				GOT_CMD_REG <= '1'; -- If command was received.
+			elsif MC_CLR_CMD = '1' then -- Clear done.
+				GOT_CMD_REG <= '0';
+			end if;
+		end if;
+	end process P_GOT_CMD;
+end architecture BEHAVIOR;
\ No newline at end of file
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd
new file mode 100644
index 0000000..b1dfe91
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd
@@ -0,0 +1,240 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI IP Core peripheral Add-On				              ----
+----                                                              ----
+---- This file is part of the FPGA-ATARI project.                 ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- This hardware provides an interface to connect to a SD-Card. ----
+----                                                              ----
+---- This interface is based on the project 'SatanDisk' of        ----
+---- Miroslav Nohaj 'Jookie'. The code is an interpretation of    ----
+---- the original code, written in VERILOG. It is provided for    ----
+---- the use in a system on programmable chips (SOPC).            ----
+----                                                              ----
+---- Timing: Use a clock frequency of 16MHz for this component.   ----
+----         Use the same clock frequency for the connected AVR   ----
+----         microcontroller.                                     ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2007 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+---- This hardware works with the original ATARI                  ----
+---- hard dik driver.                                             ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K7A  2007/01/05 WF
+--   Initial Release.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF_SD_CARD is
+	port (
+		-- System:
+		RESETn			: in bit;
+		CLK				: in bit; -- 16MHz, see above.
+
+		-- ACSI section:		
+		ACSI_A1			: in bit;
+		ACSI_CSn		: in bit;
+		ACSI_ACKn		: in bit;
+		ACSI_INTn		: out bit;
+		ACSI_DRQn		: out bit;
+		ACSI_D_IN		: in std_logic_vector(7 downto 0);
+		ACSI_D_OUT		: out std_logic_vector(7 downto 0);
+		ACSI_D_EN		: out bit;
+
+		-- Microcontroller interface:
+		MC_DO			: in bit;
+		MC_PIO_DMAn		: in bit;
+		MC_RWn			: in bit;
+		MC_CLR_CMD		: in bit;
+		MC_DONE			: out bit;
+		MC_GOT_CMD		: out bit;
+		MC_D_IN			: in std_logic_vector(7 downto 0);
+		MC_D_OUT		: out std_logic_vector(7 downto 0);
+		MC_D_EN			: out bit
+      );
+end WF_SD_CARD;
+
+architecture BEHAVIOR of WF_SD_CARD is
+signal DATA_REG		: std_logic_vector(7 downto 0);
+signal D0_REG		: bit;
+signal INT_REG		: bit;
+signal DRQ_REG		: bit;
+signal DONE_REG		: bit;
+signal GOT_CMD_REG	: bit;
+signal HOLD			: bit;
+signal PREV_CSn		: bit;
+signal PREV_ACKn	: bit;
+begin
+	MC_D_OUT <= DATA_REG when MC_RWn = '0' and DONE_REG = '1' else (others => '0');
+	MC_D_EN <= '1' when MC_RWn = '0' and DONE_REG = '1' else '0';
+	ACSI_D_OUT <= DATA_REG when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else (others => '0');
+--ACSI_D_EN <= '1' when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else '0';
+ACSI_D_EN <= '0'; -- Disabled.
+--ACSI_INTn <= INT_REG;
+ACSI_INTn <= '1'; -- Disabled.
+--ACSI_DRQn <= DRQ_REG;
+ACSI_DRQn <= '1'; -- Disabled.
+	MC_DONE <= DONE_REG;
+	MC_GOT_CMD <= GOT_CMD_REG;
+
+	P_DATA: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DATA_REG <= (others => '0');
+		elsif CLK = '1' and CLK' event then
+			if D0_REG = '0' and MC_DO = '1' and MC_RWn = '1' then
+				DATA_REG <= MC_D_IN;  -- Read from AVR to ACSI.
+			end if;
+			--			
+			if PREV_CSn = '0' and ACSI_CSn = '0' and MC_RWn = '0' and DONE_REG = '0' then
+				DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR.
+			elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and MC_RWn = '0' and DONE_REG = '0' then
+				DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR.
+			end if;
+		end if;
+	end process P_DATA;
+	
+	P_SYNC: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		PREV_CSn <= ACSI_CSn;
+		PREV_ACKn <= ACSI_ACKn;
+	end process P_SYNC;
+
+	P_INT_DRQ: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			INT_REG <= '1'; -- No interrupt.
+			DRQ_REG <= '1'; -- No data request.
+		elsif CLK = '1' and CLK' event then
+			if D0_REG = '0' and MC_DO = '1' and MC_PIO_DMAn = '1' then -- Positive MC_DO edge.
+				INT_REG <= '0'; -- Release an interrupt.
+				DRQ_REG <= '1';
+			elsif D0_REG = '0' and MC_DO = '1' then
+				INT_REG <= '1';
+				DRQ_REG <= '0'; -- Release a data request.
+			end if;
+			--
+			if MC_CLR_CMD = '1' then -- Clear done.
+				INT_REG <= '1'; -- Restore INT_REG.
+				DRQ_REG <= '1'; -- Restore DRQ_REG.
+			end if;
+			--
+			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
+				if ACSI_CSn = '0' then
+					INT_REG <= '1';
+				end if;
+				--
+				if ACSI_ACKn = '0' then
+					DRQ_REG <= '1';
+				end if;
+			end if;
+		end if;
+	end process P_INT_DRQ;
+				
+	P_HOLD: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			HOLD <= '0';
+		elsif CLK = '1' and CLK' event then
+			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
+				HOLD <= '1';
+			elsif PREV_CSn = '1' and ACSI_CSn = '1' then -- If signal is high.
+				HOLD <= '0';
+			elsif PREV_ACKn = '1' and ACSI_ACKn = '1' then -- If signal is high.
+				HOLD <= '0';
+			elsif PREV_CSn = '0' and ACSI_CSn = '1' then -- Rising edge.
+				HOLD <= '1';
+			elsif PREV_ACKn = '0' and ACSI_ACKn = '1' then -- Rising edge.
+				HOLD <= '1';
+			elsif MC_CLR_CMD = '1' then -- Clear done.
+				HOLD <= '0';
+			end if;
+		end if;
+	end process P_HOLD;
+
+	P_DONE: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DONE_REG <= '0';
+		elsif CLK = '1' and CLK' event then
+			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
+				DONE_REG <= '1';
+			elsif MC_CLR_CMD = '1' then -- Clear done.
+				DONE_REG <= '0';
+			elsif D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge.
+				DONE_REG <= '0';
+			elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge.
+				DONE_REG <= '0';
+			end if;
+		end if;
+	end process P_DONE;
+
+	P_DO_REG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			D0_REG <= '0';
+		elsif CLK = '1' and CLK' event then
+			if D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge.
+				D0_REG <= MC_DO;
+			elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge.
+				D0_REG <= MC_DO;
+			end if;
+		end if;
+	end process P_DO_REG;
+
+	P_GOT_CMD: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			GOT_CMD_REG <= '0';
+		elsif CLK = '1' and CLK' event then
+-- ?? ACSI_CSn doppelt!
+if PREV_CSn = '0' and ACSI_CSn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then
+				GOT_CMD_REG <= '1'; -- If command was received.
+			elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then
+				GOT_CMD_REG <= '1'; -- If command was received.
+			elsif MC_CLR_CMD = '1' then -- Clear done.
+				GOT_CMD_REG <= '0';
+			end if;
+		end if;
+	end process P_GOT_CMD;
+end architecture BEHAVIOR;
\ No newline at end of file
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak
new file mode 100644
index 0000000..0200dea
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak
@@ -0,0 +1,239 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- ATARI IP Core peripheral Add-On				              ----
+----                                                              ----
+---- This file is part of the FPGA-ATARI project.                 ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- This hardware provides an interface to connect to a SD-Card. ----
+----                                                              ----
+---- This interface is based on the project 'SatanDisk' of        ----
+---- Miroslav Nohaj 'Jookie'. The code is an interpretation of    ----
+---- the original code, written in VERILOG. It is provided for    ----
+---- the use in a system on programmable chips (SOPC).            ----
+----                                                              ----
+---- Timing: Use a clock frequency of 16MHz for this component.   ----
+----         Use the same clock frequency for the connected AVR   ----
+----         microcontroller.                                     ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2007 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+---- This hardware works with the original ATARI                  ----
+---- hard dik driver.                                             ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K7A  2007/01/05 WF
+--   Initial Release.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF_SD_CARD is
+	port (
+		-- System:
+		RESETn			: in bit;
+		CLK				: in bit; -- 16MHz, see above.
+
+		-- ACSI section:		
+		ACSI_A1			: in bit;
+		ACSI_CSn		: in bit;
+		ACSI_ACKn		: in bit;
+		ACSI_INTn		: out bit;
+		ACSI_DRQn		: out bit;
+		ACSI_D_IN		: in std_logic_vector(7 downto 0);
+		ACSI_D_OUT		: out std_logic_vector(7 downto 0);
+		ACSI_D_EN		: out bit;
+
+		-- Microcontroller interface:
+		MC_DO			: in bit;
+		MC_PIO_DMAn		: in bit;
+		MC_RWn			: in bit;
+		MC_CLR_CMD		: in bit;
+		MC_DONE			: out bit;
+		MC_GOT_CMD		: out bit;
+		MC_D_IN			: in std_logic_vector(7 downto 0);
+		MC_D_OUT		: out std_logic_vector(7 downto 0);
+		MC_D_EN			: out bit
+      );
+end WF_SD_CARD;
+
+architecture BEHAVIOR of WF_SD_CARD is
+signal DATA_REG		: std_logic_vector(7 downto 0);
+signal D0_REG		: bit;
+signal INT_REG		: bit;
+signal DRQ_REG		: bit;
+signal DONE_REG		: bit;
+signal GOT_CMD_REG	: bit;
+signal HOLD			: bit;
+signal PREV_CSn		: bit;
+signal PREV_ACKn	: bit;
+begin
+	MC_D_OUT <= DATA_REG when MC_RWn = '0' and DONE_REG = '1' else (others => '0');
+	MC_D_EN <= '1' when MC_RWn = '0' and DONE_REG = '1' else '0';
+	ACSI_D_OUT <= DATA_REG when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else (others => '0');
+-- ???:
+--ACSI_D_EN <= '1' when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else '0';
+ACSI_D_EN <= '0';
+	ACSI_INTn <= INT_REG;
+	ACSI_DRQn <= DRQ_REG;
+	MC_DONE <= DONE_REG;
+	MC_GOT_CMD <= GOT_CMD_REG;
+
+	P_DATA: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DATA_REG <= (others => '0');
+		elsif CLK = '1' and CLK' event then
+			if D0_REG = '0' and MC_DO = '1' and MC_RWn = '1' then
+				DATA_REG <= MC_D_IN;  -- Read from AVR to ACSI.
+			end if;
+			--			
+			if PREV_CSn = '0' and ACSI_CSn = '0' and MC_RWn = '0' and DONE_REG = '0' then
+				DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR.
+			elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and MC_RWn = '0' and DONE_REG = '0' then
+				DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR.
+			end if;
+		end if;
+	end process P_DATA;
+	
+	P_SYNC: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		PREV_CSn <= ACSI_CSn;
+		PREV_ACKn <= ACSI_ACKn;
+	end process P_SYNC;
+
+	P_INT_DRQ: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			INT_REG <= '1'; -- No interrupt.
+			DRQ_REG <= '1'; -- No data request.
+		elsif CLK = '1' and CLK' event then
+			if D0_REG = '0' and MC_DO = '1' and MC_PIO_DMAn = '1' then -- Positive MC_DO edge.
+				INT_REG <= '0'; -- Release an interrupt.
+				DRQ_REG <= '1';
+			elsif D0_REG = '0' and MC_DO = '1' then
+				INT_REG <= '1';
+				DRQ_REG <= '0'; -- Release a data request.
+			end if;
+			--
+			if MC_CLR_CMD = '1' then -- Clear done.
+				INT_REG <= '1'; -- Restore INT_REG.
+				DRQ_REG <= '1'; -- Restore DRQ_REG.
+			end if;
+			--
+			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
+				if ACSI_CSn = '0' then
+					INT_REG <= '1';
+				end if;
+				--
+				if ACSI_ACKn = '0' then
+					DRQ_REG <= '1';
+				end if;
+			end if;
+		end if;
+	end process P_INT_DRQ;
+				
+	P_HOLD: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			HOLD <= '0';
+		elsif CLK = '1' and CLK' event then
+			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
+				HOLD <= '1';
+			elsif PREV_CSn = '1' and ACSI_CSn = '1' then -- If signal is high.
+				HOLD <= '0';
+			elsif PREV_ACKn = '1' and ACSI_ACKn = '1' then -- If signal is high.
+				HOLD <= '0';
+			elsif PREV_CSn = '0' and ACSI_CSn = '1' then -- Rising edge.
+				HOLD <= '1';
+			elsif PREV_ACKn = '0' and ACSI_ACKn = '1' then -- Rising edge.
+				HOLD <= '1';
+			elsif MC_CLR_CMD = '1' then -- Clear done.
+				HOLD <= '0';
+			end if;
+		end if;
+	end process P_HOLD;
+
+	P_DONE: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DONE_REG <= '0';
+		elsif CLK = '1' and CLK' event then
+			if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then
+				DONE_REG <= '1';
+			elsif MC_CLR_CMD = '1' then -- Clear done.
+				DONE_REG <= '0';
+			elsif D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge.
+				DONE_REG <= '0';
+			elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge.
+				DONE_REG <= '0';
+			end if;
+		end if;
+	end process P_DONE;
+
+	P_DO_REG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			D0_REG <= '0';
+		elsif CLK = '1' and CLK' event then
+			if D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge.
+				D0_REG <= MC_DO;
+			elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge.
+				D0_REG <= MC_DO;
+			end if;
+		end if;
+	end process P_DO_REG;
+
+	P_GOT_CMD: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			GOT_CMD_REG <= '0';
+		elsif CLK = '1' and CLK' event then
+-- ?? ACSI_CSn doppelt!
+--if PREV_CSn = '0' and ACSI_CSn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then
+				GOT_CMD_REG <= '1'; -- If command was received.
+			elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then
+				GOT_CMD_REG <= '1'; -- If command was received.
+			elsif MC_CLR_CMD = '1' then -- Clear done.
+				GOT_CMD_REG <= '0';
+			end if;
+		end if;
+	end process P_GOT_CMD;
+end architecture BEHAVIOR;
\ No newline at end of file
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
new file mode 100644
index 0000000..9d048de
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
@@ -0,0 +1,84 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- YM2149 compatible sound generator.				              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Model of the ST or STE's YM2149 sound generator.             ----
+----                                                              ----
+---- This is the package file containing the component            ----
+---- declarations.                                                ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package WF2149IP_PKG is
+type BUSCYCLES is (INACTIVE, R_READ, R_WRITE, ADDRESS);
+
+component WF2149IP_WAVE
+	port(
+		RESETn		: in bit;
+		SYS_CLK		: in bit;
+
+		WAV_STRB	: in bit;
+
+		ADR			: in bit_vector(3 downto 0);
+		DATA_IN		: in std_logic_vector(7 downto 0);
+		DATA_OUT	: out std_logic_vector(7 downto 0);
+		DATA_EN		: out bit;
+		
+		BUSCYCLE	: in BUSCYCLES;
+		CTRL_REG	: in bit_vector(5 downto 0);
+
+		OUT_A		: out bit;
+		OUT_B		: out bit;
+		OUT_C		: out bit
+	);
+end component;
+end WF2149IP_PKG;
\ No newline at end of file
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
new file mode 100644
index 0000000..3f5024a
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
@@ -0,0 +1,170 @@
+----------------------------------------------------------------------
+----                                                              ----
+----  YM2149 compatible sound generator.			              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Model of the ST or STE's YM2149 sound generator.             ----
+---- This IP core of the sound generator differs slightly from    ----
+---- the original. Firstly it is a synchronous design without any ----
+---- latches (like assumed in the original chip). This required   ----
+---- the introduction of a system adequate clock. In detail this  ----
+---- SYS_CLK should on the one hand be fast enough to meet the    ----
+---- timing requirements of the system's bus cycle and should one ----
+---- the other hand drive the PWM modules correctly. To meet both ----
+---- a SYS_CLK of 16MHz or above is recommended.                  ----
+---- Secondly, the original chip has an implemented DA converter. ----
+---- This feature is not possible in today's FPGAs. Therefore the ----
+---- converter is replaced by pulse width modulators. This solu-  ----
+---- tion is very simple in comparison to other approaches like   ----
+---- external DA converters with wave tables etc. The soltution   ----
+---- with the pulse width modulators is probably not as accurate  ----
+---- DAs with wavetables. For a detailed descrition of the hard-  ----
+---- ware PWM filter look at the end of the wave file, where the  ----
+---- pulse width modulators can be found.                         ----
+---- For a proper operation it is required, that the wave clock   ----
+---- is lower than the system clock. A good choice is for example ----
+---- 2MHz for the wave clock and 16MHz for the system clock.      ----
+----                                                              ----
+---- Main module file.                                            ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B	2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8B  2008/12/24 WF
+--   Rewritten this top level file as a wrapper for the top_soc file.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.wf2149ip_pkg.all;
+
+entity WF2149IP_TOP is
+	port(
+		
+		SYS_CLK		: in bit; -- Read the inforation in the header!
+		RESETn   	: in bit;
+
+		WAV_CLK		: in bit; -- Read the inforation in the header!
+		SELn		: in bit;
+		
+		BDIR		: in bit;
+		BC2, BC1	: in bit;
+
+		A9n, A8		: in bit;
+		DA			: inout std_logic_vector(7 downto 0);
+		
+		IO_A		: inout std_logic_vector(7 downto 0);
+		IO_B		: inout std_logic_vector(7 downto 0);
+		
+		OUT_A		: out bit; -- Analog (PWM) outputs.
+		OUT_B		: out bit;
+		OUT_C		: out bit
+	);
+end WF2149IP_TOP;
+
+architecture STRUCTURE of WF2149IP_TOP is
+component WF2149IP_TOP_SOC
+	port(
+		SYS_CLK		: in bit;
+		RESETn   	: in bit;
+		WAV_CLK		: in bit;
+		SELn		: in bit;
+		BDIR		: in bit;
+		BC2, BC1	: in bit;
+		A9n, A8		: in bit;
+		DA_IN		: in std_logic_vector(7 downto 0);
+		DA_OUT		: out std_logic_vector(7 downto 0);
+		DA_EN		: out bit;
+		IO_A_IN		: in bit_vector(7 downto 0);
+		IO_A_OUT	: out bit_vector(7 downto 0);
+		IO_A_EN		: out bit;
+		IO_B_IN		: in bit_vector(7 downto 0);
+		IO_B_OUT	: out bit_vector(7 downto 0);
+		IO_B_EN		: out bit;
+		OUT_A		: out bit;
+		OUT_B		: out bit;
+		OUT_C		: out bit
+	);
+end component;
+--
+signal DA_OUT       : std_logic_vector(7 downto 0);
+signal DA_EN        : bit;
+signal IO_A_IN      : bit_vector(7 downto 0);
+signal IO_A_OUT     : bit_vector(7 downto 0);
+signal IO_A_EN      : bit;
+signal IO_B_IN      : bit_vector(7 downto 0);
+signal IO_B_OUT     : bit_vector(7 downto 0);
+signal IO_B_EN      : bit;
+begin
+    IO_A_IN <= To_BitVector(IO_A);
+    IO_B_IN <= To_BitVector(IO_B);
+
+    IO_A <= To_StdLogicVector(IO_A_OUT) when IO_A_EN = '1' else (others => 'Z');
+    IO_B <= To_StdLogicVector(IO_B_OUT) when IO_B_EN = '1' else (others => 'Z');
+
+    DA <= DA_OUT when DA_EN = '1' else (others => 'Z');
+
+    I_SOUND: WF2149IP_TOP_SOC
+        port map(SYS_CLK            => SYS_CLK,
+                 RESETn             => RESETn,
+                 WAV_CLK            => WAV_CLK,
+                 SELn               => SELn,
+                 BDIR               => BDIR,
+                 BC2                => BC2,
+                 BC1                => BC1,
+                 A9n                => A9n,
+                 A8                 => A8,
+                 DA_IN              => DA,
+                 DA_OUT             => DA_OUT,
+                 DA_EN              => DA_EN,
+                 IO_A_IN            => IO_A_IN,
+                 IO_A_OUT           => IO_A_OUT,
+                 IO_A_EN            => IO_A_EN,
+                 IO_B_IN            => IO_B_IN,
+                 IO_B_OUT           => IO_B_OUT,
+                 IO_B_EN            => IO_B_EN,
+                 OUT_A              => OUT_A,
+                 OUT_B              => OUT_B,
+                 OUT_C              => OUT_C
+        );
+end STRUCTURE;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
new file mode 100644
index 0000000..77ea5ef
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
@@ -0,0 +1,229 @@
+----------------------------------------------------------------------
+----                                                              ----
+----  YM2149 compatible sound generator.			              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Model of the ST or STE's YM2149 sound generator.             ----
+---- This IP core of the sound generator differs slightly from    ----
+---- the original. Firstly it is a synchronous design without any ----
+---- latches (like assumed in the original chip). This required   ----
+---- the introduction of a system adequate clock. In detail this  ----
+---- SYS_CLK should on the one hand be fast enough to meet the    ----
+---- timing requirements of the system's bus cycle and should one ----
+---- the other hand drive the PWM modules correctly. To meet both ----
+---- a SYS_CLK of 16MHz or above is recommended.                  ----
+---- Secondly, the original chip has an implemented DA converter. ----
+---- This feature is not possible in today's FPGAs. Therefore the ----
+---- converter is replaced by pulse width modulators. This solu-  ----
+---- tion is very simple in comparison to other approaches like   ----
+---- external DA converters with wave tables etc. The soltution   ----
+---- with the pulse width modulators is probably not as accurate  ----
+---- DAs with wavetables. For a detailed descrition of the hard-  ----
+---- ware PWM filter look at the end of the wave file, where the  ----
+---- pulse width modulators can be found.                         ----
+---- For a proper operation it is required, that the wave clock   ----
+---- is lower than the system clock. A good choice is for example ----
+---- 2MHz for the wave clock and 16MHz for the system clock.      ----
+----                                                              ----
+---- Main module file.                                            ----
+---- Top level file for use in systems on programmable chips.     ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+--   Top level file provided for SOC (systems on programmable chips).
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.wf2149ip_pkg.all;
+
+entity WF2149IP_TOP_SOC is
+	port(
+		
+		SYS_CLK		: in bit; -- Read the inforation in the header!
+		RESETn   	: in bit;
+
+		WAV_CLK		: in bit; -- Read the inforation in the header!
+		SELn		: in bit;
+		
+		BDIR		: in bit;
+		BC2, BC1	: in bit;
+
+		A9n, A8		: in bit;
+		DA_IN		: in std_logic_vector(7 downto 0);
+		DA_OUT		: out std_logic_vector(7 downto 0);
+		DA_EN		: out bit;
+		
+		IO_A_IN		: in bit_vector(7 downto 0);
+		IO_A_OUT	: out bit_vector(7 downto 0);
+		IO_A_EN		: out bit;
+		IO_B_IN		: in bit_vector(7 downto 0);
+		IO_B_OUT	: out bit_vector(7 downto 0);
+		IO_B_EN		: out bit;
+
+		OUT_A		: out bit; -- Analog (PWM) outputs.
+		OUT_B		: out bit;
+		OUT_C		: out bit
+	);
+end WF2149IP_TOP_SOC;
+
+architecture STRUCTURE of WF2149IP_TOP_SOC is
+signal BUSCYCLE		: BUSCYCLES;
+signal DATA_OUT_I	: std_logic_vector(7 downto 0);
+signal DATA_EN_I	: bit;
+signal WAV_STRB		: bit;
+signal ADR_I		: bit_vector(3 downto 0);
+signal CTRL_REG		: bit_vector(7 downto 0);
+signal PORT_A		: bit_vector(7 downto 0);
+signal PORT_B		: bit_vector(7 downto 0);
+begin
+	P_WAVSTRB: process(RESETn, SYS_CLK)
+	variable LOCK	: boolean;
+	variable TMP	: bit;
+	begin
+		if RESETn = '0' then
+			LOCK := false;
+			TMP := '0';
+		elsif SYS_CLK = '1' and SYS_CLK' event then
+			if WAV_CLK = '1' and LOCK = false then
+				LOCK := true;
+				TMP := not TMP; -- Divider by 2.
+				case SELn is
+					when '1' 	=> WAV_STRB <= '1';
+					when others => WAV_STRB <= TMP;
+				end case;
+			elsif WAV_CLK = '0' then
+				LOCK := false;
+				WAV_STRB <= '0';
+			else
+				WAV_STRB <= '0';
+			end if;
+		end if;
+	end process P_WAVSTRB;		
+
+	with BDIR & BC2 & BC1 select
+		BUSCYCLE <= INACTIVE	when "000" | "010" | "101",
+					ADDRESS 	when "001" | "100" | "111",
+					R_READ 		when "011",
+					R_WRITE 	when "110";
+
+	ADDRESSLATCH: process(RESETn, SYS_CLK)
+	-- This process is responsible to store the desired register
+	-- address. The default (after reset) is channel A fine tone 
+	-- adjustment.
+	begin
+		if RESETn = '0' then
+			ADR_I <= (others => '0');
+        elsif SYS_CLK = '1' and SYS_CLK' event then
+			if BUSCYCLE = ADDRESS and A9n = '0' and A8 = '1' and DA_IN(7 downto 4) = x"0" then
+				ADR_I <= To_BitVector(DA_IN(3 downto 0));
+			end if;
+		end if;
+	end process ADDRESSLATCH;	
+
+	P_CTRL_REG: process(RESETn, SYS_CLK)
+	-- THIS is the Control register for the mixer and for the I/O ports.
+	begin
+		if RESETn = '0' then
+			CTRL_REG <= x"00";
+		elsif SYS_CLK = '1' and SYS_CLK' event then
+			if BUSCYCLE = R_WRITE and ADR_I = x"7" then
+				CTRL_REG <= To_BitVector(DA_IN);
+			end if;
+		end if;
+	end process P_CTRL_REG;
+	
+	DIG_PORTS: process(RESETn, SYS_CLK)
+	begin
+		if RESETn = '0' then
+			PORT_A <= x"00";
+			PORT_B <= x"00";
+		elsif SYS_CLK = '1' and SYS_CLK' event then
+			if BUSCYCLE = R_WRITE and ADR_I = x"E" then
+				PORT_A <= To_BitVector(DA_IN);
+			elsif BUSCYCLE = R_WRITE and ADR_I = x"F" then
+				PORT_B <= To_BitVector(DA_IN);
+			end if;
+		end if;	
+	end process DIG_PORTS;
+	-- Set port direction to input or to output:
+	IO_A_EN	<= '1' when CTRL_REG(6) = '1' else '0';
+	IO_B_EN <= '1' when CTRL_REG(7) = '1' else '0';
+	IO_A_OUT <= PORT_A;
+	IO_B_OUT <= PORT_B;
+
+	I_PSG_WAVE: WF2149IP_WAVE
+		port map(
+			RESETn		=> RESETn,
+			SYS_CLK	=> SYS_CLK,
+
+			WAV_STRB	=> WAV_STRB,
+
+			ADR			=> ADR_I,
+			DATA_IN		=> DA_IN,
+			DATA_OUT	=> DATA_OUT_I,
+			DATA_EN		=> DATA_EN_I,
+			
+			BUSCYCLE	=> BUSCYCLE,
+			CTRL_REG	=> CTRL_REG(5 downto 0),
+						
+			OUT_A		=> OUT_A,
+			OUT_B		=> OUT_B,
+			OUT_C		=> OUT_C
+		);
+
+	-- Read the ports and registers:
+	DA_EN <= 	'1' when DATA_EN_I = '1' else
+				'1' when BUSCYCLE = R_READ and ADR_I = x"7" else
+				'1' when BUSCYCLE = R_READ and ADR_I = x"E" else
+				'1' when BUSCYCLE = R_READ and ADR_I = x"F" else '0';
+				
+	DA_OUT <= 	DATA_OUT_I when DATA_EN_I = '1' else -- WAV stuff.
+				To_StdLogicVector(IO_A_IN) when BUSCYCLE = R_READ and ADR_I = x"E" else
+				To_StdLogicVector(IO_B_IN) when BUSCYCLE = R_READ and ADR_I = x"F" else
+				To_StdLogicVector(CTRL_REG) when BUSCYCLE = R_READ and ADR_I = x"7" else (others => '0');
+
+end STRUCTURE;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
new file mode 100644
index 0000000..d829f9b
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
@@ -0,0 +1,533 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- YM2149 compatible sound generator.				              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- Model of the ST or STE's YM2149 sound generator.             ----
+----                                                              ----
+---- Waveform generator.                                          ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K9A  2009/06/20 WF
+--   NOISE_OUT has now synchronous reset to meet preset requirement.
+--   Fixed a bug in the envelope generator. Thanks to Lyndon Amsdon finding it.
+--   Correction of the schematic given in the end of this file.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use work.wf2149ip_pkg.all;
+
+entity WF2149IP_WAVE is
+	port(
+		RESETn		: in bit;
+		SYS_CLK		: in bit;
+
+		WAV_STRB	: in bit;
+
+		ADR			: in bit_vector(3 downto 0);
+		DATA_IN		: in std_logic_vector(7 downto 0);
+		DATA_OUT	: out std_logic_vector(7 downto 0);
+		DATA_EN		: out bit;
+		
+		BUSCYCLE	: in BUSCYCLES;
+		CTRL_REG	: in bit_vector(5 downto 0);
+
+		OUT_A		: out bit;
+		OUT_B		: out bit;
+		OUT_C		: out bit
+	);
+end entity WF2149IP_WAVE;
+
+architecture BEHAVIOR of WF2149IP_WAVE is
+signal FREQUENCY_A	: std_logic_vector(11 downto 0);
+signal FREQUENCY_B	: std_logic_vector(11 downto 0);
+signal FREQUENCY_C	: std_logic_vector(11 downto 0);
+signal NOISE_FREQ	: std_logic_vector(4 downto 0);
+signal LEVEL_A		: std_logic_vector(4 downto 0);
+signal LEVEL_B		: std_logic_vector(4 downto 0);
+signal LEVEL_C		: std_logic_vector(4 downto 0);
+signal ENV_FREQ		: std_logic_vector(15 downto 0);
+signal ENV_SHAPE	: std_logic_vector(3 downto 0);
+signal ENV_RESET	: boolean;
+signal ENV_STRB		: bit;
+signal OSC_A_OUT	: bit;
+signal OSC_B_OUT	: bit;
+signal OSC_C_OUT	: bit;
+signal NOISE_OUT	: bit;
+signal AUDIO_A		: bit;
+signal AUDIO_B		: bit;
+signal AUDIO_C		: bit;
+signal VOL_ENV		: std_logic_vector(4 downto 0);
+signal AMPLITUDE_A	: std_logic_vector(4 downto 0);
+signal AMPLITUDE_B	: std_logic_vector(4 downto 0);
+signal AMPLITUDE_C	: std_logic_vector(4 downto 0);
+signal VOLUME_A		: std_logic_vector(7 downto 0);
+signal VOLUME_B		: std_logic_vector(7 downto 0);
+signal VOLUME_C		: std_logic_vector(7 downto 0);
+signal PWM_RAMP		: std_logic_vector(7 downto 0);
+begin
+	REGISTERS: process(RESETn, SYS_CLK)
+	-- This process is responsible for initialisation
+	-- and write access to the configuration registers.
+	begin
+		if RESETn = '0' then
+			FREQUENCY_A <= x"000";
+			FREQUENCY_B <= x"000";
+			FREQUENCY_C <= x"000";
+			NOISE_FREQ <= "00000";
+			LEVEL_A <= "00000";
+			LEVEL_B <= "00000";
+			LEVEL_C <= "00000";
+			ENV_FREQ <= (others => '0');
+			ENV_SHAPE <= "0000";
+		elsif SYS_CLK = '1' and SYS_CLK' event then
+			ENV_RESET <= false; -- Initialize signal.
+			if BUSCYCLE = R_WRITE then
+				case ADR is
+					when x"0" => FREQUENCY_A(7 downto 0) <= DATA_IN;
+					when x"1" => FREQUENCY_A(11 downto 8) <= DATA_IN(3 downto 0);
+					when x"2" => FREQUENCY_B(7 downto 0) <= DATA_IN;
+					when x"3" => FREQUENCY_B(11 downto 8) <= DATA_IN(3 downto 0);
+					when x"4" => FREQUENCY_C(7 downto 0) <= DATA_IN;
+					when x"5" => FREQUENCY_C(11 downto 8) <= DATA_IN(3 downto 0);
+					when x"6" => NOISE_FREQ <= DATA_IN(4 downto 0);
+					when x"8" => LEVEL_A <= DATA_IN(4 downto 0);
+					when x"9" => LEVEL_B <= DATA_IN(4 downto 0);
+					when x"A" => LEVEL_C <= DATA_IN(4 downto 0);
+					when x"B" => ENV_FREQ(7 downto 0) <= DATA_IN;
+					when x"C" => ENV_FREQ(15 downto 8) <= DATA_IN;	
+								 ENV_RESET <= true; -- Initialize the envelope generator.
+					when x"D" => ENV_SHAPE <= DATA_IN(3 downto 0);
+					when others => null;
+				end case;
+			end if;
+		end if;
+	end process REGISTERS;
+
+	-- Read back the configuration registers:
+	DATA_OUT <=	FREQUENCY_A(7 downto 0) when BUSCYCLE = R_READ and ADR = x"0" else
+				"0000" & FREQUENCY_A(11 downto 8) when BUSCYCLE = R_READ and ADR = x"1" else
+				FREQUENCY_B(7 downto 0) when BUSCYCLE = R_READ and ADR = x"2" else
+				"0000" & FREQUENCY_B(11 downto 8) when BUSCYCLE = R_READ and ADR = x"3" else
+				FREQUENCY_C(7 downto 0) when BUSCYCLE = R_READ and ADR = x"4" else
+				"0000" & FREQUENCY_C(11 downto 8) when BUSCYCLE = R_READ and ADR = x"5" else
+				"000" & NOISE_FREQ when BUSCYCLE = R_READ and ADR = x"6" else
+				"000" & LEVEL_A when BUSCYCLE = R_READ and ADR = x"8" else
+				"000" & LEVEL_B when BUSCYCLE = R_READ and ADR = x"9" else
+				"000" & LEVEL_C when BUSCYCLE = R_READ and ADR = x"A" else
+				ENV_FREQ(7 downto 0) when BUSCYCLE = R_READ and ADR = x"B" else
+				ENV_FREQ(15 downto 8) when BUSCYCLE = R_READ and ADR = x"C" else
+				x"0" & ENV_SHAPE when BUSCYCLE = R_READ and ADR = x"D" else (others => '0');
+	DATA_EN <=	'1' when BUSCYCLE = R_READ and ADR >= x"0" and ADR <= x"6" else
+				'1' when BUSCYCLE = R_READ and ADR >= x"8" and ADR <= x"D" else '0';
+
+	MUSICGENERATOR: process(RESETn, SYS_CLK)
+	variable CLK_DIV	: std_logic_vector(2 downto 0);
+	variable CNT_CH_A 	: std_logic_vector(11 downto 0);
+	variable CNT_CH_B 	: std_logic_vector(11 downto 0);
+	variable CNT_CH_C 	: std_logic_vector(11 downto 0);
+	begin
+		if RESETn = '0' then
+			CLK_DIV := "000";
+			CNT_CH_A := (others => '0');
+			CNT_CH_B := (others => '0');
+			CNT_CH_C := (others => '0');
+			OSC_A_OUT <= '0';
+			OSC_B_OUT <= '0';
+			OSC_C_OUT <= '0';
+		elsif SYS_CLK = '1' and SYS_CLK' event then
+			if WAV_STRB = '1' then
+				-- Divider by 8 for the oscillators brings in connection 
+				-- with the toggle flip flops CH_x_OUT the required divider
+				-- ratio of 16.
+				CLK_DIV := CLK_DIV + '1';
+
+				if CLK_DIV = "000" then
+					if FREQUENCY_A = x"000" then
+						CNT_CH_A := (others => '0');
+						OSC_A_OUT <= '0';
+					elsif CNT_CH_A = x"000" then
+						CNT_CH_A := FREQUENCY_A - '1' ;
+						OSC_A_OUT <= not OSC_A_OUT;
+					else
+						CNT_CH_A := CNT_CH_A - '1';
+					end if;
+
+					if FREQUENCY_B = x"000" then
+						CNT_CH_B := (others => '0');
+						OSC_B_OUT <= '0';
+					elsif CNT_CH_B = x"000" then
+						CNT_CH_B := FREQUENCY_B - '1' ;
+						OSC_B_OUT <= not OSC_B_OUT;
+					else
+						CNT_CH_B := CNT_CH_B - '1';
+					end if;
+
+					if FREQUENCY_C = x"000" then
+						CNT_CH_C := (others => '0');
+						OSC_C_OUT <= '0';
+					elsif CNT_CH_C = x"000" then
+						CNT_CH_C := FREQUENCY_C - '1' ;
+						OSC_C_OUT <= not OSC_C_OUT;
+					else
+						CNT_CH_C := CNT_CH_C - '1';
+					end if;
+				end if;
+			end if;
+		end if;
+	end process MUSICGENERATOR;
+
+	NOISEGENERATOR: process
+	-- The noise shift polynomial is taken from a template of Kazuhiro TSUJIKAWA's 
+	-- (ESE Artists' factory) approach for a 2149 equivalent. But the implementation
+	-- is done in another way.
+	-- LFSR (linear feedback shift register polynomial: f(x) = x^17 + x^14 + 1.
+	variable CLK_DIV	: std_logic_vector(3 downto 0);
+	variable CNT_NOISE 	: std_logic_vector(4 downto 0);
+	variable N_SHFT 	: std_logic_vector(16 downto 0);
+	begin
+		wait until SYS_CLK = '1' and SYS_CLK' event;
+		if RESETn = '0' then
+			CLK_DIV := x"0";
+			CNT_NOISE := (others => '1'); -- Preset the polynomial shift register.
+			NOISE_OUT <= '1';
+		elsif WAV_STRB = '1' then
+			-- Divider by 16 for the noise generator.
+			CLK_DIV := CLK_DIV + '1';
+			if CLK_DIV = x"0" then
+				-- Noise frequency counter.
+				if NOISE_FREQ = "00000" then
+					CNT_NOISE := (others => '0');
+				elsif CNT_NOISE = "00000" then
+					CNT_NOISE := NOISE_FREQ - '1' ;
+					N_SHFT := N_SHFT(15 downto 14) & not(N_SHFT(16) xor N_SHFT(13)) & 
+													N_SHFT(12 downto 0) & not N_SHFT(16);
+				else
+					CNT_NOISE := CNT_NOISE - '1';
+				end if;
+			end if;
+		end if;
+		NOISE_OUT <= To_Bit(N_SHFT(16));
+	end process NOISEGENERATOR;
+
+	ENVELOPE_PERIOD: process(RESETn, SYS_CLK)
+	-- The envelope period is controlled by the Envelope Frequency and the divider ratio which is
+	-- 256/32 = 8. For further information see the original data sheet.
+	variable ENV_CLK : std_logic_vector(18 downto 0);
+	variable LOCK : boolean;
+	begin
+		if RESETn = '0' then
+			ENV_STRB <= '0';
+			ENV_CLK := (others => '0');
+			LOCK := false;
+		elsif SYS_CLK = '1' and SYS_CLK' event then
+			if WAV_STRB = '1' and LOCK = false then
+				LOCK := true;
+				if ENV_FREQ = x"0000" then
+					ENV_STRB <= '0';
+				elsif ENV_CLK = x"0000" & "000" then
+					ENV_CLK := (ENV_FREQ & "111") - '1' ;
+					ENV_STRB <= '1';
+				else
+					ENV_CLK := ENV_CLK - '1';
+					ENV_STRB <= '0';
+				end if;
+			elsif WAV_STRB = '0' then
+				LOCK := false;
+				ENV_STRB <= '0';
+			else
+				ENV_STRB <= '0';
+			end if;
+		end if;
+	end process ENVELOPE_PERIOD;
+	
+	ENVELOPE: process(RESETn, SYS_CLK)
+	-- Envelope shapes:
+	-- case ENV_SHAPE:
+	--
+	-- 0 0 x x  \___
+	--
+	-- 0 1 x x  /|___
+	--
+	-- 1 0 0 0  _|\|\|\|\|
+	--
+	-- 1 0 0 1  \___
+	--
+	-- 1 0 1 0  \/\/
+	--            ___
+	-- 1 0 1 1  \|
+	--
+	-- 1 1 0 0  /|/|/|/|
+	--           ___
+	-- 1 1 0 1  /
+	--
+	-- 1 1 1 0  /\/\
+	--
+	-- 1 1 1 1  /|___
+	--
+	variable ENV_STOP	: boolean;
+	variable ENV_UP_DNn	: bit;
+	begin
+		if RESETn = '0' then
+			VOL_ENV <= (others => '0');
+			ENV_UP_DNn := '0';
+			ENV_STOP := false;
+		elsif SYS_CLK = '1' and SYS_CLK' event then
+			if ENV_RESET = true then
+				ENV_STOP := false;
+				case ENV_SHAPE is
+					when "1011" | "1010" | "1001" | "1000" | "0011" | "0010" | "0001" | "0000" =>
+						VOL_ENV <= "11111"; -- Start on top.
+						ENV_UP_DNn := '0';
+					when others =>
+						VOL_ENV <= "00000"; -- Start at bottom.
+						ENV_UP_DNn := '1';
+				end case;
+			elsif ENV_STRB = '1' then
+				case ENV_SHAPE is
+					when "1001" | "0011" | "0010" | "0001" | "0000"  =>
+						if VOL_ENV > "00000" then
+							VOL_ENV <= VOL_ENV - '1';
+						end if;
+					when "1111" | "0111" | "0110" | "0101" | "0100"  =>
+						if VOL_ENV < "11111" and ENV_STOP = false then
+							VOL_ENV <= VOL_ENV + '1';
+						else
+							VOL_ENV <= "00000";
+							ENV_STOP := true;
+						end if;
+					when "1000" =>
+						VOL_ENV <= VOL_ENV - '1';
+					when "1110" | "1010" =>
+						if ENV_UP_DNn = '0' then
+							VOL_ENV <= VOL_ENV - '1';
+						else
+							VOL_ENV <= VOL_ENV + '1';
+						end if;
+						--
+                        if VOL_ENV = "00001" then
+							ENV_UP_DNn := '1';
+                        elsif VOL_ENV = "11110" then
+							ENV_UP_DNn := '0';
+						end if;
+					when "1011" =>
+						if VOL_ENV > "00000" and ENV_STOP = false then
+							VOL_ENV <= VOL_ENV - '1';
+						else
+							VOL_ENV <= "11111";
+							ENV_STOP := true;
+						end if;
+					when "1100" =>
+						VOL_ENV <= VOL_ENV + '1';
+					when "1101" =>
+						if VOL_ENV < "11111" then
+							VOL_ENV <= VOL_ENV + '1';
+						end if;
+					when others => null; -- Covers U, X, Z, W, H, L, -.
+				end case;
+			end if;
+		end if;
+	end process ENVELOPE;
+
+	--MIXER:
+	-- The mixer controls are dependant on the mixer settings and the output of the
+	-- audio data for all three channels. The noise generator and the square wave
+	-- generators A, B and C are mixed together by a simple boolean OR.
+	AUDIO_A <= (OSC_A_OUT and not CTRL_REG(0)) or (NOISE_OUT and not CTRL_REG(3));
+	AUDIO_B <= (OSC_B_OUT and not CTRL_REG(1)) or (NOISE_OUT and not CTRL_REG(4));
+	AUDIO_C <= (OSC_C_OUT and not CTRL_REG(2)) or (NOISE_OUT and not CTRL_REG(5));
+
+	--LEVEL (e.g. volume control):
+	-- The linear amplitude for the DA converters of channel A, B or C are fixed
+	-- (LEVEL(3 downto 0)) or delivered by the envelope generator.
+	-- The following behavior is taken from the 2149 IP core of Mike J (www.fpgaarcade.com):
+	-- "make sure level 31 (env) = level 15 (tone)"
+	-- Thus there is a resulting & '1' modeling if LEVEL amplitudes are selected.
+	AMPLITUDE_A <= 	LEVEL_A(3 downto 0) & '1' 	when LEVEL_A(4) = '0' and AUDIO_A = '1' else
+					VOL_ENV 					when LEVEL_A(4) = '1' and AUDIO_A = '1' else "00000";
+	AMPLITUDE_B <= 	LEVEL_B(3 downto 0) & '1' 	when LEVEL_B(4) = '0' and AUDIO_B = '1' else
+					VOL_ENV 					when LEVEL_B(4) = '1' and AUDIO_B = '1' else "00000";
+	AMPLITUDE_C <= 	LEVEL_C(3 downto 0) & '1' 	when LEVEL_C(4) = '0' and AUDIO_C = '1' else
+					VOL_ENV 					when LEVEL_C(4) = '1' and AUDIO_C = '1' else "00000";
+
+	-- The values for the logarithmic DA converter volume controls are taken from the linear 
+	-- mixer of Mike J's 2149 IP core (www.fpgaarcade.com).
+	with AMPLITUDE_A select
+						VOLUME_A <= x"FF" when "11111",
+									x"D9" when "11110",
+									x"BA" when "11101",
+									x"9F" when "11100",
+									x"88" when "11011",
+									x"74" when "11010",
+									x"63" when "11001",
+									x"54" when "11000",
+									x"48" when "10111",
+									x"3D" when "10110",
+									x"34" when "10101",
+									x"2C" when "10100",
+									x"25" when "10011",
+									x"1F" when "10010",
+									x"1A" when "10001",
+									x"16" when "10000",
+									x"13" when "01111",
+									x"10" when "01110",
+									x"0D" when "01101",
+									x"0B" when "01100",
+									x"09" when "01011",
+									x"08" when "01010",
+									x"07" when "01001",
+									x"06" when "01000",
+									x"05" when "00111",
+									x"04" when "00110",
+									x"03" when "00101",
+									x"03" when "00100",
+									x"02" when "00011",
+									x"02" when "00010",
+									x"01" when "00001",
+									x"00" when others; -- Also covers U, X, Z, W, H, L, -.
+
+	with AMPLITUDE_B select 
+						VOLUME_B <= x"FF" when "11111",
+									x"D9" when "11110",
+									x"BA" when "11101",
+									x"9F" when "11100",
+									x"88" when "11011",
+									x"74" when "11010",
+									x"63" when "11001",
+									x"54" when "11000",
+									x"48" when "10111",
+									x"3D" when "10110",
+									x"34" when "10101",
+									x"2C" when "10100",
+									x"25" when "10011",
+									x"1F" when "10010",
+									x"1A" when "10001",
+									x"16" when "10000",
+									x"13" when "01111",
+									x"10" when "01110",
+									x"0D" when "01101",
+									x"0B" when "01100",
+									x"09" when "01011",
+									x"08" when "01010",
+									x"07" when "01001",
+									x"06" when "01000",
+									x"05" when "00111",
+									x"04" when "00110",
+									x"03" when "00101",
+									x"03" when "00100",
+									x"02" when "00011",
+									x"02" when "00010",
+									x"01" when "00001",
+									x"00" when others; -- Also covers U, X, Z, W, H, L, -.
+
+	with AMPLITUDE_C select
+						VOLUME_C <= x"FF" when "11111",
+									x"D9" when "11110",
+									x"BA" when "11101",
+									x"9F" when "11100",
+									x"88" when "11011",
+									x"74" when "11010",
+									x"63" when "11001",
+									x"54" when "11000",
+									x"48" when "10111",
+									x"3D" when "10110",
+									x"34" when "10101",
+									x"2C" when "10100",
+									x"25" when "10011",
+									x"1F" when "10010",
+									x"1A" when "10001",
+									x"16" when "10000",
+									x"13" when "01111",
+									x"10" when "01110",
+									x"0D" when "01101",
+									x"0B" when "01100",
+									x"09" when "01011",
+									x"08" when "01010",
+									x"07" when "01001",
+									x"06" when "01000",
+									x"05" when "00111",
+									x"04" when "00110",
+									x"03" when "00101",
+									x"03" when "00100",
+									x"02" when "00011",
+									x"02" when "00010",
+									x"01" when "00001",
+									x"00" when others; -- Also covers U, X, Z, W, H, L, -.
+
+	DA_CONVERSION: process
+	-- The DA conversion for the three analog outputs is originally performed by a built in DA converter.
+	-- For this is not possible in current FPGA designs, the converter is replaced by three PWM units
+	-- operating at a frequency which is 100 times higher than the highest noise or music frequency which
+	-- is 2MHz/16 = 125kHz. So the PWM frequency requires about 12.5MHz or more. The design is done for
+	-- a PWM frequency of 16MHz).
+	begin
+		wait until SYS_CLK = '1' and SYS_CLK' event;
+		PWM_RAMP <= PWM_RAMP + '1';
+	end process DA_CONVERSION;
+	OUT_A <= '0' when VOLUME_A = x"00" else '1' when PWM_RAMP < VOLUME_A else '0';
+	OUT_B <= '0' when VOLUME_B = x"00" else '1' when PWM_RAMP < VOLUME_B else '0';
+	OUT_C <= '0' when VOLUME_C = x"00" else '1' when PWM_RAMP < VOLUME_C else '0';
+	--
+	-- To obtain proper analog output it is necessary to install analog RC filters to the pulse width
+	-- outputs. An example is given for the direct wiring of the three analog outputs and for a system
+	-- clock frequency of 16MHz. The output circuitry looks in this case as follows:
+	--
+	-- OUT_A ---------|1kOhm|-----------|                      |\ e.g. LM741
+	--                                  |----------------------|+\       ||
+	-- OUT_B ---------|1kOhm|-----------|                      | OP------||--- Analog Signal
+	--                                  |                |-----|-/	|    ||
+	-- OUT_C ---------|1kOhm|-----------|                |     |/   |   4u7
+	--                                  |                |__________|
+	--                                  |
+	--                                 --- 10nF.
+	--                                 ---
+	--                                  |
+	--                                  |
+	--                                 ---
+	--  WF.
+end architecture BEHAVIOR;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
new file mode 100644
index 0000000..e60cc43
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
@@ -0,0 +1,244 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- 6850 compatible IP Core    					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- UART 6850 compatible IP core                                 ----
+----                                                              ----
+---- Control unit and status logic.                               ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K9A  2009/06/20 WF
+--   CTRL_REG has now synchronous reset to meet preset requirements.
+--   Process P_DCD has now synchronous reset to meet preset requirements.
+--   IRQ_In has now synchronous reset to meet preset requirement.
+-- Revision 2K9B  2009/12/24 WF
+--   Fixed the interrupt logic.
+--   Introduced a minor RTSn correction.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF6850IP_CTRL_STATUS is
+  port (
+		CLK			: in bit;
+        RESETn		: in bit;
+
+        CS			: in bit_vector(2 downto 0); -- Active if "011".
+        E			: in bit;   
+        RWn     	: in bit;
+        RS			: in bit;
+
+        DATA_IN		: in bit_vector(7 downto 0);   
+        DATA_OUT	: out bit_vector(7 downto 0);   
+		DATA_EN		: out bit;
+		
+		-- Status register stuff:
+		RDRF		: in bit;	-- Receive data register full.
+		TDRE		: in bit;	-- Transmit data register empty.
+		DCDn		: in bit;	-- Data carrier detect.
+		CTSn		: in bit;	-- Clear to send.
+		FE			: in bit;	-- Framing error.
+		OVR			: in bit;	-- Overrun error.
+		PE			: in bit;	-- Parity error.
+
+		-- Control register stuff:
+		MCLR		: buffer bit; -- Master clear (high active).
+		RTSn		: out bit; -- Request to send.
+		CDS			: out bit_vector(1 downto 0); -- Clock control.
+		WS			: out bit_vector(2 downto 0); -- Word select.
+		TC			: out bit_vector(1 downto 0); -- Transmit control.
+		IRQn		: out bit -- Interrupt request.
+       );                                              
+end entity WF6850IP_CTRL_STATUS;
+
+architecture BEHAVIOR of WF6850IP_CTRL_STATUS is
+signal CTRL_REG		: bit_vector(7 downto 0);
+signal STATUS_REG	: bit_vector(7 downto 0);
+signal RIE			: bit;
+signal IRQ_I		: bit;
+signal CTS_In		: bit;
+signal DCD_In		: bit;
+signal DCD_FLAGn	: bit;
+begin
+	P_SAMPLE: process
+	begin
+		wait until CLK = '0' and CLK' event;
+		CTS_In <= CTSn; -- Sample CTSn on the negative clock edge.
+		DCD_In <= DCDn; -- Sample DCDn on the negative clock edge.
+	end process P_SAMPLE;
+
+	STATUS_REG(7) <= IRQ_I;
+	STATUS_REG(6) <= PE;
+	STATUS_REG(5) <= OVR;
+	STATUS_REG(4) <= FE;
+	STATUS_REG(3) <= CTS_In; -- Reflexion of the input pin.
+	STATUS_REG(2) <= DCD_FLAGn;
+	STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'.
+	STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty.
+
+	DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' and E = '1' else (others => '0');
+	DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' and E = '1' else '0';
+	
+	MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0';
+	RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1';
+
+	CDS <= CTRL_REG(1 downto 0);
+	WS <= CTRL_REG(4 downto 2);
+	TC <= CTRL_REG(6 downto 5);
+	RIE <= CTRL_REG(7);
+	
+	P_IRQ: process
+	variable DCD_OVR_LOCK	: boolean;
+	variable DCD_LOCK	    : boolean;
+	variable DCD_TRANS	    : boolean;	
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' then
+			DCD_OVR_LOCK := false;
+			IRQn <= '1';
+			IRQ_I <= '0';
+		elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
+			DCD_OVR_LOCK := false; -- Enable reset by reading the status.
+		end if;
+
+        -- Clear interrupts when disabled.
+        if CTRL_REG(7) = '0' then
+            IRQn <= '1';
+            IRQ_I <= '0';
+        elsif CTRL_REG(6 downto 5) /= "01" then
+            IRQn <= '1';
+            IRQ_I <= '0';
+        end if;
+
+		-- Transmitter interrupt:
+        if TDRE = '1' and CTRL_REG(6 downto 5) = "01" and CTS_In = '0' then
+			IRQn <= '0';
+			IRQ_I <= '1';
+		elsif  CS = "011" and RWn = '0' and RS = '1' and E = '1' then
+			IRQn <= '1'; -- Clear by writing to the transmit data register.
+		end if;
+					
+		-- Receiver interrupts:
+		if RDRF = '1' and RIE = '1' and DCD_In = '0' then
+			IRQn <= '0';
+			IRQ_I <= '1';
+		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
+			IRQn <= '1'; -- Clear by reading the receive data register.
+		end if;
+
+		if OVR = '1' and RIE = '1' then
+			IRQn <= '0';
+			IRQ_I <= '1';
+			DCD_OVR_LOCK := true;
+		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1'  and DCD_OVR_LOCK = false then
+			IRQn <= '1'; -- Clear by reading the receive data register after the status.
+		end if;
+					
+		if DCD_In = '1' and RIE = '1' and DCD_TRANS = false then
+			IRQn <= '0';
+			IRQ_I <= '1';
+			-- DCD_TRANS is used to detect a low to high transition of DCDn.
+			DCD_TRANS := true;
+			DCD_OVR_LOCK := true;
+		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1'  and DCD_OVR_LOCK = false then
+			IRQn <= '1'; -- Clear by reading the receive data register after the status.
+		elsif DCD_In = '0' then
+			DCD_TRANS := false;
+		end if;
+
+		-- The reset of the IRQ status flag:
+		-- Clear by writing to the transmit data register.
+		-- Clear by reading the receive data register.
+		if  CS = "011" and RS = '1' and E = '1' then
+			IRQ_I <= '0'; 
+		end if;
+	end process P_IRQ;
+	
+	CONTROL: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' then
+			CTRL_REG <= "01000000";
+		elsif CS = "011" and RWn = '0' and RS = '0' and E = '1' then
+			CTRL_REG <= DATA_IN;
+		end if;
+	end process CONTROL;	
+
+	P_DCD: process
+	-- This process is some kind of tricky. Refer to the MC6850 data
+	-- sheet for more information.
+	variable READ_LOCK		: boolean;
+	variable DCD_RELEASE	: boolean;
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' then
+			DCD_FLAGn <= '0'; -- This interrupt source must initialise low.
+			READ_LOCK := true;
+			DCD_RELEASE := false;
+		elsif MCLR = '1' then
+			DCD_FLAGn <= DCD_In;
+			READ_LOCK := true;
+		elsif DCD_In = '1' then
+			DCD_FLAGn <= '1';
+		elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
+			READ_LOCK := false;	-- Un-READ_LOCK if receiver data register is read. 
+		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and READ_LOCK = false then
+			-- Clear if receiver status register read access.
+			-- After data register has ben read and READ_LOCK again.
+			DCD_RELEASE := true;
+			READ_LOCK := true;
+			DCD_FLAGn <= DCD_In;
+		elsif DCD_In = '0' and DCD_RELEASE = true then
+			DCD_FLAGn <= '0';
+			DCD_RELEASE := false;
+		end if;
+	end process P_DCD;	
+end architecture BEHAVIOR;
+
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak
new file mode 100644
index 0000000..a0ea9e4
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak
@@ -0,0 +1,244 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- 6850 compatible IP Core    					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- UART 6850 compatible IP core                                 ----
+----                                                              ----
+---- Control unit and status logic.                               ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K9A  2009/06/20 WF
+--   CTRL_REG has now synchronous reset to meet preset requirements.
+--   Process P_DCD has now synchronous reset to meet preset requirements.
+--   IRQ_In has now synchronous reset to meet preset requirement.
+-- Revision 2K9B  2009/12/24 WF
+--   Fixed the interrupt logic.
+--   Introduced a minor RTSn correction.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF6850IP_CTRL_STATUS is
+  port (
+		CLK			: in bit;
+        RESETn		: in bit;
+
+        CS			: in bit_vector(2 downto 0); -- Active if "011".
+        E			: in bit;   
+        RWn     	: in bit;
+        RS			: in bit;
+
+        DATA_IN		: in bit_vector(7 downto 0);   
+        DATA_OUT	: out bit_vector(7 downto 0);   
+		DATA_EN		: out bit;
+		
+		-- Status register stuff:
+		RDRF		: in bit;	-- Receive data register full.
+		TDRE		: in bit;	-- Transmit data register empty.
+		DCDn		: in bit;	-- Data carrier detect.
+		CTSn		: in bit;	-- Clear to send.
+		FE			: in bit;	-- Framing error.
+		OVR			: in bit;	-- Overrun error.
+		PE			: in bit;	-- Parity error.
+
+		-- Control register stuff:
+		MCLR		: buffer bit; -- Master clear (high active).
+		RTSn		: out bit; -- Request to send.
+		CDS			: out bit_vector(1 downto 0); -- Clock control.
+		WS			: out bit_vector(2 downto 0); -- Word select.
+		TC			: out bit_vector(1 downto 0); -- Transmit control.
+		IRQn		: out bit -- Interrupt request.
+       );                                              
+end entity WF6850IP_CTRL_STATUS;
+
+architecture BEHAVIOR of WF6850IP_CTRL_STATUS is
+signal CTRL_REG		: bit_vector(7 downto 0);
+signal STATUS_REG	: bit_vector(7 downto 0);
+signal RIE			: bit;
+signal IRQ_I		: bit;
+signal CTS_In		: bit;
+signal DCD_In		: bit;
+signal DCD_FLAGn	: bit;
+begin
+	P_SAMPLE: process
+	begin
+		wait until CLK = '0' and CLK' event;
+		CTS_In <= CTSn; -- Sample CTSn on the negative clock edge.
+		DCD_In <= DCDn; -- Sample DCDn on the negative clock edge.
+	end process P_SAMPLE;
+
+	STATUS_REG(7) <= IRQ_I;
+	STATUS_REG(6) <= PE;
+	STATUS_REG(5) <= OVR;
+	STATUS_REG(4) <= FE;
+	STATUS_REG(3) <= CTS_In; -- Reflexion of the input pin.
+	STATUS_REG(2) <= DCD_FLAGn;
+	STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'.
+	STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty.
+
+	DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' and E = '1' else (others => '0');
+	DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' and E = '1' else '0';
+	
+	MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0';
+	RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1';
+
+	CDS <= CTRL_REG(1 downto 0);
+	WS <= CTRL_REG(4 downto 2);
+	TC <= CTRL_REG(6 downto 5);
+	RIE <= CTRL_REG(7);
+	
+	P_IRQ: process
+	variable DCD_OVR_LOCK	: boolean;
+	variable DCD_LOCK	    : boolean;
+	variable DCD_TRANS	    : boolean;	
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' then
+			DCD_OVR_LOCK := false;
+			IRQn <= '1';
+			IRQ_I <= '0';
+		elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
+			DCD_OVR_LOCK := false; -- Enable reset by reading the status.
+		end if;
+
+-- Clear interrupts when disabled.
+if CTRL_REG(7) = '0' then
+    IRQn <= '1';
+    IRQ_I <= '0';
+elsif CTRL_REG(6 downto 5) /= "01" then
+    IRQn <= '1';
+    IRQ_I <= '0';
+end if;
+
+		-- Transmitter interrupt:
+        if TDRE = '1' and CTRL_REG(6 downto 5) = "01" and CTS_In = '0' then
+			IRQn <= '0';
+			IRQ_I <= '1';
+		elsif  CS = "011" and RWn = '0' and RS = '1' and E = '1' then
+			IRQn <= '1'; -- Clear by writing to the transmit data register.
+		end if;
+					
+		-- Receiver interrupts:
+		if RDRF = '1' and RIE = '1' and DCD_In = '0' then
+			IRQn <= '0';
+			IRQ_I <= '1';
+		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
+			IRQn <= '1'; -- Clear by reading the receive data register.
+		end if;
+
+		if OVR = '1' and RIE = '1' then
+			IRQn <= '0';
+			IRQ_I <= '1';
+			DCD_OVR_LOCK := true;
+		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1'  and DCD_OVR_LOCK = false then
+			IRQn <= '1'; -- Clear by reading the receive data register after the status.
+		end if;
+					
+		if DCD_In = '1' and RIE = '1' and DCD_TRANS = false then
+			IRQn <= '0';
+			IRQ_I <= '1';
+			-- DCD_TRANS is used to detect a low to high transition of DCDn.
+			DCD_TRANS := true;
+			DCD_OVR_LOCK := true;
+		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1'  and DCD_OVR_LOCK = false then
+			IRQn <= '1'; -- Clear by reading the receive data register after the status.
+		elsif DCD_In = '0' then
+			DCD_TRANS := false;
+		end if;
+
+		-- The reset of the IRQ status flag:
+		-- Clear by writing to the transmit data register.
+		-- Clear by reading the receive data register.
+		if  CS = "011" and RS = '1' and E = '1' then
+			IRQ_I <= '0'; 
+		end if;
+	end process P_IRQ;
+	
+	CONTROL: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' then
+			CTRL_REG <= "01000000";
+		elsif CS = "011" and RWn = '0' and RS = '0' and E = '1' then
+			CTRL_REG <= DATA_IN;
+		end if;
+	end process CONTROL;	
+
+	P_DCD: process
+	-- This process is some kind of tricky. Refer to the MC6850 data
+	-- sheet for more information.
+	variable READ_LOCK		: boolean;
+	variable DCD_RELEASE	: boolean;
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RESETn = '0' then
+			DCD_FLAGn <= '0'; -- This interrupt source must initialise low.
+			READ_LOCK := true;
+			DCD_RELEASE := false;
+		elsif MCLR = '1' then
+			DCD_FLAGn <= DCD_In;
+			READ_LOCK := true;
+		elsif DCD_In = '1' then
+			DCD_FLAGn <= '1';
+		elsif CS = "011" and RWn = '1' and RS = '0' and E = '1' then
+			READ_LOCK := false;	-- Un-READ_LOCK if receiver data register is read. 
+		elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' and READ_LOCK = false then
+			-- Clear if receiver status register read access.
+			-- After data register has ben read and READ_LOCK again.
+			DCD_RELEASE := true;
+			READ_LOCK := true;
+			DCD_FLAGn <= DCD_In;
+		elsif DCD_In = '0' and DCD_RELEASE = true then
+			DCD_FLAGn <= '0';
+			DCD_RELEASE := false;
+		end if;
+	end process P_DCD;	
+end architecture BEHAVIOR;
+
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
new file mode 100644
index 0000000..755e018
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
@@ -0,0 +1,415 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- 6850 compatible IP Core    					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- UART 6850 compatible IP core                                 ----
+----                                                              ----
+---- 6850's receiver unit.                                        ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF6850IP_RECEIVE is
+  port (
+		CLK					: in bit;
+        RESETn				: in bit;
+		MCLR				: in bit;
+
+        CS					: in bit_vector(2 downto 0);
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+
+        DATA_OUT	        : out bit_vector(7 downto 0);   
+		DATA_EN				: out bit;
+		
+		WS					: in bit_vector(2 downto 0);
+		CDS					: in bit_vector(1 downto 0);
+
+        RXCLK				: in bit;
+        RXDATA				: in bit;
+
+		RDRF				: buffer bit;
+		OVR					: out bit;
+		PE					: out bit;
+		FE					: out bit
+       );                                              
+end entity WF6850IP_RECEIVE;
+
+architecture BEHAVIOR of WF6850IP_RECEIVE is
+type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC);
+signal RCV_STATE, RCV_NEXT_STATE	: RCV_STATES;
+signal RXDATA_I		: bit;
+signal RXDATA_S		: bit;
+signal DATA_REG		: bit_vector(7 downto 0);
+signal SHIFT_REG	: bit_vector(7 downto 0);
+signal CLK_STRB		: bit;
+signal BITCNT		: std_logic_vector(2 downto 0);
+begin
+	P_SAMPLE: process
+	-- This filter provides a synchronisation to the system
+	-- clock, even for random baud rates of the received data
+	-- stream.
+	variable FLT_TMP	: integer range 0 to 2;
+	begin
+		wait until CLK = '1' and CLK' event;
+		--
+		RXDATA_I <= RXDATA;
+		--
+		if RXDATA_I = '1' and FLT_TMP < 2 then
+			FLT_TMP := FLT_TMP + 1;
+		elsif RXDATA_I = '1' then
+			RXDATA_S <= '1';
+		elsif RXDATA_I = '0' and FLT_TMP > 0 then
+			FLT_TMP := FLT_TMP - 1;
+		elsif RXDATA_I = '0' then
+			RXDATA_S <= '0';
+		end if;
+	end process P_SAMPLE;
+
+	CLKDIV: process
+	variable CLK_LOCK	: boolean;
+	variable STRB_LOCK	: boolean;
+	variable CLK_DIVCNT	: std_logic_vector(6 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		if CDS = "00" then -- Divider off.
+			if RXCLK = '1' and STRB_LOCK = false then
+				CLK_STRB <= '1';
+				STRB_LOCK := true;
+			elsif RXCLK = '0' then
+				CLK_STRB <= '0';
+				STRB_LOCK := false;
+			else
+				CLK_STRB <= '0';
+			end if;
+		elsif RCV_STATE = IDLE then
+			-- Preset the CLKDIV with the start delays.
+			if CDS = "01" then
+				CLK_DIVCNT := "0001000"; -- Half of div by 16 mode.
+			elsif CDS = "10" then
+				CLK_DIVCNT := "0100000"; -- Half of div by 64 mode.
+			end if;
+	 		CLK_STRB <= '0';
+		else
+			if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then
+				CLK_DIVCNT := CLK_DIVCNT - '1';
+				CLK_STRB <= '0';
+				CLK_LOCK := true;
+			elsif CDS = "01" and CLK_DIVCNT = "0000000" then
+				CLK_DIVCNT := "0010000"; -- Div by 16 mode.
+				--
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				else
+					CLK_STRB <= '0';
+				end if;
+			elsif CDS = "10" and CLK_DIVCNT = "0000000" then
+				CLK_DIVCNT := "1000000"; -- Div by 64 mode.
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				else
+					CLK_STRB <= '0';
+				end if;
+			elsif RXCLK = '0' then
+				CLK_LOCK := false;
+				STRB_LOCK := false;
+				CLK_STRB <= '0';
+			else
+				CLK_STRB <= '0';
+			end if;
+		end if;
+	end process CLKDIV;
+	
+	DATAREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DATA_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				DATA_REG <= x"00";
+			elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data.
+				-- Transfer from shift- to data register only if
+				-- data register is empty (RDRF = '0').
+				DATA_REG <= '0' & SHIFT_REG(7 downto 1);
+			elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data.
+				-- Transfer from shift- to data register only if
+				-- data register is empty (RDRF = '0').
+				DATA_REG <= SHIFT_REG;
+			end if;
+		end if;
+	end process DATAREG;	
+    DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0');
+    DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0';
+	
+	SHIFTREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SHIFT_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				SHIFT_REG <= x"00";
+			elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then
+				SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right.
+			end if;
+		end if;
+	end process SHIFTREG;	
+
+	P_BITCNT: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RCV_STATE = SAMPLE and CLK_STRB = '1' then
+			BITCNT <= BITCNT + '1';
+		elsif RCV_STATE /= SAMPLE then
+			BITCNT <= (others => '0');
+		end if;
+	end process P_BITCNT;
+
+	FRAME_ERR: process(RESETn, CLK)
+	-- This module detects a framing error
+	-- during stop bit 1 and stop bit 2.
+	variable FE_I: bit;
+	begin
+		if RESETn = '0' then
+			FE_I := '0';
+			FE <= '0';
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				FE_I := '0';
+				FE <= '0';
+			elsif CLK_STRB = '1' then
+				if RCV_STATE = STOP1 and RXDATA_S = '0' then
+					FE_I := '1';
+				elsif RCV_STATE = STOP2 and RXDATA_S = '0' then
+					FE_I := '1';
+				elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
+					FE_I := '0'; -- Error resets when correct data appears.
+				end if;
+			end if;
+			if RCV_STATE = SYNC then
+				FE <= FE_I; -- Update the FE every SYNC time.
+			end if;
+		end if;
+	end process FRAME_ERR;
+
+	OVERRUN: process(RESETn, CLK)
+	variable OVR_I		: bit;
+	variable FIRST_READ	: boolean;
+	begin
+		if RESETn = '0' then
+			OVR_I := '0';
+			OVR <= '0';
+			FIRST_READ := false;
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				OVR_I := '0';
+				OVR <= '0';
+				FIRST_READ := false;
+			elsif CLK_STRB = '1' and RCV_STATE = STOP1 then
+				-- Overrun appears if RDRF is '1' in this state.
+				OVR_I := RDRF;
+			end if;
+			if CS = "011" and RWn = '1' and RS = '1' and E = '1' and OVR_I = '1' then
+				-- If an overrun was detected, the concerning flag is
+				-- set when the valid data word in the receiver data
+				-- register is read. Thereafter the RDRF flag is reset
+				-- and the overrun disappears (OVR_I goes low) after 
+				-- a second read (in time) of the receiver data register.
+				if FIRST_READ = false then
+					OVR <= '1';
+					FIRST_READ := true;
+				else
+					OVR <= '0';
+					FIRST_READ := false;
+				end if;
+			end if;
+		end if;
+	end process OVERRUN;
+	
+	PARITY_TEST: process(RESETn, CLK)
+	variable PAR_TMP	: bit;
+	variable PE_I		: bit;
+	begin
+		if RESETn = '0' then
+			PE <= '0';
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				PE <= '0';
+			elsif CLK_STRB = '1' then -- Sample parity on clock strobe.
+				PE_I := '0'; -- Initialise.
+				if RCV_STATE = PARITY then
+				    for i in 1 to 7 loop
+				        if i = 1 then
+				            PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
+				        else
+				            PAR_TMP := PAR_TMP xor SHIFT_REG(i);
+				        end if;
+				    end loop;
+					if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
+				    	PE_I := PAR_TMP xor RXDATA_S;
+					elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
+						PE_I := not PAR_TMP xor RXDATA_S;
+					else -- No parity for WS = "100" and WS = "101".
+						PE_I := '0';		
+					end if;
+				end if;
+			end if;
+			-- Transmit the parity flag together with the data
+			-- In other words: no parity to the status register
+			-- when RDRF inhibits the data transfer to the
+			-- receiver data register.
+			if RCV_STATE = SYNC and RDRF = '0' then
+				PE <= PE_I;
+			elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
+				PE <= '0'; -- Clear when reading the data register.
+			end if;
+		end if;
+	end process PARITY_TEST;
+
+	P_RDRF: process(RESETn, CLK)
+	-- Receive data register full flag.
+	begin
+		if RESETn = '0' then
+			RDRF <= '0';
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				RDRF <= '0';
+			elsif RCV_STATE = SYNC then
+				RDRF <= '1'; -- Data register is full until now!
+			elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
+				RDRF <= '0'; -- After reading the data register ...
+			end if;
+		end if;
+	end process P_RDRF;
+	
+	RCV_STATEREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			RCV_STATE <= IDLE;
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				RCV_STATE <= IDLE;
+			else
+				RCV_STATE <= RCV_NEXT_STATE;
+			end if;
+		end if;
+	end process RCV_STATEREG;
+	
+	RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB)
+	begin
+		case RCV_STATE is
+			when IDLE =>
+				if RXDATA_S = '0' and CDS = "00" then
+					RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode.
+				elsif RXDATA_S = '0' and CDS = "01" then
+					RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode.
+				elsif RXDATA_S = '0' and CDS = "10" then
+					RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode.
+				else
+					RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-)
+				end if;
+			when WAIT_START =>
+				if CLK_STRB = '1' then
+					if RXDATA_S = '0' then
+						RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes.
+					else
+						RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back.
+					end if;
+				else
+					RCV_NEXT_STATE <= WAIT_START; -- Stay.
+				end if;
+			when SAMPLE =>
+				if CLK_STRB = '1' then
+					if BITCNT < "110" and WS(2) = '0' then
+						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits.
+					elsif BITCNT < "111" and WS(2) = '1' then
+						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits.
+					elsif WS = "100" or WS = "101" then
+						RCV_NEXT_STATE <= STOP1; -- No parity check enabled.
+					else
+						RCV_NEXT_STATE <= PARITY; -- Parity enabled.
+					end if;
+				else
+					RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode.
+				end if;
+			when PARITY =>
+				if CLK_STRB = '1' then
+					RCV_NEXT_STATE <= STOP1;
+				else
+					RCV_NEXT_STATE <= PARITY;
+				end if;				
+			when STOP1 =>
+				if CLK_STRB = '1' then
+					if RXDATA_S = '0' then
+						RCV_NEXT_STATE <= SYNC; -- Framing error detected.
+					elsif WS = "000" or WS = "001" or WS = "100" then
+						RCV_NEXT_STATE <= STOP2; -- Two stop bits selected.
+					else
+						RCV_NEXT_STATE <= SYNC; -- One stop bit selected.
+					end if;
+				else
+					RCV_NEXT_STATE <= STOP1;
+				end if;				
+			when STOP2 =>
+				if CLK_STRB = '1' then
+					RCV_NEXT_STATE <= SYNC;
+				else
+					RCV_NEXT_STATE <= STOP2;
+				end if;				
+			when SYNC =>
+				RCV_NEXT_STATE <= IDLE;
+		end case;
+	end process RCV_STATEDEC;
+end architecture BEHAVIOR;
+
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak
new file mode 100644
index 0000000..e8c82b2
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak
@@ -0,0 +1,415 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- 6850 compatible IP Core    					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- UART 6850 compatible IP core                                 ----
+----                                                              ----
+---- 6850's receiver unit.                                        ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B	2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF6850IP_RECEIVE is
+  port (
+		CLK					: in bit;
+        RESETn				: in bit;
+		MCLR				: in bit;
+
+        CS					: in bit_vector(2 downto 0);
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+
+        DATA_OUT	        : out bit_vector(7 downto 0);   
+		DATA_EN				: out bit;
+		
+		WS					: in bit_vector(2 downto 0);
+		CDS					: in bit_vector(1 downto 0);
+
+        RXCLK				: in bit;
+        RXDATA				: in bit;
+
+		RDRF				: buffer bit;
+		OVR					: out bit;
+		PE					: out bit;
+		FE					: out bit
+       );                                              
+end entity WF6850IP_RECEIVE;
+
+architecture BEHAVIOR of WF6850IP_RECEIVE is
+type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC);
+signal RCV_STATE, RCV_NEXT_STATE	: RCV_STATES;
+signal RXDATA_I		: bit;
+signal RXDATA_S		: bit;
+signal DATA_REG		: bit_vector(7 downto 0);
+signal SHIFT_REG	: bit_vector(7 downto 0);
+signal CLK_STRB		: bit;
+signal BITCNT		: std_logic_vector(2 downto 0);
+begin
+	P_SAMPLE: process
+	-- This filter provides a synchronisation to the system
+	-- clock, even for random baud rates of the received data
+	-- stream.
+	variable FLT_TMP	: integer range 0 to 2;
+	begin
+		wait until CLK = '1' and CLK' event;
+		--
+		RXDATA_I <= RXDATA;
+		--
+		if RXDATA_I = '1' and FLT_TMP < 2 then
+			FLT_TMP := FLT_TMP + 1;
+		elsif RXDATA_I = '1' then
+			RXDATA_S <= '1';
+		elsif RXDATA_I = '0' and FLT_TMP > 0 then
+			FLT_TMP := FLT_TMP - 1;
+		elsif RXDATA_I = '0' then
+			RXDATA_S <= '0';
+		end if;
+	end process P_SAMPLE;
+
+	CLKDIV: process
+	variable CLK_LOCK	: boolean;
+	variable STRB_LOCK	: boolean;
+	variable CLK_DIVCNT	: std_logic_vector(6 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		if CDS = "00" then -- Divider off.
+			if RXCLK = '1' and STRB_LOCK = false then
+				CLK_STRB <= '1';
+				STRB_LOCK := true;
+			elsif RXCLK = '0' then
+				CLK_STRB <= '0';
+				STRB_LOCK := false;
+			else
+				CLK_STRB <= '0';
+			end if;
+		elsif RCV_STATE = IDLE then
+			-- Preset the CLKDIV with the start delays.
+			if CDS = "01" then
+				CLK_DIVCNT := "0001000"; -- Half of div by 16 mode.
+			elsif CDS = "10" then
+				CLK_DIVCNT := "0100000"; -- Half of div by 64 mode.
+			end if;
+	 		CLK_STRB <= '0';
+		else
+			if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then
+				CLK_DIVCNT := CLK_DIVCNT - '1';
+				CLK_STRB <= '0';
+				CLK_LOCK := true;
+			elsif CDS = "01" and CLK_DIVCNT = "0000000" then
+				CLK_DIVCNT := "0010000"; -- Div by 16 mode.
+				--
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				else
+					CLK_STRB <= '0';
+				end if;
+			elsif CDS = "10" and CLK_DIVCNT = "0000000" then
+				CLK_DIVCNT := "1000000"; -- Div by 64 mode.
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				else
+					CLK_STRB <= '0';
+				end if;
+			elsif RXCLK = '0' then
+				CLK_LOCK := false;
+				STRB_LOCK := false;
+				CLK_STRB <= '0';
+			else
+				CLK_STRB <= '0';
+			end if;
+		end if;
+	end process CLKDIV;
+	
+	DATAREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DATA_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				DATA_REG <= x"00";
+			elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data.
+				-- Transfer from shift- to data register only if
+				-- data register is empty (RDRF = '0').
+				DATA_REG <= '0' & SHIFT_REG(7 downto 1);
+			elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data.
+				-- Transfer from shift- to data register only if
+				-- data register is empty (RDRF = '0').
+				DATA_REG <= SHIFT_REG;
+			end if;
+		end if;
+	end process DATAREG;	
+--DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0');
+--DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0';
+DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' else (others => '0');
+DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0';
+	
+	SHIFTREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SHIFT_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				SHIFT_REG <= x"00";
+			elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then
+				SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right.
+			end if;
+		end if;
+	end process SHIFTREG;	
+
+	P_BITCNT: process
+	begin
+		wait until CLK = '1' and CLK' event;
+		if RCV_STATE = SAMPLE and CLK_STRB = '1' then
+			BITCNT <= BITCNT + '1';
+		elsif RCV_STATE /= SAMPLE then
+			BITCNT <= (others => '0');
+		end if;
+	end process P_BITCNT;
+
+	FRAME_ERR: process(RESETn, CLK)
+	-- This module detects a framing error
+	-- during stop bit 1 and stop bit 2.
+	variable FE_I: bit;
+	begin
+		if RESETn = '0' then
+			FE_I := '0';
+			FE <= '0';
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				FE_I := '0';
+				FE <= '0';
+			elsif CLK_STRB = '1' then
+				if RCV_STATE = STOP1 and RXDATA_S = '0' then
+					FE_I := '1';
+				elsif RCV_STATE = STOP2 and RXDATA_S = '0' then
+					FE_I := '1';
+				elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then
+					FE_I := '0'; -- Error resets when correct data appears.
+				end if;
+			end if;
+			if RCV_STATE = SYNC then
+				FE <= FE_I; -- Update the FE every SYNC time.
+			end if;
+		end if;
+	end process FRAME_ERR;
+
+	OVERRUN: process(RESETn, CLK)
+	variable OVR_I		: bit;
+	variable FIRST_READ	: boolean;
+	begin
+		if RESETn = '0' then
+			OVR_I := '0';
+			OVR <= '0';
+			FIRST_READ := false;
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				OVR_I := '0';
+				OVR <= '0';
+				FIRST_READ := false;
+			elsif CLK_STRB = '1' and RCV_STATE = STOP1 then
+				-- Overrun appears if RDRF is '1' in this state.
+				OVR_I := RDRF;
+			end if;
+			if CS = "011" and RWn = '1' and RS = '1' and E = '1' and OVR_I = '1' then
+				-- If an overrun was detected, the concerning flag is
+				-- set when the valid data word in the receiver data
+				-- register is read. Thereafter the RDRF flag is reset
+				-- and the overrun disappears (OVR_I goes low) after 
+				-- a second read (in time) of the receiver data register.
+				if FIRST_READ = false then
+					OVR <= '1';
+					FIRST_READ := true;
+				else
+					OVR <= '0';
+					FIRST_READ := false;
+				end if;
+			end if;
+		end if;
+	end process OVERRUN;
+	
+	PARITY_TEST: process(RESETn, CLK)
+	variable PAR_TMP	: bit;
+	variable PE_I		: bit;
+	begin
+		if RESETn = '0' then
+			PE <= '0';
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				PE <= '0';
+			elsif CLK_STRB = '1' then -- Sample parity on clock strobe.
+				PE_I := '0'; -- Initialise.
+				if RCV_STATE = PARITY then
+				    for i in 1 to 7 loop
+				        if i = 1 then
+				            PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
+				        else
+				            PAR_TMP := PAR_TMP xor SHIFT_REG(i);
+				        end if;
+				    end loop;
+					if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
+				    	PE_I := PAR_TMP xor RXDATA_S;
+					elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
+						PE_I := not PAR_TMP xor RXDATA_S;
+					else -- No parity for WS = "100" and WS = "101".
+						PE_I := '0';		
+					end if;
+				end if;
+			end if;
+			-- Transmit the parity flag together with the data
+			-- In other words: no parity to the status register
+			-- when RDRF inhibits the data transfer to the
+			-- receiver data register.
+			if RCV_STATE = SYNC and RDRF = '0' then
+				PE <= PE_I;
+			elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
+				PE <= '0'; -- Clear when reading the data register.
+			end if;
+		end if;
+	end process PARITY_TEST;
+
+	P_RDRF: process(RESETn, CLK)
+	-- Receive data register full flag.
+	begin
+		if RESETn = '0' then
+			RDRF <= '0';
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				RDRF <= '0';
+			elsif RCV_STATE = SYNC then
+				RDRF <= '1'; -- Data register is full until now!
+			elsif CS = "011" and RWn = '1' and RS = '1' and E = '1' then
+				RDRF <= '0'; -- After reading the data register ...
+			end if;
+		end if;
+	end process P_RDRF;
+	
+	RCV_STATEREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			RCV_STATE <= IDLE;
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				RCV_STATE <= IDLE;
+			else
+				RCV_STATE <= RCV_NEXT_STATE;
+			end if;
+		end if;
+	end process RCV_STATEREG;
+	
+	RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB)
+	begin
+		case RCV_STATE is
+			when IDLE =>
+				if RXDATA_S = '0' and CDS = "00" then
+					RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode.
+				elsif RXDATA_S = '0' and CDS = "01" then
+					RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode.
+				elsif RXDATA_S = '0' and CDS = "10" then
+					RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode.
+				else
+					RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-)
+				end if;
+			when WAIT_START =>
+				if CLK_STRB = '1' then
+					if RXDATA_S = '0' then
+						RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes.
+					else
+						RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back.
+					end if;
+				else
+					RCV_NEXT_STATE <= WAIT_START; -- Stay.
+				end if;
+			when SAMPLE =>
+				if CLK_STRB = '1' then
+					if BITCNT < "110" and WS(2) = '0' then
+						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits.
+					elsif BITCNT < "111" and WS(2) = '1' then
+						RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits.
+					elsif WS = "100" or WS = "101" then
+						RCV_NEXT_STATE <= STOP1; -- No parity check enabled.
+					else
+						RCV_NEXT_STATE <= PARITY; -- Parity enabled.
+					end if;
+				else
+					RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode.
+				end if;
+			when PARITY =>
+				if CLK_STRB = '1' then
+					RCV_NEXT_STATE <= STOP1;
+				else
+					RCV_NEXT_STATE <= PARITY;
+				end if;				
+			when STOP1 =>
+				if CLK_STRB = '1' then
+					if RXDATA_S = '0' then
+						RCV_NEXT_STATE <= SYNC; -- Framing error detected.
+					elsif WS = "000" or WS = "001" or WS = "100" then
+						RCV_NEXT_STATE <= STOP2; -- Two stop bits selected.
+					else
+						RCV_NEXT_STATE <= SYNC; -- One stop bit selected.
+					end if;
+				else
+					RCV_NEXT_STATE <= STOP1;
+				end if;				
+			when STOP2 =>
+				if CLK_STRB = '1' then
+					RCV_NEXT_STATE <= SYNC;
+				else
+					RCV_NEXT_STATE <= STOP2;
+				end if;				
+			when SYNC =>
+				RCV_NEXT_STATE <= IDLE;
+		end case;
+	end process RCV_STATEDEC;
+end architecture BEHAVIOR;
+
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
new file mode 100644
index 0000000..60a7885
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
@@ -0,0 +1,135 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- 6850 compatible IP Core     					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- UART 6850 compatible IP core                                 ----
+----                                                              ----
+---- This is the top level file.                                  ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 Wolfgang Foerster                         ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B	2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8B  2008/12/24 WF
+--   Rewritten this top level file as a wrapper for the top_soc file.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF6850IP_TOP is
+  port (
+		CLK					: in bit;
+        RESETn				: in bit;
+
+        CS2n, CS1, CS0		: in bit;
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+
+        DATA		        : inout std_logic_vector(7 downto 0);   
+
+        TXCLK				: in bit;
+        RXCLK				: in bit;
+        RXDATA				: in bit;
+        CTSn				: in bit;
+        DCDn				: in bit;
+        
+        IRQn				: out std_logic;
+        TXDATA				: out bit;   
+        RTSn				: out bit
+       );                                              
+end entity WF6850IP_TOP;
+
+architecture STRUCTURE of WF6850IP_TOP is
+component WF6850IP_TOP_SOC
+  port (
+		CLK					: in bit;
+        RESETn				: in bit;
+        CS2n, CS1, CS0		: in bit;
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+        DATA_IN		        : in std_logic_vector(7 downto 0);   
+        DATA_OUT	        : out std_logic_vector(7 downto 0);   
+		DATA_EN				: out bit;
+        TXCLK				: in bit;
+        RXCLK				: in bit;
+        RXDATA				: in bit;
+        CTSn				: in bit;
+        DCDn				: in bit;
+        IRQn				: out bit;
+        TXDATA				: out bit;   
+        RTSn				: out bit
+       );                                              
+end component;
+signal DATA_OUT     : std_logic_vector(7 downto 0);
+signal DATA_EN      : bit;
+signal IRQ_In       : bit;
+begin
+    DATA <= DATA_OUT when DATA_EN = '1' else (others => 'Z');
+    IRQn <= '0' when IRQ_In = '0' else 'Z'; -- Open drain.
+
+    I_UART: WF6850IP_TOP_SOC
+      port map(CLK          => CLK,
+               RESETn       => RESETn,
+               CS2n         => CS2n,
+               CS1          => CS1,
+               CS0          => CS0,
+               E            => E,
+               RWn          => RWn,
+               RS           => RS,
+               DATA_IN      => DATA,
+               DATA_OUT     => DATA_OUT,
+               DATA_EN      => DATA_EN,
+               TXCLK        => TXCLK,
+               RXCLK        => RXCLK,
+               RXDATA       => RXDATA,
+               CTSn         => CTSn,
+               DCDn         => DCDn,
+               IRQn         => IRQ_In,
+               TXDATA       => TXDATA,
+               RTSn         => RTSn
+           );                                              
+end architecture STRUCTURE;
\ No newline at end of file
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
new file mode 100644
index 0000000..cbca6bd
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
@@ -0,0 +1,255 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- 6850 compatible IP Core     					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- UART 6850 compatible IP core                                 ----
+----                                                              ----
+---- This is the top level file.                                  ----
+---- Top level file for use in systems on programmable chips.     ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+--   Top level file provided for SOC (systems on programmable chips).
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K9B  2009/12/24 WF
+--   Fixed the interrupt logic.
+--   Introduced a minor RTSn correction.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF6850IP_TOP_SOC is
+  port (
+		CLK					: in bit;
+        RESETn				: in bit;
+
+        CS2n, CS1, CS0		: in bit;
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+
+        DATA_IN		        : in std_logic_vector(7 downto 0);   
+        DATA_OUT	        : out std_logic_vector(7 downto 0);   
+		DATA_EN				: out bit;
+
+        TXCLK				: in bit;
+        RXCLK				: in bit;
+        RXDATA				: in bit;
+        CTSn				: in bit;
+        DCDn				: in bit;
+        
+        IRQn				: out bit;
+        TXDATA				: out bit;   
+        RTSn				: out bit
+       );                                              
+end entity WF6850IP_TOP_SOC;
+
+architecture STRUCTURE of WF6850IP_TOP_SOC is
+component WF6850IP_CTRL_STATUS
+	port (
+		CLK			: in bit;
+        RESETn		: in bit;
+        CS			: in bit_vector(2 downto 0);
+        E			: in bit;   
+        RWn     	: in bit;
+        RS			: in bit;
+        DATA_IN		: in bit_vector(7 downto 0);   
+        DATA_OUT	: out bit_vector(7 downto 0);  
+		DATA_EN		: out bit;
+		RDRF		: in bit;
+		TDRE		: in bit;
+		DCDn		: in bit;
+		CTSn		: in bit;
+		FE			: in bit;
+		OVR			: in bit;
+		PE			: in bit;
+		MCLR		: out bit;
+		RTSn		: out bit;
+		CDS			: out bit_vector(1 downto 0);
+		WS			: out bit_vector(2 downto 0);
+		TC			: out bit_vector(1 downto 0);
+		IRQn		: out bit
+       );                                              
+end component;
+
+component WF6850IP_RECEIVE
+	port (
+		CLK					: in bit;
+        RESETn				: in bit;
+		MCLR				: in bit;
+        CS					: in bit_vector(2 downto 0);
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+        DATA_OUT	        : out bit_vector(7 downto 0);   
+		DATA_EN				: out bit;
+		WS					: in bit_vector(2 downto 0);
+		CDS					: in bit_vector(1 downto 0);
+        RXCLK				: in bit;
+        RXDATA				: in bit;
+		RDRF				: out bit;
+		OVR					: out bit;
+		PE					: out bit;
+		FE					: out bit
+       );                                              
+end component;
+
+component WF6850IP_TRANSMIT
+	port (
+		CLK					: in bit;
+        RESETn				: in bit;
+		MCLR				: in bit;
+        CS					: in bit_vector(2 downto 0);
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+        DATA_IN		        : in bit_vector(7 downto 0);   
+		CTSn				: in bit;
+		TC					: in bit_vector(1 downto 0);
+		WS					: in bit_vector(2 downto 0);
+		CDS					: in bit_vector(1 downto 0);
+        TXCLK				: in bit;
+		TDRE				: out bit;        
+        TXDATA				: out bit
+       );                                              
+end component;
+signal DATA_IN_I	: bit_vector(7 downto 0);
+signal DATA_RX		: bit_vector(7 downto 0);
+signal DATA_RX_EN	: bit;
+signal DATA_CTRL	: bit_vector(7 downto 0);
+signal DATA_CTRL_EN	: bit;
+signal RDRF_I		: bit;
+signal TDRE_I		: bit;
+signal FE_I			: bit;
+signal OVR_I		: bit;
+signal PE_I			: bit;
+signal MCLR_I		: bit;
+signal CDS_I		: bit_vector(1 downto 0);
+signal WS_I			: bit_vector(2 downto 0);
+signal TC_I			: bit_vector(1 downto 0);
+signal IRQ_In		: bit;
+begin
+	DATA_IN_I <= To_BitVector(DATA_IN);
+	DATA_EN <= DATA_RX_EN or DATA_CTRL_EN;
+	DATA_OUT <= To_StdLogicVector(DATA_RX) when DATA_RX_EN = '1' else
+				To_StdLogicVector(DATA_CTRL) when DATA_CTRL_EN = '1' else (others => '0');
+				
+	IRQn <= '0' when IRQ_In = '0' else '1';
+
+	I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS
+	port map(
+			CLK			=> CLK,
+	        RESETn		=> RESETn,
+	        CS(2)		=> CS2n,
+	        CS(1)		=> CS1,
+	        CS(0)		=> CS0,
+	        E			=> E,
+	        RWn     	=> RWn,
+	        RS			=> RS,
+	        DATA_IN		=> DATA_IN_I,
+			DATA_OUT	=> DATA_CTRL,
+			DATA_EN		=> DATA_CTRL_EN,
+			RDRF		=> RDRF_I,
+			TDRE		=> TDRE_I,
+			DCDn		=> DCDn,
+			CTSn		=> CTSn,
+			FE			=> FE_I,
+			OVR			=> OVR_I,
+			PE			=> PE_I,
+			MCLR		=> MCLR_I,
+			RTSn		=> RTSn,
+			CDS			=> CDS_I,
+			WS			=> WS_I,
+			TC			=> TC_I,
+			IRQn		=> IRQ_In
+	);                                              
+
+	I_UART_RECEIVE: WF6850IP_RECEIVE
+	port map (
+			CLK			=> CLK,
+	        RESETn		=> RESETn,
+			MCLR		=> MCLR_I,
+	        CS(2)		=> CS2n,
+	        CS(1)		=> CS1,
+	        CS(0)		=> CS0,
+	        E			=> E,
+	        RWn     	=> RWn,
+	        RS			=> RS,
+	        DATA_OUT	=> DATA_RX,
+			DATA_EN		=> DATA_RX_EN,
+			WS			=> WS_I,
+			CDS			=> CDS_I,
+			RXCLK		=> RXCLK,
+			RXDATA		=> RXDATA,
+			RDRF		=> RDRF_I,
+			OVR			=> OVR_I,
+			PE			=> PE_I,
+			FE			=> FE_I
+	);                                              
+
+	I_UART_TRANSMIT: WF6850IP_TRANSMIT
+	port map (
+			CLK			=> CLK,
+	        RESETn		=> RESETn,
+			MCLR		=> MCLR_I,
+	        CS(2)		=> CS2n,
+	        CS(1)		=> CS1,
+	        CS(0)		=> CS0,
+	        E			=> E,
+	        RWn     	=> RWn,
+	        RS			=> RS,
+	        DATA_IN		=> DATA_IN_I,
+			CTSn		=> CTSn,
+			TC			=> TC_I,
+			WS			=> WS_I,
+			CDS			=> CDS_I,
+			TDRE		=> TDRE_I,
+			TXCLK		=> TXCLK,
+			TXDATA		=> TXDATA
+	);
+end architecture STRUCTURE;
\ No newline at end of file
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak
new file mode 100644
index 0000000..6f80a67
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak
@@ -0,0 +1,252 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- 6850 compatible IP Core     					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- UART 6850 compatible IP core                                 ----
+----                                                              ----
+---- This is the top level file.                                  ----
+---- Top level file for use in systems on programmable chips.     ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+--   Top level file provided for SOC (systems on programmable chips).
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF6850IP_TOP_SOC is
+  port (
+		CLK					: in bit;
+        RESETn				: in bit;
+
+        CS2n, CS1, CS0		: in bit;
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+
+        DATA_IN		        : in std_logic_vector(7 downto 0);   
+        DATA_OUT	        : out std_logic_vector(7 downto 0);   
+		DATA_EN				: out bit;
+
+        TXCLK				: in bit;
+        RXCLK				: in bit;
+        RXDATA				: in bit;
+        CTSn				: in bit;
+        DCDn				: in bit;
+        
+        IRQn				: out bit;
+        TXDATA				: out bit;   
+        RTSn				: out bit
+       );                                              
+end entity WF6850IP_TOP_SOC;
+
+architecture STRUCTURE of WF6850IP_TOP_SOC is
+component WF6850IP_CTRL_STATUS
+	port (
+		CLK			: in bit;
+        RESETn		: in bit;
+        CS			: in bit_vector(2 downto 0);
+        E			: in bit;   
+        RWn     	: in bit;
+        RS			: in bit;
+        DATA_IN		: in bit_vector(7 downto 0);   
+        DATA_OUT	: out bit_vector(7 downto 0);  
+		DATA_EN		: out bit;
+		RDRF		: in bit;
+		TDRE		: in bit;
+		DCDn		: in bit;
+		CTSn		: in bit;
+		FE			: in bit;
+		OVR			: in bit;
+		PE			: in bit;
+		MCLR		: out bit;
+		RTSn		: out bit;
+		CDS			: out bit_vector(1 downto 0);
+		WS			: out bit_vector(2 downto 0);
+		TC			: out bit_vector(1 downto 0);
+		IRQn		: out bit
+       );                                              
+end component;
+
+component WF6850IP_RECEIVE
+	port (
+		CLK					: in bit;
+        RESETn				: in bit;
+		MCLR				: in bit;
+        CS					: in bit_vector(2 downto 0);
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+        DATA_OUT	        : out bit_vector(7 downto 0);   
+		DATA_EN				: out bit;
+		WS					: in bit_vector(2 downto 0);
+		CDS					: in bit_vector(1 downto 0);
+        RXCLK				: in bit;
+        RXDATA				: in bit;
+		RDRF				: out bit;
+		OVR					: out bit;
+		PE					: out bit;
+		FE					: out bit
+       );                                              
+end component;
+
+component WF6850IP_TRANSMIT
+	port (
+		CLK					: in bit;
+        RESETn				: in bit;
+		MCLR				: in bit;
+        CS					: in bit_vector(2 downto 0);
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+        DATA_IN		        : in bit_vector(7 downto 0);   
+		CTSn				: in bit;
+		TC					: in bit_vector(1 downto 0);
+		WS					: in bit_vector(2 downto 0);
+		CDS					: in bit_vector(1 downto 0);
+        TXCLK				: in bit;
+		TDRE				: out bit;        
+        TXDATA				: out bit
+       );                                              
+end component;
+signal DATA_IN_I	: bit_vector(7 downto 0);
+signal DATA_RX		: bit_vector(7 downto 0);
+signal DATA_RX_EN	: bit;
+signal DATA_CTRL	: bit_vector(7 downto 0);
+signal DATA_CTRL_EN	: bit;
+signal RDRF_I		: bit;
+signal TDRE_I		: bit;
+signal FE_I			: bit;
+signal OVR_I		: bit;
+signal PE_I			: bit;
+signal MCLR_I		: bit;
+signal CDS_I		: bit_vector(1 downto 0);
+signal WS_I			: bit_vector(2 downto 0);
+signal TC_I			: bit_vector(1 downto 0);
+signal IRQ_In		: bit;
+begin
+	DATA_IN_I <= To_BitVector(DATA_IN);
+	DATA_EN <= DATA_RX_EN or DATA_CTRL_EN;
+	DATA_OUT <= To_StdLogicVector(DATA_RX) when DATA_RX_EN = '1' else
+				To_StdLogicVector(DATA_CTRL) when DATA_CTRL_EN = '1' else (others => '0');
+				
+	IRQn <= '0' when IRQ_In = '0' else '1';
+
+	I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS
+	port map(
+			CLK			=> CLK,
+	        RESETn		=> RESETn,
+	        CS(2)		=> CS2n,
+	        CS(1)		=> CS1,
+	        CS(0)		=> CS0,
+	        E			=> E,
+	        RWn     	=> RWn,
+	        RS			=> RS,
+	        DATA_IN		=> DATA_IN_I,
+			DATA_OUT	=> DATA_CTRL,
+			DATA_EN		=> DATA_CTRL_EN,
+			RDRF		=> RDRF_I,
+			TDRE		=> TDRE_I,
+			DCDn		=> DCDn,
+			CTSn		=> CTSn,
+			FE			=> FE_I,
+			OVR			=> OVR_I,
+			PE			=> PE_I,
+			MCLR		=> MCLR_I,
+			RTSn		=> RTSn,
+			CDS			=> CDS_I,
+			WS			=> WS_I,
+			TC			=> TC_I,
+			IRQn		=> IRQ_In
+	);                                              
+
+	I_UART_RECEIVE: WF6850IP_RECEIVE
+	port map (
+			CLK			=> CLK,
+	        RESETn		=> RESETn,
+			MCLR		=> MCLR_I,
+	        CS(2)		=> CS2n,
+	        CS(1)		=> CS1,
+	        CS(0)		=> CS0,
+	        E			=> E,
+	        RWn     	=> RWn,
+	        RS			=> RS,
+	        DATA_OUT	=> DATA_RX,
+			DATA_EN		=> DATA_RX_EN,
+			WS			=> WS_I,
+			CDS			=> CDS_I,
+			RXCLK		=> RXCLK,
+			RXDATA		=> RXDATA,
+			RDRF		=> RDRF_I,
+			OVR			=> OVR_I,
+			PE			=> PE_I,
+			FE			=> FE_I
+	);                                              
+
+	I_UART_TRANSMIT: WF6850IP_TRANSMIT
+	port map (
+			CLK			=> CLK,
+	        RESETn		=> RESETn,
+			MCLR		=> MCLR_I,
+	        CS(2)		=> CS2n,
+	        CS(1)		=> CS1,
+	        CS(0)		=> CS0,
+	        E			=> E,
+	        RWn     	=> RWn,
+	        RS			=> RS,
+	        DATA_IN		=> DATA_IN_I,
+			CTSn		=> CTSn,
+			TC			=> TC_I,
+			WS			=> WS_I,
+			CDS			=> CDS_I,
+			TDRE		=> TDRE_I,
+			TXCLK		=> TXCLK,
+			TXDATA		=> TXDATA
+	);
+end architecture STRUCTURE;
\ No newline at end of file
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
new file mode 100644
index 0000000..c8ae6fc
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
@@ -0,0 +1,339 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- 6850 compatible IP Core    					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- UART 6850 compatible IP core                                 ----
+----                                                              ----
+---- 6850's transmitter unit.                                     ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K8B  2008/11/01 WF
+--   Fixed the T_DRE process concerning the TDRE <= '1' setting.
+--   Thanks to Lyndon Amsdon finding the bug.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF6850IP_TRANSMIT is
+  port (
+		CLK					: in bit;
+        RESETn				: in bit;
+		MCLR				: in bit;
+
+        CS					: in bit_vector(2 downto 0);
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+
+        DATA_IN		        : in bit_vector(7 downto 0);   
+
+		CTSn				: in bit;
+
+		TC					: in bit_vector(1 downto 0);
+		WS					: in bit_vector(2 downto 0);
+		CDS					: in bit_vector(1 downto 0);
+
+        TXCLK				: in bit;
+
+		TDRE				: buffer bit;
+        TXDATA				: out bit
+       );                                              
+end entity WF6850IP_TRANSMIT;
+
+architecture BEHAVIOR of WF6850IP_TRANSMIT is
+type TR_STATES is (IDLE, LOAD_SHFT, START, SHIFTOUT, PARITY, STOP1, STOP2);
+signal TR_STATE, TR_NEXT_STATE	: TR_STATES;
+signal CLK_STRB		: bit;
+signal DATA_REG		: bit_vector(7 downto 0);
+signal SHIFT_REG	: bit_vector(7 downto 0);
+signal BITCNT		: std_logic_vector(2 downto 0);
+signal PARITY_I		: bit;
+begin
+	-- The default condition in this statement is to ensure
+	-- to cover all possibilities for example if there is a
+	-- one hot decoding of the state machine with wrong states
+	-- (e.g. not one of the given here).
+	TXDATA <= 	'1' 			when TR_STATE = IDLE 		else
+				'1' 			when TR_STATE = LOAD_SHFT 	else
+				'0' 			when TR_STATE = START 		else
+				SHIFT_REG(0) 	when TR_STATE = SHIFTOUT 	else
+				PARITY_I		when TR_STATE = PARITY 		else
+				'1'				when TR_STATE = STOP1 		else
+				'1'				when TR_STATE = STOP2 		else '1';
+
+	CLKDIV: process
+	variable CLK_LOCK	: boolean;
+	variable STRB_LOCK	: boolean;
+	variable CLK_DIVCNT	: std_logic_vector(6 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		if CDS = "00" then -- divider off
+			if TXCLK = '0' and STRB_LOCK = false then  -- Works on negative TXCLK edge.
+				CLK_STRB <= '1';
+				STRB_LOCK := true;
+			elsif TXCLK = '1' then
+				CLK_STRB <= '0';
+				STRB_LOCK := false;
+			else
+				CLK_STRB <= '0';
+			end if;
+		elsif TR_STATE = IDLE then
+			-- preset the CLKDIV with the start delays
+			if CDS = "01" then
+				CLK_DIVCNT := "0010000"; -- div by 16 mode
+			elsif CDS = "10" then
+				CLK_DIVCNT := "1000000"; -- div by 64 mode
+			end if;
+			CLK_STRB <= '0';
+		else
+			-- Works on negative TXCLK edge:
+			if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then
+				CLK_DIVCNT := CLK_DIVCNT - '1';
+				CLK_STRB <= '0';
+				CLK_LOCK := true;
+			elsif CDS = "01" and CLK_DIVCNT = "0000000" then
+				CLK_DIVCNT := "0010000"; -- Div by 16 mode.
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				else
+					CLK_STRB <= '0';
+				end if;
+			elsif CDS = "10" and CLK_DIVCNT = "0000000" then
+				CLK_DIVCNT := "1000000"; -- Div by 64 mode.
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				else
+					CLK_STRB <= '0';
+				end if;
+			elsif TXCLK = '1' then
+				CLK_LOCK := false;
+				STRB_LOCK := false;
+				CLK_STRB <= '0';
+			else
+				CLK_STRB <= '0';
+			end if;
+		end if;
+	end process CLKDIV;
+
+	DATAREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DATA_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				DATA_REG <= x"00";
+			elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then
+				DATA_REG <= '0' & DATA_IN(6 downto 0); -- 7 bit data mode.
+			elsif WS(2) = '1' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then
+				DATA_REG <= DATA_IN; -- 8 bit data mode.
+			end if;
+		end if;
+	end process DATAREG;	
+
+	SHIFTREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SHIFT_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				SHIFT_REG <= x"00";
+			elsif TR_STATE = LOAD_SHFT and TDRE = '0' then
+				-- If during LOAD_SHIFT the transmitter data register
+				-- is empty (TDRE = '1') the shift register will not
+				-- be loaded. When additionally TC = "11", the break
+				-- character (zero data and no stop bits) is sent.
+				SHIFT_REG <= DATA_REG;
+			elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then
+				SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right.
+			end if;
+		end if;
+	end process SHIFTREG;	
+
+	P_BITCNT: process
+	-- Counter for the data bits transmitted.
+	begin
+		wait until CLK = '1' and CLK' event;
+		if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
+			BITCNT <= BITCNT + '1';
+		elsif TR_STATE /= SHIFTOUT then
+			BITCNT <= "000";
+		end if;
+	end process P_BITCNT;
+
+	P_TDRE: process(RESETn, CLK)
+	-- Transmit data register empty flag.
+	variable LOCK	: boolean;
+	begin
+		if RESETn = '0' then
+			TDRE <= '1';
+			LOCK := false;
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				TDRE <= '1';
+            elsif TR_NEXT_STATE = START and TR_STATE /= START then
+				-- Data has been loaded to shift register, thus data register is free again.
+				-- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once
+				-- entering the state now.
+				TDRE <= '1';
+			elsif  CS = "011" and RWn = '0' and RS = '1' and E = '1' and LOCK = false then
+				LOCK := true;
+			elsif E = '0' and LOCK = true then
+				-- This construction clears TDRE after the falling edge of E
+				-- and after the transmit data register has been written to.
+				TDRE <= '0';
+				LOCK := false;
+			end if;
+		end if;
+	end process P_TDRE;
+
+	PARITY_GEN: process
+	variable PAR_TMP	: bit;
+	begin
+		wait until CLK = '1' and CLK' event;
+		if TR_STATE = START then -- Calculate the parity during the start phase.
+		    for i in 1 to 7 loop
+		        if i = 1 then
+		            PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
+		        else
+		            PAR_TMP := PAR_TMP xor SHIFT_REG(i);
+		        end if;
+		    end loop;
+			if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
+				PARITY_I <= PAR_TMP;
+			elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
+				PARITY_I <= not PAR_TMP;
+			else -- No parity for WS = "100" and WS = "101".
+				PARITY_I <= '0';		
+			end if;
+		end if;
+	end process PARITY_GEN;
+
+	TR_STATEREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			TR_STATE <= IDLE;
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				TR_STATE <= IDLE;
+			else
+				TR_STATE <= TR_NEXT_STATE;
+			end if;
+		end if;
+	end process TR_STATEREG;
+	
+	TR_STATEDEC: process(TR_STATE, CLK_STRB, TC, BITCNT, WS, TDRE, CTSn)
+	begin
+		case TR_STATE is
+			when IDLE =>
+				if TDRE = '1' and TC = "11" then
+					TR_NEXT_STATE <= LOAD_SHFT;
+				elsif TDRE = '0' and CTSn = '0' then -- Start if data register is not empty.
+					TR_NEXT_STATE <= LOAD_SHFT;
+				else
+					TR_NEXT_STATE <= IDLE;
+				end if;
+			when LOAD_SHFT =>
+				TR_NEXT_STATE <= START;
+			when START =>
+				if CLK_STRB = '1' then
+					TR_NEXT_STATE <= SHIFTOUT;
+				else
+					TR_NEXT_STATE <= START;
+				end if;
+			when SHIFTOUT =>
+				if CLK_STRB = '1' then
+					if BITCNT < "110" and WS(2) = '0' then
+						TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data bits.
+					elsif BITCNT < "111" and WS(2) = '1' then
+						TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data bits.
+					elsif WS = "100" or WS = "101" then
+						if TDRE = '1' and TC = "11" then
+							-- Break condition, do not send a stop bit.
+							TR_NEXT_STATE <= IDLE;
+						else
+							TR_NEXT_STATE <= STOP1; -- No parity check enabled.
+						end if;
+					else
+						TR_NEXT_STATE <= PARITY; -- Parity enabled.
+					end if;
+				else
+					TR_NEXT_STATE <= SHIFTOUT;
+				end if;
+			when PARITY =>
+				if CLK_STRB = '1' then
+					if TDRE = '1' and TC = "11" then
+						-- Break condition, do not send a stop bit.
+						TR_NEXT_STATE <= IDLE;
+					else
+						TR_NEXT_STATE <= STOP1; -- No parity check enabled.
+					end if;
+				else
+					TR_NEXT_STATE <= PARITY;
+				end if;				
+			when STOP1 =>
+				if CLK_STRB = '1' and (WS = "000" or WS = "001" or WS = "100") then
+					TR_NEXT_STATE <= STOP2; -- Two stop bits selected.
+				elsif CLK_STRB = '1' then
+					TR_NEXT_STATE <= IDLE; -- One stop bits selected.
+				else
+					TR_NEXT_STATE <= STOP1;
+				end if;				
+			when STOP2 =>
+				if CLK_STRB = '1' then
+					TR_NEXT_STATE <= IDLE;
+				else
+					TR_NEXT_STATE <= STOP2;
+				end if;				
+		end case;
+	end process TR_STATEDEC;
+end architecture BEHAVIOR;
+
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak
new file mode 100644
index 0000000..bcff094
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak
@@ -0,0 +1,339 @@
+----------------------------------------------------------------------
+----                                                              ----
+---- 6850 compatible IP Core    					              ----
+----                                                              ----
+---- This file is part of the SUSKA ATARI clone project.          ----
+---- http://www.experiment-s.de                                   ----
+----                                                              ----
+---- Description:                                                 ----
+---- UART 6850 compatible IP core                                 ----
+----                                                              ----
+---- 6850's transmitter unit.                                     ----
+----                                                              ----
+----                                                              ----
+---- To Do:                                                       ----
+---- -                                                            ----
+----                                                              ----
+---- Author(s):                                                   ----
+---- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de   ----
+----                                                              ----
+----------------------------------------------------------------------
+----                                                              ----
+---- Copyright (C) 2006 - 2008 Wolfgang Foerster                  ----
+----                                                              ----
+---- This source file may be used and distributed without         ----
+---- restriction provided that this copyright statement is not    ----
+---- removed from the file and that any derivative work contains  ----
+---- the original copyright notice and the associated disclaimer. ----
+----                                                              ----
+---- This source file is free software; you can redistribute it   ----
+---- and/or modify it under the terms of the GNU Lesser General   ----
+---- Public License as published by the Free Software Foundation; ----
+---- either version 2.1 of the License, or (at your option) any   ----
+---- later version.                                               ----
+----                                                              ----
+---- This source is distributed in the hope that it will be       ----
+---- useful, but WITHOUT ANY WARRANTY; without even the implied   ----
+---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ----
+---- PURPOSE. See the GNU Lesser General Public License for more  ----
+---- details.                                                     ----
+----                                                              ----
+---- You should have received a copy of the GNU Lesser General    ----
+---- Public License along with this source; if not, download it   ----
+---- from http://www.gnu.org/licenses/lgpl.html                   ----
+----                                                              ----
+----------------------------------------------------------------------
+-- 
+-- Revision History
+-- 
+-- Revision 2K6A  2006/06/03 WF
+--   Initial Release.
+-- Revision 2K6B  2006/11/07 WF
+--   Modified Source to compile with the Xilinx ISE.
+-- Revision 2K8A  2008/07/14 WF
+--   Minor changes.
+-- Revision 2K8B  2008/11/01 WF
+--   Fixed the T_DRE process concerning the TDRE <= '1' setting.
+--   Thanks to Lyndon Amsdon finding the bug.
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity WF6850IP_TRANSMIT is
+  port (
+		CLK					: in bit;
+        RESETn				: in bit;
+		MCLR				: in bit;
+
+        CS					: in bit_vector(2 downto 0);
+        E		       		: in bit;   
+        RWn              	: in bit;
+        RS					: in bit;
+
+        DATA_IN		        : in bit_vector(7 downto 0);   
+
+		CTSn				: in bit;
+
+		TC					: in bit_vector(1 downto 0);
+		WS					: in bit_vector(2 downto 0);
+		CDS					: in bit_vector(1 downto 0);
+
+        TXCLK				: in bit;
+
+		TDRE				: buffer bit;
+        TXDATA				: out bit
+       );                                              
+end entity WF6850IP_TRANSMIT;
+
+architecture BEHAVIOR of WF6850IP_TRANSMIT is
+type TR_STATES is (IDLE, LOAD_SHFT, START, SHIFTOUT, PARITY, STOP1, STOP2);
+signal TR_STATE, TR_NEXT_STATE	: TR_STATES;
+signal CLK_STRB		: bit;
+signal DATA_REG		: bit_vector(7 downto 0);
+signal SHIFT_REG	: bit_vector(7 downto 0);
+signal BITCNT		: std_logic_vector(2 downto 0);
+signal PARITY_I		: bit;
+begin
+	-- The default condition in this statement is to ensure
+	-- to cover all possibilities for example if there is a
+	-- one hot decoding of the state machine with wrong states
+	-- (e.g. not one of the given here).
+	TXDATA <= 	'1' 			when TR_STATE = IDLE 		else
+				'1' 			when TR_STATE = LOAD_SHFT 	else
+				'0' 			when TR_STATE = START 		else
+				SHIFT_REG(0) 	when TR_STATE = SHIFTOUT 	else
+				PARITY_I		when TR_STATE = PARITY 		else
+				'1'				when TR_STATE = STOP1 		else
+				'1'				when TR_STATE = STOP2 		else '1';
+
+	CLKDIV: process
+	variable CLK_LOCK	: boolean;
+	variable STRB_LOCK	: boolean;
+	variable CLK_DIVCNT	: std_logic_vector(6 downto 0);
+	begin
+		wait until CLK = '1' and CLK' event;
+		if CDS = "00" then -- divider off
+			if TXCLK = '0' and STRB_LOCK = false then  -- Works on negative TXCLK edge.
+				CLK_STRB <= '1';
+				STRB_LOCK := true;
+			elsif TXCLK = '1' then
+				CLK_STRB <= '0';
+				STRB_LOCK := false;
+			else
+				CLK_STRB <= '0';
+			end if;
+		elsif TR_STATE = IDLE then
+			-- preset the CLKDIV with the start delays
+			if CDS = "01" then
+				CLK_DIVCNT := "0010000"; -- div by 16 mode
+			elsif CDS = "10" then
+				CLK_DIVCNT := "1000000"; -- div by 64 mode
+			end if;
+			CLK_STRB <= '0';
+		else
+			-- Works on negative TXCLK edge:
+			if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then
+				CLK_DIVCNT := CLK_DIVCNT - '1';
+				CLK_STRB <= '0';
+				CLK_LOCK := true;
+			elsif CDS = "01" and CLK_DIVCNT = "0000000" then
+				CLK_DIVCNT := "0010000"; -- Div by 16 mode.
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				else
+					CLK_STRB <= '0';
+				end if;
+			elsif CDS = "10" and CLK_DIVCNT = "0000000" then
+				CLK_DIVCNT := "1000000"; -- Div by 64 mode.
+				if STRB_LOCK = false then
+					STRB_LOCK := true;
+					CLK_STRB <= '1';
+				else
+					CLK_STRB <= '0';
+				end if;
+			elsif TXCLK = '1' then
+				CLK_LOCK := false;
+				STRB_LOCK := false;
+				CLK_STRB <= '0';
+			else
+				CLK_STRB <= '0';
+			end if;
+		end if;
+	end process CLKDIV;
+
+	DATAREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			DATA_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				DATA_REG <= x"00";
+			elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then
+				DATA_REG <= '0' & DATA_IN(6 downto 0); -- 7 bit data mode.
+			elsif WS(2) = '1' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then
+				DATA_REG <= DATA_IN; -- 8 bit data mode.
+			end if;
+		end if;
+	end process DATAREG;	
+
+	SHIFTREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			SHIFT_REG <= x"00";
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				SHIFT_REG <= x"00";
+			elsif TR_STATE = LOAD_SHFT and TDRE = '0' then
+				-- If during LOAD_SHIFT the transmitter data register
+				-- is empty (TDRE = '1') the shift register will not
+				-- be loaded. When additionally TC = "11", the break
+				-- character (zero data and no stop bits) is sent.
+				SHIFT_REG <= DATA_REG;
+			elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then
+				SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right.
+			end if;
+		end if;
+	end process SHIFTREG;	
+
+	P_BITCNT: process
+	-- Counter for the data bits transmitted.
+	begin
+		wait until CLK = '1' and CLK' event;
+		if TR_STATE = SHIFTOUT and CLK_STRB = '1' then
+			BITCNT <= BITCNT + '1';
+		elsif TR_STATE /= SHIFTOUT then
+			BITCNT <= "000";
+		end if;
+	end process P_BITCNT;
+
+	P_TDRE: process(RESETn, CLK)
+	-- Transmit data register empty flag.
+	variable LOCK	: boolean;
+	begin
+		if RESETn = '0' then
+			TDRE <= '1';
+			LOCK := false;
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				TDRE <= '1';
+            elsif TR_NEXT_STATE = START and TR_STATE /= START then
+				-- Data has been loaded to shift register, thus data register is free again.
+				-- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once
+				-- entering the state now.
+				TDRE <= '1';
+			elsif  CS = "011" and RWn = '0' and RS = '1' and E = '1' and LOCK = false then
+				LOCK := true;
+			elsif E = '0' and LOCK = true and CS /= "011" then
+				-- This construction clears TDRE after the falling edge of E
+				-- and after the transmit data register has been written to.
+				TDRE <= '0';
+				LOCK := false;
+			end if;
+		end if;
+	end process P_TDRE;
+
+	PARITY_GEN: process
+	variable PAR_TMP	: bit;
+	begin
+		wait until CLK = '1' and CLK' event;
+		if TR_STATE = START then -- Calculate the parity during the start phase.
+		    for i in 1 to 7 loop
+		        if i = 1 then
+		            PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i);
+		        else
+		            PAR_TMP := PAR_TMP xor SHIFT_REG(i);
+		        end if;
+		    end loop;
+			if WS = "000" or WS = "010" or WS = "110" then -- Even parity.
+				PARITY_I <= PAR_TMP;
+			elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity.
+				PARITY_I <= not PAR_TMP;
+			else -- No parity for WS = "100" and WS = "101".
+				PARITY_I <= '0';		
+			end if;
+		end if;
+	end process PARITY_GEN;
+
+	TR_STATEREG: process(RESETn, CLK)
+	begin
+		if RESETn = '0' then
+			TR_STATE <= IDLE;
+		elsif CLK = '1' and CLK' event then
+			if MCLR = '1' then
+				TR_STATE <= IDLE;
+			else
+				TR_STATE <= TR_NEXT_STATE;
+			end if;
+		end if;
+	end process TR_STATEREG;
+	
+	TR_STATEDEC: process(TR_STATE, CLK_STRB, TC, BITCNT, WS, TDRE, CTSn)
+	begin
+		case TR_STATE is
+			when IDLE =>
+				if TDRE = '1' and TC = "11" then
+					TR_NEXT_STATE <= LOAD_SHFT;
+				elsif TDRE = '0' and CTSn = '0' then -- Start if data register is not empty.
+					TR_NEXT_STATE <= LOAD_SHFT;
+				else
+					TR_NEXT_STATE <= IDLE;
+				end if;
+			when LOAD_SHFT =>
+				TR_NEXT_STATE <= START;
+			when START =>
+				if CLK_STRB = '1' then
+					TR_NEXT_STATE <= SHIFTOUT;
+				else
+					TR_NEXT_STATE <= START;
+				end if;
+			when SHIFTOUT =>
+				if CLK_STRB = '1' then
+					if BITCNT < "110" and WS(2) = '0' then
+						TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data bits.
+					elsif BITCNT < "111" and WS(2) = '1' then
+						TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data bits.
+					elsif WS = "100" or WS = "101" then
+						if TDRE = '1' and TC = "11" then
+							-- Break condition, do not send a stop bit.
+							TR_NEXT_STATE <= IDLE;
+						else
+							TR_NEXT_STATE <= STOP1; -- No parity check enabled.
+						end if;
+					else
+						TR_NEXT_STATE <= PARITY; -- Parity enabled.
+					end if;
+				else
+					TR_NEXT_STATE <= SHIFTOUT;
+				end if;
+			when PARITY =>
+				if CLK_STRB = '1' then
+					if TDRE = '1' and TC = "11" then
+						-- Break condition, do not send a stop bit.
+						TR_NEXT_STATE <= IDLE;
+					else
+						TR_NEXT_STATE <= STOP1; -- No parity check enabled.
+					end if;
+				else
+					TR_NEXT_STATE <= PARITY;
+				end if;				
+			when STOP1 =>
+				if CLK_STRB = '1' and (WS = "000" or WS = "001" or WS = "100") then
+					TR_NEXT_STATE <= STOP2; -- Two stop bits selected.
+				elsif CLK_STRB = '1' then
+					TR_NEXT_STATE <= IDLE; -- One stop bits selected.
+				else
+					TR_NEXT_STATE <= STOP1;
+				end if;				
+			when STOP2 =>
+				if CLK_STRB = '1' then
+					TR_NEXT_STATE <= IDLE;
+				else
+					TR_NEXT_STATE <= STOP2;
+				end if;				
+		end case;
+	end process TR_STATEDEC;
+end architecture BEHAVIOR;
+
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.bsf b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.bsf
new file mode 100644
index 0000000..f4d66a5
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.bsf
@@ -0,0 +1,95 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 168)
+	(text "dcfifo0" (rect 62 1 105 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 152 25 164)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+		(text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 16 104)(line_width 1))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
+		(text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 16 120)(line_width 1))
+	)
+	(port
+		(pt 0 144)
+		(input)
+		(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 20 138 37 151)(font "Arial" (font_size 8)))
+		(line (pt 0 144)(pt 16 144)(line_width 1))
+	)
+	(port
+		(pt 160 72)
+		(output)
+		(text "wrusedw[9..0]" (rect 0 0 84 14)(font "Arial" (font_size 8)))
+		(text "wrusedw[9..0]" (rect 69 66 132 79)(font "Arial" (font_size 8)))
+		(line (pt 160 72)(pt 144 72)(line_width 3))
+	)
+	(port
+		(pt 160 96)
+		(output)
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 105 90 141 103)(font "Arial" (font_size 8)))
+		(line (pt 160 96)(pt 144 96)(line_width 3))
+	)
+	(drawing
+		(text "8 bits x 1024 words" (rect 63 140 144 152)(font "Arial" ))
+		(line (pt 16 16)(pt 144 16)(line_width 1))
+		(line (pt 144 16)(pt 144 152)(line_width 1))
+		(line (pt 144 152)(pt 16 152)(line_width 1))
+		(line (pt 16 152)(pt 16 16)(line_width 1))
+		(line (pt 16 84)(pt 144 84)(line_width 1))
+		(line (pt 16 132)(pt 144 132)(line_width 1))
+		(line (pt 16 66)(pt 22 72)(line_width 1))
+		(line (pt 22 72)(pt 16 78)(line_width 1))
+		(line (pt 16 114)(pt 22 120)(line_width 1))
+		(line (pt 22 120)(pt 16 126)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.cmp b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.cmp
new file mode 100644
index 0000000..1f8ad52
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.cmp
@@ -0,0 +1,28 @@
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component dcfifo0
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		wrusedw		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.qip b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.qip
new file mode 100644
index 0000000..a22ffe4
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dcfifo0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo0.cmp"]
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.vhd
new file mode 100644
index 0000000..9db22fa
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.vhd
@@ -0,0 +1,202 @@
+-- megafunction wizard: %LPM_FIFO+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: dcfifo_mixed_widths 
+
+-- ============================================================
+-- File Name: dcfifo0.vhd
+-- Megafunction Name(s):
+-- 			dcfifo_mixed_widths
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 222 10/21/2009 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dcfifo0 IS
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		wrusedw		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
+	);
+END dcfifo0;
+
+
+ARCHITECTURE SYN OF dcfifo0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (9 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT dcfifo_mixed_widths
+	GENERIC (
+		intended_device_family		: STRING;
+		lpm_numwords		: NATURAL;
+		lpm_showahead		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL;
+		lpm_widthu		: NATURAL;
+		lpm_widthu_r		: NATURAL;
+		lpm_width_r		: NATURAL;
+		overflow_checking		: STRING;
+		rdsync_delaypipe		: NATURAL;
+		underflow_checking		: STRING;
+		use_eab		: STRING;
+		write_aclr_synch		: STRING;
+		wrsync_delaypipe		: NATURAL
+	);
+	PORT (
+			wrclk	: IN STD_LOGIC ;
+			rdreq	: IN STD_LOGIC ;
+			wrusedw	: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
+			aclr	: IN STD_LOGIC ;
+			rdclk	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			wrreq	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	wrusedw    <= sub_wire0(9 DOWNTO 0);
+	q    <= sub_wire1(31 DOWNTO 0);
+
+	dcfifo_mixed_widths_component : dcfifo_mixed_widths
+	GENERIC MAP (
+		intended_device_family => "Cyclone III",
+		lpm_numwords => 1024,
+		lpm_showahead => "OFF",
+		lpm_type => "dcfifo",
+		lpm_width => 8,
+		lpm_widthu => 10,
+		lpm_widthu_r => 8,
+		lpm_width_r => 32,
+		overflow_checking => "ON",
+		rdsync_delaypipe => 5,
+		underflow_checking => "ON",
+		use_eab => "ON",
+		write_aclr_synch => "OFF",
+		wrsync_delaypipe => 5
+	)
+	PORT MAP (
+		wrclk => wrclk,
+		rdreq => rdreq,
+		aclr => aclr,
+		rdclk => rdclk,
+		wrreq => wrreq,
+		data => data,
+		wrusedw => sub_wire0,
+		q => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "4"
+-- Retrieval info: PRIVATE: Depth NUMERIC "1024"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "8"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "32"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
+-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "32"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
+-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
+-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+-- Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL wrusedw[9..0]
+-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+-- Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_waveforms.html FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak
new file mode 100644
index 0000000..c3ca670
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo0.vhd.bak
@@ -0,0 +1,202 @@
+-- megafunction wizard: %LPM_FIFO+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: dcfifo_mixed_widths 
+
+-- ============================================================
+-- File Name: dcfifo0.vhd
+-- Megafunction Name(s):
+-- 			dcfifo_mixed_widths
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 222 10/21/2009 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dcfifo0 IS
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
+		wrusedw		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+END dcfifo0;
+
+
+ARCHITECTURE SYN OF dcfifo0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+
+
+
+	COMPONENT dcfifo_mixed_widths
+	GENERIC (
+		intended_device_family		: STRING;
+		lpm_numwords		: NATURAL;
+		lpm_showahead		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL;
+		lpm_widthu		: NATURAL;
+		lpm_widthu_r		: NATURAL;
+		lpm_width_r		: NATURAL;
+		overflow_checking		: STRING;
+		rdsync_delaypipe		: NATURAL;
+		underflow_checking		: STRING;
+		use_eab		: STRING;
+		write_aclr_synch		: STRING;
+		wrsync_delaypipe		: NATURAL
+	);
+	PORT (
+			wrclk	: IN STD_LOGIC ;
+			rdreq	: IN STD_LOGIC ;
+			wrusedw	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			aclr	: IN STD_LOGIC ;
+			rdclk	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
+			wrreq	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	wrusedw    <= sub_wire0(4 DOWNTO 0);
+	q    <= sub_wire1(15 DOWNTO 0);
+
+	dcfifo_mixed_widths_component : dcfifo_mixed_widths
+	GENERIC MAP (
+		intended_device_family => "Cyclone III",
+		lpm_numwords => 32,
+		lpm_showahead => "OFF",
+		lpm_type => "dcfifo",
+		lpm_width => 8,
+		lpm_widthu => 5,
+		lpm_widthu_r => 4,
+		lpm_width_r => 16,
+		overflow_checking => "ON",
+		rdsync_delaypipe => 5,
+		underflow_checking => "ON",
+		use_eab => "ON",
+		write_aclr_synch => "OFF",
+		wrsync_delaypipe => 5
+	)
+	PORT MAP (
+		wrclk => wrclk,
+		rdreq => rdreq,
+		aclr => aclr,
+		rdclk => rdclk,
+		wrreq => wrreq,
+		data => data,
+		wrusedw => sub_wire0,
+		q => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "4"
+-- Retrieval info: PRIVATE: Depth NUMERIC "32"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "8"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "16"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "16"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
+-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
+-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+-- Retrieval info: USED_PORT: wrusedw 0 0 5 0 OUTPUT NODEFVAL wrusedw[4..0]
+-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+-- Retrieval info: CONNECT: wrusedw 0 0 5 0 @wrusedw 0 0 5 0
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_waveforms.html FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo0_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.bsf b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.bsf
new file mode 100644
index 0000000..7a4a386
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.bsf
@@ -0,0 +1,95 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 168)
+	(text "dcfifo1" (rect 62 1 105 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 152 25 164)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+		(text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 16 104)(line_width 1))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
+		(text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 16 120)(line_width 1))
+	)
+	(port
+		(pt 0 144)
+		(input)
+		(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 20 138 37 151)(font "Arial" (font_size 8)))
+		(line (pt 0 144)(pt 16 144)(line_width 1))
+	)
+	(port
+		(pt 160 96)
+		(output)
+		(text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[7..0]" (rect 111 90 141 103)(font "Arial" (font_size 8)))
+		(line (pt 160 96)(pt 144 96)(line_width 3))
+	)
+	(port
+		(pt 160 120)
+		(output)
+		(text "rdusedw[9..0]" (rect 0 0 80 14)(font "Arial" (font_size 8)))
+		(text "rdusedw[9..0]" (rect 73 114 135 127)(font "Arial" (font_size 8)))
+		(line (pt 160 120)(pt 144 120)(line_width 3))
+	)
+	(drawing
+		(text "32 bits x 256 words" (rect 63 140 144 152)(font "Arial" ))
+		(line (pt 16 16)(pt 144 16)(line_width 1))
+		(line (pt 144 16)(pt 144 152)(line_width 1))
+		(line (pt 144 152)(pt 16 152)(line_width 1))
+		(line (pt 16 152)(pt 16 16)(line_width 1))
+		(line (pt 16 84)(pt 144 84)(line_width 1))
+		(line (pt 16 132)(pt 144 132)(line_width 1))
+		(line (pt 16 66)(pt 22 72)(line_width 1))
+		(line (pt 22 72)(pt 16 78)(line_width 1))
+		(line (pt 16 114)(pt 22 120)(line_width 1))
+		(line (pt 22 120)(pt 16 126)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.cmp b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.cmp
new file mode 100644
index 0000000..a1b8d55
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.cmp
@@ -0,0 +1,28 @@
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component dcfifo1
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		rdusedw		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
+	);
+end component;
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.qip b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.qip
new file mode 100644
index 0000000..bf1428c
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "dcfifo1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dcfifo1.cmp"]
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.vhd b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.vhd
new file mode 100644
index 0000000..d05dd0a
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.vhd
@@ -0,0 +1,202 @@
+-- megafunction wizard: %LPM_FIFO+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: dcfifo_mixed_widths 
+
+-- ============================================================
+-- File Name: dcfifo1.vhd
+-- Megafunction Name(s):
+-- 			dcfifo_mixed_widths
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 222 10/21/2009 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dcfifo1 IS
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		rdusedw		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
+	);
+END dcfifo1;
+
+
+ARCHITECTURE SYN OF dcfifo1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (9 DOWNTO 0);
+
+
+
+	COMPONENT dcfifo_mixed_widths
+	GENERIC (
+		intended_device_family		: STRING;
+		lpm_numwords		: NATURAL;
+		lpm_showahead		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL;
+		lpm_widthu		: NATURAL;
+		lpm_widthu_r		: NATURAL;
+		lpm_width_r		: NATURAL;
+		overflow_checking		: STRING;
+		rdsync_delaypipe		: NATURAL;
+		underflow_checking		: STRING;
+		use_eab		: STRING;
+		write_aclr_synch		: STRING;
+		wrsync_delaypipe		: NATURAL
+	);
+	PORT (
+			wrclk	: IN STD_LOGIC ;
+			rdreq	: IN STD_LOGIC ;
+			aclr	: IN STD_LOGIC ;
+			rdclk	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			wrreq	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			rdusedw	: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+	rdusedw    <= sub_wire1(9 DOWNTO 0);
+
+	dcfifo_mixed_widths_component : dcfifo_mixed_widths
+	GENERIC MAP (
+		intended_device_family => "Cyclone III",
+		lpm_numwords => 256,
+		lpm_showahead => "OFF",
+		lpm_type => "dcfifo",
+		lpm_width => 32,
+		lpm_widthu => 8,
+		lpm_widthu_r => 10,
+		lpm_width_r => 8,
+		overflow_checking => "ON",
+		rdsync_delaypipe => 5,
+		underflow_checking => "ON",
+		use_eab => "ON",
+		write_aclr_synch => "OFF",
+		wrsync_delaypipe => 5
+	)
+	PORT MAP (
+		wrclk => wrclk,
+		rdreq => rdreq,
+		aclr => aclr,
+		rdclk => rdclk,
+		wrreq => wrreq,
+		data => data,
+		q => sub_wire0,
+		rdusedw => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "4"
+-- Retrieval info: PRIVATE: Depth NUMERIC "256"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "32"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "8"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "10"
+-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
+-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
+-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+-- Retrieval info: USED_PORT: rdusedw 0 0 10 0 OUTPUT NODEFVAL rdusedw[9..0]
+-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+-- Retrieval info: CONNECT: rdusedw 0 0 10 0 @rdusedw 0 0 10 0
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_waveforms.html FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak
new file mode 100644
index 0000000..e7c6ae6
--- /dev/null
+++ b/FPGA_quartus_GE/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak
@@ -0,0 +1,202 @@
+-- megafunction wizard: %LPM_FIFO+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: dcfifo_mixed_widths 
+
+-- ============================================================
+-- File Name: dcfifo1.vhd
+-- Megafunction Name(s):
+-- 			dcfifo_mixed_widths
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 222 10/21/2009 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dcfifo1 IS
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wrusedw		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+END dcfifo1;
+
+
+ARCHITECTURE SYN OF dcfifo1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT dcfifo_mixed_widths
+	GENERIC (
+		intended_device_family		: STRING;
+		lpm_numwords		: NATURAL;
+		lpm_showahead		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL;
+		lpm_widthu		: NATURAL;
+		lpm_widthu_r		: NATURAL;
+		lpm_width_r		: NATURAL;
+		overflow_checking		: STRING;
+		rdsync_delaypipe		: NATURAL;
+		underflow_checking		: STRING;
+		use_eab		: STRING;
+		write_aclr_synch		: STRING;
+		wrsync_delaypipe		: NATURAL
+	);
+	PORT (
+			wrclk	: IN STD_LOGIC ;
+			rdreq	: IN STD_LOGIC ;
+			wrusedw	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+			aclr	: IN STD_LOGIC ;
+			rdclk	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			wrreq	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	wrusedw    <= sub_wire0(3 DOWNTO 0);
+	q    <= sub_wire1(7 DOWNTO 0);
+
+	dcfifo_mixed_widths_component : dcfifo_mixed_widths
+	GENERIC MAP (
+		intended_device_family => "Cyclone III",
+		lpm_numwords => 16,
+		lpm_showahead => "OFF",
+		lpm_type => "dcfifo",
+		lpm_width => 16,
+		lpm_widthu => 4,
+		lpm_widthu_r => 5,
+		lpm_width_r => 8,
+		overflow_checking => "ON",
+		rdsync_delaypipe => 5,
+		underflow_checking => "ON",
+		use_eab => "ON",
+		write_aclr_synch => "OFF",
+		wrsync_delaypipe => 5
+	)
+	PORT MAP (
+		wrclk => wrclk,
+		rdreq => rdreq,
+		aclr => aclr,
+		rdclk => rdclk,
+		wrreq => wrreq,
+		data => data,
+		wrusedw => sub_wire0,
+		q => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "4"
+-- Retrieval info: PRIVATE: Depth NUMERIC "16"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "16"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "1"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "8"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
+-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
+-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+-- Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL wrusedw[3..0]
+-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+-- Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_waveforms.html FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/Interrupt_Handler/interrupt_handler.tdf b/FPGA_quartus_GE/Interrupt_Handler/interrupt_handler.tdf
new file mode 100644
index 0000000..a455469
--- /dev/null
+++ b/FPGA_quartus_GE/Interrupt_Handler/interrupt_handler.tdf
@@ -0,0 +1,478 @@
+TITLE "INTERRUPT HANDLER UND C1287";
+
+-- CREATED BY FREDI ASCHWANDEN
+
+INCLUDE "lpm_bustri_LONG.inc";
+INCLUDE "lpm_bustri_BYT.inc";
+
+
+--  Parameters Statement (optional)
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+
+--  Subdesign Section
+
+SUBDESIGN interrupt_handler
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	MAIN_CLK : INPUT;
+	nFB_WR : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	FB_ADR[31..0] : INPUT;
+	PIC_INT : INPUT;
+	E0_INT : INPUT;
+	DVI_INT : INPUT;
+	nPCI_INTA : INPUT;
+	nPCI_INTB : INPUT;
+	nPCI_INTC : INPUT;
+	nPCI_INTD : INPUT;
+	nMFP_INT : INPUT;
+	nFB_OE : INPUT;
+	DSP_INT : INPUT;
+	VSYNC : INPUT;
+	HSYNC : INPUT;
+	DMA_DRQ : INPUT;
+	nIRQ[7..2] : OUTPUT;
+	INT_HANDLER_TA : OUTPUT;
+	ACP_CONF[31..0] : OUTPUT;
+	TIN0 : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	FB_B[3..0]				:NODE;
+	INT_CTR[31..0]			:DFFE;
+	INT_CTR_CS				:NODE;
+	INT_LATCH[31..0]		:DFF;
+	INT_LATCH_CS			:NODE;
+	INT_CLEAR[31..0]		:DFF;
+	INT_CLEAR_CS			:NODE;
+	INT_IN[31..0]			:NODE;
+	INT_ENA[31..0]			:DFFE;
+	INT_ENA_CS				:NODE;
+	ACP_CONF[31..0]			:DFFE;
+	ACP_CONF_CS				:NODE;
+	PSEUDO_BUS_ERROR		:NODE;
+	UHR_AS					:NODE;
+	UHR_DS					:NODE;
+	RTC_ADR[5..0]			:DFFE;
+	ACHTELSEKUNDEN[2..0]	:DFFE;
+	WERTE[7..0][63..0]		:DFFE;			-- WERTE REGISTER 0-63
+	PIC_INT_SYNC[2..0]		:DFF;
+	INC_SEC					:NODE;
+	INC_MIN					:NODE;
+	INC_STD					:NODE;
+	INC_TAG					:NODE;
+	ANZAHL_TAGE_DES_MONATS[7..0]:NODE;
+	WINTERZEIT				:NODE;
+	SOMMERZEIT				:NODE;
+	INC_MONAT				:NODE;
+	INC_JAHR				:NODE;
+	UPDATE_ON				:NODE;
+	
+BEGIN
+-- BYT SELECT
+	FB_B0 =  FB_SIZE1 & !FB_SIZE0 & !FB_ADR1				-- HWORD
+		# !FB_SIZE1 &  FB_SIZE0 & !FB_ADR1 & !FB_ADR0	-- HHBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+	FB_B1 =  FB_SIZE1 & !FB_SIZE0 & !FB_ADR1				-- HWORD
+		# !FB_SIZE1 &  FB_SIZE0 & !FB_ADR1 &  FB_ADR0	-- HLBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+	FB_B2 =  FB_SIZE1 & !FB_SIZE0 &  FB_ADR1				-- LWORD
+		# !FB_SIZE1 &  FB_SIZE0 &  FB_ADR1 & !FB_ADR0	-- LHBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+	FB_B3 =  FB_SIZE1 & !FB_SIZE0 &  FB_ADR1				-- LWORD
+		# !FB_SIZE1 &  FB_SIZE0 &  FB_ADR1 &  FB_ADR0	-- LLBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+
+-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN
+	INT_CTR[].CLK = MAIN_CLK;
+	INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000";						-- $10000/4
+	INT_CTR[] = FB_AD[];
+	INT_CTR[31..24].ENA = INT_CTR_CS & FB_B0 & !nFB_WR;
+	INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR;
+	INT_CTR[15..8].ENA  = INT_CTR_CS & FB_B2 & !nFB_WR;
+	INT_CTR[7..0].ENA   = INT_CTR_CS & FB_B3 & !nFB_WR;
+-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
+	INT_ENA[].CLK = MAIN_CLK;
+	INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001";						-- $10004/4
+	INT_ENA[] = FB_AD[];
+	INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR;
+	INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR;
+	INT_ENA[15..8].ENA  = INT_ENA_CS & FB_B2 & !nFB_WR;
+	INT_ENA[7..0].ENA   = INT_ENA_CS & FB_B3 & !nFB_WR;
+-- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR
+	INT_CLEAR[].CLK = MAIN_CLK;
+	INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002";						-- $10008/4
+	INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR;
+	INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR;
+	INT_CLEAR[15..8]  = FB_AD[15..8]  & INT_CLEAR_CS & FB_B2 & !nFB_WR;
+	INT_CLEAR[7..0]   = FB_AD[7..0]   & INT_CLEAR_CS & FB_B3 & !nFB_WR;
+-- INTERRUPT LATCH REGISTER READ ONLY
+	INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003";						-- $1000C/4
+-- INTERRUPT
+	!nIRQ2 = HSYNC 						& INT_ENA[26];
+	!nIRQ3 = INT_CTR0 					& INT_ENA[27];
+	!nIRQ4 = VSYNC 						& INT_ENA[28];
+	 nIRQ5 = INT_LATCH[]==H"00000000" 	& INT_ENA[29];
+	!nIRQ6 = !nMFP_INT 					& INT_ENA[30];
+	!nIRQ7 = PSEUDO_BUS_ERROR			& INT_ENA[31];
+
+PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8"			-- SCC
+							#  FB_ADR[19..4]==H"F8E0"			-- VME
+							#  FB_ADR[19..4]==H"F920"			-- PADDLE
+							#  FB_ADR[19..4]==H"F921"			-- PADDLE
+							#  FB_ADR[19..4]==H"F922"			-- PADDLE
+							#  FB_ADR[19..4]==H"FFA8"			-- MFP2
+							#  FB_ADR[19..4]==H"FFA9"			-- MFP2
+							#  FB_ADR[19..4]==H"FFAA"			-- MFP2
+							#  FB_ADR[19..4]==H"FFA8"			-- MFP2
+							#  FB_ADR[19..8]==H"F87"			-- TT SCSI
+							#  FB_ADR[19..4]==H"FFC2"			-- ST UHR
+							#  FB_ADR[19..4]==H"FFC3"			-- ST UHR
+							#  FB_ADR[19..4]==H"F890"			-- DMA SOUND
+							#  FB_ADR[19..4]==H"F891"			-- DMA SOUND
+							#  FB_ADR[19..4]==H"F892");			-- DMA SOUND
+-- IF VIDEO ADR CHANGE
+TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
+
+-- INTERRUPT LATCH
+	INT_LATCH[] = H"FFFFFFFF";
+	INT_LATCH0.CLK = PIC_INT & INT_ENA[0];
+	INT_LATCH1.CLK = E0_INT & INT_ENA[1];
+	INT_LATCH2.CLK = DVI_INT & INT_ENA[2];
+	INT_LATCH3.CLK = !nPCI_INTA & INT_ENA[3];
+	INT_LATCH4.CLK = !nPCI_INTB & INT_ENA[4];
+	INT_LATCH5.CLK = !nPCI_INTC & INT_ENA[5];
+	INT_LATCH6.CLK = !nPCI_INTD & INT_ENA[6];
+	INT_LATCH7.CLK = DSP_INT & INT_ENA[7];
+	INT_LATCH8.CLK = VSYNC & INT_ENA[8];
+	INT_LATCH9.CLK = HSYNC & INT_ENA[9];
+	
+-- INTERRUPT CLEAR
+	INT_LATCH[].CLRN = !INT_CLEAR[];
+	
+-- INT_IN
+	INT_IN0 = PIC_INT;
+	INT_IN1 = E0_INT;
+	INT_IN2 = DVI_INT;
+	INT_IN3 = !nPCI_INTA;
+	INT_IN4 = !nPCI_INTB;
+	INT_IN5 = !nPCI_INTC;
+	INT_IN6 = !nPCI_INTD;
+	INT_IN7 = DSP_INT;
+	INT_IN8 = VSYNC;
+	INT_IN9 = HSYNC;
+	INT_IN[25..10] = H"0";
+	INT_IN26 = HSYNC; 
+	INT_IN27 = INT_CTR0; 
+	INT_IN28 = VSYNC; 
+	INT_IN29 = INT_LATCH[]!=H"00000000";
+	INT_IN30 = !nMFP_INT; 
+	INT_IN31 = DMA_DRQ; 
+--***************************************************************************************
+-- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE 
+	ACP_CONF[].CLK = MAIN_CLK;
+	ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000";		-- $4'0000/4
+	ACP_CONF[] = FB_AD[];
+	ACP_CONF[31..24].ENA = ACP_CONF_CS & FB_B0 & !nFB_WR;
+	ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR;
+	ACP_CONF[15..8].ENA  = ACP_CONF_CS & FB_B2 & !nFB_WR;
+	ACP_CONF[7..0].ENA   = ACP_CONF_CS & FB_B3 & !nFB_WR;
+--***************************************************************************************
+	
+--------------------------------------------------------------	
+-- C1287   0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR
+----------------------------------------------------------
+	RTC_ADR[].CLK = MAIN_CLK;
+	RTC_ADR[] = FB_AD[21..16];
+	UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1;	-- FFFF8961 
+	UHR_DS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B1" & FB_B3;	-- FFFF8963
+	RTC_ADR[].ENA = UHR_AS & !nFB_WR;
+	WERTE[][].CLK = MAIN_CLK;
+	WERTE[7..0][0] = FB_AD[23..16] & RTC_ADR[]==0 & UHR_DS & !nFB_WR;
+	WERTE[7..0][1] = FB_AD[23..16];
+	WERTE[7..0][2] = FB_AD[23..16] & RTC_ADR[]==2 & UHR_DS & !nFB_WR;
+	WERTE[7..0][3] = FB_AD[23..16];
+	WERTE[7..0][4] = FB_AD[23..16] & RTC_ADR[]==4 & UHR_DS & !nFB_WR;
+	WERTE[7..0][5] = FB_AD[23..16];
+	WERTE[7..0][6] = FB_AD[23..16] & RTC_ADR[]==6 & UHR_DS & !nFB_WR;
+	WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR;
+	WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR;
+	WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR;
+	WERTE[7..0][10] = FB_AD[23..16];
+	WERTE[7..0][11] = FB_AD[23..16];
+	WERTE[7..0][12] = FB_AD[23..16];
+	WERTE[7..0][13] = FB_AD[23..16];
+	WERTE[7..0][14] = FB_AD[23..16];
+	WERTE[7..0][15] = FB_AD[23..16];
+	WERTE[7..0][16] = FB_AD[23..16];
+	WERTE[7..0][17] = FB_AD[23..16];
+	WERTE[7..0][18] = FB_AD[23..16];
+	WERTE[7..0][19] = FB_AD[23..16];
+	WERTE[7..0][20] = FB_AD[23..16];
+	WERTE[7..0][21] = FB_AD[23..16];
+	WERTE[7..0][22] = FB_AD[23..16];
+	WERTE[7..0][23] = FB_AD[23..16];
+	WERTE[7..0][24] = FB_AD[23..16];
+	WERTE[7..0][25] = FB_AD[23..16];
+	WERTE[7..0][26] = FB_AD[23..16];
+	WERTE[7..0][27] = FB_AD[23..16];
+	WERTE[7..0][28] = FB_AD[23..16];
+	WERTE[7..0][29] = FB_AD[23..16];
+	WERTE[7..0][30] = FB_AD[23..16];
+	WERTE[7..0][31] = FB_AD[23..16];
+	WERTE[7..0][32] = FB_AD[23..16];
+	WERTE[7..0][33] = FB_AD[23..16];
+	WERTE[7..0][34] = FB_AD[23..16];
+	WERTE[7..0][35] = FB_AD[23..16];
+	WERTE[7..0][36] = FB_AD[23..16];
+	WERTE[7..0][37] = FB_AD[23..16];
+	WERTE[7..0][38] = FB_AD[23..16];
+	WERTE[7..0][39] = FB_AD[23..16];
+	WERTE[7..0][40] = FB_AD[23..16];
+	WERTE[7..0][41] = FB_AD[23..16];
+	WERTE[7..0][42] = FB_AD[23..16];
+	WERTE[7..0][43] = FB_AD[23..16];
+	WERTE[7..0][44] = FB_AD[23..16];
+	WERTE[7..0][45] = FB_AD[23..16];
+	WERTE[7..0][46] = FB_AD[23..16];
+	WERTE[7..0][47] = FB_AD[23..16];
+	WERTE[7..0][48] = FB_AD[23..16];
+	WERTE[7..0][49] = FB_AD[23..16];
+	WERTE[7..0][50] = FB_AD[23..16];
+	WERTE[7..0][51] = FB_AD[23..16];
+	WERTE[7..0][52] = FB_AD[23..16];
+	WERTE[7..0][53] = FB_AD[23..16];
+	WERTE[7..0][54] = FB_AD[23..16];
+	WERTE[7..0][55] = FB_AD[23..16];
+	WERTE[7..0][56] = FB_AD[23..16];
+	WERTE[7..0][57] = FB_AD[23..16];
+	WERTE[7..0][58] = FB_AD[23..16];
+	WERTE[7..0][59] = FB_AD[23..16];
+	WERTE[7..0][60] = FB_AD[23..16];
+	WERTE[7..0][61] = FB_AD[23..16];
+	WERTE[7..0][62] = FB_AD[23..16];
+	WERTE[7..0][63] = FB_AD[23..16];
+	WERTE[][0].ENA = RTC_ADR[]==0 & UHR_DS & !nFB_WR;
+	WERTE[][1].ENA = RTC_ADR[]==1 & UHR_DS & !nFB_WR;
+	WERTE[][2].ENA = RTC_ADR[]==2 & UHR_DS & !nFB_WR;
+	WERTE[][3].ENA = RTC_ADR[]==3 & UHR_DS & !nFB_WR;
+	WERTE[][4].ENA = RTC_ADR[]==4 & UHR_DS & !nFB_WR;
+	WERTE[][5].ENA = RTC_ADR[]==5 & UHR_DS & !nFB_WR;
+	WERTE[][6].ENA = RTC_ADR[]==6 & UHR_DS & !nFB_WR;
+	WERTE[][7].ENA = RTC_ADR[]==7 & UHR_DS & !nFB_WR;
+	WERTE[][8].ENA = RTC_ADR[]==8 & UHR_DS & !nFB_WR;
+	WERTE[][9].ENA = RTC_ADR[]==9 & UHR_DS & !nFB_WR;
+	WERTE[][10].ENA = RTC_ADR[]==10 & UHR_DS & !nFB_WR;
+	WERTE[][11].ENA = RTC_ADR[]==11 & UHR_DS & !nFB_WR;
+	WERTE[][12].ENA = RTC_ADR[]==12 & UHR_DS & !nFB_WR;
+	WERTE[][13].ENA = RTC_ADR[]==13 & UHR_DS & !nFB_WR;
+	WERTE[][14].ENA = RTC_ADR[]==14 & UHR_DS & !nFB_WR;
+	WERTE[][15].ENA = RTC_ADR[]==15 & UHR_DS & !nFB_WR;
+	WERTE[][16].ENA = RTC_ADR[]==16 & UHR_DS & !nFB_WR;
+	WERTE[][17].ENA = RTC_ADR[]==17 & UHR_DS & !nFB_WR;
+	WERTE[][18].ENA = RTC_ADR[]==18 & UHR_DS & !nFB_WR;
+	WERTE[][19].ENA = RTC_ADR[]==19 & UHR_DS & !nFB_WR;
+	WERTE[][20].ENA = RTC_ADR[]==20 & UHR_DS & !nFB_WR;
+	WERTE[][21].ENA = RTC_ADR[]==21 & UHR_DS & !nFB_WR;
+	WERTE[][22].ENA = RTC_ADR[]==22 & UHR_DS & !nFB_WR;
+	WERTE[][23].ENA = RTC_ADR[]==23 & UHR_DS & !nFB_WR;
+	WERTE[][24].ENA = RTC_ADR[]==24 & UHR_DS & !nFB_WR;
+	WERTE[][25].ENA = RTC_ADR[]==25 & UHR_DS & !nFB_WR;
+	WERTE[][26].ENA = RTC_ADR[]==26 & UHR_DS & !nFB_WR;
+	WERTE[][27].ENA = RTC_ADR[]==27 & UHR_DS & !nFB_WR;
+	WERTE[][28].ENA = RTC_ADR[]==28 & UHR_DS & !nFB_WR;
+	WERTE[][29].ENA = RTC_ADR[]==29 & UHR_DS & !nFB_WR;
+	WERTE[][30].ENA = RTC_ADR[]==30 & UHR_DS & !nFB_WR;
+	WERTE[][31].ENA = RTC_ADR[]==31 & UHR_DS & !nFB_WR;
+	WERTE[][32].ENA = RTC_ADR[]==32 & UHR_DS & !nFB_WR;
+	WERTE[][33].ENA = RTC_ADR[]==33 & UHR_DS & !nFB_WR;
+	WERTE[][34].ENA = RTC_ADR[]==34 & UHR_DS & !nFB_WR;
+	WERTE[][35].ENA = RTC_ADR[]==35 & UHR_DS & !nFB_WR;
+	WERTE[][36].ENA = RTC_ADR[]==36 & UHR_DS & !nFB_WR;
+	WERTE[][37].ENA = RTC_ADR[]==37 & UHR_DS & !nFB_WR;
+	WERTE[][38].ENA = RTC_ADR[]==38 & UHR_DS & !nFB_WR;
+	WERTE[][39].ENA = RTC_ADR[]==39 & UHR_DS & !nFB_WR;
+	WERTE[][40].ENA = RTC_ADR[]==40 & UHR_DS & !nFB_WR;
+	WERTE[][41].ENA = RTC_ADR[]==41 & UHR_DS & !nFB_WR;
+	WERTE[][42].ENA = RTC_ADR[]==42 & UHR_DS & !nFB_WR;
+	WERTE[][43].ENA = RTC_ADR[]==43 & UHR_DS & !nFB_WR;
+	WERTE[][44].ENA = RTC_ADR[]==44 & UHR_DS & !nFB_WR;
+	WERTE[][45].ENA = RTC_ADR[]==45 & UHR_DS & !nFB_WR;
+	WERTE[][46].ENA = RTC_ADR[]==46 & UHR_DS & !nFB_WR;
+	WERTE[][47].ENA = RTC_ADR[]==47 & UHR_DS & !nFB_WR;
+	WERTE[][48].ENA = RTC_ADR[]==48 & UHR_DS & !nFB_WR;
+	WERTE[][49].ENA = RTC_ADR[]==49 & UHR_DS & !nFB_WR;
+	WERTE[][50].ENA = RTC_ADR[]==50 & UHR_DS & !nFB_WR;
+	WERTE[][51].ENA = RTC_ADR[]==51 & UHR_DS & !nFB_WR;
+	WERTE[][52].ENA = RTC_ADR[]==52 & UHR_DS & !nFB_WR;
+	WERTE[][53].ENA = RTC_ADR[]==53 & UHR_DS & !nFB_WR;
+	WERTE[][54].ENA = RTC_ADR[]==54 & UHR_DS & !nFB_WR;
+	WERTE[][55].ENA = RTC_ADR[]==55 & UHR_DS & !nFB_WR;
+	WERTE[][56].ENA = RTC_ADR[]==56 & UHR_DS & !nFB_WR;
+	WERTE[][57].ENA = RTC_ADR[]==57 & UHR_DS & !nFB_WR;
+	WERTE[][58].ENA = RTC_ADR[]==58 & UHR_DS & !nFB_WR;
+	WERTE[][59].ENA = RTC_ADR[]==59 & UHR_DS & !nFB_WR;
+	WERTE[][60].ENA = RTC_ADR[]==60 & UHR_DS & !nFB_WR;
+	WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR;
+	WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR;
+	WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR;
+	PIC_INT_SYNC[].CLK = MAIN_CLK;	PIC_INT_SYNC[0] = PIC_INT;
+	PIC_INT_SYNC[1] = PIC_INT_SYNC[0];
+	PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0];
+	UPDATE_ON = !WERTE[7][11];		
+	WERTE[6][10].CLRN = GND;	-- KEIN UIP
+	UPDATE_ON = !WERTE[7][11];	-- UPDATE ON OFF
+	WERTE[2][11] = VCC;	-- IMMER BINARY
+	WERTE[1][11] = VCC;	-- IMMER 24H FORMAT
+	WERTE[0][11] = VCC;	-- IMMER SOMMERZEITKORREKTUR
+	WERTE[7][13] = VCC;	-- IMMER RICHTIG
+-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG)
+	SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4  & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL
+	WERTE[0][13] = SOMMERZEIT;
+	WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT);
+	WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13];  --LETZTER SONNTAG IM OKTOBER
+-- ACHTELSEKUNDEN
+	ACHTELSEKUNDEN[].CLK = MAIN_CLK;
+	ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1;
+	ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON;
+-- SEKUNDEN
+	INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON;   
+	WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);			-- SEKUNDEN ZÄHLEN BIS 59
+	WERTE[][0].ENA  = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);	
+-- MINUTEN
+	INC_MIN = INC_SEC & WERTE[][0]==59;							--  
+	WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);			-- MINUTEN ZÄHLEN BIS 59
+	WERTE[][2].ENA  = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);								--  
+-- STUNDEN
+	INC_STD = INC_MIN & WERTE[][2]==59;							  
+	WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);  -- STUNDEN ZÄHLEN BIS 23
+	WERTE[][4].ENA  = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);		-- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT	 
+-- WOCHENTAG UND TAG 
+	INC_TAG = INC_STD & WERTE[][2]==23;						
+	WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR)				-- WOCHENTAG ZÄHLEN BIS 7
+			   # 1              & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);			-- DANN BEI 1 WEITER
+	WERTE[][6].ENA  = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);
+	ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12)
+							 # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11)  
+							 # 29 &  WERTE[][8]==2 & WERTE[1..0][9]==0  
+							 # 28 &  WERTE[][8]==2 & WERTE[1..0][9]!=0;  
+	WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR)  	-- TAG ZÄHLEN BIS MONATSENDE
+			   # 1              & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR);		-- DANN BEI 1 WEITER
+	WERTE[][7].ENA  = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR);								--  
+-- MONATE
+	INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[];							--  
+	WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR)					-- MONATE ZÄHLEN BIS 12
+			   # 1              & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);					-- DANN BEI 1 WEITER
+	WERTE[][8].ENA  = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);
+-- JAHR		   
+	INC_JAHR = INC_MONAT & WERTE[][8]==12;							--  
+	WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);					-- JAHRE ZÄHLEN BIS 99
+	WERTE[][9].ENA  = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);
+-- TRISTATE OUTPUT
+
+	FB_AD[31..24] = lpm_bustri_BYT(
+					INT_CTR_CS   & INT_CTR[31..24] 
+				  #	INT_ENA_CS   & INT_ENA[31..24]
+				  #	INT_LATCH_CS & INT_LATCH[31..24]
+				  # INT_CLEAR_CS & INT_IN[31..24]
+				  # ACP_CONF_CS  & ACP_CONF[31..24]
+				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+	FB_AD[23..16] = lpm_bustri_BYT(
+				   WERTE[][0] & RTC_ADR[]==0 & UHR_DS 
+				 # WERTE[][1] & RTC_ADR[]==1 & UHR_DS
+				 # WERTE[][2] & RTC_ADR[]==2 & UHR_DS
+				 # WERTE[][3] & RTC_ADR[]==3 & UHR_DS
+				 # WERTE[][4] & RTC_ADR[]==4 & UHR_DS
+				 # WERTE[][5] & RTC_ADR[]==5 & UHR_DS
+				 # WERTE[][6] & RTC_ADR[]==6 & UHR_DS
+				 # WERTE[][7] & RTC_ADR[]==7 & UHR_DS
+				 # WERTE[][8] & RTC_ADR[]==8 & UHR_DS
+				 # WERTE[][9] & RTC_ADR[]==9 & UHR_DS
+				 # WERTE[][10] & RTC_ADR[]==10 & UHR_DS
+				 # WERTE[][11] & RTC_ADR[]==11 & UHR_DS
+				 # WERTE[][12] & RTC_ADR[]==12 & UHR_DS
+				 # WERTE[][13] & RTC_ADR[]==13 & UHR_DS
+				 # WERTE[][14] & RTC_ADR[]==14 & UHR_DS
+				 # WERTE[][15] & RTC_ADR[]==15 & UHR_DS
+				 # WERTE[][16] & RTC_ADR[]==16 & UHR_DS
+				 # WERTE[][17] & RTC_ADR[]==17 & UHR_DS
+				 # WERTE[][18] & RTC_ADR[]==18 & UHR_DS
+				 # WERTE[][19] & RTC_ADR[]==19 & UHR_DS
+				 # WERTE[][20] & RTC_ADR[]==20 & UHR_DS
+				 # WERTE[][21] & RTC_ADR[]==21 & UHR_DS
+				 # WERTE[][22] & RTC_ADR[]==22 & UHR_DS
+				 # WERTE[][23] & RTC_ADR[]==23 & UHR_DS
+				 # WERTE[][24] & RTC_ADR[]==24 & UHR_DS
+				 # WERTE[][25] & RTC_ADR[]==25 & UHR_DS
+				 # WERTE[][26] & RTC_ADR[]==26 & UHR_DS
+				 # WERTE[][27] & RTC_ADR[]==27 & UHR_DS
+				 # WERTE[][28] & RTC_ADR[]==28 & UHR_DS
+				 # WERTE[][29] & RTC_ADR[]==29 & UHR_DS
+				 # WERTE[][30] & RTC_ADR[]==30 & UHR_DS
+				 # WERTE[][31] & RTC_ADR[]==31 & UHR_DS
+				 # WERTE[][32] & RTC_ADR[]==32 & UHR_DS
+				 # WERTE[][33] & RTC_ADR[]==33 & UHR_DS
+				 # WERTE[][34] & RTC_ADR[]==34 & UHR_DS
+				 # WERTE[][35] & RTC_ADR[]==35 & UHR_DS
+				 # WERTE[][36] & RTC_ADR[]==36 & UHR_DS
+				 # WERTE[][37] & RTC_ADR[]==37 & UHR_DS
+				 # WERTE[][38] & RTC_ADR[]==38 & UHR_DS
+				 # WERTE[][39] & RTC_ADR[]==39 & UHR_DS
+				 # WERTE[][40] & RTC_ADR[]==40 & UHR_DS
+				 # WERTE[][41] & RTC_ADR[]==41 & UHR_DS
+				 # WERTE[][42] & RTC_ADR[]==42 & UHR_DS
+				 # WERTE[][43] & RTC_ADR[]==43 & UHR_DS
+				 # WERTE[][44] & RTC_ADR[]==44 & UHR_DS
+				 # WERTE[][45] & RTC_ADR[]==45 & UHR_DS
+				 # WERTE[][46] & RTC_ADR[]==46 & UHR_DS
+				 # WERTE[][47] & RTC_ADR[]==47 & UHR_DS
+				 # WERTE[][48] & RTC_ADR[]==48 & UHR_DS
+				 # WERTE[][49] & RTC_ADR[]==49 & UHR_DS
+				 # WERTE[][50] & RTC_ADR[]==50 & UHR_DS
+				 # WERTE[][51] & RTC_ADR[]==51 & UHR_DS
+				 # WERTE[][52] & RTC_ADR[]==52 & UHR_DS
+				 # WERTE[][53] & RTC_ADR[]==53 & UHR_DS
+				 # WERTE[][54] & RTC_ADR[]==54 & UHR_DS
+				 # WERTE[][55] & RTC_ADR[]==55 & UHR_DS
+				 # WERTE[][56] & RTC_ADR[]==56 & UHR_DS
+				 # WERTE[][57] & RTC_ADR[]==57 & UHR_DS
+				 # WERTE[][58] & RTC_ADR[]==58 & UHR_DS
+				 # WERTE[][59] & RTC_ADR[]==59 & UHR_DS
+				 # WERTE[][60] & RTC_ADR[]==60 & UHR_DS
+				 # WERTE[][61] & RTC_ADR[]==61 & UHR_DS
+				 # WERTE[][62] & RTC_ADR[]==62 & UHR_DS
+				 # WERTE[][63] & RTC_ADR[]==63 & UHR_DS
+				 # (0,RTC_ADR[])			   & UHR_AS
+				 # INT_CTR_CS   & INT_CTR[23..16] 
+				 # INT_ENA_CS   & INT_ENA[23..16]
+				 # INT_LATCH_CS & INT_LATCH[23..16]
+				 # INT_CLEAR_CS & INT_IN[23..16]
+				 # ACP_CONF_CS  & ACP_CONF[23..16]
+				  ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+	FB_AD[15..8] = lpm_bustri_BYT(
+					INT_CTR_CS   & INT_CTR[15..8] 
+				  #	INT_ENA_CS   & INT_ENA[15..8]
+				  #	INT_LATCH_CS & INT_LATCH[15..8]
+				  # INT_CLEAR_CS & INT_IN[15..8]
+				  # ACP_CONF_CS  & ACP_CONF[15..8]
+				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+	FB_AD[7..0] = lpm_bustri_BYT(
+					INT_CTR_CS   & INT_CTR[7..0] 
+				  #	INT_ENA_CS   & INT_ENA[7..0]
+				  #	INT_LATCH_CS & INT_LATCH[7..0]
+				  # INT_CLEAR_CS & INT_IN[7..0]
+				  # ACP_CONF_CS  & ACP_CONF[7..0]
+				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+
+	INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS;
+END;
+
+
diff --git a/FPGA_quartus_GE/Interrupt_Handler/interrupt_handler.v b/FPGA_quartus_GE/Interrupt_Handler/interrupt_handler.v
new file mode 100644
index 0000000..e24f0a8
--- /dev/null
+++ b/FPGA_quartus_GE/Interrupt_Handler/interrupt_handler.v
@@ -0,0 +1,3615 @@
+// Xilinx XPort Language Converter, Version 4.1 (110)
+// 
+// AHDL    Design Source: interrupt_handler.tdf
+// Verilog Design Output: interrupt_handler.v
+// Created 23-Feb-2014 10:34 AM
+//
+// Copyright (c) 2014, Xilinx, Inc.  All Rights Reserved.
+// Xilinx Inc makes no warranty, expressed or implied, with respect to
+// the operation and/or functionality of the converted output files.
+// 
+
+// INTERRUPT HANDLER UND C1287
+
+
+//  CREATED BY FREDI ASCHWANDEN
+//   Parameters Statement (optional)
+//  {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+//  {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+//   Subdesign Section
+module interrupt_handler(MAIN_CLK, nFB_WR, nFB_CS1, nFB_CS2, FB_SIZE0,
+      FB_SIZE1, FB_ADR, PIC_INT, E0_INT, DVI_INT, nPCI_INTA, nPCI_INTB,
+      nPCI_INTC, nPCI_INTD, nMFP_INT, nFB_OE, DSP_INT, VSYNC, HSYNC, DMA_DRQ,
+      nIRQ, INT_HANDLER_TA, ACP_CONF, TIN0, FB_AD, nRST);
+
+//  {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+//  {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+   input MAIN_CLK, nFB_WR, nFB_CS1, nFB_CS2, FB_SIZE0, FB_SIZE1;
+   input [31:0] FB_ADR;
+   input PIC_INT, E0_INT, DVI_INT, nPCI_INTA, nPCI_INTB, nPCI_INTC, nPCI_INTD,
+	 nMFP_INT, nFB_OE, DSP_INT, VSYNC, HSYNC, DMA_DRQ;
+   output [7:2] nIRQ;
+   output INT_HANDLER_TA;
+   output [31:0] ACP_CONF;
+   output TIN0;
+   inout [31:0] FB_AD;
+	 input nRST;
+
+//  WERTE REGISTER 0-63
+   wire [3:0] FB_B;
+   wire [31:0] INT_CTR;
+   wire [31:0] INT_CTR_d;
+   wire INT_CTR_CS;
+   wire [31:0] INT_LATCH;
+   wire [31:0] INT_LATCH_d;
+	 reg [31:0] INT_LATCH_d_prev;
+   wire [31:0] INT_LATCH_clk;
+   wire INT_LATCH31_clrn, INT_LATCH30_clrn, INT_LATCH29_clrn, INT_LATCH28_clrn,
+	 INT_LATCH27_clrn, INT_LATCH26_clrn, INT_LATCH25_clrn,
+	 INT_LATCH24_clrn, INT_LATCH23_clrn, INT_LATCH22_clrn,
+	 INT_LATCH21_clrn, INT_LATCH20_clrn, INT_LATCH19_clrn,
+	 INT_LATCH18_clrn, INT_LATCH17_clrn, INT_LATCH16_clrn,
+	 INT_LATCH15_clrn, INT_LATCH14_clrn, INT_LATCH13_clrn,
+	 INT_LATCH12_clrn, INT_LATCH11_clrn, INT_LATCH10_clrn, INT_LATCH9_clrn,
+	 INT_LATCH8_clrn, INT_LATCH7_clrn, INT_LATCH6_clrn, INT_LATCH5_clrn,
+	 INT_LATCH4_clrn, INT_LATCH3_clrn, INT_LATCH2_clrn, INT_LATCH1_clrn,
+	 INT_LATCH0_clrn, INT_LATCH_CS; 
+   wire [31:0] INT_CLEAR;
+   wire [31:0] INT_CLEAR_d;
+   wire INT_CLEAR_CS;
+   wire [31:0] INT_IN;
+   wire [31:0] INT_ENA;
+   wire [31:0] INT_ENA_d;
+   wire INT_ENA_CS;
+   wire [31:0] ACP_CONF_d;
+   wire ACP_CONF_CS, PSEUDO_BUS_ERROR, UHR_AS, UHR_DS;
+   wire [5:0] RTC_ADR;
+   wire [5:0] RTC_ADR_d;
+   wire [2:0] ACHTELSEKUNDEN;
+   wire [2:0] ACHTELSEKUNDEN_d;
+   wire [63:0] WERTE7_;
+   wire [63:0] WERTE7__d;
+   wire WERTE7_13_ena, WERTE7_9_ena, WERTE7_8_ena, WERTE7_7_ena, WERTE7_6_ena,
+	 WERTE7_4_ena, WERTE7_2_ena, WERTE7_0_ena;
+   wire [63:0] WERTE6_;
+   wire [63:0] WERTE6__d;
+   wire WERTE6_10_clrn, WERTE6_13_ena, WERTE6_9_ena, WERTE6_8_ena,
+	 WERTE6_7_ena, WERTE6_6_ena, WERTE6_4_ena, WERTE6_2_ena, WERTE6_0_ena;
+   wire [63:0] WERTE5_;
+   wire [63:0] WERTE5__d;
+   wire WERTE5_13_ena, WERTE5_9_ena, WERTE5_8_ena, WERTE5_7_ena, WERTE5_6_ena,
+	 WERTE5_4_ena, WERTE5_2_ena, WERTE5_0_ena;
+   wire [63:0] WERTE4_;
+   wire [63:0] WERTE4__d;
+   wire WERTE4_13_ena, WERTE4_9_ena, WERTE4_8_ena, WERTE4_7_ena, WERTE4_6_ena,
+	 WERTE4_4_ena, WERTE4_2_ena, WERTE4_0_ena;
+   wire [63:0] WERTE3_;
+   wire [63:0] WERTE3__d;
+   wire WERTE3_13_ena, WERTE3_9_ena, WERTE3_8_ena, WERTE3_7_ena, WERTE3_6_ena,
+	 WERTE3_4_ena, WERTE3_2_ena, WERTE3_0_ena;
+   wire [63:0] WERTE2_;
+   wire [63:0] WERTE2__d;
+   wire WERTE2_13_ena, WERTE2_9_ena, WERTE2_8_ena, WERTE2_7_ena, WERTE2_6_ena,
+	 WERTE2_4_ena, WERTE2_2_ena, WERTE2_0_ena;
+   wire [63:0] WERTE1_;
+   wire [63:0] WERTE1__d;
+   wire WERTE1_13_ena, WERTE1_9_ena, WERTE1_8_ena, WERTE1_7_ena, WERTE1_6_ena,
+	 WERTE1_4_ena, WERTE1_2_ena, WERTE1_0_ena;
+   wire [63:0] WERTE0_;
+   wire [63:0] WERTE0__d;
+   wire WERTE0_13_ena, WERTE0_9_ena, WERTE0_8_ena, WERTE0_7_ena, WERTE0_6_ena,
+	 WERTE0_4_ena, WERTE0_2_ena, WERTE0_0_ena;
+   wire [2:0] PIC_INT_SYNC;
+   wire [2:0] PIC_INT_SYNC_d;
+   wire INC_SEC, INC_MIN, INC_STD, INC_TAG;
+   wire [7:0] ANZAHL_TAGE_DES_MONATS;
+   wire WINTERZEIT, SOMMERZEIT, INC_MONAT, INC_JAHR, UPDATE_ON, gnd, vcc;
+   wire [7:0] u0_data;
+   wire u0_enabledt;
+   wire [7:0] u0_tridata;
+   wire [7:0] u1_data;
+   wire u1_enabledt;
+   wire [7:0] u1_tridata;
+   wire [7:0] u2_data;
+   wire u2_enabledt;
+   wire [7:0] u2_tridata;
+   wire [7:0] u3_data;
+   wire u3_enabledt;
+   wire [7:0] u3_tridata;
+   wire UPDATE_ON_1, UPDATE_ON_2, WERTE0_0_ena_1, WERTE0_0_ena_2,
+	 WERTE0_2_ena_1, WERTE0_2_ena_2, WERTE0_4_ena_1, WERTE0_4_ena_2,
+	 WERTE0_6_ena_1, WERTE0_6_ena_2, WERTE0_7_ena_1, WERTE0_7_ena_2,
+	 WERTE0_8_ena_1, WERTE0_8_ena_2, WERTE0_9_ena_1, WERTE0_9_ena_2,
+	 WERTE0_13_ena_1, WERTE0_13_ena_2, WERTE0_0_d_1, WERTE0_0_d_2,
+	 WERTE0_2_d_1, WERTE0_2_d_2, WERTE0_4_d_1, WERTE0_4_d_2, WERTE0_6_d_1,
+	 WERTE0_6_d_2, WERTE0_7_d_1, WERTE0_7_d_2, WERTE0_8_d_1, WERTE0_8_d_2,
+	 WERTE0_9_d_1, WERTE0_9_d_2, WERTE0_11_d_1, WERTE0_11_d_2,
+	 WERTE0_13_d_1, WERTE0_13_d_2, WERTE1_0_ena_1, WERTE1_0_ena_2,
+	 WERTE1_2_ena_1, WERTE1_2_ena_2, WERTE1_4_ena_1, WERTE1_4_ena_2,
+	 WERTE1_6_ena_1, WERTE1_6_ena_2, WERTE1_7_ena_1, WERTE1_7_ena_2,
+	 WERTE1_8_ena_1, WERTE1_8_ena_2, WERTE1_9_ena_1, WERTE1_9_ena_2,
+	 WERTE1_0_d_1, WERTE1_0_d_2, WERTE1_2_d_1, WERTE1_2_d_2, WERTE1_4_d_1,
+	 WERTE1_4_d_2, WERTE1_6_d_1, WERTE1_6_d_2, WERTE1_7_d_1, WERTE1_7_d_2,
+	 WERTE1_8_d_1, WERTE1_8_d_2, WERTE1_9_d_1, WERTE1_9_d_2, WERTE1_11_d_1,
+	 WERTE1_11_d_2, WERTE2_0_ena_1, WERTE2_0_ena_2, WERTE2_2_ena_1,
+	 WERTE2_2_ena_2, WERTE2_4_ena_1, WERTE2_4_ena_2, WERTE2_6_ena_1,
+	 WERTE2_6_ena_2, WERTE2_7_ena_1, WERTE2_7_ena_2, WERTE2_8_ena_1,
+	 WERTE2_8_ena_2, WERTE2_9_ena_1, WERTE2_9_ena_2, WERTE2_0_d_1,
+	 WERTE2_0_d_2, WERTE2_2_d_1, WERTE2_2_d_2, WERTE2_4_d_1, WERTE2_4_d_2,
+	 WERTE2_6_d_1, WERTE2_6_d_2, WERTE2_7_d_1, WERTE2_7_d_2, WERTE2_8_d_1,
+	 WERTE2_8_d_2, WERTE2_9_d_1, WERTE2_9_d_2, WERTE2_11_d_1,
+	 WERTE2_11_d_2, WERTE3_0_ena_1, WERTE3_0_ena_2, WERTE3_2_ena_1,
+	 WERTE3_2_ena_2, WERTE3_4_ena_1, WERTE3_4_ena_2, WERTE3_6_ena_1,
+	 WERTE3_6_ena_2, WERTE3_7_ena_1, WERTE3_7_ena_2, WERTE3_8_ena_1,
+	 WERTE3_8_ena_2, WERTE3_9_ena_1, WERTE3_9_ena_2, WERTE3_0_d_1,
+	 WERTE3_0_d_2, WERTE3_2_d_1, WERTE3_2_d_2, WERTE3_4_d_1, WERTE3_4_d_2,
+	 WERTE3_6_d_1, WERTE3_6_d_2, WERTE3_7_d_1, WERTE3_7_d_2, WERTE3_8_d_1,
+	 WERTE3_8_d_2, WERTE3_9_d_1, WERTE3_9_d_2, WERTE4_0_ena_1,
+	 WERTE4_0_ena_2, WERTE4_2_ena_1, WERTE4_2_ena_2, WERTE4_4_ena_1,
+	 WERTE4_4_ena_2, WERTE4_6_ena_1, WERTE4_6_ena_2, WERTE4_7_ena_1,
+	 WERTE4_7_ena_2, WERTE4_8_ena_1, WERTE4_8_ena_2, WERTE4_9_ena_1,
+	 WERTE4_9_ena_2, WERTE4_0_d_1, WERTE4_0_d_2, WERTE4_2_d_1,
+	 WERTE4_2_d_2, WERTE4_4_d_1, WERTE4_4_d_2, WERTE4_6_d_1, WERTE4_6_d_2,
+	 WERTE4_7_d_1, WERTE4_7_d_2, WERTE4_8_d_1, WERTE4_8_d_2, WERTE4_9_d_1,
+	 WERTE4_9_d_2, WERTE5_0_ena_1, WERTE5_0_ena_2, WERTE5_2_ena_1,
+	 WERTE5_2_ena_2, WERTE5_4_ena_1, WERTE5_4_ena_2, WERTE5_6_ena_1,
+	 WERTE5_6_ena_2, WERTE5_7_ena_1, WERTE5_7_ena_2, WERTE5_8_ena_1,
+	 WERTE5_8_ena_2, WERTE5_9_ena_1, WERTE5_9_ena_2, WERTE5_0_d_1,
+	 WERTE5_0_d_2, WERTE5_2_d_1, WERTE5_2_d_2, WERTE5_4_d_1, WERTE5_4_d_2,
+	 WERTE5_6_d_1, WERTE5_6_d_2, WERTE5_7_d_1, WERTE5_7_d_2, WERTE5_8_d_1,
+	 WERTE5_8_d_2, WERTE5_9_d_1, WERTE5_9_d_2, WERTE6_0_ena_1,
+	 WERTE6_0_ena_2, WERTE6_2_ena_1, WERTE6_2_ena_2, WERTE6_4_ena_1,
+	 WERTE6_4_ena_2, WERTE6_6_ena_1, WERTE6_6_ena_2, WERTE6_7_ena_1,
+	 WERTE6_7_ena_2, WERTE6_8_ena_1, WERTE6_8_ena_2, WERTE6_9_ena_1,
+	 WERTE6_9_ena_2, WERTE6_0_d_1, WERTE6_0_d_2, WERTE6_2_d_1,
+	 WERTE6_2_d_2, WERTE6_4_d_1, WERTE6_4_d_2, WERTE6_6_d_1, WERTE6_6_d_2,
+	 WERTE6_7_d_1, WERTE6_7_d_2, WERTE6_8_d_1, WERTE6_8_d_2, WERTE6_9_d_1,
+	 WERTE6_9_d_2, WERTE7_0_ena_1, WERTE7_0_ena_2, WERTE7_2_ena_1,
+	 WERTE7_2_ena_2, WERTE7_4_ena_1, WERTE7_4_ena_2, WERTE7_6_ena_1,
+	 WERTE7_6_ena_2, WERTE7_7_ena_1, WERTE7_7_ena_2, WERTE7_8_ena_1,
+	 WERTE7_8_ena_2, WERTE7_9_ena_1, WERTE7_9_ena_2, WERTE7_0_d_1,
+	 WERTE7_0_d_2, WERTE7_2_d_1, WERTE7_2_d_2, WERTE7_4_d_1, WERTE7_4_d_2,
+	 WERTE7_6_d_1, WERTE7_6_d_2, WERTE7_7_d_1, WERTE7_7_d_2, WERTE7_8_d_1,
+	 WERTE7_8_d_2, WERTE7_9_d_1, WERTE7_9_d_2, WERTE7_13_d_1,
+	 WERTE7_13_d_2, ACHTELSEKUNDEN0_ena_ctrl, ACHTELSEKUNDEN0_clk_ctrl,
+	 PIC_INT_SYNC0_clk_ctrl, WERTE0_63_ena_ctrl, WERTE0_62_ena_ctrl,
+	 WERTE0_61_ena_ctrl, WERTE0_60_ena_ctrl, WERTE0_59_ena_ctrl,
+	 WERTE0_58_ena_ctrl, WERTE0_57_ena_ctrl, WERTE0_56_ena_ctrl,
+	 WERTE0_55_ena_ctrl, WERTE0_54_ena_ctrl, WERTE0_53_ena_ctrl,
+	 WERTE0_52_ena_ctrl, WERTE0_51_ena_ctrl, WERTE0_50_ena_ctrl,
+	 WERTE0_49_ena_ctrl, WERTE0_48_ena_ctrl, WERTE0_47_ena_ctrl,
+	 WERTE0_46_ena_ctrl, WERTE0_45_ena_ctrl, WERTE0_44_ena_ctrl,
+	 WERTE0_43_ena_ctrl, WERTE0_42_ena_ctrl, WERTE0_41_ena_ctrl,
+	 WERTE0_40_ena_ctrl, WERTE0_39_ena_ctrl, WERTE0_38_ena_ctrl,
+	 WERTE0_37_ena_ctrl, WERTE0_36_ena_ctrl, WERTE0_35_ena_ctrl,
+	 WERTE0_34_ena_ctrl, WERTE0_33_ena_ctrl, WERTE0_32_ena_ctrl,
+	 WERTE0_31_ena_ctrl, WERTE0_30_ena_ctrl, WERTE0_29_ena_ctrl,
+	 WERTE0_28_ena_ctrl, WERTE0_27_ena_ctrl, WERTE0_26_ena_ctrl,
+	 WERTE0_25_ena_ctrl, WERTE0_24_ena_ctrl, WERTE0_23_ena_ctrl,
+	 WERTE0_22_ena_ctrl, WERTE0_21_ena_ctrl, WERTE0_20_ena_ctrl,
+	 WERTE0_19_ena_ctrl, WERTE0_18_ena_ctrl, WERTE0_17_ena_ctrl,
+	 WERTE0_16_ena_ctrl, WERTE0_15_ena_ctrl, WERTE0_14_ena_ctrl,
+	 WERTE0_12_ena_ctrl, WERTE0_11_ena_ctrl, WERTE0_10_ena_ctrl,
+	 WERTE0_5_ena_ctrl, WERTE0_3_ena_ctrl, WERTE0_1_ena_ctrl,
+	 WERTE0_0_clk_ctrl, WERTE1_0_clk_ctrl, WERTE2_0_clk_ctrl,
+	 WERTE3_0_clk_ctrl, WERTE4_0_clk_ctrl, WERTE5_0_clk_ctrl,
+	 WERTE6_0_clk_ctrl, WERTE7_0_clk_ctrl, RTC_ADR0_ena_ctrl,
+	 RTC_ADR0_clk_ctrl, ACP_CONF0_ena_ctrl, ACP_CONF8_ena_ctrl,
+	 ACP_CONF16_ena_ctrl, ACP_CONF24_ena_ctrl, ACP_CONF0_clk_ctrl,
+	 INT_CLEAR0_clk_ctrl, INT_ENA0_ena_ctrl, INT_ENA8_ena_ctrl,
+	 INT_ENA16_ena_ctrl, INT_ENA24_ena_ctrl, INT_ENA0_clk_ctrl,
+	 INT_CTR0_ena_ctrl, INT_CTR8_ena_ctrl, INT_CTR16_ena_ctrl,
+	 INT_CTR24_ena_ctrl, INT_CTR0_clk_ctrl, INT_LATCH9_clk_1,
+	 INT_LATCH8_clk_1, INT_LATCH7_clk_1, INT_LATCH6_clk_1,
+	 INT_LATCH5_clk_1, INT_LATCH4_clk_1, INT_LATCH3_clk_1,
+	 INT_LATCH2_clk_1, INT_LATCH1_clk_1, INT_LATCH0_clk_1;
+   reg [31:0] INT_CTR_q;
+   reg [31:0] INT_LATCH_q;
+   reg [31:0] INT_CLEAR_q;
+   reg [31:0] INT_ENA_q;
+   reg [31:0] ACP_CONF_q;
+   reg [5:0] RTC_ADR_q;
+   reg [2:0] ACHTELSEKUNDEN_q;
+   reg [63:0] WERTE7__q;
+   reg [63:0] WERTE6__q;
+   reg [63:0] WERTE5__q;
+   reg [63:0] WERTE4__q;
+   reg [63:0] WERTE3__q;
+   reg [63:0] WERTE2__q;
+   reg [63:0] WERTE1__q;
+   reg [63:0] WERTE0__q;
+   reg [2:0] PIC_INT_SYNC_q;
+
+
+// Sub Module Section
+   lpm_bustri_BYT  u0 (.data(u0_data), .enabledt(u0_enabledt),
+	 .tridata(u0_tridata));
+
+   lpm_bustri_BYT  u1 (.data(u1_data), .enabledt(u1_enabledt),
+	 .tridata(u1_tridata));
+
+   lpm_bustri_BYT  u2 (.data(u2_data), .enabledt(u2_enabledt),
+	 .tridata(u2_tridata));
+
+   lpm_bustri_BYT  u3 (.data(u3_data), .enabledt(u3_enabledt),
+	 .tridata(u3_tridata));
+
+
+   assign ACP_CONF[31:24] = ACP_CONF_q[31:24];
+   always @(posedge ACP_CONF0_clk_ctrl)
+      if (ACP_CONF24_ena_ctrl)
+	 {ACP_CONF_q[31], ACP_CONF_q[30], ACP_CONF_q[29], ACP_CONF_q[28],
+	       ACP_CONF_q[27], ACP_CONF_q[26], ACP_CONF_q[25], ACP_CONF_q[24]}
+	       <= ACP_CONF_d[31:24];
+
+   assign ACP_CONF[23:16] = ACP_CONF_q[23:16];
+   always @(posedge ACP_CONF0_clk_ctrl)
+      if (ACP_CONF16_ena_ctrl)
+	 {ACP_CONF_q[23], ACP_CONF_q[22], ACP_CONF_q[21], ACP_CONF_q[20],
+	       ACP_CONF_q[19], ACP_CONF_q[18], ACP_CONF_q[17], ACP_CONF_q[16]}
+	       <= ACP_CONF_d[23:16];
+
+   assign ACP_CONF[15:8] = ACP_CONF_q[15:8];
+   always @(posedge ACP_CONF0_clk_ctrl)
+      if (ACP_CONF8_ena_ctrl)
+	 {ACP_CONF_q[15], ACP_CONF_q[14], ACP_CONF_q[13], ACP_CONF_q[12],
+	       ACP_CONF_q[11], ACP_CONF_q[10], ACP_CONF_q[9], ACP_CONF_q[8]} <=
+	       ACP_CONF_d[15:8];
+
+   assign ACP_CONF[7:0] = ACP_CONF_q[7:0];
+   always @(posedge ACP_CONF0_clk_ctrl)
+      if (ACP_CONF0_ena_ctrl)
+	 {ACP_CONF_q[7], ACP_CONF_q[6], ACP_CONF_q[5], ACP_CONF_q[4],
+	       ACP_CONF_q[3], ACP_CONF_q[2], ACP_CONF_q[1], ACP_CONF_q[0]} <=
+	       ACP_CONF_d[7:0];
+
+   always @(posedge INT_CTR0_clk_ctrl)
+      if (INT_CTR24_ena_ctrl)
+	 {INT_CTR_q[31], INT_CTR_q[30], INT_CTR_q[29], INT_CTR_q[28],
+	       INT_CTR_q[27], INT_CTR_q[26], INT_CTR_q[25], INT_CTR_q[24]} <=
+	       INT_CTR_d[31:24];
+
+   always @(posedge INT_CTR0_clk_ctrl)
+      if (INT_CTR16_ena_ctrl)
+	 {INT_CTR_q[23], INT_CTR_q[22], INT_CTR_q[21], INT_CTR_q[20],
+	       INT_CTR_q[19], INT_CTR_q[18], INT_CTR_q[17], INT_CTR_q[16]} <=
+	       INT_CTR_d[23:16];
+
+   always @(posedge INT_CTR0_clk_ctrl)
+      if (INT_CTR8_ena_ctrl)
+	 {INT_CTR_q[15], INT_CTR_q[14], INT_CTR_q[13], INT_CTR_q[12],
+	       INT_CTR_q[11], INT_CTR_q[10], INT_CTR_q[9], INT_CTR_q[8]} <=
+	       INT_CTR_d[15:8];
+
+   always @(posedge INT_CTR0_clk_ctrl)
+      if (INT_CTR0_ena_ctrl)
+	 {INT_CTR_q[7], INT_CTR_q[6], INT_CTR_q[5], INT_CTR_q[4], INT_CTR_q[3],
+	       INT_CTR_q[2], INT_CTR_q[1], INT_CTR_q[0]} <= INT_CTR_d[7:0];
+
+//GE
+always @(posedge MAIN_CLK)
+	INT_LATCH_d_prev <= INT_LATCH_d;
+	
+genvar n;
+generate
+for(n = 0; n < 32; n = n + 1) begin: syncint
+	always @(posedge MAIN_CLK)
+	begin
+		if (!nRST)
+			INT_LATCH_q[n] <= 1'b0;
+		else if (INT_CLEAR_q[n])
+			INT_LATCH_q[n] <= 1'b0;
+		else if (INT_LATCH_d[n] & !INT_LATCH_d_prev[n])
+			INT_LATCH_q[n] <= 1'b1;
+		else
+			INT_LATCH_q[n] <= INT_LATCH_q[n];
+	end
+end
+endgenerate
+
+   /*always @(posedge INT_LATCH_clk or negedge INT_LATCH31_clrn)
+      if (!INT_LATCH31_clrn)
+	 INT_LATCH_q[31] <= 1'h0;
+      else
+	 INT_LATCH_q[31] <= INT_LATCH_d[31];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH30_clrn)
+      if (!INT_LATCH30_clrn)
+	 INT_LATCH_q[30] <= 1'h0;
+      else
+	 INT_LATCH_q[30] <= INT_LATCH_d[30];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH29_clrn)
+      if (!INT_LATCH29_clrn)
+	 INT_LATCH_q[29] <= 1'h0;
+      else
+	 INT_LATCH_q[29] <= INT_LATCH_d[29];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH28_clrn)
+      if (!INT_LATCH28_clrn)
+	 INT_LATCH_q[28] <= 1'h0;
+      else
+	 INT_LATCH_q[28] <= INT_LATCH_d[28];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH27_clrn)
+      if (!INT_LATCH27_clrn)
+	 INT_LATCH_q[27] <= 1'h0;
+      else
+	 INT_LATCH_q[27] <= INT_LATCH_d[27];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH26_clrn)
+      if (!INT_LATCH26_clrn)
+	 INT_LATCH_q[26] <= 1'h0;
+      else
+	 INT_LATCH_q[26] <= INT_LATCH_d[26];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH25_clrn)
+      if (!INT_LATCH25_clrn)
+	 INT_LATCH_q[25] <= 1'h0;
+      else
+	 INT_LATCH_q[25] <= INT_LATCH_d[25];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH24_clrn)
+      if (!INT_LATCH24_clrn)
+	 INT_LATCH_q[24] <= 1'h0;
+      else
+	 INT_LATCH_q[24] <= INT_LATCH_d[24];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH23_clrn)
+      if (!INT_LATCH23_clrn)
+	 INT_LATCH_q[23] <= 1'h0;
+      else
+	 INT_LATCH_q[23] <= INT_LATCH_d[23];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH22_clrn)
+      if (!INT_LATCH22_clrn)
+	 INT_LATCH_q[22] <= 1'h0;
+      else
+	 INT_LATCH_q[22] <= INT_LATCH_d[22];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH21_clrn)
+      if (!INT_LATCH21_clrn)
+	 INT_LATCH_q[21] <= 1'h0;
+      else
+	 INT_LATCH_q[21] <= INT_LATCH_d[21];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH20_clrn)
+      if (!INT_LATCH20_clrn)
+	 INT_LATCH_q[20] <= 1'h0;
+      else
+	 INT_LATCH_q[20] <= INT_LATCH_d[20];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH19_clrn)
+      if (!INT_LATCH19_clrn)
+	 INT_LATCH_q[19] <= 1'h0;
+      else
+	 INT_LATCH_q[19] <= INT_LATCH_d[19];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH18_clrn)
+      if (!INT_LATCH18_clrn)
+	 INT_LATCH_q[18] <= 1'h0;
+      else
+	 INT_LATCH_q[18] <= INT_LATCH_d[18];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH17_clrn)
+      if (!INT_LATCH17_clrn)
+	 INT_LATCH_q[17] <= 1'h0;
+      else
+	 INT_LATCH_q[17] <= INT_LATCH_d[17];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH16_clrn)
+      if (!INT_LATCH16_clrn)
+	 INT_LATCH_q[16] <= 1'h0;
+      else
+	 INT_LATCH_q[16] <= INT_LATCH_d[16];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH15_clrn)
+      if (!INT_LATCH15_clrn)
+	 INT_LATCH_q[15] <= 1'h0;
+      else
+	 INT_LATCH_q[15] <= INT_LATCH_d[15];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH14_clrn)
+      if (!INT_LATCH14_clrn)
+	 INT_LATCH_q[14] <= 1'h0;
+      else
+	 INT_LATCH_q[14] <= INT_LATCH_d[14];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH13_clrn)
+      if (!INT_LATCH13_clrn)
+	 INT_LATCH_q[13] <= 1'h0;
+      else
+	 INT_LATCH_q[13] <= INT_LATCH_d[13];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH12_clrn)
+      if (!INT_LATCH12_clrn)
+	 INT_LATCH_q[12] <= 1'h0;
+      else
+	 INT_LATCH_q[12] <= INT_LATCH_d[12];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH11_clrn)
+      if (!INT_LATCH11_clrn)
+	 INT_LATCH_q[11] <= 1'h0;
+      else
+	 INT_LATCH_q[11] <= INT_LATCH_d[11];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH10_clrn)
+      if (!INT_LATCH10_clrn)
+	 INT_LATCH_q[10] <= 1'h0;
+      else
+	 INT_LATCH_q[10] <= INT_LATCH_d[10];
+
+   always @(posedge INT_LATCH9_clk_1 or negedge INT_LATCH9_clrn)
+      if (!INT_LATCH9_clrn)
+	 INT_LATCH_q[9] <= 1'h0;
+      else
+	 INT_LATCH_q[9] <= INT_LATCH_d[9];
+
+   always @(posedge INT_LATCH8_clk_1 or negedge INT_LATCH8_clrn)
+      if (!INT_LATCH8_clrn)
+	 INT_LATCH_q[8] <= 1'h0;
+      else
+	 INT_LATCH_q[8] <= INT_LATCH_d[8];
+
+   always @(posedge INT_LATCH7_clk_1 or negedge INT_LATCH7_clrn)
+      if (!INT_LATCH7_clrn)
+	 INT_LATCH_q[7] <= 1'h0;
+      else
+	 INT_LATCH_q[7] <= INT_LATCH_d[7];
+
+   always @(posedge INT_LATCH6_clk_1 or negedge INT_LATCH6_clrn)
+      if (!INT_LATCH6_clrn)
+	 INT_LATCH_q[6] <= 1'h0;
+      else
+	 INT_LATCH_q[6] <= INT_LATCH_d[6];
+
+   always @(posedge INT_LATCH5_clk_1 or negedge INT_LATCH5_clrn)
+      if (!INT_LATCH5_clrn)
+	 INT_LATCH_q[5] <= 1'h0;
+      else
+	 INT_LATCH_q[5] <= INT_LATCH_d[5];
+
+   always @(posedge INT_LATCH4_clk_1 or negedge INT_LATCH4_clrn)
+      if (!INT_LATCH4_clrn)
+	 INT_LATCH_q[4] <= 1'h0;
+      else
+	 INT_LATCH_q[4] <= INT_LATCH_d[4];
+
+   always @(posedge INT_LATCH3_clk_1 or negedge INT_LATCH3_clrn)
+      if (!INT_LATCH3_clrn)
+	 INT_LATCH_q[3] <= 1'h0;
+      else
+	 INT_LATCH_q[3] <= INT_LATCH_d[3];
+
+   always @(posedge INT_LATCH2_clk_1 or negedge INT_LATCH2_clrn)
+      if (!INT_LATCH2_clrn)
+	 INT_LATCH_q[2] <= 1'h0;
+      else
+	 INT_LATCH_q[2] <= INT_LATCH_d[2];
+
+   always @(posedge INT_LATCH1_clk_1 or negedge INT_LATCH1_clrn)
+      if (!INT_LATCH1_clrn)
+	 INT_LATCH_q[1] <= 1'h0;
+      else
+	 INT_LATCH_q[1] <= INT_LATCH_d[1];
+
+   always @(posedge INT_LATCH0_clk_1 or negedge INT_LATCH0_clrn)
+      if (!INT_LATCH0_clrn)
+	 INT_LATCH_q[0] <= 1'h0;
+      else
+	 INT_LATCH_q[0] <= INT_LATCH_d[0];*/
+	 
+
+   always @(posedge INT_CLEAR0_clk_ctrl)
+      INT_CLEAR_q <= INT_CLEAR_d;
+
+   always @(posedge INT_ENA0_clk_ctrl)
+      if (INT_ENA24_ena_ctrl)
+	 {INT_ENA_q[31], INT_ENA_q[30], INT_ENA_q[29], INT_ENA_q[28],
+	       INT_ENA_q[27], INT_ENA_q[26], INT_ENA_q[25], INT_ENA_q[24]} <=
+	       INT_ENA_d[31:24];
+
+   always @(posedge INT_ENA0_clk_ctrl)
+      if (INT_ENA16_ena_ctrl)
+	 {INT_ENA_q[23], INT_ENA_q[22], INT_ENA_q[21], INT_ENA_q[20],
+	       INT_ENA_q[19], INT_ENA_q[18], INT_ENA_q[17], INT_ENA_q[16]} <=
+	       INT_ENA_d[23:16];
+
+   always @(posedge INT_ENA0_clk_ctrl)
+      if (INT_ENA8_ena_ctrl)
+	 {INT_ENA_q[15], INT_ENA_q[14], INT_ENA_q[13], INT_ENA_q[12],
+	       INT_ENA_q[11], INT_ENA_q[10], INT_ENA_q[9], INT_ENA_q[8]} <=
+	       INT_ENA_d[15:8];
+
+   always @(posedge INT_ENA0_clk_ctrl)
+      if (INT_ENA0_ena_ctrl)
+	 {INT_ENA_q[7], INT_ENA_q[6], INT_ENA_q[5], INT_ENA_q[4], INT_ENA_q[3],
+	       INT_ENA_q[2], INT_ENA_q[1], INT_ENA_q[0]} <= INT_ENA_d[7:0];
+
+   always @(posedge RTC_ADR0_clk_ctrl)
+      if (RTC_ADR0_ena_ctrl)
+	 RTC_ADR_q <= RTC_ADR_d;
+
+   always @(posedge ACHTELSEKUNDEN0_clk_ctrl)
+      if (ACHTELSEKUNDEN0_ena_ctrl)
+	 ACHTELSEKUNDEN_q <= ACHTELSEKUNDEN_d;
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_63_ena_ctrl)
+	 WERTE7__q[63] <= WERTE7__d[63];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_62_ena_ctrl)
+	 WERTE7__q[62] <= WERTE7__d[62];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_61_ena_ctrl)
+	 WERTE7__q[61] <= WERTE7__d[61];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_60_ena_ctrl)
+	 WERTE7__q[60] <= WERTE7__d[60];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_59_ena_ctrl)
+	 WERTE7__q[59] <= WERTE7__d[59];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_58_ena_ctrl)
+	 WERTE7__q[58] <= WERTE7__d[58];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_57_ena_ctrl)
+	 WERTE7__q[57] <= WERTE7__d[57];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_56_ena_ctrl)
+	 WERTE7__q[56] <= WERTE7__d[56];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_55_ena_ctrl)
+	 WERTE7__q[55] <= WERTE7__d[55];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_54_ena_ctrl)
+	 WERTE7__q[54] <= WERTE7__d[54];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_53_ena_ctrl)
+	 WERTE7__q[53] <= WERTE7__d[53];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_52_ena_ctrl)
+	 WERTE7__q[52] <= WERTE7__d[52];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_51_ena_ctrl)
+	 WERTE7__q[51] <= WERTE7__d[51];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_50_ena_ctrl)
+	 WERTE7__q[50] <= WERTE7__d[50];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_49_ena_ctrl)
+	 WERTE7__q[49] <= WERTE7__d[49];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_48_ena_ctrl)
+	 WERTE7__q[48] <= WERTE7__d[48];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_47_ena_ctrl)
+	 WERTE7__q[47] <= WERTE7__d[47];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_46_ena_ctrl)
+	 WERTE7__q[46] <= WERTE7__d[46];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_45_ena_ctrl)
+	 WERTE7__q[45] <= WERTE7__d[45];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_44_ena_ctrl)
+	 WERTE7__q[44] <= WERTE7__d[44];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_43_ena_ctrl)
+	 WERTE7__q[43] <= WERTE7__d[43];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_42_ena_ctrl)
+	 WERTE7__q[42] <= WERTE7__d[42];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_41_ena_ctrl)
+	 WERTE7__q[41] <= WERTE7__d[41];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_40_ena_ctrl)
+	 WERTE7__q[40] <= WERTE7__d[40];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_39_ena_ctrl)
+	 WERTE7__q[39] <= WERTE7__d[39];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_38_ena_ctrl)
+	 WERTE7__q[38] <= WERTE7__d[38];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_37_ena_ctrl)
+	 WERTE7__q[37] <= WERTE7__d[37];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_36_ena_ctrl)
+	 WERTE7__q[36] <= WERTE7__d[36];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_35_ena_ctrl)
+	 WERTE7__q[35] <= WERTE7__d[35];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_34_ena_ctrl)
+	 WERTE7__q[34] <= WERTE7__d[34];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_33_ena_ctrl)
+	 WERTE7__q[33] <= WERTE7__d[33];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_32_ena_ctrl)
+	 WERTE7__q[32] <= WERTE7__d[32];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_31_ena_ctrl)
+	 WERTE7__q[31] <= WERTE7__d[31];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_30_ena_ctrl)
+	 WERTE7__q[30] <= WERTE7__d[30];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_29_ena_ctrl)
+	 WERTE7__q[29] <= WERTE7__d[29];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_28_ena_ctrl)
+	 WERTE7__q[28] <= WERTE7__d[28];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_27_ena_ctrl)
+	 WERTE7__q[27] <= WERTE7__d[27];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_26_ena_ctrl)
+	 WERTE7__q[26] <= WERTE7__d[26];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_25_ena_ctrl)
+	 WERTE7__q[25] <= WERTE7__d[25];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_24_ena_ctrl)
+	 WERTE7__q[24] <= WERTE7__d[24];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_23_ena_ctrl)
+	 WERTE7__q[23] <= WERTE7__d[23];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_22_ena_ctrl)
+	 WERTE7__q[22] <= WERTE7__d[22];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_21_ena_ctrl)
+	 WERTE7__q[21] <= WERTE7__d[21];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_20_ena_ctrl)
+	 WERTE7__q[20] <= WERTE7__d[20];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_19_ena_ctrl)
+	 WERTE7__q[19] <= WERTE7__d[19];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_18_ena_ctrl)
+	 WERTE7__q[18] <= WERTE7__d[18];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_17_ena_ctrl)
+	 WERTE7__q[17] <= WERTE7__d[17];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_16_ena_ctrl)
+	 WERTE7__q[16] <= WERTE7__d[16];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_15_ena_ctrl)
+	 WERTE7__q[15] <= WERTE7__d[15];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_14_ena_ctrl)
+	 WERTE7__q[14] <= WERTE7__d[14];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE7_13_ena)
+	 WERTE7__q[13] <= WERTE7__d[13];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_12_ena_ctrl)
+	 WERTE7__q[12] <= WERTE7__d[12];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_11_ena_ctrl)
+	 WERTE7__q[11] <= WERTE7__d[11];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_10_ena_ctrl)
+	 WERTE7__q[10] <= WERTE7__d[10];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE7_9_ena)
+	 WERTE7__q[9] <= WERTE7__d[9];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE7_8_ena)
+	 WERTE7__q[8] <= WERTE7__d[8];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE7_7_ena)
+	 WERTE7__q[7] <= WERTE7__d[7];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE7_6_ena)
+	 WERTE7__q[6] <= WERTE7__d[6];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_5_ena_ctrl)
+	 WERTE7__q[5] <= WERTE7__d[5];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE7_4_ena)
+	 WERTE7__q[4] <= WERTE7__d[4];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_3_ena_ctrl)
+	 WERTE7__q[3] <= WERTE7__d[3];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE7_2_ena)
+	 WERTE7__q[2] <= WERTE7__d[2];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_1_ena_ctrl)
+	 WERTE7__q[1] <= WERTE7__d[1];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE7_0_ena)
+	 WERTE7__q[0] <= WERTE7__d[0];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_63_ena_ctrl)
+	 WERTE6__q[63] <= WERTE6__d[63];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_62_ena_ctrl)
+	 WERTE6__q[62] <= WERTE6__d[62];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_61_ena_ctrl)
+	 WERTE6__q[61] <= WERTE6__d[61];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_60_ena_ctrl)
+	 WERTE6__q[60] <= WERTE6__d[60];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_59_ena_ctrl)
+	 WERTE6__q[59] <= WERTE6__d[59];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_58_ena_ctrl)
+	 WERTE6__q[58] <= WERTE6__d[58];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_57_ena_ctrl)
+	 WERTE6__q[57] <= WERTE6__d[57];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_56_ena_ctrl)
+	 WERTE6__q[56] <= WERTE6__d[56];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_55_ena_ctrl)
+	 WERTE6__q[55] <= WERTE6__d[55];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_54_ena_ctrl)
+	 WERTE6__q[54] <= WERTE6__d[54];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_53_ena_ctrl)
+	 WERTE6__q[53] <= WERTE6__d[53];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_52_ena_ctrl)
+	 WERTE6__q[52] <= WERTE6__d[52];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_51_ena_ctrl)
+	 WERTE6__q[51] <= WERTE6__d[51];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_50_ena_ctrl)
+	 WERTE6__q[50] <= WERTE6__d[50];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_49_ena_ctrl)
+	 WERTE6__q[49] <= WERTE6__d[49];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_48_ena_ctrl)
+	 WERTE6__q[48] <= WERTE6__d[48];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_47_ena_ctrl)
+	 WERTE6__q[47] <= WERTE6__d[47];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_46_ena_ctrl)
+	 WERTE6__q[46] <= WERTE6__d[46];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_45_ena_ctrl)
+	 WERTE6__q[45] <= WERTE6__d[45];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_44_ena_ctrl)
+	 WERTE6__q[44] <= WERTE6__d[44];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_43_ena_ctrl)
+	 WERTE6__q[43] <= WERTE6__d[43];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_42_ena_ctrl)
+	 WERTE6__q[42] <= WERTE6__d[42];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_41_ena_ctrl)
+	 WERTE6__q[41] <= WERTE6__d[41];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_40_ena_ctrl)
+	 WERTE6__q[40] <= WERTE6__d[40];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_39_ena_ctrl)
+	 WERTE6__q[39] <= WERTE6__d[39];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_38_ena_ctrl)
+	 WERTE6__q[38] <= WERTE6__d[38];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_37_ena_ctrl)
+	 WERTE6__q[37] <= WERTE6__d[37];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_36_ena_ctrl)
+	 WERTE6__q[36] <= WERTE6__d[36];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_35_ena_ctrl)
+	 WERTE6__q[35] <= WERTE6__d[35];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_34_ena_ctrl)
+	 WERTE6__q[34] <= WERTE6__d[34];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_33_ena_ctrl)
+	 WERTE6__q[33] <= WERTE6__d[33];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_32_ena_ctrl)
+	 WERTE6__q[32] <= WERTE6__d[32];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_31_ena_ctrl)
+	 WERTE6__q[31] <= WERTE6__d[31];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_30_ena_ctrl)
+	 WERTE6__q[30] <= WERTE6__d[30];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_29_ena_ctrl)
+	 WERTE6__q[29] <= WERTE6__d[29];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_28_ena_ctrl)
+	 WERTE6__q[28] <= WERTE6__d[28];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_27_ena_ctrl)
+	 WERTE6__q[27] <= WERTE6__d[27];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_26_ena_ctrl)
+	 WERTE6__q[26] <= WERTE6__d[26];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_25_ena_ctrl)
+	 WERTE6__q[25] <= WERTE6__d[25];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_24_ena_ctrl)
+	 WERTE6__q[24] <= WERTE6__d[24];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_23_ena_ctrl)
+	 WERTE6__q[23] <= WERTE6__d[23];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_22_ena_ctrl)
+	 WERTE6__q[22] <= WERTE6__d[22];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_21_ena_ctrl)
+	 WERTE6__q[21] <= WERTE6__d[21];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_20_ena_ctrl)
+	 WERTE6__q[20] <= WERTE6__d[20];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_19_ena_ctrl)
+	 WERTE6__q[19] <= WERTE6__d[19];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_18_ena_ctrl)
+	 WERTE6__q[18] <= WERTE6__d[18];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_17_ena_ctrl)
+	 WERTE6__q[17] <= WERTE6__d[17];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_16_ena_ctrl)
+	 WERTE6__q[16] <= WERTE6__d[16];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_15_ena_ctrl)
+	 WERTE6__q[15] <= WERTE6__d[15];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_14_ena_ctrl)
+	 WERTE6__q[14] <= WERTE6__d[14];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE6_13_ena)
+	 WERTE6__q[13] <= WERTE6__d[13];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_12_ena_ctrl)
+	 WERTE6__q[12] <= WERTE6__d[12];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_11_ena_ctrl)
+	 WERTE6__q[11] <= WERTE6__d[11];
+
+   always @(posedge WERTE6_0_clk_ctrl or negedge WERTE6_10_clrn)
+      if (!WERTE6_10_clrn)
+	 WERTE6__q[10] <= 1'h0;
+      else
+	 if (WERTE0_10_ena_ctrl)
+	    WERTE6__q[10] <= WERTE6__d[10];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE6_9_ena)
+	 WERTE6__q[9] <= WERTE6__d[9];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE6_8_ena)
+	 WERTE6__q[8] <= WERTE6__d[8];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE6_7_ena)
+	 WERTE6__q[7] <= WERTE6__d[7];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE6_6_ena)
+	 WERTE6__q[6] <= WERTE6__d[6];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_5_ena_ctrl)
+	 WERTE6__q[5] <= WERTE6__d[5];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE6_4_ena)
+	 WERTE6__q[4] <= WERTE6__d[4];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_3_ena_ctrl)
+	 WERTE6__q[3] <= WERTE6__d[3];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE6_2_ena)
+	 WERTE6__q[2] <= WERTE6__d[2];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_1_ena_ctrl)
+	 WERTE6__q[1] <= WERTE6__d[1];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE6_0_ena)
+	 WERTE6__q[0] <= WERTE6__d[0];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_63_ena_ctrl)
+	 WERTE5__q[63] <= WERTE5__d[63];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_62_ena_ctrl)
+	 WERTE5__q[62] <= WERTE5__d[62];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_61_ena_ctrl)
+	 WERTE5__q[61] <= WERTE5__d[61];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_60_ena_ctrl)
+	 WERTE5__q[60] <= WERTE5__d[60];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_59_ena_ctrl)
+	 WERTE5__q[59] <= WERTE5__d[59];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_58_ena_ctrl)
+	 WERTE5__q[58] <= WERTE5__d[58];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_57_ena_ctrl)
+	 WERTE5__q[57] <= WERTE5__d[57];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_56_ena_ctrl)
+	 WERTE5__q[56] <= WERTE5__d[56];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_55_ena_ctrl)
+	 WERTE5__q[55] <= WERTE5__d[55];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_54_ena_ctrl)
+	 WERTE5__q[54] <= WERTE5__d[54];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_53_ena_ctrl)
+	 WERTE5__q[53] <= WERTE5__d[53];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_52_ena_ctrl)
+	 WERTE5__q[52] <= WERTE5__d[52];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_51_ena_ctrl)
+	 WERTE5__q[51] <= WERTE5__d[51];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_50_ena_ctrl)
+	 WERTE5__q[50] <= WERTE5__d[50];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_49_ena_ctrl)
+	 WERTE5__q[49] <= WERTE5__d[49];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_48_ena_ctrl)
+	 WERTE5__q[48] <= WERTE5__d[48];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_47_ena_ctrl)
+	 WERTE5__q[47] <= WERTE5__d[47];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_46_ena_ctrl)
+	 WERTE5__q[46] <= WERTE5__d[46];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_45_ena_ctrl)
+	 WERTE5__q[45] <= WERTE5__d[45];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_44_ena_ctrl)
+	 WERTE5__q[44] <= WERTE5__d[44];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_43_ena_ctrl)
+	 WERTE5__q[43] <= WERTE5__d[43];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_42_ena_ctrl)
+	 WERTE5__q[42] <= WERTE5__d[42];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_41_ena_ctrl)
+	 WERTE5__q[41] <= WERTE5__d[41];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_40_ena_ctrl)
+	 WERTE5__q[40] <= WERTE5__d[40];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_39_ena_ctrl)
+	 WERTE5__q[39] <= WERTE5__d[39];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_38_ena_ctrl)
+	 WERTE5__q[38] <= WERTE5__d[38];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_37_ena_ctrl)
+	 WERTE5__q[37] <= WERTE5__d[37];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_36_ena_ctrl)
+	 WERTE5__q[36] <= WERTE5__d[36];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_35_ena_ctrl)
+	 WERTE5__q[35] <= WERTE5__d[35];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_34_ena_ctrl)
+	 WERTE5__q[34] <= WERTE5__d[34];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_33_ena_ctrl)
+	 WERTE5__q[33] <= WERTE5__d[33];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_32_ena_ctrl)
+	 WERTE5__q[32] <= WERTE5__d[32];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_31_ena_ctrl)
+	 WERTE5__q[31] <= WERTE5__d[31];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_30_ena_ctrl)
+	 WERTE5__q[30] <= WERTE5__d[30];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_29_ena_ctrl)
+	 WERTE5__q[29] <= WERTE5__d[29];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_28_ena_ctrl)
+	 WERTE5__q[28] <= WERTE5__d[28];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_27_ena_ctrl)
+	 WERTE5__q[27] <= WERTE5__d[27];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_26_ena_ctrl)
+	 WERTE5__q[26] <= WERTE5__d[26];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_25_ena_ctrl)
+	 WERTE5__q[25] <= WERTE5__d[25];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_24_ena_ctrl)
+	 WERTE5__q[24] <= WERTE5__d[24];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_23_ena_ctrl)
+	 WERTE5__q[23] <= WERTE5__d[23];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_22_ena_ctrl)
+	 WERTE5__q[22] <= WERTE5__d[22];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_21_ena_ctrl)
+	 WERTE5__q[21] <= WERTE5__d[21];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_20_ena_ctrl)
+	 WERTE5__q[20] <= WERTE5__d[20];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_19_ena_ctrl)
+	 WERTE5__q[19] <= WERTE5__d[19];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_18_ena_ctrl)
+	 WERTE5__q[18] <= WERTE5__d[18];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_17_ena_ctrl)
+	 WERTE5__q[17] <= WERTE5__d[17];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_16_ena_ctrl)
+	 WERTE5__q[16] <= WERTE5__d[16];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_15_ena_ctrl)
+	 WERTE5__q[15] <= WERTE5__d[15];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_14_ena_ctrl)
+	 WERTE5__q[14] <= WERTE5__d[14];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE5_13_ena)
+	 WERTE5__q[13] <= WERTE5__d[13];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_12_ena_ctrl)
+	 WERTE5__q[12] <= WERTE5__d[12];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_11_ena_ctrl)
+	 WERTE5__q[11] <= WERTE5__d[11];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_10_ena_ctrl)
+	 WERTE5__q[10] <= WERTE5__d[10];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE5_9_ena)
+	 WERTE5__q[9] <= WERTE5__d[9];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE5_8_ena)
+	 WERTE5__q[8] <= WERTE5__d[8];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE5_7_ena)
+	 WERTE5__q[7] <= WERTE5__d[7];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE5_6_ena)
+	 WERTE5__q[6] <= WERTE5__d[6];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_5_ena_ctrl)
+	 WERTE5__q[5] <= WERTE5__d[5];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE5_4_ena)
+	 WERTE5__q[4] <= WERTE5__d[4];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_3_ena_ctrl)
+	 WERTE5__q[3] <= WERTE5__d[3];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE5_2_ena)
+	 WERTE5__q[2] <= WERTE5__d[2];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_1_ena_ctrl)
+	 WERTE5__q[1] <= WERTE5__d[1];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE5_0_ena)
+	 WERTE5__q[0] <= WERTE5__d[0];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_63_ena_ctrl)
+	 WERTE4__q[63] <= WERTE4__d[63];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_62_ena_ctrl)
+	 WERTE4__q[62] <= WERTE4__d[62];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_61_ena_ctrl)
+	 WERTE4__q[61] <= WERTE4__d[61];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_60_ena_ctrl)
+	 WERTE4__q[60] <= WERTE4__d[60];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_59_ena_ctrl)
+	 WERTE4__q[59] <= WERTE4__d[59];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_58_ena_ctrl)
+	 WERTE4__q[58] <= WERTE4__d[58];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_57_ena_ctrl)
+	 WERTE4__q[57] <= WERTE4__d[57];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_56_ena_ctrl)
+	 WERTE4__q[56] <= WERTE4__d[56];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_55_ena_ctrl)
+	 WERTE4__q[55] <= WERTE4__d[55];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_54_ena_ctrl)
+	 WERTE4__q[54] <= WERTE4__d[54];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_53_ena_ctrl)
+	 WERTE4__q[53] <= WERTE4__d[53];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_52_ena_ctrl)
+	 WERTE4__q[52] <= WERTE4__d[52];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_51_ena_ctrl)
+	 WERTE4__q[51] <= WERTE4__d[51];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_50_ena_ctrl)
+	 WERTE4__q[50] <= WERTE4__d[50];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_49_ena_ctrl)
+	 WERTE4__q[49] <= WERTE4__d[49];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_48_ena_ctrl)
+	 WERTE4__q[48] <= WERTE4__d[48];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_47_ena_ctrl)
+	 WERTE4__q[47] <= WERTE4__d[47];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_46_ena_ctrl)
+	 WERTE4__q[46] <= WERTE4__d[46];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_45_ena_ctrl)
+	 WERTE4__q[45] <= WERTE4__d[45];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_44_ena_ctrl)
+	 WERTE4__q[44] <= WERTE4__d[44];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_43_ena_ctrl)
+	 WERTE4__q[43] <= WERTE4__d[43];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_42_ena_ctrl)
+	 WERTE4__q[42] <= WERTE4__d[42];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_41_ena_ctrl)
+	 WERTE4__q[41] <= WERTE4__d[41];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_40_ena_ctrl)
+	 WERTE4__q[40] <= WERTE4__d[40];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_39_ena_ctrl)
+	 WERTE4__q[39] <= WERTE4__d[39];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_38_ena_ctrl)
+	 WERTE4__q[38] <= WERTE4__d[38];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_37_ena_ctrl)
+	 WERTE4__q[37] <= WERTE4__d[37];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_36_ena_ctrl)
+	 WERTE4__q[36] <= WERTE4__d[36];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_35_ena_ctrl)
+	 WERTE4__q[35] <= WERTE4__d[35];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_34_ena_ctrl)
+	 WERTE4__q[34] <= WERTE4__d[34];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_33_ena_ctrl)
+	 WERTE4__q[33] <= WERTE4__d[33];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_32_ena_ctrl)
+	 WERTE4__q[32] <= WERTE4__d[32];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_31_ena_ctrl)
+	 WERTE4__q[31] <= WERTE4__d[31];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_30_ena_ctrl)
+	 WERTE4__q[30] <= WERTE4__d[30];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_29_ena_ctrl)
+	 WERTE4__q[29] <= WERTE4__d[29];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_28_ena_ctrl)
+	 WERTE4__q[28] <= WERTE4__d[28];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_27_ena_ctrl)
+	 WERTE4__q[27] <= WERTE4__d[27];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_26_ena_ctrl)
+	 WERTE4__q[26] <= WERTE4__d[26];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_25_ena_ctrl)
+	 WERTE4__q[25] <= WERTE4__d[25];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_24_ena_ctrl)
+	 WERTE4__q[24] <= WERTE4__d[24];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_23_ena_ctrl)
+	 WERTE4__q[23] <= WERTE4__d[23];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_22_ena_ctrl)
+	 WERTE4__q[22] <= WERTE4__d[22];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_21_ena_ctrl)
+	 WERTE4__q[21] <= WERTE4__d[21];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_20_ena_ctrl)
+	 WERTE4__q[20] <= WERTE4__d[20];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_19_ena_ctrl)
+	 WERTE4__q[19] <= WERTE4__d[19];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_18_ena_ctrl)
+	 WERTE4__q[18] <= WERTE4__d[18];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_17_ena_ctrl)
+	 WERTE4__q[17] <= WERTE4__d[17];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_16_ena_ctrl)
+	 WERTE4__q[16] <= WERTE4__d[16];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_15_ena_ctrl)
+	 WERTE4__q[15] <= WERTE4__d[15];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_14_ena_ctrl)
+	 WERTE4__q[14] <= WERTE4__d[14];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE4_13_ena)
+	 WERTE4__q[13] <= WERTE4__d[13];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_12_ena_ctrl)
+	 WERTE4__q[12] <= WERTE4__d[12];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_11_ena_ctrl)
+	 WERTE4__q[11] <= WERTE4__d[11];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_10_ena_ctrl)
+	 WERTE4__q[10] <= WERTE4__d[10];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE4_9_ena)
+	 WERTE4__q[9] <= WERTE4__d[9];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE4_8_ena)
+	 WERTE4__q[8] <= WERTE4__d[8];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE4_7_ena)
+	 WERTE4__q[7] <= WERTE4__d[7];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE4_6_ena)
+	 WERTE4__q[6] <= WERTE4__d[6];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_5_ena_ctrl)
+	 WERTE4__q[5] <= WERTE4__d[5];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE4_4_ena)
+	 WERTE4__q[4] <= WERTE4__d[4];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_3_ena_ctrl)
+	 WERTE4__q[3] <= WERTE4__d[3];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE4_2_ena)
+	 WERTE4__q[2] <= WERTE4__d[2];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_1_ena_ctrl)
+	 WERTE4__q[1] <= WERTE4__d[1];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE4_0_ena)
+	 WERTE4__q[0] <= WERTE4__d[0];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_63_ena_ctrl)
+	 WERTE3__q[63] <= WERTE3__d[63];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_62_ena_ctrl)
+	 WERTE3__q[62] <= WERTE3__d[62];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_61_ena_ctrl)
+	 WERTE3__q[61] <= WERTE3__d[61];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_60_ena_ctrl)
+	 WERTE3__q[60] <= WERTE3__d[60];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_59_ena_ctrl)
+	 WERTE3__q[59] <= WERTE3__d[59];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_58_ena_ctrl)
+	 WERTE3__q[58] <= WERTE3__d[58];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_57_ena_ctrl)
+	 WERTE3__q[57] <= WERTE3__d[57];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_56_ena_ctrl)
+	 WERTE3__q[56] <= WERTE3__d[56];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_55_ena_ctrl)
+	 WERTE3__q[55] <= WERTE3__d[55];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_54_ena_ctrl)
+	 WERTE3__q[54] <= WERTE3__d[54];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_53_ena_ctrl)
+	 WERTE3__q[53] <= WERTE3__d[53];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_52_ena_ctrl)
+	 WERTE3__q[52] <= WERTE3__d[52];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_51_ena_ctrl)
+	 WERTE3__q[51] <= WERTE3__d[51];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_50_ena_ctrl)
+	 WERTE3__q[50] <= WERTE3__d[50];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_49_ena_ctrl)
+	 WERTE3__q[49] <= WERTE3__d[49];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_48_ena_ctrl)
+	 WERTE3__q[48] <= WERTE3__d[48];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_47_ena_ctrl)
+	 WERTE3__q[47] <= WERTE3__d[47];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_46_ena_ctrl)
+	 WERTE3__q[46] <= WERTE3__d[46];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_45_ena_ctrl)
+	 WERTE3__q[45] <= WERTE3__d[45];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_44_ena_ctrl)
+	 WERTE3__q[44] <= WERTE3__d[44];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_43_ena_ctrl)
+	 WERTE3__q[43] <= WERTE3__d[43];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_42_ena_ctrl)
+	 WERTE3__q[42] <= WERTE3__d[42];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_41_ena_ctrl)
+	 WERTE3__q[41] <= WERTE3__d[41];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_40_ena_ctrl)
+	 WERTE3__q[40] <= WERTE3__d[40];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_39_ena_ctrl)
+	 WERTE3__q[39] <= WERTE3__d[39];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_38_ena_ctrl)
+	 WERTE3__q[38] <= WERTE3__d[38];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_37_ena_ctrl)
+	 WERTE3__q[37] <= WERTE3__d[37];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_36_ena_ctrl)
+	 WERTE3__q[36] <= WERTE3__d[36];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_35_ena_ctrl)
+	 WERTE3__q[35] <= WERTE3__d[35];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_34_ena_ctrl)
+	 WERTE3__q[34] <= WERTE3__d[34];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_33_ena_ctrl)
+	 WERTE3__q[33] <= WERTE3__d[33];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_32_ena_ctrl)
+	 WERTE3__q[32] <= WERTE3__d[32];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_31_ena_ctrl)
+	 WERTE3__q[31] <= WERTE3__d[31];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_30_ena_ctrl)
+	 WERTE3__q[30] <= WERTE3__d[30];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_29_ena_ctrl)
+	 WERTE3__q[29] <= WERTE3__d[29];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_28_ena_ctrl)
+	 WERTE3__q[28] <= WERTE3__d[28];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_27_ena_ctrl)
+	 WERTE3__q[27] <= WERTE3__d[27];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_26_ena_ctrl)
+	 WERTE3__q[26] <= WERTE3__d[26];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_25_ena_ctrl)
+	 WERTE3__q[25] <= WERTE3__d[25];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_24_ena_ctrl)
+	 WERTE3__q[24] <= WERTE3__d[24];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_23_ena_ctrl)
+	 WERTE3__q[23] <= WERTE3__d[23];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_22_ena_ctrl)
+	 WERTE3__q[22] <= WERTE3__d[22];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_21_ena_ctrl)
+	 WERTE3__q[21] <= WERTE3__d[21];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_20_ena_ctrl)
+	 WERTE3__q[20] <= WERTE3__d[20];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_19_ena_ctrl)
+	 WERTE3__q[19] <= WERTE3__d[19];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_18_ena_ctrl)
+	 WERTE3__q[18] <= WERTE3__d[18];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_17_ena_ctrl)
+	 WERTE3__q[17] <= WERTE3__d[17];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_16_ena_ctrl)
+	 WERTE3__q[16] <= WERTE3__d[16];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_15_ena_ctrl)
+	 WERTE3__q[15] <= WERTE3__d[15];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_14_ena_ctrl)
+	 WERTE3__q[14] <= WERTE3__d[14];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE3_13_ena)
+	 WERTE3__q[13] <= WERTE3__d[13];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_12_ena_ctrl)
+	 WERTE3__q[12] <= WERTE3__d[12];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_11_ena_ctrl)
+	 WERTE3__q[11] <= WERTE3__d[11];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_10_ena_ctrl)
+	 WERTE3__q[10] <= WERTE3__d[10];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE3_9_ena)
+	 WERTE3__q[9] <= WERTE3__d[9];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE3_8_ena)
+	 WERTE3__q[8] <= WERTE3__d[8];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE3_7_ena)
+	 WERTE3__q[7] <= WERTE3__d[7];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE3_6_ena)
+	 WERTE3__q[6] <= WERTE3__d[6];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_5_ena_ctrl)
+	 WERTE3__q[5] <= WERTE3__d[5];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE3_4_ena)
+	 WERTE3__q[4] <= WERTE3__d[4];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_3_ena_ctrl)
+	 WERTE3__q[3] <= WERTE3__d[3];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE3_2_ena)
+	 WERTE3__q[2] <= WERTE3__d[2];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_1_ena_ctrl)
+	 WERTE3__q[1] <= WERTE3__d[1];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE3_0_ena)
+	 WERTE3__q[0] <= WERTE3__d[0];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_63_ena_ctrl)
+	 WERTE2__q[63] <= WERTE2__d[63];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_62_ena_ctrl)
+	 WERTE2__q[62] <= WERTE2__d[62];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_61_ena_ctrl)
+	 WERTE2__q[61] <= WERTE2__d[61];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_60_ena_ctrl)
+	 WERTE2__q[60] <= WERTE2__d[60];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_59_ena_ctrl)
+	 WERTE2__q[59] <= WERTE2__d[59];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_58_ena_ctrl)
+	 WERTE2__q[58] <= WERTE2__d[58];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_57_ena_ctrl)
+	 WERTE2__q[57] <= WERTE2__d[57];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_56_ena_ctrl)
+	 WERTE2__q[56] <= WERTE2__d[56];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_55_ena_ctrl)
+	 WERTE2__q[55] <= WERTE2__d[55];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_54_ena_ctrl)
+	 WERTE2__q[54] <= WERTE2__d[54];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_53_ena_ctrl)
+	 WERTE2__q[53] <= WERTE2__d[53];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_52_ena_ctrl)
+	 WERTE2__q[52] <= WERTE2__d[52];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_51_ena_ctrl)
+	 WERTE2__q[51] <= WERTE2__d[51];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_50_ena_ctrl)
+	 WERTE2__q[50] <= WERTE2__d[50];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_49_ena_ctrl)
+	 WERTE2__q[49] <= WERTE2__d[49];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_48_ena_ctrl)
+	 WERTE2__q[48] <= WERTE2__d[48];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_47_ena_ctrl)
+	 WERTE2__q[47] <= WERTE2__d[47];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_46_ena_ctrl)
+	 WERTE2__q[46] <= WERTE2__d[46];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_45_ena_ctrl)
+	 WERTE2__q[45] <= WERTE2__d[45];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_44_ena_ctrl)
+	 WERTE2__q[44] <= WERTE2__d[44];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_43_ena_ctrl)
+	 WERTE2__q[43] <= WERTE2__d[43];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_42_ena_ctrl)
+	 WERTE2__q[42] <= WERTE2__d[42];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_41_ena_ctrl)
+	 WERTE2__q[41] <= WERTE2__d[41];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_40_ena_ctrl)
+	 WERTE2__q[40] <= WERTE2__d[40];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_39_ena_ctrl)
+	 WERTE2__q[39] <= WERTE2__d[39];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_38_ena_ctrl)
+	 WERTE2__q[38] <= WERTE2__d[38];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_37_ena_ctrl)
+	 WERTE2__q[37] <= WERTE2__d[37];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_36_ena_ctrl)
+	 WERTE2__q[36] <= WERTE2__d[36];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_35_ena_ctrl)
+	 WERTE2__q[35] <= WERTE2__d[35];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_34_ena_ctrl)
+	 WERTE2__q[34] <= WERTE2__d[34];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_33_ena_ctrl)
+	 WERTE2__q[33] <= WERTE2__d[33];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_32_ena_ctrl)
+	 WERTE2__q[32] <= WERTE2__d[32];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_31_ena_ctrl)
+	 WERTE2__q[31] <= WERTE2__d[31];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_30_ena_ctrl)
+	 WERTE2__q[30] <= WERTE2__d[30];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_29_ena_ctrl)
+	 WERTE2__q[29] <= WERTE2__d[29];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_28_ena_ctrl)
+	 WERTE2__q[28] <= WERTE2__d[28];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_27_ena_ctrl)
+	 WERTE2__q[27] <= WERTE2__d[27];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_26_ena_ctrl)
+	 WERTE2__q[26] <= WERTE2__d[26];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_25_ena_ctrl)
+	 WERTE2__q[25] <= WERTE2__d[25];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_24_ena_ctrl)
+	 WERTE2__q[24] <= WERTE2__d[24];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_23_ena_ctrl)
+	 WERTE2__q[23] <= WERTE2__d[23];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_22_ena_ctrl)
+	 WERTE2__q[22] <= WERTE2__d[22];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_21_ena_ctrl)
+	 WERTE2__q[21] <= WERTE2__d[21];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_20_ena_ctrl)
+	 WERTE2__q[20] <= WERTE2__d[20];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_19_ena_ctrl)
+	 WERTE2__q[19] <= WERTE2__d[19];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_18_ena_ctrl)
+	 WERTE2__q[18] <= WERTE2__d[18];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_17_ena_ctrl)
+	 WERTE2__q[17] <= WERTE2__d[17];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_16_ena_ctrl)
+	 WERTE2__q[16] <= WERTE2__d[16];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_15_ena_ctrl)
+	 WERTE2__q[15] <= WERTE2__d[15];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_14_ena_ctrl)
+	 WERTE2__q[14] <= WERTE2__d[14];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE2_13_ena)
+	 WERTE2__q[13] <= WERTE2__d[13];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_12_ena_ctrl)
+	 WERTE2__q[12] <= WERTE2__d[12];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_11_ena_ctrl)
+	 WERTE2__q[11] <= WERTE2__d[11];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_10_ena_ctrl)
+	 WERTE2__q[10] <= WERTE2__d[10];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE2_9_ena)
+	 WERTE2__q[9] <= WERTE2__d[9];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE2_8_ena)
+	 WERTE2__q[8] <= WERTE2__d[8];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE2_7_ena)
+	 WERTE2__q[7] <= WERTE2__d[7];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE2_6_ena)
+	 WERTE2__q[6] <= WERTE2__d[6];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_5_ena_ctrl)
+	 WERTE2__q[5] <= WERTE2__d[5];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE2_4_ena)
+	 WERTE2__q[4] <= WERTE2__d[4];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_3_ena_ctrl)
+	 WERTE2__q[3] <= WERTE2__d[3];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE2_2_ena)
+	 WERTE2__q[2] <= WERTE2__d[2];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_1_ena_ctrl)
+	 WERTE2__q[1] <= WERTE2__d[1];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE2_0_ena)
+	 WERTE2__q[0] <= WERTE2__d[0];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_63_ena_ctrl)
+	 WERTE1__q[63] <= WERTE1__d[63];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_62_ena_ctrl)
+	 WERTE1__q[62] <= WERTE1__d[62];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_61_ena_ctrl)
+	 WERTE1__q[61] <= WERTE1__d[61];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_60_ena_ctrl)
+	 WERTE1__q[60] <= WERTE1__d[60];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_59_ena_ctrl)
+	 WERTE1__q[59] <= WERTE1__d[59];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_58_ena_ctrl)
+	 WERTE1__q[58] <= WERTE1__d[58];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_57_ena_ctrl)
+	 WERTE1__q[57] <= WERTE1__d[57];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_56_ena_ctrl)
+	 WERTE1__q[56] <= WERTE1__d[56];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_55_ena_ctrl)
+	 WERTE1__q[55] <= WERTE1__d[55];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_54_ena_ctrl)
+	 WERTE1__q[54] <= WERTE1__d[54];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_53_ena_ctrl)
+	 WERTE1__q[53] <= WERTE1__d[53];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_52_ena_ctrl)
+	 WERTE1__q[52] <= WERTE1__d[52];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_51_ena_ctrl)
+	 WERTE1__q[51] <= WERTE1__d[51];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_50_ena_ctrl)
+	 WERTE1__q[50] <= WERTE1__d[50];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_49_ena_ctrl)
+	 WERTE1__q[49] <= WERTE1__d[49];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_48_ena_ctrl)
+	 WERTE1__q[48] <= WERTE1__d[48];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_47_ena_ctrl)
+	 WERTE1__q[47] <= WERTE1__d[47];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_46_ena_ctrl)
+	 WERTE1__q[46] <= WERTE1__d[46];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_45_ena_ctrl)
+	 WERTE1__q[45] <= WERTE1__d[45];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_44_ena_ctrl)
+	 WERTE1__q[44] <= WERTE1__d[44];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_43_ena_ctrl)
+	 WERTE1__q[43] <= WERTE1__d[43];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_42_ena_ctrl)
+	 WERTE1__q[42] <= WERTE1__d[42];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_41_ena_ctrl)
+	 WERTE1__q[41] <= WERTE1__d[41];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_40_ena_ctrl)
+	 WERTE1__q[40] <= WERTE1__d[40];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_39_ena_ctrl)
+	 WERTE1__q[39] <= WERTE1__d[39];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_38_ena_ctrl)
+	 WERTE1__q[38] <= WERTE1__d[38];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_37_ena_ctrl)
+	 WERTE1__q[37] <= WERTE1__d[37];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_36_ena_ctrl)
+	 WERTE1__q[36] <= WERTE1__d[36];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_35_ena_ctrl)
+	 WERTE1__q[35] <= WERTE1__d[35];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_34_ena_ctrl)
+	 WERTE1__q[34] <= WERTE1__d[34];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_33_ena_ctrl)
+	 WERTE1__q[33] <= WERTE1__d[33];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_32_ena_ctrl)
+	 WERTE1__q[32] <= WERTE1__d[32];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_31_ena_ctrl)
+	 WERTE1__q[31] <= WERTE1__d[31];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_30_ena_ctrl)
+	 WERTE1__q[30] <= WERTE1__d[30];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_29_ena_ctrl)
+	 WERTE1__q[29] <= WERTE1__d[29];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_28_ena_ctrl)
+	 WERTE1__q[28] <= WERTE1__d[28];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_27_ena_ctrl)
+	 WERTE1__q[27] <= WERTE1__d[27];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_26_ena_ctrl)
+	 WERTE1__q[26] <= WERTE1__d[26];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_25_ena_ctrl)
+	 WERTE1__q[25] <= WERTE1__d[25];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_24_ena_ctrl)
+	 WERTE1__q[24] <= WERTE1__d[24];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_23_ena_ctrl)
+	 WERTE1__q[23] <= WERTE1__d[23];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_22_ena_ctrl)
+	 WERTE1__q[22] <= WERTE1__d[22];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_21_ena_ctrl)
+	 WERTE1__q[21] <= WERTE1__d[21];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_20_ena_ctrl)
+	 WERTE1__q[20] <= WERTE1__d[20];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_19_ena_ctrl)
+	 WERTE1__q[19] <= WERTE1__d[19];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_18_ena_ctrl)
+	 WERTE1__q[18] <= WERTE1__d[18];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_17_ena_ctrl)
+	 WERTE1__q[17] <= WERTE1__d[17];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_16_ena_ctrl)
+	 WERTE1__q[16] <= WERTE1__d[16];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_15_ena_ctrl)
+	 WERTE1__q[15] <= WERTE1__d[15];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_14_ena_ctrl)
+	 WERTE1__q[14] <= WERTE1__d[14];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE1_13_ena)
+	 WERTE1__q[13] <= WERTE1__d[13];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_12_ena_ctrl)
+	 WERTE1__q[12] <= WERTE1__d[12];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_11_ena_ctrl)
+	 WERTE1__q[11] <= WERTE1__d[11];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_10_ena_ctrl)
+	 WERTE1__q[10] <= WERTE1__d[10];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE1_9_ena)
+	 WERTE1__q[9] <= WERTE1__d[9];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE1_8_ena)
+	 WERTE1__q[8] <= WERTE1__d[8];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE1_7_ena)
+	 WERTE1__q[7] <= WERTE1__d[7];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE1_6_ena)
+	 WERTE1__q[6] <= WERTE1__d[6];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_5_ena_ctrl)
+	 WERTE1__q[5] <= WERTE1__d[5];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE1_4_ena)
+	 WERTE1__q[4] <= WERTE1__d[4];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_3_ena_ctrl)
+	 WERTE1__q[3] <= WERTE1__d[3];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE1_2_ena)
+	 WERTE1__q[2] <= WERTE1__d[2];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_1_ena_ctrl)
+	 WERTE1__q[1] <= WERTE1__d[1];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE1_0_ena)
+	 WERTE1__q[0] <= WERTE1__d[0];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_63_ena_ctrl)
+	 WERTE0__q[63] <= WERTE0__d[63];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_62_ena_ctrl)
+	 WERTE0__q[62] <= WERTE0__d[62];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_61_ena_ctrl)
+	 WERTE0__q[61] <= WERTE0__d[61];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_60_ena_ctrl)
+	 WERTE0__q[60] <= WERTE0__d[60];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_59_ena_ctrl)
+	 WERTE0__q[59] <= WERTE0__d[59];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_58_ena_ctrl)
+	 WERTE0__q[58] <= WERTE0__d[58];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_57_ena_ctrl)
+	 WERTE0__q[57] <= WERTE0__d[57];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_56_ena_ctrl)
+	 WERTE0__q[56] <= WERTE0__d[56];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_55_ena_ctrl)
+	 WERTE0__q[55] <= WERTE0__d[55];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_54_ena_ctrl)
+	 WERTE0__q[54] <= WERTE0__d[54];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_53_ena_ctrl)
+	 WERTE0__q[53] <= WERTE0__d[53];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_52_ena_ctrl)
+	 WERTE0__q[52] <= WERTE0__d[52];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_51_ena_ctrl)
+	 WERTE0__q[51] <= WERTE0__d[51];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_50_ena_ctrl)
+	 WERTE0__q[50] <= WERTE0__d[50];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_49_ena_ctrl)
+	 WERTE0__q[49] <= WERTE0__d[49];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_48_ena_ctrl)
+	 WERTE0__q[48] <= WERTE0__d[48];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_47_ena_ctrl)
+	 WERTE0__q[47] <= WERTE0__d[47];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_46_ena_ctrl)
+	 WERTE0__q[46] <= WERTE0__d[46];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_45_ena_ctrl)
+	 WERTE0__q[45] <= WERTE0__d[45];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_44_ena_ctrl)
+	 WERTE0__q[44] <= WERTE0__d[44];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_43_ena_ctrl)
+	 WERTE0__q[43] <= WERTE0__d[43];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_42_ena_ctrl)
+	 WERTE0__q[42] <= WERTE0__d[42];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_41_ena_ctrl)
+	 WERTE0__q[41] <= WERTE0__d[41];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_40_ena_ctrl)
+	 WERTE0__q[40] <= WERTE0__d[40];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_39_ena_ctrl)
+	 WERTE0__q[39] <= WERTE0__d[39];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_38_ena_ctrl)
+	 WERTE0__q[38] <= WERTE0__d[38];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_37_ena_ctrl)
+	 WERTE0__q[37] <= WERTE0__d[37];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_36_ena_ctrl)
+	 WERTE0__q[36] <= WERTE0__d[36];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_35_ena_ctrl)
+	 WERTE0__q[35] <= WERTE0__d[35];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_34_ena_ctrl)
+	 WERTE0__q[34] <= WERTE0__d[34];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_33_ena_ctrl)
+	 WERTE0__q[33] <= WERTE0__d[33];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_32_ena_ctrl)
+	 WERTE0__q[32] <= WERTE0__d[32];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_31_ena_ctrl)
+	 WERTE0__q[31] <= WERTE0__d[31];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_30_ena_ctrl)
+	 WERTE0__q[30] <= WERTE0__d[30];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_29_ena_ctrl)
+	 WERTE0__q[29] <= WERTE0__d[29];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_28_ena_ctrl)
+	 WERTE0__q[28] <= WERTE0__d[28];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_27_ena_ctrl)
+	 WERTE0__q[27] <= WERTE0__d[27];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_26_ena_ctrl)
+	 WERTE0__q[26] <= WERTE0__d[26];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_25_ena_ctrl)
+	 WERTE0__q[25] <= WERTE0__d[25];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_24_ena_ctrl)
+	 WERTE0__q[24] <= WERTE0__d[24];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_23_ena_ctrl)
+	 WERTE0__q[23] <= WERTE0__d[23];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_22_ena_ctrl)
+	 WERTE0__q[22] <= WERTE0__d[22];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_21_ena_ctrl)
+	 WERTE0__q[21] <= WERTE0__d[21];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_20_ena_ctrl)
+	 WERTE0__q[20] <= WERTE0__d[20];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_19_ena_ctrl)
+	 WERTE0__q[19] <= WERTE0__d[19];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_18_ena_ctrl)
+	 WERTE0__q[18] <= WERTE0__d[18];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_17_ena_ctrl)
+	 WERTE0__q[17] <= WERTE0__d[17];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_16_ena_ctrl)
+	 WERTE0__q[16] <= WERTE0__d[16];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_15_ena_ctrl)
+	 WERTE0__q[15] <= WERTE0__d[15];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_14_ena_ctrl)
+	 WERTE0__q[14] <= WERTE0__d[14];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_13_ena)
+	 WERTE0__q[13] <= WERTE0__d[13];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_12_ena_ctrl)
+	 WERTE0__q[12] <= WERTE0__d[12];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_11_ena_ctrl)
+	 WERTE0__q[11] <= WERTE0__d[11];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_10_ena_ctrl)
+	 WERTE0__q[10] <= WERTE0__d[10];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_9_ena)
+	 WERTE0__q[9] <= WERTE0__d[9];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_8_ena)
+	 WERTE0__q[8] <= WERTE0__d[8];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_7_ena)
+	 WERTE0__q[7] <= WERTE0__d[7];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_6_ena)
+	 WERTE0__q[6] <= WERTE0__d[6];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_5_ena_ctrl)
+	 WERTE0__q[5] <= WERTE0__d[5];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_4_ena)
+	 WERTE0__q[4] <= WERTE0__d[4];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_3_ena_ctrl)
+	 WERTE0__q[3] <= WERTE0__d[3];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_2_ena)
+	 WERTE0__q[2] <= WERTE0__d[2];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_1_ena_ctrl)
+	 WERTE0__q[1] <= WERTE0__d[1];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_0_ena)
+	 WERTE0__q[0] <= WERTE0__d[0];
+
+   always @(posedge PIC_INT_SYNC0_clk_ctrl)
+      PIC_INT_SYNC_q <= PIC_INT_SYNC_d;
+
+// Start of original equations
+
+//  BYT SELECT
+//  HWORD
+//  HHBYT
+//  LONG UND LINE
+   assign FB_B[0] = (FB_SIZE1 & (!FB_SIZE0) & (!FB_ADR[1])) | ((!FB_SIZE1) &
+	 FB_SIZE0 & (!FB_ADR[1]) & (!FB_ADR[0])) | ((!FB_SIZE1) & (!FB_SIZE0))
+	 | (FB_SIZE1 & FB_SIZE0);
+
+//  HWORD
+//  HLBYT
+//  LONG UND LINE
+   assign FB_B[1] = (FB_SIZE1 & (!FB_SIZE0) & (!FB_ADR[1])) | ((!FB_SIZE1) &
+	 FB_SIZE0 & (!FB_ADR[1]) & FB_ADR[0]) | ((!FB_SIZE1) & (!FB_SIZE0)) |
+	 (FB_SIZE1 & FB_SIZE0);
+
+//  LWORD
+//  LHBYT
+//  LONG UND LINE
+   assign FB_B[2] = (FB_SIZE1 & (!FB_SIZE0) & FB_ADR[1]) | ((!FB_SIZE1) &
+	 FB_SIZE0 & FB_ADR[1] & (!FB_ADR[0])) | ((!FB_SIZE1) & (!FB_SIZE0)) |
+	 (FB_SIZE1 & FB_SIZE0);
+
+//  LWORD
+//  LLBYT
+//  LONG UND LINE
+   assign FB_B[3] = (FB_SIZE1 & (!FB_SIZE0) & FB_ADR[1]) | ((!FB_SIZE1) &
+	 FB_SIZE0 & FB_ADR[1] & FB_ADR[0]) | ((!FB_SIZE1) & (!FB_SIZE0)) |
+	 (FB_SIZE1 & FB_SIZE0);
+
+//  INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN
+   assign INT_CTR0_clk_ctrl = MAIN_CLK;
+
+//  $10000/4
+   assign INT_CTR_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h4000;
+   assign INT_CTR_d = FB_AD;
+   assign INT_CTR24_ena_ctrl = INT_CTR_CS & FB_B[0] & (!nFB_WR);
+   assign INT_CTR16_ena_ctrl = INT_CTR_CS & FB_B[1] & (!nFB_WR);
+   assign INT_CTR8_ena_ctrl = INT_CTR_CS & FB_B[2] & (!nFB_WR);
+   assign INT_CTR0_ena_ctrl = INT_CTR_CS & FB_B[3] & (!nFB_WR);
+
+//  INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
+   assign INT_ENA0_clk_ctrl = MAIN_CLK;
+
+//  $10004/4
+   assign INT_ENA_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h4001;
+   assign INT_ENA_d = FB_AD;
+   assign INT_ENA24_ena_ctrl = INT_ENA_CS & FB_B[0] & (!nFB_WR);
+   assign INT_ENA16_ena_ctrl = INT_ENA_CS & FB_B[1] & (!nFB_WR);
+   assign INT_ENA8_ena_ctrl = INT_ENA_CS & FB_B[2] & (!nFB_WR);
+   assign INT_ENA0_ena_ctrl = INT_ENA_CS & FB_B[3] & (!nFB_WR);
+
+//  INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR
+   assign INT_CLEAR0_clk_ctrl = MAIN_CLK;
+
+//  $10008/4
+   assign INT_CLEAR_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h4002;
+   assign INT_CLEAR_d[31:24] = FB_AD[31:24] & {8{INT_CLEAR_CS}} & {8{FB_B[0]}}
+	 & {8{!nFB_WR}};
+   assign INT_CLEAR_d[23:16] = FB_AD[23:16] & {8{INT_CLEAR_CS}} & {8{FB_B[1]}}
+	 & {8{!nFB_WR}};
+   assign INT_CLEAR_d[15:8] = FB_AD[15:8] & {8{INT_CLEAR_CS}} & {8{FB_B[2]}} &
+	 {8{!nFB_WR}};
+   assign INT_CLEAR_d[7:0] = FB_AD[7:0] & {8{INT_CLEAR_CS}} & {8{FB_B[3]}} &
+	 {8{!nFB_WR}};
+
+//  INTERRUPT LATCH REGISTER READ ONLY
+//  $1000C/4
+   assign INT_LATCH_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h4003;
+
+//  INTERRUPT
+   assign nIRQ[2] = !(HSYNC & INT_ENA_q[26]);
+   assign nIRQ[3] = !(INT_CTR_q[0] & INT_ENA_q[27]);
+   assign nIRQ[4] = !(VSYNC & INT_ENA_q[28]);
+   assign nIRQ[5] = INT_LATCH_q == 32'h0 & INT_ENA_q[29];
+   assign nIRQ[6] = !((!nMFP_INT) & INT_ENA_q[30]);
+   assign nIRQ[7] = !(PSEUDO_BUS_ERROR & INT_ENA_q[31]);
+
+//  SCC
+//  VME
+//  PADDLE
+//  PADDLE
+//  PADDLE
+//  MFP2
+//  MFP2
+//  MFP2
+//  MFP2
+//  TT SCSI
+//  ST UHR
+//  ST UHR
+//  DMA SOUND
+//  DMA SOUND
+//  DMA SOUND
+   assign PSEUDO_BUS_ERROR = (!nFB_CS1) & (FB_ADR[19:4] == 16'hF8C8 |
+	 FB_ADR[19:4] == 16'hF8E0 | FB_ADR[19:4] == 16'hF920 | FB_ADR[19:4] ==
+	 16'hF921 | FB_ADR[19:4] == 16'hF922 | FB_ADR[19:4] == 16'hFFA8 |
+	 FB_ADR[19:4] == 16'hFFA9 | FB_ADR[19:4] == 16'hFFAA | FB_ADR[19:4] ==
+	 16'hFFA8 | FB_ADR[19:8] == 12'b1111_1000_0111 | FB_ADR[19:4] ==
+	 16'hFFC2 | FB_ADR[19:4] == 16'hFFC3 | FB_ADR[19:4] == 16'hF890 |
+	 FB_ADR[19:4] == 16'hF891 | FB_ADR[19:4] == 16'hF892);
+
+//  IF VIDEO ADR CHANGE
+//  WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
+   assign TIN0 = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C100 & (!nFB_WR);
+
+//  INTERRUPT LATCH
+   /*assign INT_LATCH_d = 32'hFFFF_FFFF;
+   assign INT_LATCH0_clk_1 = PIC_INT & INT_ENA_q[0];
+   assign INT_LATCH1_clk_1 = E0_INT & INT_ENA_q[1];
+   assign INT_LATCH2_clk_1 = DVI_INT & INT_ENA_q[2];
+   assign INT_LATCH3_clk_1 = (!nPCI_INTA) & INT_ENA_q[3];
+   assign INT_LATCH4_clk_1 = (!nPCI_INTB) & INT_ENA_q[4];
+   assign INT_LATCH5_clk_1 = (!nPCI_INTC) & INT_ENA_q[5];
+   assign INT_LATCH6_clk_1 = (!nPCI_INTD) & INT_ENA_q[6];
+   assign INT_LATCH7_clk_1 = DSP_INT & INT_ENA_q[7];
+   assign INT_LATCH8_clk_1 = VSYNC & INT_ENA_q[8];
+   assign INT_LATCH9_clk_1 = HSYNC & INT_ENA_q[9];*/
+	 
+	 //GE Latch -> FF
+	 assign INT_LATCH_d[31:10] = 22'b11_1111_1111_1111_1111_1111;
+	 assign INT_LATCH_d[0] = PIC_INT & INT_ENA_q[0];
+   assign INT_LATCH_d[1] = E0_INT & INT_ENA_q[1];
+   assign INT_LATCH_d[2] = DVI_INT & INT_ENA_q[2];
+   assign INT_LATCH_d[3] = (!nPCI_INTA) & INT_ENA_q[3];
+   assign INT_LATCH_d[4] = (!nPCI_INTB) & INT_ENA_q[4];
+   assign INT_LATCH_d[5] = (!nPCI_INTC) & INT_ENA_q[5];
+   assign INT_LATCH_d[6] = (!nPCI_INTD) & INT_ENA_q[6];
+   assign INT_LATCH_d[7] = DSP_INT & INT_ENA_q[7];
+   assign INT_LATCH_d[8] = VSYNC & INT_ENA_q[8];
+   assign INT_LATCH_d[9] = HSYNC & INT_ENA_q[9];
+	 
+//  INTERRUPT CLEAR
+   assign {INT_LATCH31_clrn, INT_LATCH30_clrn, INT_LATCH29_clrn,
+	 INT_LATCH28_clrn, INT_LATCH27_clrn, INT_LATCH26_clrn,
+	 INT_LATCH25_clrn, INT_LATCH24_clrn, INT_LATCH23_clrn,
+	 INT_LATCH22_clrn, INT_LATCH21_clrn, INT_LATCH20_clrn,
+	 INT_LATCH19_clrn, INT_LATCH18_clrn, INT_LATCH17_clrn,
+	 INT_LATCH16_clrn, INT_LATCH15_clrn, INT_LATCH14_clrn,
+	 INT_LATCH13_clrn, INT_LATCH12_clrn, INT_LATCH11_clrn,
+	 INT_LATCH10_clrn, INT_LATCH9_clrn, INT_LATCH8_clrn, INT_LATCH7_clrn,
+	 INT_LATCH6_clrn, INT_LATCH5_clrn, INT_LATCH4_clrn, INT_LATCH3_clrn,
+	 INT_LATCH2_clrn, INT_LATCH1_clrn, INT_LATCH0_clrn} = ~INT_CLEAR_q;
+
+//  INT_IN
+   assign INT_IN[0] = PIC_INT;
+   assign INT_IN[1] = E0_INT;
+   assign INT_IN[2] = DVI_INT;
+   assign INT_IN[3] = !nPCI_INTA;
+   assign INT_IN[4] = !nPCI_INTB;
+   assign INT_IN[5] = !nPCI_INTC;
+   assign INT_IN[6] = !nPCI_INTD;
+   assign INT_IN[7] = DSP_INT;
+   assign INT_IN[8] = VSYNC;
+   assign INT_IN[9] = HSYNC;
+   assign INT_IN[25:10] = 16'h0;
+   assign INT_IN[26] = HSYNC;
+   assign INT_IN[27] = INT_CTR_q[0];
+   assign INT_IN[28] = VSYNC;
+   assign INT_IN[29] = INT_LATCH_q != 32'h0;
+   assign INT_IN[30] = !nMFP_INT;
+   assign INT_IN[31] = DMA_DRQ;
+
+// ***************************************************************************************
+//  ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE
+   assign ACP_CONF0_clk_ctrl = MAIN_CLK;
+
+//  $4'0000/4
+   assign ACP_CONF_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h1_0000;
+   assign ACP_CONF_d = FB_AD;
+   assign ACP_CONF24_ena_ctrl = ACP_CONF_CS & FB_B[0] & (!nFB_WR);
+   assign ACP_CONF16_ena_ctrl = ACP_CONF_CS & FB_B[1] & (!nFB_WR);
+   assign ACP_CONF8_ena_ctrl = ACP_CONF_CS & FB_B[2] & (!nFB_WR);
+   assign ACP_CONF0_ena_ctrl = ACP_CONF_CS & FB_B[3] & (!nFB_WR);
+
+// ***************************************************************************************
+// ------------------------------------------------------------
+//  C1287   0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR
+// --------------------------------------------------------
+   assign RTC_ADR0_clk_ctrl = MAIN_CLK;
+   assign RTC_ADR_d = FB_AD[21:16];
+
+//  FFFF8961
+   assign UHR_AS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C4B0 & FB_B[1];
+
+//  FFFF8963
+   assign UHR_DS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C4B1 & FB_B[3];
+   assign RTC_ADR0_ena_ctrl = UHR_AS & (!nFB_WR);
+   assign WERTE7_0_clk_ctrl = MAIN_CLK;
+   assign WERTE6_0_clk_ctrl = MAIN_CLK;
+   assign WERTE5_0_clk_ctrl = MAIN_CLK;
+   assign WERTE4_0_clk_ctrl = MAIN_CLK;
+   assign WERTE3_0_clk_ctrl = MAIN_CLK;
+   assign WERTE2_0_clk_ctrl = MAIN_CLK;
+   assign WERTE1_0_clk_ctrl = MAIN_CLK;
+   assign WERTE0_0_clk_ctrl = MAIN_CLK;
+   assign {WERTE7_0_d_1, WERTE6_0_d_1, WERTE5_0_d_1, WERTE4_0_d_1,
+	 WERTE3_0_d_1, WERTE2_0_d_1, WERTE1_0_d_1, WERTE0_0_d_1} = FB_AD[23:16]
+	 & {8{RTC_ADR_q == 6'b00_0000}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7__d[1], WERTE6__d[1], WERTE5__d[1], WERTE4__d[1],
+	 WERTE3__d[1], WERTE2__d[1], WERTE1__d[1], WERTE0__d[1]} =
+	 FB_AD[23:16];
+   assign {WERTE7_2_d_1, WERTE6_2_d_1, WERTE5_2_d_1, WERTE4_2_d_1,
+	 WERTE3_2_d_1, WERTE2_2_d_1, WERTE1_2_d_1, WERTE0_2_d_1} = FB_AD[23:16]
+	 & {8{RTC_ADR_q == 6'b00_0010}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7__d[3], WERTE6__d[3], WERTE5__d[3], WERTE4__d[3],
+	 WERTE3__d[3], WERTE2__d[3], WERTE1__d[3], WERTE0__d[3]} =
+	 FB_AD[23:16];
+   assign {WERTE7_4_d_1, WERTE6_4_d_1, WERTE5_4_d_1, WERTE4_4_d_1,
+	 WERTE3_4_d_1, WERTE2_4_d_1, WERTE1_4_d_1, WERTE0_4_d_1} = FB_AD[23:16]
+	 & {8{RTC_ADR_q == 6'b00_0100}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7__d[5], WERTE6__d[5], WERTE5__d[5], WERTE4__d[5],
+	 WERTE3__d[5], WERTE2__d[5], WERTE1__d[5], WERTE0__d[5]} =
+	 FB_AD[23:16];
+   assign {WERTE7_6_d_1, WERTE6_6_d_1, WERTE5_6_d_1, WERTE4_6_d_1,
+	 WERTE3_6_d_1, WERTE2_6_d_1, WERTE1_6_d_1, WERTE0_6_d_1} = FB_AD[23:16]
+	 & {8{RTC_ADR_q == 6'b00_0110}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7_7_d_1, WERTE6_7_d_1, WERTE5_7_d_1, WERTE4_7_d_1,
+	 WERTE3_7_d_1, WERTE2_7_d_1, WERTE1_7_d_1, WERTE0_7_d_1} = FB_AD[23:16]
+	 & {8{RTC_ADR_q == 6'b00_0111}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7_8_d_1, WERTE6_8_d_1, WERTE5_8_d_1, WERTE4_8_d_1,
+	 WERTE3_8_d_1, WERTE2_8_d_1, WERTE1_8_d_1, WERTE0_8_d_1} = FB_AD[23:16]
+	 & {8{RTC_ADR_q == 6'b00_1000}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7_9_d_1, WERTE6_9_d_1, WERTE5_9_d_1, WERTE4_9_d_1,
+	 WERTE3_9_d_1, WERTE2_9_d_1, WERTE1_9_d_1, WERTE0_9_d_1} = FB_AD[23:16]
+	 & {8{RTC_ADR_q == 6'b00_1001}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7__d[10], WERTE6__d[10], WERTE5__d[10], WERTE4__d[10],
+	 WERTE3__d[10], WERTE2__d[10], WERTE1__d[10], WERTE0__d[10]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[11], WERTE6__d[11], WERTE5__d[11], WERTE4__d[11],
+	 WERTE3__d[11], WERTE2_11_d_1, WERTE1_11_d_1, WERTE0_11_d_1} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[12], WERTE6__d[12], WERTE5__d[12], WERTE4__d[12],
+	 WERTE3__d[12], WERTE2__d[12], WERTE1__d[12], WERTE0__d[12]} =
+	 FB_AD[23:16];
+   assign {WERTE7_13_d_1, WERTE6__d[13], WERTE5__d[13], WERTE4__d[13],
+	 WERTE3__d[13], WERTE2__d[13], WERTE1__d[13], WERTE0_13_d_1} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[14], WERTE6__d[14], WERTE5__d[14], WERTE4__d[14],
+	 WERTE3__d[14], WERTE2__d[14], WERTE1__d[14], WERTE0__d[14]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[15], WERTE6__d[15], WERTE5__d[15], WERTE4__d[15],
+	 WERTE3__d[15], WERTE2__d[15], WERTE1__d[15], WERTE0__d[15]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[16], WERTE6__d[16], WERTE5__d[16], WERTE4__d[16],
+	 WERTE3__d[16], WERTE2__d[16], WERTE1__d[16], WERTE0__d[16]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[17], WERTE6__d[17], WERTE5__d[17], WERTE4__d[17],
+	 WERTE3__d[17], WERTE2__d[17], WERTE1__d[17], WERTE0__d[17]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[18], WERTE6__d[18], WERTE5__d[18], WERTE4__d[18],
+	 WERTE3__d[18], WERTE2__d[18], WERTE1__d[18], WERTE0__d[18]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[19], WERTE6__d[19], WERTE5__d[19], WERTE4__d[19],
+	 WERTE3__d[19], WERTE2__d[19], WERTE1__d[19], WERTE0__d[19]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[20], WERTE6__d[20], WERTE5__d[20], WERTE4__d[20],
+	 WERTE3__d[20], WERTE2__d[20], WERTE1__d[20], WERTE0__d[20]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[21], WERTE6__d[21], WERTE5__d[21], WERTE4__d[21],
+	 WERTE3__d[21], WERTE2__d[21], WERTE1__d[21], WERTE0__d[21]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[22], WERTE6__d[22], WERTE5__d[22], WERTE4__d[22],
+	 WERTE3__d[22], WERTE2__d[22], WERTE1__d[22], WERTE0__d[22]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[23], WERTE6__d[23], WERTE5__d[23], WERTE4__d[23],
+	 WERTE3__d[23], WERTE2__d[23], WERTE1__d[23], WERTE0__d[23]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[24], WERTE6__d[24], WERTE5__d[24], WERTE4__d[24],
+	 WERTE3__d[24], WERTE2__d[24], WERTE1__d[24], WERTE0__d[24]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[25], WERTE6__d[25], WERTE5__d[25], WERTE4__d[25],
+	 WERTE3__d[25], WERTE2__d[25], WERTE1__d[25], WERTE0__d[25]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[26], WERTE6__d[26], WERTE5__d[26], WERTE4__d[26],
+	 WERTE3__d[26], WERTE2__d[26], WERTE1__d[26], WERTE0__d[26]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[27], WERTE6__d[27], WERTE5__d[27], WERTE4__d[27],
+	 WERTE3__d[27], WERTE2__d[27], WERTE1__d[27], WERTE0__d[27]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[28], WERTE6__d[28], WERTE5__d[28], WERTE4__d[28],
+	 WERTE3__d[28], WERTE2__d[28], WERTE1__d[28], WERTE0__d[28]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[29], WERTE6__d[29], WERTE5__d[29], WERTE4__d[29],
+	 WERTE3__d[29], WERTE2__d[29], WERTE1__d[29], WERTE0__d[29]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[30], WERTE6__d[30], WERTE5__d[30], WERTE4__d[30],
+	 WERTE3__d[30], WERTE2__d[30], WERTE1__d[30], WERTE0__d[30]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[31], WERTE6__d[31], WERTE5__d[31], WERTE4__d[31],
+	 WERTE3__d[31], WERTE2__d[31], WERTE1__d[31], WERTE0__d[31]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[32], WERTE6__d[32], WERTE5__d[32], WERTE4__d[32],
+	 WERTE3__d[32], WERTE2__d[32], WERTE1__d[32], WERTE0__d[32]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[33], WERTE6__d[33], WERTE5__d[33], WERTE4__d[33],
+	 WERTE3__d[33], WERTE2__d[33], WERTE1__d[33], WERTE0__d[33]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[34], WERTE6__d[34], WERTE5__d[34], WERTE4__d[34],
+	 WERTE3__d[34], WERTE2__d[34], WERTE1__d[34], WERTE0__d[34]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[35], WERTE6__d[35], WERTE5__d[35], WERTE4__d[35],
+	 WERTE3__d[35], WERTE2__d[35], WERTE1__d[35], WERTE0__d[35]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[36], WERTE6__d[36], WERTE5__d[36], WERTE4__d[36],
+	 WERTE3__d[36], WERTE2__d[36], WERTE1__d[36], WERTE0__d[36]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[37], WERTE6__d[37], WERTE5__d[37], WERTE4__d[37],
+	 WERTE3__d[37], WERTE2__d[37], WERTE1__d[37], WERTE0__d[37]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[38], WERTE6__d[38], WERTE5__d[38], WERTE4__d[38],
+	 WERTE3__d[38], WERTE2__d[38], WERTE1__d[38], WERTE0__d[38]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[39], WERTE6__d[39], WERTE5__d[39], WERTE4__d[39],
+	 WERTE3__d[39], WERTE2__d[39], WERTE1__d[39], WERTE0__d[39]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[40], WERTE6__d[40], WERTE5__d[40], WERTE4__d[40],
+	 WERTE3__d[40], WERTE2__d[40], WERTE1__d[40], WERTE0__d[40]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[41], WERTE6__d[41], WERTE5__d[41], WERTE4__d[41],
+	 WERTE3__d[41], WERTE2__d[41], WERTE1__d[41], WERTE0__d[41]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[42], WERTE6__d[42], WERTE5__d[42], WERTE4__d[42],
+	 WERTE3__d[42], WERTE2__d[42], WERTE1__d[42], WERTE0__d[42]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[43], WERTE6__d[43], WERTE5__d[43], WERTE4__d[43],
+	 WERTE3__d[43], WERTE2__d[43], WERTE1__d[43], WERTE0__d[43]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[44], WERTE6__d[44], WERTE5__d[44], WERTE4__d[44],
+	 WERTE3__d[44], WERTE2__d[44], WERTE1__d[44], WERTE0__d[44]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[45], WERTE6__d[45], WERTE5__d[45], WERTE4__d[45],
+	 WERTE3__d[45], WERTE2__d[45], WERTE1__d[45], WERTE0__d[45]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[46], WERTE6__d[46], WERTE5__d[46], WERTE4__d[46],
+	 WERTE3__d[46], WERTE2__d[46], WERTE1__d[46], WERTE0__d[46]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[47], WERTE6__d[47], WERTE5__d[47], WERTE4__d[47],
+	 WERTE3__d[47], WERTE2__d[47], WERTE1__d[47], WERTE0__d[47]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[48], WERTE6__d[48], WERTE5__d[48], WERTE4__d[48],
+	 WERTE3__d[48], WERTE2__d[48], WERTE1__d[48], WERTE0__d[48]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[49], WERTE6__d[49], WERTE5__d[49], WERTE4__d[49],
+	 WERTE3__d[49], WERTE2__d[49], WERTE1__d[49], WERTE0__d[49]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[50], WERTE6__d[50], WERTE5__d[50], WERTE4__d[50],
+	 WERTE3__d[50], WERTE2__d[50], WERTE1__d[50], WERTE0__d[50]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[51], WERTE6__d[51], WERTE5__d[51], WERTE4__d[51],
+	 WERTE3__d[51], WERTE2__d[51], WERTE1__d[51], WERTE0__d[51]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[52], WERTE6__d[52], WERTE5__d[52], WERTE4__d[52],
+	 WERTE3__d[52], WERTE2__d[52], WERTE1__d[52], WERTE0__d[52]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[53], WERTE6__d[53], WERTE5__d[53], WERTE4__d[53],
+	 WERTE3__d[53], WERTE2__d[53], WERTE1__d[53], WERTE0__d[53]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[54], WERTE6__d[54], WERTE5__d[54], WERTE4__d[54],
+	 WERTE3__d[54], WERTE2__d[54], WERTE1__d[54], WERTE0__d[54]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[55], WERTE6__d[55], WERTE5__d[55], WERTE4__d[55],
+	 WERTE3__d[55], WERTE2__d[55], WERTE1__d[55], WERTE0__d[55]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[56], WERTE6__d[56], WERTE5__d[56], WERTE4__d[56],
+	 WERTE3__d[56], WERTE2__d[56], WERTE1__d[56], WERTE0__d[56]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[57], WERTE6__d[57], WERTE5__d[57], WERTE4__d[57],
+	 WERTE3__d[57], WERTE2__d[57], WERTE1__d[57], WERTE0__d[57]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[58], WERTE6__d[58], WERTE5__d[58], WERTE4__d[58],
+	 WERTE3__d[58], WERTE2__d[58], WERTE1__d[58], WERTE0__d[58]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[59], WERTE6__d[59], WERTE5__d[59], WERTE4__d[59],
+	 WERTE3__d[59], WERTE2__d[59], WERTE1__d[59], WERTE0__d[59]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[60], WERTE6__d[60], WERTE5__d[60], WERTE4__d[60],
+	 WERTE3__d[60], WERTE2__d[60], WERTE1__d[60], WERTE0__d[60]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[61], WERTE6__d[61], WERTE5__d[61], WERTE4__d[61],
+	 WERTE3__d[61], WERTE2__d[61], WERTE1__d[61], WERTE0__d[61]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[62], WERTE6__d[62], WERTE5__d[62], WERTE4__d[62],
+	 WERTE3__d[62], WERTE2__d[62], WERTE1__d[62], WERTE0__d[62]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[63], WERTE6__d[63], WERTE5__d[63], WERTE4__d[63],
+	 WERTE3__d[63], WERTE2__d[63], WERTE1__d[63], WERTE0__d[63]} =
+	 FB_AD[23:16];
+   assign {WERTE7_0_ena_1, WERTE6_0_ena_1, WERTE5_0_ena_1, WERTE4_0_ena_1,
+	 WERTE3_0_ena_1, WERTE2_0_ena_1, WERTE1_0_ena_1, WERTE0_0_ena_1} =
+	 {8{RTC_ADR_q == 6'b00_0000}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign WERTE0_1_ena_ctrl = RTC_ADR_q == 6'b00_0001 & UHR_DS & (!nFB_WR);
+   assign {WERTE7_2_ena_1, WERTE6_2_ena_1, WERTE5_2_ena_1, WERTE4_2_ena_1,
+	 WERTE3_2_ena_1, WERTE2_2_ena_1, WERTE1_2_ena_1, WERTE0_2_ena_1} =
+	 {8{RTC_ADR_q == 6'b00_0010}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign WERTE0_3_ena_ctrl = RTC_ADR_q == 6'b00_0011 & UHR_DS & (!nFB_WR);
+   assign {WERTE7_4_ena_1, WERTE6_4_ena_1, WERTE5_4_ena_1, WERTE4_4_ena_1,
+	 WERTE3_4_ena_1, WERTE2_4_ena_1, WERTE1_4_ena_1, WERTE0_4_ena_1} =
+	 {8{RTC_ADR_q == 6'b00_0100}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign WERTE0_5_ena_ctrl = RTC_ADR_q == 6'b00_0101 & UHR_DS & (!nFB_WR);
+   assign {WERTE7_6_ena_1, WERTE6_6_ena_1, WERTE5_6_ena_1, WERTE4_6_ena_1,
+	 WERTE3_6_ena_1, WERTE2_6_ena_1, WERTE1_6_ena_1, WERTE0_6_ena_1} =
+	 {8{RTC_ADR_q == 6'b00_0110}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7_7_ena_1, WERTE6_7_ena_1, WERTE5_7_ena_1, WERTE4_7_ena_1,
+	 WERTE3_7_ena_1, WERTE2_7_ena_1, WERTE1_7_ena_1, WERTE0_7_ena_1} =
+	 {8{RTC_ADR_q == 6'b00_0111}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7_8_ena_1, WERTE6_8_ena_1, WERTE5_8_ena_1, WERTE4_8_ena_1,
+	 WERTE3_8_ena_1, WERTE2_8_ena_1, WERTE1_8_ena_1, WERTE0_8_ena_1} =
+	 {8{RTC_ADR_q == 6'b00_1000}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7_9_ena_1, WERTE6_9_ena_1, WERTE5_9_ena_1, WERTE4_9_ena_1,
+	 WERTE3_9_ena_1, WERTE2_9_ena_1, WERTE1_9_ena_1, WERTE0_9_ena_1} =
+	 {8{RTC_ADR_q == 6'b00_1001}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign WERTE0_10_ena_ctrl = RTC_ADR_q == 6'b00_1010 & UHR_DS & (!nFB_WR);
+   assign WERTE0_11_ena_ctrl = RTC_ADR_q == 6'b00_1011 & UHR_DS & (!nFB_WR);
+   assign WERTE0_12_ena_ctrl = RTC_ADR_q == 6'b00_1100 & UHR_DS & (!nFB_WR);
+   assign {WERTE7_13_ena, WERTE6_13_ena, WERTE5_13_ena, WERTE4_13_ena,
+	 WERTE3_13_ena, WERTE2_13_ena, WERTE1_13_ena, WERTE0_13_ena_1} =
+	 {8{RTC_ADR_q == 6'b00_1101}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign WERTE0_14_ena_ctrl = RTC_ADR_q == 6'b00_1110 & UHR_DS & (!nFB_WR);
+   assign WERTE0_15_ena_ctrl = RTC_ADR_q == 6'b00_1111 & UHR_DS & (!nFB_WR);
+   assign WERTE0_16_ena_ctrl = RTC_ADR_q == 6'b01_0000 & UHR_DS & (!nFB_WR);
+   assign WERTE0_17_ena_ctrl = RTC_ADR_q == 6'b01_0001 & UHR_DS & (!nFB_WR);
+   assign WERTE0_18_ena_ctrl = RTC_ADR_q == 6'b01_0010 & UHR_DS & (!nFB_WR);
+   assign WERTE0_19_ena_ctrl = RTC_ADR_q == 6'b01_0011 & UHR_DS & (!nFB_WR);
+   assign WERTE0_20_ena_ctrl = RTC_ADR_q == 6'b01_0100 & UHR_DS & (!nFB_WR);
+   assign WERTE0_21_ena_ctrl = RTC_ADR_q == 6'b01_0101 & UHR_DS & (!nFB_WR);
+   assign WERTE0_22_ena_ctrl = RTC_ADR_q == 6'b01_0110 & UHR_DS & (!nFB_WR);
+   assign WERTE0_23_ena_ctrl = RTC_ADR_q == 6'b01_0111 & UHR_DS & (!nFB_WR);
+   assign WERTE0_24_ena_ctrl = RTC_ADR_q == 6'b01_1000 & UHR_DS & (!nFB_WR);
+   assign WERTE0_25_ena_ctrl = RTC_ADR_q == 6'b01_1001 & UHR_DS & (!nFB_WR);
+   assign WERTE0_26_ena_ctrl = RTC_ADR_q == 6'b01_1010 & UHR_DS & (!nFB_WR);
+   assign WERTE0_27_ena_ctrl = RTC_ADR_q == 6'b01_1011 & UHR_DS & (!nFB_WR);
+   assign WERTE0_28_ena_ctrl = RTC_ADR_q == 6'b01_1100 & UHR_DS & (!nFB_WR);
+   assign WERTE0_29_ena_ctrl = RTC_ADR_q == 6'b01_1101 & UHR_DS & (!nFB_WR);
+   assign WERTE0_30_ena_ctrl = RTC_ADR_q == 6'b01_1110 & UHR_DS & (!nFB_WR);
+   assign WERTE0_31_ena_ctrl = RTC_ADR_q == 6'b01_1111 & UHR_DS & (!nFB_WR);
+   assign WERTE0_32_ena_ctrl = RTC_ADR_q == 6'b10_0000 & UHR_DS & (!nFB_WR);
+   assign WERTE0_33_ena_ctrl = RTC_ADR_q == 6'b10_0001 & UHR_DS & (!nFB_WR);
+   assign WERTE0_34_ena_ctrl = RTC_ADR_q == 6'b10_0010 & UHR_DS & (!nFB_WR);
+   assign WERTE0_35_ena_ctrl = RTC_ADR_q == 6'b10_0011 & UHR_DS & (!nFB_WR);
+   assign WERTE0_36_ena_ctrl = RTC_ADR_q == 6'b10_0100 & UHR_DS & (!nFB_WR);
+   assign WERTE0_37_ena_ctrl = RTC_ADR_q == 6'b10_0101 & UHR_DS & (!nFB_WR);
+   assign WERTE0_38_ena_ctrl = RTC_ADR_q == 6'b10_0110 & UHR_DS & (!nFB_WR);
+   assign WERTE0_39_ena_ctrl = RTC_ADR_q == 6'b10_0111 & UHR_DS & (!nFB_WR);
+   assign WERTE0_40_ena_ctrl = RTC_ADR_q == 6'b10_1000 & UHR_DS & (!nFB_WR);
+   assign WERTE0_41_ena_ctrl = RTC_ADR_q == 6'b10_1001 & UHR_DS & (!nFB_WR);
+   assign WERTE0_42_ena_ctrl = RTC_ADR_q == 6'b10_1010 & UHR_DS & (!nFB_WR);
+   assign WERTE0_43_ena_ctrl = RTC_ADR_q == 6'b10_1011 & UHR_DS & (!nFB_WR);
+   assign WERTE0_44_ena_ctrl = RTC_ADR_q == 6'b10_1100 & UHR_DS & (!nFB_WR);
+   assign WERTE0_45_ena_ctrl = RTC_ADR_q == 6'b10_1101 & UHR_DS & (!nFB_WR);
+   assign WERTE0_46_ena_ctrl = RTC_ADR_q == 6'b10_1110 & UHR_DS & (!nFB_WR);
+   assign WERTE0_47_ena_ctrl = RTC_ADR_q == 6'b10_1111 & UHR_DS & (!nFB_WR);
+   assign WERTE0_48_ena_ctrl = RTC_ADR_q == 6'b11_0000 & UHR_DS & (!nFB_WR);
+   assign WERTE0_49_ena_ctrl = RTC_ADR_q == 6'b11_0001 & UHR_DS & (!nFB_WR);
+   assign WERTE0_50_ena_ctrl = RTC_ADR_q == 6'b11_0010 & UHR_DS & (!nFB_WR);
+   assign WERTE0_51_ena_ctrl = RTC_ADR_q == 6'b11_0011 & UHR_DS & (!nFB_WR);
+   assign WERTE0_52_ena_ctrl = RTC_ADR_q == 6'b11_0100 & UHR_DS & (!nFB_WR);
+   assign WERTE0_53_ena_ctrl = RTC_ADR_q == 6'b11_0101 & UHR_DS & (!nFB_WR);
+   assign WERTE0_54_ena_ctrl = RTC_ADR_q == 6'b11_0110 & UHR_DS & (!nFB_WR);
+   assign WERTE0_55_ena_ctrl = RTC_ADR_q == 6'b11_0111 & UHR_DS & (!nFB_WR);
+   assign WERTE0_56_ena_ctrl = RTC_ADR_q == 6'b11_1000 & UHR_DS & (!nFB_WR);
+   assign WERTE0_57_ena_ctrl = RTC_ADR_q == 6'b11_1001 & UHR_DS & (!nFB_WR);
+   assign WERTE0_58_ena_ctrl = RTC_ADR_q == 6'b11_1010 & UHR_DS & (!nFB_WR);
+   assign WERTE0_59_ena_ctrl = RTC_ADR_q == 6'b11_1011 & UHR_DS & (!nFB_WR);
+   assign WERTE0_60_ena_ctrl = RTC_ADR_q == 6'b11_1100 & UHR_DS & (!nFB_WR);
+   assign WERTE0_61_ena_ctrl = RTC_ADR_q == 6'b11_1101 & UHR_DS & (!nFB_WR);
+   assign WERTE0_62_ena_ctrl = RTC_ADR_q == 6'b11_1110 & UHR_DS & (!nFB_WR);
+   assign WERTE0_63_ena_ctrl = RTC_ADR_q == 6'b11_1111 & UHR_DS & (!nFB_WR);
+   assign PIC_INT_SYNC0_clk_ctrl = MAIN_CLK;
+   assign PIC_INT_SYNC_d[0] = PIC_INT;
+   assign PIC_INT_SYNC_d[1] = PIC_INT_SYNC_q[0];
+   assign PIC_INT_SYNC_d[2] = (!PIC_INT_SYNC_q[1]) & PIC_INT_SYNC_q[0];
+   assign UPDATE_ON_1 = !WERTE7__q[11];
+
+//  KEIN UIP
+   assign WERTE6_10_clrn = gnd;
+
+//  UPDATE ON OFF
+   assign UPDATE_ON_2 = !WERTE7__q[11];
+
+//  IMMER BINARY
+   assign WERTE2_11_d_2 = vcc;
+
+//  IMMER 24H FORMAT
+   assign WERTE1_11_d_2 = vcc;
+
+//  IMMER SOMMERZEITKORREKTUR
+   assign WERTE0_11_d_2 = vcc;
+
+//  IMMER RICHTIG
+   assign WERTE7_13_d_2 = vcc;
+
+//  SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG)
+// LETZTER SONNTAG IM APRIL
+   assign SOMMERZEIT = {WERTE7__q[6], WERTE6__q[6], WERTE5__q[6], WERTE4__q[6],
+	 WERTE3__q[6], WERTE2__q[6], WERTE1__q[6], WERTE0__q[6]} ==
+	 8'b0000_0001 & {WERTE7__q[4], WERTE6__q[4], WERTE5__q[4],
+	 WERTE4__q[4], WERTE3__q[4], WERTE2__q[4], WERTE1__q[4], WERTE0__q[4]}
+	 == 8'b0000_0001 & {WERTE7__q[8], WERTE6__q[8], WERTE5__q[8],
+	 WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]}
+	 == 8'b0000_0100 & {WERTE7__q[7], WERTE6__q[7], WERTE5__q[7],
+	 WERTE4__q[7], WERTE3__q[7], WERTE2__q[7], WERTE1__q[7], WERTE0__q[7]}
+	 > 8'b0001_0111;
+   assign WERTE0_13_d_2 = SOMMERZEIT;
+   assign WERTE0_13_ena_2 = INC_STD & (SOMMERZEIT | WINTERZEIT);
+
+// LETZTER SONNTAG IM OKTOBER
+   assign WINTERZEIT = {WERTE7__q[6], WERTE6__q[6], WERTE5__q[6], WERTE4__q[6],
+	 WERTE3__q[6], WERTE2__q[6], WERTE1__q[6], WERTE0__q[6]} ==
+	 8'b0000_0001 & {WERTE7__q[4], WERTE6__q[4], WERTE5__q[4],
+	 WERTE4__q[4], WERTE3__q[4], WERTE2__q[4], WERTE1__q[4], WERTE0__q[4]}
+	 == 8'b0000_0001 & {WERTE7__q[8], WERTE6__q[8], WERTE5__q[8],
+	 WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]}
+	 == 8'b0000_1010 & {WERTE7__q[7], WERTE6__q[7], WERTE5__q[7],
+	 WERTE4__q[7], WERTE3__q[7], WERTE2__q[7], WERTE1__q[7], WERTE0__q[7]}
+	 > 8'b0001_1000 & WERTE0__q[13];
+
+//  ACHTELSEKUNDEN
+   assign ACHTELSEKUNDEN0_clk_ctrl = MAIN_CLK;
+   assign ACHTELSEKUNDEN_d = ACHTELSEKUNDEN_q + 3'b001;
+   assign ACHTELSEKUNDEN0_ena_ctrl = PIC_INT_SYNC_q[2] & UPDATE_ON;
+
+//  SEKUNDEN
+   assign INC_SEC = ACHTELSEKUNDEN_q == 3'b111 & PIC_INT_SYNC_q[2] & UPDATE_ON;
+
+//  SEKUNDEN ZÄHLEN BIS 59
+   assign {WERTE7_0_d_2, WERTE6_0_d_2, WERTE5_0_d_2, WERTE4_0_d_2,
+	 WERTE3_0_d_2, WERTE2_0_d_2, WERTE1_0_d_2, WERTE0_0_d_2} =
+	 ({WERTE7__q[0], WERTE6__q[0], WERTE5__q[0], WERTE4__q[0],
+	 WERTE3__q[0], WERTE2__q[0], WERTE1__q[0], WERTE0__q[0]} +
+	 8'b0000_0001) & {8{{WERTE7__q[0], WERTE6__q[0], WERTE5__q[0],
+	 WERTE4__q[0], WERTE3__q[0], WERTE2__q[0], WERTE1__q[0], WERTE0__q[0]}
+	 != 8'b0011_1011}} & (~({8{RTC_ADR_q == 6'b00_0000}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}));
+   assign {WERTE7_0_ena_2, WERTE6_0_ena_2, WERTE5_0_ena_2, WERTE4_0_ena_2,
+	 WERTE3_0_ena_2, WERTE2_0_ena_2, WERTE1_0_ena_2, WERTE0_0_ena_2} =
+	 {8{INC_SEC}} & (~({8{RTC_ADR_q == 6'b00_0000}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}));
+
+//  MINUTEN
+   assign INC_MIN = INC_SEC & {WERTE7__q[0], WERTE6__q[0], WERTE5__q[0],
+	 WERTE4__q[0], WERTE3__q[0], WERTE2__q[0], WERTE1__q[0], WERTE0__q[0]}
+	 == 8'b0011_1011;
+
+//  MINUTEN ZÄHLEN BIS 59
+   assign {WERTE7_2_d_2, WERTE6_2_d_2, WERTE5_2_d_2, WERTE4_2_d_2,
+	 WERTE3_2_d_2, WERTE2_2_d_2, WERTE1_2_d_2, WERTE0_2_d_2} =
+	 ({WERTE7__q[2], WERTE6__q[2], WERTE5__q[2], WERTE4__q[2],
+	 WERTE3__q[2], WERTE2__q[2], WERTE1__q[2], WERTE0__q[2]} +
+	 8'b0000_0001) & {8{{WERTE7__q[2], WERTE6__q[2], WERTE5__q[2],
+	 WERTE4__q[2], WERTE3__q[2], WERTE2__q[2], WERTE1__q[2], WERTE0__q[2]}
+	 != 8'b0011_1011}} & (~({8{RTC_ADR_q == 6'b00_0010}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}));
+   assign {WERTE7_2_ena_2, WERTE6_2_ena_2, WERTE5_2_ena_2, WERTE4_2_ena_2,
+	 WERTE3_2_ena_2, WERTE2_2_ena_2, WERTE1_2_ena_2, WERTE0_2_ena_2} =
+	 {8{INC_MIN}} & (~({8{RTC_ADR_q == 6'b00_0010}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}));
+
+//  STUNDEN
+   assign INC_STD = INC_MIN & {WERTE7__q[2], WERTE6__q[2], WERTE5__q[2],
+	 WERTE4__q[2], WERTE3__q[2], WERTE2__q[2], WERTE1__q[2], WERTE0__q[2]}
+	 == 8'b0011_1011;
+
+//  STUNDEN ZÄHLEN BIS 23
+   assign {WERTE7_4_d_2, WERTE6_4_d_2, WERTE5_4_d_2, WERTE4_4_d_2,
+	 WERTE3_4_d_2, WERTE2_4_d_2, WERTE1_4_d_2, WERTE0_4_d_2} =
+	 (({WERTE7__q[4], WERTE6__q[4], WERTE5__q[4], WERTE4__q[4],
+	 WERTE3__q[4], WERTE2__q[4], WERTE1__q[4], WERTE0__q[4]} +
+	 8'b0000_0001) + (8'b0000_0001 & {8{SOMMERZEIT}})) & {8{{WERTE7__q[4],
+	 WERTE6__q[4], WERTE5__q[4], WERTE4__q[4], WERTE3__q[4], WERTE2__q[4],
+	 WERTE1__q[4], WERTE0__q[4]} != 8'b0001_0111}} & (~({8{RTC_ADR_q ==
+	 6'b00_0100}} & {8{UHR_DS}} & {8{!nFB_WR}}));
+
+//  EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT
+   assign {WERTE7_4_ena_2, WERTE6_4_ena_2, WERTE5_4_ena_2, WERTE4_4_ena_2,
+	 WERTE3_4_ena_2, WERTE2_4_ena_2, WERTE1_4_ena_2, WERTE0_4_ena_2} =
+	 {8{INC_STD}} & (~({8{WINTERZEIT}} & {8{WERTE0__q[12]}})) &
+	 (~({8{RTC_ADR_q == 6'b00_0100}} & {8{UHR_DS}} & {8{!nFB_WR}}));
+
+//  WOCHENTAG UND TAG
+   assign INC_TAG = INC_STD & {WERTE7__q[2], WERTE6__q[2], WERTE5__q[2],
+	 WERTE4__q[2], WERTE3__q[2], WERTE2__q[2], WERTE1__q[2], WERTE0__q[2]}
+	 == 8'b0001_0111;
+
+//  WOCHENTAG ZÄHLEN BIS 7
+//  DANN BEI 1 WEITER
+   assign {WERTE7_6_d_2, WERTE6_6_d_2, WERTE5_6_d_2, WERTE4_6_d_2,
+	 WERTE3_6_d_2, WERTE2_6_d_2, WERTE1_6_d_2, WERTE0_6_d_2} =
+	 (({WERTE7__q[6], WERTE6__q[6], WERTE5__q[6], WERTE4__q[6],
+	 WERTE3__q[6], WERTE2__q[6], WERTE1__q[6], WERTE0__q[6]} +
+	 8'b0000_0001) & {8{{WERTE7__q[6], WERTE6__q[6], WERTE5__q[6],
+	 WERTE4__q[6], WERTE3__q[6], WERTE2__q[6], WERTE1__q[6], WERTE0__q[6]}
+	 != 8'b0000_0111}} & (~({8{RTC_ADR_q == 6'b00_0110}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}))) | (8'b0000_0001 & {8{{WERTE7__q[6], WERTE6__q[6],
+	 WERTE5__q[6], WERTE4__q[6], WERTE3__q[6], WERTE2__q[6], WERTE1__q[6],
+	 WERTE0__q[6]} == 8'b0000_0111}} & (~({8{RTC_ADR_q == 6'b00_0110}} &
+	 {8{UHR_DS}} & {8{!nFB_WR}})));
+   assign {WERTE7_6_ena_2, WERTE6_6_ena_2, WERTE5_6_ena_2, WERTE4_6_ena_2,
+	 WERTE3_6_ena_2, WERTE2_6_ena_2, WERTE1_6_ena_2, WERTE0_6_ena_2} =
+	 {8{INC_TAG}} & (~({8{RTC_ADR_q == 6'b00_0110}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}));
+   assign ANZAHL_TAGE_DES_MONATS = (8'b0001_1111 & ({8{{WERTE7__q[8],
+	 WERTE6__q[8], WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8],
+	 WERTE1__q[8], WERTE0__q[8]} == 8'b0000_0001}} | {8{{WERTE7__q[8],
+	 WERTE6__q[8], WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8],
+	 WERTE1__q[8], WERTE0__q[8]} == 8'b0000_0011}} | {8{{WERTE7__q[8],
+	 WERTE6__q[8], WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8],
+	 WERTE1__q[8], WERTE0__q[8]} == 8'b0000_0101}} | {8{{WERTE7__q[8],
+	 WERTE6__q[8], WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8],
+	 WERTE1__q[8], WERTE0__q[8]} == 8'b0000_0111}} | {8{{WERTE7__q[8],
+	 WERTE6__q[8], WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8],
+	 WERTE1__q[8], WERTE0__q[8]} == 8'b0000_1000}} | {8{{WERTE7__q[8],
+	 WERTE6__q[8], WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8],
+	 WERTE1__q[8], WERTE0__q[8]} == 8'b0000_1010}} | {8{{WERTE7__q[8],
+	 WERTE6__q[8], WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8],
+	 WERTE1__q[8], WERTE0__q[8]} == 8'b0000_1100}})) | (8'b0001_1110 &
+	 ({8{{WERTE7__q[8], WERTE6__q[8], WERTE5__q[8], WERTE4__q[8],
+	 WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]} ==
+	 8'b0000_0100}} | {8{{WERTE7__q[8], WERTE6__q[8], WERTE5__q[8],
+	 WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]}
+	 == 8'b0000_0110}} | {8{{WERTE7__q[8], WERTE6__q[8], WERTE5__q[8],
+	 WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]}
+	 == 8'b0000_1001}} | {8{{WERTE7__q[8], WERTE6__q[8], WERTE5__q[8],
+	 WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]}
+	 == 8'b0000_1011}})) | (8'b0001_1101 & {8{{WERTE7__q[8], WERTE6__q[8],
+	 WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8],
+	 WERTE0__q[8]} == 8'b0000_0010}} & {8{{WERTE1__q[9], WERTE0__q[9]} ==
+	 2'b00}}) | (8'b0001_1100 & {8{{WERTE7__q[8], WERTE6__q[8],
+	 WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8],
+	 WERTE0__q[8]} == 8'b0000_0010}} & {8{{WERTE1__q[9], WERTE0__q[9]} !=
+	 2'b00}});
+
+//  TAG ZÄHLEN BIS MONATSENDE
+//  DANN BEI 1 WEITER
+   assign {WERTE7_7_d_2, WERTE6_7_d_2, WERTE5_7_d_2, WERTE4_7_d_2,
+	 WERTE3_7_d_2, WERTE2_7_d_2, WERTE1_7_d_2, WERTE0_7_d_2} =
+	 (({WERTE7__q[7], WERTE6__q[7], WERTE5__q[7], WERTE4__q[7],
+	 WERTE3__q[7], WERTE2__q[7], WERTE1__q[7], WERTE0__q[7]} +
+	 8'b0000_0001) & {8{{WERTE7__q[7], WERTE6__q[7], WERTE5__q[7],
+	 WERTE4__q[7], WERTE3__q[7], WERTE2__q[7], WERTE1__q[7], WERTE0__q[7]}
+	 != ANZAHL_TAGE_DES_MONATS}} & (~({8{RTC_ADR_q == 6'b00_0111}} &
+	 {8{UHR_DS}} & {8{!nFB_WR}}))) | (8'b0000_0001 & {8{{WERTE7__q[7],
+	 WERTE6__q[7], WERTE5__q[7], WERTE4__q[7], WERTE3__q[7], WERTE2__q[7],
+	 WERTE1__q[7], WERTE0__q[7]} == ANZAHL_TAGE_DES_MONATS}} &
+	 (~({8{RTC_ADR_q == 6'b00_0111}} & {8{UHR_DS}} & {8{!nFB_WR}})));
+   assign {WERTE7_7_ena_2, WERTE6_7_ena_2, WERTE5_7_ena_2, WERTE4_7_ena_2,
+	 WERTE3_7_ena_2, WERTE2_7_ena_2, WERTE1_7_ena_2, WERTE0_7_ena_2} =
+	 {8{INC_TAG}} & (~({8{RTC_ADR_q == 6'b00_0111}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}));
+
+//  MONATE
+   assign INC_MONAT = INC_TAG & {WERTE7__q[7], WERTE6__q[7], WERTE5__q[7],
+	 WERTE4__q[7], WERTE3__q[7], WERTE2__q[7], WERTE1__q[7], WERTE0__q[7]}
+	 == ANZAHL_TAGE_DES_MONATS;
+
+//  MONATE ZÄHLEN BIS 12
+//  DANN BEI 1 WEITER
+   assign {WERTE7_8_d_2, WERTE6_8_d_2, WERTE5_8_d_2, WERTE4_8_d_2,
+	 WERTE3_8_d_2, WERTE2_8_d_2, WERTE1_8_d_2, WERTE0_8_d_2} =
+	 (({WERTE7__q[8], WERTE6__q[8], WERTE5__q[8], WERTE4__q[8],
+	 WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]} +
+	 8'b0000_0001) & {8{{WERTE7__q[8], WERTE6__q[8], WERTE5__q[8],
+	 WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]}
+	 != 8'b0000_1100}} & (~({8{RTC_ADR_q == 6'b00_1000}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}))) | (8'b0000_0001 & {8{{WERTE7__q[8], WERTE6__q[8],
+	 WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8],
+	 WERTE0__q[8]} == 8'b0000_1100}} & (~({8{RTC_ADR_q == 6'b00_1000}} &
+	 {8{UHR_DS}} & {8{!nFB_WR}})));
+   assign {WERTE7_8_ena_2, WERTE6_8_ena_2, WERTE5_8_ena_2, WERTE4_8_ena_2,
+	 WERTE3_8_ena_2, WERTE2_8_ena_2, WERTE1_8_ena_2, WERTE0_8_ena_2} =
+	 {8{INC_MONAT}} & (~({8{RTC_ADR_q == 6'b00_1000}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}));
+
+//  JAHR
+   assign INC_JAHR = INC_MONAT & {WERTE7__q[8], WERTE6__q[8], WERTE5__q[8],
+	 WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]}
+	 == 8'b0000_1100;
+
+//  JAHRE ZÄHLEN BIS 99
+   assign {WERTE7_9_d_2, WERTE6_9_d_2, WERTE5_9_d_2, WERTE4_9_d_2,
+	 WERTE3_9_d_2, WERTE2_9_d_2, WERTE1_9_d_2, WERTE0_9_d_2} =
+	 ({WERTE7__q[9], WERTE6__q[9], WERTE5__q[9], WERTE4__q[9],
+	 WERTE3__q[9], WERTE2__q[9], WERTE1__q[9], WERTE0__q[9]} +
+	 8'b0000_0001) & {8{{WERTE7__q[9], WERTE6__q[9], WERTE5__q[9],
+	 WERTE4__q[9], WERTE3__q[9], WERTE2__q[9], WERTE1__q[9], WERTE0__q[9]}
+	 != 8'b0110_0011}} & (~({8{RTC_ADR_q == 6'b00_1001}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}));
+   assign {WERTE7_9_ena_2, WERTE6_9_ena_2, WERTE5_9_ena_2, WERTE4_9_ena_2,
+	 WERTE3_9_ena_2, WERTE2_9_ena_2, WERTE1_9_ena_2, WERTE0_9_ena_2} =
+	 {8{INC_JAHR}} & (~({8{RTC_ADR_q == 6'b00_1001}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}));
+
+//  TRISTATE OUTPUT
+   assign u0_data = ({8{INT_CTR_CS}} & INT_CTR_q[31:24]) | ({8{INT_ENA_CS}} &
+	 INT_ENA_q[31:24]) | ({8{INT_LATCH_CS}} & INT_LATCH_q[31:24]) |
+	 ({8{INT_CLEAR_CS}} & INT_IN[31:24]) | ({8{ACP_CONF_CS}} &
+	 ACP_CONF_q[31:24]);
+   assign u0_enabledt = (INT_CTR_CS | INT_ENA_CS | INT_LATCH_CS | INT_CLEAR_CS
+	 | ACP_CONF_CS) & (!nFB_OE);
+   assign FB_AD[31:24] = u0_tridata;
+   assign u1_data = ({WERTE7__q[0], WERTE6__q[0], WERTE5__q[0], WERTE4__q[0],
+	 WERTE3__q[0], WERTE2__q[0], WERTE1__q[0], WERTE0__q[0]} & {8{RTC_ADR_q
+	 == 6'b00_0000}} & {8{UHR_DS}}) | ({WERTE7__q[1], WERTE6__q[1],
+	 WERTE5__q[1], WERTE4__q[1], WERTE3__q[1], WERTE2__q[1], WERTE1__q[1],
+	 WERTE0__q[1]} & {8{RTC_ADR_q == 6'b00_0001}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[2], WERTE6__q[2], WERTE5__q[2], WERTE4__q[2],
+	 WERTE3__q[2], WERTE2__q[2], WERTE1__q[2], WERTE0__q[2]} & {8{RTC_ADR_q
+	 == 6'b00_0010}} & {8{UHR_DS}}) | ({WERTE7__q[3], WERTE6__q[3],
+	 WERTE5__q[3], WERTE4__q[3], WERTE3__q[3], WERTE2__q[3], WERTE1__q[3],
+	 WERTE0__q[3]} & {8{RTC_ADR_q == 6'b00_0011}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[4], WERTE6__q[4], WERTE5__q[4], WERTE4__q[4],
+	 WERTE3__q[4], WERTE2__q[4], WERTE1__q[4], WERTE0__q[4]} & {8{RTC_ADR_q
+	 == 6'b00_0100}} & {8{UHR_DS}}) | ({WERTE7__q[5], WERTE6__q[5],
+	 WERTE5__q[5], WERTE4__q[5], WERTE3__q[5], WERTE2__q[5], WERTE1__q[5],
+	 WERTE0__q[5]} & {8{RTC_ADR_q == 6'b00_0101}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[6], WERTE6__q[6], WERTE5__q[6], WERTE4__q[6],
+	 WERTE3__q[6], WERTE2__q[6], WERTE1__q[6], WERTE0__q[6]} & {8{RTC_ADR_q
+	 == 6'b00_0110}} & {8{UHR_DS}}) | ({WERTE7__q[7], WERTE6__q[7],
+	 WERTE5__q[7], WERTE4__q[7], WERTE3__q[7], WERTE2__q[7], WERTE1__q[7],
+	 WERTE0__q[7]} & {8{RTC_ADR_q == 6'b00_0111}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[8], WERTE6__q[8], WERTE5__q[8], WERTE4__q[8],
+	 WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]} & {8{RTC_ADR_q
+	 == 6'b00_1000}} & {8{UHR_DS}}) | ({WERTE7__q[9], WERTE6__q[9],
+	 WERTE5__q[9], WERTE4__q[9], WERTE3__q[9], WERTE2__q[9], WERTE1__q[9],
+	 WERTE0__q[9]} & {8{RTC_ADR_q == 6'b00_1001}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[10], WERTE6__q[10], WERTE5__q[10], WERTE4__q[10],
+	 WERTE3__q[10], WERTE2__q[10], WERTE1__q[10], WERTE0__q[10]} &
+	 {8{RTC_ADR_q == 6'b00_1010}} & {8{UHR_DS}}) | ({WERTE7__q[11],
+	 WERTE6__q[11], WERTE5__q[11], WERTE4__q[11], WERTE3__q[11],
+	 WERTE2__q[11], WERTE1__q[11], WERTE0__q[11]} & {8{RTC_ADR_q ==
+	 6'b00_1011}} & {8{UHR_DS}}) | ({WERTE7__q[12], WERTE6__q[12],
+	 WERTE5__q[12], WERTE4__q[12], WERTE3__q[12], WERTE2__q[12],
+	 WERTE1__q[12], WERTE0__q[12]} & {8{RTC_ADR_q == 6'b00_1100}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[13], WERTE6__q[13], WERTE5__q[13],
+	 WERTE4__q[13], WERTE3__q[13], WERTE2__q[13], WERTE1__q[13],
+	 WERTE0__q[13]} & {8{RTC_ADR_q == 6'b00_1101}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[14], WERTE6__q[14], WERTE5__q[14], WERTE4__q[14],
+	 WERTE3__q[14], WERTE2__q[14], WERTE1__q[14], WERTE0__q[14]} &
+	 {8{RTC_ADR_q == 6'b00_1110}} & {8{UHR_DS}}) | ({WERTE7__q[15],
+	 WERTE6__q[15], WERTE5__q[15], WERTE4__q[15], WERTE3__q[15],
+	 WERTE2__q[15], WERTE1__q[15], WERTE0__q[15]} & {8{RTC_ADR_q ==
+	 6'b00_1111}} & {8{UHR_DS}}) | ({WERTE7__q[16], WERTE6__q[16],
+	 WERTE5__q[16], WERTE4__q[16], WERTE3__q[16], WERTE2__q[16],
+	 WERTE1__q[16], WERTE0__q[16]} & {8{RTC_ADR_q == 6'b01_0000}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[17], WERTE6__q[17], WERTE5__q[17],
+	 WERTE4__q[17], WERTE3__q[17], WERTE2__q[17], WERTE1__q[17],
+	 WERTE0__q[17]} & {8{RTC_ADR_q == 6'b01_0001}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[18], WERTE6__q[18], WERTE5__q[18], WERTE4__q[18],
+	 WERTE3__q[18], WERTE2__q[18], WERTE1__q[18], WERTE0__q[18]} &
+	 {8{RTC_ADR_q == 6'b01_0010}} & {8{UHR_DS}}) | ({WERTE7__q[19],
+	 WERTE6__q[19], WERTE5__q[19], WERTE4__q[19], WERTE3__q[19],
+	 WERTE2__q[19], WERTE1__q[19], WERTE0__q[19]} & {8{RTC_ADR_q ==
+	 6'b01_0011}} & {8{UHR_DS}}) | ({WERTE7__q[20], WERTE6__q[20],
+	 WERTE5__q[20], WERTE4__q[20], WERTE3__q[20], WERTE2__q[20],
+	 WERTE1__q[20], WERTE0__q[20]} & {8{RTC_ADR_q == 6'b01_0100}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[21], WERTE6__q[21], WERTE5__q[21],
+	 WERTE4__q[21], WERTE3__q[21], WERTE2__q[21], WERTE1__q[21],
+	 WERTE0__q[21]} & {8{RTC_ADR_q == 6'b01_0101}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[22], WERTE6__q[22], WERTE5__q[22], WERTE4__q[22],
+	 WERTE3__q[22], WERTE2__q[22], WERTE1__q[22], WERTE0__q[22]} &
+	 {8{RTC_ADR_q == 6'b01_0110}} & {8{UHR_DS}}) | ({WERTE7__q[23],
+	 WERTE6__q[23], WERTE5__q[23], WERTE4__q[23], WERTE3__q[23],
+	 WERTE2__q[23], WERTE1__q[23], WERTE0__q[23]} & {8{RTC_ADR_q ==
+	 6'b01_0111}} & {8{UHR_DS}}) | ({WERTE7__q[24], WERTE6__q[24],
+	 WERTE5__q[24], WERTE4__q[24], WERTE3__q[24], WERTE2__q[24],
+	 WERTE1__q[24], WERTE0__q[24]} & {8{RTC_ADR_q == 6'b01_1000}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[25], WERTE6__q[25], WERTE5__q[25],
+	 WERTE4__q[25], WERTE3__q[25], WERTE2__q[25], WERTE1__q[25],
+	 WERTE0__q[25]} & {8{RTC_ADR_q == 6'b01_1001}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[26], WERTE6__q[26], WERTE5__q[26], WERTE4__q[26],
+	 WERTE3__q[26], WERTE2__q[26], WERTE1__q[26], WERTE0__q[26]} &
+	 {8{RTC_ADR_q == 6'b01_1010}} & {8{UHR_DS}}) | ({WERTE7__q[27],
+	 WERTE6__q[27], WERTE5__q[27], WERTE4__q[27], WERTE3__q[27],
+	 WERTE2__q[27], WERTE1__q[27], WERTE0__q[27]} & {8{RTC_ADR_q ==
+	 6'b01_1011}} & {8{UHR_DS}}) | ({WERTE7__q[28], WERTE6__q[28],
+	 WERTE5__q[28], WERTE4__q[28], WERTE3__q[28], WERTE2__q[28],
+	 WERTE1__q[28], WERTE0__q[28]} & {8{RTC_ADR_q == 6'b01_1100}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[29], WERTE6__q[29], WERTE5__q[29],
+	 WERTE4__q[29], WERTE3__q[29], WERTE2__q[29], WERTE1__q[29],
+	 WERTE0__q[29]} & {8{RTC_ADR_q == 6'b01_1101}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[30], WERTE6__q[30], WERTE5__q[30], WERTE4__q[30],
+	 WERTE3__q[30], WERTE2__q[30], WERTE1__q[30], WERTE0__q[30]} &
+	 {8{RTC_ADR_q == 6'b01_1110}} & {8{UHR_DS}}) | ({WERTE7__q[31],
+	 WERTE6__q[31], WERTE5__q[31], WERTE4__q[31], WERTE3__q[31],
+	 WERTE2__q[31], WERTE1__q[31], WERTE0__q[31]} & {8{RTC_ADR_q ==
+	 6'b01_1111}} & {8{UHR_DS}}) | ({WERTE7__q[32], WERTE6__q[32],
+	 WERTE5__q[32], WERTE4__q[32], WERTE3__q[32], WERTE2__q[32],
+	 WERTE1__q[32], WERTE0__q[32]} & {8{RTC_ADR_q == 6'b10_0000}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[33], WERTE6__q[33], WERTE5__q[33],
+	 WERTE4__q[33], WERTE3__q[33], WERTE2__q[33], WERTE1__q[33],
+	 WERTE0__q[33]} & {8{RTC_ADR_q == 6'b10_0001}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[34], WERTE6__q[34], WERTE5__q[34], WERTE4__q[34],
+	 WERTE3__q[34], WERTE2__q[34], WERTE1__q[34], WERTE0__q[34]} &
+	 {8{RTC_ADR_q == 6'b10_0010}} & {8{UHR_DS}}) | ({WERTE7__q[35],
+	 WERTE6__q[35], WERTE5__q[35], WERTE4__q[35], WERTE3__q[35],
+	 WERTE2__q[35], WERTE1__q[35], WERTE0__q[35]} & {8{RTC_ADR_q ==
+	 6'b10_0011}} & {8{UHR_DS}}) | ({WERTE7__q[36], WERTE6__q[36],
+	 WERTE5__q[36], WERTE4__q[36], WERTE3__q[36], WERTE2__q[36],
+	 WERTE1__q[36], WERTE0__q[36]} & {8{RTC_ADR_q == 6'b10_0100}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[37], WERTE6__q[37], WERTE5__q[37],
+	 WERTE4__q[37], WERTE3__q[37], WERTE2__q[37], WERTE1__q[37],
+	 WERTE0__q[37]} & {8{RTC_ADR_q == 6'b10_0101}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[38], WERTE6__q[38], WERTE5__q[38], WERTE4__q[38],
+	 WERTE3__q[38], WERTE2__q[38], WERTE1__q[38], WERTE0__q[38]} &
+	 {8{RTC_ADR_q == 6'b10_0110}} & {8{UHR_DS}}) | ({WERTE7__q[39],
+	 WERTE6__q[39], WERTE5__q[39], WERTE4__q[39], WERTE3__q[39],
+	 WERTE2__q[39], WERTE1__q[39], WERTE0__q[39]} & {8{RTC_ADR_q ==
+	 6'b10_0111}} & {8{UHR_DS}}) | ({WERTE7__q[40], WERTE6__q[40],
+	 WERTE5__q[40], WERTE4__q[40], WERTE3__q[40], WERTE2__q[40],
+	 WERTE1__q[40], WERTE0__q[40]} & {8{RTC_ADR_q == 6'b10_1000}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[41], WERTE6__q[41], WERTE5__q[41],
+	 WERTE4__q[41], WERTE3__q[41], WERTE2__q[41], WERTE1__q[41],
+	 WERTE0__q[41]} & {8{RTC_ADR_q == 6'b10_1001}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[42], WERTE6__q[42], WERTE5__q[42], WERTE4__q[42],
+	 WERTE3__q[42], WERTE2__q[42], WERTE1__q[42], WERTE0__q[42]} &
+	 {8{RTC_ADR_q == 6'b10_1010}} & {8{UHR_DS}}) | ({WERTE7__q[43],
+	 WERTE6__q[43], WERTE5__q[43], WERTE4__q[43], WERTE3__q[43],
+	 WERTE2__q[43], WERTE1__q[43], WERTE0__q[43]} & {8{RTC_ADR_q ==
+	 6'b10_1011}} & {8{UHR_DS}}) | ({WERTE7__q[44], WERTE6__q[44],
+	 WERTE5__q[44], WERTE4__q[44], WERTE3__q[44], WERTE2__q[44],
+	 WERTE1__q[44], WERTE0__q[44]} & {8{RTC_ADR_q == 6'b10_1100}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[45], WERTE6__q[45], WERTE5__q[45],
+	 WERTE4__q[45], WERTE3__q[45], WERTE2__q[45], WERTE1__q[45],
+	 WERTE0__q[45]} & {8{RTC_ADR_q == 6'b10_1101}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[46], WERTE6__q[46], WERTE5__q[46], WERTE4__q[46],
+	 WERTE3__q[46], WERTE2__q[46], WERTE1__q[46], WERTE0__q[46]} &
+	 {8{RTC_ADR_q == 6'b10_1110}} & {8{UHR_DS}}) | ({WERTE7__q[47],
+	 WERTE6__q[47], WERTE5__q[47], WERTE4__q[47], WERTE3__q[47],
+	 WERTE2__q[47], WERTE1__q[47], WERTE0__q[47]} & {8{RTC_ADR_q ==
+	 6'b10_1111}} & {8{UHR_DS}}) | ({WERTE7__q[48], WERTE6__q[48],
+	 WERTE5__q[48], WERTE4__q[48], WERTE3__q[48], WERTE2__q[48],
+	 WERTE1__q[48], WERTE0__q[48]} & {8{RTC_ADR_q == 6'b11_0000}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[49], WERTE6__q[49], WERTE5__q[49],
+	 WERTE4__q[49], WERTE3__q[49], WERTE2__q[49], WERTE1__q[49],
+	 WERTE0__q[49]} & {8{RTC_ADR_q == 6'b11_0001}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[50], WERTE6__q[50], WERTE5__q[50], WERTE4__q[50],
+	 WERTE3__q[50], WERTE2__q[50], WERTE1__q[50], WERTE0__q[50]} &
+	 {8{RTC_ADR_q == 6'b11_0010}} & {8{UHR_DS}}) | ({WERTE7__q[51],
+	 WERTE6__q[51], WERTE5__q[51], WERTE4__q[51], WERTE3__q[51],
+	 WERTE2__q[51], WERTE1__q[51], WERTE0__q[51]} & {8{RTC_ADR_q ==
+	 6'b11_0011}} & {8{UHR_DS}}) | ({WERTE7__q[52], WERTE6__q[52],
+	 WERTE5__q[52], WERTE4__q[52], WERTE3__q[52], WERTE2__q[52],
+	 WERTE1__q[52], WERTE0__q[52]} & {8{RTC_ADR_q == 6'b11_0100}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[53], WERTE6__q[53], WERTE5__q[53],
+	 WERTE4__q[53], WERTE3__q[53], WERTE2__q[53], WERTE1__q[53],
+	 WERTE0__q[53]} & {8{RTC_ADR_q == 6'b11_0101}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[54], WERTE6__q[54], WERTE5__q[54], WERTE4__q[54],
+	 WERTE3__q[54], WERTE2__q[54], WERTE1__q[54], WERTE0__q[54]} &
+	 {8{RTC_ADR_q == 6'b11_0110}} & {8{UHR_DS}}) | ({WERTE7__q[55],
+	 WERTE6__q[55], WERTE5__q[55], WERTE4__q[55], WERTE3__q[55],
+	 WERTE2__q[55], WERTE1__q[55], WERTE0__q[55]} & {8{RTC_ADR_q ==
+	 6'b11_0111}} & {8{UHR_DS}}) | ({WERTE7__q[56], WERTE6__q[56],
+	 WERTE5__q[56], WERTE4__q[56], WERTE3__q[56], WERTE2__q[56],
+	 WERTE1__q[56], WERTE0__q[56]} & {8{RTC_ADR_q == 6'b11_1000}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[57], WERTE6__q[57], WERTE5__q[57],
+	 WERTE4__q[57], WERTE3__q[57], WERTE2__q[57], WERTE1__q[57],
+	 WERTE0__q[57]} & {8{RTC_ADR_q == 6'b11_1001}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[58], WERTE6__q[58], WERTE5__q[58], WERTE4__q[58],
+	 WERTE3__q[58], WERTE2__q[58], WERTE1__q[58], WERTE0__q[58]} &
+	 {8{RTC_ADR_q == 6'b11_1010}} & {8{UHR_DS}}) | ({WERTE7__q[59],
+	 WERTE6__q[59], WERTE5__q[59], WERTE4__q[59], WERTE3__q[59],
+	 WERTE2__q[59], WERTE1__q[59], WERTE0__q[59]} & {8{RTC_ADR_q ==
+	 6'b11_1011}} & {8{UHR_DS}}) | ({WERTE7__q[60], WERTE6__q[60],
+	 WERTE5__q[60], WERTE4__q[60], WERTE3__q[60], WERTE2__q[60],
+	 WERTE1__q[60], WERTE0__q[60]} & {8{RTC_ADR_q == 6'b11_1100}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[61], WERTE6__q[61], WERTE5__q[61],
+	 WERTE4__q[61], WERTE3__q[61], WERTE2__q[61], WERTE1__q[61],
+	 WERTE0__q[61]} & {8{RTC_ADR_q == 6'b11_1101}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[62], WERTE6__q[62], WERTE5__q[62], WERTE4__q[62],
+	 WERTE3__q[62], WERTE2__q[62], WERTE1__q[62], WERTE0__q[62]} &
+	 {8{RTC_ADR_q == 6'b11_1110}} & {8{UHR_DS}}) | ({WERTE7__q[63],
+	 WERTE6__q[63], WERTE5__q[63], WERTE4__q[63], WERTE3__q[63],
+	 WERTE2__q[63], WERTE1__q[63], WERTE0__q[63]} & {8{RTC_ADR_q ==
+	 6'b11_1111}} & {8{UHR_DS}}) | ({2'b00, RTC_ADR_q} & {8{UHR_AS}}) |
+	 ({8{INT_CTR_CS}} & INT_CTR_q[23:16]) | ({8{INT_ENA_CS}} &
+	 INT_ENA_q[23:16]) | ({8{INT_LATCH_CS}} & INT_LATCH_q[23:16]) |
+	 ({8{INT_CLEAR_CS}} & INT_IN[23:16]) | ({8{ACP_CONF_CS}} &
+	 ACP_CONF_q[23:16]);
+   assign u1_enabledt = (UHR_DS | UHR_AS | INT_CTR_CS | INT_ENA_CS |
+	 INT_LATCH_CS | INT_CLEAR_CS | ACP_CONF_CS) & (!nFB_OE);
+   assign FB_AD[23:16] = u1_tridata;
+   assign u2_data = ({8{INT_CTR_CS}} & INT_CTR_q[15:8]) | ({8{INT_ENA_CS}} &
+	 INT_ENA_q[15:8]) | ({8{INT_LATCH_CS}} & INT_LATCH_q[15:8]) |
+	 ({8{INT_CLEAR_CS}} & INT_IN[15:8]) | ({8{ACP_CONF_CS}} &
+	 ACP_CONF_q[15:8]);
+   assign u2_enabledt = (INT_CTR_CS | INT_ENA_CS | INT_LATCH_CS | INT_CLEAR_CS
+	 | ACP_CONF_CS) & (!nFB_OE);
+   assign FB_AD[15:8] = u2_tridata;
+   assign u3_data = ({8{INT_CTR_CS}} & INT_CTR_q[7:0]) | ({8{INT_ENA_CS}} &
+	 INT_ENA_q[7:0]) | ({8{INT_LATCH_CS}} & INT_LATCH_q[7:0]) |
+	 ({8{INT_CLEAR_CS}} & INT_IN[7:0]) | ({8{ACP_CONF_CS}} &
+	 ACP_CONF_q[7:0]);
+   assign u3_enabledt = (INT_CTR_CS | INT_ENA_CS | INT_LATCH_CS | INT_CLEAR_CS
+	 | ACP_CONF_CS) & (!nFB_OE);
+   assign FB_AD[7:0] = u3_tridata;
+   assign INT_HANDLER_TA = INT_CTR_CS | INT_ENA_CS | INT_LATCH_CS |
+	 INT_CLEAR_CS;
+
+
+// Assignments added to explicitly combine the
+// effects of multiple drivers in the source
+   assign UPDATE_ON = UPDATE_ON_1 | UPDATE_ON_2;
+   assign WERTE0_0_ena = WERTE0_0_ena_1 | WERTE0_0_ena_2;
+   assign WERTE0_2_ena = WERTE0_2_ena_1 | WERTE0_2_ena_2;
+   assign WERTE0_4_ena = WERTE0_4_ena_1 | WERTE0_4_ena_2;
+   assign WERTE0_6_ena = WERTE0_6_ena_1 | WERTE0_6_ena_2;
+   assign WERTE0_7_ena = WERTE0_7_ena_1 | WERTE0_7_ena_2;
+   assign WERTE0_8_ena = WERTE0_8_ena_1 | WERTE0_8_ena_2;
+   assign WERTE0_9_ena = WERTE0_9_ena_1 | WERTE0_9_ena_2;
+   assign WERTE0_13_ena = WERTE0_13_ena_1 | WERTE0_13_ena_2;
+   assign WERTE0__d[0] = WERTE0_0_d_1 | WERTE0_0_d_2;
+   assign WERTE0__d[2] = WERTE0_2_d_1 | WERTE0_2_d_2;
+   assign WERTE0__d[4] = WERTE0_4_d_1 | WERTE0_4_d_2;
+   assign WERTE0__d[6] = WERTE0_6_d_1 | WERTE0_6_d_2;
+   assign WERTE0__d[7] = WERTE0_7_d_1 | WERTE0_7_d_2;
+   assign WERTE0__d[8] = WERTE0_8_d_1 | WERTE0_8_d_2;
+   assign WERTE0__d[9] = WERTE0_9_d_1 | WERTE0_9_d_2;
+   assign WERTE0__d[11] = WERTE0_11_d_1 | WERTE0_11_d_2;
+   assign WERTE0__d[13] = WERTE0_13_d_1 | WERTE0_13_d_2;
+   assign WERTE1_0_ena = WERTE1_0_ena_1 | WERTE1_0_ena_2;
+   assign WERTE1_2_ena = WERTE1_2_ena_1 | WERTE1_2_ena_2;
+   assign WERTE1_4_ena = WERTE1_4_ena_1 | WERTE1_4_ena_2;
+   assign WERTE1_6_ena = WERTE1_6_ena_1 | WERTE1_6_ena_2;
+   assign WERTE1_7_ena = WERTE1_7_ena_1 | WERTE1_7_ena_2;
+   assign WERTE1_8_ena = WERTE1_8_ena_1 | WERTE1_8_ena_2;
+   assign WERTE1_9_ena = WERTE1_9_ena_1 | WERTE1_9_ena_2;
+   assign WERTE1__d[0] = WERTE1_0_d_1 | WERTE1_0_d_2;
+   assign WERTE1__d[2] = WERTE1_2_d_1 | WERTE1_2_d_2;
+   assign WERTE1__d[4] = WERTE1_4_d_1 | WERTE1_4_d_2;
+   assign WERTE1__d[6] = WERTE1_6_d_1 | WERTE1_6_d_2;
+   assign WERTE1__d[7] = WERTE1_7_d_1 | WERTE1_7_d_2;
+   assign WERTE1__d[8] = WERTE1_8_d_1 | WERTE1_8_d_2;
+   assign WERTE1__d[9] = WERTE1_9_d_1 | WERTE1_9_d_2;
+   assign WERTE1__d[11] = WERTE1_11_d_1 | WERTE1_11_d_2;
+   assign WERTE2_0_ena = WERTE2_0_ena_1 | WERTE2_0_ena_2;
+   assign WERTE2_2_ena = WERTE2_2_ena_1 | WERTE2_2_ena_2;
+   assign WERTE2_4_ena = WERTE2_4_ena_1 | WERTE2_4_ena_2;
+   assign WERTE2_6_ena = WERTE2_6_ena_1 | WERTE2_6_ena_2;
+   assign WERTE2_7_ena = WERTE2_7_ena_1 | WERTE2_7_ena_2;
+   assign WERTE2_8_ena = WERTE2_8_ena_1 | WERTE2_8_ena_2;
+   assign WERTE2_9_ena = WERTE2_9_ena_1 | WERTE2_9_ena_2;
+   assign WERTE2__d[0] = WERTE2_0_d_1 | WERTE2_0_d_2;
+   assign WERTE2__d[2] = WERTE2_2_d_1 | WERTE2_2_d_2;
+   assign WERTE2__d[4] = WERTE2_4_d_1 | WERTE2_4_d_2;
+   assign WERTE2__d[6] = WERTE2_6_d_1 | WERTE2_6_d_2;
+   assign WERTE2__d[7] = WERTE2_7_d_1 | WERTE2_7_d_2;
+   assign WERTE2__d[8] = WERTE2_8_d_1 | WERTE2_8_d_2;
+   assign WERTE2__d[9] = WERTE2_9_d_1 | WERTE2_9_d_2;
+   assign WERTE2__d[11] = WERTE2_11_d_1 | WERTE2_11_d_2;
+   assign WERTE3_0_ena = WERTE3_0_ena_1 | WERTE3_0_ena_2;
+   assign WERTE3_2_ena = WERTE3_2_ena_1 | WERTE3_2_ena_2;
+   assign WERTE3_4_ena = WERTE3_4_ena_1 | WERTE3_4_ena_2;
+   assign WERTE3_6_ena = WERTE3_6_ena_1 | WERTE3_6_ena_2;
+   assign WERTE3_7_ena = WERTE3_7_ena_1 | WERTE3_7_ena_2;
+   assign WERTE3_8_ena = WERTE3_8_ena_1 | WERTE3_8_ena_2;
+   assign WERTE3_9_ena = WERTE3_9_ena_1 | WERTE3_9_ena_2;
+   assign WERTE3__d[0] = WERTE3_0_d_1 | WERTE3_0_d_2;
+   assign WERTE3__d[2] = WERTE3_2_d_1 | WERTE3_2_d_2;
+   assign WERTE3__d[4] = WERTE3_4_d_1 | WERTE3_4_d_2;
+   assign WERTE3__d[6] = WERTE3_6_d_1 | WERTE3_6_d_2;
+   assign WERTE3__d[7] = WERTE3_7_d_1 | WERTE3_7_d_2;
+   assign WERTE3__d[8] = WERTE3_8_d_1 | WERTE3_8_d_2;
+   assign WERTE3__d[9] = WERTE3_9_d_1 | WERTE3_9_d_2;
+   assign WERTE4_0_ena = WERTE4_0_ena_1 | WERTE4_0_ena_2;
+   assign WERTE4_2_ena = WERTE4_2_ena_1 | WERTE4_2_ena_2;
+   assign WERTE4_4_ena = WERTE4_4_ena_1 | WERTE4_4_ena_2;
+   assign WERTE4_6_ena = WERTE4_6_ena_1 | WERTE4_6_ena_2;
+   assign WERTE4_7_ena = WERTE4_7_ena_1 | WERTE4_7_ena_2;
+   assign WERTE4_8_ena = WERTE4_8_ena_1 | WERTE4_8_ena_2;
+   assign WERTE4_9_ena = WERTE4_9_ena_1 | WERTE4_9_ena_2;
+   assign WERTE4__d[0] = WERTE4_0_d_1 | WERTE4_0_d_2;
+   assign WERTE4__d[2] = WERTE4_2_d_1 | WERTE4_2_d_2;
+   assign WERTE4__d[4] = WERTE4_4_d_1 | WERTE4_4_d_2;
+   assign WERTE4__d[6] = WERTE4_6_d_1 | WERTE4_6_d_2;
+   assign WERTE4__d[7] = WERTE4_7_d_1 | WERTE4_7_d_2;
+   assign WERTE4__d[8] = WERTE4_8_d_1 | WERTE4_8_d_2;
+   assign WERTE4__d[9] = WERTE4_9_d_1 | WERTE4_9_d_2;
+   assign WERTE5_0_ena = WERTE5_0_ena_1 | WERTE5_0_ena_2;
+   assign WERTE5_2_ena = WERTE5_2_ena_1 | WERTE5_2_ena_2;
+   assign WERTE5_4_ena = WERTE5_4_ena_1 | WERTE5_4_ena_2;
+   assign WERTE5_6_ena = WERTE5_6_ena_1 | WERTE5_6_ena_2;
+   assign WERTE5_7_ena = WERTE5_7_ena_1 | WERTE5_7_ena_2;
+   assign WERTE5_8_ena = WERTE5_8_ena_1 | WERTE5_8_ena_2;
+   assign WERTE5_9_ena = WERTE5_9_ena_1 | WERTE5_9_ena_2;
+   assign WERTE5__d[0] = WERTE5_0_d_1 | WERTE5_0_d_2;
+   assign WERTE5__d[2] = WERTE5_2_d_1 | WERTE5_2_d_2;
+   assign WERTE5__d[4] = WERTE5_4_d_1 | WERTE5_4_d_2;
+   assign WERTE5__d[6] = WERTE5_6_d_1 | WERTE5_6_d_2;
+   assign WERTE5__d[7] = WERTE5_7_d_1 | WERTE5_7_d_2;
+   assign WERTE5__d[8] = WERTE5_8_d_1 | WERTE5_8_d_2;
+   assign WERTE5__d[9] = WERTE5_9_d_1 | WERTE5_9_d_2;
+   assign WERTE6_0_ena = WERTE6_0_ena_1 | WERTE6_0_ena_2;
+   assign WERTE6_2_ena = WERTE6_2_ena_1 | WERTE6_2_ena_2;
+   assign WERTE6_4_ena = WERTE6_4_ena_1 | WERTE6_4_ena_2;
+   assign WERTE6_6_ena = WERTE6_6_ena_1 | WERTE6_6_ena_2;
+   assign WERTE6_7_ena = WERTE6_7_ena_1 | WERTE6_7_ena_2;
+   assign WERTE6_8_ena = WERTE6_8_ena_1 | WERTE6_8_ena_2;
+   assign WERTE6_9_ena = WERTE6_9_ena_1 | WERTE6_9_ena_2;
+   assign WERTE6__d[0] = WERTE6_0_d_1 | WERTE6_0_d_2;
+   assign WERTE6__d[2] = WERTE6_2_d_1 | WERTE6_2_d_2;
+   assign WERTE6__d[4] = WERTE6_4_d_1 | WERTE6_4_d_2;
+   assign WERTE6__d[6] = WERTE6_6_d_1 | WERTE6_6_d_2;
+   assign WERTE6__d[7] = WERTE6_7_d_1 | WERTE6_7_d_2;
+   assign WERTE6__d[8] = WERTE6_8_d_1 | WERTE6_8_d_2;
+   assign WERTE6__d[9] = WERTE6_9_d_1 | WERTE6_9_d_2;
+   assign WERTE7_0_ena = WERTE7_0_ena_1 | WERTE7_0_ena_2;
+   assign WERTE7_2_ena = WERTE7_2_ena_1 | WERTE7_2_ena_2;
+   assign WERTE7_4_ena = WERTE7_4_ena_1 | WERTE7_4_ena_2;
+   assign WERTE7_6_ena = WERTE7_6_ena_1 | WERTE7_6_ena_2;
+   assign WERTE7_7_ena = WERTE7_7_ena_1 | WERTE7_7_ena_2;
+   assign WERTE7_8_ena = WERTE7_8_ena_1 | WERTE7_8_ena_2;
+   assign WERTE7_9_ena = WERTE7_9_ena_1 | WERTE7_9_ena_2;
+   assign WERTE7__d[0] = WERTE7_0_d_1 | WERTE7_0_d_2;
+   assign WERTE7__d[2] = WERTE7_2_d_1 | WERTE7_2_d_2;
+   assign WERTE7__d[4] = WERTE7_4_d_1 | WERTE7_4_d_2;
+   assign WERTE7__d[6] = WERTE7_6_d_1 | WERTE7_6_d_2;
+   assign WERTE7__d[7] = WERTE7_7_d_1 | WERTE7_7_d_2;
+   assign WERTE7__d[8] = WERTE7_8_d_1 | WERTE7_8_d_2;
+   assign WERTE7__d[9] = WERTE7_9_d_1 | WERTE7_9_d_2;
+   assign WERTE7__d[13] = WERTE7_13_d_1 | WERTE7_13_d_2;
+
+// Define power signal(s)
+   assign vcc = 1'b1;
+   assign gnd = 1'b0;
+endmodule
diff --git a/FPGA_quartus_GE/PLLJ_PLLSPE_INFO.txt b/FPGA_quartus_GE/PLLJ_PLLSPE_INFO.txt
new file mode 100644
index 0000000..8ee82dc
--- /dev/null
+++ b/FPGA_quartus_GE/PLLJ_PLLSPE_INFO.txt
@@ -0,0 +1,20 @@
+PLL_Name	altpll1:b2v_inst|altpll:altpll_component|altpll_8tp2:auto_generated|pll1
+PLLJITTER	33
+PLLSPEmax	84
+PLLSPEmin	-53
+
+PLL_Name	altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|pll1
+PLLJITTER	43
+PLLSPEmax	84
+PLLSPEmin	-53
+
+PLL_Name	altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|pll1
+PLLJITTER	NA
+PLLSPEmax	84
+PLLSPEmin	-53
+
+PLL_Name	altpll4:b2v_inst22|altpll:altpll_component|altpll_r4n2:auto_generated|pll1
+PLLJITTER	31
+PLLSPEmax	84
+PLLSPEmin	-53
+
diff --git a/FPGA_quartus_GE/UNUSED b/FPGA_quartus_GE/UNUSED
new file mode 100644
index 0000000..3a7d9e6
--- /dev/null
+++ b/FPGA_quartus_GE/UNUSED
@@ -0,0 +1,27 @@
+
+-- Clearbox generated Memory Initialization File (.mif)
+
+WIDTH=3;
+DEPTH=16;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+	00  :   7;
+	01  :   6;
+	02  :   5;
+	03  :   4;
+	04  :   3;
+	05  :   2;
+	06  :   1;
+	07  :   0;
+	08  :   7;
+	09  :   6;
+	0a  :   5;
+	0b  :   4;
+	0c  :   3;
+	0d  :   2;
+	0e  :   1;
+	0f  :   0;
+END;
diff --git a/FPGA_quartus_GE/Video/BLITTER/BLITTER.vhd b/FPGA_quartus_GE/Video/BLITTER/BLITTER.vhd
new file mode 100644
index 0000000..e09ed0b
--- /dev/null
+++ b/FPGA_quartus_GE/Video/BLITTER/BLITTER.vhd
@@ -0,0 +1,75 @@
+-- WARNING: Do NOT edit the input and output ports in this file in a text
+-- editor if you plan to continue editing the block that represents it in
+-- the Block Editor! File corruption is VERY likely to occur.
+
+-- Copyright (C) 1991-2008 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+
+-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
+-- Created on Fri Oct 16 15:40:59 2009
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+
+--  Entity Declaration
+
+ENTITY BLITTER IS
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	PORT
+	(
+		nRSTO : IN STD_LOGIC;
+		MAIN_CLK : IN STD_LOGIC;
+		FB_ALE : IN STD_LOGIC;
+		nFB_WR : IN STD_LOGIC;
+		nFB_OE : IN STD_LOGIC;
+		FB_SIZE0 : IN STD_LOGIC;
+		FB_SIZE1 : IN STD_LOGIC;
+		VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0);
+		BLITTER_ON : IN STD_LOGIC;
+		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
+		nFB_CS1 : IN STD_LOGIC;
+		nFB_CS2 : IN STD_LOGIC;
+		nFB_CS3 : IN STD_LOGIC;
+		DDRCLK0 : IN STD_LOGIC;
+		BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0);
+		BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0);
+		BLITTER_RUN : OUT STD_LOGIC;
+		BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0);
+		BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0);
+		BLITTER_SIG : OUT STD_LOGIC;
+		BLITTER_WR : OUT STD_LOGIC;
+		BLITTER_TA : OUT STD_LOGIC;
+		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0)
+	);
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+	
+END BLITTER;
+
+
+--  Architecture Body
+
+ARCHITECTURE BLITTER_architecture OF BLITTER IS
+
+	
+BEGIN
+	BLITTER_RUN <= '0';
+	BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
+	BLITTER_ADR <=  x"76543210";
+	BLITTER_SIG <= '0';
+	BLITTER_WR <= '0';
+	BLITTER_TA <= '0';
+
+END BLITTER_architecture;
diff --git a/FPGA_quartus_GE/Video/BLITTER/BLITTER.vhd.bak b/FPGA_quartus_GE/Video/BLITTER/BLITTER.vhd.bak
new file mode 100644
index 0000000..f674080
--- /dev/null
+++ b/FPGA_quartus_GE/Video/BLITTER/BLITTER.vhd.bak
@@ -0,0 +1,75 @@
+-- WARNING: Do NOT edit the input and output ports in this file in a text
+-- editor if you plan to continue editing the block that represents it in
+-- the Block Editor! File corruption is VERY likely to occur.
+
+-- Copyright (C) 1991-2008 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+
+-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
+-- Created on Fri Oct 16 15:40:59 2009
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+
+--  Entity Declaration
+
+ENTITY BLITTER IS
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	PORT
+	(
+		nRSTO : IN STD_LOGIC;
+		MAIN_CLK : IN STD_LOGIC;
+		FB_ALE : IN STD_LOGIC;
+		nFB_WR : IN STD_LOGIC;
+		nFB_OE : IN STD_LOGIC;
+		FB_SIZE0 : IN STD_LOGIC;
+		FB_SIZE1 : IN STD_LOGIC;
+		VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0);
+		BLITTER_ON : IN STD_LOGIC;
+		FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
+		nFB_CS1 : IN STD_LOGIC;
+		nFB_CS2 : IN STD_LOGIC;
+		nFB_CS3 : IN STD_LOGIC;
+		DDRCLK0 : IN STD_LOGIC;
+		BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0);
+		BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0);
+		BLITTER_RUN : OUT STD_LOGIC;
+		BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0);
+		BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0);
+		BLITTER_SIG : OUT STD_LOGIC;
+		BLITTER_WR : OUT STD_LOGIC;
+		BLITTER_TA : OUT STD_LOGIC;
+		FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0)
+	);
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+	
+END BLITTER;
+
+
+--  Architecture Body
+
+ARCHITECTURE BLITTER_architecture OF BLITTER IS
+
+	
+BEGIN
+	BLITTER_RUN <= '0';
+	BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
+	BLITTER_ADR <=  x"FEDCBA9876543210";
+	BLITTER_SIG <= '0';
+	BLITTER_WR <= '0';
+	BLITTER_TA <= '0';
+
+END BLITTER_architecture;
diff --git a/FPGA_quartus_GE/Video/DDR_CTR.tdf b/FPGA_quartus_GE/Video/DDR_CTR.tdf
new file mode 100644
index 0000000..d5b5ec2
--- /dev/null
+++ b/FPGA_quartus_GE/Video/DDR_CTR.tdf
@@ -0,0 +1,659 @@
+TITLE "DDR_CTR";
+
+-- CREATED BY FREDI ASCHWANDEN
+
+INCLUDE "lpm_bustri_BYT.inc";
+
+-- FIFO WATER MARK
+CONSTANT FIFO_LWM = 0;
+CONSTANT FIFO_MWM = 200;
+CONSTANT FIFO_HWM = 500;
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+SUBDESIGN DDR_CTR
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	FB_ADR[31..0] : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	nFB_CS3 : INPUT;
+	nFB_OE : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	nRSTO : INPUT;
+	MAIN_CLK : INPUT;
+	FB_ALE : INPUT;
+	nFB_WR : INPUT;
+	DDR_SYNC_66M : INPUT;
+	CLR_FIFO : INPUT;
+	VIDEO_RAM_CTR[15..0] : INPUT;
+	BLITTER_ADR[31..0] : INPUT;
+	BLITTER_SIG : INPUT;
+	BLITTER_WR : INPUT;
+	DDRCLK0 : INPUT;
+	CLK33M : INPUT;
+	FIFO_MW[8..0] : INPUT;
+	VA[12..0] : OUTPUT;
+	nVWE : OUTPUT;
+	nVRAS : OUTPUT;
+	nVCS : OUTPUT;
+	VCKE : OUTPUT;
+	nVCAS : OUTPUT;
+	FB_LE[3..0] : OUTPUT;
+	FB_VDOE[3..0] : OUTPUT;
+	SR_FIFO_WRE : OUTPUT;
+	SR_DDR_FB : OUTPUT;
+	SR_DDR_WR : OUTPUT;
+	SR_DDRWR_D_SEL : OUTPUT;
+	SR_VDMP[7..0] : OUTPUT;
+	VIDEO_DDR_TA : OUTPUT;
+	SR_BLITTER_DACK : OUTPUT;
+	BA[1..0] : OUTPUT;
+	DDRWR_D_SEL1 : OUTPUT;
+	VDM_SEL[3..0] : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	FB_REGDDR				:MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);	
+	DDR_SM					:MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8,					-- START (NORMAL 8 CYCLES TOTAL = 60ns)
+													   DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, 		 					-- CONFIG 
+												                   DS_T4R,DS_T5R,										-- READ CPU UND BLITTER,  
+												                   DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W,		 	-- WRITE CPU UND BLITTER
+												                   DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, 	-- READ FIFO
+																				 DS_CB6,       DS_CB8,					-- CLOSE FIFO BANK
+												       DS_R2,DS_R3,DS_R4, DS_R5, DS_R6);		 						-- REFRESH 10X7.5NS=75NS
+	LINE					:NODE;
+	FB_B[3..0]				:NODE;
+	VCAS					:NODE;
+	VRAS					:NODE;
+	VWE						:NODE;
+	VA_P[12..0]				:DFF;
+	BA_P[1..0]				:DFF;
+	VA_S[12..0]				:DFF;
+	BA_S[1..0]				:DFF;
+	MCS[1..0]				:DFF;
+	CPU_DDR_SYNC			:DFF;
+	DDR_SEL					:NODE;
+	DDR_CS					:DFFE;
+	DDR_CONFIG				:NODE;
+	SR_DDR_WR				:DFF;
+	SR_DDRWR_D_SEL			:DFF;
+	SR_VDMP[7..0] 			:DFF;
+	CPU_ROW_ADR[12..0]		:NODE;
+	CPU_BA[1..0]			:NODE;
+	CPU_COL_ADR[9..0]		:NODE;
+	CPU_SIG					:NODE;
+	CPU_REQ					:DFF;
+	CPU_AC					:DFF;
+	BUS_CYC					:DFF;
+	BUS_CYC_END				:NODE;
+	BLITTER_REQ				:DFF;
+	BLITTER_AC				:DFF;
+	BLITTER_ROW_ADR[12..0]	:NODE;
+	BLITTER_BA[1..0]		:NODE;
+	BLITTER_COL_ADR[9..0]	:NODE;
+	FIFO_REQ				:DFF;
+	FIFO_AC					:DFF;
+	FIFO_ROW_ADR[12..0]		:NODE;
+	FIFO_BA[1..0]			:NODE;
+	FIFO_COL_ADR[9..0]		:NODE;
+	FIFO_ACTIVE				:NODE;
+	CLR_FIFO_SYNC			:DFF;
+	CLEAR_FIFO_CNT			:DFF;
+	STOP					:DFF;
+	SR_FIFO_WRE				:DFF;
+	FIFO_BANK_OK			:DFF;
+	FIFO_BANK_NOT_OK		:NODE;
+	DDR_REFRESH_ON			:NODE;
+	DDR_REFRESH_CNT[10..0]	:DFF;
+	DDR_REFRESH_REQ			:DFF;
+	DDR_REFRESH_SIG[3..0]	:DFFE;
+	REFRESH_TIME			:DFF;
+	VIDEO_BASE_L_D[7..0]	:DFFE;
+	VIDEO_BASE_L			:NODE;
+	VIDEO_BASE_M_D[7..0]	:DFFE;
+	VIDEO_BASE_M			:NODE;
+	VIDEO_BASE_H_D[7..0]	:DFFE;
+	VIDEO_BASE_H			:NODE;
+	VIDEO_BASE_X_D[2..0]	:DFFE;
+	VIDEO_ADR_CNT[22..0]	:DFFE;
+	VIDEO_CNT_L				:NODE;
+	VIDEO_CNT_M				:NODE;
+	VIDEO_CNT_H				:NODE;
+	VIDEO_BASE_ADR[22..0]	:NODE;
+	VIDEO_ACT_ADR[26..0]	:NODE;
+	
+BEGIN
+	LINE =  FB_SIZE0 &  FB_SIZE1;
+-- BYT SELECT
+	FB_B0 = FB_ADR[1..0]==0 								-- ADR==0
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR)  --------------------------------------------------
+	FB_REGDDR.CLK = MAIN_CLK;
+	CASE FB_REGDDR IS
+		WHEN FR_WAIT => 
+			FB_LE0   = !nFB_WR;
+			IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN		-- LOS WENN BEREIT ODER IMMER BEI LINE WRITE
+				FB_REGDDR = FR_S0;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S0 =>
+			IF DDR_CS THEN
+				FB_LE0   = !nFB_WR;
+				VIDEO_DDR_TA = VCC;
+				IF LINE THEN							
+					FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
+					FB_REGDDR = FR_S1;
+				ELSE
+					BUS_CYC_END = VCC;
+					FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
+					FB_REGDDR = FR_WAIT;
+				END IF;
+			ELSE
+				FB_REGDDR = FR_WAIT;	
+			END IF;
+		WHEN FR_S1 => 
+			IF DDR_CS THEN
+				FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
+				FB_LE1   = !nFB_WR;
+				VIDEO_DDR_TA = VCC;
+				FB_REGDDR = FR_S2;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S2 => 
+			IF DDR_CS THEN
+				FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
+				FB_LE2   = !nFB_WR;
+				IF !BUS_CYC & LINE & !nFB_WR THEN		-- BEI LINE WRITE EVT. WARTEN
+					FB_REGDDR = FR_S2;
+				ELSE
+					VIDEO_DDR_TA = VCC;
+					FB_REGDDR = FR_S3;
+				END IF;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S3 => 
+			IF DDR_CS THEN
+				FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
+				FB_LE3   = !nFB_WR;
+				VIDEO_DDR_TA = VCC;
+				BUS_CYC_END = VCC;
+				FB_REGDDR = FR_WAIT;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+	END CASE;
+-- DDR STEUERUNG -----------------------------------------------------
+-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; 
+	VCKE = VIDEO_RAM_CTR0;
+	nVCS = !VIDEO_RAM_CTR1;
+	DDR_REFRESH_ON = VIDEO_RAM_CTR2;
+	DDR_CONFIG = VIDEO_RAM_CTR3;	
+	FIFO_ACTIVE = VIDEO_RAM_CTR8;
+--------------------------------
+	CPU_ROW_ADR[] = FB_ADR[26..14];
+	CPU_BA[] = FB_ADR[13..12];
+	CPU_COL_ADR[] = FB_ADR[11..2];
+	nVRAS = !VRAS;
+	nVCAS = !VCAS;
+	nVWE = !VWE;
+	SR_DDR_WR.CLK = DDRCLK0;
+	SR_DDRWR_D_SEL.CLK = DDRCLK0;
+	SR_VDMP[7..0].CLK = DDRCLK0;
+	SR_FIFO_WRE.CLK = DDRCLK0; 
+	CPU_AC.CLK = DDRCLK0;
+	FIFO_AC.CLK = DDRCLK0;
+	BLITTER_AC.CLK = DDRCLK0;
+	DDRWR_D_SEL1 = BLITTER_AC;
+-- SELECT LOGIC
+	DDR_SEL  = FB_ALE & FB_AD[31..30]==B"01";
+	DDR_CS.CLK = MAIN_CLK;
+	DDR_CS.ENA = FB_ALE;
+	DDR_CS	 = DDR_SEL;
+-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER
+	CPU_SIG = DDR_SEL & (nFB_WR # !LINE)  & !DDR_CONFIG					-- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
+			# DDR_SEL          			  &  DDR_CONFIG					-- CONFIG SOFORT LOS
+			# FB_REGDDR==FR_S1 & !nFB_WR; 								-- LINE WRITE SPÄTER
+	CPU_REQ.CLK = DDR_SYNC_66M;
+	CPU_REQ = CPU_SIG 
+			# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC;		-- HALTEN BUS CYC BEGONNEN ODER FERTIG
+	BUS_CYC.CLK = DDRCLK0;
+	BUS_CYC = BUS_CYC & !BUS_CYC_END;
+	-- STATE MACHINE SYNCHRONISIEREN -----------------
+	MCS[].CLK = DDRCLK0;
+	MCS0 = MAIN_CLK;
+	MCS1 = MCS0;		
+	CPU_DDR_SYNC.CLK = DDRCLK0;
+	CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS;				-- NUR 1 WENN EIN
+	---------------------------------------------------
+	VA_S[].CLK = DDRCLK0;
+	BA_S[].CLK = DDRCLK0;
+	VA[] =  VA_S[];
+	BA[] =  BA_S[];
+	VA_P[].CLK = DDRCLK0;
+	BA_P[].CLK = DDRCLK0;
+-- DDR STATE MACHINE  -----------------------------------------------
+	DDR_SM.CLK = DDRCLK0;
+	CASE DDR_SM IS
+		WHEN DS_T1 =>
+			IF DDR_REFRESH_REQ THEN
+				DDR_SM = DS_R2;
+			ELSE
+				IF CPU_DDR_SYNC THEN							-- SYNCHRON UND EIN?
+					IF DDR_CONFIG THEN							-- JA
+						DDR_SM = DS_C2;
+					ELSE
+						IF CPU_REQ THEN							-- BEI WAIT UND LINE WRITE
+							VA_S[] = CPU_ROW_ADR[];
+							BA_S[] = CPU_BA[];
+							CPU_AC = VCC;
+							BUS_CYC = VCC;
+							DDR_SM = DS_T2B;
+						ELSE
+							IF FIFO_REQ # !BLITTER_REQ THEN			-- FIFO IST DEFAULT
+								VA_P[] = FIFO_ROW_ADR[];
+								BA_P[] = FIFO_BA[];
+								FIFO_AC = VCC;						-- VORBESETZEN
+							ELSE
+								VA_P[] = BLITTER_ROW_ADR[];
+								BA_P[] = BLITTER_BA[];
+								BLITTER_AC = VCC;					-- VORBESETZEN
+							END IF;
+							DDR_SM = DS_T2A;
+						END IF;
+					END IF;
+				ELSE
+					DDR_SM = DS_T1;									-- NEIN ->SYNCHRONISIEREN
+				END IF;
+			END IF;
+			
+		WHEN DS_T2A =>												-- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK ***
+			IF DDR_SEL & (nFB_WR # !LINE) THEN
+				VRAS = VCC;
+				VA[] = FB_AD[26..14];
+				BA[] = FB_AD[13..12]; 
+				VA_S[10] = VCC;										-- AUTO PRECHARGE DA NICHT FIFO PAGE  
+				CPU_AC = VCC;
+				BUS_CYC = VCC;										-- BUS CYCLUS LOSTRETEN
+			ELSE
+				VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ;
+				VA[] = VA_P[];
+				BA[] = BA_P[]; 
+				VA_S[10] = !(FIFO_AC & FIFO_REQ);
+				FIFO_BANK_OK = FIFO_AC & FIFO_REQ;
+				FIFO_AC = FIFO_AC & FIFO_REQ;
+				BLITTER_AC = BLITTER_AC & BLITTER_REQ;
+			END IF;	
+			DDR_SM = DS_T3;
+
+		WHEN DS_T2B =>
+			VRAS = VCC;
+			FIFO_BANK_NOT_OK = VCC;
+			CPU_AC = VCC;
+			BUS_CYC = VCC;											-- BUS CYCLUS LOSTRETEN
+			DDR_SM = DS_T3;
+
+		WHEN DS_T3 =>
+			CPU_AC = CPU_AC;
+			FIFO_AC = FIFO_AC;
+			BLITTER_AC = BLITTER_AC;
+			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
+			IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN
+				DDR_SM = DS_T4W;
+			ELSE
+				IF CPU_AC THEN										-- CPU?
+					VA_S[9..0] = CPU_COL_ADR[];
+					BA_S[] = CPU_BA[];
+					DDR_SM = DS_T4R;												 
+				ELSE
+					IF FIFO_AC THEN									-- FIFO?
+						VA_S[9..0] = FIFO_COL_ADR[];
+						BA_S[] = FIFO_BA[];
+						DDR_SM = DS_T4F;
+					ELSE
+						IF BLITTER_AC THEN
+							VA_S[9..0] = BLITTER_COL_ADR[];
+							BA_S[] = BLITTER_BA[];
+							DDR_SM = DS_T4R;												 
+						ELSE
+							DDR_SM = DS_N8;
+						END IF;
+					END IF;
+				END IF;
+			END IF;
+-- READ			
+		WHEN DS_T4R =>
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			VCAS = VCC;															
+			SR_DDR_FB = CPU_AC;										-- READ DATEN FÜR CPU
+			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER DACK AND BLITTER LATCH DATEN
+			DDR_SM = DS_T5R;	
+			
+		WHEN DS_T5R =>
+ 			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			IF FIFO_REQ & FIFO_BANK_OK THEN							-- FIFO READ EINSCHIEBEN WENN BANK OK
+ 				VA_S[9..0] = FIFO_COL_ADR[];
+ 				VA_S[10] = GND;										-- MANUEL PRECHARGE
+ 				BA_S[] = FIFO_BA[];
+				DDR_SM = DS_T6F;
+ 			ELSE	
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
+				DDR_SM = DS_CB6;
+			END IF;
+-- WRITE			
+		WHEN DS_T4W =>
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER ACK AND BLITTER LATCH DATEN
+			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
+ 			DDR_SM = DS_T5W;
+			
+		WHEN DS_T5W =>
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			VA_S[9..0] = CPU_AC     & CPU_COL_ADR[]
+					   # BLITTER_AC & BLITTER_COL_ADR[];
+			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
+			BA_S[]  = CPU_AC     & CPU_BA[]
+				    # BLITTER_AC & BLITTER_BA[];
+			SR_VDMP[7..4] = FB_B[];									-- BYTE ENABLE WRITE
+			SR_VDMP[3..0] = LINE & B"1111";							-- LINE ENABLE WRITE
+			DDR_SM = DS_T6W;
+			
+		WHEN DS_T6W =>								 
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			VCAS = VCC;															
+			VWE  = VCC;
+			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITER
+			SR_DDRWR_D_SEL = VCC;									-- 2. HÄLFTE WRITE DATEN SELEKTIEREN
+			SR_VDMP[] = LINE & B"11111111";							-- WENN LINE DANN ACTIV 
+			DDR_SM = DS_T7W;
+
+		WHEN DS_T7W =>								 
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITE
+			SR_DDRWR_D_SEL = VCC;									-- 2. HÄLFTE WRITE DATEN SELEKTIEREN
+			DDR_SM = DS_T8W;
+
+		WHEN DS_T8W =>								 
+			DDR_SM = DS_T9W;
+
+		WHEN DS_T9W =>								 
+			IF FIFO_REQ & FIFO_BANK_OK  THEN
+				VA_S[9..0] = FIFO_COL_ADR[];
+				VA_S[10] = GND;										-- NON AUTO PRECHARGE  
+				BA_S[] = FIFO_BA[];
+				DDR_SM = DS_T6F;
+			ELSE
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
+				DDR_SM = DS_CB6;
+			END IF;
+-- FIFO READ 
+		WHEN DS_T4F =>
+			VCAS = VCC;															
+			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
+			DDR_SM = DS_T5F;
+			
+		WHEN DS_T5F =>
+			IF FIFO_REQ THEN
+				IF VIDEO_ADR_CNT[7..0]==H"FF" THEN					-- NEUE PAGE?
+					VA_S[10] = VCC;									-- ALLE PAGES SCHLIESSEN  
+					DDR_SM = DS_CB6;								-- BANK SCHLIESSEN
+				ELSE
+					VA_S[9..0] = FIFO_COL_ADR[]+4;
+					VA_S[10] = GND;									-- NON AUTO PRECHARGE  
+					BA_S[] = FIFO_BA[];
+					DDR_SM = DS_T6F;
+				END IF;											 
+			ELSE
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
+				DDR_SM = DS_CB6;									-- NOCH OFFEN LASSEN
+			END IF;
+			
+		WHEN DS_T6F =>
+			VCAS = VCC;															
+			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
+			DDR_SM = DS_T7F;
+																							 
+		WHEN DS_T7F =>
+			IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN	
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESEN 
+				DDR_SM = DS_CB8;									-- BANK SCHLIESSEN
+			ELSE
+				IF FIFO_REQ THEN
+					IF VIDEO_ADR_CNT[7..0]==H"FF" THEN				-- NEUE PAGE?
+						VA_S[10] = VCC;								-- ALLE PAGES SCHLIESSEN 
+						DDR_SM = DS_CB8;							-- BANK SCHLIESSEN
+					ELSE
+						VA_S[9..0] = FIFO_COL_ADR[]+4;
+						VA_S[10] = GND;								-- NON AUTO PRECHARGE  
+						BA_S[] = FIFO_BA[];
+						DDR_SM = DS_T8F;
+					END IF;											 
+				ELSE
+					VA_S[10] = VCC;									-- ALLE PAGES SCHLIESEN 
+					DDR_SM = DS_CB8;								-- BANK SCHLIESSEN
+				END IF;
+			END IF;
+			
+		WHEN DS_T8F =>
+			VCAS = VCC;															
+			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
+			IF FIFO_MW[]<FIFO_LWM THEN								-- NOTFALL?
+				DDR_SM = DS_T5F;									-- JA->
+			ELSE
+				DDR_SM = DS_T9F;
+			END IF;																	 
+			
+		WHEN DS_T9F =>
+			IF FIFO_REQ THEN
+				IF VIDEO_ADR_CNT[7..0]==H"FF" THEN					-- NEUE PAGE?
+					VA_S[10] = VCC;									-- ALLE BANKS SCHLIESEN 
+					DDR_SM = DS_CB6;								-- BANK SCHLIESSEN
+				ELSE
+ 					VA_P[9..0] = FIFO_COL_ADR[]+4;
+					VA_P[10] = GND;									-- NON AUTO PRECHARGE  
+					BA_P[] = FIFO_BA[];
+					DDR_SM = DS_T10F;
+ 				END IF;											 
+			ELSE
+				VA_S[10] = VCC;										-- ALLE BANKS SCHLIESEN 
+				DDR_SM = DS_CB6;									-- BANK SCHLIESSEN
+			END IF;
+
+		WHEN DS_T10F =>
+ 			IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN
+ 				VRAS = VCC;
+ 				VA[] = FB_AD[26..14];
+ 				BA[] = FB_AD[13..12]; 
+ 				CPU_AC = VCC;
+ 				BUS_CYC = VCC;										-- BUS CYCLUS LOSTRETEN
+ 				VA_S[10] = VCC;										-- AUTO PRECHARGE DA NICHT FIFO BANK
+ 				DDR_SM = DS_T3;
+ 			ELSE
+				VCAS = VCC;
+				VA[] = VA_P[];
+				BA[] = BA_P[];
+				SR_FIFO_WRE = VCC;									-- DATEN WRITE FIFO
+				DDR_SM = DS_T7F;
+			END IF;	
+
+-- CONFIG CYCLUS
+		WHEN DS_C2 =>
+			DDR_SM = DS_C3;
+		WHEN DS_C3 =>
+			BUS_CYC = CPU_REQ;
+			DDR_SM = DS_C4;
+		WHEN DS_C4 =>
+			IF CPU_REQ THEN
+				DDR_SM = DS_C5;
+			ELSE
+				DDR_SM = DS_T1;
+			END IF;	
+		WHEN DS_C5 =>
+			DDR_SM = DS_C6;
+		WHEN DS_C6 =>
+			VA_S[] = FB_AD[12..0];
+			BA_S[] = FB_AD[14..13];
+			DDR_SM = DS_C7;
+		WHEN DS_C7 =>
+			VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
+			VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
+			VWE	 = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
+			DDR_SM = DS_N8;
+-- CLOSE FIFO BANK
+		WHEN DS_CB6 =>
+			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
+			VRAS = VCC;									-- BÄNKE SCHLIESSEN
+			VWE = VCC;
+			DDR_SM = DS_N7;
+		WHEN DS_CB8 =>
+			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
+			VRAS = VCC;									-- BÄNKE SCHLIESSEN
+			VWE = VCC;
+			DDR_SM = DS_T1;
+-- REFRESH 70NS = 10 ZYCLEN
+		WHEN DS_R2 =>
+			IF DDR_REFRESH_SIG[]==9 THEN				-- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
+				VRAS = VCC;								-- ALLE BANKS SCHLIESSEN
+				VWE = VCC;		
+				VA[10] = VCC;
+				FIFO_BANK_NOT_OK = VCC;
+				DDR_SM = DS_R4;
+			ELSE
+				VCAS = VCC;
+				VRAS = VCC;
+				DDR_SM = DS_R3;
+			END IF;
+		WHEN DS_R3 =>
+			DDR_SM = DS_R4;
+		WHEN DS_R4 =>
+			DDR_SM = DS_R5;
+		WHEN DS_R5 =>
+			DDR_SM = DS_R6;
+		WHEN DS_R6 =>
+			DDR_SM = DS_N5;
+-- LEERSCHLAUFE			
+		WHEN DS_N5 =>
+			DDR_SM = DS_N6;
+		WHEN DS_N6 =>
+			DDR_SM = DS_N7;
+		WHEN DS_N7 =>
+			DDR_SM = DS_N8;
+		WHEN DS_N8 =>
+			DDR_SM = DS_T1;
+	END CASE;
+
+---------------------------------------------------------------
+-- BLITTER ----------------------
+-----------------------------------------
+	BLITTER_REQ.CLK = DDRCLK0;
+	BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
+	BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
+	BLITTER_BA1 = BLITTER_ADR13;
+	BLITTER_BA0 = BLITTER_ADR12;
+	BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
+------------------------------------------------------------------------------	
+-- FIFO ---------------------------------
+--------------------------------------------------------
+	FIFO_REQ.CLK = DDRCLK0;
+	FIFO_REQ = (FIFO_MW[]<FIFO_MWM
+			  # FIFO_MW[]<FIFO_HWM & FIFO_REQ) & FIFO_ACTIVE & !CLEAR_FIFO_CNT & !STOP & !DDR_CONFIG & VCKE & !nVCS;
+	FIFO_ROW_ADR[] = VIDEO_ADR_CNT[22..10];
+	FIFO_BA1 	   = VIDEO_ADR_CNT9;
+	FIFO_BA0 	   = VIDEO_ADR_CNT8;
+	FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
+	FIFO_BANK_OK.CLK = DDRCLK0;
+	FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
+	-- ZÄHLER RÜCKSETZEN WENN CLR FIFO ----------------
+	CLR_FIFO_SYNC.CLK =DDRCLK0;
+	CLR_FIFO_SYNC = CLR_FIFO;				-- SYNCHRONISIEREN
+	CLEAR_FIFO_CNT.CLK  = DDRCLK0;
+	CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
+	STOP.CLK = DDRCLK0;
+	STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
+	-- ZÄHLEN -----------------------------------------------
+	VIDEO_ADR_CNT[].CLK = DDRCLK0;
+	VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
+	VIDEO_ADR_CNT[] =  CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
+					# !CLEAR_FIFO_CNT & VIDEO_ADR_CNT[]+1;	
+	VIDEO_BASE_ADR[22..20] = VIDEO_BASE_X_D[];
+	VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
+	VIDEO_BASE_ADR[11..4]  = VIDEO_BASE_M_D[];
+	VIDEO_BASE_ADR[3..0]   = VIDEO_BASE_L_D[7..4];
+	VDM_SEL[] = VIDEO_BASE_L_D[3..0];
+	-- AKTUELLE VIDEO ADRESSE
+	VIDEO_ACT_ADR[26..4] = VIDEO_ADR_CNT[] - (0,FIFO_MW[]);
+	VIDEO_ACT_ADR[3..0] = VDM_SEL[];
+-----------------------------------------------------------------------------------------
+-- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
+-----------------------------------------------------------------------------------------
+	DDR_REFRESH_CNT[].CLK = CLK33M;
+	DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1;													-- ZÄHLEN 0-2047 
+	REFRESH_TIME.CLK = DDRCLK0;
+	REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK;											-- SYNC
+	DDR_REFRESH_SIG[].CLK = DDRCLK0;												
+	DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;				
+	DDR_REFRESH_SIG[] =  REFRESH_TIME & 9                     & DDR_REFRESH_ON & !DDR_CONFIG	-- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF)
+					  # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; 	-- MINUS 1 WENN GEMACHT
+	DDR_REFRESH_REQ.CLK = DDRCLK0;
+	DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;
+-----------------------------------------------------------	
+-- VIDEO REGISTER -----------------------
+---------------------------------------------------------------------------------------------------------------------
+	VIDEO_BASE_L_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; 								-- 820D/2
+	VIDEO_BASE_L_D[] = FB_AD[23..16];												-- SORRY, NUR 16 BYT GRENZEN
+	VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;	
+
+	VIDEO_BASE_M_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; 								-- 8203/2
+	VIDEO_BASE_M_D[] = FB_AD[23..16];
+	VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;	
+
+	VIDEO_BASE_H_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100";			 					-- 8200-1/2
+	VIDEO_BASE_H_D[] = FB_AD[23..16];
+	VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;	
+	VIDEO_BASE_X_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_X_D[] = FB_AD[26..24];
+	VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;	
+
+	VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; 								-- 8209/2
+	VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; 								-- 8207/2
+	VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; 								-- 8204,5/2
+					  
+	FB_AD[31..24] = lpm_bustri_BYT(
+						VIDEO_BASE_H  & (0,VIDEO_BASE_X_D[]) 
+					  # VIDEO_CNT_H	  & (0,VIDEO_ACT_ADR[26..24])
+					  ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
+
+	FB_AD[23..16] = lpm_bustri_BYT(
+						VIDEO_BASE_L  & VIDEO_BASE_L_D[]
+					  # VIDEO_BASE_M  & VIDEO_BASE_M_D[]
+					  # VIDEO_BASE_H  & VIDEO_BASE_H_D[]
+					  # VIDEO_CNT_L	  & VIDEO_ACT_ADR[7..0]
+					  # VIDEO_CNT_M	  & VIDEO_ACT_ADR[15..8]
+					  # VIDEO_CNT_H	  & VIDEO_ACT_ADR[23..16]
+					  ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
+END;
+
diff --git a/FPGA_quartus_GE/Video/DDR_CTR.tdf.bak b/FPGA_quartus_GE/Video/DDR_CTR.tdf.bak
new file mode 100644
index 0000000..ead66e8
--- /dev/null
+++ b/FPGA_quartus_GE/Video/DDR_CTR.tdf.bak
@@ -0,0 +1,660 @@
+TITLE "DDR_CTR";
+
+-- CREATED BY FREDI ASCHWANDEN
+
+INCLUDE "lpm_bustri_BYT.inc";
+
+-- FIFO WATER MARK
+CONSTANT FIFO_LWM = 0;
+CONSTANT FIFO_MWM = 200;
+CONSTANT FIFO_HWM = 500;
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+SUBDESIGN DDR_CTR
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	FB_ADR[31..0] : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	nFB_CS3 : INPUT;
+	nFB_OE : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	nRSTO : INPUT;
+	MAIN_CLK : INPUT;
+	FB_ALE : INPUT;
+	nFB_WR : INPUT;
+	DDR_SYNC_66M : INPUT;
+	CLR_FIFO : INPUT;
+	VIDEO_RAM_CTR[15..0] : INPUT;
+	BLITTER_ADR[31..0] : INPUT;
+	BLITTER_SIG : INPUT;
+	BLITTER_WR : INPUT;
+	DDRCLK0 : INPUT;
+	CLK33M : INPUT;
+	FIFO_MW[8..0] : INPUT;
+	VA[12..0] : OUTPUT;
+	nVWE : OUTPUT;
+	nVRAS : OUTPUT;
+	nVCS : OUTPUT;
+	VCKE : OUTPUT;
+	nVCAS : OUTPUT;
+	FB_LE[3..0] : OUTPUT;
+	FB_VDOE[3..0] : OUTPUT;
+	CLEAR_FIFO_CNT : OUTPUT;
+	SR_FIFO_WRE : OUTPUT;
+	SR_DDR_FB : OUTPUT;
+	SR_DDR_WR : OUTPUT;
+	SR_DDRWR_D_SEL : OUTPUT;
+	SR_VDMP[7..0] : OUTPUT;
+	VIDEO_DDR_TA : OUTPUT;
+	SR_BLITTER_DACK : OUTPUT;
+	BA[1..0] : OUTPUT;
+	DDRWR_D_SEL1 : OUTPUT;
+	VDM_SEL[3..0] : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	FB_REGDDR				:MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);	
+	DDR_SM					:MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8,					-- START (NORMAL 8 CYCLES TOTAL = 60ns)
+													   DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, 		 					-- CONFIG 
+												                   DS_T4R,DS_T5R,										-- READ CPU UND BLITTER,  
+												                   DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W,		 	-- WRITE CPU UND BLITTER
+												                   DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, 	-- READ FIFO
+																				 DS_CB6,       DS_CB8,					-- CLOSE FIFO BANK
+												       DS_R2,DS_R3,DS_R4, DS_R5, DS_R6);		 						-- REFRESH 10X7.5NS=75NS
+	LINE					:NODE;
+	FB_B[3..0]				:NODE;
+	VCAS					:NODE;
+	VRAS					:NODE;
+	VWE						:NODE;
+	VA_P[12..0]				:DFF;
+	BA_P[1..0]				:DFF;
+	VA_S[12..0]				:DFF;
+	BA_S[1..0]				:DFF;
+	MCS[1..0]				:DFF;
+	CPU_DDR_SYNC			:DFF;
+	DDR_SEL					:NODE;
+	DDR_CS					:DFFE;
+	DDR_CONFIG				:NODE;
+	SR_DDR_WR				:DFF;
+	SR_DDRWR_D_SEL			:DFF;
+	SR_VDMP[7..0] 			:DFF;
+	CPU_ROW_ADR[12..0]		:NODE;
+	CPU_BA[1..0]			:NODE;
+	CPU_COL_ADR[9..0]		:NODE;
+	CPU_SIG					:NODE;
+	CPU_REQ					:DFF;
+	CPU_AC					:DFF;
+	BUS_CYC					:DFF;
+	BUS_CYC_END				:NODE;
+	BLITTER_REQ				:DFF;
+	BLITTER_AC				:DFF;
+	BLITTER_ROW_ADR[12..0]	:NODE;
+	BLITTER_BA[1..0]		:NODE;
+	BLITTER_COL_ADR[9..0]	:NODE;
+	FIFO_REQ				:DFF;
+	FIFO_AC					:DFF;
+	FIFO_ROW_ADR[12..0]		:NODE;
+	FIFO_BA[1..0]			:NODE;
+	FIFO_COL_ADR[9..0]		:NODE;
+	FIFO_ACTIVE				:NODE;
+	CLR_FIFO_SYNC			:DFF;
+	CLEAR_FIFO_CNT			:DFF;
+	STOP					:DFF;
+	SR_FIFO_WRE				:DFF;
+	FIFO_BANK_OK			:DFF;
+	FIFO_BANK_NOT_OK		:NODE;
+	DDR_REFRESH_ON			:NODE;
+	DDR_REFRESH_CNT[10..0]	:DFF;
+	DDR_REFRESH_REQ			:DFF;
+	DDR_REFRESH_SIG[3..0]	:DFFE;
+	REFRESH_TIME			:DFF;
+	VIDEO_BASE_L_D[7..0]	:DFFE;
+	VIDEO_BASE_L			:NODE;
+	VIDEO_BASE_M_D[7..0]	:DFFE;
+	VIDEO_BASE_M			:NODE;
+	VIDEO_BASE_H_D[7..0]	:DFFE;
+	VIDEO_BASE_H			:NODE;
+	VIDEO_BASE_X_D[2..0]	:DFFE;
+	VIDEO_ADR_CNT[22..0]	:DFFE;
+	VIDEO_CNT_L				:NODE;
+	VIDEO_CNT_M				:NODE;
+	VIDEO_CNT_H				:NODE;
+	VIDEO_BASE_ADR[22..0]	:NODE;
+	VIDEO_ACT_ADR[26..0]	:NODE;
+	
+BEGIN
+	LINE =  FB_SIZE0 &  FB_SIZE1;
+-- BYT SELECT
+	FB_B0 = FB_ADR[1..0]==0 								-- ADR==0
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR)  --------------------------------------------------
+	FB_REGDDR.CLK = MAIN_CLK;
+	CASE FB_REGDDR IS
+		WHEN FR_WAIT => 
+			FB_LE0   = !nFB_WR;
+			IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN		-- LOS WENN BEREIT ODER IMMER BEI LINE WRITE
+				FB_REGDDR = FR_S0;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S0 =>
+			IF DDR_CS THEN
+				FB_LE0   = !nFB_WR;
+				VIDEO_DDR_TA = VCC;
+				IF LINE THEN							
+					FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
+					FB_REGDDR = FR_S1;
+				ELSE
+					BUS_CYC_END = VCC;
+					FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
+					FB_REGDDR = FR_WAIT;
+				END IF;
+			ELSE
+				FB_REGDDR = FR_WAIT;	
+			END IF;
+		WHEN FR_S1 => 
+			IF DDR_CS THEN
+				FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
+				FB_LE1   = !nFB_WR;
+				VIDEO_DDR_TA = VCC;
+				FB_REGDDR = FR_S2;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S2 => 
+			IF DDR_CS THEN
+				FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
+				FB_LE2   = !nFB_WR;
+				IF !BUS_CYC & LINE & !nFB_WR THEN		-- BEI LINE WRITE EVT. WARTEN
+					FB_REGDDR = FR_S2;
+				ELSE
+					VIDEO_DDR_TA = VCC;
+					FB_REGDDR = FR_S3;
+				END IF;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S3 => 
+			IF DDR_CS THEN
+				FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
+				FB_LE3   = !nFB_WR;
+				VIDEO_DDR_TA = VCC;
+				BUS_CYC_END = VCC;
+				FB_REGDDR = FR_WAIT;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+	END CASE;
+-- DDR STEUERUNG -----------------------------------------------------
+-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; 
+	VCKE = VIDEO_RAM_CTR0;
+	nVCS = !VIDEO_RAM_CTR1;
+	DDR_REFRESH_ON = VIDEO_RAM_CTR2;
+	DDR_CONFIG = VIDEO_RAM_CTR3;	
+	FIFO_ACTIVE = VIDEO_RAM_CTR8;
+--------------------------------
+	CPU_ROW_ADR[] = FB_ADR[26..14];
+	CPU_BA[] = FB_ADR[13..12];
+	CPU_COL_ADR[] = FB_ADR[11..2];
+	nVRAS = !VRAS;
+	nVCAS = !VCAS;
+	nVWE = !VWE;
+	SR_DDR_WR.CLK = DDRCLK0;
+	SR_DDRWR_D_SEL.CLK = DDRCLK0;
+	SR_VDMP[7..0].CLK = DDRCLK0;
+	SR_FIFO_WRE.CLK = DDRCLK0; 
+	CPU_AC.CLK = DDRCLK0;
+	FIFO_AC.CLK = DDRCLK0;
+	BLITTER_AC.CLK = DDRCLK0;
+	DDRWR_D_SEL1 = BLITTER_AC;
+-- SELECT LOGIC
+	DDR_SEL  = FB_ALE & FB_AD[31..30]==B"01";
+	DDR_CS.CLK = MAIN_CLK;
+	DDR_CS.ENA = FB_ALE;
+	DDR_CS	 = DDR_SEL;
+-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER
+	CPU_SIG = DDR_SEL & (nFB_WR # !LINE)  & !DDR_CONFIG					-- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
+			# DDR_SEL          			  &  DDR_CONFIG					-- CONFIG SOFORT LOS
+			# FB_REGDDR==FR_S1 & !nFB_WR; 								-- LINE WRITE SPÄTER
+	CPU_REQ.CLK = DDR_SYNC_66M;
+	CPU_REQ = CPU_SIG 
+			# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC;		-- HALTEN BUS CYC BEGONNEN ODER FERTIG
+	BUS_CYC.CLK = DDRCLK0;
+	BUS_CYC = BUS_CYC & !BUS_CYC_END;
+	-- STATE MACHINE SYNCHRONISIEREN -----------------
+	MCS[].CLK = DDRCLK0;
+	MCS0 = MAIN_CLK;
+	MCS1 = MCS0;		
+	CPU_DDR_SYNC.CLK = DDRCLK0;
+	CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS;				-- NUR 1 WENN EIN
+	---------------------------------------------------
+	VA_S[].CLK = DDRCLK0;
+	BA_S[].CLK = DDRCLK0;
+	VA[] =  VA_S[];
+	BA[] =  BA_S[];
+	VA_P[].CLK = DDRCLK0;
+	BA_P[].CLK = DDRCLK0;
+-- DDR STATE MACHINE  -----------------------------------------------
+	DDR_SM.CLK = DDRCLK0;
+	CASE DDR_SM IS
+		WHEN DS_T1 =>
+			IF DDR_REFRESH_REQ THEN
+				DDR_SM = DS_R2;
+			ELSE
+				IF CPU_DDR_SYNC THEN							-- SYNCHRON UND EIN?
+					IF DDR_CONFIG THEN							-- JA
+						DDR_SM = DS_C2;
+					ELSE
+						IF CPU_REQ THEN							-- BEI WAIT UND LINE WRITE
+							VA_S[] = CPU_ROW_ADR[];
+							BA_S[] = CPU_BA[];
+							CPU_AC = VCC;
+							BUS_CYC = VCC;
+							DDR_SM = DS_T2B;
+						ELSE
+							IF FIFO_REQ # !BLITTER_REQ THEN			-- FIFO IST DEFAULT
+								VA_P[] = FIFO_ROW_ADR[];
+								BA_P[] = FIFO_BA[];
+								FIFO_AC = VCC;						-- VORBESETZEN
+							ELSE
+								VA_P[] = BLITTER_ROW_ADR[];
+								BA_P[] = BLITTER_BA[];
+								BLITTER_AC = VCC;					-- VORBESETZEN
+							END IF;
+							DDR_SM = DS_T2A;
+						END IF;
+					END IF;
+				ELSE
+					DDR_SM = DS_T1;									-- NEIN ->SYNCHRONISIEREN
+				END IF;
+			END IF;
+			
+		WHEN DS_T2A =>												-- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK ***
+			IF DDR_SEL & (nFB_WR # !LINE) THEN
+				VRAS = VCC;
+				VA[] = FB_AD[26..14];
+				BA[] = FB_AD[13..12]; 
+				VA_S[10] = VCC;										-- AUTO PRECHARGE DA NICHT FIFO PAGE  
+				CPU_AC = VCC;
+				BUS_CYC = VCC;										-- BUS CYCLUS LOSTRETEN
+			ELSE
+				VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ;
+				VA[] = VA_P[];
+				BA[] = BA_P[]; 
+				VA_S[10] = !(FIFO_AC & FIFO_REQ);
+				FIFO_BANK_OK = FIFO_AC & FIFO_REQ;
+				FIFO_AC = FIFO_AC & FIFO_REQ;
+				BLITTER_AC = BLITTER_AC & BLITTER_REQ;
+			END IF;	
+			DDR_SM = DS_T3;
+
+		WHEN DS_T2B =>
+			VRAS = VCC;
+			FIFO_BANK_NOT_OK = VCC;
+			CPU_AC = VCC;
+			BUS_CYC = VCC;											-- BUS CYCLUS LOSTRETEN
+			DDR_SM = DS_T3;
+
+		WHEN DS_T3 =>
+			CPU_AC = CPU_AC;
+			FIFO_AC = FIFO_AC;
+			BLITTER_AC = BLITTER_AC;
+			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
+			IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN
+				DDR_SM = DS_T4W;
+			ELSE
+				IF CPU_AC THEN										-- CPU?
+					VA_S[9..0] = CPU_COL_ADR[];
+					BA_S[] = CPU_BA[];
+					DDR_SM = DS_T4R;												 
+				ELSE
+					IF FIFO_AC THEN									-- FIFO?
+						VA_S[9..0] = FIFO_COL_ADR[];
+						BA_S[] = FIFO_BA[];
+						DDR_SM = DS_T4F;
+					ELSE
+						IF BLITTER_AC THEN
+							VA_S[9..0] = BLITTER_COL_ADR[];
+							BA_S[] = BLITTER_BA[];
+							DDR_SM = DS_T4R;												 
+						ELSE
+							DDR_SM = DS_N8;
+						END IF;
+					END IF;
+				END IF;
+			END IF;
+-- READ			
+		WHEN DS_T4R =>
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			VCAS = VCC;															
+			SR_DDR_FB = CPU_AC;										-- READ DATEN FÜR CPU
+			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER DACK AND BLITTER LATCH DATEN
+			DDR_SM = DS_T5R;	
+			
+		WHEN DS_T5R =>
+ 			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			IF FIFO_REQ & FIFO_BANK_OK THEN							-- FIFO READ EINSCHIEBEN WENN BANK OK
+ 				VA_S[9..0] = FIFO_COL_ADR[];
+ 				VA_S[10] = GND;										-- MANUEL PRECHARGE
+ 				BA_S[] = FIFO_BA[];
+				DDR_SM = DS_T6F;
+ 			ELSE	
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
+				DDR_SM = DS_CB6;
+			END IF;
+-- WRITE			
+		WHEN DS_T4W =>
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER ACK AND BLITTER LATCH DATEN
+			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
+ 			DDR_SM = DS_T5W;
+			
+		WHEN DS_T5W =>
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			VA_S[9..0] = CPU_AC     & CPU_COL_ADR[]
+					   # BLITTER_AC & BLITTER_COL_ADR[];
+			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
+			BA_S[]  = CPU_AC     & CPU_BA[]
+				    # BLITTER_AC & BLITTER_BA[];
+			SR_VDMP[7..4] = FB_B[];									-- BYTE ENABLE WRITE
+			SR_VDMP[3..0] = LINE & B"1111";							-- LINE ENABLE WRITE
+			DDR_SM = DS_T6W;
+			
+		WHEN DS_T6W =>								 
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			VCAS = VCC;															
+			VWE  = VCC;
+			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITER
+			SR_DDRWR_D_SEL = VCC;									-- 2. HÄLFTE WRITE DATEN SELEKTIEREN
+			SR_VDMP[] = LINE & B"11111111";							-- WENN LINE DANN ACTIV 
+			DDR_SM = DS_T7W;
+
+		WHEN DS_T7W =>								 
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITE
+			SR_DDRWR_D_SEL = VCC;									-- 2. HÄLFTE WRITE DATEN SELEKTIEREN
+			DDR_SM = DS_T8W;
+
+		WHEN DS_T8W =>								 
+			DDR_SM = DS_T9W;
+
+		WHEN DS_T9W =>								 
+			IF FIFO_REQ & FIFO_BANK_OK  THEN
+				VA_S[9..0] = FIFO_COL_ADR[];
+				VA_S[10] = GND;										-- NON AUTO PRECHARGE  
+				BA_S[] = FIFO_BA[];
+				DDR_SM = DS_T6F;
+			ELSE
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
+				DDR_SM = DS_CB6;
+			END IF;
+-- FIFO READ 
+		WHEN DS_T4F =>
+			VCAS = VCC;															
+			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
+			DDR_SM = DS_T5F;
+			
+		WHEN DS_T5F =>
+			IF FIFO_REQ THEN
+				IF VIDEO_ADR_CNT[7..0]==H"FF" THEN					-- NEUE PAGE?
+					VA_S[10] = VCC;									-- ALLE PAGES SCHLIESSEN  
+					DDR_SM = DS_CB6;								-- BANK SCHLIESSEN
+				ELSE
+					VA_S[9..0] = FIFO_COL_ADR[]+4;
+					VA_S[10] = GND;									-- NON AUTO PRECHARGE  
+					BA_S[] = FIFO_BA[];
+					DDR_SM = DS_T6F;
+				END IF;											 
+			ELSE
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
+				DDR_SM = DS_CB6;									-- NOCH OFFEN LASSEN
+			END IF;
+			
+		WHEN DS_T6F =>
+			VCAS = VCC;															
+			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
+			DDR_SM = DS_T7F;
+																							 
+		WHEN DS_T7F =>
+			IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN	
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESEN 
+				DDR_SM = DS_CB8;									-- BANK SCHLIESSEN
+			ELSE
+				IF FIFO_REQ THEN
+					IF VIDEO_ADR_CNT[7..0]==H"FF" THEN				-- NEUE PAGE?
+						VA_S[10] = VCC;								-- ALLE PAGES SCHLIESSEN 
+						DDR_SM = DS_CB8;							-- BANK SCHLIESSEN
+					ELSE
+						VA_S[9..0] = FIFO_COL_ADR[]+4;
+						VA_S[10] = GND;								-- NON AUTO PRECHARGE  
+						BA_S[] = FIFO_BA[];
+						DDR_SM = DS_T8F;
+					END IF;											 
+				ELSE
+					VA_S[10] = VCC;									-- ALLE PAGES SCHLIESEN 
+					DDR_SM = DS_CB8;								-- BANK SCHLIESSEN
+				END IF;
+			END IF;
+			
+		WHEN DS_T8F =>
+			VCAS = VCC;															
+			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
+			IF FIFO_MW[]<FIFO_LWM THEN								-- NOTFALL?
+				DDR_SM = DS_T5F;									-- JA->
+			ELSE
+				DDR_SM = DS_T9F;
+			END IF;																	 
+			
+		WHEN DS_T9F =>
+			IF FIFO_REQ THEN
+				IF VIDEO_ADR_CNT[7..0]==H"FF" THEN					-- NEUE PAGE?
+					VA_S[10] = VCC;									-- ALLE BANKS SCHLIESEN 
+					DDR_SM = DS_CB6;								-- BANK SCHLIESSEN
+				ELSE
+ 					VA_P[9..0] = FIFO_COL_ADR[]+4;
+					VA_P[10] = GND;									-- NON AUTO PRECHARGE  
+					BA_P[] = FIFO_BA[];
+					DDR_SM = DS_T10F;
+ 				END IF;											 
+			ELSE
+				VA_S[10] = VCC;										-- ALLE BANKS SCHLIESEN 
+				DDR_SM = DS_CB6;									-- BANK SCHLIESSEN
+			END IF;
+
+		WHEN DS_T10F =>
+ 			IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN
+ 				VRAS = VCC;
+ 				VA[] = FB_AD[26..14];
+ 				BA[] = FB_AD[13..12]; 
+ 				CPU_AC = VCC;
+ 				BUS_CYC = VCC;										-- BUS CYCLUS LOSTRETEN
+ 				VA_S[10] = VCC;										-- AUTO PRECHARGE DA NICHT FIFO BANK
+ 				DDR_SM = DS_T3;
+ 			ELSE
+				VCAS = VCC;
+				VA[] = VA_P[];
+				BA[] = BA_P[];
+				SR_FIFO_WRE = VCC;									-- DATEN WRITE FIFO
+				DDR_SM = DS_T7F;
+			END IF;	
+
+-- CONFIG CYCLUS
+		WHEN DS_C2 =>
+			DDR_SM = DS_C3;
+		WHEN DS_C3 =>
+			BUS_CYC = CPU_REQ;
+			DDR_SM = DS_C4;
+		WHEN DS_C4 =>
+			IF CPU_REQ THEN
+				DDR_SM = DS_C5;
+			ELSE
+				DDR_SM = DS_T1;
+			END IF;	
+		WHEN DS_C5 =>
+			DDR_SM = DS_C6;
+		WHEN DS_C6 =>
+			VA_S[] = FB_AD[12..0];
+			BA_S[] = FB_AD[14..13];
+			DDR_SM = DS_C7;
+		WHEN DS_C7 =>
+			VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
+			VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
+			VWE	 = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
+			DDR_SM = DS_N8;
+-- CLOSE FIFO BANK
+		WHEN DS_CB6 =>
+			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
+			VRAS = VCC;									-- BÄNKE SCHLIESSEN
+			VWE = VCC;
+			DDR_SM = DS_N7;
+		WHEN DS_CB8 =>
+			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
+			VRAS = VCC;									-- BÄNKE SCHLIESSEN
+			VWE = VCC;
+			DDR_SM = DS_T1;
+-- REFRESH 70NS = 10 ZYCLEN
+		WHEN DS_R2 =>
+			IF DDR_REFRESH_SIG[]==9 THEN				-- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
+				VRAS = VCC;								-- ALLE BANKS SCHLIESSEN
+				VWE = VCC;		
+				VA[10] = VCC;
+				FIFO_BANK_NOT_OK = VCC;
+				DDR_SM = DS_R4;
+			ELSE
+				VCAS = VCC;
+				VRAS = VCC;
+				DDR_SM = DS_R3;
+			END IF;
+		WHEN DS_R3 =>
+			DDR_SM = DS_R4;
+		WHEN DS_R4 =>
+			DDR_SM = DS_R5;
+		WHEN DS_R5 =>
+			DDR_SM = DS_R6;
+		WHEN DS_R6 =>
+			DDR_SM = DS_N5;
+-- LEERSCHLAUFE			
+		WHEN DS_N5 =>
+			DDR_SM = DS_N6;
+		WHEN DS_N6 =>
+			DDR_SM = DS_N7;
+		WHEN DS_N7 =>
+			DDR_SM = DS_N8;
+		WHEN DS_N8 =>
+			DDR_SM = DS_T1;
+	END CASE;
+
+---------------------------------------------------------------
+-- BLITTER ----------------------
+-----------------------------------------
+	BLITTER_REQ.CLK = DDRCLK0;
+	BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
+	BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
+	BLITTER_BA1 = BLITTER_ADR13;
+	BLITTER_BA0 = BLITTER_ADR12;
+	BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
+------------------------------------------------------------------------------	
+-- FIFO ---------------------------------
+--------------------------------------------------------
+	FIFO_REQ.CLK = DDRCLK0;
+	FIFO_REQ = (FIFO_MW[]<FIFO_MWM
+			  # FIFO_MW[]<FIFO_HWM & FIFO_REQ) & FIFO_ACTIVE & !CLEAR_FIFO_CNT & !STOP & !DDR_CONFIG & VCKE & !nVCS;
+	FIFO_ROW_ADR[] = VIDEO_ADR_CNT[22..10];
+	FIFO_BA1 	   = VIDEO_ADR_CNT9;
+	FIFO_BA0 	   = VIDEO_ADR_CNT8;
+	FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
+	FIFO_BANK_OK.CLK = DDRCLK0;
+	FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
+	-- ZÄHLER RÜCKSETZEN WENN CLR FIFO ----------------
+	CLR_FIFO_SYNC.CLK =DDRCLK0;
+	CLR_FIFO_SYNC = CLR_FIFO;				-- SYNCHRONISIEREN
+	CLEAR_FIFO_CNT.CLK  = DDRCLK0;
+	CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
+	STOP.CLK = DDRCLK0;
+	STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
+	-- ZÄHLEN -----------------------------------------------
+	VIDEO_ADR_CNT[].CLK = DDRCLK0;
+	VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
+	VIDEO_ADR_CNT[] =  CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
+					# !CLEAR_FIFO_CNT & VIDEO_ADR_CNT[]+1;	
+	VIDEO_BASE_ADR[22..20] = VIDEO_BASE_X_D[];
+	VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
+	VIDEO_BASE_ADR[11..4]  = VIDEO_BASE_M_D[];
+	VIDEO_BASE_ADR[3..0]   = VIDEO_BASE_L_D[7..4];
+	VDM_SEL[] = VIDEO_BASE_L_D[3..0];
+	-- AKTUELLE VIDEO ADRESSE
+	VIDEO_ACT_ADR[26..4] = VIDEO_ADR_CNT[] - (0,FIFO_MW[]);
+	VIDEO_ACT_ADR[3..0] = VDM_SEL[];
+-----------------------------------------------------------------------------------------
+-- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
+-----------------------------------------------------------------------------------------
+	DDR_REFRESH_CNT[].CLK = CLK33M;
+	DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1;													-- ZÄHLEN 0-2047 
+	REFRESH_TIME.CLK = DDRCLK0;
+	REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK;											-- SYNC
+	DDR_REFRESH_SIG[].CLK = DDRCLK0;												
+	DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;				
+	DDR_REFRESH_SIG[] =  REFRESH_TIME & 9                     & DDR_REFRESH_ON & !DDR_CONFIG	-- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF)
+					  # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; 	-- MINUS 1 WENN GEMACHT
+	DDR_REFRESH_REQ.CLK = DDRCLK0;
+	DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;
+-----------------------------------------------------------	
+-- VIDEO REGISTER -----------------------
+---------------------------------------------------------------------------------------------------------------------
+	VIDEO_BASE_L_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; 								-- 820D/2
+	VIDEO_BASE_L_D[] = FB_AD[23..16];												-- SORRY, NUR 16 BYT GRENZEN
+	VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;	
+
+	VIDEO_BASE_M_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; 								-- 8203/2
+	VIDEO_BASE_M_D[] = FB_AD[23..16];
+	VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;	
+
+	VIDEO_BASE_H_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100";			 					-- 8200-1/2
+	VIDEO_BASE_H_D[] = FB_AD[23..16];
+	VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;	
+	VIDEO_BASE_X_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_X_D[] = FB_AD[26..24];
+	VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;	
+
+	VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; 								-- 8209/2
+	VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; 								-- 8207/2
+	VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; 								-- 8204,5/2
+					  
+	FB_AD[31..24] = lpm_bustri_BYT(
+						VIDEO_BASE_H  & (0,VIDEO_BASE_X_D[]) 
+					  # VIDEO_CNT_H	  & (0,VIDEO_ACT_ADR[26..24])
+					  ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
+
+	FB_AD[23..16] = lpm_bustri_BYT(
+						VIDEO_BASE_L  & VIDEO_BASE_L_D[]
+					  # VIDEO_BASE_M  & VIDEO_BASE_M_D[]
+					  # VIDEO_BASE_H  & VIDEO_BASE_H_D[]
+					  # VIDEO_CNT_L	  & VIDEO_ACT_ADR[7..0]
+					  # VIDEO_CNT_M	  & VIDEO_ACT_ADR[15..8]
+					  # VIDEO_CNT_H	  & VIDEO_ACT_ADR[23..16]
+					  ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
+END;
+
diff --git a/FPGA_quartus_GE/Video/DDR_CTR.v b/FPGA_quartus_GE/Video/DDR_CTR.v
new file mode 100644
index 0000000..238a56b
--- /dev/null
+++ b/FPGA_quartus_GE/Video/DDR_CTR.v
@@ -0,0 +1,1095 @@
+// Xilinx XPort Language Converter, Version 4.1 (110)
+// 
+// AHDL    Design Source: DDR_CTR.tdf
+// Verilog Design Output: DDR_CTR.v
+// Created 03-Mar-2014 09:18 PM
+//
+// Copyright (c) 2014, Xilinx, Inc.  All Rights Reserved.
+// Xilinx Inc makes no warranty, expressed or implied, with respect to
+// the operation and/or functionality of the converted output files.
+// 
+
+// DDR_CTR
+
+
+//  CREATED BY FREDI ASCHWANDEN
+//  FIFO WATER MARK
+//  {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+//  {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+module DDR_CTR(FB_ADR, nFB_CS1, nFB_CS2, nFB_CS3, nFB_OE, FB_SIZE0, FB_SIZE1,
+      nRSTO, MAIN_CLK, FB_ALE, nFB_WR, DDR_SYNC_66M, CLR_FIFO, VIDEO_RAM_CTR,
+      BLITTER_ADR, BLITTER_SIG, BLITTER_WR, DDRCLK0, CLK33M, FIFO_MW, VA, nVWE,
+      nVRAS, nVCS, VCKE, nVCAS, FB_LE, FB_VDOE, SR_FIFO_WRE, SR_DDR_FB,
+      SR_DDR_WR, SR_DDRWR_D_SEL, SR_VDMP, VIDEO_DDR_TA, SR_BLITTER_DACK, BA,
+      DDRWR_D_SEL1, VDM_SEL, FB_AD);
+
+//  {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+//  {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+   input [31:0] FB_ADR;
+   input nFB_CS1, nFB_CS2, nFB_CS3, nFB_OE, FB_SIZE0, FB_SIZE1, nRSTO,
+	 MAIN_CLK, FB_ALE, nFB_WR, DDR_SYNC_66M, CLR_FIFO;
+   input [15:0] VIDEO_RAM_CTR;
+   input [31:0] BLITTER_ADR;
+   input BLITTER_SIG, BLITTER_WR, DDRCLK0, CLK33M;
+   input [8:0] FIFO_MW;
+   output [12:0] VA;
+   output nVWE, nVRAS, nVCS, VCKE, nVCAS;
+   output [3:0] FB_LE;
+   output [3:0] FB_VDOE;
+   output SR_FIFO_WRE, SR_DDR_FB, SR_DDR_WR, SR_DDRWR_D_SEL;
+   output [7:0] SR_VDMP;
+   output VIDEO_DDR_TA, SR_BLITTER_DACK;
+   output [1:0] BA;
+   output DDRWR_D_SEL1;
+   output [3:0] VDM_SEL;
+   reg [3:0] FB_LE;
+   reg [3:0] FB_VDOE;
+   reg SR_DDR_FB, VIDEO_DDR_TA, SR_BLITTER_DACK;
+   inout [31:0] FB_AD;
+
+//  START (NORMAL 8 CYCLES TOTAL = 60ns)
+//  CONFIG
+//  READ CPU UND BLITTER,
+//  WRITE CPU UND BLITTER
+//  READ FIFO
+//  CLOSE FIFO BANK
+//  REFRESH 10X7.5NS=75NS
+   wire [2:0] FB_REGDDR_;
+   wire [5:0] DDR_SM_;
+   wire LINE;
+   wire [3:0] FB_B;
+   wire [12:0] VA_P;
+   wire [1:0] BA_P;
+   wire [12:0] VA_S;
+   wire [1:0] BA_S;
+   wire [1:0] MCS;
+   wire [1:0] MCS_d;
+   wire CPU_DDR_SYNC, CPU_DDR_SYNC_d, CPU_DDR_SYNC_clk, DDR_SEL, DDR_CS,
+	 DDR_CS_d, DDR_CS_clk, DDR_CS_ena, DDR_CONFIG, SR_DDR_WR_clk,
+	 SR_DDRWR_D_SEL_clk;
+   wire [12:0] CPU_ROW_ADR;
+   wire [1:0] CPU_BA;
+   wire [9:0] CPU_COL_ADR;
+   wire CPU_SIG, CPU_REQ, CPU_REQ_d, CPU_REQ_clk, CPU_AC, CPU_AC_clk, BUS_CYC,
+	 BUS_CYC_d, BUS_CYC_clk, BLITTER_REQ, BLITTER_REQ_d, BLITTER_REQ_clk,
+	 BLITTER_AC, BLITTER_AC_clk;
+   wire [12:0] BLITTER_ROW_ADR;
+   wire [1:0] BLITTER_BA;
+   wire [9:0] BLITTER_COL_ADR;
+   wire FIFO_REQ, FIFO_REQ_d, FIFO_REQ_clk, FIFO_AC, FIFO_AC_clk;
+   wire [12:0] FIFO_ROW_ADR;
+   wire [1:0] FIFO_BA;
+   wire [9:0] FIFO_COL_ADR;
+   wire FIFO_ACTIVE, CLR_FIFO_SYNC, CLR_FIFO_SYNC_d, CLR_FIFO_SYNC_clk,
+	 CLEAR_FIFO_CNT, CLEAR_FIFO_CNT_d, CLEAR_FIFO_CNT_clk, STOP, STOP_d,
+	 STOP_clk, SR_FIFO_WRE_clk, FIFO_BANK_OK, FIFO_BANK_OK_d,
+	 FIFO_BANK_OK_clk, DDR_REFRESH_ON;
+   wire [10:0] DDR_REFRESH_CNT;
+   wire [10:0] DDR_REFRESH_CNT_d;
+   wire DDR_REFRESH_REQ, DDR_REFRESH_REQ_d, DDR_REFRESH_REQ_clk;
+   wire [3:0] DDR_REFRESH_SIG;
+   wire [3:0] DDR_REFRESH_SIG_d;
+   wire REFRESH_TIME, REFRESH_TIME_d, REFRESH_TIME_clk;
+   wire [7:0] VIDEO_BASE_L_D;
+   wire [7:0] VIDEO_BASE_L_D_d;
+   wire VIDEO_BASE_L;
+   wire [7:0] VIDEO_BASE_M_D;
+   wire [7:0] VIDEO_BASE_M_D_d;
+   wire VIDEO_BASE_M;
+   wire [7:0] VIDEO_BASE_H_D;
+   wire [7:0] VIDEO_BASE_H_D_d;
+   wire VIDEO_BASE_H;
+   wire [2:0] VIDEO_BASE_X_D;
+   wire [2:0] VIDEO_BASE_X_D_d;
+   wire [7:0] VIDEO_BASE_X_D_FULL;
+   wire [22:0] VIDEO_ADR_CNT;
+   wire [22:0] VIDEO_ADR_CNT_d;
+   wire VIDEO_CNT_L, VIDEO_CNT_M, VIDEO_CNT_H;
+   wire [22:0] VIDEO_BASE_ADR;
+   wire [26:0] VIDEO_ACT_ADR;
+   wire vcc, gnd;
+   wire [7:0] u0_data;
+   wire u0_enabledt;
+   wire [7:0] u0_tridata;
+   wire [7:0] u1_data;
+   wire u1_enabledt;
+   wire [7:0] u1_tridata;
+   wire FIFO_BANK_OK_d_2, BUS_CYC_d_1, BA0_1, BA1_1, VA0_1, VA1_1, VA2_1,
+	 VA3_1, VA4_1, VA5_1, VA6_1, VA7_1, VA8_1, VA9_1, VA10_1, VA11_1,
+	 VA12_1, VIDEO_BASE_X_D0_ena_ctrl, VIDEO_BASE_X_D0_clk_ctrl,
+	 VIDEO_BASE_H_D0_ena_ctrl, VIDEO_BASE_H_D0_clk_ctrl,
+	 VIDEO_BASE_M_D0_ena_ctrl, VIDEO_BASE_M_D0_clk_ctrl,
+	 VIDEO_BASE_L_D0_ena_ctrl, VIDEO_BASE_L_D0_clk_ctrl,
+	 DDR_REFRESH_SIG0_ena_ctrl, DDR_REFRESH_SIG0_clk_ctrl,
+	 DDR_REFRESH_CNT0_clk_ctrl, VIDEO_ADR_CNT0_ena_ctrl,
+	 VIDEO_ADR_CNT0_clk_ctrl, DDR_SM_0_clk_ctrl, BA_P0_clk_ctrl,
+	 VA_P0_clk_ctrl, BA_S0_clk_ctrl, VA_S0_clk_ctrl, MCS0_clk_ctrl,
+	 SR_VDMP0_clk_ctrl, FB_REGDDR_0_clk_ctrl;
+   reg [2:0] FB_REGDDR__d;
+   reg [2:0] FB_REGDDR__q;
+   reg [5:0] DDR_SM__d;
+   reg [5:0] DDR_SM__q;
+   reg VCAS, VRAS, VWE;
+   reg [12:0] VA_P_d;
+   reg [12:0] VA_P_q;
+   reg [1:0] BA_P_d;
+   reg [1:0] BA_P_q;
+   reg [12:0] VA_S_d;
+   reg [12:0] VA_S_q;
+   reg [1:0] BA_S_d;
+   reg [1:0] BA_S_q;
+   reg [1:0] MCS_q;
+   reg CPU_DDR_SYNC_q, DDR_CS_q, SR_DDR_WR_d, SR_DDR_WR_q, SR_DDRWR_D_SEL_d,
+	 SR_DDRWR_D_SEL_q;
+   reg [7:0] SR_VDMP_d;
+   reg [7:0] SR_VDMP_q;
+   reg CPU_REQ_q, CPU_AC_d, CPU_AC_q, BUS_CYC_q, BUS_CYC_END, BLITTER_REQ_q,
+	 BLITTER_AC_d, BLITTER_AC_q, FIFO_REQ_q, FIFO_AC_d, FIFO_AC_q,
+	 CLR_FIFO_SYNC_q, CLEAR_FIFO_CNT_q, STOP_q, SR_FIFO_WRE_d,
+	 SR_FIFO_WRE_q, FIFO_BANK_OK_q, FIFO_BANK_NOT_OK;
+   reg [10:0] DDR_REFRESH_CNT_q;
+   reg DDR_REFRESH_REQ_q;
+   reg [3:0] DDR_REFRESH_SIG_q;
+   reg REFRESH_TIME_q;
+   reg [7:0] VIDEO_BASE_L_D_q;
+   reg [7:0] VIDEO_BASE_M_D_q;
+   reg [7:0] VIDEO_BASE_H_D_q;
+   reg [2:0] VIDEO_BASE_X_D_q;
+   reg [22:0] VIDEO_ADR_CNT_q;
+   reg FIFO_BANK_OK_d_1, BUS_CYC_d_2, BA0_2, BA1_2, VA0_2, VA1_2, VA2_2, VA3_2,
+	 VA4_2, VA5_2, VA6_2, VA7_2, VA8_2, VA9_2, VA10_2, VA11_2, VA12_2;
+
+
+// Sub Module Section
+   lpm_bustri_BYT  u0 (.data(u0_data), .enabledt(u0_enabledt),
+	 .tridata(u0_tridata));
+
+   lpm_bustri_BYT  u1 (.data(u1_data), .enabledt(u1_enabledt),
+	 .tridata(u1_tridata));
+
+
+   assign SR_FIFO_WRE = SR_FIFO_WRE_q;
+   always @(posedge SR_FIFO_WRE_clk)
+      SR_FIFO_WRE_q <= SR_FIFO_WRE_d;
+
+   assign SR_DDR_WR = SR_DDR_WR_q;
+   always @(posedge SR_DDR_WR_clk)
+      SR_DDR_WR_q <= SR_DDR_WR_d;
+
+   assign SR_DDRWR_D_SEL = SR_DDRWR_D_SEL_q;
+   always @(posedge SR_DDRWR_D_SEL_clk)
+      SR_DDRWR_D_SEL_q <= SR_DDRWR_D_SEL_d;
+
+   assign SR_VDMP = SR_VDMP_q;
+   always @(posedge SR_VDMP0_clk_ctrl)
+      SR_VDMP_q <= SR_VDMP_d;
+
+   always @(posedge FB_REGDDR_0_clk_ctrl)
+      FB_REGDDR__q <= FB_REGDDR__d;
+
+   always @(posedge DDR_SM_0_clk_ctrl)
+      DDR_SM__q <= DDR_SM__d;
+
+   always @(posedge VA_P0_clk_ctrl)
+      VA_P_q <= VA_P_d;
+
+   always @(posedge BA_P0_clk_ctrl)
+      BA_P_q <= BA_P_d;
+
+   always @(posedge VA_S0_clk_ctrl)
+      VA_S_q <= VA_S_d;
+
+   always @(posedge BA_S0_clk_ctrl)
+      BA_S_q <= BA_S_d;
+
+   always @(posedge MCS0_clk_ctrl)
+      MCS_q <= MCS_d;
+
+   always @(posedge CPU_DDR_SYNC_clk)
+      CPU_DDR_SYNC_q <= CPU_DDR_SYNC_d;
+
+   always @(posedge DDR_CS_clk)
+      if (DDR_CS_ena)
+	 DDR_CS_q <= DDR_CS_d;
+
+   always @(posedge CPU_REQ_clk)
+      CPU_REQ_q <= CPU_REQ_d;
+
+   always @(posedge CPU_AC_clk)
+      CPU_AC_q <= CPU_AC_d;
+
+   always @(posedge BUS_CYC_clk)
+      BUS_CYC_q <= BUS_CYC_d;
+
+   always @(posedge BLITTER_REQ_clk)
+      BLITTER_REQ_q <= BLITTER_REQ_d;
+
+   always @(posedge BLITTER_AC_clk)
+      BLITTER_AC_q <= BLITTER_AC_d;
+
+   always @(posedge FIFO_REQ_clk)
+      FIFO_REQ_q <= FIFO_REQ_d;
+
+   always @(posedge FIFO_AC_clk)
+      FIFO_AC_q <= FIFO_AC_d;
+
+   always @(posedge CLR_FIFO_SYNC_clk)
+      CLR_FIFO_SYNC_q <= CLR_FIFO_SYNC_d;
+
+   always @(posedge CLEAR_FIFO_CNT_clk)
+      CLEAR_FIFO_CNT_q <= CLEAR_FIFO_CNT_d;
+
+   always @(posedge STOP_clk)
+      STOP_q <= STOP_d;
+
+   always @(posedge FIFO_BANK_OK_clk)
+      FIFO_BANK_OK_q <= FIFO_BANK_OK_d;
+
+   always @(posedge DDR_REFRESH_CNT0_clk_ctrl)
+      DDR_REFRESH_CNT_q <= DDR_REFRESH_CNT_d;
+
+   always @(posedge DDR_REFRESH_REQ_clk)
+      DDR_REFRESH_REQ_q <= DDR_REFRESH_REQ_d;
+
+   always @(posedge DDR_REFRESH_SIG0_clk_ctrl)
+      if (DDR_REFRESH_SIG0_ena_ctrl)
+	 DDR_REFRESH_SIG_q <= DDR_REFRESH_SIG_d;
+
+   always @(posedge REFRESH_TIME_clk)
+      REFRESH_TIME_q <= REFRESH_TIME_d;
+
+   always @(posedge VIDEO_BASE_L_D0_clk_ctrl)
+      if (VIDEO_BASE_L_D0_ena_ctrl)
+	 VIDEO_BASE_L_D_q <= VIDEO_BASE_L_D_d;
+
+   always @(posedge VIDEO_BASE_M_D0_clk_ctrl)
+      if (VIDEO_BASE_M_D0_ena_ctrl)
+	 VIDEO_BASE_M_D_q <= VIDEO_BASE_M_D_d;
+
+   always @(posedge VIDEO_BASE_H_D0_clk_ctrl)
+      if (VIDEO_BASE_H_D0_ena_ctrl)
+	 VIDEO_BASE_H_D_q <= VIDEO_BASE_H_D_d;
+
+   always @(posedge VIDEO_BASE_X_D0_clk_ctrl)
+      if (VIDEO_BASE_X_D0_ena_ctrl)
+	 VIDEO_BASE_X_D_q <= VIDEO_BASE_X_D_d;
+
+   always @(posedge VIDEO_ADR_CNT0_clk_ctrl)
+      if (VIDEO_ADR_CNT0_ena_ctrl)
+	 VIDEO_ADR_CNT_q <= VIDEO_ADR_CNT_d;
+
+// Start of original equations
+   assign LINE = FB_SIZE0 & FB_SIZE1;
+
+//  BYT SELECT
+//  ADR==0
+//  LONG UND LINE
+   assign FB_B[0] = FB_ADR[1:0] == 2'b00 | (FB_SIZE1 & FB_SIZE0) | ((!FB_SIZE1)
+	 & (!FB_SIZE0));
+
+//  ADR==1
+//  HIGH WORD
+//  LONG UND LINE
+   assign FB_B[1] = FB_ADR[1:0] == 2'b01 | (FB_SIZE1 & (!FB_SIZE0) &
+	 (!FB_ADR[1])) | (FB_SIZE1 & FB_SIZE0) | ((!FB_SIZE1) & (!FB_SIZE0));
+
+//  ADR==2
+//  LONG UND LINE
+   assign FB_B[2] = FB_ADR[1:0] == 2'b10 | (FB_SIZE1 & FB_SIZE0) | ((!FB_SIZE1)
+	 & (!FB_SIZE0));
+
+//  ADR==3
+//  LOW WORD
+//  LONG UND LINE
+   assign FB_B[3] = FB_ADR[1:0] == 2'b11 | (FB_SIZE1 & (!FB_SIZE0) & FB_ADR[1])
+	 | (FB_SIZE1 & FB_SIZE0) | ((!FB_SIZE1) & (!FB_SIZE0));
+
+//  CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR)  --------------------------------------------------
+   assign FB_REGDDR_0_clk_ctrl = MAIN_CLK;
+
+
+   always @(FB_REGDDR__q or DDR_SEL or BUS_CYC_q or LINE or DDR_CS_q or nFB_OE
+	 or MAIN_CLK or DDR_CONFIG or nFB_WR or vcc) begin
+      FB_REGDDR__d = FB_REGDDR__q;
+      {FB_VDOE[0], FB_VDOE[1]} = 2'b00;
+      {FB_LE[0], FB_LE[1], FB_VDOE[2], FB_LE[2], FB_VDOE[3], FB_LE[3],
+	    VIDEO_DDR_TA, BUS_CYC_END} = 8'b0000_0000;
+      casex (FB_REGDDR__q)
+      3'b000: begin
+	    FB_LE[0] = !nFB_WR;
+
+//  LOS WENN BEREIT ODER IMMER BEI LINE WRITE
+	    if (BUS_CYC_q | (DDR_SEL & LINE & (!nFB_WR))) begin
+	       FB_REGDDR__d = 3'b001;
+	    end else begin
+	       FB_REGDDR__d = 3'b000;
+	    end
+	 end
+      3'b001: begin
+	    if (DDR_CS_q) begin
+	       FB_LE[0] = !nFB_WR;
+	       VIDEO_DDR_TA = vcc;
+	       if (LINE) begin
+		  FB_VDOE[0] = (!nFB_OE) & (!DDR_CONFIG);
+		  FB_REGDDR__d = 3'b010;
+	       end else begin
+		  BUS_CYC_END = vcc;
+		  FB_VDOE[0] = (!nFB_OE) & (!MAIN_CLK) & (!DDR_CONFIG);
+		  FB_REGDDR__d = 3'b000;
+	       end
+	    end else begin
+	       FB_REGDDR__d = 3'b000;
+	    end
+	 end
+      3'b010: begin
+	    if (DDR_CS_q) begin
+	       FB_VDOE[1] = (!nFB_OE) & (!DDR_CONFIG);
+	       FB_LE[1] = !nFB_WR;
+	       VIDEO_DDR_TA = vcc;
+	       FB_REGDDR__d = 3'b011;
+	    end else begin
+	       FB_REGDDR__d = 3'b000;
+	    end
+	 end
+      3'b011: begin
+	    if (DDR_CS_q) begin
+	       FB_VDOE[2] = (!nFB_OE) & (!DDR_CONFIG);
+	       FB_LE[2] = !nFB_WR;
+
+//  BEI LINE WRITE EVT. WARTEN
+	       if ((!BUS_CYC_q) & LINE & (!nFB_WR)) begin
+		  FB_REGDDR__d = 3'b011;
+	       end else begin
+		  VIDEO_DDR_TA = vcc;
+		  FB_REGDDR__d = 3'b100;
+	       end
+	    end else begin
+	       FB_REGDDR__d = 3'b000;
+	    end
+	 end
+      3'b100: begin
+	    if (DDR_CS_q) begin
+	       FB_VDOE[3] = (!nFB_OE) & (!MAIN_CLK) & (!DDR_CONFIG);
+	       FB_LE[3] = !nFB_WR;
+	       VIDEO_DDR_TA = vcc;
+	       BUS_CYC_END = vcc;
+	       FB_REGDDR__d = 3'b000;
+	    end else begin
+	       FB_REGDDR__d = 3'b000;
+	    end
+	 end
+      endcase
+   end
+
+//  DDR STEUERUNG -----------------------------------------------------
+//  VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE;
+   assign VCKE = VIDEO_RAM_CTR[0];
+   assign nVCS = !VIDEO_RAM_CTR[1];
+   assign DDR_REFRESH_ON = VIDEO_RAM_CTR[2];
+   assign DDR_CONFIG = VIDEO_RAM_CTR[3];
+   assign FIFO_ACTIVE = VIDEO_RAM_CTR[8];
+
+// ------------------------------
+   assign CPU_ROW_ADR = FB_ADR[26:14];
+   assign CPU_BA = FB_ADR[13:12];
+   assign CPU_COL_ADR = FB_ADR[11:2];
+   assign nVRAS = !VRAS;
+   assign nVCAS = !VCAS;
+   assign nVWE = !VWE;
+   assign SR_DDR_WR_clk = DDRCLK0;
+   assign SR_DDRWR_D_SEL_clk = DDRCLK0;
+   assign SR_VDMP0_clk_ctrl = DDRCLK0;
+   assign SR_FIFO_WRE_clk = DDRCLK0;
+   assign CPU_AC_clk = DDRCLK0;
+   assign FIFO_AC_clk = DDRCLK0;
+   assign BLITTER_AC_clk = DDRCLK0;
+   assign DDRWR_D_SEL1 = BLITTER_AC_q;
+
+//  SELECT LOGIC
+   assign DDR_SEL = FB_ALE & FB_AD[31:30] == 2'b01;
+   assign DDR_CS_clk = MAIN_CLK;
+   assign DDR_CS_ena = FB_ALE;
+   assign DDR_CS_d = DDR_SEL;
+
+//  WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER
+//  NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
+//  CONFIG SOFORT LOS
+//  LINE WRITE SPÄTER
+   assign CPU_SIG = (DDR_SEL & (nFB_WR | (!LINE)) & (!DDR_CONFIG)) | (DDR_SEL &
+	 DDR_CONFIG) | (FB_REGDDR__q == 3'b010 & (!nFB_WR));
+   assign CPU_REQ_clk = DDR_SYNC_66M;
+
+//  HALTEN BUS CYC BEGONNEN ODER FERTIG
+   assign CPU_REQ_d = CPU_SIG | (CPU_REQ_q & FB_REGDDR__q != 3'b010 &
+	 FB_REGDDR__q != 3'b100 & (!BUS_CYC_END) & (!BUS_CYC_q));
+   assign BUS_CYC_clk = DDRCLK0;
+   assign BUS_CYC_d_1 = BUS_CYC_q & (!BUS_CYC_END);
+
+//  STATE MACHINE SYNCHRONISIEREN -----------------
+   assign MCS0_clk_ctrl = DDRCLK0;
+   assign MCS_d[0] = MAIN_CLK;
+   assign MCS_d[1] = MCS_q[0];
+   assign CPU_DDR_SYNC_clk = DDRCLK0;
+
+//  NUR 1 WENN EIN
+   assign CPU_DDR_SYNC_d = MCS_q == 2'b10 & VCKE & (!nVCS);
+
+// -------------------------------------------------
+   assign VA_S0_clk_ctrl = DDRCLK0;
+   assign BA_S0_clk_ctrl = DDRCLK0;
+   assign {VA12_1, VA11_1, VA10_1, VA9_1, VA8_1, VA7_1, VA6_1, VA5_1, VA4_1,
+	 VA3_1, VA2_1, VA1_1, VA0_1} = VA_S_q;
+   assign {BA1_1, BA0_1} = BA_S_q;
+   assign VA_P0_clk_ctrl = DDRCLK0;
+   assign BA_P0_clk_ctrl = DDRCLK0;
+
+//  DDR STATE MACHINE  -----------------------------------------------
+   assign DDR_SM_0_clk_ctrl = DDRCLK0;
+
+
+   always @(DDR_SM__q or DDR_REFRESH_REQ_q or CPU_DDR_SYNC_q or DDR_CONFIG or
+	 CPU_ROW_ADR or FIFO_ROW_ADR or BLITTER_ROW_ADR or BLITTER_REQ_q or
+	 BLITTER_WR or FIFO_AC_q or CPU_COL_ADR or BLITTER_COL_ADR or VA_S_q or
+	 CPU_BA or BLITTER_BA or FB_B or CPU_AC_q or BLITTER_AC_q or
+	 FIFO_BANK_OK_q or FIFO_MW or FIFO_REQ_q or VIDEO_ADR_CNT_q or
+	 FIFO_COL_ADR or gnd or DDR_SEL or LINE or FIFO_BA or FB_AD or VA_P_q
+	 or BA_P_q or CPU_REQ_q or nFB_WR or FB_SIZE0 or FB_SIZE1 or
+	 DDR_REFRESH_SIG_q or vcc) begin
+      DDR_SM__d = DDR_SM__q;
+      BA_S_d = 2'b00;
+      VA_S_d = 13'b0_0000_0000_0000;
+      BA_P_d = 2'b00;
+      {VA_P_d[9], VA_P_d[8], VA_P_d[7], VA_P_d[6], VA_P_d[5], VA_P_d[4],
+	    VA_P_d[3], VA_P_d[2], VA_P_d[1], VA_P_d[0], VA_P_d[10]} =
+	    11'b000_0000_0000;
+      SR_VDMP_d = 8'b0000_0000;
+      VA_P_d[12:11] = 2'b00;
+      {FIFO_BANK_OK_d_1, FIFO_AC_d, SR_DDR_FB, SR_BLITTER_DACK, BLITTER_AC_d,
+	    SR_DDR_WR_d, SR_DDRWR_D_SEL_d, CPU_AC_d, VA12_2, VA11_2, VA9_2,
+	    VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2,
+	    BA1_2, BA0_2, SR_FIFO_WRE_d, BUS_CYC_d_2, VWE, VA10_2,
+	    FIFO_BANK_NOT_OK, VCAS, VRAS} =
+	    29'b0_0000_0000_0000_0000_0000_0000_0000;
+      casex (DDR_SM__q)
+      6'b00_0000: begin
+	    if (DDR_REFRESH_REQ_q) begin
+	       DDR_SM__d = 6'b01_1111;
+
+//  SYNCHRON UND EIN?
+	    end else if (CPU_DDR_SYNC_q) begin
+
+//  JA
+	       if (DDR_CONFIG) begin
+		  DDR_SM__d = 6'b00_1000;
+
+//  BEI WAIT UND LINE WRITE
+	       end else if (CPU_REQ_q) begin
+		  VA_S_d = CPU_ROW_ADR;
+		  BA_S_d = CPU_BA;
+		  CPU_AC_d = vcc;
+		  BUS_CYC_d_2 = vcc;
+		  DDR_SM__d = 6'b00_0010;
+	       end else begin
+
+//  FIFO IST DEFAULT
+		  if (FIFO_REQ_q | (!BLITTER_REQ_q)) begin
+		     VA_P_d = FIFO_ROW_ADR;
+		     BA_P_d = FIFO_BA;
+
+//  VORBESETZEN
+		     FIFO_AC_d = vcc;
+		  end else begin
+		     VA_P_d = BLITTER_ROW_ADR;
+		     BA_P_d = BLITTER_BA;
+
+//  VORBESETZEN
+		     BLITTER_AC_d = vcc;
+		  end
+		  DDR_SM__d = 6'b00_0001;
+	       end
+	    end else begin
+
+//  NEIN ->SYNCHRONISIEREN
+	       DDR_SM__d = 6'b00_0000;
+	    end
+	 end
+      6'b00_0001: begin
+
+//  SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK ***
+	    if (DDR_SEL & (nFB_WR | (!LINE))) begin
+	       VRAS = vcc;
+	       {VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2,
+		     VA4_2, VA3_2, VA2_2, VA1_2, VA0_2} = FB_AD[26:14];
+	       {BA1_2, BA0_2} = FB_AD[13:12];
+
+//  AUTO PRECHARGE DA NICHT FIFO PAGE
+	       VA_S_d[10] = vcc;
+	       CPU_AC_d = vcc;
+
+//  BUS CYCLUS LOSTRETEN
+	       BUS_CYC_d_2 = vcc;
+	    end else begin
+	       VRAS = (FIFO_AC_q & FIFO_REQ_q) | (BLITTER_AC_q &
+		     BLITTER_REQ_q);
+	       {VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2,
+		     VA4_2, VA3_2, VA2_2, VA1_2, VA0_2} = VA_P_q;
+	       {BA1_2, BA0_2} = BA_P_q;
+	       VA_S_d[10] = !(FIFO_AC_q & FIFO_REQ_q);
+	       FIFO_BANK_OK_d_1 = FIFO_AC_q & FIFO_REQ_q;
+	       FIFO_AC_d = FIFO_AC_q & FIFO_REQ_q;
+	       BLITTER_AC_d = BLITTER_AC_q & BLITTER_REQ_q;
+	    end
+	    DDR_SM__d = 6'b00_0011;
+	 end
+      6'b00_0010: begin
+	    VRAS = vcc;
+	    FIFO_BANK_NOT_OK = vcc;
+	    CPU_AC_d = vcc;
+
+//  BUS CYCLUS LOSTRETEN
+	    BUS_CYC_d_2 = vcc;
+	    DDR_SM__d = 6'b00_0011;
+	 end
+      6'b00_0011: begin
+	    CPU_AC_d = CPU_AC_q;
+	    FIFO_AC_d = FIFO_AC_q;
+	    BLITTER_AC_d = BLITTER_AC_q;
+
+//  AUTO PRECHARGE WENN NICHT FIFO PAGE
+	    VA_S_d[10] = VA_S_q[10];
+	    if (((!nFB_WR) & CPU_AC_q) | (BLITTER_WR & BLITTER_AC_q)) begin
+	       DDR_SM__d = 6'b01_0000;
+
+//  CPU?
+	    end else if (CPU_AC_q) begin
+	       VA_S_d[9:0] = CPU_COL_ADR;
+	       BA_S_d = CPU_BA;
+	       DDR_SM__d = 6'b00_1110;
+
+//  FIFO?
+	    end else if (FIFO_AC_q) begin
+	       VA_S_d[9:0] = FIFO_COL_ADR;
+	       BA_S_d = FIFO_BA;
+	       DDR_SM__d = 6'b01_0110;
+	    end else if (BLITTER_AC_q) begin
+	       VA_S_d[9:0] = BLITTER_COL_ADR;
+	       BA_S_d = BLITTER_BA;
+	       DDR_SM__d = 6'b00_1110;
+	    end else begin
+
+//  READ
+	       DDR_SM__d = 6'b00_0111;
+	    end
+	 end
+      6'b00_1110: begin
+	    CPU_AC_d = CPU_AC_q;
+	    BLITTER_AC_d = BLITTER_AC_q;
+	    VCAS = vcc;
+
+//  READ DATEN FÜR CPU
+	    SR_DDR_FB = CPU_AC_q;
+
+//  BLITTER DACK AND BLITTER LATCH DATEN
+	    SR_BLITTER_DACK = BLITTER_AC_q;
+	    DDR_SM__d = 6'b00_1111;
+	 end
+      6'b00_1111: begin
+	    CPU_AC_d = CPU_AC_q;
+	    BLITTER_AC_d = BLITTER_AC_q;
+
+//  FIFO READ EINSCHIEBEN WENN BANK OK
+	    if (FIFO_REQ_q & FIFO_BANK_OK_q) begin
+	       VA_S_d[9:0] = FIFO_COL_ADR;
+
+//  MANUEL PRECHARGE
+	       VA_S_d[10] = gnd;
+	       BA_S_d = FIFO_BA;
+	       DDR_SM__d = 6'b01_1000;
+	    end else begin
+
+//  ALLE PAGES SCHLIESSEN
+	       VA_S_d[10] = vcc;
+
+//  WRITE
+	       DDR_SM__d = 6'b01_1101;
+	    end
+	 end
+      6'b01_0000: begin
+	    CPU_AC_d = CPU_AC_q;
+	    BLITTER_AC_d = BLITTER_AC_q;
+
+//  BLITTER ACK AND BLITTER LATCH DATEN
+	    SR_BLITTER_DACK = BLITTER_AC_q;
+
+//  AUTO PRECHARGE WENN NICHT FIFO PAGE
+	    VA_S_d[10] = VA_S_q[10];
+	    DDR_SM__d = 6'b01_0001;
+	 end
+      6'b01_0001: begin
+	    CPU_AC_d = CPU_AC_q;
+	    BLITTER_AC_d = BLITTER_AC_q;
+	    VA_S_d[9:0] = ({10{CPU_AC_q}} & CPU_COL_ADR) | ({10{BLITTER_AC_q}}
+		  & BLITTER_COL_ADR);
+
+//  AUTO PRECHARGE WENN NICHT FIFO PAGE
+	    VA_S_d[10] = VA_S_q[10];
+	    BA_S_d = ({2{CPU_AC_q}} & CPU_BA) | ({2{BLITTER_AC_q}} &
+		  BLITTER_BA);
+
+//  BYTE ENABLE WRITE
+	    SR_VDMP_d[7:4] = FB_B;
+
+//  LINE ENABLE WRITE
+	    SR_VDMP_d[3:0] = {4{LINE}} & 4'b1111;
+	    DDR_SM__d = 6'b01_0010;
+	 end
+      6'b01_0010: begin
+	    CPU_AC_d = CPU_AC_q;
+	    BLITTER_AC_d = BLITTER_AC_q;
+	    VCAS = vcc;
+	    VWE = vcc;
+
+//  WRITE COMMAND CPU UND BLITTER IF WRITER
+	    SR_DDR_WR_d = vcc;
+
+//  2. HÄLFTE WRITE DATEN SELEKTIEREN
+	    SR_DDRWR_D_SEL_d = vcc;
+
+//  WENN LINE DANN ACTIV
+	    SR_VDMP_d = {8{LINE}} & 8'b1111_1111;
+	    DDR_SM__d = 6'b01_0011;
+	 end
+      6'b01_0011: begin
+	    CPU_AC_d = CPU_AC_q;
+	    BLITTER_AC_d = BLITTER_AC_q;
+
+//  WRITE COMMAND CPU UND BLITTER IF WRITE
+	    SR_DDR_WR_d = vcc;
+
+//  2. HÄLFTE WRITE DATEN SELEKTIEREN
+	    SR_DDRWR_D_SEL_d = vcc;
+	    DDR_SM__d = 6'b01_0100;
+	 end
+      6'b01_0100: begin
+	    DDR_SM__d = 6'b01_0101;
+	 end
+      6'b01_0101: begin
+	    if (FIFO_REQ_q & FIFO_BANK_OK_q) begin
+	       VA_S_d[9:0] = FIFO_COL_ADR;
+
+//  NON AUTO PRECHARGE
+	       VA_S_d[10] = gnd;
+	       BA_S_d = FIFO_BA;
+	       DDR_SM__d = 6'b01_1000;
+	    end else begin
+
+//  ALLE PAGES SCHLIESSEN
+	       VA_S_d[10] = vcc;
+
+//  FIFO READ
+	       DDR_SM__d = 6'b01_1101;
+	    end
+	 end
+      6'b01_0110: begin
+	    VCAS = vcc;
+
+//  DATEN WRITE FIFO
+	    SR_FIFO_WRE_d = vcc;
+	    DDR_SM__d = 6'b01_0111;
+	 end
+      6'b01_0111: begin
+	    if (FIFO_REQ_q) begin
+
+//  NEUE PAGE?
+	       if (VIDEO_ADR_CNT_q[7:0] == 8'b1111_1111) begin
+
+//  ALLE PAGES SCHLIESSEN
+		  VA_S_d[10] = vcc;
+
+//  BANK SCHLIESSEN
+		  DDR_SM__d = 6'b01_1101;
+	       end else begin
+		  VA_S_d[9:0] = FIFO_COL_ADR + 10'b00_0000_0100;
+
+//  NON AUTO PRECHARGE
+		  VA_S_d[10] = gnd;
+		  BA_S_d = FIFO_BA;
+		  DDR_SM__d = 6'b01_1000;
+	       end
+	    end else begin
+
+//  ALLE PAGES SCHLIESSEN
+	       VA_S_d[10] = vcc;
+
+//  NOCH OFFEN LASSEN
+	       DDR_SM__d = 6'b01_1101;
+	    end
+	 end
+      6'b01_1000: begin
+	    VCAS = vcc;
+
+//  DATEN WRITE FIFO
+	    SR_FIFO_WRE_d = vcc;
+	    DDR_SM__d = 6'b01_1001;
+	 end
+      6'b01_1001: begin
+	    if (CPU_REQ_q & FIFO_MW > 9'b0_0000_0000) begin
+
+//  ALLE PAGES SCHLIESEN
+	       VA_S_d[10] = vcc;
+
+//  BANK SCHLIESSEN
+	       DDR_SM__d = 6'b01_1110;
+	    end else if (FIFO_REQ_q) begin
+
+//  NEUE PAGE?
+	       if (VIDEO_ADR_CNT_q[7:0] == 8'b1111_1111) begin
+
+//  ALLE PAGES SCHLIESSEN
+		  VA_S_d[10] = vcc;
+
+//  BANK SCHLIESSEN
+		  DDR_SM__d = 6'b01_1110;
+	       end else begin
+		  VA_S_d[9:0] = FIFO_COL_ADR + 10'b00_0000_0100;
+
+//  NON AUTO PRECHARGE
+		  VA_S_d[10] = gnd;
+		  BA_S_d = FIFO_BA;
+		  DDR_SM__d = 6'b01_1010;
+	       end
+	    end else begin
+
+//  ALLE PAGES SCHLIESEN
+	       VA_S_d[10] = vcc;
+
+//  BANK SCHLIESSEN
+	       DDR_SM__d = 6'b01_1110;
+	    end
+	 end
+      6'b01_1010: begin
+	    VCAS = vcc;
+
+//  DATEN WRITE FIFO
+	    SR_FIFO_WRE_d = vcc;
+
+//  NOTFALL?
+	    if (FIFO_MW < 9'b0_0000_0000) begin
+
+//  JA->
+	       DDR_SM__d = 6'b01_0111;
+	    end else begin
+	       DDR_SM__d = 6'b01_1011;
+	    end
+	 end
+      6'b01_1011: begin
+	    if (FIFO_REQ_q) begin
+
+//  NEUE PAGE?
+	       if (VIDEO_ADR_CNT_q[7:0] == 8'b1111_1111) begin
+
+//  ALLE BANKS SCHLIESEN
+		  VA_S_d[10] = vcc;
+
+//  BANK SCHLIESSEN
+		  DDR_SM__d = 6'b01_1101;
+	       end else begin
+		  VA_P_d[9:0] = FIFO_COL_ADR + 10'b00_0000_0100;
+
+//  NON AUTO PRECHARGE
+		  VA_P_d[10] = gnd;
+		  BA_P_d = FIFO_BA;
+		  DDR_SM__d = 6'b01_1100;
+	       end
+	    end else begin
+
+//  ALLE BANKS SCHLIESEN
+	       VA_S_d[10] = vcc;
+
+//  BANK SCHLIESSEN
+	       DDR_SM__d = 6'b01_1101;
+	    end
+	 end
+      6'b01_1100: begin
+	    if (DDR_SEL & (nFB_WR | (!LINE)) & FB_AD[13:12] != FIFO_BA) begin
+	       VRAS = vcc;
+	       {VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2,
+		     VA4_2, VA3_2, VA2_2, VA1_2, VA0_2} = FB_AD[26:14];
+	       {BA1_2, BA0_2} = FB_AD[13:12];
+	       CPU_AC_d = vcc;
+
+//  BUS CYCLUS LOSTRETEN
+	       BUS_CYC_d_2 = vcc;
+
+//  AUTO PRECHARGE DA NICHT FIFO BANK
+	       VA_S_d[10] = vcc;
+	       DDR_SM__d = 6'b00_0011;
+	    end else begin
+	       VCAS = vcc;
+	       {VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2,
+		     VA4_2, VA3_2, VA2_2, VA1_2, VA0_2} = VA_P_q;
+	       {BA1_2, BA0_2} = BA_P_q;
+
+//  DATEN WRITE FIFO
+	       SR_FIFO_WRE_d = vcc;
+
+//  CONFIG CYCLUS
+	       DDR_SM__d = 6'b01_1001;
+	    end
+	 end
+      6'b00_1000: begin
+	    DDR_SM__d = 6'b00_1001;
+	 end
+      6'b00_1001: begin
+	    BUS_CYC_d_2 = CPU_REQ_q;
+	    DDR_SM__d = 6'b00_1010;
+	 end
+      6'b00_1010: begin
+	    if (CPU_REQ_q) begin
+	       DDR_SM__d = 6'b00_1011;
+	    end else begin
+	       DDR_SM__d = 6'b00_0000;
+	    end
+	 end
+      6'b00_1011: begin
+	    DDR_SM__d = 6'b00_1100;
+	 end
+      6'b00_1100: begin
+	    VA_S_d = FB_AD[12:0];
+	    BA_S_d = FB_AD[14:13];
+	    DDR_SM__d = 6'b00_1101;
+	 end
+      6'b00_1101: begin
+
+//  NUR BEI LONG WRITE
+	    VRAS = FB_AD[18] & (!nFB_WR) & (!FB_SIZE0) & (!FB_SIZE1);
+
+//  NUR BEI LONG WRITE
+	    VCAS = FB_AD[17] & (!nFB_WR) & (!FB_SIZE0) & (!FB_SIZE1);
+
+//  NUR BEI LONG WRITE
+	    VWE = FB_AD[16] & (!nFB_WR) & (!FB_SIZE0) & (!FB_SIZE1);
+
+//  CLOSE FIFO BANK
+	    DDR_SM__d = 6'b00_0111;
+	 end
+      6'b01_1101: begin
+
+//  AUF NOT OK
+	    FIFO_BANK_NOT_OK = vcc;
+
+//  BÄNKE SCHLIESSEN
+	    VRAS = vcc;
+	    VWE = vcc;
+	    DDR_SM__d = 6'b00_0110;
+	 end
+      6'b01_1110: begin
+
+//  AUF NOT OK
+	    FIFO_BANK_NOT_OK = vcc;
+
+//  BÄNKE SCHLIESSEN
+	    VRAS = vcc;
+	    VWE = vcc;
+
+//  REFRESH 70NS = 10 ZYCLEN
+	    DDR_SM__d = 6'b00_0000;
+	 end
+      6'b01_1111: begin
+
+//  EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
+	    if (DDR_REFRESH_SIG_q == 4'b1001) begin
+
+//  ALLE BANKS SCHLIESSEN
+	       VRAS = vcc;
+	       VWE = vcc;
+	       VA10_2 = vcc;
+	       FIFO_BANK_NOT_OK = vcc;
+	       DDR_SM__d = 6'b10_0001;
+	    end else begin
+	       VCAS = vcc;
+	       VRAS = vcc;
+	       DDR_SM__d = 6'b10_0000;
+	    end
+	 end
+      6'b10_0000: begin
+	    DDR_SM__d = 6'b10_0001;
+	 end
+      6'b10_0001: begin
+	    DDR_SM__d = 6'b10_0010;
+	 end
+      6'b10_0010: begin
+	    DDR_SM__d = 6'b10_0011;
+	 end
+      6'b10_0011: begin
+
+//  LEERSCHLAUFE
+	    DDR_SM__d = 6'b00_0100;
+	 end
+      6'b00_0100: begin
+	    DDR_SM__d = 6'b00_0101;
+	 end
+      6'b00_0101: begin
+	    DDR_SM__d = 6'b00_0110;
+	 end
+      6'b00_0110: begin
+	    DDR_SM__d = 6'b00_0111;
+	 end
+      6'b00_0111: begin
+	    DDR_SM__d = 6'b00_0000;
+	 end
+      endcase
+   end
+
+// -------------------------------------------------------------
+//  BLITTER ----------------------
+// ---------------------------------------
+   assign BLITTER_REQ_clk = DDRCLK0;
+   assign BLITTER_REQ_d = BLITTER_SIG & (!DDR_CONFIG) & VCKE & (!nVCS);
+   assign BLITTER_ROW_ADR = BLITTER_ADR[26:14];
+   assign BLITTER_BA[1] = BLITTER_ADR[13];
+   assign BLITTER_BA[0] = BLITTER_ADR[12];
+   assign BLITTER_COL_ADR = BLITTER_ADR[11:2];
+
+// ----------------------------------------------------------------------------
+//  FIFO ---------------------------------
+// ------------------------------------------------------
+   assign FIFO_REQ_clk = DDRCLK0;
+   assign FIFO_REQ_d = (FIFO_MW < 9'b0_1100_1000 | (FIFO_MW < 9'b1_1111_0100 &
+	 FIFO_REQ_q)) & FIFO_ACTIVE & (!CLEAR_FIFO_CNT_q) & (!STOP_q) &
+	 (!DDR_CONFIG) & VCKE & (!nVCS);
+   assign FIFO_ROW_ADR = VIDEO_ADR_CNT_q[22:10];
+   assign FIFO_BA[1] = VIDEO_ADR_CNT_q[9];
+   assign FIFO_BA[0] = VIDEO_ADR_CNT_q[8];
+   assign FIFO_COL_ADR = {VIDEO_ADR_CNT_q[7], VIDEO_ADR_CNT_q[6],
+	 VIDEO_ADR_CNT_q[5], VIDEO_ADR_CNT_q[4], VIDEO_ADR_CNT_q[3],
+	 VIDEO_ADR_CNT_q[2], VIDEO_ADR_CNT_q[1], VIDEO_ADR_CNT_q[0], 2'b00};
+   assign FIFO_BANK_OK_clk = DDRCLK0;
+   assign FIFO_BANK_OK_d_2 = FIFO_BANK_OK_q & (!FIFO_BANK_NOT_OK);
+
+//  ZÄHLER RÜCKSETZEN WENN CLR FIFO ----------------
+   assign CLR_FIFO_SYNC_clk = DDRCLK0;
+
+//  SYNCHRONISIEREN
+   assign CLR_FIFO_SYNC_d = CLR_FIFO;
+   assign CLEAR_FIFO_CNT_clk = DDRCLK0;
+   assign CLEAR_FIFO_CNT_d = CLR_FIFO_SYNC_q | (!FIFO_ACTIVE);
+   assign STOP_clk = DDRCLK0;
+   assign STOP_d = CLR_FIFO_SYNC_q | CLEAR_FIFO_CNT_q;
+
+//  ZÄHLEN -----------------------------------------------
+   assign VIDEO_ADR_CNT0_clk_ctrl = DDRCLK0;
+   assign VIDEO_ADR_CNT0_ena_ctrl = SR_FIFO_WRE_q | CLEAR_FIFO_CNT_q;
+   assign VIDEO_ADR_CNT_d = ({23{CLEAR_FIFO_CNT_q}} & VIDEO_BASE_ADR) |
+	 ({23{!CLEAR_FIFO_CNT_q}} & (VIDEO_ADR_CNT_q + 23'h1));
+   assign VIDEO_BASE_ADR[22:20] = VIDEO_BASE_X_D_q;
+   assign VIDEO_BASE_ADR[19:12] = VIDEO_BASE_H_D_q;
+   assign VIDEO_BASE_ADR[11:4] = VIDEO_BASE_M_D_q;
+   assign VIDEO_BASE_ADR[3:0] = VIDEO_BASE_L_D_q[7:4];
+   assign VDM_SEL = VIDEO_BASE_L_D_q[3:0];
+
+//  AKTUELLE VIDEO ADRESSE
+   assign VIDEO_ACT_ADR[26:4] = VIDEO_ADR_CNT_q - {14'b00_0000_0000_0000,
+	 FIFO_MW};
+   assign VIDEO_ACT_ADR[3:0] = VDM_SEL;
+
+// ---------------------------------------------------------------------------------------
+//  REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
+// ---------------------------------------------------------------------------------------
+   assign DDR_REFRESH_CNT0_clk_ctrl = CLK33M;
+
+//  ZÄHLEN 0-2047
+   assign DDR_REFRESH_CNT_d = DDR_REFRESH_CNT_q + 11'b000_0000_0001;
+   assign REFRESH_TIME_clk = DDRCLK0;
+
+//  SYNC
+   assign REFRESH_TIME_d = DDR_REFRESH_CNT_q == 11'b000_0000_0000 &
+	 (!MAIN_CLK);
+   assign DDR_REFRESH_SIG0_clk_ctrl = DDRCLK0;
+   assign DDR_REFRESH_SIG0_ena_ctrl = REFRESH_TIME_q | DDR_SM__q == 6'b10_0011;
+
+//  9 STÜCK (8 REFRESH UND 1 ALS VORLAUF)
+//  MINUS 1 WENN GEMACHT
+   assign DDR_REFRESH_SIG_d = ({4{REFRESH_TIME_q}} & 4'b1001 &
+	 {4{DDR_REFRESH_ON}} & {4{!DDR_CONFIG}}) | ({4{!REFRESH_TIME_q}} &
+	 (DDR_REFRESH_SIG_q - 4'b0001) & {4{DDR_REFRESH_ON}} &
+	 {4{!DDR_CONFIG}});
+   assign DDR_REFRESH_REQ_clk = DDRCLK0;
+   assign DDR_REFRESH_REQ_d = DDR_REFRESH_SIG_q != 4'b0000 & DDR_REFRESH_ON &
+	 (!REFRESH_TIME_q) & (!DDR_CONFIG);
+
+// ---------------------------------------------------------
+//  VIDEO REGISTER -----------------------
+// -------------------------------------------------------------------------------------------------------------------
+   assign VIDEO_BASE_L_D0_clk_ctrl = MAIN_CLK;
+
+//  820D/2
+   assign VIDEO_BASE_L = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C106;
+
+//  SORRY, NUR 16 BYT GRENZEN
+   assign VIDEO_BASE_L_D_d = FB_AD[23:16];
+   assign VIDEO_BASE_L_D0_ena_ctrl = (!nFB_WR) & VIDEO_BASE_L & FB_B[1];
+   assign VIDEO_BASE_M_D0_clk_ctrl = MAIN_CLK;
+
+//  8203/2
+   assign VIDEO_BASE_M = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C101;
+   assign VIDEO_BASE_M_D_d = FB_AD[23:16];
+   assign VIDEO_BASE_M_D0_ena_ctrl = (!nFB_WR) & VIDEO_BASE_M & FB_B[3];
+   assign VIDEO_BASE_H_D0_clk_ctrl = MAIN_CLK;
+
+//  8200-1/2
+   assign VIDEO_BASE_H = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C100;
+   assign VIDEO_BASE_H_D_d = FB_AD[23:16];
+   assign VIDEO_BASE_H_D0_ena_ctrl = (!nFB_WR) & VIDEO_BASE_H & FB_B[1];
+   assign VIDEO_BASE_X_D0_clk_ctrl = MAIN_CLK;
+   assign VIDEO_BASE_X_D_d = FB_AD[26:24];
+   assign VIDEO_BASE_X_D0_ena_ctrl = (!nFB_WR) & VIDEO_BASE_H & FB_B[0];
+
+//  8209/2
+   assign VIDEO_CNT_L = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C104;
+
+//  8207/2
+   assign VIDEO_CNT_M = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C103;
+
+//  8204,5/2
+   assign VIDEO_CNT_H = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C102;
+
+//  GE
+   assign VIDEO_BASE_X_D_FULL = {5'b0_0000, VIDEO_BASE_X_D_q};
+   assign u0_data = ({8{VIDEO_BASE_H}} & VIDEO_BASE_X_D_FULL) |
+	 ({8{VIDEO_CNT_H}} & {5'b0_0000, VIDEO_ACT_ADR[26:24]});
+   assign u0_enabledt = (VIDEO_BASE_H | VIDEO_CNT_H) & (!nFB_OE);
+   assign FB_AD[31:24] = u0_tridata;
+   assign u1_data = ({8{VIDEO_BASE_L}} & VIDEO_BASE_L_D_q) | ({8{VIDEO_BASE_M}}
+	 & VIDEO_BASE_M_D_q) | ({8{VIDEO_BASE_H}} & VIDEO_BASE_H_D_q) |
+	 ({8{VIDEO_CNT_L}} & VIDEO_ACT_ADR[7:0]) | ({8{VIDEO_CNT_M}} &
+	 VIDEO_ACT_ADR[15:8]) | ({8{VIDEO_CNT_H}} & VIDEO_ACT_ADR[23:16]);
+   assign u1_enabledt = (VIDEO_BASE_L | VIDEO_BASE_M | VIDEO_BASE_H |
+	 VIDEO_CNT_L | VIDEO_CNT_M | VIDEO_CNT_H) & (!nFB_OE);
+   assign FB_AD[23:16] = u1_tridata;
+
+
+// Assignments added to explicitly combine the
+// effects of multiple drivers in the source
+   assign FIFO_BANK_OK_d = FIFO_BANK_OK_d_1 | FIFO_BANK_OK_d_2;
+   assign BUS_CYC_d = BUS_CYC_d_1 | BUS_CYC_d_2;
+   assign BA[0] = BA0_1 | BA0_2;
+   assign BA[1] = BA1_1 | BA1_2;
+   assign VA[0] = VA0_1 | VA0_2;
+   assign VA[1] = VA1_1 | VA1_2;
+   assign VA[2] = VA2_1 | VA2_2;
+   assign VA[3] = VA3_1 | VA3_2;
+   assign VA[4] = VA4_1 | VA4_2;
+   assign VA[5] = VA5_1 | VA5_2;
+   assign VA[6] = VA6_1 | VA6_2;
+   assign VA[7] = VA7_1 | VA7_2;
+   assign VA[8] = VA8_1 | VA8_2;
+   assign VA[9] = VA9_1 | VA9_2;
+   assign VA[10] = VA10_1 | VA10_2;
+   assign VA[11] = VA11_1 | VA11_2;
+   assign VA[12] = VA12_1 | VA12_2;
+
+// Define power signal(s)
+   assign vcc = 1'b1;
+   assign gnd = 1'b0;
+endmodule
diff --git a/FPGA_quartus_GE/Video/DDR_CTR_BLITTER.tdf.bak b/FPGA_quartus_GE/Video/DDR_CTR_BLITTER.tdf.bak
new file mode 100644
index 0000000..03052b4
--- /dev/null
+++ b/FPGA_quartus_GE/Video/DDR_CTR_BLITTER.tdf.bak
@@ -0,0 +1,352 @@
+TITLE "DDR_CTR_BLITTER";
+
+-- CREATED BY FREDI ASCHWANDEN
+
+INCLUDE "lpm_bustri_BYT.inc";
+
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+SUBDESIGN DDR_CTR_BLITTER
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	FB_ADR[31..0] : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	nFB_CS3 : INPUT;
+	nFB_OE : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	nRSTO : INPUT;
+	MAIN_CLK : INPUT;
+	FIFO_FULL : INPUT;
+	FB_ALE : INPUT;
+	nFB_WR : INPUT;
+	DDR_SYNC_66M : INPUT;
+	VSYNC : INPUT;
+	BLITTER_ON : INPUT;
+	VIDEO_RAM_CTR[15..0] : INPUT;
+	VDVZ[127..0] : INPUT;
+	DDRCLK[3..0] : INPUT;
+	BA0 : OUTPUT;
+	BA1 : OUTPUT;
+	VA[12..0] : OUTPUT;
+	nVWE : OUTPUT;
+	nVRAS : OUTPUT;
+	nVCS : OUTPUT;
+	VCKE : OUTPUT;
+	nVCAS : OUTPUT;
+	FIFO_WRE : OUTPUT;
+	FB_LE[3..0] : OUTPUT;
+	FB_VDOE[3..0] : OUTPUT;
+	START_CYC_RDWR : OUTPUT;
+	DDR_WR : OUTPUT;
+	CLEAR_FIFO_CNT : OUTPUT;
+	BLITTER_RUN : OUTPUT;
+	BLITTER_DOUT[127..0] : OUTPUT;
+	BLITTER_LE[3..0] : OUTPUT;
+	BLITTER_RDE : OUTPUT;
+	DDRWR_D_SEL[1..0] : OUTPUT;
+	VDMP[7..0] : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	FB_REGDDR				:MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);
+	DDR_SM					:MACHINE WITH STATES(DS_T1,DS_T2,DS_T3,DS_T4,DS_T5,DS_T6,DS_T7,DS_T8,DS_LS);
+	LINE					:NODE;
+	FB_B[3..0]				:NODE;
+	VCAS					:NODE;
+	VRAS					:NODE;
+	VWE						:NODE;
+	VA[12..0]				:NODE;
+	BA0						:NODE;
+	BA1						:NODE;
+	DDR_WR					:DFF;
+	DDR_SEL					:NODE;
+	DDR_CONFIG				:NODE;
+	DDRWR_D_SEL[1..0]		:DFF;
+	CPU_ROW_ADR[12..0]		:NODE;
+	CPU_BA0					:NODE;
+	CPU_BA1					:NODE;
+	CPU_COL_ADR[9..0]		:NODE;
+	CPU_SIG					:NODE;
+	CPU_REQ					:DFF;
+	BLITTER_SIG				:NODE;
+	BLITTER_REQ				:DFF;
+	BLITTER_RUN				:DFF;
+	BLITTER_WR				:DFF;
+	BLITTER_ROW_ADR[12..0]	:NODE;
+	BLITTER_BA0				:NODE;
+	BLITTER_BA1				:NODE;
+	BLITTER_COL_ADR[9..0]	:NODE;
+	FIFO_SIG				:NODE;
+	FIFO_REQ				:DFF;
+	FIFO_ROW_ADR[12..0]		:NODE;
+	FIFO_BA0				:NODE;
+	FIFO_BA1				:NODE;
+	FIFO_COL_ADR[9..0]		:NODE;
+	FIFO_WRE				:DFF;
+	FIFO_ACTIVE				:NODE;
+	CLEAR_FIFO_CNT			:DFF;
+	STOP					:DFF;
+	DDR_REFRESH_ON			:NODE;
+	VIDEO_BASE_L_D[3..0]	:DFFE;
+	VIDEO_BASE_L			:NODE;
+	VIDEO_BASE_M_D[7..0]	:DFFE;
+	VIDEO_BASE_M			:NODE;
+	VIDEO_BASE_H_D[7..0]	:DFFE;
+	VIDEO_BASE_H			:NODE;
+	VIDEO_BASE_X_D[7..0]	:DFFE;
+	VIDEO_ADR_CNT[27..0]	:DFFE;
+	VIDEO_CNT_L				:NODE;
+	VIDEO_CNT_M				:NODE;
+	VIDEO_CNT_H				:NODE;
+	VIDEO_BASE_ADR[27..0]	:NODE;
+	
+BEGIN
+	LINE =  FB_SIZE0 &  FB_SIZE1;
+-- BYT SELECT
+	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
+	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR)  --------------------------------------------------
+	FB_REGDDR.CLK = MAIN_CLK;
+	CASE FB_REGDDR IS
+		WHEN FR_WAIT => 
+			IF DDR_SEL THEN
+				FB_REGDDR = FR_S0;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S0 =>
+			FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
+			FB_LE0   = !nFB_WR;
+			IF LINE THEN							
+				FB_REGDDR = FR_S1;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S1 => 
+			FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
+			FB_LE1   = !nFB_WR;
+			FB_REGDDR = FR_S2;
+		WHEN FR_S2 => 
+			FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
+			FB_LE2   = !nFB_WR;
+			FB_REGDDR = FR_S3;
+		WHEN FR_S3 => 
+			FB_VDOE3 = !nFB_OE & !DDR_CONFIG;
+			FB_LE3   = !nFB_WR;
+			FB_REGDDR = FR_WAIT;
+	END CASE;
+-- DDR STEUERUNG -----------------------------------------------------
+-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0=VCKE,1=!nVCS,2=FIFO_ACTIVE,3=FIFO UND CNT CLEAR,15..11=VIDEO RAM BASE
+	VCKE = VIDEO_RAM_CTR0;
+	nVCS = !VIDEO_RAM_CTR1;
+	FIFO_ACTIVE = VIDEO_RAM_CTR2;
+	DDR_CONFIG = VIDEO_RAM_CTR3;	
+	DDR_REFRESH_ON = VIDEO_RAM_CTR4;
+--------------------------------
+	CPU_ROW_ADR[] = FB_ADR[26..14];
+	CPU_BA1 = FB_ADR13;
+	CPU_BA0 = FB_ADR12;
+	CPU_COL_ADR[] = FB_ADR[11..2];
+	nVRAS = !VRAS;
+	nVCAS = !VCAS;
+	nVWE = !VWE;
+	DDR_WR.CLK = DDRCLK0;
+-- SELECT LOGIC
+	DDR_SEL  =  FB_ALE & FB_AD[31..29]==B"011";
+-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER
+	CPU_SIG = DDR_SEL &  nFB_WR & !DDR_CONFIG						-- READ SOFORT LOS
+			# FR_S0   & !nFB_WR 		   							-- WRITE SPÄTER AUCH CONFIG
+			# FR_S3   & !nFB_WR &  LINE  & !DDR_CONFIG;				-- LINE WRITE
+	CPU_REQ = CPU_SIG;
+	CPU_REQ.CLK = DDR_SYNC_66M;
+	DDR_D_SEL[].CLK = DDRCLK3;
+-- DDR STATE MACHINE  -----------------------------------------------
+	DDR_SM.CLK = DDRCLK0;
+	CASE DDR_SM IS
+		WHEN DS_T1 =>
+			IF MAIN_CLK THEN
+				DDR_WR = DDR_WR;									-- WRITE HALTEN (VON T4)
+				DDR_SM = DS_T2;
+			ELSE
+				DDR_SM = DS_LS;										-- SYNCHRONISIEREN
+			END IF;
+		WHEN DS_T2 =>
+			IF !DDR_CONFIG THEN
+				VRAS  = CPU_SIG # BLITTER_SIG # FIFO_SIG # DDR_REFRESH_ON;
+				VA[]  = CPU_SIG 	& CPU_ROW_ADR[]
+					#  BLITTER_SIG & BLITTER_ROW_ADR[]
+					#  FIFO_SIG 	& FIFO_ROW_ADR[];
+				BA0   = CPU_SIG 	& CPU_BA0
+					#  BLITTER_SIG & BLITTER_BA0
+					#  FIFO_SIG 	& FIFO_BA0;
+				BA1   = CPU_SIG 	& CPU_BA1
+					#  BLITTER_SIG & BLITTER_BA1
+					#  FIFO_SIG 	& FIFO_BA1;
+				VCAS = !CPU_SIG & !BLITTER_SIG & !FIFO_SIG & DDR_REFRESH_ON;		-- AUTO REFRESH WENN SONST NICHTS
+				BLITTER_REQ = BLITTER_SIG;
+				FIFO_REQ = FIFO_SIG;	
+			END IF;
+			IF MAIN_CLK THEN
+				DDR_SM = DS_T3;
+			ELSE
+				DDR_SM = DS_LS;
+			END IF;
+		WHEN DS_T3 =>
+			IF DDR_CONFIG & CPU_REQ THEN
+				VRAS = FB_AD18;
+				VCAS = FB_AD17;
+				VWE	 = FB_AD16;
+				BA1  = FB_AD14;
+				BA0  = FB_AD13;
+				VA[] = FB_AD[12..0];
+			END IF;
+			IF !CPU_REQ & !BLITTER_REQ & !FIFO_REQ # DDR_CONFIG THEN
+				DDR_SM = DS_LS;
+			ELSE
+				BLITTER_REQ = BLITTER_SIG;
+				FIFO_REQ = FIFO_SIG;						
+				DDR_SM = DS_T4;
+			END IF;
+		WHEN DS_T4 =>
+			FIFO_REQ = FIFO_SIG;	
+			VCAS = VCC;															
+			VWE  = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ;
+			VA[9..0] = CPU_REQ     & CPU_COL_ADR[]
+					# BLITTER_REQ & BLITTER_COL_ADR[]
+					# FIFO_REQ    & FIFO_COL_ADR[];
+			VA10 = VCC;															-- AUTO PRECHARGE
+			BA0 = CPU_REQ     & CPU_BA0
+				# BLITTER_REQ & BLITTER_BA0
+				# FIFO_REQ    & FIFO_BA0;
+			BA1 = CPU_REQ     & CPU_BA1
+				# BLITTER_REQ & BLITTER_BA1
+				# FIFO_REQ    & FIFO_BA1;
+			DDR_WR         = !nFB_WR & CPU_REQ # BLITTER_WR & BLITTER_REQ;
+			FIFO_REQ = FIFO_SIG;						
+			IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN							-- GLEICHE PAGE?
+				DDR_SM = DS_T5;													-- JA->
+			ELSE
+				DDR_SM = DS_T1;													-- SONST NEUE PAGE AUFMACHEN
+			END IF;
+		WHEN DS_T5 =>
+			FIFO_REQ = FIFO_SIG;	
+			DDR_SM = DS_T6;
+		WHEN DS_T6 =>								 
+			IF CPU_SIG THEN															-- SOFORT UMSCHALTEN WENN CPU REQ
+				VRAS = VCC;
+				VA[] = CPU_ROW_ADR[];
+				BA1  = CPU_BA1;
+				BA0  = CPU_BA0;
+				DDR_SM = DS_T3;
+			ELSE
+				FIFO_REQ = FIFO_SIG;	
+				VCAS = VCC;															
+				VA[9..0] = FIFO_COL_ADR[];
+				VA10 = VCC;															-- AUTO PRECHARGE
+				BA0 = FIFO_BA0;
+				BA1 = FIFO_BA1;
+				FIFO_WRE 	   =  FIFO_REQ;											-- ODER FIFO LATCH IN 5 CYC 133
+				IF FIFO_REQ & FIFO_COL_ADR[]!= H"3FF" THEN							-- GLEICHE PAGE?
+					DDR_SM = DS_T5;													-- JA->
+				ELSE
+					DDR_SM = DS_T1;													-- SONST NEUE PAGE AUFMACHEN
+				END IF;
+			END IF;
+		WHEN DS_LS =>
+			IF !MAIN_CLK THEN														-- LEERSTATE UND SYNC
+				DDR_SM = DS_T1;	
+			ELSE
+				DDR_SM = DS_LS;	
+			END IF;
+	END CASE;
+------------------------------------------------------------------------------	
+-- FIFO ---------------------------------
+	FIFO_SIG = FIFO_ACTIVE & !FIFO_FULL & !BLITTER_SIG & !CPU_SIG;
+	FIFO_REQ.CLK = DDR_SYNC_66M;
+	FIFO_ROW_ADR[] = VIDEO_ADR_CNT[24..12];
+	FIFO_BA1 	   = VIDEO_ADR_CNT11;
+	FIFO_BA0 	   = VIDEO_ADR_CNT10;
+	FIFO_COL_ADR[] = VIDEO_ADR_CNT[9..0];
+	-- ZÄHLER RÜCKSETZEN WENN VSYNC ----------------
+	CLEAR_FIFO_CNT.CLK  = DDRCLK0;
+	CLEAR_FIFO_CNT = VSYNC # !FIFO_ACTIVE;
+	STOP.CLK = DDRCLK0;
+	STOP = VSYNC # CLEAR_FIFO_CNT;
+	VIDEO_ADR_CNT[].CLK = DDRCLK0;
+	VIDEO_ADR_CNT[] =   CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]			-- SET 
+					 # !CLEAR_FIFO_CNT & (VIDEO_ADR_CNT[]+1);		-- NEXT 16 BYTS
+	VIDEO_ADR_CNT[].ENA = CLEAR_FIFO_CNT # FIFO_WRE;
+	FIFO_WRE.CLK = DDRCLK0;
+---------------------------------------------------------------
+-- BLITTER BUS IST 128 BIT BREIT ------
+	BLITTER_SIG = GND & !CPU_SIG;
+	BLITTER_REQ.CLK = DDR_SYNC_66M;
+	BLITTER_RUN.CLK = DDRCLK0;
+	BLITTER_RUN = GND;
+	BLITTER_WR.CLK = DDRCLK0;
+	BLITTER_WR = GND;
+	DDRWR_D_SEL1 = BLITTER_WR;
+	BLITTER_ROW_ADR[] = H"0";
+	BLITTER_BA1 = GND;
+	BLITTER_BA0 = GND;
+	BLITTER_COL_ADR[] = H"0";
+	BLITTER_DOUT[] = H"0";
+	BLITTER_LE[] = H"0";
+-----------------------------------------------------------	
+-- VIDEO REGISTER -----------------------
+---------------------------------------------------------------------------------------------------------------------
+	VIDEO_BASE_L_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_L = !nFB_CS1 & FB_ADR[15..1]==H"4106"; 								-- 820D/2
+	VIDEO_BASE_L_D[] = FB_AD[23..20];												-- SORRY, NUR 16 BYT GRENZEN
+	VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;	
+
+	VIDEO_BASE_M_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_M = !nFB_CS1 & FB_ADR[15..1]==H"4101"; 								-- 8203/2
+	VIDEO_BASE_M_D[] = FB_AD[23..16];
+	VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;	
+
+	VIDEO_BASE_H_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_H = !nFB_CS1 & FB_ADR[15..1]==H"4100";			 					-- 8200-1/2
+	VIDEO_BASE_H_D[] = FB_AD[23..16];
+	VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;	
+	VIDEO_BASE_X_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_X_D[] = FB_AD[31..24];
+	VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;	
+
+	VIDEO_CNT_L = !nFB_CS1 & FB_ADR[15..1]==H"4104"; 								-- 8209/2
+	VIDEO_CNT_M = !nFB_CS1 & FB_ADR[15..1]==H"4103"; 								-- 8207/2
+	VIDEO_CNT_H = !nFB_CS1 & FB_ADR[15..1]==H"4102"; 								-- 8205/2
+					  
+	FB_AD[31..24] = lpm_bustri_BYT(
+						VIDEO_BASE_H     & VIDEO_BASE_X_D[] 
+					  # VIDEO_CNT_H		 & VIDEO_ADR_CNT[27..20]
+					  ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
+
+	FB_AD[23..16] = lpm_bustri_BYT(
+						VIDEO_BASE_L  & (VIDEO_BASE_L_D[],B"0000")
+					  # VIDEO_BASE_M  &  VIDEO_BASE_M_D[]
+					  # VIDEO_BASE_H  &  VIDEO_BASE_H_D[]
+					  # VIDEO_CNT_L	  & (VIDEO_ADR_CNT[3..0],B"0000")
+					  # VIDEO_CNT_M	  &  VIDEO_ADR_CNT[11..4]
+					  # VIDEO_CNT_H	  &  VIDEO_ADR_CNT[19..12]
+					  ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
+						
+	VIDEO_BASE_ADR[27..20] = VIDEO_BASE_X_D[];
+	VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
+	VIDEO_BASE_ADR[11..4]  = VIDEO_BASE_M_D[];
+	VIDEO_BASE_ADR[3..0]   = VIDEO_BASE_L_D[];
+END;
+
diff --git a/FPGA_quartus_GE/Video/UNUSED b/FPGA_quartus_GE/Video/UNUSED
new file mode 100644
index 0000000..12f424b
--- /dev/null
+++ b/FPGA_quartus_GE/Video/UNUSED
@@ -0,0 +1,267 @@
+
+-- Clearbox generated Memory Initialization File (.mif)
+
+WIDTH=6;
+DEPTH=256;
+
+ADDRESS_RADIX=HEX;
+DATA_RADIX=HEX;
+
+CONTENT BEGIN
+	000  :   0F;
+	001  :   0E;
+	002  :   0D;
+	003  :   0C;
+	004  :   0B;
+	005  :   0A;
+	006  :   09;
+	007  :   08;
+	008  :   07;
+	009  :   06;
+	00a  :   05;
+	00b  :   04;
+	00c  :   03;
+	00d  :   02;
+	00e  :   01;
+	00f  :   00;
+	010  :   0F;
+	011  :   0E;
+	012  :   0D;
+	013  :   0C;
+	014  :   0B;
+	015  :   0A;
+	016  :   09;
+	017  :   08;
+	018  :   07;
+	019  :   06;
+	01a  :   05;
+	01b  :   04;
+	01c  :   03;
+	01d  :   02;
+	01e  :   01;
+	01f  :   00;
+	020  :   0F;
+	021  :   0E;
+	022  :   0D;
+	023  :   0C;
+	024  :   0B;
+	025  :   0A;
+	026  :   09;
+	027  :   08;
+	028  :   07;
+	029  :   06;
+	02a  :   05;
+	02b  :   04;
+	02c  :   03;
+	02d  :   02;
+	02e  :   01;
+	02f  :   00;
+	030  :   0F;
+	031  :   0E;
+	032  :   0D;
+	033  :   0C;
+	034  :   0B;
+	035  :   0A;
+	036  :   09;
+	037  :   08;
+	038  :   07;
+	039  :   06;
+	03a  :   05;
+	03b  :   04;
+	03c  :   03;
+	03d  :   02;
+	03e  :   01;
+	03f  :   00;
+	040  :   0F;
+	041  :   0E;
+	042  :   0D;
+	043  :   0C;
+	044  :   0B;
+	045  :   0A;
+	046  :   09;
+	047  :   08;
+	048  :   07;
+	049  :   06;
+	04a  :   05;
+	04b  :   04;
+	04c  :   03;
+	04d  :   02;
+	04e  :   01;
+	04f  :   00;
+	050  :   0F;
+	051  :   0E;
+	052  :   0D;
+	053  :   0C;
+	054  :   0B;
+	055  :   0A;
+	056  :   09;
+	057  :   08;
+	058  :   07;
+	059  :   06;
+	05a  :   05;
+	05b  :   04;
+	05c  :   03;
+	05d  :   02;
+	05e  :   01;
+	05f  :   00;
+	060  :   0F;
+	061  :   0E;
+	062  :   0D;
+	063  :   0C;
+	064  :   0B;
+	065  :   0A;
+	066  :   09;
+	067  :   08;
+	068  :   07;
+	069  :   06;
+	06a  :   05;
+	06b  :   04;
+	06c  :   03;
+	06d  :   02;
+	06e  :   01;
+	06f  :   00;
+	070  :   0F;
+	071  :   0E;
+	072  :   0D;
+	073  :   0C;
+	074  :   0B;
+	075  :   0A;
+	076  :   09;
+	077  :   08;
+	078  :   07;
+	079  :   06;
+	07a  :   05;
+	07b  :   04;
+	07c  :   03;
+	07d  :   02;
+	07e  :   01;
+	07f  :   00;
+	080  :   0F;
+	081  :   0E;
+	082  :   0D;
+	083  :   0C;
+	084  :   0B;
+	085  :   0A;
+	086  :   09;
+	087  :   08;
+	088  :   07;
+	089  :   06;
+	08a  :   05;
+	08b  :   04;
+	08c  :   03;
+	08d  :   02;
+	08e  :   01;
+	08f  :   00;
+	090  :   0F;
+	091  :   0E;
+	092  :   0D;
+	093  :   0C;
+	094  :   0B;
+	095  :   0A;
+	096  :   09;
+	097  :   08;
+	098  :   07;
+	099  :   06;
+	09a  :   05;
+	09b  :   04;
+	09c  :   03;
+	09d  :   02;
+	09e  :   01;
+	09f  :   00;
+	0a0  :   0F;
+	0a1  :   0E;
+	0a2  :   0D;
+	0a3  :   0C;
+	0a4  :   0B;
+	0a5  :   0A;
+	0a6  :   09;
+	0a7  :   08;
+	0a8  :   07;
+	0a9  :   06;
+	0aa  :   05;
+	0ab  :   04;
+	0ac  :   03;
+	0ad  :   02;
+	0ae  :   01;
+	0af  :   00;
+	0b0  :   0F;
+	0b1  :   0E;
+	0b2  :   0D;
+	0b3  :   0C;
+	0b4  :   0B;
+	0b5  :   0A;
+	0b6  :   09;
+	0b7  :   08;
+	0b8  :   07;
+	0b9  :   06;
+	0ba  :   05;
+	0bb  :   04;
+	0bc  :   03;
+	0bd  :   02;
+	0be  :   01;
+	0bf  :   00;
+	0c0  :   0F;
+	0c1  :   0E;
+	0c2  :   0D;
+	0c3  :   0C;
+	0c4  :   0B;
+	0c5  :   0A;
+	0c6  :   09;
+	0c7  :   08;
+	0c8  :   07;
+	0c9  :   06;
+	0ca  :   05;
+	0cb  :   04;
+	0cc  :   03;
+	0cd  :   02;
+	0ce  :   01;
+	0cf  :   00;
+	0d0  :   0F;
+	0d1  :   0E;
+	0d2  :   0D;
+	0d3  :   0C;
+	0d4  :   0B;
+	0d5  :   0A;
+	0d6  :   09;
+	0d7  :   08;
+	0d8  :   07;
+	0d9  :   06;
+	0da  :   05;
+	0db  :   04;
+	0dc  :   03;
+	0dd  :   02;
+	0de  :   01;
+	0df  :   00;
+	0e0  :   0F;
+	0e1  :   0E;
+	0e2  :   0D;
+	0e3  :   0C;
+	0e4  :   0B;
+	0e5  :   0A;
+	0e6  :   09;
+	0e7  :   08;
+	0e8  :   07;
+	0e9  :   06;
+	0ea  :   05;
+	0eb  :   04;
+	0ec  :   03;
+	0ed  :   02;
+	0ee  :   01;
+	0ef  :   00;
+	0f0  :   0F;
+	0f1  :   0E;
+	0f2  :   0D;
+	0f3  :   0C;
+	0f4  :   0B;
+	0f5  :   0A;
+	0f6  :   09;
+	0f7  :   08;
+	0f8  :   07;
+	0f9  :   06;
+	0fa  :   05;
+	0fb  :   04;
+	0fc  :   03;
+	0fd  :   02;
+	0fe  :   01;
+	0ff  :   00;
+END;
diff --git a/FPGA_quartus_GE/Video/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_quartus_GE/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
new file mode 100644
index 0000000..2c9adcc
--- /dev/null
+++ b/FPGA_quartus_GE/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
@@ -0,0 +1,675 @@
+TITLE "VIDEO MODUSE UND CLUT CONTROL";
+
+-- CREATED BY FREDI ASCHWANDEN
+
+INCLUDE "lpm_bustri_WORD.inc";
+INCLUDE "lpm_bustri_BYT.inc";
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	nRSTO : INPUT;
+	MAIN_CLK : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	nFB_CS3 : INPUT;
+	nFB_WR : INPUT;
+	nFB_OE : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	nFB_BURST : INPUT;
+	FB_ADR[31..0] : INPUT;
+	CLK33M : INPUT;
+	CLK25M : INPUT;
+	BLITTER_RUN : INPUT;
+	CLK_VIDEO : INPUT;
+	VR_D[8..0] : INPUT;
+	VR_BUSY : INPUT;
+	COLOR8 : OUTPUT;
+	ACP_CLUT_RD : OUTPUT;
+	COLOR1 : OUTPUT;
+	FALCON_CLUT_RDH : OUTPUT;
+	FALCON_CLUT_RDL : OUTPUT;
+	FALCON_CLUT_WR[3..0] : OUTPUT;
+	ST_CLUT_RD : OUTPUT;
+	ST_CLUT_WR[1..0] : OUTPUT;
+	CLUT_MUX_ADR[3..0] : OUTPUT;
+	HSYNC : OUTPUT;
+	VSYNC : OUTPUT;
+	nBLANK : OUTPUT;
+	nSYNC : OUTPUT;
+	nPD_VGA : OUTPUT;
+	FIFO_RDE : OUTPUT;
+	COLOR2 : OUTPUT;
+	COLOR4 : OUTPUT;
+	PIXEL_CLK : OUTPUT;
+	CLUT_OFF[3..0] : OUTPUT;
+	BLITTER_ON : OUTPUT;
+	VIDEO_RAM_CTR[15..0] : OUTPUT;
+	VIDEO_MOD_TA : OUTPUT;
+	CCR[23..0] : OUTPUT;
+	CCSEL[2..0] : OUTPUT;
+	ACP_CLUT_WR[3..0] : OUTPUT;
+	INTER_ZEI : OUTPUT;
+	DOP_FIFO_CLR : OUTPUT;
+	VIDEO_RECONFIG : OUTPUT;
+	VR_WR : OUTPUT;
+	VR_RD : OUTPUT;
+	CLR_FIFO : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	CLK17M						:DFF;
+	CLK13M						:DFF;
+	ACP_CLUT_CS					:NODE;
+	ACP_CLUT					:NODE;
+	VIDEO_PLL_CONFIG_CS			:NODE;
+	VR_WR						:DFF;
+	VR_DOUT[8..0]				:DFFE;
+	VR_FRQ[7..0]				:DFFE;
+	VIDEO_PLL_RECONFIG_CS		:NODE;
+	VIDEO_RECONFIG				:DFF;
+	FALCON_CLUT_CS				:NODE;
+	FALCON_CLUT					:NODE;
+	ST_CLUT_CS					:NODE;
+	ST_CLUT						:NODE;
+	FB_B[3..0]					:NODE;
+	FB_16B[1..0]				:NODE;
+	ST_SHIFT_MODE[1..0]			:DFFE;
+	ST_SHIFT_MODE_CS			:NODE;
+	FALCON_SHIFT_MODE[10..0]	:DFFE;
+	FALCON_SHIFT_MODE_CS		:NODE;
+	CLUT_MUX_ADR[3..0]			:DFF;
+	CLUT_MUX_AV[1..0][3..0]		:DFF;
+	ACP_VCTR_CS					:NODE;
+	ACP_VCTR[31..0]				:DFFE;
+	CCR_CS						:NODE;
+	CCR[23..0]					:DFFE;
+	ACP_VIDEO_ON				:NODE;
+	SYS_CTR[6..0]				:DFFE;
+	SYS_CTR_CS					:NODE;
+	VDL_LOF[15..0]				:DFFE;
+	VDL_LOF_CS					:NODE;
+	VDL_LWD[15..0]				:DFFE;
+	VDL_LWD_CS					:NODE;
+-- DIV. CONTROL REGISTER
+	CLUT_TA						:DFF;  			-- BRAUCHT EIN WAITSTAT
+	HSYNC						:DFF;
+	HSYNC_I[7..0]				:DFF;
+	HSY_LEN[7..0]				:DFF;			-- LÄNGE HSYNC PULS IN PIXEL_CLK
+	HSYNC_START					:DFF;
+	LAST						:DFF;			-- LETZTES PIXEL EINER ZEILE ERREICHT
+	VSYNC						:DFF;
+	VSYNC_START					:DFFE;
+	VSYNC_I[2..0]				:DFFE;
+	nBLANK						:DFF;
+	DISP_ON						:DFF;
+	DPO_ZL						:DFFE;
+	DPO_ON						:DFF;
+	DPO_OFF						:DFF;
+	VDTRON						:DFF;
+	VDO_ZL						:DFFE;
+	VDO_ON						:DFF;
+	VDO_OFF						:DFF;
+	VHCNT[11..0]				:DFF;
+	SUB_PIXEL_CNT[6..0]			:DFFE;
+	VVCNT[10..0]				:DFFE;
+	VERZ[2..0][9..0]			:DFF;
+	RAND[6..0]					:DFF;
+	RAND_ON						:NODE;
+	FIFO_RDE					:DFF;
+	CLR_FIFO					:DFFE;
+	START_ZEILE					:DFFE;
+	SYNC_PIX					:DFF;
+	SYNC_PIX1					:DFF;
+	SYNC_PIX2					:DFF;
+	CCSEL[2..0]					:DFF;
+	COLOR16						:NODE;
+	COLOR24						:NODE;
+-- ATARI RESOLUTION
+	ATARI_SYNC					:NODE;	 
+	ATARI_HH[31..0]				:DFFE;		-- HORIZONTAL TIMING 640x480
+	ATARI_HH_CS					:NODE;
+	ATARI_VH[31..0]				:DFFE;		-- VERTIKAL TIMING 640x480 
+	ATARI_VH_CS					:NODE;
+	ATARI_HL[31..0]				:DFFE;		-- HORIZONTAL TIMING 320x240
+	ATARI_HL_CS					:NODE;
+	ATARI_VL[31..0]				:DFFE;		-- VERTIKAL TIMING 320x240
+	ATARI_VL_CS					:NODE;
+-- HORIZONTAL
+	RAND_LINKS[11..0]			:NODE;
+	HDIS_START[11..0]			:NODE;
+	HDIS_END[11..0]				:NODE;  
+	RAND_RECHTS[11..0]			:NODE;
+	HS_START[11..0]				:NODE;
+	H_TOTAL[11..0]				:NODE;
+	HDIS_LEN[11..0]				:NODE;
+	MULF[5..0]					:NODE;
+	VDL_HHT[11..0]				:DFFE;
+	VDL_HHT_CS					:NODE;
+	VDL_HBE[11..0]				:DFFE;
+	VDL_HBE_CS					:NODE;
+	VDL_HDB[11..0]				:DFFE;
+	VDL_HDB_CS					:NODE;
+	VDL_HDE[11..0]				:DFFE;
+	VDL_HDE_CS					:NODE;
+	VDL_HBB[11..0]				:DFFE;
+	VDL_HBB_CS					:NODE;
+	VDL_HSS[11..0]				:DFFE;
+	VDL_HSS_CS					:NODE;
+-- VERTIKAL
+	RAND_OBEN[10..0]			:NODE; 
+	VDIS_START[10..0]			:NODE; 
+	VDIS_END[10..0]				:NODE; 
+	RAND_UNTEN[10..0]			:NODE; 
+	VS_START[10..0]				:NODE; 
+	V_TOTAL[10..0]				:NODE;  
+	FALCON_VIDEO				:NODE;
+	ST_VIDEO					:NODE;
+	INTER_ZEI					:DFF;
+	DOP_ZEI						:DFF;
+	DOP_FIFO_CLR				:DFF;
+	
+	VDL_VBE[10..0]				:DFFE;
+	VDL_VBE_CS					:NODE;
+	VDL_VDB[10..0]				:DFFE;
+	VDL_VDB_CS					:NODE;
+	VDL_VDE[10..0]				:DFFE;
+	VDL_VDE_CS					:NODE;
+	VDL_VBB[10..0]				:DFFE;
+	VDL_VBB_CS					:NODE;
+	VDL_VSS[10..0]				:DFFE;
+	VDL_VSS_CS					:NODE;
+	VDL_VFT[10..0]				:DFFE;
+	VDL_VFT_CS					:NODE;
+	VDL_VCT[8..0]				:DFFE;
+	VDL_VCT_CS					:NODE;
+	VDL_VMD[3..0]				:DFFE;
+	VDL_VMD_CS					:NODE;
+
+BEGIN
+-- BYT SELECT 32 BIT
+	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
+	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+-- BYT SELECT 16 BIT
+	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
+	FB_16B1 = FB_ADR[0]==1									-- ADR==1
+		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
+-- ACP CLUT --
+	ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0";						-- 0-3FF/1024
+	ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
+	ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR;
+	CLUT_TA.CLK = MAIN_CLK;
+	CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA;
+--FALCON CLUT --
+	FALCON_CLUT_CS  = !nFB_CS1 & FB_ADR[19..10]==H"3E6";				-- $F9800/$400
+	FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1;				-- HIGH WORD
+	FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE &  FB_ADR1;				-- LOW WORD
+	FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
+	FALCON_CLUT_WR[3..2] = FB_16B[] &  FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
+-- ST CLUT --
+	ST_CLUT_CS  = !nFB_CS1 & FB_ADR[19..5]==H"7C12";					-- $F8240/$20
+	ST_CLUT_RD  = ST_CLUT_CS & !nFB_OE;
+	ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR;
+-- ST SHIFT MODE
+	ST_SHIFT_MODE[].CLK = MAIN_CLK;
+	ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130";				-- $F8260/2
+	ST_SHIFT_MODE[] = FB_AD[25..24];
+	ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
+	COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
+	COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
+	COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
+-- FALCON SHIFT MODE
+	FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
+	FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133";			-- $F8266/2
+	FALCON_SHIFT_MODE[] = FB_AD[26..16];
+	FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
+	FALCON_SHIFT_MODE[7..0].ENA  = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
+	CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
+	COLOR1  = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR8  = FALCON_SHIFT_MODE4  & !COLOR16           & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR16 = FALCON_SHIFT_MODE8                       & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR4  = !COLOR1             & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
+-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
+	ACP_VCTR[].CLK = MAIN_CLK;
+	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100";						-- $400/4
+	ACP_VCTR[31..8] = FB_AD[31..8];
+	ACP_VCTR[5..0] = FB_AD[5..0];
+	ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
+	ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR;
+	ACP_VCTR[15..8].ENA  = ACP_VCTR_CS & FB_B2 & !nFB_WR;
+	ACP_VCTR[5..0].ENA   = ACP_VCTR_CS & FB_B3 & !nFB_WR;
+	ACP_VIDEO_ON = ACP_VCTR0;
+	nPD_VGA = ACP_VCTR1;
+	-- ATARI MODUS
+	ATARI_SYNC = ACP_VCTR26;			-- WENN 1 AUTOMATISCHE AUFLÖSUNG
+	-- HORIZONTAL TIMING 640x480
+	ATARI_HH[].CLK = MAIN_CLK;
+	ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104";						-- $410/4
+	ATARI_HH[] = FB_AD[];
+	ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
+	ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
+	ATARI_HH[15..8].ENA  = ATARI_HH_CS & FB_B2 & !nFB_WR;
+	ATARI_HH[7..0].ENA   = ATARI_HH_CS & FB_B3 & !nFB_WR;
+	-- VERTIKAL TIMING 640x480
+	ATARI_VH[].CLK = MAIN_CLK;
+	ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105";						-- $414/4
+	ATARI_VH[] = FB_AD[];
+	ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
+	ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
+	ATARI_VH[15..8].ENA  = ATARI_VH_CS & FB_B2 & !nFB_WR;
+	ATARI_VH[7..0].ENA   = ATARI_VH_CS & FB_B3 & !nFB_WR;
+	-- HORIZONTAL TIMING 320x240
+	ATARI_HL[].CLK = MAIN_CLK;
+	ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106";						-- $418/4
+	ATARI_HL[] = FB_AD[];
+	ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
+	ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
+	ATARI_HL[15..8].ENA  = ATARI_HL_CS & FB_B2 & !nFB_WR;
+	ATARI_HL[7..0].ENA   = ATARI_HL_CS & FB_B3 & !nFB_WR;
+	-- VERTIKAL TIMING 320x240
+	ATARI_VL[].CLK = MAIN_CLK;
+	ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107";						-- $41C/4
+	ATARI_VL[] = FB_AD[];
+	ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
+	ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
+	ATARI_VL[15..8].ENA  = ATARI_VL_CS & FB_B2 & !nFB_WR;
+	ATARI_VL[7..0].ENA   = ATARI_VL_CS & FB_B3 & !nFB_WR;
+-- VIDEO PLL CONFIG
+	VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1;	-- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
+	VR_WR.CLK = MAIN_CLK;
+	VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
+	VR_RD = VIDEO_PLL_CONFIG_CS &  nFB_WR & !VR_BUSY;
+	VR_DOUT[].CLK = MAIN_CLK;
+	VR_DOUT[].ENA = !VR_BUSY;
+	VR_DOUT[] = VR_D[];
+	VR_FRQ[].CLK = MAIN_CLK;
+	VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
+	VR_FRQ[] = FB_AD[23..16];
+-- VIDEO PLL RECONFIG
+	VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0;		-- $(F)000'0800 
+	VIDEO_RECONFIG.CLK = MAIN_CLK;
+	VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
+------------------------------------------------------------------------------------------------------------------------
+	VIDEO_RAM_CTR[] = ACP_VCTR[31..16];
+-------------- COLOR MODE IM ACP SETZEN	
+	COLOR1   = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
+	COLOR8   = 			    ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
+	COLOR16  = 				   		     ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
+	COLOR24  = 										  ACP_VCTR2 & ACP_VIDEO_ON;
+	ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
+-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
+	ACP_VCTR7          = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
+	ACP_VCTR6          = ST_SHIFT_MODE_CS     & !nFB_WR & !ACP_VIDEO_ON;
+	ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
+	FALCON_VIDEO	   = ACP_VCTR7;
+	FALCON_CLUT        = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
+	ST_VIDEO		   = ACP_VCTR6;
+	ST_CLUT            = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1;
+	CCSEL[].CLK = PIXEL_CLK;
+	CCSEL[] = B"000" & ST_CLUT				-- ONLY FOR INFORMATION
+			# B"001" & FALCON_CLUT
+			# B"100" & ACP_CLUT
+			# B"101" & COLOR16
+			# B"110" & COLOR24
+			# B"111" & RAND_ON;
+-- DIVERSE (VIDEO)-REGISTER ----------------------------
+-- RANDFARBE
+	CCR[].CLK = MAIN_CLK;
+	CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101";						-- $404/4
+	CCR[] = FB_AD[23..0];
+	CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
+	CCR[15..8].ENA  = CCR_CS & FB_B2 & !nFB_WR;
+	CCR[7..0].ENA   = CCR_CS & FB_B3 & !nFB_WR;
+--SYS CTR
+	SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003";						-- $8006/2
+	SYS_CTR[].CLK = MAIN_CLK;
+	SYS_CTR[6..0] = FB_AD[22..16];
+	SYS_CTR[6..0].ENA  = SYS_CTR_CS & !nFB_WR & FB_B3;
+	BLITTER_ON = !SYS_CTR3;
+--VDL_LOF
+	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $820E/2
+	VDL_LOF[].CLK = MAIN_CLK;
+	VDL_LOF[] = FB_AD[31..16];
+	VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
+	VDL_LOF[7..0].ENA  = VDL_LOF_CS & !nFB_WR & FB_B3;
+--VDL_LWD
+	VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108";						-- $8210/2
+	VDL_LWD[].CLK = MAIN_CLK;
+	VDL_LWD[] = FB_AD[31..16];
+	VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
+	VDL_LWD[7..0].ENA  = VDL_LWD_CS & !nFB_WR & FB_B1;
+-- HORIZONTAL
+-- VDL_HHT
+	VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141";						-- $8282/2
+	VDL_HHT[].CLK = MAIN_CLK;
+	VDL_HHT[] = FB_AD[27..16];
+	VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
+	VDL_HHT[7..0].ENA  = VDL_HHT_CS & !nFB_WR & FB_B3;
+-- VDL_HBE
+	VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143";						-- $8286/2
+	VDL_HBE[].CLK = MAIN_CLK;
+	VDL_HBE[] = FB_AD[27..16];
+	VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
+	VDL_HBE[7..0].ENA  = VDL_HBE_CS & !nFB_WR & FB_B3;
+-- VDL_HDB
+	VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144";						-- $8288/2
+	VDL_HDB[].CLK = MAIN_CLK;
+	VDL_HDB[] = FB_AD[27..16];
+	VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
+	VDL_HDB[7..0].ENA  = VDL_HDB_CS & !nFB_WR & FB_B1;
+-- VDL_HDE
+	VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145";						-- $828A/2
+	VDL_HDE[].CLK = MAIN_CLK;
+	VDL_HDE[] = FB_AD[27..16];
+	VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
+	VDL_HDE[7..0].ENA  = VDL_HDE_CS & !nFB_WR & FB_B3;
+-- VDL_HBB
+	VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142";						-- $8284/2
+	VDL_HBB[].CLK = MAIN_CLK;
+	VDL_HBB[] = FB_AD[27..16];
+	VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
+	VDL_HBB[7..0].ENA  = VDL_HBB_CS & !nFB_WR & FB_B1;
+-- VDL_HSS
+	VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146";						-- $828C/2
+	VDL_HSS[].CLK = MAIN_CLK;
+	VDL_HSS[] = FB_AD[27..16];
+	VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
+	VDL_HSS[7..0].ENA  = VDL_HSS_CS & !nFB_WR & FB_B1;
+-- VERTIKAL
+-- VDL_VBE
+	VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153";						-- $82A6/2
+	VDL_VBE[].CLK = MAIN_CLK;
+	VDL_VBE[] = FB_AD[26..16];
+	VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
+	VDL_VBE[7..0].ENA  = VDL_VBE_CS & !nFB_WR & FB_B3;
+-- VDL_VDB
+	VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154";						-- $82A8/2
+	VDL_VDB[].CLK = MAIN_CLK;
+	VDL_VDB[] = FB_AD[26..16];
+	VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
+	VDL_VDB[7..0].ENA  = VDL_VDB_CS & !nFB_WR & FB_B1;
+-- VDL_VDE
+	VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155";						-- $82AA/2
+	VDL_VDE[].CLK = MAIN_CLK;
+	VDL_VDE[] = FB_AD[26..16];
+	VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
+	VDL_VDE[7..0].ENA  = VDL_VDE_CS & !nFB_WR & FB_B3;
+-- VDL_VBB
+	VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152";						-- $82A4/2
+	VDL_VBB[].CLK = MAIN_CLK;
+	VDL_VBB[] = FB_AD[26..16];
+	VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
+	VDL_VBB[7..0].ENA  = VDL_VBB_CS & !nFB_WR & FB_B1;
+-- VDL_VSS
+	VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156";						-- $82AC/2
+	VDL_VSS[].CLK = MAIN_CLK;
+	VDL_VSS[] = FB_AD[26..16];
+	VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
+	VDL_VSS[7..0].ENA  = VDL_VSS_CS & !nFB_WR & FB_B1;
+-- VDL_VFT
+	VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151";						-- $82A2/2
+	VDL_VFT[].CLK = MAIN_CLK;
+	VDL_VFT[] = FB_AD[26..16];
+	VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
+	VDL_VFT[7..0].ENA  = VDL_VFT_CS & !nFB_WR & FB_B3;
+-- VDL_VCT
+	VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160";						-- $82C0/2
+	VDL_VCT[].CLK = MAIN_CLK;
+	VDL_VCT[] = FB_AD[24..16];
+	VDL_VCT[8].ENA 		= VDL_VCT_CS & !nFB_WR & FB_B0;
+	VDL_VCT[7..0].ENA  	= VDL_VCT_CS & !nFB_WR & FB_B1;
+-- VDL_VMD
+	VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161";						-- $82C2/2
+	VDL_VMD[].CLK = MAIN_CLK;
+	VDL_VMD[] = FB_AD[19..16];
+	VDL_VMD[3..0].ENA  	= VDL_VMD_CS & !nFB_WR & FB_B3;
+--- REGISTER OUT
+	FB_AD[31..16] = lpm_bustri_WORD(
+						ST_SHIFT_MODE_CS 		& (0,ST_SHIFT_MODE[],B"00000000") 
+					  #	FALCON_SHIFT_MODE_CS 	& (0,FALCON_SHIFT_MODE[])
+					  # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0])	 
+					  # VDL_LOF_CS & VDL_LOF[]
+					  # VDL_LWD_CS & VDL_LWD[]
+					  #	VDL_HBE_CS & (0,VDL_HBE[])
+					  #	VDL_HDB_CS & (0,VDL_HDB[])
+					  #	VDL_HDE_CS & (0,VDL_HDE[])
+					  #	VDL_HBB_CS & (0,VDL_HBB[])
+					  #	VDL_HSS_CS & (0,VDL_HSS[])
+					  #	VDL_HHT_CS & (0,VDL_HHT[])
+					  #	VDL_VBE_CS & (0,VDL_VBE[])
+					  #	VDL_VDB_CS & (0,VDL_VDB[])
+					  #	VDL_VDE_CS & (0,VDL_VDE[])
+					  #	VDL_VBB_CS & (0,VDL_VBB[])
+					  #	VDL_VSS_CS & (0,VDL_VSS[])
+					  #	VDL_VFT_CS & (0,VDL_VFT[])
+					  #	VDL_VCT_CS & (0,VDL_VCT[])			 
+					  #	VDL_VMD_CS & (0,VDL_VMD[])
+ 					  #	ACP_VCTR_CS & ACP_VCTR[31..16]
+ 					  #	ATARI_HH_CS & ATARI_HH[31..16]
+					  #	ATARI_VH_CS & ATARI_VH[31..16]
+					  #	ATARI_HL_CS & ATARI_HL[31..16]
+					  #	ATARI_VL_CS & ATARI_VL[31..16]
+					  #	CCR_CS & (0,CCR[23..16])
+ 					  #	VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
+ 					  #	VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
+					  ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
+					 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS 
+					 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
+					 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE);
+
+ 	FB_AD[15..0] = lpm_bustri_WORD(
+ 					   	ACP_VCTR_CS & ACP_VCTR[15..0]
+					  #	ATARI_HH_CS & ATARI_HH[15..0]
+					  #	ATARI_VH_CS & ATARI_VH[15..0]
+					  #	ATARI_HL_CS & ATARI_HL[15..0]
+					  #	ATARI_VL_CS & ATARI_VL[15..0]
+ 					  #	CCR_CS & CCR[15..0]
+ 					  ,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
+
+	VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS 
+			   	 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
+				 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
+				 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
+	
+-- VIDEO AUSGABE SETZEN
+	CLK17M.CLK = CLK33M;
+	CLK17M = !CLK17M;
+	CLK13M.CLK = CLK25M;
+	CLK13M = !CLK13M;
+	PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0) 
+			#	CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
+			#	CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
+			#	CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
+			#	CLK25M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	CLK33M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#	CLK_VIDEO  & ACP_VIDEO_ON & ACP_VCTR[9];
+--------------------------------------------------------------
+-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK
+----------------------------------------------------------------
+	HSY_LEN[].CLK = MAIN_CLK;		
+	HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0)
+			#	16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
+			#	28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
+			#	32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
+			#	28 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	32 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#   16 + (0,VR_FRQ[7..1]) &  ACP_VIDEO_ON & ACP_VCTR[9];			-- hsync puls length in pixeln=frequenz/ = 500ns
+
+ 	MULF[] =  2  & !ST_VIDEO &  VDL_VMD2						-- MULTIPLIKATIONS FAKTOR
+			# 4  & !ST_VIDEO & !VDL_VMD2
+			# 16 &  ST_VIDEO &  VDL_VMD2
+			# 32 &  ST_VIDEO & !VDL_VMD2;
+	 	
+	 	
+	HDIS_LEN[] =  320 &  VDL_VMD2								-- BREITE IN PIXELN
+			   #  640 & !VDL_VMD2;
+					
+-- DOPPELZEILENMODUS
+	DOP_ZEI.CLK = MAIN_CLK;
+	DOP_ZEI = VDL_VMD0 & ST_VIDEO;								-- ZEILENVERDOPPELUNG EIN AUS
+	INTER_ZEI.CLK = PIXEL_CLK;
+	INTER_ZEI =  DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) 	    -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
+	          #  DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); 		-- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
+	DOP_FIFO_CLR.CLK = PIXEL_CLK;
+	DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX;				-- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
+					
+	RAND_LINKS[] 	=  VDL_HBE[] 									&  ACP_VIDEO_ON
+					#  21											& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  42											& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					#  VDL_HBE[] * (0,MULF[5..1])					& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
+	HDIS_START[] 	=  VDL_HDB[] 									&  ACP_VIDEO_ON
+					#  RAND_LINKS[]+1 								& !ACP_VIDEO_ON;						--  
+	HDIS_END[]	 	=  VDL_HDE[] 									&  ACP_VIDEO_ON
+					#  RAND_LINKS[]+HDIS_LEN[]						& !ACP_VIDEO_ON; 						--  
+	RAND_RECHTS[] 	=  VDL_HBB[] 									&  ACP_VIDEO_ON
+					#  HDIS_END[]+1									& !ACP_VIDEO_ON; 						--  
+	HS_START[]		=  VDL_HSS[] 									&  ACP_VIDEO_ON
+					#  ATARI_HL[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_HH[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1])		& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
+	H_TOTAL[] 		=  VDL_HHT[] 									&  ACP_VIDEO_ON
+					#  ATARI_HL[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_HH[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (VDL_HHT[]+2) * (0,MULF[])	 				& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
+					
+	RAND_OBEN[]		=  VDL_VBE[]					&  ACP_VIDEO_ON
+					#  31							& !ACP_VIDEO_ON &  ATARI_SYNC 
+					# (0,VDL_VBE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
+	VDIS_START[]	=  VDL_VDB[]					&  ACP_VIDEO_ON
+					#  32							& !ACP_VIDEO_ON &  ATARI_SYNC 
+					# (0,VDL_VDB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
+	VDIS_END[]		=  VDL_VDE[]					&  ACP_VIDEO_ON
+					#  431							& !ACP_VIDEO_ON &  ATARI_SYNC &  ST_VIDEO
+					#  511							& !ACP_VIDEO_ON &  ATARI_SYNC & !ST_VIDEO
+					# (0,VDL_VDE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
+	RAND_UNTEN[]	=  VDL_VBB[]					&  ACP_VIDEO_ON
+					#  VDIS_END[]+1					& !ACP_VIDEO_ON &  ATARI_SYNC 
+					# (0,VDL_VBB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC;  
+	VS_START[]		=  VDL_VSS[]					&  ACP_VIDEO_ON
+					#  ATARI_VL[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_VH[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (0,VDL_VSS[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
+	V_TOTAL[] 		=  VDL_VFT[]					&  ACP_VIDEO_ON
+					#  ATARI_VL[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_VH[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (0,VDL_VFT[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
+-- ZÄHLER
+	LAST.CLK = PIXEL_CLK;
+	LAST = VHCNT[]==(H_TOTAL[]-2);
+	VHCNT[].CLK = PIXEL_CLK;
+	VHCNT[] = (VHCNT[] + 1) & !LAST;
+	VVCNT[].CLK = PIXEL_CLK;
+	VVCNT[].ENA = LAST;
+	VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
+-- DISPLAY ON OFF
+	DPO_ZL.CLK = PIXEL_CLK;
+	DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1);	-- 1 ZEILE DAVOR ON OFF
+	DPO_ZL.ENA = LAST;												-- AM ZEILENENDE ÜBERNEHMEN
+	DPO_ON.CLK = PIXEL_CLK;
+	DPO_ON = VHCNT[]==RAND_LINKS[];									-- BESSER EINZELN WEGEN TIMING
+	DPO_OFF.CLK = PIXEL_CLK;
+	DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1);
+	DISP_ON.CLK = PIXEL_CLK;
+	DISP_ON = DISP_ON & !DPO_OFF 
+			# DPO_ON & DPO_ZL;
+-- DATENTRANSFER ON OFF
+	VDO_ON.CLK = PIXEL_CLK;
+	VDO_ON = VHCNT[]==(HDIS_START[]-1);								-- BESSER EINZELN WEGEN TIMING
+	VDO_OFF.CLK = PIXEL_CLK;
+	VDO_OFF = VHCNT[]==HDIS_END[];
+	VDO_ZL.CLK = PIXEL_CLK;
+	VDO_ZL.ENA = LAST;												-- AM ZEILENENDE ÜBERNEHMEN
+	VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]);	-- 1 ZEILE DAVOR ON OFF
+	VDTRON.CLK = PIXEL_CLK;
+	VDTRON = VDTRON & !VDO_OFF
+		   # VDO_ON & VDO_ZL;
+-- VERZÖGERUNG UND SYNC	
+	HSYNC_START.CLK = PIXEL_CLK;
+	HSYNC_START = VHCNT[]==HS_START[]-3;
+	HSYNC_I[].CLK = PIXEL_CLK;
+	HSYNC_I[] = HSY_LEN[]    &  HSYNC_START
+			 # (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
+	VSYNC_START.CLK = PIXEL_CLK;
+	VSYNC_START.ENA = LAST;
+	VSYNC_START = VVCNT[]==(VS_START[]-3);						-- start am ende der Zeile vor dem vsync		
+	VSYNC_I[].CLK = PIXEL_CLK;
+	VSYNC_I[].ENA = LAST;										-- start am ende der Zeile vor dem vsync
+	VSYNC_I[] =   3 	    &  VSYNC_START						-- 3 zeilen vsync length
+			# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0;		-- runterzählen bis 0
+	VERZ[][].CLK = PIXEL_CLK;
+	VERZ[][1] = VERZ[][0];
+	VERZ[][2] = VERZ[][1];
+	VERZ[][3] = VERZ[][2];
+	VERZ[][4] = VERZ[][3];
+	VERZ[][5] = VERZ[][4];
+	VERZ[][6] = VERZ[][5];
+	VERZ[][7] = VERZ[][6];
+	VERZ[][8] = VERZ[][7];
+	VERZ[][9] = VERZ[][8];
+	VERZ[0][0] = DISP_ON;
+	VERZ[1][0] = HSYNC_I[]!=0;
+	VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
+				#  ACP_VCTR15 &  VDL_VCT6  & HSYNC_I[]==0;		-- NUR MÖGLICH WENN BEIDE
+	VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
+				#  ACP_VCTR15 &  VDL_VCT5  & VSYNC_I[]==0;		-- NUR MÖGLICH WENN BEIDE
+	nBLANK.CLK = PIXEL_CLK;
+	nBLANK =  VERZ[0][8];
+	HSYNC.CLK = PIXEL_CLK;
+	HSYNC  =  VERZ[1][9];
+	VSYNC.CLK = PIXEL_CLK;
+	VSYNC  =  VERZ[2][9];
+	nSYNC  = GND;
+-- RANDFARBE MACHEN ------------------------------------
+	RAND[].CLK = PIXEL_CLK;
+	RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
+	RAND[1] = RAND[0];
+	RAND[2] = RAND[1];
+	RAND[3] = RAND[2];
+	RAND[4] = RAND[3];
+	RAND[5] = RAND[4];
+	RAND[6] = RAND[5];
+	RAND_ON = RAND[6];
+----------------------------------------------------------
+	CLR_FIFO.CLK = PIXEL_CLK;
+	CLR_FIFO.ENA = LAST;
+	CLR_FIFO = VVCNT[]==V_TOTAL[]-2;								-- IN LETZTER ZEILE LÖSCHEN
+	START_ZEILE.CLK = PIXEL_CLK;
+	START_ZEILE.ENA = LAST;
+	START_ZEILE = VVCNT[]==0;										-- ZEILE 1
+	SYNC_PIX.CLK = PIXEL_CLK;
+	SYNC_PIX  = VHCNT[]==3 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SYNC_PIX1.CLK = PIXEL_CLK;
+	SYNC_PIX1 = VHCNT[]==5 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SYNC_PIX2.CLK = PIXEL_CLK;
+	SYNC_PIX2 = VHCNT[]==7 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
+	SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
+	SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX;			--count up if display on sonst clear bei sync pix		
+	FIFO_RDE.CLK = PIXEL_CLK;	
+	FIFO_RDE = (SUB_PIXEL_CNT[6..0]==1 & COLOR1
+			  # SUB_PIXEL_CNT[5..0]==1 & COLOR2 
+			  # SUB_PIXEL_CNT[4..0]==1 & COLOR4 
+			  # SUB_PIXEL_CNT[3..0]==1 & COLOR8 
+			  # SUB_PIXEL_CNT[2..0]==1 & COLOR16 
+			  # SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON
+			  # SYNC_PIX # SYNC_PIX1 # SYNC_PIX2;				-- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
+	
+	CLUT_MUX_ADR[].CLK = PIXEL_CLK;
+	CLUT_MUX_AV[][].CLK = PIXEL_CLK; 
+	CLUT_MUX_AV[0][]  = SUB_PIXEL_CNT[3..0];
+	CLUT_MUX_AV[1][]  = CLUT_MUX_AV[0][];
+	CLUT_MUX_ADR[] = CLUT_MUX_AV[1][];
+END;
diff --git a/FPGA_quartus_GE/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak b/FPGA_quartus_GE/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
new file mode 100644
index 0000000..fda03c9
--- /dev/null
+++ b/FPGA_quartus_GE/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak
@@ -0,0 +1,675 @@
+TITLE "VIDEO MODUSE UND CLUT CONTROL";
+
+-- CREATED BY FREDI ASCHWANDEN
+
+INCLUDE "lpm_bustri_WORD.inc";
+INCLUDE "lpm_bustri_BYT.inc";
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	nRSTO : INPUT;
+	MAIN_CLK : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	nFB_CS3 : INPUT;
+	nFB_WR : INPUT;
+	nFB_OE : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	nFB_BURST : INPUT;
+	FB_ADR[31..0] : INPUT;
+	CLK33M : INPUT;
+	CLK25M : INPUT;
+	BLITTER_RUN : INPUT;
+	CLK_VIDEO : INPUT;
+	VR_D[8..0] : INPUT;
+	VR_BUSY : INPUT;
+	COLOR8 : OUTPUT;
+	ACP_CLUT_RD : OUTPUT;
+	COLOR1 : OUTPUT;
+	FALCON_CLUT_RDH : OUTPUT;
+	FALCON_CLUT_RDL : OUTPUT;
+	FALCON_CLUT_WR[3..0] : OUTPUT;
+	ST_CLUT_RD : OUTPUT;
+	ST_CLUT_WR[1..0] : OUTPUT;
+	CLUT_MUX_ADR[3..0] : OUTPUT;
+	HSYNC : OUTPUT;
+	VSYNC : OUTPUT;
+	nBLANK : OUTPUT;
+	nSYNC : OUTPUT;
+	nPD_VGA : OUTPUT;
+	FIFO_RDE : OUTPUT;
+	COLOR2 : OUTPUT;
+	COLOR4 : OUTPUT;
+	PIXEL_CLK : OUTPUT;
+	CLUT_OFF[3..0] : OUTPUT;
+	BLITTER_ON : OUTPUT;
+	VIDEO_RAM_CTR[15..0] : OUTPUT;
+	VIDEO_MOD_TA : OUTPUT;
+	CCR[23..0] : OUTPUT;
+	CCSEL[2..0] : OUTPUT;
+	ACP_CLUT_WR[3..0] : OUTPUT;
+	INTER_ZEI : OUTPUT;
+	DOP_FIFO_CLR : OUTPUT;
+	VIDEO_RECONFIG : OUTPUT;
+	VR_WR : OUTPUT;
+	VR_RD : OUTPUT;
+	CLR_FIFO : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	CLK17M						:DFF;
+	CLK13M						:DFF;
+	ACP_CLUT_CS					:NODE;
+	ACP_CLUT					:NODE;
+	VIDEO_PLL_CONFIG_CS			:NODE;
+	VR_WR						:DFF;
+	VR_DOUT[8..0]				:DFFE;
+	VR_FRQ[7..0]				:DFFE;
+	VIDEO_PLL_RECONFIG_CS		:NODE;
+	VIDEO_RECONFIG				:DFF;
+	FALCON_CLUT_CS				:NODE;
+	FALCON_CLUT					:NODE;
+	ST_CLUT_CS					:NODE;
+	ST_CLUT						:NODE;
+	FB_B[3..0]					:NODE;
+	FB_16B[1..0]				:NODE;
+	ST_SHIFT_MODE[1..0]			:DFFE;
+	ST_SHIFT_MODE_CS			:NODE;
+	FALCON_SHIFT_MODE[10..0]	:DFFE;
+	FALCON_SHIFT_MODE_CS		:NODE;
+	CLUT_MUX_ADR[3..0]			:DFF;
+	CLUT_MUX_AV[1..0][3..0]		:DFF;
+	ACP_VCTR_CS					:NODE;
+	ACP_VCTR[31..0]				:DFFE;
+	CCR_CS						:NODE;
+	CCR[23..0]					:DFFE;
+	ACP_VIDEO_ON				:NODE;
+	SYS_CTR[6..0]				:DFFE;
+	SYS_CTR_CS					:NODE;
+	VDL_LOF[15..0]				:DFFE;
+	VDL_LOF_CS					:NODE;
+	VDL_LWD[15..0]				:DFFE;
+	VDL_LWD_CS					:NODE;
+-- DIV. CONTROL REGISTER
+	CLUT_TA						:DFF;  			-- BRAUCHT EIN WAITSTAT
+	HSYNC						:DFF;
+	HSYNC_I[7..0]				:DFF;
+	HSY_LEN[7..0]				:DFF;			-- LÄNGE HSYNC PULS IN PIXEL_CLK
+	HSYNC_START					:DFF;
+	LAST						:DFF;			-- LETZTES PIXEL EINER ZEILE ERREICHT
+	VSYNC						:DFF;
+	VSYNC_START					:DFFE;
+	VSYNC_I[2..0]				:DFFE;
+	nBLANK						:DFF;
+	DISP_ON						:DFF;
+	DPO_ZL						:DFFE;
+	DPO_ON						:DFF;
+	DPO_OFF						:DFF;
+	VDTRON						:DFF;
+	VDO_ZL						:DFFE;
+	VDO_ON						:DFF;
+	VDO_OFF						:DFF;
+	VHCNT[11..0]				:DFF;
+	SUB_PIXEL_CNT[6..0]			:DFFE;
+	VVCNT[10..0]				:DFFE;
+	VERZ[2..0][9..0]			:DFF;
+	RAND[6..0]					:DFF;
+	RAND_ON						:NODE;
+	FIFO_RDE					:DFF;
+	CLR_FIFO					:DFFE;
+	START_ZEILE					:DFFE;
+	SYNC_PIX					:DFF;
+	SYNC_PIX1					:DFF;
+	SYNC_PIX2					:DFF;
+	CCSEL[2..0]					:DFF;
+	COLOR16						:NODE;
+	COLOR24						:NODE;
+-- ATARI RESOLUTION
+	ATARI_SYNC					:NODE;	 
+	ATARI_HH[31..0]				:DFFE;		-- HORIZONTAL TIMING 640x480
+	ATARI_HH_CS					:NODE;
+	ATARI_VH[31..0]				:DFFE;		-- VERTIKAL TIMING 640x480 
+	ATARI_VH_CS					:NODE;
+	ATARI_HL[31..0]				:DFFE;		-- HORIZONTAL TIMING 320x240
+	ATARI_HL_CS					:NODE;
+	ATARI_VL[31..0]				:DFFE;		-- VERTIKAL TIMING 320x240
+	ATARI_VL_CS					:NODE;
+-- HORIZONTAL
+	RAND_LINKS[11..0]			:NODE;
+	HDIS_START[11..0]			:NODE;
+	HDIS_END[11..0]				:NODE;  
+	RAND_RECHTS[11..0]			:NODE;
+	HS_START[11..0]				:NODE;
+	H_TOTAL[11..0]				:NODE;
+	HDIS_LEN[11..0]				:NODE;
+	MULF[5..0]					:NODE;
+	VDL_HHT[11..0]				:DFFE;
+	VDL_HHT_CS					:NODE;
+	VDL_HBE[11..0]				:DFFE;
+	VDL_HBE_CS					:NODE;
+	VDL_HDB[11..0]				:DFFE;
+	VDL_HDB_CS					:NODE;
+	VDL_HDE[11..0]				:DFFE;
+	VDL_HDE_CS					:NODE;
+	VDL_HBB[11..0]				:DFFE;
+	VDL_HBB_CS					:NODE;
+	VDL_HSS[11..0]				:DFFE;
+	VDL_HSS_CS					:NODE;
+-- VERTIKAL
+	RAND_OBEN[10..0]			:NODE; 
+	VDIS_START[10..0]			:NODE; 
+	VDIS_END[10..0]				:NODE; 
+	RAND_UNTEN[10..0]			:NODE; 
+	VS_START[10..0]				:NODE; 
+	V_TOTAL[10..0]				:NODE;  
+	FALCON_VIDEO				:NODE;
+	ST_VIDEO					:NODE;
+	INTER_ZEI					:DFF;
+	DOP_ZEI						:DFF;
+	DOP_FIFO_CLR				:DFF;
+	
+	VDL_VBE[10..0]				:DFFE;
+	VDL_VBE_CS					:NODE;
+	VDL_VDB[10..0]				:DFFE;
+	VDL_VDB_CS					:NODE;
+	VDL_VDE[10..0]				:DFFE;
+	VDL_VDE_CS					:NODE;
+	VDL_VBB[10..0]				:DFFE;
+	VDL_VBB_CS					:NODE;
+	VDL_VSS[10..0]				:DFFE;
+	VDL_VSS_CS					:NODE;
+	VDL_VFT[10..0]				:DFFE;
+	VDL_VFT_CS					:NODE;
+	VDL_VCT[8..0]				:DFFE;
+	VDL_VCT_CS					:NODE;
+	VDL_VMD[3..0]				:DFFE;
+	VDL_VMD_CS					:NODE;
+
+BEGIN
+-- BYT SELECT 32 BIT
+	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
+	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+-- BYT SELECT 16 BIT
+	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
+	FB_16B1 = FB_ADR[0]==1									-- ADR==1
+		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
+-- ACP CLUT --
+	ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0";						-- 0-3FF/1024
+	ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
+	ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR;
+	CLUT_TA.CLK = MAIN_CLK;
+	CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA;
+--FALCON CLUT --
+	FALCON_CLUT_CS  = !nFB_CS1 & FB_ADR[19..10]==H"3E6";				-- $F9800/$400
+	FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1;				-- HIGH WORD
+	FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE &  FB_ADR1;				-- LOW WORD
+	FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
+	FALCON_CLUT_WR[3..2] = FB_16B[] &  FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
+-- ST CLUT --
+	ST_CLUT_CS  = !nFB_CS1 & FB_ADR[19..5]==H"7C12";					-- $F8240/$20
+	ST_CLUT_RD  = ST_CLUT_CS & !nFB_OE;
+	ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR;
+-- ST SHIFT MODE
+	ST_SHIFT_MODE[].CLK = MAIN_CLK;
+	ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130";				-- $F8260/2
+	ST_SHIFT_MODE[] = FB_AD[25..24];
+	ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
+	COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
+	COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
+	COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
+-- FALCON SHIFT MODE
+	FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
+	FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133";			-- $F8266/2
+	FALCON_SHIFT_MODE[] = FB_AD[26..16];
+	FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
+	FALCON_SHIFT_MODE[7..0].ENA  = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
+	CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
+	COLOR1  = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR8  = FALCON_SHIFT_MODE4  & !COLOR16           & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR16 = FALCON_SHIFT_MODE8                       & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR4  = !COLOR1             & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
+-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
+	ACP_VCTR[].CLK = MAIN_CLK;
+	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100";						-- $400/4
+	ACP_VCTR[31..8] = FB_AD[31..8];
+	ACP_VCTR[5..0] = FB_AD[5..0];
+	ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
+	ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR;
+	ACP_VCTR[15..8].ENA  = ACP_VCTR_CS & FB_B2 & !nFB_WR;
+	ACP_VCTR[5..0].ENA   = ACP_VCTR_CS & FB_B3 & !nFB_WR;
+	ACP_VIDEO_ON = ACP_VCTR0;
+	nPD_VGA = ACP_VCTR1;
+	-- ATARI MODUS
+	ATARI_SYNC = ACP_VCTR26;			-- WENN 1 AUTOMATISCHE AUFLÖSUNG
+	-- HORIZONTAL TIMING 640x480
+	ATARI_HH[].CLK = MAIN_CLK;
+	ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104";						-- $410/4
+	ATARI_HH[] = FB_AD[];
+	ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
+	ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
+	ATARI_HH[15..8].ENA  = ATARI_HH_CS & FB_B2 & !nFB_WR;
+	ATARI_HH[7..0].ENA   = ATARI_HH_CS & FB_B3 & !nFB_WR;
+	-- VERTIKAL TIMING 640x480
+	ATARI_VH[].CLK = MAIN_CLK;
+	ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105";						-- $414/4
+	ATARI_VH[] = FB_AD[];
+	ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
+	ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
+	ATARI_VH[15..8].ENA  = ATARI_VH_CS & FB_B2 & !nFB_WR;
+	ATARI_VH[7..0].ENA   = ATARI_VH_CS & FB_B3 & !nFB_WR;
+	-- HORIZONTAL TIMING 320x240
+	ATARI_HL[].CLK = MAIN_CLK;
+	ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106";						-- $418/4
+	ATARI_HL[] = FB_AD[];
+	ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
+	ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
+	ATARI_HL[15..8].ENA  = ATARI_HL_CS & FB_B2 & !nFB_WR;
+	ATARI_HL[7..0].ENA   = ATARI_HL_CS & FB_B3 & !nFB_WR;
+	-- VERTIKAL TIMING 320x240
+	ATARI_VL[].CLK = MAIN_CLK;
+	ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107";						-- $41C/4
+	ATARI_VL[] = FB_AD[];
+	ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
+	ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
+	ATARI_VL[15..8].ENA  = ATARI_VL_CS & FB_B2 & !nFB_WR;
+	ATARI_VL[7..0].ENA   = ATARI_VL_CS & FB_B3 & !nFB_WR;
+-- VIDEO PLL CONFIG
+	VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1;	-- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
+	VR_WR.CLK = MAIN_CLK;
+	VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
+	VR_RD = VIDEO_PLL_CONFIG_CS &  nFB_WR & !VR_BUSY;
+	VR_DOUT[].CLK = MAIN_CLK;
+	VR_DOUT[].ENA = !VR_BUSY;
+	VR_DOUT[] = VR_D[];
+	VR_FRQ[].CLK = MAIN_CLK;
+	VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
+	VR_FRQ[] = FB_AD[23..16];
+-- VIDEO PLL RECONFIG
+	VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0;		-- $(F)000'0800 
+	VIDEO_RECONFIG.CLK = MAIN_CLK;
+	VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
+------------------------------------------------------------------------------------------------------------------------
+	VIDEO_RAM_CTR[] = ACP_VCTR[31..16];
+-------------- COLOR MODE IM ACP SETZEN	
+	COLOR1   = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
+	COLOR8   = 			    ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
+	COLOR16  = 				   		     ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
+	COLOR24  = 										  ACP_VCTR2 & ACP_VIDEO_ON;
+	ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
+-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
+	ACP_VCTR7          = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
+	ACP_VCTR6          = ST_SHIFT_MODE_CS     & !nFB_WR & !ACP_VIDEO_ON;
+	ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
+	FALCON_VIDEO	   = ACP_VCTR7;
+	FALCON_CLUT        = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
+	ST_VIDEO		   = ACP_VCTR6;
+	ST_CLUT            = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1;
+	CCSEL[].CLK = PIXEL_CLK;
+	CCSEL[] = B"000" & ST_CLUT				-- ONLY FOR INFORMATION
+			# B"001" & FALCON_CLUT
+			# B"100" & ACP_CLUT
+			# B"101" & COLOR16
+			# B"110" & COLOR24
+			# B"111" & RAND_ON;
+-- DIVERSE (VIDEO)-REGISTER ----------------------------
+-- RANDFARBE
+	CCR[].CLK = MAIN_CLK;
+	CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101";						-- $404/4
+	CCR[] = FB_AD[23..0];
+	CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
+	CCR[15..8].ENA  = CCR_CS & FB_B2 & !nFB_WR;
+	CCR[7..0].ENA   = CCR_CS & FB_B3 & !nFB_WR;
+--SYS CTR
+	SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003";						-- $8006/2
+	SYS_CTR[].CLK = MAIN_CLK;
+	SYS_CTR[6..0] = FB_AD[22..16];
+	SYS_CTR[6..0].ENA  = SYS_CTR_CS & !nFB_WR & FB_B3;
+	BLITTER_ON = !SYS_CTR3;
+--VDL_LOF
+	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $820E/2
+	VDL_LOF[].CLK = MAIN_CLK;
+	VDL_LOF[] = FB_AD[31..16];
+	VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
+	VDL_LOF[7..0].ENA  = VDL_LOF_CS & !nFB_WR & FB_B3;
+--VDL_LWD
+	VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108";						-- $8210/2
+	VDL_LWD[].CLK = MAIN_CLK;
+	VDL_LWD[] = FB_AD[31..16];
+	VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
+	VDL_LWD[7..0].ENA  = VDL_LWD_CS & !nFB_WR & FB_B1;
+-- HORIZONTAL
+-- VDL_HHT
+	VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141";						-- $8282/2
+	VDL_HHT[].CLK = MAIN_CLK;
+	VDL_HHT[] = FB_AD[27..16];
+	VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
+	VDL_HHT[7..0].ENA  = VDL_HHT_CS & !nFB_WR & FB_B3;
+-- VDL_HBE
+	VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143";						-- $8286/2
+	VDL_HBE[].CLK = MAIN_CLK;
+	VDL_HBE[] = FB_AD[27..16];
+	VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
+	VDL_HBE[7..0].ENA  = VDL_HBE_CS & !nFB_WR & FB_B3;
+-- VDL_HDB
+	VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144";						-- $8288/2
+	VDL_HDB[].CLK = MAIN_CLK;
+	VDL_HDB[] = FB_AD[27..16];
+	VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
+	VDL_HDB[7..0].ENA  = VDL_HDB_CS & !nFB_WR & FB_B1;
+-- VDL_HDE
+	VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145";						-- $828A/2
+	VDL_HDE[].CLK = MAIN_CLK;
+	VDL_HDE[] = FB_AD[27..16];
+	VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
+	VDL_HDE[7..0].ENA  = VDL_HDE_CS & !nFB_WR & FB_B3;
+-- VDL_HBB
+	VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142";						-- $8284/2
+	VDL_HBB[].CLK = MAIN_CLK;
+	VDL_HBB[] = FB_AD[27..16];
+	VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
+	VDL_HBB[7..0].ENA  = VDL_HBB_CS & !nFB_WR & FB_B1;
+-- VDL_HSS
+	VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146";						-- $828C/2
+	VDL_HSS[].CLK = MAIN_CLK;
+	VDL_HSS[] = FB_AD[27..16];
+	VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
+	VDL_HSS[7..0].ENA  = VDL_HSS_CS & !nFB_WR & FB_B1;
+-- VERTIKAL
+-- VDL_VBE
+	VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153";						-- $82A6/2
+	VDL_VBE[].CLK = MAIN_CLK;
+	VDL_VBE[] = FB_AD[26..16];
+	VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
+	VDL_VBE[7..0].ENA  = VDL_VBE_CS & !nFB_WR & FB_B3;
+-- VDL_VDB
+	VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154";						-- $82A8/2
+	VDL_VDB[].CLK = MAIN_CLK;
+	VDL_VDB[] = FB_AD[26..16];
+	VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
+	VDL_VDB[7..0].ENA  = VDL_VDB_CS & !nFB_WR & FB_B1;
+-- VDL_VDE
+	VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155";						-- $82AA/2
+	VDL_VDE[].CLK = MAIN_CLK;
+	VDL_VDE[] = FB_AD[26..16];
+	VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
+	VDL_VDE[7..0].ENA  = VDL_VDE_CS & !nFB_WR & FB_B3;
+-- VDL_VBB
+	VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152";						-- $82A4/2
+	VDL_VBB[].CLK = MAIN_CLK;
+	VDL_VBB[] = FB_AD[26..16];
+	VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
+	VDL_VBB[7..0].ENA  = VDL_VBB_CS & !nFB_WR & FB_B1;
+-- VDL_VSS
+	VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156";						-- $82AC/2
+	VDL_VSS[].CLK = MAIN_CLK;
+	VDL_VSS[] = FB_AD[26..16];
+	VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
+	VDL_VSS[7..0].ENA  = VDL_VSS_CS & !nFB_WR & FB_B1;
+-- VDL_VFT
+	VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151";						-- $82A2/2
+	VDL_VFT[].CLK = MAIN_CLK;
+	VDL_VFT[] = FB_AD[26..16];
+	VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
+	VDL_VFT[7..0].ENA  = VDL_VFT_CS & !nFB_WR & FB_B3;
+-- VDL_VCT
+	VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160";						-- $82C0/2
+	VDL_VCT[].CLK = MAIN_CLK;
+	VDL_VCT[] = FB_AD[24..16];
+	VDL_VCT[8].ENA 		= VDL_VCT_CS & !nFB_WR & FB_B0;
+	VDL_VCT[7..0].ENA  	= VDL_VCT_CS & !nFB_WR & FB_B1;
+-- VDL_VMD
+	VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161";						-- $82C2/2
+	VDL_VMD[].CLK = MAIN_CLK;
+	VDL_VMD[] = FB_AD[19..16];
+	VDL_VMD[3..0].ENA  	= VDL_VMD_CS & !nFB_WR & FB_B3;
+--- REGISTER OUT
+	FB_AD[31..16] = lpm_bustri_WORD(
+						ST_SHIFT_MODE_CS 		& (0,ST_SHIFT_MODE[],B"00000000") 
+					  #	FALCON_SHIFT_MODE_CS 	& (0,FALCON_SHIFT_MODE[])
+					  # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0])	 
+					  # VDL_LOF_CS & VDL_LOF[]
+					  # VDL_LWD_CS & VDL_LWD[]
+					  #	VDL_HBE_CS & (0,VDL_HBE[])
+					  #	VDL_HDB_CS & (0,VDL_HDB[])
+					  #	VDL_HDE_CS & (0,VDL_HDE[])
+					  #	VDL_HBB_CS & (0,VDL_HBB[])
+					  #	VDL_HSS_CS & (0,VDL_HSS[])
+					  #	VDL_HHT_CS & (0,VDL_HHT[])
+					  #	VDL_VBE_CS & (0,VDL_VBE[])
+					  #	VDL_VDB_CS & (0,VDL_VDB[])
+					  #	VDL_VDE_CS & (0,VDL_VDE[])
+					  #	VDL_VBB_CS & (0,VDL_VBB[])
+					  #	VDL_VSS_CS & (0,VDL_VSS[])
+					  #	VDL_VFT_CS & (0,VDL_VFT[])
+					  #	VDL_VCT_CS & (0,VDL_VCT[])			 
+					  #	VDL_VMD_CS & (0,VDL_VMD[])
+ 					  #	ACP_VCTR_CS & ACP_VCTR[31..16]
+ 					  #	ATARI_HH_CS & ATARI_HH[31..16]
+					  #	ATARI_VH_CS & ATARI_VH[31..16]
+					  #	ATARI_HL_CS & ATARI_HL[31..16]
+					  #	ATARI_VL_CS & ATARI_VL[31..16]
+					  #	CCR_CS & (0,CCR[23..16])
+ 					  #	VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
+ 					  #	VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
+					  ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
+					 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS 
+					 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
+					 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE);
+
+ 	FB_AD[15..0] = lpm_bustri_WORD(
+ 					   	ACP_VCTR_CS & ACP_VCTR[15..0]
+					  #	ATARI_HH_CS & ATARI_HH[15..0]
+					  #	ATARI_VH_CS & ATARI_VH[15..0]
+					  #	ATARI_HL_CS & ATARI_HL[15..0]
+					  #	ATARI_VL_CS & ATARI_VL[15..0]
+ 					  #	CCR_CS & CCR[15..0]
+ 					  ,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
+
+	VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS 
+			   	 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
+				 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
+				 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
+	
+-- VIDEO AUSGABE SETZEN
+	CLK17M.CLK = CLK33M;
+	CLK17M = !CLK17M;
+	CLK13M.CLK = CLK25M;
+	CLK13M = !CLK13M;
+	PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0) 
+			#	CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
+			#	CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
+			#	CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
+			#	CLK25M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	CLK33M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#	CLK_VIDEO  & ACP_VIDEO_ON & ACP_VCTR[9];
+--------------------------------------------------------------
+-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK
+----------------------------------------------------------------
+	HSY_LEN[].CLK = MAIN_CLK;		
+	HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0)
+			#	16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
+			#	28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
+			#	32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
+			#	28 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	32 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#   16 + (0,VR_FRQ[7..1]) &  ACP_VIDEO_ON & ACP_VCTR[9];			-- hsync puls length in pixeln=frequenz/ = 500ns
+
+ 	MULF[] =  2  & !ST_VIDEO &  VDL_VMD2						-- MULTIPLIKATIONS FAKTOR
+			# 4  & !ST_VIDEO & !VDL_VMD2
+			# 16 &  ST_VIDEO &  VDL_VMD2
+			# 32 &  ST_VIDEO & !VDL_VMD2;
+	 	
+	 	
+	HDIS_LEN[] =  320 &  VDL_VMD2								-- BREITE IN PIXELN
+			   #  640 & !VDL_VMD2;
+					
+-- DOPPELZEILENMODUS
+	DOP_ZEI.CLK = MAIN_CLK;
+	DOP_ZEI = VDL_VMD0 & ST_VIDEO;								-- ZEILENVERDOPPELUNG EIN AUS
+	INTER_ZEI.CLK = PIXEL_CLK;
+	INTER_ZEI =  DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) 	    -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
+	          #  DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); 		-- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
+	DOP_FIFO_CLR.CLK = PIXEL_CLK;
+	DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX;				-- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
+					
+	RAND_LINKS[] 	=  VDL_HBE[] 									&  ACP_VIDEO_ON
+					#  21											& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  42											& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					#  VDL_HBE[] * (0,MULF[5..1])					& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
+	HDIS_START[] 	=  VDL_HDB[] 									&  ACP_VIDEO_ON
+					#  RAND_LINKS[]+1 								& !ACP_VIDEO_ON;						--  
+	HDIS_END[]	 	=  VDL_HDE[] 									&  ACP_VIDEO_ON
+					#  RAND_LINKS[]+HDIS_LEN[]						& !ACP_VIDEO_ON; 						--  
+	RAND_RECHTS[] 	=  VDL_HBB[] 									&  ACP_VIDEO_ON
+					#  HDIS_END[]+1									& !ACP_VIDEO_ON; 						--  
+	HS_START[]		=  VDL_HSS[] 									&  ACP_VIDEO_ON
+					#  ATARI_HL[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_HH[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1])		& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
+	H_TOTAL[] 		=  VDL_HHT[] 									&  ACP_VIDEO_ON
+					#  ATARI_HL[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_HH[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (VDL_HHT[]+2) * (0,MULF[])	 				& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
+					
+	RAND_OBEN[]		=  VDL_VBE[]					&  ACP_VIDEO_ON
+					#  31							& !ACP_VIDEO_ON &  ATARI_SYNC 
+					# (0,VDL_VBE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
+	VDIS_START[]	=  VDL_VDB[]					&  ACP_VIDEO_ON
+					#  32							& !ACP_VIDEO_ON &  ATARI_SYNC 
+					# (0,VDL_VDB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
+	VDIS_END[]		=  VDL_VDE[]					&  ACP_VIDEO_ON
+					#  431							& !ACP_VIDEO_ON &  ATARI_SYNC &  ST_VIDEO
+					#  511							& !ACP_VIDEO_ON &  ATARI_SYNC & !ST_VIDEO
+					# (0,VDL_VDE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
+	RAND_UNTEN[]	=  VDL_VBB[]					&  ACP_VIDEO_ON
+					#  VDIS_END[]+1					& !ACP_VIDEO_ON &  ATARI_SYNC 
+					# (0,VDL_VBB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC;  
+	VS_START[]		=  VDL_VSS[]					&  ACP_VIDEO_ON
+					#  ATARI_VL[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_VH[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (0,VDL_VSS[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
+	V_TOTAL[] 		=  VDL_VFT[]					&  ACP_VIDEO_ON
+					#  ATARI_VL[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_VH[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (0,VDL_VFT[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
+-- ZÄHLER
+	LAST.CLK = PIXEL_CLK;
+	LAST = VHCNT[]==(H_TOTAL[]-2);
+	VHCNT[].CLK = PIXEL_CLK;
+	VHCNT[] = (VHCNT[] + 1) & !LAST;
+	VVCNT[].CLK = PIXEL_CLK;
+	VVCNT[].ENA = LAST;
+	VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
+-- DISPLAY ON OFF
+	DPO_ZL.CLK = PIXEL_CLK;
+	DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1);	-- 1 ZEILE DAVOR ON OFF
+	DPO_ZL.ENA = LAST;												-- AM ZEILENENDE ÜBERNEHMEN
+	DPO_ON.CLK = PIXEL_CLK;
+	DPO_ON = VHCNT[]==RAND_LINKS[];									-- BESSER EINZELN WEGEN TIMING
+	DPO_OFF.CLK = PIXEL_CLK;
+	DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1);
+	DISP_ON.CLK = PIXEL_CLK;
+	DISP_ON = DISP_ON & !DPO_OFF 
+			# DPO_ON & DPO_ZL;
+-- DATENTRANSFER ON OFF
+	VDO_ON.CLK = PIXEL_CLK;
+	VDO_ON = VHCNT[]==(HDIS_START[]-1);								-- BESSER EINZELN WEGEN TIMING
+	VDO_OFF.CLK = PIXEL_CLK;
+	VDO_OFF = VHCNT[]==HDIS_END[];
+	VDO_ZL.CLK = PIXEL_CLK;
+	VDO_ZL.ENA = LAST;												-- AM ZEILENENDE ÜBERNEHMEN
+	VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]);	-- 1 ZEILE DAVOR ON OFF
+	VDTRON.CLK = PIXEL_CLK;
+	VDTRON = VDTRON & !VDO_OFF
+		   # VDO_ON & VDO_ZL;
+-- VERZÖGERUNG UND SYNC	
+	HSYNC_START.CLK = PIXEL_CLK;
+	HSYNC_START = VHCNT[]==HS_START[]-3;
+	HSYNC_I[].CLK = PIXEL_CLK;
+	HSYNC_I[] = HSY_LEN[]    &  HSYNC_START
+			 # (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
+	VSYNC_START.CLK = PIXEL_CLK;
+	VSYNC_START.ENA = LAST;
+	VSYNC_START = VVCNT[]==(VS_START[]-3);						-- start am ende der Zeile vor dem vsync		
+	VSYNC_I[].CLK = PIXEL_CLK;
+	VSYNC_I[].ENA = LAST;										-- start am ende der Zeile vor dem vsync
+	VSYNC_I[] =   3 	    &  VSYNC_START						-- 3 zeilen vsync length
+			# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0;		-- runterzählen bis 0
+	VERZ[][].CLK = PIXEL_CLK;
+	VERZ[][1] = VERZ[][0];
+	VERZ[][2] = VERZ[][1];
+	VERZ[][3] = VERZ[][2];
+	VERZ[][4] = VERZ[][3];
+	VERZ[][5] = VERZ[][4];
+	VERZ[][6] = VERZ[][5];
+	VERZ[][7] = VERZ[][6];
+	VERZ[][8] = VERZ[][7];
+	VERZ[][9] = VERZ[][8];
+	VERZ[0][0] = DISP_ON;
+	VERZ[1][0] = HSYNC_I[]!=0;
+	VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
+				#  ACP_VCTR15 &  VDL_VCT6  & HSYNC_I[]==0;		-- NUR MÖGLICH WENN BEIDE
+	VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
+				#  ACP_VCTR15 &  VDL_VCT5  & VSYNC_I[]==0;		-- NUR MÖGLICH WENN BEIDE
+	nBLANK.CLK = PIXEL_CLK;
+	nBLANK =  VERZ[0][8];
+	HSYNC.CLK = PIXEL_CLK;
+	HSYNC  =  VERZ[1][9];
+	VSYNC.CLK = PIXEL_CLK;
+	VSYNC  =  VERZ[2][9];
+	nSYNC  = GND;
+-- RANDFARBE MACHEN ------------------------------------
+	RAND[].CLK = PIXEL_CLK;
+	RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
+	RAND[1] = RAND[0];
+	RAND[2] = RAND[1];
+	RAND[3] = RAND[2];
+	RAND[4] = RAND[3];
+	RAND[5] = RAND[4];
+	RAND[6] = RAND[5];
+	RAND_ON = RAND[6];
+----------------------------------------------------------
+	CLR_FIFO.CLK = PIXEL_CLK;
+	CLR_FIFO.ENA = LAST;
+	CLR_FIFO = VVCNT[]==V_TOTAL[]-2;								-- IN LETZTER ZEILE LÖSCHEN
+	START_ZEILE.CLK = PIXEL_CLK;
+	START_ZEILE.ENA = LAST;
+	START_ZEILE = VVCNT[]==0;										-- ZEILE 1
+	SYNC_PIX.CLK = PIXEL_CLK;
+	SYNC_PIX  = VHCNT[]==1 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SYNC_PIX1.CLK = PIXEL_CLK;
+	SYNC_PIX1 = VHCNT[]==3 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SYNC_PIX2.CLK = PIXEL_CLK;
+	SYNC_PIX2 = VHCNT[]==5 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
+	SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
+	SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX;			--count up if display on sonst clear bei sync pix		
+	FIFO_RDE.CLK = PIXEL_CLK;	
+	FIFO_RDE = (SUB_PIXEL_CNT[6..0]==1 & COLOR1
+			  # SUB_PIXEL_CNT[5..0]==1 & COLOR2 
+			  # SUB_PIXEL_CNT[4..0]==1 & COLOR4 
+			  # SUB_PIXEL_CNT[3..0]==1 & COLOR8 
+			  # SUB_PIXEL_CNT[2..0]==1 & COLOR16 
+			  # SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON
+			  # SYNC_PIX # SYNC_PIX1 # SYNC_PIX2;				-- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
+	
+	CLUT_MUX_ADR[].CLK = PIXEL_CLK;
+	CLUT_MUX_AV[][].CLK = PIXEL_CLK; 
+	CLUT_MUX_AV[0][]  = SUB_PIXEL_CNT[3..0];
+	CLUT_MUX_AV[1][]  = CLUT_MUX_AV[0][];
+	CLUT_MUX_ADR[] = CLUT_MUX_AV[1][];
+END;
diff --git a/FPGA_quartus_GE/Video/VIDEO_MOD_MUX_CLUTCTR.v b/FPGA_quartus_GE/Video/VIDEO_MOD_MUX_CLUTCTR.v
new file mode 100644
index 0000000..cda30e2
--- /dev/null
+++ b/FPGA_quartus_GE/Video/VIDEO_MOD_MUX_CLUTCTR.v
@@ -0,0 +1,1500 @@
+// Xilinx XPort Language Converter, Version 4.1 (110)
+// 
+// AHDL    Design Source: VIDEO_MOD_MUX_CLUTCTR.tdf
+// Verilog Design Output: VIDEO_MOD_MUX_CLUTCTR.v
+// Created 02-Mar-2014 04:36 PM
+//
+// Copyright (c) 2014, Xilinx, Inc.  All Rights Reserved.
+// Xilinx Inc makes no warranty, expressed or implied, with respect to
+// the operation and/or functionality of the converted output files.
+// 
+
+// VIDEO MODUSE UND CLUT CONTROL
+
+
+//  CREATED BY FREDI ASCHWANDEN
+//  GE http://quartushelp.altera.com/current/mergedProjects/hdl/ahdl/ahdl_elements_arithmetic_operators.htm
+//  {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+//  {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+module VIDEO_MOD_MUX_CLUTCTR(nRSTO, MAIN_CLK, nFB_CS1, nFB_CS2, nFB_CS3,
+      nFB_WR, nFB_OE, FB_SIZE0, FB_SIZE1, nFB_BURST, FB_ADR, CLK33M, CLK25M,
+      BLITTER_RUN, CLK_VIDEO, VR_D, VR_BUSY, COLOR8, ACP_CLUT_RD, COLOR1,
+      FALCON_CLUT_RDH, FALCON_CLUT_RDL, FALCON_CLUT_WR, ST_CLUT_RD, ST_CLUT_WR,
+      CLUT_MUX_ADR, HSYNC, VSYNC, nBLANK, nSYNC, nPD_VGA, FIFO_RDE, COLOR2,
+      COLOR4, PIXEL_CLK, CLUT_OFF, BLITTER_ON, VIDEO_RAM_CTR, VIDEO_MOD_TA,
+      CCR, CCSEL, ACP_CLUT_WR, INTER_ZEI, DOP_FIFO_CLR, VIDEO_RECONFIG, VR_WR,
+      VR_RD, CLR_FIFO, FB_AD);
+
+//  {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+//  {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+   input nRSTO, MAIN_CLK, nFB_CS1, nFB_CS2, nFB_CS3, nFB_WR, nFB_OE, FB_SIZE0,
+	 FB_SIZE1, nFB_BURST;
+   input [31:0] FB_ADR;
+   input CLK33M, CLK25M, BLITTER_RUN, CLK_VIDEO;
+   input [8:0] VR_D;
+   input VR_BUSY;
+   output COLOR8, ACP_CLUT_RD, COLOR1, FALCON_CLUT_RDH, FALCON_CLUT_RDL;
+   output [3:0] FALCON_CLUT_WR;
+   output ST_CLUT_RD;
+   output [1:0] ST_CLUT_WR;
+   output [3:0] CLUT_MUX_ADR;
+   output HSYNC, VSYNC, nBLANK, nSYNC, nPD_VGA, FIFO_RDE, COLOR2, COLOR4,
+	 PIXEL_CLK;
+   output [3:0] CLUT_OFF;
+   output BLITTER_ON;
+   output [15:0] VIDEO_RAM_CTR;
+   output VIDEO_MOD_TA;
+   output [23:0] CCR;
+   output [2:0] CCSEL;
+   output [3:0] ACP_CLUT_WR;
+   output INTER_ZEI, DOP_FIFO_CLR, VIDEO_RECONFIG, VR_WR, VR_RD, CLR_FIFO;
+   inout [31:0] FB_AD;
+
+//  DIV. CONTROL REGISTER
+//  BRAUCHT EIN WAITSTAT
+//  LÄNGE HSYNC PULS IN PIXEL_CLK
+//  LETZTES PIXEL EINER ZEILE ERREICHT
+//  ATARI RESOLUTION
+//  HORIZONTAL TIMING 640x480
+//  VERTIKAL TIMING 640x480
+//  HORIZONTAL TIMING 320x240
+//  VERTIKAL TIMING 320x240
+//  HORIZONTAL
+//  GE
+//  GE
+//  GE
+//  VERTIKAL
+   wire CLK17M, CLK17M_d, CLK17M_clk, CLK13M, CLK13M_d, CLK13M_clk,
+	 ACP_CLUT_CS, ACP_CLUT, VIDEO_PLL_CONFIG_CS, VR_WR_d, VR_WR_clk;
+   wire [8:0] VR_DOUT;
+   wire [8:0] VR_DOUT_d;
+   wire [7:0] VR_FRQ;
+   wire [7:0] VR_FRQ_d;
+   wire VIDEO_PLL_RECONFIG_CS, VIDEO_RECONFIG_d, VIDEO_RECONFIG_clk,
+	 FALCON_CLUT_CS, FALCON_CLUT, ST_CLUT_CS, ST_CLUT;
+   wire [3:0] FB_B;
+   wire [1:0] FB_16B;
+   wire [1:0] ST_SHIFT_MODE;
+   wire [1:0] ST_SHIFT_MODE_d;
+   wire ST_SHIFT_MODE_CS;
+   wire [10:0] FALCON_SHIFT_MODE;
+   wire [10:0] FALCON_SHIFT_MODE_d;
+   wire FALCON_SHIFT_MODE_CS;
+   wire [3:0] CLUT_MUX_ADR_d;
+   wire [3:0] CLUT_MUX_AV1_;
+   wire [3:0] CLUT_MUX_AV1__d;
+   wire [3:0] CLUT_MUX_AV0_;
+   wire [3:0] CLUT_MUX_AV0__d;
+   wire ACP_VCTR_CS;
+   wire [31:0] ACP_VCTR;
+   wire [31:0] ACP_VCTR_d;
+   wire CCR_CS;
+   wire [23:0] CCR_d;
+   wire ACP_VIDEO_ON;
+   wire [6:0] SYS_CTR;
+   wire [6:0] SYS_CTR_d;
+   wire SYS_CTR_CS;
+   wire [15:0] VDL_LOF;
+   wire [15:0] VDL_LOF_d;
+   wire VDL_LOF_CS;
+   wire [15:0] VDL_LWD;
+   wire [15:0] VDL_LWD_d;
+   wire VDL_LWD_CS, CLUT_TA, CLUT_TA_d, CLUT_TA_clk, HSYNC_d, HSYNC_clk;
+   wire [7:0] HSYNC_I;
+   wire [7:0] HSYNC_I_d;
+   wire [7:0] HSY_LEN;
+   wire [7:0] HSY_LEN_d;
+   wire HSYNC_START, HSYNC_START_d, HSYNC_START_clk, LAST, LAST_d, LAST_clk,
+	 VSYNC_d, VSYNC_clk, VSYNC_START, VSYNC_START_d, VSYNC_START_clk,
+	 VSYNC_START_ena;
+   wire [2:0] VSYNC_I;
+   wire [2:0] VSYNC_I_d;
+   wire nBLANK_d, nBLANK_clk, DISP_ON, DISP_ON_d, DISP_ON_clk, DPO_ZL,
+	 DPO_ZL_d, DPO_ZL_clk, DPO_ZL_ena, DPO_ON, DPO_ON_d, DPO_ON_clk,
+	 DPO_OFF, DPO_OFF_d, DPO_OFF_clk, VDTRON, VDTRON_d, VDTRON_clk, VDO_ZL,
+	 VDO_ZL_d, VDO_ZL_clk, VDO_ZL_ena, VDO_ON, VDO_ON_d, VDO_ON_clk,
+	 VDO_OFF, VDO_OFF_d, VDO_OFF_clk;
+   wire [11:0] VHCNT;
+   wire [11:0] VHCNT_d;
+   wire [6:0] SUB_PIXEL_CNT;
+   wire [6:0] SUB_PIXEL_CNT_d;
+   wire [10:0] VVCNT;
+   wire [10:0] VVCNT_d;
+   wire [9:0] VERZ2_;
+   wire [9:0] VERZ2__d;
+   wire [9:0] VERZ1_;
+   wire [9:0] VERZ1__d;
+   wire [9:0] VERZ0_;
+   wire [9:0] VERZ0__d;
+   wire [6:0] RAND;
+   wire [6:0] RAND_d;
+   wire RAND_ON, FIFO_RDE_d, FIFO_RDE_clk, CLR_FIFO_d, CLR_FIFO_clk,
+	 CLR_FIFO_ena, START_ZEILE, START_ZEILE_d, START_ZEILE_clk,
+	 START_ZEILE_ena, SYNC_PIX, SYNC_PIX_d, SYNC_PIX_clk, SYNC_PIX1,
+	 SYNC_PIX1_d, SYNC_PIX1_clk, SYNC_PIX2, SYNC_PIX2_d, SYNC_PIX2_clk;
+   wire [2:0] CCSEL_d;
+   wire COLOR16, COLOR24, ATARI_SYNC;
+   wire [31:0] ATARI_HH;
+   wire [31:0] ATARI_HH_d;
+   wire ATARI_HH_CS;
+   wire [31:0] ATARI_VH;
+   wire [31:0] ATARI_VH_d;
+   wire ATARI_VH_CS;
+   wire [31:0] ATARI_HL;
+   wire [31:0] ATARI_HL_d;
+   wire ATARI_HL_CS;
+   wire [31:0] ATARI_VL;
+   wire [31:0] ATARI_VL_d;
+   wire ATARI_VL_CS;
+   wire [11:0] RAND_LINKS;
+   wire [23:0] RAND_LINKS_FULL;
+   wire [11:0] HDIS_START;
+   wire [11:0] HDIS_END;
+   wire [11:0] RAND_RECHTS;
+   wire [11:0] HS_START;
+   wire [23:0] HS_START_FULL;
+   wire [11:0] H_TOTAL;
+   wire [23:0] H_TOTAL_FULL;
+   wire [11:0] HDIS_LEN;
+   wire [5:0] MULF;
+   wire [11:0] VDL_HHT;
+   wire [11:0] VDL_HHT_d;
+   wire VDL_HHT_CS;
+   wire [11:0] VDL_HBE;
+   wire [11:0] VDL_HBE_d;
+   wire VDL_HBE_CS;
+   wire [11:0] VDL_HDB;
+   wire [11:0] VDL_HDB_d;
+   wire VDL_HDB_CS;
+   wire [11:0] VDL_HDE;
+   wire [11:0] VDL_HDE_d;
+   wire VDL_HDE_CS;
+   wire [11:0] VDL_HBB;
+   wire [11:0] VDL_HBB_d;
+   wire VDL_HBB_CS;
+   wire [11:0] VDL_HSS;
+   wire [11:0] VDL_HSS_d;
+   wire VDL_HSS_CS;
+   wire [10:0] RAND_OBEN;
+   wire [10:0] VDIS_START;
+   wire [10:0] VDIS_END;
+   wire [10:0] RAND_UNTEN;
+   wire [10:0] VS_START;
+   wire [10:0] V_TOTAL;
+   wire FALCON_VIDEO, ST_VIDEO, INTER_ZEI_d, INTER_ZEI_clk, DOP_ZEI, DOP_ZEI_d,
+	 DOP_ZEI_clk, DOP_FIFO_CLR_d, DOP_FIFO_CLR_clk;
+   wire [10:0] VDL_VBE;
+   wire [10:0] VDL_VBE_d;
+   wire VDL_VBE_CS;
+   wire [10:0] VDL_VDB;
+   wire [10:0] VDL_VDB_d;
+   wire VDL_VDB_CS;
+   wire [10:0] VDL_VDE;
+   wire [10:0] VDL_VDE_d;
+   wire VDL_VDE_CS;
+   wire [10:0] VDL_VBB;
+   wire [10:0] VDL_VBB_d;
+   wire VDL_VBB_CS;
+   wire [10:0] VDL_VSS;
+   wire [10:0] VDL_VSS_d;
+   wire VDL_VSS_CS;
+   wire [10:0] VDL_VFT;
+   wire [10:0] VDL_VFT_d;
+   wire VDL_VFT_CS;
+   wire [8:0] VDL_VCT;
+   wire [8:0] VDL_VCT_d;
+   wire VDL_VCT8_ena, VDL_VCT_CS;
+   wire [3:0] VDL_VMD;
+   wire [3:0] VDL_VMD_d;
+   wire VDL_VMD_CS;
+   wire [15:0] u0_data;
+   wire u0_enabledt;
+   wire [15:0] u0_tridata;
+   wire [15:0] u1_data;
+   wire u1_enabledt;
+   wire [15:0] u1_tridata;
+   wire gnd, COLOR16_1, COLOR16_2, VERZ1_0_d_1, VERZ1_0_d_2, COLOR4_1,
+	 COLOR4_2, COLOR1_1, COLOR1_2, COLOR1_3, COLOR8_1, COLOR8_2,
+	 CLUT_MUX_AV0_0_clk_ctrl, CLUT_MUX_AV1_0_clk_ctrl,
+	 CLUT_MUX_ADR0_clk_ctrl, SUB_PIXEL_CNT0_ena_ctrl,
+	 SUB_PIXEL_CNT0_clk_ctrl, RAND0_clk_ctrl, VERZ0_0_clk_ctrl,
+	 VERZ1_0_clk_ctrl, VERZ2_0_clk_ctrl, VSYNC_I0_ena_ctrl,
+	 VSYNC_I0_clk_ctrl, HSYNC_I0_clk_ctrl, VVCNT0_ena_ctrl,
+	 VVCNT0_clk_ctrl, VHCNT0_clk_ctrl, HSY_LEN0_clk_ctrl,
+	 VDL_VMD0_ena_ctrl, VDL_VMD0_clk_ctrl, VDL_VCT0_ena_ctrl,
+	 VDL_VCT0_clk_ctrl, VDL_VFT0_ena_ctrl, VDL_VFT8_ena_ctrl,
+	 VDL_VFT0_clk_ctrl, VDL_VSS0_ena_ctrl, VDL_VSS8_ena_ctrl,
+	 VDL_VSS0_clk_ctrl, VDL_VBB0_ena_ctrl, VDL_VBB8_ena_ctrl,
+	 VDL_VBB0_clk_ctrl, VDL_VDE0_ena_ctrl, VDL_VDE8_ena_ctrl,
+	 VDL_VDE0_clk_ctrl, VDL_VDB0_ena_ctrl, VDL_VDB8_ena_ctrl,
+	 VDL_VDB0_clk_ctrl, VDL_VBE0_ena_ctrl, VDL_VBE8_ena_ctrl,
+	 VDL_VBE0_clk_ctrl, VDL_HSS0_ena_ctrl, VDL_HSS8_ena_ctrl,
+	 VDL_HSS0_clk_ctrl, VDL_HBB0_ena_ctrl, VDL_HBB8_ena_ctrl,
+	 VDL_HBB0_clk_ctrl, VDL_HDE0_ena_ctrl, VDL_HDE8_ena_ctrl,
+	 VDL_HDE0_clk_ctrl, VDL_HDB0_ena_ctrl, VDL_HDB8_ena_ctrl,
+	 VDL_HDB0_clk_ctrl, VDL_HBE0_ena_ctrl, VDL_HBE8_ena_ctrl,
+	 VDL_HBE0_clk_ctrl, VDL_HHT0_ena_ctrl, VDL_HHT8_ena_ctrl,
+	 VDL_HHT0_clk_ctrl, VDL_LWD0_ena_ctrl, VDL_LWD8_ena_ctrl,
+	 VDL_LWD0_clk_ctrl, VDL_LOF0_ena_ctrl, VDL_LOF8_ena_ctrl,
+	 VDL_LOF0_clk_ctrl, SYS_CTR0_ena_ctrl, SYS_CTR0_clk_ctrl,
+	 CCR0_ena_ctrl, CCR8_ena_ctrl, CCR16_ena_ctrl, CCR0_clk_ctrl,
+	 CCSEL0_clk_ctrl, ACP_VCTR6_ena_ctrl, VR_FRQ0_ena_ctrl,
+	 VR_FRQ0_clk_ctrl, VR_DOUT0_ena_ctrl, VR_DOUT0_clk_ctrl,
+	 ATARI_VL0_ena_ctrl, ATARI_VL8_ena_ctrl, ATARI_VL16_ena_ctrl,
+	 ATARI_VL24_ena_ctrl, ATARI_VL0_clk_ctrl, ATARI_HL0_ena_ctrl,
+	 ATARI_HL8_ena_ctrl, ATARI_HL16_ena_ctrl, ATARI_HL24_ena_ctrl,
+	 ATARI_HL0_clk_ctrl, ATARI_VH0_ena_ctrl, ATARI_VH8_ena_ctrl,
+	 ATARI_VH16_ena_ctrl, ATARI_VH24_ena_ctrl, ATARI_VH0_clk_ctrl,
+	 ATARI_HH0_ena_ctrl, ATARI_HH8_ena_ctrl, ATARI_HH16_ena_ctrl,
+	 ATARI_HH24_ena_ctrl, ATARI_HH0_clk_ctrl, ACP_VCTR0_ena_ctrl,
+	 ACP_VCTR8_ena_ctrl, ACP_VCTR16_ena_ctrl, ACP_VCTR24_ena_ctrl,
+	 ACP_VCTR0_clk_ctrl, FALCON_SHIFT_MODE0_ena_ctrl,
+	 FALCON_SHIFT_MODE8_ena_ctrl, FALCON_SHIFT_MODE0_clk_ctrl,
+	 ST_SHIFT_MODE0_ena_ctrl, ST_SHIFT_MODE0_clk_ctrl;
+   reg CLK17M_q, CLK13M_q, VR_WR_q;
+   reg [8:0] VR_DOUT_q;
+   reg [7:0] VR_FRQ_q;
+   reg VIDEO_RECONFIG_q;
+   reg [1:0] ST_SHIFT_MODE_q;
+   reg [10:0] FALCON_SHIFT_MODE_q;
+   reg [3:0] CLUT_MUX_ADR_q;
+   reg [3:0] CLUT_MUX_AV1__q;
+   reg [3:0] CLUT_MUX_AV0__q;
+   reg [31:0] ACP_VCTR_q;
+   reg [23:0] CCR_q;
+   reg [6:0] SYS_CTR_q;
+   reg [15:0] VDL_LOF_q;
+   reg [15:0] VDL_LWD_q;
+   reg CLUT_TA_q, HSYNC_q;
+   reg [7:0] HSYNC_I_q;
+   reg [7:0] HSY_LEN_q;
+   reg HSYNC_START_q, LAST_q, VSYNC_q, VSYNC_START_q;
+   reg [2:0] VSYNC_I_q;
+   reg nBLANK_q, DISP_ON_q, DPO_ZL_q, DPO_ON_q, DPO_OFF_q, VDTRON_q, VDO_ZL_q,
+	 VDO_ON_q, VDO_OFF_q;
+   reg [11:0] VHCNT_q;
+   reg [6:0] SUB_PIXEL_CNT_q;
+   reg [10:0] VVCNT_q;
+   reg [9:0] VERZ2__q;
+   reg [9:0] VERZ1__q;
+   reg [9:0] VERZ0__q;
+   reg [6:0] RAND_q;
+   reg FIFO_RDE_q, CLR_FIFO_q, START_ZEILE_q, SYNC_PIX_q, SYNC_PIX1_q,
+	 SYNC_PIX2_q;
+   reg [2:0] CCSEL_q;
+   reg [31:0] ATARI_HH_q;
+   reg [31:0] ATARI_VH_q;
+   reg [31:0] ATARI_HL_q;
+   reg [31:0] ATARI_VL_q;
+   reg [11:0] VDL_HHT_q;
+   reg [11:0] VDL_HBE_q;
+   reg [11:0] VDL_HDB_q;
+   reg [11:0] VDL_HDE_q;
+   reg [11:0] VDL_HBB_q;
+   reg [11:0] VDL_HSS_q;
+   reg INTER_ZEI_q, DOP_ZEI_q, DOP_FIFO_CLR_q;
+   reg [10:0] VDL_VBE_q;
+   reg [10:0] VDL_VDB_q;
+   reg [10:0] VDL_VDE_q;
+   reg [10:0] VDL_VBB_q;
+   reg [10:0] VDL_VSS_q;
+   reg [10:0] VDL_VFT_q;
+   reg [8:0] VDL_VCT_q;
+   reg [3:0] VDL_VMD_q;
+
+
+// Sub Module Section
+   //GE lpm_bustri_WORD  u0 (.data(u0_data), .enabledt(u0_enabledt),
+	 //GE .tridata(u0_tridata));
+
+   //GE lpm_bustri_WORD  u1 (.data(u1_data), .enabledt(u1_enabledt),
+	 //GE .tridata(u1_tridata));
+
+
+   assign CLUT_MUX_ADR = CLUT_MUX_ADR_q;
+   always @(posedge CLUT_MUX_ADR0_clk_ctrl)
+      CLUT_MUX_ADR_q <= CLUT_MUX_ADR_d;
+
+   assign HSYNC = HSYNC_q;
+   always @(posedge HSYNC_clk)
+      HSYNC_q <= HSYNC_d;
+
+   assign VSYNC = VSYNC_q;
+   always @(posedge VSYNC_clk)
+      VSYNC_q <= VSYNC_d;
+
+   assign nBLANK = nBLANK_q;
+   always @(posedge nBLANK_clk)
+      nBLANK_q <= nBLANK_d;
+
+   assign FIFO_RDE = FIFO_RDE_q;
+   always @(posedge FIFO_RDE_clk)
+      FIFO_RDE_q <= FIFO_RDE_d;
+
+   assign CCR[23:16] = CCR_q[23:16];
+   always @(posedge CCR0_clk_ctrl)
+      if (CCR16_ena_ctrl)
+	 {CCR_q[23], CCR_q[22], CCR_q[21], CCR_q[20], CCR_q[19], CCR_q[18],
+	       CCR_q[17], CCR_q[16]} <= CCR_d[23:16];
+
+   assign CCR[15:8] = CCR_q[15:8];
+   always @(posedge CCR0_clk_ctrl)
+      if (CCR8_ena_ctrl)
+	 {CCR_q[15], CCR_q[14], CCR_q[13], CCR_q[12], CCR_q[11], CCR_q[10],
+	       CCR_q[9], CCR_q[8]} <= CCR_d[15:8];
+
+   assign CCR[7:0] = CCR_q[7:0];
+   always @(posedge CCR0_clk_ctrl)
+      if (CCR0_ena_ctrl)
+	 {CCR_q[7], CCR_q[6], CCR_q[5], CCR_q[4], CCR_q[3], CCR_q[2], CCR_q[1],
+	       CCR_q[0]} <= CCR_d[7:0];
+
+   assign CCSEL = CCSEL_q;
+   always @(posedge CCSEL0_clk_ctrl)
+      CCSEL_q <= CCSEL_d;
+
+   assign INTER_ZEI = INTER_ZEI_q;
+   always @(posedge INTER_ZEI_clk)
+      INTER_ZEI_q <= INTER_ZEI_d;
+
+   assign DOP_FIFO_CLR = DOP_FIFO_CLR_q;
+   always @(posedge DOP_FIFO_CLR_clk)
+      DOP_FIFO_CLR_q <= DOP_FIFO_CLR_d;
+
+   assign VIDEO_RECONFIG = VIDEO_RECONFIG_q;
+   always @(posedge VIDEO_RECONFIG_clk)
+      VIDEO_RECONFIG_q <= VIDEO_RECONFIG_d;
+
+   assign VR_WR = VR_WR_q;
+   always @(posedge VR_WR_clk)
+      VR_WR_q <= VR_WR_d;
+
+   assign CLR_FIFO = CLR_FIFO_q;	 
+   always @(posedge CLR_FIFO_clk)
+      if (CLR_FIFO_ena)
+	 CLR_FIFO_q <= CLR_FIFO_d;
+
+   always @(posedge CLK17M_clk)
+      CLK17M_q <= CLK17M_d;
+
+   always @(posedge CLK13M_clk)
+      CLK13M_q <= CLK13M_d;
+
+   always @(posedge VR_DOUT0_clk_ctrl)
+      if (VR_DOUT0_ena_ctrl)
+	 VR_DOUT_q <= VR_DOUT_d;
+
+   always @(posedge VR_FRQ0_clk_ctrl)
+      if (VR_FRQ0_ena_ctrl)
+	 VR_FRQ_q <= VR_FRQ_d;
+
+   always @(posedge ST_SHIFT_MODE0_clk_ctrl)
+      if (ST_SHIFT_MODE0_ena_ctrl)
+	 ST_SHIFT_MODE_q <= ST_SHIFT_MODE_d;
+
+   always @(posedge FALCON_SHIFT_MODE0_clk_ctrl)
+      if (FALCON_SHIFT_MODE8_ena_ctrl)
+	 {FALCON_SHIFT_MODE_q[10], FALCON_SHIFT_MODE_q[9],
+	       FALCON_SHIFT_MODE_q[8]} <= FALCON_SHIFT_MODE_d[10:8];
+
+   always @(posedge FALCON_SHIFT_MODE0_clk_ctrl)
+      if (FALCON_SHIFT_MODE0_ena_ctrl)
+	 {FALCON_SHIFT_MODE_q[7], FALCON_SHIFT_MODE_q[6],
+	       FALCON_SHIFT_MODE_q[5], FALCON_SHIFT_MODE_q[4],
+	       FALCON_SHIFT_MODE_q[3], FALCON_SHIFT_MODE_q[2],
+	       FALCON_SHIFT_MODE_q[1], FALCON_SHIFT_MODE_q[0]} <=
+	       FALCON_SHIFT_MODE_d[7:0];
+
+   always @(posedge CLUT_MUX_AV1_0_clk_ctrl)
+      CLUT_MUX_AV1__q <= CLUT_MUX_AV1__d;
+
+   always @(posedge CLUT_MUX_AV0_0_clk_ctrl)
+      CLUT_MUX_AV0__q <= CLUT_MUX_AV0__d;
+
+   always @(posedge ACP_VCTR0_clk_ctrl)
+      if (ACP_VCTR24_ena_ctrl)
+	 {ACP_VCTR_q[31], ACP_VCTR_q[30], ACP_VCTR_q[29], ACP_VCTR_q[28],
+	       ACP_VCTR_q[27], ACP_VCTR_q[26], ACP_VCTR_q[25], ACP_VCTR_q[24]}
+	       <= ACP_VCTR_d[31:24];
+
+   always @(posedge ACP_VCTR0_clk_ctrl)
+      if (ACP_VCTR16_ena_ctrl)
+	 {ACP_VCTR_q[23], ACP_VCTR_q[22], ACP_VCTR_q[21], ACP_VCTR_q[20],
+	       ACP_VCTR_q[19], ACP_VCTR_q[18], ACP_VCTR_q[17], ACP_VCTR_q[16]}
+	       <= ACP_VCTR_d[23:16];
+
+   always @(posedge ACP_VCTR0_clk_ctrl)
+      if (ACP_VCTR8_ena_ctrl)
+	 {ACP_VCTR_q[15], ACP_VCTR_q[14], ACP_VCTR_q[13], ACP_VCTR_q[12],
+	       ACP_VCTR_q[11], ACP_VCTR_q[10], ACP_VCTR_q[9], ACP_VCTR_q[8]} <=
+	       ACP_VCTR_d[15:8];
+
+   always @(posedge ACP_VCTR0_clk_ctrl)
+      if (ACP_VCTR6_ena_ctrl)
+	 {ACP_VCTR_q[7], ACP_VCTR_q[6]} <= ACP_VCTR_d[7:6];
+
+   always @(posedge ACP_VCTR0_clk_ctrl)
+      if (ACP_VCTR0_ena_ctrl)
+	 {ACP_VCTR_q[5], ACP_VCTR_q[4], ACP_VCTR_q[3], ACP_VCTR_q[2],
+	       ACP_VCTR_q[1], ACP_VCTR_q[0]} <= ACP_VCTR_d[5:0];
+
+   always @(posedge SYS_CTR0_clk_ctrl)
+      if (SYS_CTR0_ena_ctrl)
+	 SYS_CTR_q <= SYS_CTR_d;
+
+   always @(posedge VDL_LOF0_clk_ctrl)
+      if (VDL_LOF8_ena_ctrl)
+	 {VDL_LOF_q[15], VDL_LOF_q[14], VDL_LOF_q[13], VDL_LOF_q[12],
+	       VDL_LOF_q[11], VDL_LOF_q[10], VDL_LOF_q[9], VDL_LOF_q[8]} <=
+	       VDL_LOF_d[15:8];
+
+   always @(posedge VDL_LOF0_clk_ctrl)
+      if (VDL_LOF0_ena_ctrl)
+	 {VDL_LOF_q[7], VDL_LOF_q[6], VDL_LOF_q[5], VDL_LOF_q[4], VDL_LOF_q[3],
+	       VDL_LOF_q[2], VDL_LOF_q[1], VDL_LOF_q[0]} <= VDL_LOF_d[7:0];
+
+   always @(posedge VDL_LWD0_clk_ctrl)
+      if (VDL_LWD8_ena_ctrl)
+	 {VDL_LWD_q[15], VDL_LWD_q[14], VDL_LWD_q[13], VDL_LWD_q[12],
+	       VDL_LWD_q[11], VDL_LWD_q[10], VDL_LWD_q[9], VDL_LWD_q[8]} <=
+	       VDL_LWD_d[15:8];
+
+   always @(posedge VDL_LWD0_clk_ctrl)
+      if (VDL_LWD0_ena_ctrl)
+	 {VDL_LWD_q[7], VDL_LWD_q[6], VDL_LWD_q[5], VDL_LWD_q[4], VDL_LWD_q[3],
+	       VDL_LWD_q[2], VDL_LWD_q[1], VDL_LWD_q[0]} <= VDL_LWD_d[7:0];
+
+   always @(posedge CLUT_TA_clk)
+      CLUT_TA_q <= CLUT_TA_d;
+
+   always @(posedge HSYNC_I0_clk_ctrl)
+      HSYNC_I_q <= HSYNC_I_d;
+
+   always @(posedge HSY_LEN0_clk_ctrl)
+      HSY_LEN_q <= HSY_LEN_d;
+
+   always @(posedge HSYNC_START_clk)
+      HSYNC_START_q <= HSYNC_START_d;
+
+   always @(posedge LAST_clk)
+      LAST_q <= LAST_d;
+
+   always @(posedge VSYNC_START_clk)
+      if (VSYNC_START_ena)
+	 VSYNC_START_q <= VSYNC_START_d;
+
+   always @(posedge VSYNC_I0_clk_ctrl)
+      if (VSYNC_I0_ena_ctrl)
+	 VSYNC_I_q <= VSYNC_I_d;
+
+   always @(posedge DISP_ON_clk)
+      DISP_ON_q <= DISP_ON_d;
+
+   always @(posedge DPO_ZL_clk)
+      if (DPO_ZL_ena)
+	 DPO_ZL_q <= DPO_ZL_d;
+
+   always @(posedge DPO_ON_clk)
+      DPO_ON_q <= DPO_ON_d;
+
+   always @(posedge DPO_OFF_clk)
+      DPO_OFF_q <= DPO_OFF_d;
+
+   always @(posedge VDTRON_clk)
+      VDTRON_q <= VDTRON_d;
+
+   always @(posedge VDO_ZL_clk)
+      if (VDO_ZL_ena)
+	 VDO_ZL_q <= VDO_ZL_d;
+
+   always @(posedge VDO_ON_clk)
+      VDO_ON_q <= VDO_ON_d;
+
+   always @(posedge VDO_OFF_clk)
+      VDO_OFF_q <= VDO_OFF_d;
+
+   always @(posedge VHCNT0_clk_ctrl)
+      VHCNT_q <= VHCNT_d;
+
+   always @(posedge SUB_PIXEL_CNT0_clk_ctrl)
+      if (SUB_PIXEL_CNT0_ena_ctrl)
+	 SUB_PIXEL_CNT_q <= SUB_PIXEL_CNT_d;
+
+   always @(posedge VVCNT0_clk_ctrl)
+      if (VVCNT0_ena_ctrl)
+	 VVCNT_q <= VVCNT_d;
+
+   always @(posedge VERZ2_0_clk_ctrl)
+      VERZ2__q <= VERZ2__d;
+
+   always @(posedge VERZ1_0_clk_ctrl)
+      VERZ1__q <= VERZ1__d;
+
+   always @(posedge VERZ0_0_clk_ctrl)
+      VERZ0__q <= VERZ0__d;
+
+   always @(posedge RAND0_clk_ctrl)
+      RAND_q <= RAND_d;
+
+   always @(posedge START_ZEILE_clk)
+      if (START_ZEILE_ena)
+	 START_ZEILE_q <= START_ZEILE_d;
+
+   always @(posedge SYNC_PIX_clk)
+      SYNC_PIX_q <= SYNC_PIX_d;
+
+   always @(posedge SYNC_PIX1_clk)
+      SYNC_PIX1_q <= SYNC_PIX1_d;
+
+   always @(posedge SYNC_PIX2_clk)
+      SYNC_PIX2_q <= SYNC_PIX2_d;
+
+   always @(posedge ATARI_HH0_clk_ctrl)
+      if (ATARI_HH24_ena_ctrl)
+	 {ATARI_HH_q[31], ATARI_HH_q[30], ATARI_HH_q[29], ATARI_HH_q[28],
+	       ATARI_HH_q[27], ATARI_HH_q[26], ATARI_HH_q[25], ATARI_HH_q[24]}
+	       <= ATARI_HH_d[31:24];
+
+   always @(posedge ATARI_HH0_clk_ctrl)
+      if (ATARI_HH16_ena_ctrl)
+	 {ATARI_HH_q[23], ATARI_HH_q[22], ATARI_HH_q[21], ATARI_HH_q[20],
+	       ATARI_HH_q[19], ATARI_HH_q[18], ATARI_HH_q[17], ATARI_HH_q[16]}
+	       <= ATARI_HH_d[23:16];
+
+   always @(posedge ATARI_HH0_clk_ctrl)
+      if (ATARI_HH8_ena_ctrl)
+	 {ATARI_HH_q[15], ATARI_HH_q[14], ATARI_HH_q[13], ATARI_HH_q[12],
+	       ATARI_HH_q[11], ATARI_HH_q[10], ATARI_HH_q[9], ATARI_HH_q[8]} <=
+	       ATARI_HH_d[15:8];
+
+   always @(posedge ATARI_HH0_clk_ctrl)
+      if (ATARI_HH0_ena_ctrl)
+	 {ATARI_HH_q[7], ATARI_HH_q[6], ATARI_HH_q[5], ATARI_HH_q[4],
+	       ATARI_HH_q[3], ATARI_HH_q[2], ATARI_HH_q[1], ATARI_HH_q[0]} <=
+	       ATARI_HH_d[7:0];
+
+   always @(posedge ATARI_VH0_clk_ctrl)
+      if (ATARI_VH24_ena_ctrl)
+	 {ATARI_VH_q[31], ATARI_VH_q[30], ATARI_VH_q[29], ATARI_VH_q[28],
+	       ATARI_VH_q[27], ATARI_VH_q[26], ATARI_VH_q[25], ATARI_VH_q[24]}
+	       <= ATARI_VH_d[31:24];
+
+   always @(posedge ATARI_VH0_clk_ctrl)
+      if (ATARI_VH16_ena_ctrl)
+	 {ATARI_VH_q[23], ATARI_VH_q[22], ATARI_VH_q[21], ATARI_VH_q[20],
+	       ATARI_VH_q[19], ATARI_VH_q[18], ATARI_VH_q[17], ATARI_VH_q[16]}
+	       <= ATARI_VH_d[23:16];
+
+   always @(posedge ATARI_VH0_clk_ctrl)
+      if (ATARI_VH8_ena_ctrl)
+	 {ATARI_VH_q[15], ATARI_VH_q[14], ATARI_VH_q[13], ATARI_VH_q[12],
+	       ATARI_VH_q[11], ATARI_VH_q[10], ATARI_VH_q[9], ATARI_VH_q[8]} <=
+	       ATARI_VH_d[15:8];
+
+   always @(posedge ATARI_VH0_clk_ctrl)
+      if (ATARI_VH0_ena_ctrl)
+	 {ATARI_VH_q[7], ATARI_VH_q[6], ATARI_VH_q[5], ATARI_VH_q[4],
+	       ATARI_VH_q[3], ATARI_VH_q[2], ATARI_VH_q[1], ATARI_VH_q[0]} <=
+	       ATARI_VH_d[7:0];
+
+   always @(posedge ATARI_HL0_clk_ctrl)
+      if (ATARI_HL24_ena_ctrl)
+	 {ATARI_HL_q[31], ATARI_HL_q[30], ATARI_HL_q[29], ATARI_HL_q[28],
+	       ATARI_HL_q[27], ATARI_HL_q[26], ATARI_HL_q[25], ATARI_HL_q[24]}
+	       <= ATARI_HL_d[31:24];
+
+   always @(posedge ATARI_HL0_clk_ctrl)
+      if (ATARI_HL16_ena_ctrl)
+	 {ATARI_HL_q[23], ATARI_HL_q[22], ATARI_HL_q[21], ATARI_HL_q[20],
+	       ATARI_HL_q[19], ATARI_HL_q[18], ATARI_HL_q[17], ATARI_HL_q[16]}
+	       <= ATARI_HL_d[23:16];
+
+   always @(posedge ATARI_HL0_clk_ctrl)
+      if (ATARI_HL8_ena_ctrl)
+	 {ATARI_HL_q[15], ATARI_HL_q[14], ATARI_HL_q[13], ATARI_HL_q[12],
+	       ATARI_HL_q[11], ATARI_HL_q[10], ATARI_HL_q[9], ATARI_HL_q[8]} <=
+	       ATARI_HL_d[15:8];
+
+   always @(posedge ATARI_HL0_clk_ctrl)
+      if (ATARI_HL0_ena_ctrl)
+	 {ATARI_HL_q[7], ATARI_HL_q[6], ATARI_HL_q[5], ATARI_HL_q[4],
+	       ATARI_HL_q[3], ATARI_HL_q[2], ATARI_HL_q[1], ATARI_HL_q[0]} <=
+	       ATARI_HL_d[7:0];
+
+   always @(posedge ATARI_VL0_clk_ctrl)
+      if (ATARI_VL24_ena_ctrl)
+	 {ATARI_VL_q[31], ATARI_VL_q[30], ATARI_VL_q[29], ATARI_VL_q[28],
+	       ATARI_VL_q[27], ATARI_VL_q[26], ATARI_VL_q[25], ATARI_VL_q[24]}
+	       <= ATARI_VL_d[31:24];
+
+   always @(posedge ATARI_VL0_clk_ctrl)
+      if (ATARI_VL16_ena_ctrl)
+	 {ATARI_VL_q[23], ATARI_VL_q[22], ATARI_VL_q[21], ATARI_VL_q[20],
+	       ATARI_VL_q[19], ATARI_VL_q[18], ATARI_VL_q[17], ATARI_VL_q[16]}
+	       <= ATARI_VL_d[23:16];
+
+   always @(posedge ATARI_VL0_clk_ctrl)
+      if (ATARI_VL8_ena_ctrl)
+	 {ATARI_VL_q[15], ATARI_VL_q[14], ATARI_VL_q[13], ATARI_VL_q[12],
+	       ATARI_VL_q[11], ATARI_VL_q[10], ATARI_VL_q[9], ATARI_VL_q[8]} <=
+	       ATARI_VL_d[15:8];
+
+   always @(posedge ATARI_VL0_clk_ctrl)
+      if (ATARI_VL0_ena_ctrl)
+	 {ATARI_VL_q[7], ATARI_VL_q[6], ATARI_VL_q[5], ATARI_VL_q[4],
+	       ATARI_VL_q[3], ATARI_VL_q[2], ATARI_VL_q[1], ATARI_VL_q[0]} <=
+	       ATARI_VL_d[7:0];
+
+   always @(posedge VDL_HHT0_clk_ctrl)
+      if (VDL_HHT8_ena_ctrl)
+	 {VDL_HHT_q[11], VDL_HHT_q[10], VDL_HHT_q[9], VDL_HHT_q[8]} <=
+	       VDL_HHT_d[11:8];
+
+   always @(posedge VDL_HHT0_clk_ctrl)
+      if (VDL_HHT0_ena_ctrl)
+	 {VDL_HHT_q[7], VDL_HHT_q[6], VDL_HHT_q[5], VDL_HHT_q[4], VDL_HHT_q[3],
+	       VDL_HHT_q[2], VDL_HHT_q[1], VDL_HHT_q[0]} <= VDL_HHT_d[7:0];
+
+   always @(posedge VDL_HBE0_clk_ctrl)
+      if (VDL_HBE8_ena_ctrl)
+	 {VDL_HBE_q[11], VDL_HBE_q[10], VDL_HBE_q[9], VDL_HBE_q[8]} <=
+	       VDL_HBE_d[11:8];
+
+   always @(posedge VDL_HBE0_clk_ctrl)
+      if (VDL_HBE0_ena_ctrl)
+	 {VDL_HBE_q[7], VDL_HBE_q[6], VDL_HBE_q[5], VDL_HBE_q[4], VDL_HBE_q[3],
+	       VDL_HBE_q[2], VDL_HBE_q[1], VDL_HBE_q[0]} <= VDL_HBE_d[7:0];
+
+   always @(posedge VDL_HDB0_clk_ctrl)
+      if (VDL_HDB8_ena_ctrl)
+	 {VDL_HDB_q[11], VDL_HDB_q[10], VDL_HDB_q[9], VDL_HDB_q[8]} <=
+	       VDL_HDB_d[11:8];
+
+   always @(posedge VDL_HDB0_clk_ctrl)
+      if (VDL_HDB0_ena_ctrl)
+	 {VDL_HDB_q[7], VDL_HDB_q[6], VDL_HDB_q[5], VDL_HDB_q[4], VDL_HDB_q[3],
+	       VDL_HDB_q[2], VDL_HDB_q[1], VDL_HDB_q[0]} <= VDL_HDB_d[7:0];
+
+   always @(posedge VDL_HDE0_clk_ctrl)
+      if (VDL_HDE8_ena_ctrl)
+	 {VDL_HDE_q[11], VDL_HDE_q[10], VDL_HDE_q[9], VDL_HDE_q[8]} <=
+	       VDL_HDE_d[11:8];
+
+   always @(posedge VDL_HDE0_clk_ctrl)
+      if (VDL_HDE0_ena_ctrl)
+	 {VDL_HDE_q[7], VDL_HDE_q[6], VDL_HDE_q[5], VDL_HDE_q[4], VDL_HDE_q[3],
+	       VDL_HDE_q[2], VDL_HDE_q[1], VDL_HDE_q[0]} <= VDL_HDE_d[7:0];
+
+   always @(posedge VDL_HBB0_clk_ctrl)
+      if (VDL_HBB8_ena_ctrl)
+	 {VDL_HBB_q[11], VDL_HBB_q[10], VDL_HBB_q[9], VDL_HBB_q[8]} <=
+	       VDL_HBB_d[11:8];
+
+   always @(posedge VDL_HBB0_clk_ctrl)
+      if (VDL_HBB0_ena_ctrl)
+	 {VDL_HBB_q[7], VDL_HBB_q[6], VDL_HBB_q[5], VDL_HBB_q[4], VDL_HBB_q[3],
+	       VDL_HBB_q[2], VDL_HBB_q[1], VDL_HBB_q[0]} <= VDL_HBB_d[7:0];
+
+   always @(posedge VDL_HSS0_clk_ctrl)
+      if (VDL_HSS8_ena_ctrl)
+	 {VDL_HSS_q[11], VDL_HSS_q[10], VDL_HSS_q[9], VDL_HSS_q[8]} <=
+	       VDL_HSS_d[11:8];
+
+   always @(posedge VDL_HSS0_clk_ctrl)
+      if (VDL_HSS0_ena_ctrl)
+	 {VDL_HSS_q[7], VDL_HSS_q[6], VDL_HSS_q[5], VDL_HSS_q[4], VDL_HSS_q[3],
+	       VDL_HSS_q[2], VDL_HSS_q[1], VDL_HSS_q[0]} <= VDL_HSS_d[7:0];
+
+   always @(posedge DOP_ZEI_clk)
+      DOP_ZEI_q <= DOP_ZEI_d;
+
+   always @(posedge VDL_VBE0_clk_ctrl)
+      if (VDL_VBE8_ena_ctrl)
+	 {VDL_VBE_q[10], VDL_VBE_q[9], VDL_VBE_q[8]} <= VDL_VBE_d[10:8];
+
+   always @(posedge VDL_VBE0_clk_ctrl)
+      if (VDL_VBE0_ena_ctrl)
+	 {VDL_VBE_q[7], VDL_VBE_q[6], VDL_VBE_q[5], VDL_VBE_q[4], VDL_VBE_q[3],
+	       VDL_VBE_q[2], VDL_VBE_q[1], VDL_VBE_q[0]} <= VDL_VBE_d[7:0];
+
+   always @(posedge VDL_VDB0_clk_ctrl)
+      if (VDL_VDB8_ena_ctrl)
+	 {VDL_VDB_q[10], VDL_VDB_q[9], VDL_VDB_q[8]} <= VDL_VDB_d[10:8];
+
+   always @(posedge VDL_VDB0_clk_ctrl)
+      if (VDL_VDB0_ena_ctrl)
+	 {VDL_VDB_q[7], VDL_VDB_q[6], VDL_VDB_q[5], VDL_VDB_q[4], VDL_VDB_q[3],
+	       VDL_VDB_q[2], VDL_VDB_q[1], VDL_VDB_q[0]} <= VDL_VDB_d[7:0];
+
+   always @(posedge VDL_VDE0_clk_ctrl)
+      if (VDL_VDE8_ena_ctrl)
+	 {VDL_VDE_q[10], VDL_VDE_q[9], VDL_VDE_q[8]} <= VDL_VDE_d[10:8];
+
+   always @(posedge VDL_VDE0_clk_ctrl)
+      if (VDL_VDE0_ena_ctrl)
+	 {VDL_VDE_q[7], VDL_VDE_q[6], VDL_VDE_q[5], VDL_VDE_q[4], VDL_VDE_q[3],
+	       VDL_VDE_q[2], VDL_VDE_q[1], VDL_VDE_q[0]} <= VDL_VDE_d[7:0];
+
+   always @(posedge VDL_VBB0_clk_ctrl)
+      if (VDL_VBB8_ena_ctrl)
+	 {VDL_VBB_q[10], VDL_VBB_q[9], VDL_VBB_q[8]} <= VDL_VBB_d[10:8];
+
+   always @(posedge VDL_VBB0_clk_ctrl)
+      if (VDL_VBB0_ena_ctrl)
+	 {VDL_VBB_q[7], VDL_VBB_q[6], VDL_VBB_q[5], VDL_VBB_q[4], VDL_VBB_q[3],
+	       VDL_VBB_q[2], VDL_VBB_q[1], VDL_VBB_q[0]} <= VDL_VBB_d[7:0];
+
+   always @(posedge VDL_VSS0_clk_ctrl)
+      if (VDL_VSS8_ena_ctrl)
+	 {VDL_VSS_q[10], VDL_VSS_q[9], VDL_VSS_q[8]} <= VDL_VSS_d[10:8];
+
+   always @(posedge VDL_VSS0_clk_ctrl)
+      if (VDL_VSS0_ena_ctrl)
+	 {VDL_VSS_q[7], VDL_VSS_q[6], VDL_VSS_q[5], VDL_VSS_q[4], VDL_VSS_q[3],
+	       VDL_VSS_q[2], VDL_VSS_q[1], VDL_VSS_q[0]} <= VDL_VSS_d[7:0];
+
+   always @(posedge VDL_VFT0_clk_ctrl)
+      if (VDL_VFT8_ena_ctrl)
+	 {VDL_VFT_q[10], VDL_VFT_q[9], VDL_VFT_q[8]} <= VDL_VFT_d[10:8];
+
+   always @(posedge VDL_VFT0_clk_ctrl)
+      if (VDL_VFT0_ena_ctrl)
+	 {VDL_VFT_q[7], VDL_VFT_q[6], VDL_VFT_q[5], VDL_VFT_q[4], VDL_VFT_q[3],
+	       VDL_VFT_q[2], VDL_VFT_q[1], VDL_VFT_q[0]} <= VDL_VFT_d[7:0];
+
+   always @(posedge VDL_VCT0_clk_ctrl)
+      if (VDL_VCT8_ena)
+	 VDL_VCT_q[8] <= VDL_VCT_d[8];
+
+   always @(posedge VDL_VCT0_clk_ctrl)
+      if (VDL_VCT0_ena_ctrl)
+	 {VDL_VCT_q[7], VDL_VCT_q[6], VDL_VCT_q[5], VDL_VCT_q[4], VDL_VCT_q[3],
+	       VDL_VCT_q[2], VDL_VCT_q[1], VDL_VCT_q[0]} <= VDL_VCT_d[7:0];
+
+   always @(posedge VDL_VMD0_clk_ctrl)
+      if (VDL_VMD0_ena_ctrl)
+	 VDL_VMD_q <= VDL_VMD_d;
+
+// Start of original equations
+
+//  BYT SELECT 32 BIT
+//  ADR==0
+   assign FB_B[0] = FB_ADR[1:0] == 2'b00;
+
+//  ADR==1
+//  HIGH WORD
+//  LONG UND LINE
+   assign FB_B[1] = FB_ADR[1:0] == 2'b01 | (FB_SIZE1 & (!FB_SIZE0) &
+	 (!FB_ADR[1])) | (FB_SIZE1 & FB_SIZE0) | ((!FB_SIZE1) & (!FB_SIZE0));
+
+//  ADR==2
+//  LONG UND LINE
+   assign FB_B[2] = FB_ADR[1:0] == 2'b10 | (FB_SIZE1 & FB_SIZE0) | ((!FB_SIZE1)
+	 & (!FB_SIZE0));
+
+//  ADR==3
+//  LOW WORD
+//  LONG UND LINE
+   assign FB_B[3] = FB_ADR[1:0] == 2'b11 | (FB_SIZE1 & (!FB_SIZE0) & FB_ADR[1])
+	 | (FB_SIZE1 & FB_SIZE0) | ((!FB_SIZE1) & (!FB_SIZE0));
+
+//  BYT SELECT 16 BIT
+//  ADR==0
+   assign FB_16B[0] = FB_ADR[0] == 1'b0;
+
+//  ADR==1
+//  NOT BYT
+   assign FB_16B[1] = FB_ADR[0] == 1'b1 | (!((!FB_SIZE1) & FB_SIZE0));
+
+//  ACP CLUT --
+//  0-3FF/1024
+   assign ACP_CLUT_CS = (!nFB_CS2) & FB_ADR[27:10] == 18'h0;
+   assign ACP_CLUT_RD = ACP_CLUT_CS & (!nFB_OE);
+   assign ACP_CLUT_WR = FB_B & {4{ACP_CLUT_CS}} & {4{!nFB_WR}};
+   assign CLUT_TA_clk = MAIN_CLK;
+   assign CLUT_TA_d = (ACP_CLUT_CS | FALCON_CLUT_CS | ST_CLUT_CS) &
+	 (!VIDEO_MOD_TA);
+
+// FALCON CLUT --
+//  $F9800/$400
+   assign FALCON_CLUT_CS = (!nFB_CS1) & FB_ADR[19:10] == 10'b11_1110_0110;
+
+//  HIGH WORD
+   assign FALCON_CLUT_RDH = FALCON_CLUT_CS & (!nFB_OE) & (!FB_ADR[1]);
+
+//  LOW WORD
+   assign FALCON_CLUT_RDL = FALCON_CLUT_CS & (!nFB_OE) & FB_ADR[1];
+   assign FALCON_CLUT_WR[1:0] = FB_16B & {2{!FB_ADR[1]}} & {2{FALCON_CLUT_CS}}
+	 & {2{!nFB_WR}};
+   assign FALCON_CLUT_WR[3:2] = FB_16B & {2{FB_ADR[1]}} & {2{FALCON_CLUT_CS}} &
+	 {2{!nFB_WR}};
+
+//  ST CLUT --
+//  $F8240/$20
+   assign ST_CLUT_CS = (!nFB_CS1) & FB_ADR[19:5] == 15'b111_1100_0001_0010;
+   assign ST_CLUT_RD = ST_CLUT_CS & (!nFB_OE);
+   assign ST_CLUT_WR = FB_16B & {2{ST_CLUT_CS}} & {2{!nFB_WR}};
+
+//  ST SHIFT MODE
+   assign ST_SHIFT_MODE0_clk_ctrl = MAIN_CLK;
+
+//  $F8260/2
+   assign ST_SHIFT_MODE_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C130;
+   assign ST_SHIFT_MODE_d = FB_AD[25:24];
+   assign ST_SHIFT_MODE0_ena_ctrl = ST_SHIFT_MODE_CS & (!nFB_WR) & FB_B[0];
+
+//  MONO
+   assign COLOR1_1 = ST_SHIFT_MODE_q == 2'b10 & (!COLOR8) & ST_VIDEO &
+	 (!ACP_VIDEO_ON);
+
+//  4 FARBEN
+   assign COLOR2 = ST_SHIFT_MODE_q == 2'b01 & (!COLOR8) & ST_VIDEO &
+	 (!ACP_VIDEO_ON);
+
+//  16 FARBEN
+   assign COLOR4_1 = ST_SHIFT_MODE_q == 2'b00 & (!COLOR8) & ST_VIDEO &
+	 (!ACP_VIDEO_ON);
+
+//  FALCON SHIFT MODE
+   assign FALCON_SHIFT_MODE0_clk_ctrl = MAIN_CLK;
+
+//  $F8266/2
+   assign FALCON_SHIFT_MODE_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C133;
+   assign FALCON_SHIFT_MODE_d = FB_AD[26:16];
+   assign FALCON_SHIFT_MODE8_ena_ctrl = FALCON_SHIFT_MODE_CS & (!nFB_WR) &
+	 FB_B[2];
+   assign FALCON_SHIFT_MODE0_ena_ctrl = FALCON_SHIFT_MODE_CS & (!nFB_WR) &
+	 FB_B[3];
+   assign CLUT_OFF = FALCON_SHIFT_MODE_q[3:0] & {4{COLOR4}};
+   assign COLOR1_2 = FALCON_SHIFT_MODE_q[10] & (!COLOR16) & (!COLOR8) &
+	 FALCON_VIDEO & (!ACP_VIDEO_ON);
+   assign COLOR8_1 = FALCON_SHIFT_MODE_q[4] & (!COLOR16) & FALCON_VIDEO &
+	 (!ACP_VIDEO_ON);
+   assign COLOR16_1 = FALCON_SHIFT_MODE_q[8] & FALCON_VIDEO & (!ACP_VIDEO_ON);
+   assign COLOR4_2 = (!COLOR1) & (!COLOR16) & (!COLOR8) & FALCON_VIDEO &
+	 (!ACP_VIDEO_ON);
+
+//  ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
+   assign ACP_VCTR0_clk_ctrl = MAIN_CLK;
+
+//  $400/4
+   assign ACP_VCTR_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h100;
+   assign ACP_VCTR_d[31:8] = FB_AD[31:8];
+   assign ACP_VCTR_d[5:0] = FB_AD[5:0];
+   assign ACP_VCTR24_ena_ctrl = ACP_VCTR_CS & FB_B[0] & (!nFB_WR);
+   assign ACP_VCTR16_ena_ctrl = ACP_VCTR_CS & FB_B[1] & (!nFB_WR);
+   assign ACP_VCTR8_ena_ctrl = ACP_VCTR_CS & FB_B[2] & (!nFB_WR);
+   assign ACP_VCTR0_ena_ctrl = ACP_VCTR_CS & FB_B[3] & (!nFB_WR);
+   assign ACP_VIDEO_ON = ACP_VCTR_q[0];
+   assign nPD_VGA = ACP_VCTR_q[1];
+
+//  ATARI MODUS
+//  WENN 1 AUTOMATISCHE AUFLÖSUNG
+   assign ATARI_SYNC = ACP_VCTR_q[26];
+
+//  HORIZONTAL TIMING 640x480
+   assign ATARI_HH0_clk_ctrl = MAIN_CLK;
+
+//  $410/4
+   assign ATARI_HH_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h104;
+   assign ATARI_HH_d = FB_AD;
+   assign ATARI_HH24_ena_ctrl = ATARI_HH_CS & FB_B[0] & (!nFB_WR);
+   assign ATARI_HH16_ena_ctrl = ATARI_HH_CS & FB_B[1] & (!nFB_WR);
+   assign ATARI_HH8_ena_ctrl = ATARI_HH_CS & FB_B[2] & (!nFB_WR);
+   assign ATARI_HH0_ena_ctrl = ATARI_HH_CS & FB_B[3] & (!nFB_WR);
+
+//  VERTIKAL TIMING 640x480
+   assign ATARI_VH0_clk_ctrl = MAIN_CLK;
+
+//  $414/4
+   assign ATARI_VH_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h105;
+   assign ATARI_VH_d = FB_AD;
+   assign ATARI_VH24_ena_ctrl = ATARI_VH_CS & FB_B[0] & (!nFB_WR);
+   assign ATARI_VH16_ena_ctrl = ATARI_VH_CS & FB_B[1] & (!nFB_WR);
+   assign ATARI_VH8_ena_ctrl = ATARI_VH_CS & FB_B[2] & (!nFB_WR);
+   assign ATARI_VH0_ena_ctrl = ATARI_VH_CS & FB_B[3] & (!nFB_WR);
+
+//  HORIZONTAL TIMING 320x240
+   assign ATARI_HL0_clk_ctrl = MAIN_CLK;
+
+//  $418/4
+   assign ATARI_HL_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h106;
+   assign ATARI_HL_d = FB_AD;
+   assign ATARI_HL24_ena_ctrl = ATARI_HL_CS & FB_B[0] & (!nFB_WR);
+   assign ATARI_HL16_ena_ctrl = ATARI_HL_CS & FB_B[1] & (!nFB_WR);
+   assign ATARI_HL8_ena_ctrl = ATARI_HL_CS & FB_B[2] & (!nFB_WR);
+   assign ATARI_HL0_ena_ctrl = ATARI_HL_CS & FB_B[3] & (!nFB_WR);
+
+//  VERTIKAL TIMING 320x240
+   assign ATARI_VL0_clk_ctrl = MAIN_CLK;
+
+//  $41C/4
+   assign ATARI_VL_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h107;
+   assign ATARI_VL_d = FB_AD;
+   assign ATARI_VL24_ena_ctrl = ATARI_VL_CS & FB_B[0] & (!nFB_WR);
+   assign ATARI_VL16_ena_ctrl = ATARI_VL_CS & FB_B[1] & (!nFB_WR);
+   assign ATARI_VL8_ena_ctrl = ATARI_VL_CS & FB_B[2] & (!nFB_WR);
+   assign ATARI_VL0_ena_ctrl = ATARI_VL_CS & FB_B[3] & (!nFB_WR);
+
+//  VIDEO PLL CONFIG
+//  $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
+   assign VIDEO_PLL_CONFIG_CS = (!nFB_CS2) & FB_ADR[27:9] == 19'h3 & FB_B[0] &
+	 FB_B[1];
+   assign VR_WR_clk = MAIN_CLK;
+   assign VR_WR_d = VIDEO_PLL_CONFIG_CS & (!nFB_WR) & (!VR_BUSY) & (!VR_WR_q);
+   assign VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & (!VR_BUSY);
+   assign VR_DOUT0_clk_ctrl = MAIN_CLK;
+   assign VR_DOUT0_ena_ctrl = !VR_BUSY;
+   assign VR_DOUT_d = VR_D;
+   assign VR_FRQ0_clk_ctrl = MAIN_CLK;
+   assign VR_FRQ0_ena_ctrl = VR_WR_q & FB_ADR[8:0] == 9'b0_0000_0100;
+   assign VR_FRQ_d = FB_AD[23:16];
+
+//  VIDEO PLL RECONFIG
+//  $(F)000'0800
+   assign VIDEO_PLL_RECONFIG_CS = (!nFB_CS2) & FB_ADR[27:0] == 28'h800 &
+	 FB_B[0];
+   assign VIDEO_RECONFIG_clk = MAIN_CLK;
+   assign VIDEO_RECONFIG_d = VIDEO_PLL_RECONFIG_CS & (!nFB_WR) & (!VR_BUSY) &
+	 (!VIDEO_RECONFIG_q);
+
+// ----------------------------------------------------------------------------------------------------------------------
+   assign VIDEO_RAM_CTR = ACP_VCTR_q[31:16];
+
+// ------------ COLOR MODE IM ACP SETZEN
+   assign COLOR1_3 = ACP_VCTR_q[5] & (!ACP_VCTR_q[4]) & (!ACP_VCTR_q[3]) &
+	 (!ACP_VCTR_q[2]) & ACP_VIDEO_ON;
+   assign COLOR8_2 = ACP_VCTR_q[4] & (!ACP_VCTR_q[3]) & (!ACP_VCTR_q[2]) &
+	 ACP_VIDEO_ON;
+   assign COLOR16_2 = ACP_VCTR_q[3] & (!ACP_VCTR_q[2]) & ACP_VIDEO_ON;
+   assign COLOR24 = ACP_VCTR_q[2] & ACP_VIDEO_ON;
+   assign ACP_CLUT = (ACP_VIDEO_ON & (COLOR1 | COLOR8)) | (ST_VIDEO & COLOR1);
+
+//  ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
+   assign ACP_VCTR_d[7] = FALCON_SHIFT_MODE_CS & (!nFB_WR) & (!ACP_VIDEO_ON);
+   assign ACP_VCTR_d[6] = ST_SHIFT_MODE_CS & (!nFB_WR) & (!ACP_VIDEO_ON);
+   assign ACP_VCTR6_ena_ctrl = (FALCON_SHIFT_MODE_CS & (!nFB_WR)) |
+	 (ST_SHIFT_MODE_CS & (!nFB_WR)) | (ACP_VCTR_CS & FB_B[3] & (!nFB_WR) &
+	 FB_AD[0]);
+   assign FALCON_VIDEO = ACP_VCTR_q[7];
+   assign FALCON_CLUT = FALCON_VIDEO & (!ACP_VIDEO_ON) & (!COLOR16);
+   assign ST_VIDEO = ACP_VCTR_q[6];
+   assign ST_CLUT = ST_VIDEO & (!ACP_VIDEO_ON) & (!FALCON_CLUT) & (!COLOR1);
+   assign CCSEL0_clk_ctrl = PIXEL_CLK;
+
+//  ONLY FOR INFORMATION
+   assign CCSEL_d = (3'b000 & {3{ST_CLUT}}) | (3'b001 & {3{FALCON_CLUT}}) |
+	 (3'b100 & {3{ACP_CLUT}}) | (3'b101 & {3{COLOR16}}) | (3'b110 &
+	 {3{COLOR24}}) | (3'b111 & {3{RAND_ON}});
+
+//  DIVERSE (VIDEO)-REGISTER ----------------------------
+//  RANDFARBE
+   assign CCR0_clk_ctrl = MAIN_CLK;
+
+//  $404/4
+   assign CCR_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h101;
+   assign CCR_d = FB_AD[23:0];
+   assign CCR16_ena_ctrl = CCR_CS & FB_B[1] & (!nFB_WR);
+   assign CCR8_ena_ctrl = CCR_CS & FB_B[2] & (!nFB_WR);
+   assign CCR0_ena_ctrl = CCR_CS & FB_B[3] & (!nFB_WR);
+
+// SYS CTR
+//  $8006/2
+   assign SYS_CTR_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C003;
+   assign SYS_CTR0_clk_ctrl = MAIN_CLK;
+   assign SYS_CTR_d = FB_AD[22:16];
+   assign SYS_CTR0_ena_ctrl = SYS_CTR_CS & (!nFB_WR) & FB_B[3];
+   assign BLITTER_ON = !SYS_CTR_q[3];
+
+// VDL_LOF
+//  $820E/2
+   assign VDL_LOF_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C107;
+   assign VDL_LOF0_clk_ctrl = MAIN_CLK;
+   assign VDL_LOF_d = FB_AD[31:16];
+   assign VDL_LOF8_ena_ctrl = VDL_LOF_CS & (!nFB_WR) & FB_B[2];
+   assign VDL_LOF0_ena_ctrl = VDL_LOF_CS & (!nFB_WR) & FB_B[3];
+
+// VDL_LWD
+//  $8210/2
+   assign VDL_LWD_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C108;
+   assign VDL_LWD0_clk_ctrl = MAIN_CLK;
+   assign VDL_LWD_d = FB_AD[31:16];
+   assign VDL_LWD8_ena_ctrl = VDL_LWD_CS & (!nFB_WR) & FB_B[0];
+   assign VDL_LWD0_ena_ctrl = VDL_LWD_CS & (!nFB_WR) & FB_B[1];
+
+//  HORIZONTAL
+//  VDL_HHT
+//  $8282/2
+   assign VDL_HHT_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C141;
+   assign VDL_HHT0_clk_ctrl = MAIN_CLK;
+   assign VDL_HHT_d = FB_AD[27:16];
+   assign VDL_HHT8_ena_ctrl = VDL_HHT_CS & (!nFB_WR) & FB_B[2];
+   assign VDL_HHT0_ena_ctrl = VDL_HHT_CS & (!nFB_WR) & FB_B[3];
+
+//  VDL_HBE
+//  $8286/2
+   assign VDL_HBE_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C143;
+   assign VDL_HBE0_clk_ctrl = MAIN_CLK;
+   assign VDL_HBE_d = FB_AD[27:16];
+   assign VDL_HBE8_ena_ctrl = VDL_HBE_CS & (!nFB_WR) & FB_B[2];
+   assign VDL_HBE0_ena_ctrl = VDL_HBE_CS & (!nFB_WR) & FB_B[3];
+
+//  VDL_HDB
+//  $8288/2
+   assign VDL_HDB_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C144;
+   assign VDL_HDB0_clk_ctrl = MAIN_CLK;
+   assign VDL_HDB_d = FB_AD[27:16];
+   assign VDL_HDB8_ena_ctrl = VDL_HDB_CS & (!nFB_WR) & FB_B[0];
+   assign VDL_HDB0_ena_ctrl = VDL_HDB_CS & (!nFB_WR) & FB_B[1];
+
+//  VDL_HDE
+//  $828A/2
+   assign VDL_HDE_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C145;
+   assign VDL_HDE0_clk_ctrl = MAIN_CLK;
+   assign VDL_HDE_d = FB_AD[27:16];
+   assign VDL_HDE8_ena_ctrl = VDL_HDE_CS & (!nFB_WR) & FB_B[2];
+   assign VDL_HDE0_ena_ctrl = VDL_HDE_CS & (!nFB_WR) & FB_B[3];
+
+//  VDL_HBB
+//  $8284/2
+   assign VDL_HBB_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C142;
+   assign VDL_HBB0_clk_ctrl = MAIN_CLK;
+   assign VDL_HBB_d = FB_AD[27:16];
+   assign VDL_HBB8_ena_ctrl = VDL_HBB_CS & (!nFB_WR) & FB_B[0];
+   assign VDL_HBB0_ena_ctrl = VDL_HBB_CS & (!nFB_WR) & FB_B[1];
+
+//  VDL_HSS
+//  $828C/2
+   assign VDL_HSS_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C146;
+   assign VDL_HSS0_clk_ctrl = MAIN_CLK;
+   assign VDL_HSS_d = FB_AD[27:16];
+   assign VDL_HSS8_ena_ctrl = VDL_HSS_CS & (!nFB_WR) & FB_B[0];
+   assign VDL_HSS0_ena_ctrl = VDL_HSS_CS & (!nFB_WR) & FB_B[1];
+
+//  VERTIKAL
+//  VDL_VBE
+//  $82A6/2
+   assign VDL_VBE_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C153;
+   assign VDL_VBE0_clk_ctrl = MAIN_CLK;
+   assign VDL_VBE_d = FB_AD[26:16];
+   assign VDL_VBE8_ena_ctrl = VDL_VBE_CS & (!nFB_WR) & FB_B[2];
+   assign VDL_VBE0_ena_ctrl = VDL_VBE_CS & (!nFB_WR) & FB_B[3];
+
+//  VDL_VDB
+//  $82A8/2
+   assign VDL_VDB_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C154;
+   assign VDL_VDB0_clk_ctrl = MAIN_CLK;
+   assign VDL_VDB_d = FB_AD[26:16];
+   assign VDL_VDB8_ena_ctrl = VDL_VDB_CS & (!nFB_WR) & FB_B[0];
+   assign VDL_VDB0_ena_ctrl = VDL_VDB_CS & (!nFB_WR) & FB_B[1];
+
+//  VDL_VDE
+//  $82AA/2
+   assign VDL_VDE_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C155;
+   assign VDL_VDE0_clk_ctrl = MAIN_CLK;
+   assign VDL_VDE_d = FB_AD[26:16];
+   assign VDL_VDE8_ena_ctrl = VDL_VDE_CS & (!nFB_WR) & FB_B[2];
+   assign VDL_VDE0_ena_ctrl = VDL_VDE_CS & (!nFB_WR) & FB_B[3];
+
+//  VDL_VBB
+//  $82A4/2
+   assign VDL_VBB_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C152;
+   assign VDL_VBB0_clk_ctrl = MAIN_CLK;
+   assign VDL_VBB_d = FB_AD[26:16];
+   assign VDL_VBB8_ena_ctrl = VDL_VBB_CS & (!nFB_WR) & FB_B[0];
+   assign VDL_VBB0_ena_ctrl = VDL_VBB_CS & (!nFB_WR) & FB_B[1];
+
+//  VDL_VSS
+//  $82AC/2
+   assign VDL_VSS_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C156;
+   assign VDL_VSS0_clk_ctrl = MAIN_CLK;
+   assign VDL_VSS_d = FB_AD[26:16];
+   assign VDL_VSS8_ena_ctrl = VDL_VSS_CS & (!nFB_WR) & FB_B[0];
+   assign VDL_VSS0_ena_ctrl = VDL_VSS_CS & (!nFB_WR) & FB_B[1];
+
+//  VDL_VFT
+//  $82A2/2
+   assign VDL_VFT_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C151;
+   assign VDL_VFT0_clk_ctrl = MAIN_CLK;
+   assign VDL_VFT_d = FB_AD[26:16];
+   assign VDL_VFT8_ena_ctrl = VDL_VFT_CS & (!nFB_WR) & FB_B[2];
+   assign VDL_VFT0_ena_ctrl = VDL_VFT_CS & (!nFB_WR) & FB_B[3];
+
+//  VDL_VCT
+//  $82C0/2
+   assign VDL_VCT_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C160;
+   assign VDL_VCT0_clk_ctrl = MAIN_CLK;
+   assign VDL_VCT_d = FB_AD[24:16];
+   assign VDL_VCT8_ena = VDL_VCT_CS & (!nFB_WR) & FB_B[0];
+   assign VDL_VCT0_ena_ctrl = VDL_VCT_CS & (!nFB_WR) & FB_B[1];
+
+//  VDL_VMD
+//  $82C2/2
+   assign VDL_VMD_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C161;
+   assign VDL_VMD0_clk_ctrl = MAIN_CLK;
+   assign VDL_VMD_d = FB_AD[19:16];
+   assign VDL_VMD0_ena_ctrl = VDL_VMD_CS & (!nFB_WR) & FB_B[3];
+
+// - REGISTER OUT
+   assign u0_data = ({16{ST_SHIFT_MODE_CS}} & {6'b00_0000, ST_SHIFT_MODE_q,
+	 8'b0000_0000}) | ({16{FALCON_SHIFT_MODE_CS}} & {5'b0_0000,
+	 FALCON_SHIFT_MODE_q}) | ({16{SYS_CTR_CS}} & {9'b1_0000_0000,
+	 SYS_CTR_q[6:4], !BLITTER_RUN, SYS_CTR_q[2:0]}) | ({16{VDL_LOF_CS}} &
+	 VDL_LOF_q) | ({16{VDL_LWD_CS}} & VDL_LWD_q) | ({16{VDL_HBE_CS}} &
+	 {4'b0000, VDL_HBE_q}) | ({16{VDL_HDB_CS}} & {4'b0000, VDL_HDB_q}) |
+	 ({16{VDL_HDE_CS}} & {4'b0000, VDL_HDE_q}) | ({16{VDL_HBB_CS}} &
+	 {4'b0000, VDL_HBB_q}) | ({16{VDL_HSS_CS}} & {4'b0000, VDL_HSS_q}) |
+	 ({16{VDL_HHT_CS}} & {4'b0000, VDL_HHT_q}) | ({16{VDL_VBE_CS}} &
+	 {5'b0_0000, VDL_VBE_q}) | ({16{VDL_VDB_CS}} & {5'b0_0000, VDL_VDB_q})
+	 | ({16{VDL_VDE_CS}} & {5'b0_0000, VDL_VDE_q}) | ({16{VDL_VBB_CS}} &
+	 {5'b0_0000, VDL_VBB_q}) | ({16{VDL_VSS_CS}} & {5'b0_0000, VDL_VSS_q})
+	 | ({16{VDL_VFT_CS}} & {5'b0_0000, VDL_VFT_q}) | ({16{VDL_VCT_CS}} &
+	 {7'b000_0000, VDL_VCT_q}) | ({16{VDL_VMD_CS}} & {12'b0000_0000_0000,
+	 VDL_VMD_q}) | ({16{ACP_VCTR_CS}} & ACP_VCTR_q[31:16]) |
+	 ({16{ATARI_HH_CS}} & ATARI_HH_q[31:16]) | ({16{ATARI_VH_CS}} &
+	 ATARI_VH_q[31:16]) | ({16{ATARI_HL_CS}} & ATARI_HL_q[31:16]) |
+	 ({16{ATARI_VL_CS}} & ATARI_VL_q[31:16]) | ({16{CCR_CS}} &
+	 {8'b0000_0000, CCR_q[23:16]}) | ({16{VIDEO_PLL_CONFIG_CS}} &
+	 {7'b000_0000, VR_DOUT_q}) | ({16{VIDEO_PLL_RECONFIG_CS}} & {VR_BUSY,
+	 4'b0000, VR_WR_q, VR_RD, VIDEO_RECONFIG_q, 8'b1111_1010});
+   assign u0_enabledt = (ST_SHIFT_MODE_CS | FALCON_SHIFT_MODE_CS | ACP_VCTR_CS
+	 | CCR_CS | SYS_CTR_CS | VDL_LOF_CS | VDL_LWD_CS | VDL_HBE_CS |
+	 VDL_HDB_CS | VDL_HDE_CS | VDL_HBB_CS | VDL_HSS_CS | VDL_HHT_CS |
+	 ATARI_HH_CS | ATARI_VH_CS | ATARI_HL_CS | ATARI_VL_CS |
+	 VIDEO_PLL_CONFIG_CS | VIDEO_PLL_RECONFIG_CS | VDL_VBE_CS | VDL_VDB_CS
+	 | VDL_VDE_CS | VDL_VBB_CS | VDL_VSS_CS | VDL_VFT_CS | VDL_VCT_CS |
+	 VDL_VMD_CS) & (!nFB_OE);
+   //GE assign FB_AD[31:16] = u0_tridata;
+	 assign FB_AD[31:16] = (u0_enabledt ? u0_data : 16'bzzzz_zzzz_zzzz_zzzz);
+   assign u1_data = ({16{ACP_VCTR_CS}} & ACP_VCTR_q[15:0]) | ({16{ATARI_HH_CS}}
+	 & ATARI_HH_q[15:0]) | ({16{ATARI_VH_CS}} & ATARI_VH_q[15:0]) |
+	 ({16{ATARI_HL_CS}} & ATARI_HL_q[15:0]) | ({16{ATARI_VL_CS}} &
+	 ATARI_VL_q[15:0]) | ({16{CCR_CS}} & CCR_q[15:0]);
+   assign u1_enabledt = (ACP_VCTR_CS | CCR_CS | ATARI_HH_CS | ATARI_VH_CS |
+	 ATARI_HL_CS | ATARI_VL_CS) & (!nFB_OE);
+   //GE assign FB_AD[15:0] = u1_tridata;
+	 assign FB_AD[15:0] = (u1_enabledt ? u1_data : 16'bzzzz_zzzz_zzzz_zzzz);
+	 
+   assign VIDEO_MOD_TA = CLUT_TA_q | ST_SHIFT_MODE_CS | FALCON_SHIFT_MODE_CS |
+	 ACP_VCTR_CS | SYS_CTR_CS | VDL_LOF_CS | VDL_LWD_CS | VDL_HBE_CS |
+	 VDL_HDB_CS | VDL_HDE_CS | VDL_HBB_CS | VDL_HSS_CS | VDL_HHT_CS |
+	 ATARI_HH_CS | ATARI_VH_CS | ATARI_HL_CS | ATARI_VL_CS | VDL_VBE_CS |
+	 VDL_VDB_CS | VDL_VDE_CS | VDL_VBB_CS | VDL_VSS_CS | VDL_VFT_CS |
+	 VDL_VCT_CS | VDL_VMD_CS;
+
+//  VIDEO AUSGABE SETZEN
+   assign CLK17M_clk = CLK33M;
+   assign CLK17M_d = !CLK17M_q;
+   assign CLK13M_clk = CLK25M;
+   assign CLK13M_d = !CLK13M_q;
+   assign PIXEL_CLK = (CLK13M_q & (!ACP_VIDEO_ON) & (FALCON_VIDEO | ST_VIDEO) &
+	 ((VDL_VMD_q[2] & VDL_VCT_q[2]) | VDL_VCT_q[0])) | (CLK17M_q &
+	 (!ACP_VIDEO_ON) & (FALCON_VIDEO | ST_VIDEO) & ((VDL_VMD_q[2] &
+	 (!VDL_VCT_q[2])) | VDL_VCT_q[0])) | (CLK25M & (!ACP_VIDEO_ON) &
+	 (FALCON_VIDEO | ST_VIDEO) & (!VDL_VMD_q[2]) & VDL_VCT_q[2] &
+	 (!VDL_VCT_q[0])) | (CLK33M & (!ACP_VIDEO_ON) & (FALCON_VIDEO |
+	 ST_VIDEO) & (!VDL_VMD_q[2]) & (!VDL_VCT_q[2]) & (!VDL_VCT_q[0])) |
+	 (CLK25M & ACP_VIDEO_ON & ACP_VCTR_q[9:8] == 2'b00) | (CLK33M &
+	 ACP_VIDEO_ON & ACP_VCTR_q[9:8] == 2'b01) | (CLK_VIDEO & ACP_VIDEO_ON &
+	 ACP_VCTR_q[9]);
+
+// ------------------------------------------------------------
+//  HORIZONTALE SYNC LÄNGE in PIXEL_CLK
+// --------------------------------------------------------------
+   assign HSY_LEN0_clk_ctrl = MAIN_CLK;
+
+//  hsync puls length in pixeln=frequenz/ = 500ns
+   assign HSY_LEN_d = (8'b0000_1110 & {8{!ACP_VIDEO_ON}} & ({8{FALCON_VIDEO}} |
+	 {8{ST_VIDEO}}) & (({8{VDL_VMD_q[2]}} & {8{VDL_VCT_q[2]}}) |
+	 {8{VDL_VCT_q[0]}})) | (8'b0001_0000 & {8{!ACP_VIDEO_ON}} &
+	 ({8{FALCON_VIDEO}} | {8{ST_VIDEO}}) & (({8{VDL_VMD_q[2]}} &
+	 {8{!VDL_VCT_q[2]}}) | {8{VDL_VCT_q[0]}})) | (8'b0001_1100 &
+	 {8{!ACP_VIDEO_ON}} & ({8{FALCON_VIDEO}} | {8{ST_VIDEO}}) &
+	 {8{!VDL_VMD_q[2]}} & {8{VDL_VCT_q[2]}} & {8{!VDL_VCT_q[0]}}) |
+	 (8'b0010_0000 & {8{!ACP_VIDEO_ON}} & ({8{FALCON_VIDEO}} |
+	 {8{ST_VIDEO}}) & {8{!VDL_VMD_q[2]}} & {8{!VDL_VCT_q[2]}} &
+	 {8{!VDL_VCT_q[0]}}) | (8'b0001_1100 & {8{ACP_VIDEO_ON}} &
+	 {8{ACP_VCTR_q[9:8] == 2'b00}}) | (8'b0010_0000 & {8{ACP_VIDEO_ON}} &
+	 {8{ACP_VCTR_q[9:8] == 2'b01}}) | ((8'b0001_0000 + {1'b0,
+	 VR_FRQ_q[7:1]}) & {8{ACP_VIDEO_ON}} & {8{ACP_VCTR_q[9]}});
+
+//  MULTIPLIKATIONS FAKTOR
+   assign MULF = (6'b00_0010 & {6{!ST_VIDEO}} & {6{VDL_VMD_q[2]}}) |
+	 (6'b00_0100 & {6{!ST_VIDEO}} & {6{!VDL_VMD_q[2]}}) | (6'b01_0000 &
+	 {6{ST_VIDEO}} & {6{VDL_VMD_q[2]}}) | (6'b10_0000 & {6{ST_VIDEO}} &
+	 {6{!VDL_VMD_q[2]}});
+
+//  BREITE IN PIXELN
+   assign HDIS_LEN = (12'b0001_0100_0000 & {12{VDL_VMD_q[2]}}) |
+	 (12'b0010_1000_0000 & {12{!VDL_VMD_q[2]}});
+
+//  DOPPELZEILENMODUS
+   assign DOP_ZEI_clk = MAIN_CLK;
+
+//  ZEILENVERDOPPELUNG EIN AUS
+   assign DOP_ZEI_d = VDL_VMD_q[0] & ST_VIDEO;
+   assign INTER_ZEI_clk = PIXEL_CLK;
+
+//  EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
+//  EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
+   assign INTER_ZEI_d = (DOP_ZEI_q & VVCNT_q[0] != VDIS_START[0] & VVCNT_q !=
+	 11'b000_0000_0000 & VHCNT_q < (HDIS_END - 12'b0000_0000_0001)) |
+	 (DOP_ZEI_q & VVCNT_q[0] == VDIS_START[0] & VVCNT_q !=
+	 11'b000_0000_0000 & VHCNT_q > (HDIS_END - 12'b0000_0000_0010));
+   assign DOP_FIFO_CLR_clk = PIXEL_CLK;
+
+//  DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
+   assign DOP_FIFO_CLR_d = (INTER_ZEI_q & HSYNC_START_q) | SYNC_PIX_q;
+
+	 
+	 wire [11:0] HTF;
+	 wire [11:0] HSF;
+//  GE
+   // assign RAND_LINKS_FULL = VDL_HBE_q * {7'b000_0000, MULF[5:1]};
+	 assign RAND_LINKS_FULL = ({12{MULF[1]}} & {12'd0, VDL_HBE_q})
+													| ({12{MULF[2]}} & {11'd0, VDL_HBE_q, 1'd0})
+													| ({12{MULF[3]}} & {10'd0, VDL_HBE_q, 2'd0})
+													| ({12{MULF[4]}} & {9'd0, VDL_HBE_q, 3'd0})
+													| ({12{MULF[5]}} & {8'd0, VDL_HBE_q, 4'd0});
+
+	
+//  GE
+   //assign HS_START_FULL = ((VDL_HHT_q + 24'h1) + VDL_HSS_q) * {7'b000_0000,
+	 // MULF[5:1]};
+	 assign HSF = ((VDL_HHT_q + 12'h1) + VDL_HSS_q);
+	 assign HS_START_FULL   = ({12{MULF[1]}} & {12'd0, HSF})
+													| ({12{MULF[2]}} & {11'd0, HSF, 1'd0})
+													| ({12{MULF[3]}} & {10'd0, HSF, 2'd0})
+													| ({12{MULF[4]}} & {9'd0, HSF, 3'd0})
+													| ({12{MULF[5]}} & {8'd0, HSF, 4'd0});
+
+//  GE
+   // assign H_TOTAL_FULL = (VDL_HHT_q + 24'h2) * {6'b00_0000, MULF};
+	 assign HTF = (VDL_HHT_q + 12'h2);
+	 assign H_TOTAL_FULL    = ({12{MULF[0]}} & {12'd0, HTF})
+													| ({12{MULF[1]}} & {11'd0, HTF, 1'd0})
+													| ({12{MULF[2]}} & {10'd0, HTF, 2'd0})
+													| ({12{MULF[3]}} & {9'd0, HTF, 3'd0})
+													| ({12{MULF[4]}} & {8'd0, HTF, 4'd0})
+													| ({12{MULF[5]}} & {7'd0, HTF, 5'd0});
+	 
+   assign RAND_LINKS = (VDL_HBE_q & {12{ACP_VIDEO_ON}}) | (12'b0000_0001_0101 &
+	 {12{!ACP_VIDEO_ON}} & {12{ATARI_SYNC}} & {12{VDL_VMD_q[2]}}) |
+	 (12'b0000_0010_1010 & {12{!ACP_VIDEO_ON}} & {12{ATARI_SYNC}} &
+	 {12{!VDL_VMD_q[2]}}) | (RAND_LINKS_FULL[11:0] & {12{!ACP_VIDEO_ON}} &
+	 {12{!ATARI_SYNC}});
+   assign HDIS_START = (VDL_HDB_q & {12{ACP_VIDEO_ON}}) | ((RAND_LINKS +
+	 12'b0000_0000_0001) & {12{!ACP_VIDEO_ON}});
+   assign HDIS_END = (VDL_HDE_q & {12{ACP_VIDEO_ON}}) | ((RAND_LINKS +
+	 HDIS_LEN) & {12{!ACP_VIDEO_ON}});
+   assign RAND_RECHTS = (VDL_HBB_q & {12{ACP_VIDEO_ON}}) | ((HDIS_END +
+	 12'b0000_0000_0001) & {12{!ACP_VIDEO_ON}});
+   assign HS_START = (VDL_HSS_q & {12{ACP_VIDEO_ON}}) | (ATARI_HL_q[11:0] &
+	 {12{!ACP_VIDEO_ON}} & {12{ATARI_SYNC}} & {12{VDL_VMD_q[2]}}) |
+	 (ATARI_HH_q[11:0] & {12{!ACP_VIDEO_ON}} & {12{ATARI_SYNC}} &
+	 {12{!VDL_VMD_q[2]}}) | (HS_START_FULL[11:0] & {12{!ACP_VIDEO_ON}} &
+	 {12{!ATARI_SYNC}});
+   assign H_TOTAL = (VDL_HHT_q & {12{ACP_VIDEO_ON}}) | (ATARI_HL_q[27:16] &
+	 {12{!ACP_VIDEO_ON}} & {12{ATARI_SYNC}} & {12{VDL_VMD_q[2]}}) |
+	 (ATARI_HH_q[27:16] & {12{!ACP_VIDEO_ON}} & {12{ATARI_SYNC}} &
+	 {12{!VDL_VMD_q[2]}}) | (H_TOTAL_FULL[11:0] & {12{!ACP_VIDEO_ON}} &
+	 {12{!ATARI_SYNC}});
+   assign RAND_OBEN = (VDL_VBE_q & {11{ACP_VIDEO_ON}}) | (11'b000_0001_1111 &
+	 {11{!ACP_VIDEO_ON}} & {11{ATARI_SYNC}}) | ({1'b0, VDL_VBE_q[10:1]} &
+	 {11{!ACP_VIDEO_ON}} & {11{!ATARI_SYNC}});
+   assign VDIS_START = (VDL_VDB_q & {11{ACP_VIDEO_ON}}) | (11'b000_0010_0000 &
+	 {11{!ACP_VIDEO_ON}} & {11{ATARI_SYNC}}) | (({1'b0, VDL_VDB_q[10:1]} +
+	 11'b000_0000_0001) & {11{!ACP_VIDEO_ON}} & {11{!ATARI_SYNC}});
+   assign VDIS_END = (VDL_VDE_q & {11{ACP_VIDEO_ON}}) | (11'b001_1010_1111 &
+	 {11{!ACP_VIDEO_ON}} & {11{ATARI_SYNC}} & {11{ST_VIDEO}}) |
+	 (11'b001_1111_1111 & {11{!ACP_VIDEO_ON}} & {11{ATARI_SYNC}} &
+	 {11{!ST_VIDEO}}) | ({1'b0, VDL_VDE_q[10:1]} & {11{!ACP_VIDEO_ON}} &
+	 {11{!ATARI_SYNC}});
+   assign RAND_UNTEN = (VDL_VBB_q & {11{ACP_VIDEO_ON}}) | ((VDIS_END +
+	 11'b000_0000_0001) & {11{!ACP_VIDEO_ON}} & {11{ATARI_SYNC}}) |
+	 (({1'b0, VDL_VBB_q[10:1]} + 11'b000_0000_0001) & {11{!ACP_VIDEO_ON}} &
+	 {11{!ATARI_SYNC}});
+   assign VS_START = (VDL_VSS_q & {11{ACP_VIDEO_ON}}) | (ATARI_VL_q[10:0] &
+	 {11{!ACP_VIDEO_ON}} & {11{ATARI_SYNC}} & {11{VDL_VMD_q[2]}}) |
+	 (ATARI_VH_q[10:0] & {11{!ACP_VIDEO_ON}} & {11{ATARI_SYNC}} &
+	 {11{!VDL_VMD_q[2]}}) | ({1'b0, VDL_VSS_q[10:1]} & {11{!ACP_VIDEO_ON}}
+	 & {11{!ATARI_SYNC}});
+   assign V_TOTAL = (VDL_VFT_q & {11{ACP_VIDEO_ON}}) | (ATARI_VL_q[26:16] &
+	 {11{!ACP_VIDEO_ON}} & {11{ATARI_SYNC}} & {11{VDL_VMD_q[2]}}) |
+	 (ATARI_VH_q[26:16] & {11{!ACP_VIDEO_ON}} & {11{ATARI_SYNC}} &
+	 {11{!VDL_VMD_q[2]}}) | ({1'b0, VDL_VFT_q[10:1]} & {11{!ACP_VIDEO_ON}}
+	 & {11{!ATARI_SYNC}});
+
+//  ZÄHLER
+   assign LAST_clk = PIXEL_CLK;
+   assign LAST_d = VHCNT_q == (H_TOTAL - 12'b0000_0000_0010);
+   assign VHCNT0_clk_ctrl = PIXEL_CLK;
+   assign VHCNT_d = (VHCNT_q + 12'b0000_0000_0001) & {12{!LAST_q}};
+   assign VVCNT0_clk_ctrl = PIXEL_CLK;
+   assign VVCNT0_ena_ctrl = LAST_q;
+   assign VVCNT_d = (VVCNT_q + 11'b000_0000_0001) & {11{VVCNT_q != (V_TOTAL -
+	 11'b000_0000_0001)}};
+
+//  DISPLAY ON OFF
+   assign DPO_ZL_clk = PIXEL_CLK;
+
+//  1 ZEILE DAVOR ON OFF
+   assign DPO_ZL_d = VVCNT_q > (RAND_OBEN - 11'b000_0000_0001) & VVCNT_q <
+	 (RAND_UNTEN - 11'b000_0000_0001);
+
+//  AM ZEILENENDE ÜBERNEHMEN
+   assign DPO_ZL_ena = LAST_q;
+   assign DPO_ON_clk = PIXEL_CLK;
+
+//  BESSER EINZELN WEGEN TIMING
+   assign DPO_ON_d = VHCNT_q == RAND_LINKS;
+   assign DPO_OFF_clk = PIXEL_CLK;
+   assign DPO_OFF_d = VHCNT_q == (RAND_RECHTS - 12'b0000_0000_0001);
+   assign DISP_ON_clk = PIXEL_CLK;
+   assign DISP_ON_d = (DISP_ON_q & (!DPO_OFF_q)) | (DPO_ON_q & DPO_ZL_q);
+
+//  DATENTRANSFER ON OFF
+   assign VDO_ON_clk = PIXEL_CLK;
+
+//  BESSER EINZELN WEGEN TIMING
+   assign VDO_ON_d = VHCNT_q == (HDIS_START - 12'b0000_0000_0001);
+   assign VDO_OFF_clk = PIXEL_CLK;
+   assign VDO_OFF_d = VHCNT_q == HDIS_END;
+   assign VDO_ZL_clk = PIXEL_CLK;
+
+//  AM ZEILENENDE ÜBERNEHMEN
+   assign VDO_ZL_ena = LAST_q;
+
+//  1 ZEILE DAVOR ON OFF
+   assign VDO_ZL_d = VVCNT_q >= (VDIS_START - 11'b000_0000_0001) & VVCNT_q <
+	 VDIS_END;
+   assign VDTRON_clk = PIXEL_CLK;
+   assign VDTRON_d = (VDTRON_q & (!VDO_OFF_q)) | (VDO_ON_q & VDO_ZL_q);
+
+//  VERZÖGERUNG UND SYNC
+   assign HSYNC_START_clk = PIXEL_CLK;
+   assign HSYNC_START_d = VHCNT_q == (HS_START - 12'b0000_0000_0011);
+   assign HSYNC_I0_clk_ctrl = PIXEL_CLK;
+   assign HSYNC_I_d = (HSY_LEN_q & {8{HSYNC_START_q}}) | ((HSYNC_I_q -
+	 8'b0000_0001) & {8{!HSYNC_START_q}} & {8{HSYNC_I_q != 8'b0000_0000}});
+   assign VSYNC_START_clk = PIXEL_CLK;
+   assign VSYNC_START_ena = LAST_q;
+
+//  start am ende der Zeile vor dem vsync
+   assign VSYNC_START_d = VVCNT_q == (VS_START - 11'b000_0000_0011);
+   assign VSYNC_I0_clk_ctrl = PIXEL_CLK;
+
+//  start am ende der Zeile vor dem vsync
+   assign VSYNC_I0_ena_ctrl = LAST_q;
+
+//  3 zeilen vsync length
+//  runterzählen bis 0
+   assign VSYNC_I_d = (3'b011 & {3{VSYNC_START_q}}) | ((VSYNC_I_q - 3'b001) &
+	 {3{!VSYNC_START_q}} & {3{VSYNC_I_q != 3'b000}});
+   assign VERZ2_0_clk_ctrl = PIXEL_CLK;
+   assign VERZ1_0_clk_ctrl = PIXEL_CLK;
+   assign VERZ0_0_clk_ctrl = PIXEL_CLK;
+   assign {VERZ2__d[1], VERZ1__d[1], VERZ0__d[1]} = {VERZ2__q[0], VERZ1__q[0],
+	 VERZ0__q[0]};
+   assign {VERZ2__d[2], VERZ1__d[2], VERZ0__d[2]} = {VERZ2__q[1], VERZ1__q[1],
+	 VERZ0__q[1]};
+   assign {VERZ2__d[3], VERZ1__d[3], VERZ0__d[3]} = {VERZ2__q[2], VERZ1__q[2],
+	 VERZ0__q[2]};
+   assign {VERZ2__d[4], VERZ1__d[4], VERZ0__d[4]} = {VERZ2__q[3], VERZ1__q[3],
+	 VERZ0__q[3]};
+   assign {VERZ2__d[5], VERZ1__d[5], VERZ0__d[5]} = {VERZ2__q[4], VERZ1__q[4],
+	 VERZ0__q[4]};
+   assign {VERZ2__d[6], VERZ1__d[6], VERZ0__d[6]} = {VERZ2__q[5], VERZ1__q[5],
+	 VERZ0__q[5]};
+   assign {VERZ2__d[7], VERZ1__d[7], VERZ0__d[7]} = {VERZ2__q[6], VERZ1__q[6],
+	 VERZ0__q[6]};
+   assign {VERZ2__d[8], VERZ1__d[8], VERZ0__d[8]} = {VERZ2__q[7], VERZ1__q[7],
+	 VERZ0__q[7]};
+   assign {VERZ2__d[9], VERZ1__d[9], VERZ0__d[9]} = {VERZ2__q[8], VERZ1__q[8],
+	 VERZ0__q[8]};
+   assign VERZ0__d[0] = DISP_ON_q;
+   assign VERZ1_0_d_1 = HSYNC_I_q != 8'b0000_0000;
+
+//  NUR MÖGLICH WENN BEIDE
+   assign VERZ1_0_d_2 = (((!ACP_VCTR_q[15]) | (!VDL_VCT_q[6])) & HSYNC_I_q !=
+	 8'b0000_0000) | (ACP_VCTR_q[15] & VDL_VCT_q[6] & HSYNC_I_q ==
+	 8'b0000_0000);
+
+//  NUR MÖGLICH WENN BEIDE
+   assign VERZ2__d[0] = (((!ACP_VCTR_q[15]) | (!VDL_VCT_q[5])) & VSYNC_I_q !=
+	 3'b000) | (ACP_VCTR_q[15] & VDL_VCT_q[5] & VSYNC_I_q == 3'b000);
+   assign nBLANK_clk = PIXEL_CLK;
+   assign nBLANK_d = VERZ0__q[8];
+   assign HSYNC_clk = PIXEL_CLK;
+   assign HSYNC_d = VERZ1__q[9];
+   assign VSYNC_clk = PIXEL_CLK;
+   assign VSYNC_d = VERZ2__q[9];
+   assign nSYNC = gnd;
+
+//  RANDFARBE MACHEN ------------------------------------
+   assign RAND0_clk_ctrl = PIXEL_CLK;
+   assign RAND_d[0] = DISP_ON_q & (!VDTRON_q) & ACP_VCTR_q[25];
+   assign RAND_d[1] = RAND_q[0];
+   assign RAND_d[2] = RAND_q[1];
+   assign RAND_d[3] = RAND_q[2];
+   assign RAND_d[4] = RAND_q[3];
+   assign RAND_d[5] = RAND_q[4];
+   assign RAND_d[6] = RAND_q[5];
+   assign RAND_ON = RAND_q[6];
+
+// --------------------------------------------------------
+   assign CLR_FIFO_clk = PIXEL_CLK;
+   assign CLR_FIFO_ena = LAST_q;
+
+//  IN LETZTER ZEILE LÖSCHEN
+   assign CLR_FIFO_d = VVCNT_q == (V_TOTAL - 11'b000_0000_0010);
+   assign START_ZEILE_clk = PIXEL_CLK;
+   assign START_ZEILE_ena = LAST_q;
+
+//  ZEILE 1
+   assign START_ZEILE_d = VVCNT_q == 11'b000_0000_0000;
+   assign SYNC_PIX_clk = PIXEL_CLK;
+
+//  SUB PIXEL ZÄHLER SYNCHRONISIEREN
+   assign SYNC_PIX_d = VHCNT_q == 12'b0000_0000_0011 & START_ZEILE_q;
+   assign SYNC_PIX1_clk = PIXEL_CLK;
+
+//  SUB PIXEL ZÄHLER SYNCHRONISIEREN
+   assign SYNC_PIX1_d = VHCNT_q == 12'b0000_0000_0101 & START_ZEILE_q;
+   assign SYNC_PIX2_clk = PIXEL_CLK;
+
+//  SUB PIXEL ZÄHLER SYNCHRONISIEREN
+   assign SYNC_PIX2_d = VHCNT_q == 12'b0000_0000_0111 & START_ZEILE_q;
+   assign SUB_PIXEL_CNT0_clk_ctrl = PIXEL_CLK;
+   assign SUB_PIXEL_CNT0_ena_ctrl = VDTRON_q | SYNC_PIX_q;
+
+// count up if display on sonst clear bei sync pix
+   assign SUB_PIXEL_CNT_d = (SUB_PIXEL_CNT_q + 7'b000_0001) & {7{!SYNC_PIX_q}};
+   assign FIFO_RDE_clk = PIXEL_CLK;
+
+//  3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
+   assign FIFO_RDE_d = (((SUB_PIXEL_CNT_q == 7'b000_0001 & COLOR1) |
+	 (SUB_PIXEL_CNT_q[5:0] == 6'b00_0001 & COLOR2) | (SUB_PIXEL_CNT_q[4:0]
+	 == 5'b0_0001 & COLOR4) | (SUB_PIXEL_CNT_q[3:0] == 4'b0001 & COLOR8) |
+	 (SUB_PIXEL_CNT_q[2:0] == 3'b001 & COLOR16) | (SUB_PIXEL_CNT_q[1:0] ==
+	 2'b01 & COLOR24)) & VDTRON_q) | SYNC_PIX_q | SYNC_PIX1_q |
+	 SYNC_PIX2_q;
+   assign CLUT_MUX_ADR0_clk_ctrl = PIXEL_CLK;
+   assign CLUT_MUX_AV1_0_clk_ctrl = PIXEL_CLK;
+   assign CLUT_MUX_AV0_0_clk_ctrl = PIXEL_CLK;
+   assign CLUT_MUX_AV0__d = SUB_PIXEL_CNT_q[3:0];
+   assign CLUT_MUX_AV1__d = CLUT_MUX_AV0__q;
+   assign CLUT_MUX_ADR_d = CLUT_MUX_AV1__q;
+
+
+// Assignments added to explicitly combine the
+// effects of multiple drivers in the source
+   assign COLOR16 = COLOR16_1 | COLOR16_2;
+   assign VERZ1__d[0] = VERZ1_0_d_1 | VERZ1_0_d_2;
+   assign COLOR4 = COLOR4_1 | COLOR4_2;
+   assign COLOR1 = COLOR1_1 | COLOR1_2 | COLOR1_3;
+   assign COLOR8 = COLOR8_1 | COLOR8_2;
+
+// Define power signal(s)
+   assign gnd = 1'b0;
+endmodule
diff --git a/FPGA_quartus_GE/Video/Video.bdf b/FPGA_quartus_GE/Video/Video.bdf
new file mode 100644
index 0000000..6210cb7
--- /dev/null
+++ b/FPGA_quartus_GE/Video/Video.bdf
@@ -0,0 +1,10651 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "graphic" (version "1.3"))
+(properties
+	(page_setup "header_footer\nDate: %D\n%f\nProject: %j\n\nPage %p of %P\nRevision: %a\nmargin\n1\n1\n1\n1\norientation\n2\npaper_size\n9\npaper_source\n15\nfit_page_wide\n1\nfit_page_tall\n1\n")
+)
+(pin
+	(input)
+	(rect 184 1192 352 1208)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "FB_ADR[31..0]" (rect 9 0 103 15)(font "Arial" ))
+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
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+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
+	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect 184 1248 352 1264)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "MAIN_CLK" (rect 9 0 78 15)(font "Arial" ))
+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
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+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
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+)
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+	(input)
+	(rect 184 1352 352 1368)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "nFB_CS1" (rect 9 0 71 15)(font "Arial" ))
+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
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+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
+	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+)
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+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "nFB_CS2" (rect 9 0 71 15)(font "Arial" ))
+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
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+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
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+)
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+	(input)
+	(rect 184 1416 352 1432)
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+	(pt 168 8)
+	(connected_pin (pt 0 0))
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+)
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+	(connected_pin (pt 0 0))
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+)
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+	(text "FB_SIZE0" (rect 9 0 73 15)(font "Arial" ))
+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
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+		(line (pt 92 12)(pt 92 4)(line_width 1))
+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
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+)
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+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
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+	(pt 168 8)
+	(connected_pin (pt 0 0))
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+	(pt 168 8)
+	(connected_pin (pt 0 0))
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+	(pt 168 8)
+	(connected_pin (pt 0 0))
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+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
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+)
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+	(pt 168 8)
+	(connected_pin (pt 0 0))
+	(drawing
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+	)
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+)
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+	(rect 184 1312 352 1328)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "DDRCLK[3..0]" (rect 9 0 99 15)(font "Arial" ))
+	(pt 168 8)
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+)
+(connector
+	(text "CLUT_MUX_ADR[3..0]" (rect 2026 2152 2169 2167)(font "Arial" ))
+	(pt 2016 2168)
+	(pt 2120 2168)
+	(bus)
+)
+(connector
+	(text "HSYNC" (rect 2026 2248 2075 2263)(font "Arial" ))
+	(pt 2104 2264)
+	(pt 2016 2264)
+)
+(connector
+	(text "VSYNC" (rect 2026 2272 2073 2287)(font "Arial" ))
+	(pt 2104 2288)
+	(pt 2016 2288)
+)
+(connector
+	(text "nBLANK" (rect 2026 2296 2080 2311)(font "Arial" ))
+	(pt 2104 2312)
+	(pt 2016 2312)
+)
+(connector
+	(text "nSYNC" (rect 2026 2320 2073 2335)(font "Arial" ))
+	(pt 2104 2336)
+	(pt 2016 2336)
+)
+(connector
+	(text "nPD_VGA" (rect 2026 2344 2089 2359)(font "Arial" ))
+	(pt 2104 2360)
+	(pt 2016 2360)
+)
+(connector
+	(text "CLUT_OFF[3..0]" (rect 2026 2072 2129 2087)(font "Arial" ))
+	(pt 2016 2088)
+	(pt 2112 2088)
+	(bus)
+)
+(connector
+	(text "BLITTER_ON" (rect 2026 2488 2113 2503)(font "Arial" ))
+	(pt 2096 2504)
+	(pt 2016 2504)
+)
+(connector
+	(text "VIDEO_RAM_CTR[15..0]" (rect 2026 2368 2182 2383)(font "Arial" ))
+	(pt 2144 2384)
+	(pt 2016 2384)
+	(bus)
+)
+(connector
+	(text "CCR[23..0]" (rect 2026 2176 2096 2191)(font "Arial" ))
+	(pt 2096 2192)
+	(pt 2016 2192)
+	(bus)
+)
+(connector
+	(text "CCSEL[2..0]" (rect 2026 2200 2105 2215)(font "Arial" ))
+	(pt 2016 2216)
+	(pt 2096 2216)
+	(bus)
+)
+(connector
+	(text "ACP_CLUT_WR[3..0]" (rect 2026 1944 2162 1959)(font "Arial" ))
+	(pt 2136 1960)
+	(pt 2016 1960)
+	(bus)
+)
+(connector
+	(text "FALCON_CLUT_WR[3..0]" (rect 2026 2048 2191 2063)(font "Arial" ))
+	(pt 2144 2064)
+	(pt 2016 2064)
+	(bus)
+)
+(connector
+	(text "INTER_ZEI" (rect 2026 2400 2097 2415)(font "Arial" ))
+	(pt 2016 2416)
+	(pt 2136 2416)
+)
+(connector
+	(text "DOP_FIFO_CLR" (rect 2026 2424 2133 2439)(font "Arial" ))
+	(pt 2016 2440)
+	(pt 2128 2440)
+)
+(connector
+	(text "VIDEO_MOD_TA" (rect 2026 2520 2133 2535)(font "Arial" ))
+	(pt 2088 2536)
+	(pt 2016 2536)
+)
+(connector
+	(text "BLITTER_RUN" (rect 1546 2528 1643 2543)(font "Arial" ))
+	(pt 1664 2544)
+	(pt 1536 2544)
+)
+(connector
+	(pt 1888 1120)
+	(pt 1888 1160)
+	(bus)
+)
+(connector
+	(text "VDM_SEL[3..0]" (rect 1810 1144 1905 1159)(font "Arial" ))
+	(pt 1888 1160)
+	(pt 1800 1160)
+	(bus)
+)
+(connector
+	(pt 1608 1432)
+	(pt 1608 1232)
+)
+(connector
+	(pt 1600 1432)
+	(pt 1608 1432)
+)
+(connector
+	(pt 1608 1432)
+	(pt 1712 1432)
+)
+(connector
+	(pt 1608 1232)
+	(pt 2072 1232)
+)
+(connector
+	(pt 2072 1248)
+	(pt 1944 1248)
+)
+(connector
+	(pt 1944 1248)
+	(pt 1944 1296)
+)
+(connector
+	(pt 1944 1296)
+	(pt 1920 1296)
+)
+(connector
+	(text "FIFO_RDE" (rect 1770 1272 1839 1287)(font "Arial" ))
+	(pt 1760 1288)
+	(pt 1856 1288)
+)
+(connector
+	(text "INTER_ZEI" (rect 1762 1288 1833 1303)(font "Arial" ))
+	(pt 1752 1304)
+	(pt 1856 1304)
+)
+(connector
+	(text "CLK33M" (rect 1586 2168 1641 2183)(font "Arial" ))
+	(pt 1512 2184)
+	(pt 1664 2184)
+)
+(connector
+	(text "CLK25M" (rect 1586 2192 1641 2207)(font "Arial" ))
+	(pt 1512 2208)
+	(pt 1664 2208)
+)
+(connector
+	(text "CLK_VIDEO" (rect 1570 2144 1649 2159)(font "Arial" ))
+	(pt 1512 2160)
+	(pt 1664 2160)
+)
+(connector
+	(text "VIDEO_MOD_TA" (rect 258 1816 365 1831)(font "Arial" ))
+	(pt 264 1832)
+	(pt 360 1832)
+)
+(connector
+	(text "COLOR8" (rect 2026 1912 2085 1927)(font "Arial" ))
+	(pt 2016 1928)
+	(pt 2120 1928)
+)
+(connector
+	(text "COLOR4" (rect 2026 1896 2085 1911)(font "Arial" ))
+	(pt 2016 1912)
+	(pt 2120 1912)
+)
+(connector
+	(text "COLOR2" (rect 2026 1880 2085 1895)(font "Arial" ))
+	(pt 2016 1896)
+	(pt 2120 1896)
+)
+(connector
+	(text "COLOR1" (rect 2026 1864 2085 1879)(font "Arial" ))
+	(pt 2016 1880)
+	(pt 2120 1880)
+)
+(connector
+	(text "FIFO_RDE" (rect 2026 1736 2095 1751)(font "Arial" ))
+	(pt 2104 1752)
+	(pt 2016 1752)
+)
+(connector
+	(text "VIDEO_RECONFIG" (rect 2026 1688 2151 1703)(font "Arial" ))
+	(pt 2144 1704)
+	(pt 2016 1704)
+)
+(connector
+	(text "VR_WR" (rect 2026 1784 2076 1799)(font "Arial" ))
+	(pt 2016 1800)
+	(pt 2112 1800)
+)
+(connector
+	(text "VR_RD" (rect 2026 1800 2074 1815)(font "Arial" ))
+	(pt 2016 1816)
+	(pt 2112 1816)
+)
+(connector
+	(text "VR_D[8..0]" (rect 1570 2120 1638 2135)(font "Arial" ))
+	(pt 1512 2136)
+	(pt 1664 2136)
+	(bus)
+)
+(connector
+	(text "VR_BUSY" (rect 1578 2104 1642 2119)(font "Arial" ))
+	(pt 1512 2120)
+	(pt 1664 2120)
+)
+(connector
+	(text "CLR_FIFO" (rect 202 2216 270 2231)(font "Arial" ))
+	(pt 296 2232)
+	(pt 192 2232)
+)
+(connector
+	(text "CLR_FIFO" (rect 2026 1752 2094 1767)(font "Arial" ))
+	(pt 2016 1768)
+	(pt 2112 1768)
+)
+(connector
+	(text "CLR_FIFO" (rect 1634 1456 1702 1471)(font "Arial" ))
+	(pt 1712 1472)
+	(pt 1632 1472)
+)
+(junction (pt 2984 1688))
+(junction (pt 792 1192))
+(junction (pt 792 1312))
+(junction (pt 792 1432))
+(junction (pt 792 1792))
+(junction (pt 792 1928))
+(junction (pt 792 1552))
+(junction (pt 792 1648))
+(junction (pt 2512 1728))
+(junction (pt 2512 1888))
+(junction (pt 2512 2048))
+(junction (pt 2512 1408))
+(junction (pt 2512 1568))
+(junction (pt 2512 1552))
+(junction (pt 2512 2208))
+(junction (pt 1344 2880))
+(junction (pt 1344 2824))
+(junction (pt 1344 2928))
+(junction (pt 1328 2904))
+(junction (pt 1328 2952))
+(junction (pt 4240 2800))
+(junction (pt 3232 3024))
+(junction (pt 1968 1424))
+(junction (pt 1608 1432))
diff --git a/FPGA_quartus_GE/Video/altddio_bidir0.bsf b/FPGA_quartus_GE/Video/altddio_bidir0.bsf
new file mode 100644
index 0000000..bcf7f28
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_bidir0.bsf
@@ -0,0 +1,99 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 240 136)
+	(text "altddio_bidir0" (rect 82 1 171 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 120 25 132)(font "Arial" ))
+	(port
+		(pt 0 24)
+		(input)
+		(text "datain_h[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
+		(text "datain_h[31..0]" (rect 4 11 76 24)(font "Arial" (font_size 8)))
+		(line (pt 0 24)(pt 88 24)(line_width 3))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "datain_l[31..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
+		(text "datain_l[31..0]" (rect 4 27 73 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 88 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "oe" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "oe" (rect 4 43 16 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 88 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "inclock" (rect 0 0 38 14)(font "Arial" (font_size 8)))
+		(text "inclock" (rect 4 59 36 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 88 72)(line_width 1))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 75 42 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 88 88)(line_width 1))
+	)
+	(port
+		(pt 240 24)
+		(output)
+		(text "dataout_h[31..0]" (rect 0 0 92 14)(font "Arial" (font_size 8)))
+		(text "dataout_h[31..0]" (rect 159 11 237 24)(font "Arial" (font_size 8)))
+		(line (pt 240 24)(pt 144 24)(line_width 3))
+	)
+	(port
+		(pt 240 40)
+		(output)
+		(text "dataout_l[31..0]" (rect 0 0 87 14)(font "Arial" (font_size 8)))
+		(text "dataout_l[31..0]" (rect 163 27 238 40)(font "Arial" (font_size 8)))
+		(line (pt 240 40)(pt 144 40)(line_width 3))
+	)
+	(port
+		(pt 240 72)
+		(output)
+		(text "combout[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
+		(text "combout[31..0]" (rect 166 59 237 72)(font "Arial" (font_size 8)))
+		(line (pt 240 72)(pt 144 72)(line_width 3))
+	)
+	(port
+		(pt 240 56)
+		(bidir)
+		(text "padio[31..0]" (rect 0 0 66 14)(font "Arial" (font_size 8)))
+		(text "padio[31..0]" (rect 181 43 238 56)(font "Arial" (font_size 8)))
+		(line (pt 240 56)(pt 144 56)(line_width 3))
+	)
+	(drawing
+		(text "ddio" (rect 108 27 129 40)(font "Arial" (font_size 8)))
+		(text "bidir" (rect 108 42 129 55)(font "Arial" (font_size 8)))
+		(text "power up" (rect 92 90 129 102)(font "Arial" ))
+		(text "low" (rect 92 100 105 112)(font "Arial" ))
+		(line (pt 88 16)(pt 144 16)(line_width 1))
+		(line (pt 144 16)(pt 144 112)(line_width 1))
+		(line (pt 144 112)(pt 88 112)(line_width 1))
+		(line (pt 88 112)(pt 88 16)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/altddio_bidir0.inc b/FPGA_quartus_GE/Video/altddio_bidir0.inc
new file mode 100644
index 0000000..5969513
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_bidir0.inc
@@ -0,0 +1,30 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altddio_bidir0 
+(
+	datain_h[31..0],
+	datain_l[31..0],
+	inclock,
+	oe,
+	outclock
+)
+
+RETURNS (
+	combout[31..0],
+	dataout_h[31..0],
+	dataout_l[31..0],
+	padio[31..0]
+);
diff --git a/FPGA_quartus_GE/Video/altddio_bidir0.ppf b/FPGA_quartus_GE/Video/altddio_bidir0.ppf
new file mode 100644
index 0000000..5601bba
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_bidir0.ppf
@@ -0,0 +1,16 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altddio_bidir0" megafunction_name="ALTDDIO_BIDIR" specifies="all_ports">
+<global>
+<pin name="datain_h[31..0]" direction="input" scope="external"  />
+<pin name="datain_l[31..0]" direction="input" scope="external"  />
+<pin name="inclock" direction="input" scope="external" source="clock"  />
+<pin name="oe" direction="input" scope="external"  />
+<pin name="outclock" direction="input" scope="external" source="clock"  />
+<pin name="combout[31..0]" direction="output" scope="external"  />
+<pin name="dataout_h[31..0]" direction="output" scope="external"  />
+<pin name="dataout_l[31..0]" direction="output" scope="external"  />
+<pin name="padio[31..0]" direction="bidir" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_quartus_GE/Video/altddio_bidir0.qip b/FPGA_quartus_GE/Video/altddio_bidir0.qip
new file mode 100644
index 0000000..3339057
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_bidir0.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTDDIO_BIDIR"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_bidir0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_bidir0.ppf"]
diff --git a/FPGA_quartus_GE/Video/altddio_bidir0.vhd b/FPGA_quartus_GE/Video/altddio_bidir0.vhd
new file mode 100644
index 0000000..a0ae0e0
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_bidir0.vhd
@@ -0,0 +1,172 @@
+-- megafunction wizard: %ALTDDIO_BIDIR%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altddio_bidir 
+
+-- ============================================================
+-- File Name: altddio_bidir0.vhd
+-- Megafunction Name(s):
+-- 			altddio_bidir
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altddio_bidir0 IS
+	PORT
+	(
+		datain_h		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		datain_l		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		inclock		: IN STD_LOGIC ;
+		oe		: IN STD_LOGIC  := '1';
+		outclock		: IN STD_LOGIC ;
+		combout		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		dataout_h		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		dataout_l		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+		padio		: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END altddio_bidir0;
+
+
+ARCHITECTURE SYN OF altddio_bidir0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT altddio_bidir
+	GENERIC (
+		extend_oe_disable		: STRING;
+		implement_input_in_lcell		: STRING;
+		intended_device_family		: STRING;
+		invert_output		: STRING;
+		lpm_type		: STRING;
+		oe_reg		: STRING;
+		power_up_high		: STRING;
+		width		: NATURAL
+	);
+	PORT (
+			outclock	: IN STD_LOGIC ;
+			padio	: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			inclock	: IN STD_LOGIC ;
+			dataout_h	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			oe	: IN STD_LOGIC ;
+			datain_h	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			combout	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			dataout_l	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			datain_l	: IN STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	dataout_h    <= sub_wire0(31 DOWNTO 0);
+	combout    <= sub_wire1(31 DOWNTO 0);
+	dataout_l    <= sub_wire2(31 DOWNTO 0);
+
+	altddio_bidir_component : altddio_bidir
+	GENERIC MAP (
+		extend_oe_disable => "UNUSED",
+		implement_input_in_lcell => "ON",
+		intended_device_family => "Cyclone III",
+		invert_output => "OFF",
+		lpm_type => "altddio_bidir",
+		oe_reg => "UNUSED",
+		power_up_high => "OFF",
+		width => 32
+	)
+	PORT MAP (
+		outclock => outclock,
+		inclock => inclock,
+		oe => oe,
+		datain_h => datain_h,
+		datain_l => datain_l,
+		dataout_h => sub_wire0,
+		combout => sub_wire1,
+		dataout_l => sub_wire2,
+		padio => padio
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_INPUT_IN_LCELL NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: OE NUMERIC "1"
+-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_COMBOUT NUMERIC "1"
+-- Retrieval info: PRIVATE: USE_DATAOUT NUMERIC "1"
+-- Retrieval info: PRIVATE: USE_DQS_UNDELAYOUT NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH NUMERIC "32"
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
+-- Retrieval info: CONSTANT: IMPLEMENT_INPUT_IN_LCELL STRING "ON"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_bidir"
+-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
+-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: combout 0 0 32 0 OUTPUT NODEFVAL combout[31..0]
+-- Retrieval info: USED_PORT: datain_h 0 0 32 0 INPUT NODEFVAL datain_h[31..0]
+-- Retrieval info: USED_PORT: datain_l 0 0 32 0 INPUT NODEFVAL datain_l[31..0]
+-- Retrieval info: USED_PORT: dataout_h 0 0 32 0 OUTPUT NODEFVAL dataout_h[31..0]
+-- Retrieval info: USED_PORT: dataout_l 0 0 32 0 OUTPUT NODEFVAL dataout_l[31..0]
+-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL inclock
+-- Retrieval info: USED_PORT: oe 0 0 0 0 INPUT VCC oe
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
+-- Retrieval info: USED_PORT: padio 0 0 32 0 BIDIR NODEFVAL padio[31..0]
+-- Retrieval info: CONNECT: @datain_h 0 0 32 0 datain_h 0 0 32 0
+-- Retrieval info: CONNECT: @datain_l 0 0 32 0 datain_l 0 0 32 0
+-- Retrieval info: CONNECT: padio 0 0 32 0 @padio 0 0 32 0
+-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+-- Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0
+-- Retrieval info: CONNECT: dataout_h 0 0 32 0 @dataout_h 0 0 32 0
+-- Retrieval info: CONNECT: dataout_l 0 0 32 0 @dataout_l 0 0 32 0
+-- Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
+-- Retrieval info: CONNECT: combout 0 0 32 0 @combout 0 0 32 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_bidir0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/Video/altddio_out0.bsf b/FPGA_quartus_GE/Video/altddio_out0.bsf
new file mode 100644
index 0000000..6554c2f
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_out0.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 232 120)
+	(text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 104 25 116)(font "Arial" ))
+	(port
+		(pt 0 24)
+		(input)
+		(text "datain_h[3..0]" (rect 0 0 76 14)(font "Arial" (font_size 8)))
+		(text "datain_h[3..0]" (rect 4 11 70 24)(font "Arial" (font_size 8)))
+		(line (pt 0 24)(pt 88 24)(line_width 3))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "datain_l[3..0]" (rect 0 0 71 14)(font "Arial" (font_size 8)))
+		(text "datain_l[3..0]" (rect 4 27 67 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 88 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 88 56)(line_width 1))
+	)
+	(port
+		(pt 232 24)
+		(output)
+		(text "dataout[3..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "dataout[3..0]" (rect 169 11 229 24)(font "Arial" (font_size 8)))
+		(line (pt 232 24)(pt 152 24)(line_width 3))
+	)
+	(drawing
+		(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
+		(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
+		(text "power up" (rect 92 74 129 86)(font "Arial" ))
+		(text "high" (rect 92 84 109 96)(font "Arial" ))
+		(line (pt 88 16)(pt 152 16)(line_width 1))
+		(line (pt 152 16)(pt 152 96)(line_width 1))
+		(line (pt 152 96)(pt 88 96)(line_width 1))
+		(line (pt 88 96)(pt 88 16)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/altddio_out0.inc b/FPGA_quartus_GE/Video/altddio_out0.inc
new file mode 100644
index 0000000..f534925
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_out0.inc
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altddio_out0 
+(
+	datain_h[3..0],
+	datain_l[3..0],
+	outclock
+)
+
+RETURNS (
+	dataout[3..0]
+);
diff --git a/FPGA_quartus_GE/Video/altddio_out0.ppf b/FPGA_quartus_GE/Video/altddio_out0.ppf
new file mode 100644
index 0000000..3f3cfb5
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_out0.ppf
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altddio_out0" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
+<global>
+<pin name="datain_h[3..0]" direction="input" scope="external"  />
+<pin name="datain_l[3..0]" direction="input" scope="external"  />
+<pin name="outclock" direction="input" scope="external" source="clock"  />
+<pin name="dataout[3..0]" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_quartus_GE/Video/altddio_out0.qip b/FPGA_quartus_GE/Video/altddio_out0.qip
new file mode 100644
index 0000000..8193856
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_out0.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.ppf"]
diff --git a/FPGA_quartus_GE/Video/altddio_out0.vhd b/FPGA_quartus_GE/Video/altddio_out0.vhd
new file mode 100644
index 0000000..f129798
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_out0.vhd
@@ -0,0 +1,136 @@
+-- megafunction wizard: %ALTDDIO_OUT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altddio_out 
+
+-- ============================================================
+-- File Name: altddio_out0.vhd
+-- Megafunction Name(s):
+-- 			altddio_out
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altddio_out0 IS
+	PORT
+	(
+		datain_h		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		datain_l		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		outclock		: IN STD_LOGIC ;
+		dataout		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+END altddio_out0;
+
+
+ARCHITECTURE SYN OF altddio_out0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+
+
+
+	COMPONENT altddio_out
+	GENERIC (
+		extend_oe_disable		: STRING;
+		intended_device_family		: STRING;
+		invert_output		: STRING;
+		lpm_type		: STRING;
+		oe_reg		: STRING;
+		power_up_high		: STRING;
+		width		: NATURAL
+	);
+	PORT (
+			dataout	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+			outclock	: IN STD_LOGIC ;
+			datain_h	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+			datain_l	: IN STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	dataout    <= sub_wire0(3 DOWNTO 0);
+
+	altddio_out_component : altddio_out
+	GENERIC MAP (
+		extend_oe_disable => "UNUSED",
+		intended_device_family => "Cyclone III",
+		invert_output => "ON",
+		lpm_type => "altddio_out",
+		oe_reg => "UNUSED",
+		power_up_high => "ON",
+		width => 4
+	)
+	PORT MAP (
+		outclock => outclock,
+		datain_h => datain_h,
+		datain_l => datain_l,
+		dataout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: OE NUMERIC "0"
+-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "1"
+-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: WIDTH NUMERIC "4"
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "ON"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
+-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
+-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "ON"
+-- Retrieval info: CONSTANT: WIDTH NUMERIC "4"
+-- Retrieval info: USED_PORT: datain_h 0 0 4 0 INPUT NODEFVAL datain_h[3..0]
+-- Retrieval info: USED_PORT: datain_l 0 0 4 0 INPUT NODEFVAL datain_l[3..0]
+-- Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL dataout[3..0]
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
+-- Retrieval info: CONNECT: @datain_h 0 0 4 0 datain_h 0 0 4 0
+-- Retrieval info: CONNECT: @datain_l 0 0 4 0 datain_l 0 0 4 0
+-- Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
+-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/Video/altddio_out1.bsf b/FPGA_quartus_GE/Video/altddio_out1.bsf
new file mode 100644
index 0000000..8289852
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_out1.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 232 120)
+	(text "altddio_out1" (rect 81 1 163 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 104 25 116)(font "Arial" ))
+	(port
+		(pt 0 24)
+		(input)
+		(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8)))
+		(line (pt 0 24)(pt 88 24)(line_width 1))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 88 40)(line_width 1))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 88 56)(line_width 1))
+	)
+	(port
+		(pt 232 24)
+		(output)
+		(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8)))
+		(line (pt 232 24)(pt 152 24)(line_width 1))
+	)
+	(drawing
+		(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
+		(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
+		(text "power up" (rect 92 74 129 86)(font "Arial" ))
+		(text "low" (rect 92 84 105 96)(font "Arial" ))
+		(line (pt 88 16)(pt 152 16)(line_width 1))
+		(line (pt 152 16)(pt 152 96)(line_width 1))
+		(line (pt 152 96)(pt 88 96)(line_width 1))
+		(line (pt 88 96)(pt 88 16)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/altddio_out1.inc b/FPGA_quartus_GE/Video/altddio_out1.inc
new file mode 100644
index 0000000..4d50b26
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_out1.inc
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altddio_out1 
+(
+	datain_h,
+	datain_l,
+	outclock
+)
+
+RETURNS (
+	dataout
+);
diff --git a/FPGA_quartus_GE/Video/altddio_out1.ppf b/FPGA_quartus_GE/Video/altddio_out1.ppf
new file mode 100644
index 0000000..9772cd3
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_out1.ppf
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altddio_out1" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
+<global>
+<pin name="datain_h" direction="input" scope="external"  />
+<pin name="datain_l" direction="input" scope="external"  />
+<pin name="outclock" direction="input" scope="external" source="clock"  />
+<pin name="dataout" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_quartus_GE/Video/altddio_out1.qip b/FPGA_quartus_GE/Video/altddio_out1.qip
new file mode 100644
index 0000000..606e0b7
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_out1.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out1.ppf"]
diff --git a/FPGA_quartus_GE/Video/altddio_out1.vhd b/FPGA_quartus_GE/Video/altddio_out1.vhd
new file mode 100644
index 0000000..cb76474
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_out1.vhd
@@ -0,0 +1,146 @@
+-- megafunction wizard: %ALTDDIO_OUT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altddio_out 
+
+-- ============================================================
+-- File Name: altddio_out1.vhd
+-- Megafunction Name(s):
+-- 			altddio_out
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altddio_out1 IS
+	PORT
+	(
+		datain_h		: IN STD_LOGIC ;
+		datain_l		: IN STD_LOGIC ;
+		outclock		: IN STD_LOGIC ;
+		dataout		: OUT STD_LOGIC 
+	);
+END altddio_out1;
+
+
+ARCHITECTURE SYN OF altddio_out1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altddio_out
+	GENERIC (
+		extend_oe_disable		: STRING;
+		intended_device_family		: STRING;
+		invert_output		: STRING;
+		lpm_type		: STRING;
+		oe_reg		: STRING;
+		power_up_high		: STRING;
+		width		: NATURAL
+	);
+	PORT (
+			dataout	: OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
+			outclock	: IN STD_LOGIC ;
+			datain_h	: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+			datain_l	: IN STD_LOGIC_VECTOR (0 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire1    <= sub_wire0(0);
+	dataout    <= sub_wire1;
+	sub_wire2    <= datain_h;
+	sub_wire3(0)    <= sub_wire2;
+	sub_wire4    <= datain_l;
+	sub_wire5(0)    <= sub_wire4;
+
+	altddio_out_component : altddio_out
+	GENERIC MAP (
+		extend_oe_disable => "UNUSED",
+		intended_device_family => "Cyclone III",
+		invert_output => "OFF",
+		lpm_type => "altddio_out",
+		oe_reg => "UNUSED",
+		power_up_high => "OFF",
+		width => 1
+	)
+	PORT MAP (
+		outclock => outclock,
+		datain_h => sub_wire3,
+		datain_l => sub_wire5,
+		dataout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: OE NUMERIC "0"
+-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: WIDTH NUMERIC "1"
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
+-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
+-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH NUMERIC "1"
+-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
+-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
+-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
+-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
+-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
+-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
+-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out1_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/Video/altddio_out2.bsf b/FPGA_quartus_GE/Video/altddio_out2.bsf
new file mode 100644
index 0000000..ff039ee
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_out2.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 232 120)
+	(text "altddio_out2" (rect 81 1 163 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 104 25 116)(font "Arial" ))
+	(port
+		(pt 0 24)
+		(input)
+		(text "datain_h[23..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
+		(text "datain_h[23..0]" (rect 4 11 76 24)(font "Arial" (font_size 8)))
+		(line (pt 0 24)(pt 88 24)(line_width 3))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "datain_l[23..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
+		(text "datain_l[23..0]" (rect 4 27 73 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 88 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 88 56)(line_width 1))
+	)
+	(port
+		(pt 232 24)
+		(output)
+		(text "dataout[23..0]" (rect 0 0 77 14)(font "Arial" (font_size 8)))
+		(text "dataout[23..0]" (rect 163 11 229 24)(font "Arial" (font_size 8)))
+		(line (pt 232 24)(pt 152 24)(line_width 3))
+	)
+	(drawing
+		(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
+		(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
+		(text "power up" (rect 92 74 129 86)(font "Arial" ))
+		(text "low" (rect 92 84 105 96)(font "Arial" ))
+		(line (pt 88 16)(pt 152 16)(line_width 1))
+		(line (pt 152 16)(pt 152 96)(line_width 1))
+		(line (pt 152 96)(pt 88 96)(line_width 1))
+		(line (pt 88 96)(pt 88 16)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/altddio_out2.inc b/FPGA_quartus_GE/Video/altddio_out2.inc
new file mode 100644
index 0000000..2257c30
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_out2.inc
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altddio_out2 
+(
+	datain_h[23..0],
+	datain_l[23..0],
+	outclock
+)
+
+RETURNS (
+	dataout[23..0]
+);
diff --git a/FPGA_quartus_GE/Video/altddio_out2.ppf b/FPGA_quartus_GE/Video/altddio_out2.ppf
new file mode 100644
index 0000000..93df472
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_out2.ppf
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altddio_out2" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
+<global>
+<pin name="datain_h[23..0]" direction="input" scope="external"  />
+<pin name="datain_l[23..0]" direction="input" scope="external"  />
+<pin name="outclock" direction="input" scope="external" source="clock"  />
+<pin name="dataout[23..0]" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_quartus_GE/Video/altddio_out2.qip b/FPGA_quartus_GE/Video/altddio_out2.qip
new file mode 100644
index 0000000..d72d5ce
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_out2.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out2.ppf"]
diff --git a/FPGA_quartus_GE/Video/altddio_out2.vhd b/FPGA_quartus_GE/Video/altddio_out2.vhd
new file mode 100644
index 0000000..30a8586
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altddio_out2.vhd
@@ -0,0 +1,136 @@
+-- megafunction wizard: %ALTDDIO_OUT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altddio_out 
+
+-- ============================================================
+-- File Name: altddio_out2.vhd
+-- Megafunction Name(s):
+-- 			altddio_out
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altddio_out2 IS
+	PORT
+	(
+		datain_h		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		datain_l		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		outclock		: IN STD_LOGIC ;
+		dataout		: OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
+	);
+END altddio_out2;
+
+
+ARCHITECTURE SYN OF altddio_out2 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+
+
+
+	COMPONENT altddio_out
+	GENERIC (
+		extend_oe_disable		: STRING;
+		intended_device_family		: STRING;
+		invert_output		: STRING;
+		lpm_type		: STRING;
+		oe_reg		: STRING;
+		power_up_high		: STRING;
+		width		: NATURAL
+	);
+	PORT (
+			dataout	: OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
+			outclock	: IN STD_LOGIC ;
+			datain_h	: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+			datain_l	: IN STD_LOGIC_VECTOR (23 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	dataout    <= sub_wire0(23 DOWNTO 0);
+
+	altddio_out_component : altddio_out
+	GENERIC MAP (
+		extend_oe_disable => "UNUSED",
+		intended_device_family => "Cyclone III",
+		invert_output => "OFF",
+		lpm_type => "altddio_out",
+		oe_reg => "UNUSED",
+		power_up_high => "OFF",
+		width => 24
+	)
+	PORT MAP (
+		outclock => outclock,
+		datain_h => datain_h,
+		datain_l => datain_l,
+		dataout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: OE NUMERIC "0"
+-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: WIDTH NUMERIC "24"
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
+-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
+-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH NUMERIC "24"
+-- Retrieval info: USED_PORT: datain_h 0 0 24 0 INPUT NODEFVAL datain_h[23..0]
+-- Retrieval info: USED_PORT: datain_l 0 0 24 0 INPUT NODEFVAL datain_l[23..0]
+-- Retrieval info: USED_PORT: dataout 0 0 24 0 OUTPUT NODEFVAL dataout[23..0]
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
+-- Retrieval info: CONNECT: @datain_h 0 0 24 0 datain_h 0 0 24 0
+-- Retrieval info: CONNECT: @datain_l 0 0 24 0 datain_l 0 0 24 0
+-- Retrieval info: CONNECT: dataout 0 0 24 0 @dataout 0 0 24 0
+-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out2_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/Video/altdpram0.bsf b/FPGA_quartus_GE/Video/altdpram0.bsf
new file mode 100644
index 0000000..e0d3ce3
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altdpram0.bsf
@@ -0,0 +1,173 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 256 208)
+	(text "altdpram0" (rect 100 1 167 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 192 25 204)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data_a[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_a[2..0]" (rect 4 19 61 32)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 112 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "address_a[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_a[3..0]" (rect 4 35 75 48)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 112 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 112 64)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "data_b[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_b[2..0]" (rect 4 83 61 96)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 112 96)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "address_b[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_b[3..0]" (rect 4 99 75 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 112 112)(line_width 3))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 112 128)(line_width 1))
+	)
+	(port
+		(pt 0 160)
+		(input)
+		(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8)))
+		(line (pt 0 160)(pt 176 160)(line_width 1))
+	)
+	(port
+		(pt 0 176)
+		(input)
+		(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8)))
+		(line (pt 0 176)(pt 181 176)(line_width 1))
+	)
+	(port
+		(pt 256 32)
+		(output)
+		(text "q_a[2..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_a[2..0]" (rect 211 19 253 32)(font "Arial" (font_size 8)))
+		(line (pt 256 32)(pt 192 32)(line_width 3))
+	)
+	(port
+		(pt 256 96)
+		(output)
+		(text "q_b[2..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_b[2..0]" (rect 211 83 253 96)(font "Arial" (font_size 8)))
+		(line (pt 256 96)(pt 192 96)(line_width 3))
+	)
+	(drawing
+		(text "16 Word(s)" (rect 136 61 148 107)(font "Arial" )(vertical))
+		(text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical))
+		(text "Block Type: AUTO" (rect 41 188 119 200)(font "Arial" ))
+		(line (pt 128 24)(pt 168 24)(line_width 1))
+		(line (pt 168 24)(pt 168 144)(line_width 1))
+		(line (pt 168 144)(pt 128 144)(line_width 1))
+		(line (pt 128 144)(pt 128 24)(line_width 1))
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+		(line (pt 114 36)(pt 112 38)(line_width 1))
+		(line (pt 92 36)(pt 112 36)(line_width 1))
+		(line (pt 120 32)(pt 128 32)(line_width 3))
+		(line (pt 112 43)(pt 120 43)(line_width 1))
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+		(line (pt 120 55)(pt 112 55)(line_width 1))
+		(line (pt 112 55)(pt 112 43)(line_width 1))
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+		(line (pt 114 52)(pt 112 54)(line_width 1))
+		(line (pt 92 52)(pt 112 52)(line_width 1))
+		(line (pt 120 48)(pt 128 48)(line_width 3))
+		(line (pt 112 59)(pt 120 59)(line_width 1))
+		(line (pt 120 59)(pt 120 71)(line_width 1))
+		(line (pt 120 71)(pt 112 71)(line_width 1))
+		(line (pt 112 71)(pt 112 59)(line_width 1))
+		(line (pt 112 66)(pt 114 68)(line_width 1))
+		(line (pt 114 68)(pt 112 70)(line_width 1))
+		(line (pt 92 68)(pt 112 68)(line_width 1))
+		(line (pt 120 64)(pt 128 64)(line_width 1))
+		(line (pt 112 91)(pt 120 91)(line_width 1))
+		(line (pt 120 91)(pt 120 103)(line_width 1))
+		(line (pt 120 103)(pt 112 103)(line_width 1))
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+		(line (pt 112 107)(pt 120 107)(line_width 1))
+		(line (pt 120 107)(pt 120 119)(line_width 1))
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+		(line (pt 184 91)(pt 192 91)(line_width 1))
+		(line (pt 192 91)(pt 192 103)(line_width 1))
+		(line (pt 192 103)(pt 184 103)(line_width 1))
+		(line (pt 184 103)(pt 184 91)(line_width 1))
+		(line (pt 184 98)(pt 186 100)(line_width 1))
+		(line (pt 186 100)(pt 184 102)(line_width 1))
+		(line (pt 181 100)(pt 184 100)(line_width 1))
+		(line (pt 168 96)(pt 184 96)(line_width 3))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/altdpram0.inc b/FPGA_quartus_GE/Video/altdpram0.inc
new file mode 100644
index 0000000..828067d
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altdpram0.inc
@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altdpram0 
+(
+	address_a[3..0],
+	address_b[3..0],
+	clock_a,
+	clock_b,
+	data_a[2..0],
+	data_b[2..0],
+	wren_a,
+	wren_b
+)
+
+RETURNS (
+	q_a[2..0],
+	q_b[2..0]
+);
diff --git a/FPGA_quartus_GE/Video/altdpram0.qip b/FPGA_quartus_GE/Video/altdpram0.qip
new file mode 100644
index 0000000..e4d02ab
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altdpram0.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram0.cmp"]
diff --git a/FPGA_quartus_GE/Video/altdpram0.vhd b/FPGA_quartus_GE/Video/altdpram0.vhd
new file mode 100644
index 0000000..c883f02
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altdpram0.vhd
@@ -0,0 +1,273 @@
+-- megafunction wizard: %LPM_RAM_DP+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: altdpram0.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altdpram0 IS
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		clock_a		: IN STD_LOGIC ;
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '1';
+		wren_b		: IN STD_LOGIC  := '1';
+		q_a		: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
+	);
+END altdpram0;
+
+
+ARCHITECTURE SYN OF altdpram0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (2 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (2 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		read_during_write_mode_port_b		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			wren_a	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			wren_b	: IN STD_LOGIC ;
+			clock1	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+			address_b	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+			data_b	: IN STD_LOGIC_VECTOR (2 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q_a    <= sub_wire0(2 DOWNTO 0);
+	q_b    <= sub_wire1(2 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK1",
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 16,
+		numwords_b => 16,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => "CLOCK0",
+		outdata_reg_b => "CLOCK1",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "OLD_DATA",
+		read_during_write_mode_port_b => "OLD_DATA",
+		widthad_a => 4,
+		widthad_b => 4,
+		width_a => 3,
+		width_b => 3,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		wren_a => wren_a,
+		clock0 => clock_a,
+		wren_b => wren_b,
+		clock1 => clock_b,
+		address_a => address_a,
+		address_b => address_b,
+		data_a => data_a,
+		data_b => data_b,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "5"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: ECC NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "48"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "3"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "3"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "3"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "3"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "0"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "3"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: USED_PORT: address_a 0 0 4 0 INPUT NODEFVAL address_a[3..0]
+-- Retrieval info: USED_PORT: address_b 0 0 4 0 INPUT NODEFVAL address_b[3..0]
+-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
+-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
+-- Retrieval info: USED_PORT: data_a 0 0 3 0 INPUT NODEFVAL data_a[2..0]
+-- Retrieval info: USED_PORT: data_b 0 0 3 0 INPUT NODEFVAL data_b[2..0]
+-- Retrieval info: USED_PORT: q_a 0 0 3 0 OUTPUT NODEFVAL q_a[2..0]
+-- Retrieval info: USED_PORT: q_b 0 0 3 0 OUTPUT NODEFVAL q_b[2..0]
+-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
+-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
+-- Retrieval info: CONNECT: @data_a 0 0 3 0 data_a 0 0 3 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+-- Retrieval info: CONNECT: q_a 0 0 3 0 @q_a 0 0 3 0
+-- Retrieval info: CONNECT: q_b 0 0 3 0 @q_b 0 0 3 0
+-- Retrieval info: CONNECT: @address_a 0 0 4 0 address_a 0 0 4 0
+-- Retrieval info: CONNECT: @data_b 0 0 3 0 data_b 0 0 3 0
+-- Retrieval info: CONNECT: @address_b 0 0 4 0 address_b 0 0 4 0
+-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram0_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/Video/altdpram1.bsf b/FPGA_quartus_GE/Video/altdpram1.bsf
new file mode 100644
index 0000000..d75db28
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altdpram1.bsf
@@ -0,0 +1,173 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 256 208)
+	(text "altdpram1" (rect 100 1 167 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 192 25 204)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data_a[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_a[5..0]" (rect 4 19 61 32)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 112 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_a[7..0]" (rect 4 35 75 48)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 112 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 112 64)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "data_b[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_b[5..0]" (rect 4 83 61 96)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 112 96)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_b[7..0]" (rect 4 99 75 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 112 112)(line_width 3))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 112 128)(line_width 1))
+	)
+	(port
+		(pt 0 160)
+		(input)
+		(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8)))
+		(line (pt 0 160)(pt 176 160)(line_width 1))
+	)
+	(port
+		(pt 0 176)
+		(input)
+		(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8)))
+		(line (pt 0 176)(pt 181 176)(line_width 1))
+	)
+	(port
+		(pt 256 32)
+		(output)
+		(text "q_a[5..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_a[5..0]" (rect 211 19 253 32)(font "Arial" (font_size 8)))
+		(line (pt 256 32)(pt 192 32)(line_width 3))
+	)
+	(port
+		(pt 256 96)
+		(output)
+		(text "q_b[5..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_b[5..0]" (rect 211 83 253 96)(font "Arial" (font_size 8)))
+		(line (pt 256 96)(pt 192 96)(line_width 3))
+	)
+	(drawing
+		(text "256 Word(s)" (rect 136 58 148 109)(font "Arial" )(vertical))
+		(text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical))
+		(text "Block Type: AUTO" (rect 41 188 119 200)(font "Arial" ))
+		(line (pt 128 24)(pt 168 24)(line_width 1))
+		(line (pt 168 24)(pt 168 144)(line_width 1))
+		(line (pt 168 144)(pt 128 144)(line_width 1))
+		(line (pt 128 144)(pt 128 24)(line_width 1))
+		(line (pt 112 27)(pt 120 27)(line_width 1))
+		(line (pt 120 27)(pt 120 39)(line_width 1))
+		(line (pt 120 39)(pt 112 39)(line_width 1))
+		(line (pt 112 39)(pt 112 27)(line_width 1))
+		(line (pt 112 34)(pt 114 36)(line_width 1))
+		(line (pt 114 36)(pt 112 38)(line_width 1))
+		(line (pt 92 36)(pt 112 36)(line_width 1))
+		(line (pt 120 32)(pt 128 32)(line_width 3))
+		(line (pt 112 43)(pt 120 43)(line_width 1))
+		(line (pt 120 43)(pt 120 55)(line_width 1))
+		(line (pt 120 55)(pt 112 55)(line_width 1))
+		(line (pt 112 55)(pt 112 43)(line_width 1))
+		(line (pt 112 50)(pt 114 52)(line_width 1))
+		(line (pt 114 52)(pt 112 54)(line_width 1))
+		(line (pt 92 52)(pt 112 52)(line_width 1))
+		(line (pt 120 48)(pt 128 48)(line_width 3))
+		(line (pt 112 59)(pt 120 59)(line_width 1))
+		(line (pt 120 59)(pt 120 71)(line_width 1))
+		(line (pt 120 71)(pt 112 71)(line_width 1))
+		(line (pt 112 71)(pt 112 59)(line_width 1))
+		(line (pt 112 66)(pt 114 68)(line_width 1))
+		(line (pt 114 68)(pt 112 70)(line_width 1))
+		(line (pt 92 68)(pt 112 68)(line_width 1))
+		(line (pt 120 64)(pt 128 64)(line_width 1))
+		(line (pt 112 91)(pt 120 91)(line_width 1))
+		(line (pt 120 91)(pt 120 103)(line_width 1))
+		(line (pt 120 103)(pt 112 103)(line_width 1))
+		(line (pt 112 103)(pt 112 91)(line_width 1))
+		(line (pt 112 98)(pt 114 100)(line_width 1))
+		(line (pt 114 100)(pt 112 102)(line_width 1))
+		(line (pt 104 100)(pt 112 100)(line_width 1))
+		(line (pt 120 96)(pt 128 96)(line_width 3))
+		(line (pt 112 107)(pt 120 107)(line_width 1))
+		(line (pt 120 107)(pt 120 119)(line_width 1))
+		(line (pt 120 119)(pt 112 119)(line_width 1))
+		(line (pt 112 119)(pt 112 107)(line_width 1))
+		(line (pt 112 114)(pt 114 116)(line_width 1))
+		(line (pt 114 116)(pt 112 118)(line_width 1))
+		(line (pt 104 116)(pt 112 116)(line_width 1))
+		(line (pt 120 112)(pt 128 112)(line_width 3))
+		(line (pt 112 123)(pt 120 123)(line_width 1))
+		(line (pt 120 123)(pt 120 135)(line_width 1))
+		(line (pt 120 135)(pt 112 135)(line_width 1))
+		(line (pt 112 135)(pt 112 123)(line_width 1))
+		(line (pt 112 130)(pt 114 132)(line_width 1))
+		(line (pt 114 132)(pt 112 134)(line_width 1))
+		(line (pt 104 132)(pt 112 132)(line_width 1))
+		(line (pt 120 128)(pt 128 128)(line_width 1))
+		(line (pt 92 36)(pt 92 161)(line_width 1))
+		(line (pt 176 36)(pt 176 161)(line_width 1))
+		(line (pt 104 100)(pt 104 177)(line_width 1))
+		(line (pt 181 100)(pt 181 177)(line_width 1))
+		(line (pt 184 27)(pt 192 27)(line_width 1))
+		(line (pt 192 27)(pt 192 39)(line_width 1))
+		(line (pt 192 39)(pt 184 39)(line_width 1))
+		(line (pt 184 39)(pt 184 27)(line_width 1))
+		(line (pt 184 34)(pt 186 36)(line_width 1))
+		(line (pt 186 36)(pt 184 38)(line_width 1))
+		(line (pt 176 36)(pt 184 36)(line_width 1))
+		(line (pt 168 32)(pt 184 32)(line_width 3))
+		(line (pt 184 91)(pt 192 91)(line_width 1))
+		(line (pt 192 91)(pt 192 103)(line_width 1))
+		(line (pt 192 103)(pt 184 103)(line_width 1))
+		(line (pt 184 103)(pt 184 91)(line_width 1))
+		(line (pt 184 98)(pt 186 100)(line_width 1))
+		(line (pt 186 100)(pt 184 102)(line_width 1))
+		(line (pt 181 100)(pt 184 100)(line_width 1))
+		(line (pt 168 96)(pt 184 96)(line_width 3))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/altdpram1.inc b/FPGA_quartus_GE/Video/altdpram1.inc
new file mode 100644
index 0000000..4a7924e
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altdpram1.inc
@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altdpram1 
+(
+	address_a[7..0],
+	address_b[7..0],
+	clock_a,
+	clock_b,
+	data_a[5..0],
+	data_b[5..0],
+	wren_a,
+	wren_b
+)
+
+RETURNS (
+	q_a[5..0],
+	q_b[5..0]
+);
diff --git a/FPGA_quartus_GE/Video/altdpram1.qip b/FPGA_quartus_GE/Video/altdpram1.qip
new file mode 100644
index 0000000..cdd178f
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altdpram1.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram1.cmp"]
diff --git a/FPGA_quartus_GE/Video/altdpram1.vhd b/FPGA_quartus_GE/Video/altdpram1.vhd
new file mode 100644
index 0000000..b2e0435
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altdpram1.vhd
@@ -0,0 +1,273 @@
+-- megafunction wizard: %LPM_RAM_DP+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: altdpram1.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altdpram1 IS
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		clock_a		: IN STD_LOGIC ;
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '1';
+		wren_b		: IN STD_LOGIC  := '1';
+		q_a		: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
+	);
+END altdpram1;
+
+
+ARCHITECTURE SYN OF altdpram1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (5 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (5 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		read_during_write_mode_port_b		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			wren_a	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			wren_b	: IN STD_LOGIC ;
+			clock1	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			address_b	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+			data_b	: IN STD_LOGIC_VECTOR (5 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q_a    <= sub_wire0(5 DOWNTO 0);
+	q_b    <= sub_wire1(5 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK1",
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 256,
+		numwords_b => 256,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => "CLOCK0",
+		outdata_reg_b => "CLOCK1",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "OLD_DATA",
+		read_during_write_mode_port_b => "OLD_DATA",
+		widthad_a => 8,
+		widthad_b => 8,
+		width_a => 6,
+		width_b => 6,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		wren_a => wren_a,
+		clock0 => clock_a,
+		wren_b => wren_b,
+		clock1 => clock_b,
+		address_a => address_a,
+		address_b => address_b,
+		data_a => data_a,
+		data_b => data_b,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "5"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: ECC NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "1536"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "6"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "6"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "6"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "6"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "0"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "6"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "6"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0]
+-- Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL address_b[7..0]
+-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
+-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
+-- Retrieval info: USED_PORT: data_a 0 0 6 0 INPUT NODEFVAL data_a[5..0]
+-- Retrieval info: USED_PORT: data_b 0 0 6 0 INPUT NODEFVAL data_b[5..0]
+-- Retrieval info: USED_PORT: q_a 0 0 6 0 OUTPUT NODEFVAL q_a[5..0]
+-- Retrieval info: USED_PORT: q_b 0 0 6 0 OUTPUT NODEFVAL q_b[5..0]
+-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
+-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
+-- Retrieval info: CONNECT: @data_a 0 0 6 0 data_a 0 0 6 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+-- Retrieval info: CONNECT: q_a 0 0 6 0 @q_a 0 0 6 0
+-- Retrieval info: CONNECT: q_b 0 0 6 0 @q_b 0 0 6 0
+-- Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
+-- Retrieval info: CONNECT: @data_b 0 0 6 0 data_b 0 0 6 0
+-- Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
+-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram1_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/Video/altdpram2.bsf b/FPGA_quartus_GE/Video/altdpram2.bsf
new file mode 100644
index 0000000..75c64aa
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altdpram2.bsf
@@ -0,0 +1,173 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 256 208)
+	(text "altdpram2" (rect 100 1 167 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 192 25 204)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data_a[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_a[7..0]" (rect 4 19 61 32)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 112 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "address_a[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_a[7..0]" (rect 4 35 75 48)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 112 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 112 64)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "data_b[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data_b[7..0]" (rect 4 83 61 96)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 112 96)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "address_b[7..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "address_b[7..0]" (rect 4 99 75 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 112 112)(line_width 3))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 112 128)(line_width 1))
+	)
+	(port
+		(pt 0 160)
+		(input)
+		(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8)))
+		(line (pt 0 160)(pt 176 160)(line_width 1))
+	)
+	(port
+		(pt 0 176)
+		(input)
+		(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8)))
+		(line (pt 0 176)(pt 181 176)(line_width 1))
+	)
+	(port
+		(pt 256 32)
+		(output)
+		(text "q_a[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_a[7..0]" (rect 211 19 253 32)(font "Arial" (font_size 8)))
+		(line (pt 256 32)(pt 192 32)(line_width 3))
+	)
+	(port
+		(pt 256 96)
+		(output)
+		(text "q_b[7..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q_b[7..0]" (rect 211 83 253 96)(font "Arial" (font_size 8)))
+		(line (pt 256 96)(pt 192 96)(line_width 3))
+	)
+	(drawing
+		(text "256 Word(s)" (rect 136 58 148 109)(font "Arial" )(vertical))
+		(text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical))
+		(text "Block Type: AUTO" (rect 41 188 119 200)(font "Arial" ))
+		(line (pt 128 24)(pt 168 24)(line_width 1))
+		(line (pt 168 24)(pt 168 144)(line_width 1))
+		(line (pt 168 144)(pt 128 144)(line_width 1))
+		(line (pt 128 144)(pt 128 24)(line_width 1))
+		(line (pt 112 27)(pt 120 27)(line_width 1))
+		(line (pt 120 27)(pt 120 39)(line_width 1))
+		(line (pt 120 39)(pt 112 39)(line_width 1))
+		(line (pt 112 39)(pt 112 27)(line_width 1))
+		(line (pt 112 34)(pt 114 36)(line_width 1))
+		(line (pt 114 36)(pt 112 38)(line_width 1))
+		(line (pt 92 36)(pt 112 36)(line_width 1))
+		(line (pt 120 32)(pt 128 32)(line_width 3))
+		(line (pt 112 43)(pt 120 43)(line_width 1))
+		(line (pt 120 43)(pt 120 55)(line_width 1))
+		(line (pt 120 55)(pt 112 55)(line_width 1))
+		(line (pt 112 55)(pt 112 43)(line_width 1))
+		(line (pt 112 50)(pt 114 52)(line_width 1))
+		(line (pt 114 52)(pt 112 54)(line_width 1))
+		(line (pt 92 52)(pt 112 52)(line_width 1))
+		(line (pt 120 48)(pt 128 48)(line_width 3))
+		(line (pt 112 59)(pt 120 59)(line_width 1))
+		(line (pt 120 59)(pt 120 71)(line_width 1))
+		(line (pt 120 71)(pt 112 71)(line_width 1))
+		(line (pt 112 71)(pt 112 59)(line_width 1))
+		(line (pt 112 66)(pt 114 68)(line_width 1))
+		(line (pt 114 68)(pt 112 70)(line_width 1))
+		(line (pt 92 68)(pt 112 68)(line_width 1))
+		(line (pt 120 64)(pt 128 64)(line_width 1))
+		(line (pt 112 91)(pt 120 91)(line_width 1))
+		(line (pt 120 91)(pt 120 103)(line_width 1))
+		(line (pt 120 103)(pt 112 103)(line_width 1))
+		(line (pt 112 103)(pt 112 91)(line_width 1))
+		(line (pt 112 98)(pt 114 100)(line_width 1))
+		(line (pt 114 100)(pt 112 102)(line_width 1))
+		(line (pt 104 100)(pt 112 100)(line_width 1))
+		(line (pt 120 96)(pt 128 96)(line_width 3))
+		(line (pt 112 107)(pt 120 107)(line_width 1))
+		(line (pt 120 107)(pt 120 119)(line_width 1))
+		(line (pt 120 119)(pt 112 119)(line_width 1))
+		(line (pt 112 119)(pt 112 107)(line_width 1))
+		(line (pt 112 114)(pt 114 116)(line_width 1))
+		(line (pt 114 116)(pt 112 118)(line_width 1))
+		(line (pt 104 116)(pt 112 116)(line_width 1))
+		(line (pt 120 112)(pt 128 112)(line_width 3))
+		(line (pt 112 123)(pt 120 123)(line_width 1))
+		(line (pt 120 123)(pt 120 135)(line_width 1))
+		(line (pt 120 135)(pt 112 135)(line_width 1))
+		(line (pt 112 135)(pt 112 123)(line_width 1))
+		(line (pt 112 130)(pt 114 132)(line_width 1))
+		(line (pt 114 132)(pt 112 134)(line_width 1))
+		(line (pt 104 132)(pt 112 132)(line_width 1))
+		(line (pt 120 128)(pt 128 128)(line_width 1))
+		(line (pt 92 36)(pt 92 161)(line_width 1))
+		(line (pt 176 36)(pt 176 161)(line_width 1))
+		(line (pt 104 100)(pt 104 177)(line_width 1))
+		(line (pt 181 100)(pt 181 177)(line_width 1))
+		(line (pt 184 27)(pt 192 27)(line_width 1))
+		(line (pt 192 27)(pt 192 39)(line_width 1))
+		(line (pt 192 39)(pt 184 39)(line_width 1))
+		(line (pt 184 39)(pt 184 27)(line_width 1))
+		(line (pt 184 34)(pt 186 36)(line_width 1))
+		(line (pt 186 36)(pt 184 38)(line_width 1))
+		(line (pt 176 36)(pt 184 36)(line_width 1))
+		(line (pt 168 32)(pt 184 32)(line_width 3))
+		(line (pt 184 91)(pt 192 91)(line_width 1))
+		(line (pt 192 91)(pt 192 103)(line_width 1))
+		(line (pt 192 103)(pt 184 103)(line_width 1))
+		(line (pt 184 103)(pt 184 91)(line_width 1))
+		(line (pt 184 98)(pt 186 100)(line_width 1))
+		(line (pt 186 100)(pt 184 102)(line_width 1))
+		(line (pt 181 100)(pt 184 100)(line_width 1))
+		(line (pt 168 96)(pt 184 96)(line_width 3))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/altdpram2.inc b/FPGA_quartus_GE/Video/altdpram2.inc
new file mode 100644
index 0000000..1909de8
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altdpram2.inc
@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altdpram2 
+(
+	address_a[7..0],
+	address_b[7..0],
+	clock_a,
+	clock_b,
+	data_a[7..0],
+	data_b[7..0],
+	wren_a,
+	wren_b
+)
+
+RETURNS (
+	q_a[7..0],
+	q_b[7..0]
+);
diff --git a/FPGA_quartus_GE/Video/altdpram2.qip b/FPGA_quartus_GE/Video/altdpram2.qip
new file mode 100644
index 0000000..f84925c
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altdpram2.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_RAM_DP+"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altdpram2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altdpram2.cmp"]
diff --git a/FPGA_quartus_GE/Video/altdpram2.vhd b/FPGA_quartus_GE/Video/altdpram2.vhd
new file mode 100644
index 0000000..238e6f3
--- /dev/null
+++ b/FPGA_quartus_GE/Video/altdpram2.vhd
@@ -0,0 +1,273 @@
+-- megafunction wizard: %LPM_RAM_DP+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: altdpram2.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altdpram2 IS
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		clock_a		: IN STD_LOGIC ;
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '1';
+		wren_b		: IN STD_LOGIC  := '1';
+		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END altdpram2;
+
+
+ARCHITECTURE SYN OF altdpram2 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		read_during_write_mode_port_b		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			wren_a	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			wren_b	: IN STD_LOGIC ;
+			clock1	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			address_b	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			data_b	: IN STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q_a    <= sub_wire0(7 DOWNTO 0);
+	q_b    <= sub_wire1(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK1",
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 256,
+		numwords_b => 256,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => "CLOCK0",
+		outdata_reg_b => "CLOCK1",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "OLD_DATA",
+		read_during_write_mode_port_b => "OLD_DATA",
+		widthad_a => 8,
+		widthad_b => 8,
+		width_a => 8,
+		width_b => 8,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		wren_a => wren_a,
+		clock0 => clock_a,
+		wren_b => wren_b,
+		clock1 => clock_b,
+		address_a => address_a,
+		address_b => address_b,
+		data_a => data_a,
+		data_b => data_b,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "5"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: ECC NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "2048"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "1"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "0"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL address_a[7..0]
+-- Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL address_b[7..0]
+-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
+-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
+-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL data_a[7..0]
+-- Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL data_b[7..0]
+-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL q_a[7..0]
+-- Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL q_b[7..0]
+-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
+-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
+-- Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
+-- Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
+-- Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
+-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altdpram2_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/Video/lpm_bustri0.bsf b/FPGA_quartus_GE/Video/lpm_bustri0.bsf
new file mode 100644
index 0000000..f65e217
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri0.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 80 40)
+	(text "lpm_bustri0" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 80 24)
+		(bidir)
+		(text "tridata[31..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "tridata[31..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 80 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "32" (rect 61 25 71 37)(font "Arial" ))
+		(text "32" (rect 13 25 23 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 56 28)(pt 64 20)(line_width 1))
+		(line (pt 8 28)(pt 16 20)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_bustri0.inc b/FPGA_quartus_GE/Video/lpm_bustri0.inc
new file mode 100644
index 0000000..1b15c22
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri0.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_bustri0 
+(
+	data[31..0],
+	enabledt
+)
+
+RETURNS (
+	tridata[31..0]
+);
diff --git a/FPGA_quartus_GE/Video/lpm_bustri0.qip b/FPGA_quartus_GE/Video/lpm_bustri0.qip
new file mode 100644
index 0000000..c70041d
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri0.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri0.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_bustri0.vhd b/FPGA_quartus_GE/Video/lpm_bustri0.vhd
new file mode 100644
index 0000000..494b3c2
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri0.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri0.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri0 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END lpm_bustri0;
+
+
+ARCHITECTURE SYN OF lpm_bustri0 IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 32
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 32 0 BIDIR NODEFVAL tridata[31..0]
+-- Retrieval info: CONNECT: tridata 0 0 32 0 @tridata 0 0 32 0
+-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_bustri1.bsf b/FPGA_quartus_GE/Video/lpm_bustri1.bsf
new file mode 100644
index 0000000..058fffb
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri1.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 80 40)
+	(text "lpm_bustri1" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[2..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[2..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 80 24)
+		(bidir)
+		(text "tridata[2..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[2..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 80 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "3" (rect 63 25 68 37)(font "Arial" ))
+		(text "3" (rect 15 25 20 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 58 28)(pt 66 20)(line_width 1))
+		(line (pt 10 28)(pt 18 20)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_bustri1.qip b/FPGA_quartus_GE/Video/lpm_bustri1.qip
new file mode 100644
index 0000000..fd76bb2
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri1.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri1.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_bustri1.vhd b/FPGA_quartus_GE/Video/lpm_bustri1.vhd
new file mode 100644
index 0000000..47db597
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri1.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri1.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri1 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (2 DOWNTO 0)
+	);
+END lpm_bustri1;
+
+
+ARCHITECTURE SYN OF lpm_bustri1 IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (2 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 3
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "3"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "3"
+-- Retrieval info: USED_PORT: data 0 0 3 0 INPUT NODEFVAL data[2..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 3 0 BIDIR NODEFVAL tridata[2..0]
+-- Retrieval info: CONNECT: tridata 0 0 3 0 @tridata 0 0 3 0
+-- Retrieval info: CONNECT: @data 0 0 3 0 data 0 0 3 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri1_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_bustri2.bsf b/FPGA_quartus_GE/Video/lpm_bustri2.bsf
new file mode 100644
index 0000000..36a4813
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri2.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 80 40)
+	(text "lpm_bustri2" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[17..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[17..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 80 24)
+		(bidir)
+		(text "tridata[17..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "tridata[17..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 80 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "18" (rect 61 25 71 37)(font "Arial" ))
+		(text "18" (rect 13 25 23 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 56 28)(pt 64 20)(line_width 1))
+		(line (pt 8 28)(pt 16 20)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_bustri2.qip b/FPGA_quartus_GE/Video/lpm_bustri2.qip
new file mode 100644
index 0000000..676e430
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri2.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri2.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_bustri2.vhd b/FPGA_quartus_GE/Video/lpm_bustri2.vhd
new file mode 100644
index 0000000..0966743
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri2.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri2.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri2 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (17 DOWNTO 0)
+	);
+END lpm_bustri2;
+
+
+ARCHITECTURE SYN OF lpm_bustri2 IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (17 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 18
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "18"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18"
+-- Retrieval info: USED_PORT: data 0 0 18 0 INPUT NODEFVAL data[17..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 18 0 BIDIR NODEFVAL tridata[17..0]
+-- Retrieval info: CONNECT: tridata 0 0 18 0 @tridata 0 0 18 0
+-- Retrieval info: CONNECT: @data 0 0 18 0 data 0 0 18 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri2_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_bustri3.bsf b/FPGA_quartus_GE/Video/lpm_bustri3.bsf
new file mode 100644
index 0000000..2dde401
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri3.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 80 40)
+	(text "lpm_bustri3" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[5..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[5..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 80 24)
+		(bidir)
+		(text "tridata[5..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[5..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 80 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "6" (rect 63 25 68 37)(font "Arial" ))
+		(text "6" (rect 15 25 20 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 58 28)(pt 66 20)(line_width 1))
+		(line (pt 10 28)(pt 18 20)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_bustri3.qip b/FPGA_quartus_GE/Video/lpm_bustri3.qip
new file mode 100644
index 0000000..8c41556
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri3.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri3.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri3.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri3.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_bustri3.vhd b/FPGA_quartus_GE/Video/lpm_bustri3.vhd
new file mode 100644
index 0000000..2344712
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri3.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri3.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri3 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (5 DOWNTO 0)
+	);
+END lpm_bustri3;
+
+
+ARCHITECTURE SYN OF lpm_bustri3 IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (5 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 6
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "6"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "6"
+-- Retrieval info: USED_PORT: data 0 0 6 0 INPUT NODEFVAL data[5..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 6 0 BIDIR NODEFVAL tridata[5..0]
+-- Retrieval info: CONNECT: tridata 0 0 6 0 @tridata 0 0 6 0
+-- Retrieval info: CONNECT: @data 0 0 6 0 data 0 0 6 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri3_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_bustri4.bsf b/FPGA_quartus_GE/Video/lpm_bustri4.bsf
new file mode 100644
index 0000000..cd9edcc
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri4.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 80 40)
+	(text "lpm_bustri4" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[4..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[4..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 80 24)
+		(bidir)
+		(text "tridata[4..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[4..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 80 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "5" (rect 63 25 68 37)(font "Arial" ))
+		(text "5" (rect 15 25 20 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 58 28)(pt 66 20)(line_width 1))
+		(line (pt 10 28)(pt 18 20)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_bustri4.qip b/FPGA_quartus_GE/Video/lpm_bustri4.qip
new file mode 100644
index 0000000..39eb21d
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri4.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri4.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri4.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri4.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_bustri4.vhd b/FPGA_quartus_GE/Video/lpm_bustri4.vhd
new file mode 100644
index 0000000..5bb209b
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri4.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri4.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri4 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+END lpm_bustri4;
+
+
+ARCHITECTURE SYN OF lpm_bustri4 IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 5
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
+-- Retrieval info: USED_PORT: data 0 0 5 0 INPUT NODEFVAL data[4..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 5 0 BIDIR NODEFVAL tridata[4..0]
+-- Retrieval info: CONNECT: tridata 0 0 5 0 @tridata 0 0 5 0
+-- Retrieval info: CONNECT: @data 0 0 5 0 data 0 0 5 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri4_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_bustri5.bsf b/FPGA_quartus_GE/Video/lpm_bustri5.bsf
new file mode 100644
index 0000000..1d9b178
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri5.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 80 40)
+	(text "lpm_bustri5" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[7..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 80 24)
+		(bidir)
+		(text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[7..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 80 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "8" (rect 63 25 68 37)(font "Arial" ))
+		(text "8" (rect 15 25 20 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 58 28)(pt 66 20)(line_width 1))
+		(line (pt 10 28)(pt 18 20)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_bustri5.inc b/FPGA_quartus_GE/Video/lpm_bustri5.inc
new file mode 100644
index 0000000..fdb4877
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri5.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_bustri5 
+(
+	data[7..0],
+	enabledt
+)
+
+RETURNS (
+	tridata[7..0]
+);
diff --git a/FPGA_quartus_GE/Video/lpm_bustri5.qip b/FPGA_quartus_GE/Video/lpm_bustri5.qip
new file mode 100644
index 0000000..daa3efa
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri5.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri5.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri5.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_bustri5.vhd b/FPGA_quartus_GE/Video/lpm_bustri5.vhd
new file mode 100644
index 0000000..e1973b4
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri5.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri5.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri5 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END lpm_bustri5;
+
+
+ARCHITECTURE SYN OF lpm_bustri5 IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 8
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 8 0 BIDIR NODEFVAL tridata[7..0]
+-- Retrieval info: CONNECT: tridata 0 0 8 0 @tridata 0 0 8 0
+-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri5_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_bustri6.bsf b/FPGA_quartus_GE/Video/lpm_bustri6.bsf
new file mode 100644
index 0000000..4c9344e
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri6.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 80 40)
+	(text "lpm_bustri6" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[23..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 80 24)
+		(bidir)
+		(text "tridata[23..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "tridata[23..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 80 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "24" (rect 61 25 71 37)(font "Arial" ))
+		(text "24" (rect 13 25 23 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 56 28)(pt 64 20)(line_width 1))
+		(line (pt 8 28)(pt 16 20)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_bustri6.qip b/FPGA_quartus_GE/Video/lpm_bustri6.qip
new file mode 100644
index 0000000..6b9f1df
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri6.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri6.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri6.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri6.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_bustri6.vhd b/FPGA_quartus_GE/Video/lpm_bustri6.vhd
new file mode 100644
index 0000000..45f409f
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri6.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri6.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri6 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (23 DOWNTO 0)
+	);
+END lpm_bustri6;
+
+
+ARCHITECTURE SYN OF lpm_bustri6 IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (23 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 24
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "24"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
+-- Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL data[23..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 24 0 BIDIR NODEFVAL tridata[23..0]
+-- Retrieval info: CONNECT: tridata 0 0 24 0 @tridata 0 0 24 0
+-- Retrieval info: CONNECT: @data 0 0 24 0 data 0 0 24 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri6_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_bustri7.bsf b/FPGA_quartus_GE/Video/lpm_bustri7.bsf
new file mode 100644
index 0000000..399a828
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri7.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 80 40)
+	(text "lpm_bustri7" (rect 7 1 86 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[3..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[3..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 80 24)
+		(bidir)
+		(text "tridata[3..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[3..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 80 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "4" (rect 63 25 68 37)(font "Arial" ))
+		(text "4" (rect 15 25 20 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 58 28)(pt 66 20)(line_width 1))
+		(line (pt 10 28)(pt 18 20)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_bustri7.qip b/FPGA_quartus_GE/Video/lpm_bustri7.qip
new file mode 100644
index 0000000..f32324c
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri7.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri7.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri7.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri7.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_bustri7.vhd b/FPGA_quartus_GE/Video/lpm_bustri7.vhd
new file mode 100644
index 0000000..4bf883d
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_bustri7.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri7.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri7 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+END lpm_bustri7;
+
+
+ARCHITECTURE SYN OF lpm_bustri7 IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 4
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
+-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL data[3..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 4 0 BIDIR NODEFVAL tridata[3..0]
+-- Retrieval info: CONNECT: tridata 0 0 4 0 @tridata 0 0 4 0
+-- Retrieval info: CONNECT: @data 0 0 4 0 data 0 0 4 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri7_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_compare1.bsf b/FPGA_quartus_GE/Video/lpm_compare1.bsf
new file mode 100644
index 0000000..9ec3796
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_compare1.bsf
@@ -0,0 +1,54 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 128 96)
+	(text "lpm_compare1" (rect 22 1 122 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 80 25 92)(font "Arial" ))
+	(port
+		(pt 0 48)
+		(input)
+		(text "dataa[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "dataa[10..0]" (rect 20 42 77 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "datab[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "datab[10..0]" (rect 20 58 77 71)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 128 56)
+		(output)
+		(text "agb" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+		(text "agb" (rect 91 50 109 63)(font "Arial" (font_size 8)))
+		(line (pt 128 56)(pt 112 56)(line_width 1))
+	)
+	(drawing
+		(text "unsigned compare" (rect 36 17 112 29)(font "Arial" ))
+		(line (pt 16 16)(pt 112 16)(line_width 1))
+		(line (pt 112 16)(pt 112 80)(line_width 1))
+		(line (pt 112 80)(pt 16 80)(line_width 1))
+		(line (pt 16 80)(pt 16 16)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_compare1.inc b/FPGA_quartus_GE/Video/lpm_compare1.inc
new file mode 100644
index 0000000..bde0ab9
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_compare1.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_compare1 
+(
+	dataa[10..0],
+	datab[10..0]
+)
+
+RETURNS (
+	AgB
+);
diff --git a/FPGA_quartus_GE/Video/lpm_compare1.qip b/FPGA_quartus_GE/Video/lpm_compare1.qip
new file mode 100644
index 0000000..ea93f3c
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_compare1.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_COMPARE"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_compare1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_compare1.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_compare1.vhd b/FPGA_quartus_GE/Video/lpm_compare1.vhd
new file mode 100644
index 0000000..a85e3b2
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_compare1.vhd
@@ -0,0 +1,127 @@
+-- megafunction wizard: %LPM_COMPARE%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_compare 
+
+-- ============================================================
+-- File Name: lpm_compare1.vhd
+-- Megafunction Name(s):
+-- 			lpm_compare
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_compare1 IS
+	PORT
+	(
+		dataa		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		datab		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		AgB		: OUT STD_LOGIC 
+	);
+END lpm_compare1;
+
+
+ARCHITECTURE SYN OF lpm_compare1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+
+
+
+	COMPONENT lpm_compare
+	GENERIC (
+		lpm_representation		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			dataa	: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+			datab	: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+			AgB	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	AgB    <= sub_wire0;
+
+	lpm_compare_component : lpm_compare
+	GENERIC MAP (
+		lpm_representation => "UNSIGNED",
+		lpm_type => "LPM_COMPARE",
+		lpm_width => 11
+	)
+	PORT MAP (
+		dataa => dataa,
+		datab => datab,
+		AgB => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
+-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
+-- Retrieval info: PRIVATE: AgtB NUMERIC "1"
+-- Retrieval info: PRIVATE: AleB NUMERIC "0"
+-- Retrieval info: PRIVATE: AltB NUMERIC "0"
+-- Retrieval info: PRIVATE: AneB NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
+-- Retrieval info: PRIVATE: Latency NUMERIC "0"
+-- Retrieval info: PRIVATE: PortBValue NUMERIC "0"
+-- Retrieval info: PRIVATE: Radix NUMERIC "10"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
+-- Retrieval info: PRIVATE: aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: clken NUMERIC "0"
+-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "11"
+-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11"
+-- Retrieval info: USED_PORT: AgB 0 0 0 0 OUTPUT NODEFVAL AgB
+-- Retrieval info: USED_PORT: dataa 0 0 11 0 INPUT NODEFVAL dataa[10..0]
+-- Retrieval info: USED_PORT: datab 0 0 11 0 INPUT NODEFVAL datab[10..0]
+-- Retrieval info: CONNECT: AgB 0 0 0 0 @AgB 0 0 0 0
+-- Retrieval info: CONNECT: @dataa 0 0 11 0 dataa 0 0 11 0
+-- Retrieval info: CONNECT: @datab 0 0 11 0 datab 0 0 11 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_constant0.bsf b/FPGA_quartus_GE/Video/lpm_constant0.bsf
new file mode 100644
index 0000000..684bbae
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_constant0.bsf
@@ -0,0 +1,42 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 96 48)
+	(text "lpm_constant0" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 32 25 44)(font "Arial" ))
+	(port
+		(pt 96 24)
+		(output)
+		(text "result[4..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[4..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 96 24)(pt 80 24)(line_width 3))
+	)
+	(drawing
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "5" (rect 87 25 92 37)(font "Arial" ))
+		(line (pt 16 16)(pt 80 16)(line_width 1))
+		(line (pt 80 16)(pt 80 32)(line_width 1))
+		(line (pt 80 32)(pt 16 32)(line_width 1))
+		(line (pt 16 32)(pt 16 16)(line_width 1))
+		(line (pt 82 28)(pt 90 20)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_constant0.qip b/FPGA_quartus_GE/Video/lpm_constant0.qip
new file mode 100644
index 0000000..bb19c49
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_constant0.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant0.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_constant0.vhd b/FPGA_quartus_GE/Video/lpm_constant0.vhd
new file mode 100644
index 0000000..63631cc
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_constant0.vhd
@@ -0,0 +1,108 @@
+-- megafunction wizard: %LPM_CONSTANT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_constant 
+
+-- ============================================================
+-- File Name: lpm_constant0.vhd
+-- Megafunction Name(s):
+-- 			lpm_constant
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_constant0 IS
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+END lpm_constant0;
+
+
+ARCHITECTURE SYN OF lpm_constant0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+
+
+
+	COMPONENT lpm_constant
+	GENERIC (
+		lpm_cvalue		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			result	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	result    <= sub_wire0(4 DOWNTO 0);
+
+	lpm_constant_component : lpm_constant
+	GENERIC MAP (
+		lpm_cvalue => 0,
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "LPM_CONSTANT",
+		lpm_width => 5
+	)
+	PORT MAP (
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: Radix NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: Value NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
+-- Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL result[4..0]
+-- Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_constant1.bsf b/FPGA_quartus_GE/Video/lpm_constant1.bsf
new file mode 100644
index 0000000..01fdb2b
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_constant1.bsf
@@ -0,0 +1,42 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 96 48)
+	(text "lpm_constant1" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 32 25 44)(font "Arial" ))
+	(port
+		(pt 96 24)
+		(output)
+		(text "result[1..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[1..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 96 24)(pt 80 24)(line_width 3))
+	)
+	(drawing
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "2" (rect 87 25 92 37)(font "Arial" ))
+		(line (pt 16 16)(pt 80 16)(line_width 1))
+		(line (pt 80 16)(pt 80 32)(line_width 1))
+		(line (pt 80 32)(pt 16 32)(line_width 1))
+		(line (pt 16 32)(pt 16 16)(line_width 1))
+		(line (pt 82 28)(pt 90 20)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_constant1.inc b/FPGA_quartus_GE/Video/lpm_constant1.inc
new file mode 100644
index 0000000..9b556e7
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_constant1.inc
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_constant1 
+(
+
+)
+
+RETURNS (
+	result[1..0]
+);
diff --git a/FPGA_quartus_GE/Video/lpm_constant1.qip b/FPGA_quartus_GE/Video/lpm_constant1.qip
new file mode 100644
index 0000000..2bc12e7
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_constant1.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant1.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_constant1.vhd b/FPGA_quartus_GE/Video/lpm_constant1.vhd
new file mode 100644
index 0000000..afa67ba
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_constant1.vhd
@@ -0,0 +1,108 @@
+-- megafunction wizard: %LPM_CONSTANT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_constant 
+
+-- ============================================================
+-- File Name: lpm_constant1.vhd
+-- Megafunction Name(s):
+-- 			lpm_constant
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_constant1 IS
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+END lpm_constant1;
+
+
+ARCHITECTURE SYN OF lpm_constant1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+
+
+
+	COMPONENT lpm_constant
+	GENERIC (
+		lpm_cvalue		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			result	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	result    <= sub_wire0(1 DOWNTO 0);
+
+	lpm_constant_component : lpm_constant
+	GENERIC MAP (
+		lpm_cvalue => 0,
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "LPM_CONSTANT",
+		lpm_width => 2
+	)
+	PORT MAP (
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: Radix NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: Value NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
+-- Retrieval info: USED_PORT: result 0 0 2 0 OUTPUT NODEFVAL result[1..0]
+-- Retrieval info: CONNECT: result 0 0 2 0 @result 0 0 2 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant1_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_constant2.bsf b/FPGA_quartus_GE/Video/lpm_constant2.bsf
new file mode 100644
index 0000000..a4b7697
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_constant2.bsf
@@ -0,0 +1,42 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 96 48)
+	(text "lpm_constant2" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 32 25 44)(font "Arial" ))
+	(port
+		(pt 96 24)
+		(output)
+		(text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[7..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 96 24)(pt 80 24)(line_width 3))
+	)
+	(drawing
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "8" (rect 87 25 92 37)(font "Arial" ))
+		(line (pt 16 16)(pt 80 16)(line_width 1))
+		(line (pt 80 16)(pt 80 32)(line_width 1))
+		(line (pt 80 32)(pt 16 32)(line_width 1))
+		(line (pt 16 32)(pt 16 16)(line_width 1))
+		(line (pt 82 28)(pt 90 20)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_constant2.qip b/FPGA_quartus_GE/Video/lpm_constant2.qip
new file mode 100644
index 0000000..ad38485
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_constant2.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant2.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_constant2.vhd b/FPGA_quartus_GE/Video/lpm_constant2.vhd
new file mode 100644
index 0000000..f25e68f
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_constant2.vhd
@@ -0,0 +1,108 @@
+-- megafunction wizard: %LPM_CONSTANT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_constant 
+
+-- ============================================================
+-- File Name: lpm_constant2.vhd
+-- Megafunction Name(s):
+-- 			lpm_constant
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_constant2 IS
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END lpm_constant2;
+
+
+ARCHITECTURE SYN OF lpm_constant2 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT lpm_constant
+	GENERIC (
+		lpm_cvalue		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			result	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	result    <= sub_wire0(7 DOWNTO 0);
+
+	lpm_constant_component : lpm_constant
+	GENERIC MAP (
+		lpm_cvalue => 0,
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "LPM_CONSTANT",
+		lpm_width => 8
+	)
+	PORT MAP (
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: Radix NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: Value NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
+-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant2_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_constant3.bsf b/FPGA_quartus_GE/Video/lpm_constant3.bsf
new file mode 100644
index 0000000..7616869
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_constant3.bsf
@@ -0,0 +1,42 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 96 48)
+	(text "lpm_constant3" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 32 25 44)(font "Arial" ))
+	(port
+		(pt 96 24)
+		(output)
+		(text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[6..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 96 24)(pt 80 24)(line_width 3))
+	)
+	(drawing
+		(text "0" (rect 75 18 80 30)(font "Arial" ))
+		(text "7" (rect 87 25 92 37)(font "Arial" ))
+		(line (pt 16 16)(pt 80 16)(line_width 1))
+		(line (pt 80 16)(pt 80 32)(line_width 1))
+		(line (pt 80 32)(pt 16 32)(line_width 1))
+		(line (pt 16 32)(pt 16 16)(line_width 1))
+		(line (pt 82 28)(pt 90 20)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_constant3.qip b/FPGA_quartus_GE/Video/lpm_constant3.qip
new file mode 100644
index 0000000..615a781
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_constant3.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant3.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant3.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_constant3.vhd b/FPGA_quartus_GE/Video/lpm_constant3.vhd
new file mode 100644
index 0000000..5d47d8e
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_constant3.vhd
@@ -0,0 +1,108 @@
+-- megafunction wizard: %LPM_CONSTANT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_constant 
+
+-- ============================================================
+-- File Name: lpm_constant3.vhd
+-- Megafunction Name(s):
+-- 			lpm_constant
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_constant3 IS
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
+	);
+END lpm_constant3;
+
+
+ARCHITECTURE SYN OF lpm_constant3 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (6 DOWNTO 0);
+
+
+
+	COMPONENT lpm_constant
+	GENERIC (
+		lpm_cvalue		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			result	: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	result    <= sub_wire0(6 DOWNTO 0);
+
+	lpm_constant_component : lpm_constant
+	GENERIC MAP (
+		lpm_cvalue => 0,
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "LPM_CONSTANT",
+		lpm_width => 7
+	)
+	PORT MAP (
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: Radix NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: Value NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "7"
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "0"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
+-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL result[6..0]
+-- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant3_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_constant4.bsf b/FPGA_quartus_GE/Video/lpm_constant4.bsf
new file mode 100644
index 0000000..181c667
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_constant4.bsf
@@ -0,0 +1,42 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 96 48)
+	(text "lpm_constant4" (rect 6 1 106 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 32 25 44)(font "Arial" ))
+	(port
+		(pt 96 24)
+		(output)
+		(text "result[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[10..0]" (rect 93 -31 106 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 96 24)(pt 80 24)(line_width 3))
+	)
+	(drawing
+		(text "2040" (rect 60 18 80 30)(font "Arial" ))
+		(text "11" (rect 85 25 95 37)(font "Arial" ))
+		(line (pt 16 16)(pt 80 16)(line_width 1))
+		(line (pt 80 16)(pt 80 32)(line_width 1))
+		(line (pt 80 32)(pt 16 32)(line_width 1))
+		(line (pt 16 32)(pt 16 16)(line_width 1))
+		(line (pt 80 28)(pt 88 20)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_constant4.inc b/FPGA_quartus_GE/Video/lpm_constant4.inc
new file mode 100644
index 0000000..a913739
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_constant4.inc
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_constant4 
+(
+
+)
+
+RETURNS (
+	result[10..0]
+);
diff --git a/FPGA_quartus_GE/Video/lpm_constant4.qip b/FPGA_quartus_GE/Video/lpm_constant4.qip
new file mode 100644
index 0000000..44fa63f
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_constant4.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_constant4.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant4.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant4.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_constant4.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_constant4.vhd b/FPGA_quartus_GE/Video/lpm_constant4.vhd
new file mode 100644
index 0000000..e0fc73d
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_constant4.vhd
@@ -0,0 +1,108 @@
+-- megafunction wizard: %LPM_CONSTANT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_constant 
+
+-- ============================================================
+-- File Name: lpm_constant4.vhd
+-- Megafunction Name(s):
+-- 			lpm_constant
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_constant4 IS
+	PORT
+	(
+		result		: OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
+	);
+END lpm_constant4;
+
+
+ARCHITECTURE SYN OF lpm_constant4 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (10 DOWNTO 0);
+
+
+
+	COMPONENT lpm_constant
+	GENERIC (
+		lpm_cvalue		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			result	: OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	result    <= sub_wire0(10 DOWNTO 0);
+
+	lpm_constant_component : lpm_constant
+	GENERIC MAP (
+		lpm_cvalue => 2040,
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "LPM_CONSTANT",
+		lpm_width => 11
+	)
+	PORT MAP (
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: Radix NUMERIC "10"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: Value NUMERIC "2040"
+-- Retrieval info: PRIVATE: nBit NUMERIC "11"
+-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "2040"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11"
+-- Retrieval info: USED_PORT: result 0 0 11 0 OUTPUT NODEFVAL result[10..0]
+-- Retrieval info: CONNECT: result 0 0 11 0 @result 0 0 11 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant4_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_ff0.bsf b/FPGA_quartus_GE/Video/lpm_ff0.bsf
new file mode 100644
index 0000000..6675606
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff0.bsf
@@ -0,0 +1,63 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 96)
+	(text "lpm_ff0" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 80 25 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8)))
+		(text "enable" (rect 20 58 53 71)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 144 56)
+		(output)
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 89 50 125 63)(font "Arial" (font_size 8)))
+		(line (pt 144 56)(pt 128 56)(line_width 3))
+	)
+	(drawing
+		(text "DFF" (rect 109 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 80)(line_width 1))
+		(line (pt 128 80)(pt 16 80)(line_width 1))
+		(line (pt 16 80)(pt 16 16)(line_width 1))
+		(line (pt 16 42)(pt 22 48)(line_width 1))
+		(line (pt 22 48)(pt 16 54)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_ff0.qip b/FPGA_quartus_GE/Video/lpm_ff0.qip
new file mode 100644
index 0000000..d33c680
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff0.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FF"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff0.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_ff0.vhd b/FPGA_quartus_GE/Video/lpm_ff0.vhd
new file mode 100644
index 0000000..4c17d8f
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff0.vhd
@@ -0,0 +1,127 @@
+-- megafunction wizard: %LPM_FF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_ff 
+
+-- ============================================================
+-- File Name: lpm_ff0.vhd
+-- Megafunction Name(s):
+-- 			lpm_ff
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_ff0 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		enable		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END lpm_ff0;
+
+
+ARCHITECTURE SYN OF lpm_ff0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT lpm_ff
+	GENERIC (
+		lpm_fftype		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enable	: IN STD_LOGIC ;
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(31 DOWNTO 0);
+
+	lpm_ff_component : lpm_ff
+	GENERIC MAP (
+		lpm_fftype => "DFF",
+		lpm_type => "LPM_FF",
+		lpm_width => 32
+	)
+	PORT MAP (
+		enable => enable,
+		clock => clock,
+		data => data,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1"
+-- Retrieval info: PRIVATE: DFF NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT NODEFVAL enable
+-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+-- Retrieval info: CONNECT: @enable 0 0 0 0 enable 0 0 0 0
+-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_ff1.bsf b/FPGA_quartus_GE/Video/lpm_ff1.bsf
new file mode 100644
index 0000000..947a023
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff1.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_ff1" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 89 42 125 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
+	)
+	(drawing
+		(text "DFF" (rect 109 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 42)(pt 22 48)(line_width 1))
+		(line (pt 22 48)(pt 16 54)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_ff1.qip b/FPGA_quartus_GE/Video/lpm_ff1.qip
new file mode 100644
index 0000000..94b30af
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff1.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FF"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff1.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_ff1.vhd b/FPGA_quartus_GE/Video/lpm_ff1.vhd
new file mode 100644
index 0000000..da02a15
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff1.vhd
@@ -0,0 +1,122 @@
+-- megafunction wizard: %LPM_FF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_ff 
+
+-- ============================================================
+-- File Name: lpm_ff1.vhd
+-- Megafunction Name(s):
+-- 			lpm_ff
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_ff1 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END lpm_ff1;
+
+
+ARCHITECTURE SYN OF lpm_ff1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT lpm_ff
+	GENERIC (
+		lpm_fftype		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(31 DOWNTO 0);
+
+	lpm_ff_component : lpm_ff
+	GENERIC MAP (
+		lpm_fftype => "DFF",
+		lpm_type => "LPM_FF",
+		lpm_width => 32
+	)
+	PORT MAP (
+		clock => clock,
+		data => data,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: DFF NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff1_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_ff2.bsf b/FPGA_quartus_GE/Video/lpm_ff2.bsf
new file mode 100644
index 0000000..b52c75b
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff2.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_ff2" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q[127..0]" (rect 83 42 125 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
+	)
+	(drawing
+		(text "DFF" (rect 109 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 42)(pt 22 48)(line_width 1))
+		(line (pt 22 48)(pt 16 54)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_ff2.qip b/FPGA_quartus_GE/Video/lpm_ff2.qip
new file mode 100644
index 0000000..9c46273
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff2.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FF"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff2.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_ff2.vhd b/FPGA_quartus_GE/Video/lpm_ff2.vhd
new file mode 100644
index 0000000..27b4c3a
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff2.vhd
@@ -0,0 +1,122 @@
+-- megafunction wizard: %LPM_FF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_ff 
+
+-- ============================================================
+-- File Name: lpm_ff2.vhd
+-- Megafunction Name(s):
+-- 			lpm_ff
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_ff2 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		q		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+END lpm_ff2;
+
+
+ARCHITECTURE SYN OF lpm_ff2 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+
+
+
+	COMPONENT lpm_ff
+	GENERIC (
+		lpm_fftype		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
+			data	: IN STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(127 DOWNTO 0);
+
+	lpm_ff_component : lpm_ff
+	GENERIC MAP (
+		lpm_fftype => "DFF",
+		lpm_type => "LPM_FF",
+		lpm_width => 128
+	)
+	PORT MAP (
+		clock => clock,
+		data => data,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: DFF NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0]
+-- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
+-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff2_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_ff3.bsf b/FPGA_quartus_GE/Video/lpm_ff3.bsf
new file mode 100644
index 0000000..51248ea
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff3.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_ff3" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[23..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "q[23..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[23..0]" (rect 89 42 125 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
+	)
+	(drawing
+		(text "DFF" (rect 109 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 42)(pt 22 48)(line_width 1))
+		(line (pt 22 48)(pt 16 54)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_ff3.qip b/FPGA_quartus_GE/Video/lpm_ff3.qip
new file mode 100644
index 0000000..98d1312
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff3.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FF"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff3.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff3.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff3.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_ff3.vhd b/FPGA_quartus_GE/Video/lpm_ff3.vhd
new file mode 100644
index 0000000..a86b4ee
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff3.vhd
@@ -0,0 +1,122 @@
+-- megafunction wizard: %LPM_FF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_ff 
+
+-- ============================================================
+-- File Name: lpm_ff3.vhd
+-- Megafunction Name(s):
+-- 			lpm_ff
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_ff3 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		q		: OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
+	);
+END lpm_ff3;
+
+
+ARCHITECTURE SYN OF lpm_ff3 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+
+
+
+	COMPONENT lpm_ff
+	GENERIC (
+		lpm_fftype		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
+			data	: IN STD_LOGIC_VECTOR (23 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(23 DOWNTO 0);
+
+	lpm_ff_component : lpm_ff
+	GENERIC MAP (
+		lpm_fftype => "DFF",
+		lpm_type => "LPM_FF",
+		lpm_width => 24
+	)
+	PORT MAP (
+		clock => clock,
+		data => data,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: DFF NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "24"
+-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL data[23..0]
+-- Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL q[23..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 24 0 @q 0 0 24 0
+-- Retrieval info: CONNECT: @data 0 0 24 0 data 0 0 24 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff3_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_ff4.bsf b/FPGA_quartus_GE/Video/lpm_ff4.bsf
new file mode 100644
index 0000000..be432cb
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff4.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_ff4" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[15..0]" (rect 89 42 125 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
+	)
+	(drawing
+		(text "DFF" (rect 109 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 42)(pt 22 48)(line_width 1))
+		(line (pt 22 48)(pt 16 54)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_ff4.inc b/FPGA_quartus_GE/Video/lpm_ff4.inc
new file mode 100644
index 0000000..ea243d6
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff4.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_ff4 
+(
+	clock,
+	data[15..0]
+)
+
+RETURNS (
+	q[15..0]
+);
diff --git a/FPGA_quartus_GE/Video/lpm_ff4.qip b/FPGA_quartus_GE/Video/lpm_ff4.qip
new file mode 100644
index 0000000..f5a0a35
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff4.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FF"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff4.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff4.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff4.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff4.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_ff4.vhd b/FPGA_quartus_GE/Video/lpm_ff4.vhd
new file mode 100644
index 0000000..a738a64
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff4.vhd
@@ -0,0 +1,122 @@
+-- megafunction wizard: %LPM_FF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_ff 
+
+-- ============================================================
+-- File Name: lpm_ff4.vhd
+-- Megafunction Name(s):
+-- 			lpm_ff
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_ff4 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+END lpm_ff4;
+
+
+ARCHITECTURE SYN OF lpm_ff4 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+
+
+
+	COMPONENT lpm_ff
+	GENERIC (
+		lpm_fftype		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
+			data	: IN STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(15 DOWNTO 0);
+
+	lpm_ff_component : lpm_ff
+	GENERIC MAP (
+		lpm_fftype => "DFF",
+		lpm_type => "LPM_FF",
+		lpm_width => 16
+	)
+	PORT MAP (
+		clock => clock,
+		data => data,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: DFF NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff4_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_ff5.bsf b/FPGA_quartus_GE/Video/lpm_ff5.bsf
new file mode 100644
index 0000000..a69af6e
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff5.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_ff5" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[7..0]" (rect 95 42 125 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
+	)
+	(drawing
+		(text "DFF" (rect 109 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 42)(pt 22 48)(line_width 1))
+		(line (pt 22 48)(pt 16 54)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_ff5.inc b/FPGA_quartus_GE/Video/lpm_ff5.inc
new file mode 100644
index 0000000..f65f941
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff5.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_ff5 
+(
+	clock,
+	data[7..0]
+)
+
+RETURNS (
+	q[7..0]
+);
diff --git a/FPGA_quartus_GE/Video/lpm_ff5.qip b/FPGA_quartus_GE/Video/lpm_ff5.qip
new file mode 100644
index 0000000..0d13267
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff5.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FF"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff5.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff5.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff5.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff5.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_ff5.vhd b/FPGA_quartus_GE/Video/lpm_ff5.vhd
new file mode 100644
index 0000000..96063a2
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff5.vhd
@@ -0,0 +1,122 @@
+-- megafunction wizard: %LPM_FF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_ff 
+
+-- ============================================================
+-- File Name: lpm_ff5.vhd
+-- Megafunction Name(s):
+-- 			lpm_ff
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_ff5 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END lpm_ff5;
+
+
+ARCHITECTURE SYN OF lpm_ff5 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT lpm_ff
+	GENERIC (
+		lpm_fftype		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			data	: IN STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	lpm_ff_component : lpm_ff
+	GENERIC MAP (
+		lpm_fftype => "DFF",
+		lpm_type => "LPM_FF",
+		lpm_width => 8
+	)
+	PORT MAP (
+		clock => clock,
+		data => data,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: DFF NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
+-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff5_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_ff6.bsf b/FPGA_quartus_GE/Video/lpm_ff6.bsf
new file mode 100644
index 0000000..73a2df0
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff6.bsf
@@ -0,0 +1,63 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 96)
+	(text "lpm_ff6" (rect 52 1 100 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 80 25 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8)))
+		(text "enable" (rect 20 58 53 71)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 144 56)
+		(output)
+		(text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q[127..0]" (rect 83 50 125 63)(font "Arial" (font_size 8)))
+		(line (pt 144 56)(pt 128 56)(line_width 3))
+	)
+	(drawing
+		(text "DFF" (rect 109 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 80)(line_width 1))
+		(line (pt 128 80)(pt 16 80)(line_width 1))
+		(line (pt 16 80)(pt 16 16)(line_width 1))
+		(line (pt 16 42)(pt 22 48)(line_width 1))
+		(line (pt 22 48)(pt 16 54)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_ff6.inc b/FPGA_quartus_GE/Video/lpm_ff6.inc
new file mode 100644
index 0000000..c8a5a36
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff6.inc
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_ff6 
+(
+	clock,
+	data[127..0],
+	enable
+)
+
+RETURNS (
+	q[127..0]
+);
diff --git a/FPGA_quartus_GE/Video/lpm_ff6.qip b/FPGA_quartus_GE/Video/lpm_ff6.qip
new file mode 100644
index 0000000..08e02f0
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff6.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FF"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_ff6.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff6.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff6.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_ff6.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_ff6.vhd b/FPGA_quartus_GE/Video/lpm_ff6.vhd
new file mode 100644
index 0000000..5cc384d
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_ff6.vhd
@@ -0,0 +1,127 @@
+-- megafunction wizard: %LPM_FF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_ff 
+
+-- ============================================================
+-- File Name: lpm_ff6.vhd
+-- Megafunction Name(s):
+-- 			lpm_ff
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_ff6 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		enable		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+END lpm_ff6;
+
+
+ARCHITECTURE SYN OF lpm_ff6 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+
+
+
+	COMPONENT lpm_ff
+	GENERIC (
+		lpm_fftype		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enable	: IN STD_LOGIC ;
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
+			data	: IN STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(127 DOWNTO 0);
+
+	lpm_ff_component : lpm_ff
+	GENERIC MAP (
+		lpm_fftype => "DFF",
+		lpm_type => "LPM_FF",
+		lpm_width => 128
+	)
+	PORT MAP (
+		enable => enable,
+		clock => clock,
+		data => data,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1"
+-- Retrieval info: PRIVATE: DFF NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0]
+-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT NODEFVAL enable
+-- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
+-- Retrieval info: CONNECT: @enable 0 0 0 0 enable 0 0 0 0
+-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff6_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_fifoDZ.bsf b/FPGA_quartus_GE/Video/lpm_fifoDZ.bsf
new file mode 100644
index 0000000..1e24640
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_fifoDZ.bsf
@@ -0,0 +1,79 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 144)
+	(text "lpm_fifoDZ" (rect 41 2 133 21)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 125 31 140)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[127..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
+		(text "data[127..0]" (rect 20 24 89 40)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "wrreq" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+		(text "wrreq" (rect 20 48 51 64)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "rdreq" (rect 0 0 34 16)(font "Arial" (font_size 8)))
+		(text "rdreq" (rect 20 64 49 80)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 88 57 104)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 16 96)(line_width 1))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 20 112 41 128)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 16 120)(line_width 1))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "q[127..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
+		(text "q[127..0]" (rect 90 24 141 40)(font "Arial" (font_size 8)))
+		(line (pt 160 32)(pt 144 32)(line_width 3))
+	)
+	(drawing
+		(text "(ack)" (rect 51 67 76 81)(font "Arial" ))
+		(text "128 bits x 128 words" (rect 31 114 134 128)(font "Arial" ))
+		(line (pt 16 16)(pt 144 16)(line_width 1))
+		(line (pt 144 16)(pt 144 128)(line_width 1))
+		(line (pt 144 128)(pt 16 128)(line_width 1))
+		(line (pt 16 128)(pt 16 16)(line_width 1))
+		(line (pt 16 108)(pt 144 108)(line_width 1))
+		(line (pt 16 90)(pt 22 96)(line_width 1))
+		(line (pt 22 96)(pt 16 102)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_fifoDZ.qip b/FPGA_quartus_GE/Video/lpm_fifoDZ.qip
new file mode 100644
index 0000000..5444627
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_fifoDZ.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifoDZ.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_fifoDZ.vhd b/FPGA_quartus_GE/Video/lpm_fifoDZ.vhd
new file mode 100644
index 0000000..95486bb
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_fifoDZ.vhd
@@ -0,0 +1,178 @@
+-- megafunction wizard: %LPM_FIFO+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: scfifo 
+
+-- ============================================================
+-- File Name: lpm_fifoDZ.vhd
+-- Megafunction Name(s):
+-- 			scfifo
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY lpm_fifoDZ IS
+	PORT
+	(
+		aclr		: IN STD_LOGIC ;
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		rdreq		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+END lpm_fifoDZ;
+
+
+ARCHITECTURE SYN OF lpm_fifodz IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+
+
+
+	COMPONENT scfifo
+	GENERIC (
+		add_ram_output_register		: STRING;
+		intended_device_family		: STRING;
+		lpm_numwords		: NATURAL;
+		lpm_showahead		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL;
+		lpm_widthu		: NATURAL;
+		overflow_checking		: STRING;
+		underflow_checking		: STRING;
+		use_eab		: STRING
+	);
+	PORT (
+			rdreq	: IN STD_LOGIC ;
+			aclr	: IN STD_LOGIC ;
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
+			wrreq	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(127 DOWNTO 0);
+
+	scfifo_component : scfifo
+	GENERIC MAP (
+		add_ram_output_register => "OFF",
+		intended_device_family => "Cyclone III",
+		lpm_numwords => 128,
+		lpm_showahead => "ON",
+		lpm_type => "scfifo",
+		lpm_width => 128,
+		lpm_widthu => 7,
+		overflow_checking => "OFF",
+		underflow_checking => "OFF",
+		use_eab => "ON"
+	)
+	PORT MAP (
+		rdreq => rdreq,
+		aclr => aclr,
+		clock => clock,
+		wrreq => wrreq,
+		data => data,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
+-- Retrieval info: PRIVATE: Clock NUMERIC "0"
+-- Retrieval info: PRIVATE: Depth NUMERIC "128"
+-- Retrieval info: PRIVATE: Empty NUMERIC "0"
+-- Retrieval info: PRIVATE: Full NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: Width NUMERIC "128"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "128"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0]
+-- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
+-- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifoDZ_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/Video/lpm_fifo_dc0.bsf b/FPGA_quartus_GE/Video/lpm_fifo_dc0.bsf
new file mode 100644
index 0000000..61b485b
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_fifo_dc0.bsf
@@ -0,0 +1,102 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 168)
+	(text "lpm_fifo_dc0" (rect 44 1 128 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 152 25 164)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+		(text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 16 104)(line_width 1))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
+		(text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 16 120)(line_width 1))
+	)
+	(port
+		(pt 0 144)
+		(input)
+		(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
+		(text "aclr" (rect 20 138 37 151)(font "Arial" (font_size 8)))
+		(line (pt 0 144)(pt 16 144)(line_width 1))
+	)
+	(port
+		(pt 160 72)
+		(output)
+		(text "wrusedw[8..0]" (rect 0 0 84 14)(font "Arial" (font_size 8)))
+		(text "wrusedw[8..0]" (rect 69 66 132 79)(font "Arial" (font_size 8)))
+		(line (pt 160 72)(pt 144 72)(line_width 3))
+	)
+	(port
+		(pt 160 96)
+		(output)
+		(text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
+		(text "q[127..0]" (rect 99 90 141 103)(font "Arial" (font_size 8)))
+		(line (pt 160 96)(pt 144 96)(line_width 3))
+	)
+	(port
+		(pt 160 120)
+		(output)
+		(text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8)))
+		(text "rdempty" (rect 102 114 140 127)(font "Arial" (font_size 8)))
+		(line (pt 160 120)(pt 144 120)(line_width 1))
+	)
+	(drawing
+		(text "128 bits x 512 words" (rect 58 140 144 152)(font "Arial" ))
+		(line (pt 16 16)(pt 144 16)(line_width 1))
+		(line (pt 144 16)(pt 144 152)(line_width 1))
+		(line (pt 144 152)(pt 16 152)(line_width 1))
+		(line (pt 16 152)(pt 16 16)(line_width 1))
+		(line (pt 16 84)(pt 144 84)(line_width 1))
+		(line (pt 16 132)(pt 144 132)(line_width 1))
+		(line (pt 16 66)(pt 22 72)(line_width 1))
+		(line (pt 22 72)(pt 16 78)(line_width 1))
+		(line (pt 16 114)(pt 22 120)(line_width 1))
+		(line (pt 22 120)(pt 16 126)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_fifo_dc0.inc b/FPGA_quartus_GE/Video/lpm_fifo_dc0.inc
new file mode 100644
index 0000000..d29fb88
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_fifo_dc0.inc
@@ -0,0 +1,30 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_fifo_dc0 
+(
+	aclr,
+	data[127..0],
+	rdclk,
+	rdreq,
+	wrclk,
+	wrreq
+)
+
+RETURNS (
+	q[127..0],
+	rdempty,
+	wrusedw[8..0]
+);
diff --git a/FPGA_quartus_GE/Video/lpm_fifo_dc0.qip b/FPGA_quartus_GE/Video/lpm_fifo_dc0.qip
new file mode 100644
index 0000000..e883724
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_fifo_dc0.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_FIFO+"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_fifo_dc0.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_fifo_dc0.vhd b/FPGA_quartus_GE/Video/lpm_fifo_dc0.vhd
new file mode 100644
index 0000000..8646d9c
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_fifo_dc0.vhd
@@ -0,0 +1,203 @@
+-- megafunction wizard: %LPM_FIFO+%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: dcfifo 
+
+-- ============================================================
+-- File Name: lpm_fifo_dc0.vhd
+-- Megafunction Name(s):
+-- 			dcfifo
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY lpm_fifo_dc0 IS
+	PORT
+	(
+		aclr		: IN STD_LOGIC  := '0';
+		data		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		rdclk		: IN STD_LOGIC ;
+		rdreq		: IN STD_LOGIC ;
+		wrclk		: IN STD_LOGIC ;
+		wrreq		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
+		rdempty		: OUT STD_LOGIC ;
+		wrusedw		: OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
+	);
+END lpm_fifo_dc0;
+
+
+ARCHITECTURE SYN OF lpm_fifo_dc0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (8 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+
+
+
+	COMPONENT dcfifo
+	GENERIC (
+		intended_device_family		: STRING;
+		lpm_numwords		: NATURAL;
+		lpm_showahead		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL;
+		lpm_widthu		: NATURAL;
+		overflow_checking		: STRING;
+		rdsync_delaypipe		: NATURAL;
+		underflow_checking		: STRING;
+		use_eab		: STRING;
+		write_aclr_synch		: STRING;
+		wrsync_delaypipe		: NATURAL
+	);
+	PORT (
+			wrclk	: IN STD_LOGIC ;
+			rdempty	: OUT STD_LOGIC ;
+			rdreq	: IN STD_LOGIC ;
+			wrusedw	: OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
+			aclr	: IN STD_LOGIC ;
+			rdclk	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
+			wrreq	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	rdempty    <= sub_wire0;
+	wrusedw    <= sub_wire1(8 DOWNTO 0);
+	q    <= sub_wire2(127 DOWNTO 0);
+
+	dcfifo_component : dcfifo
+	GENERIC MAP (
+		intended_device_family => "Cyclone III",
+		lpm_numwords => 512,
+		lpm_showahead => "OFF",
+		lpm_type => "dcfifo",
+		lpm_width => 128,
+		lpm_widthu => 9,
+		overflow_checking => "OFF",
+		rdsync_delaypipe => 6,
+		underflow_checking => "OFF",
+		use_eab => "ON",
+		write_aclr_synch => "ON",
+		wrsync_delaypipe => 6
+	)
+	PORT MAP (
+		wrclk => wrclk,
+		rdreq => rdreq,
+		aclr => aclr,
+		rdclk => rdclk,
+		wrreq => wrreq,
+		data => data,
+		rdempty => sub_wire0,
+		wrusedw => sub_wire1,
+		q => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "4"
+-- Retrieval info: PRIVATE: Depth NUMERIC "512"
+-- Retrieval info: PRIVATE: Empty NUMERIC "1"
+-- Retrieval info: PRIVATE: Full NUMERIC "1"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
+-- Retrieval info: PRIVATE: Optimize NUMERIC "1"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
+-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
+-- Retrieval info: PRIVATE: Width NUMERIC "128"
+-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
+-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
+-- Retrieval info: PRIVATE: output_width NUMERIC "128"
+-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+-- Retrieval info: PRIVATE: wsFull NUMERIC "0"
+-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
+-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
+-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
+-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "6"
+-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
+-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
+-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
+-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "6"
+-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+-- Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0]
+-- Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
+-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+-- Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+-- Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL wrusedw[8..0]
+-- Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
+-- Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
+-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+-- Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+-- Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
+-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_fifo_dc0_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/Video/lpm_latch1.bsf b/FPGA_quartus_GE/Video/lpm_latch1.bsf
new file mode 100644
index 0000000..7197b2f
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_latch1.bsf
@@ -0,0 +1,53 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 80)
+	(text "lpm_latch1" (rect 49 1 123 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "gate" (rect 0 0 24 14)(font "Arial" (font_size 8)))
+		(text "gate" (rect 20 42 41 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 105 26 141 39)(font "Arial" (font_size 8)))
+		(line (pt 160 32)(pt 144 32)(line_width 3))
+	)
+	(drawing
+		(line (pt 16 16)(pt 144 16)(line_width 1))
+		(line (pt 144 16)(pt 144 64)(line_width 1))
+		(line (pt 144 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_latch1.qip b/FPGA_quartus_GE/Video/lpm_latch1.qip
new file mode 100644
index 0000000..bc53d50
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_latch1.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_LATCH"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_latch1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch1.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_latch1.vhd b/FPGA_quartus_GE/Video/lpm_latch1.vhd
new file mode 100644
index 0000000..0afc209
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_latch1.vhd
@@ -0,0 +1,110 @@
+-- megafunction wizard: %LPM_LATCH%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_latch 
+
+-- ============================================================
+-- File Name: lpm_latch1.vhd
+-- Megafunction Name(s):
+-- 			lpm_latch
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_latch1 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		gate		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END lpm_latch1;
+
+
+ARCHITECTURE SYN OF lpm_latch1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT lpm_latch
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			q	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			gate	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(31 DOWNTO 0);
+
+	lpm_latch_component : lpm_latch
+	GENERIC MAP (
+		lpm_type => "LPM_LATCH",
+		lpm_width => 32
+	)
+	PORT MAP (
+		data => data,
+		gate => gate,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: aset NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_LATCH"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+-- Retrieval info: USED_PORT: gate 0 0 0 0 INPUT NODEFVAL gate
+-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+-- Retrieval info: CONNECT: @gate 0 0 0 0 gate 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch1_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_mux0.bsf b/FPGA_quartus_GE/Video/lpm_mux0.bsf
new file mode 100644
index 0000000..ce1e27e
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux0.bsf
@@ -0,0 +1,83 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 152 128)
+	(text "lpm_mux0" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 112 25 124)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data3x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[31..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 72 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data2x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[31..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 72 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "data1x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[31..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 72 72)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "data0x[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[31..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 72 88)(line_width 3))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 91 27 104)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 72 104)(line_width 1))
+	)
+	(port
+		(pt 80 128)
+		(input)
+		(text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[1..0]" (rect 84 115 121 128)(font "Arial" (font_size 8)))
+		(line (pt 80 128)(pt 80 116)(line_width 3))
+	)
+	(port
+		(pt 152 72)
+		(output)
+		(text "result[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[31..0]" (rect 92 59 147 72)(font "Arial" (font_size 8)))
+		(line (pt 152 72)(pt 88 72)(line_width 3))
+	)
+	(drawing
+		(line (pt 72 24)(pt 72 120)(line_width 1))
+		(line (pt 88 32)(pt 88 112)(line_width 1))
+		(line (pt 72 24)(pt 88 32)(line_width 1))
+		(line (pt 72 120)(pt 88 112)(line_width 1))
+		(line (pt 72 98)(pt 78 104)(line_width 1))
+		(line (pt 78 104)(pt 72 110)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_mux0.inc b/FPGA_quartus_GE/Video/lpm_mux0.inc
new file mode 100644
index 0000000..b0bc2be
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux0.inc
@@ -0,0 +1,28 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_mux0 
+(
+	clock,
+	data0x[31..0],
+	data1x[31..0],
+	data2x[31..0],
+	data3x[31..0],
+	sel[1..0]
+)
+
+RETURNS (
+	result[31..0]
+);
diff --git a/FPGA_quartus_GE/Video/lpm_mux0.qip b/FPGA_quartus_GE/Video/lpm_mux0.qip
new file mode 100644
index 0000000..5e8e2b6
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux0.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_mux0.vhd b/FPGA_quartus_GE/Video/lpm_mux0.vhd
new file mode 100644
index 0000000..9d641a4
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux0.vhd
@@ -0,0 +1,251 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_mux0.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_mux0 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data0x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END lpm_mux0;
+
+
+ARCHITECTURE SYN OF lpm_mux0 IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (3 DOWNTO 0, 31 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+BEGIN
+	sub_wire5    <= data0x(31 DOWNTO 0);
+	sub_wire4    <= data1x(31 DOWNTO 0);
+	sub_wire3    <= data2x(31 DOWNTO 0);
+	result    <= sub_wire0(31 DOWNTO 0);
+	sub_wire1    <= data3x(31 DOWNTO 0);
+	sub_wire2(3, 0)    <= sub_wire1(0);
+	sub_wire2(3, 1)    <= sub_wire1(1);
+	sub_wire2(3, 2)    <= sub_wire1(2);
+	sub_wire2(3, 3)    <= sub_wire1(3);
+	sub_wire2(3, 4)    <= sub_wire1(4);
+	sub_wire2(3, 5)    <= sub_wire1(5);
+	sub_wire2(3, 6)    <= sub_wire1(6);
+	sub_wire2(3, 7)    <= sub_wire1(7);
+	sub_wire2(3, 8)    <= sub_wire1(8);
+	sub_wire2(3, 9)    <= sub_wire1(9);
+	sub_wire2(3, 10)    <= sub_wire1(10);
+	sub_wire2(3, 11)    <= sub_wire1(11);
+	sub_wire2(3, 12)    <= sub_wire1(12);
+	sub_wire2(3, 13)    <= sub_wire1(13);
+	sub_wire2(3, 14)    <= sub_wire1(14);
+	sub_wire2(3, 15)    <= sub_wire1(15);
+	sub_wire2(3, 16)    <= sub_wire1(16);
+	sub_wire2(3, 17)    <= sub_wire1(17);
+	sub_wire2(3, 18)    <= sub_wire1(18);
+	sub_wire2(3, 19)    <= sub_wire1(19);
+	sub_wire2(3, 20)    <= sub_wire1(20);
+	sub_wire2(3, 21)    <= sub_wire1(21);
+	sub_wire2(3, 22)    <= sub_wire1(22);
+	sub_wire2(3, 23)    <= sub_wire1(23);
+	sub_wire2(3, 24)    <= sub_wire1(24);
+	sub_wire2(3, 25)    <= sub_wire1(25);
+	sub_wire2(3, 26)    <= sub_wire1(26);
+	sub_wire2(3, 27)    <= sub_wire1(27);
+	sub_wire2(3, 28)    <= sub_wire1(28);
+	sub_wire2(3, 29)    <= sub_wire1(29);
+	sub_wire2(3, 30)    <= sub_wire1(30);
+	sub_wire2(3, 31)    <= sub_wire1(31);
+	sub_wire2(2, 0)    <= sub_wire3(0);
+	sub_wire2(2, 1)    <= sub_wire3(1);
+	sub_wire2(2, 2)    <= sub_wire3(2);
+	sub_wire2(2, 3)    <= sub_wire3(3);
+	sub_wire2(2, 4)    <= sub_wire3(4);
+	sub_wire2(2, 5)    <= sub_wire3(5);
+	sub_wire2(2, 6)    <= sub_wire3(6);
+	sub_wire2(2, 7)    <= sub_wire3(7);
+	sub_wire2(2, 8)    <= sub_wire3(8);
+	sub_wire2(2, 9)    <= sub_wire3(9);
+	sub_wire2(2, 10)    <= sub_wire3(10);
+	sub_wire2(2, 11)    <= sub_wire3(11);
+	sub_wire2(2, 12)    <= sub_wire3(12);
+	sub_wire2(2, 13)    <= sub_wire3(13);
+	sub_wire2(2, 14)    <= sub_wire3(14);
+	sub_wire2(2, 15)    <= sub_wire3(15);
+	sub_wire2(2, 16)    <= sub_wire3(16);
+	sub_wire2(2, 17)    <= sub_wire3(17);
+	sub_wire2(2, 18)    <= sub_wire3(18);
+	sub_wire2(2, 19)    <= sub_wire3(19);
+	sub_wire2(2, 20)    <= sub_wire3(20);
+	sub_wire2(2, 21)    <= sub_wire3(21);
+	sub_wire2(2, 22)    <= sub_wire3(22);
+	sub_wire2(2, 23)    <= sub_wire3(23);
+	sub_wire2(2, 24)    <= sub_wire3(24);
+	sub_wire2(2, 25)    <= sub_wire3(25);
+	sub_wire2(2, 26)    <= sub_wire3(26);
+	sub_wire2(2, 27)    <= sub_wire3(27);
+	sub_wire2(2, 28)    <= sub_wire3(28);
+	sub_wire2(2, 29)    <= sub_wire3(29);
+	sub_wire2(2, 30)    <= sub_wire3(30);
+	sub_wire2(2, 31)    <= sub_wire3(31);
+	sub_wire2(1, 0)    <= sub_wire4(0);
+	sub_wire2(1, 1)    <= sub_wire4(1);
+	sub_wire2(1, 2)    <= sub_wire4(2);
+	sub_wire2(1, 3)    <= sub_wire4(3);
+	sub_wire2(1, 4)    <= sub_wire4(4);
+	sub_wire2(1, 5)    <= sub_wire4(5);
+	sub_wire2(1, 6)    <= sub_wire4(6);
+	sub_wire2(1, 7)    <= sub_wire4(7);
+	sub_wire2(1, 8)    <= sub_wire4(8);
+	sub_wire2(1, 9)    <= sub_wire4(9);
+	sub_wire2(1, 10)    <= sub_wire4(10);
+	sub_wire2(1, 11)    <= sub_wire4(11);
+	sub_wire2(1, 12)    <= sub_wire4(12);
+	sub_wire2(1, 13)    <= sub_wire4(13);
+	sub_wire2(1, 14)    <= sub_wire4(14);
+	sub_wire2(1, 15)    <= sub_wire4(15);
+	sub_wire2(1, 16)    <= sub_wire4(16);
+	sub_wire2(1, 17)    <= sub_wire4(17);
+	sub_wire2(1, 18)    <= sub_wire4(18);
+	sub_wire2(1, 19)    <= sub_wire4(19);
+	sub_wire2(1, 20)    <= sub_wire4(20);
+	sub_wire2(1, 21)    <= sub_wire4(21);
+	sub_wire2(1, 22)    <= sub_wire4(22);
+	sub_wire2(1, 23)    <= sub_wire4(23);
+	sub_wire2(1, 24)    <= sub_wire4(24);
+	sub_wire2(1, 25)    <= sub_wire4(25);
+	sub_wire2(1, 26)    <= sub_wire4(26);
+	sub_wire2(1, 27)    <= sub_wire4(27);
+	sub_wire2(1, 28)    <= sub_wire4(28);
+	sub_wire2(1, 29)    <= sub_wire4(29);
+	sub_wire2(1, 30)    <= sub_wire4(30);
+	sub_wire2(1, 31)    <= sub_wire4(31);
+	sub_wire2(0, 0)    <= sub_wire5(0);
+	sub_wire2(0, 1)    <= sub_wire5(1);
+	sub_wire2(0, 2)    <= sub_wire5(2);
+	sub_wire2(0, 3)    <= sub_wire5(3);
+	sub_wire2(0, 4)    <= sub_wire5(4);
+	sub_wire2(0, 5)    <= sub_wire5(5);
+	sub_wire2(0, 6)    <= sub_wire5(6);
+	sub_wire2(0, 7)    <= sub_wire5(7);
+	sub_wire2(0, 8)    <= sub_wire5(8);
+	sub_wire2(0, 9)    <= sub_wire5(9);
+	sub_wire2(0, 10)    <= sub_wire5(10);
+	sub_wire2(0, 11)    <= sub_wire5(11);
+	sub_wire2(0, 12)    <= sub_wire5(12);
+	sub_wire2(0, 13)    <= sub_wire5(13);
+	sub_wire2(0, 14)    <= sub_wire5(14);
+	sub_wire2(0, 15)    <= sub_wire5(15);
+	sub_wire2(0, 16)    <= sub_wire5(16);
+	sub_wire2(0, 17)    <= sub_wire5(17);
+	sub_wire2(0, 18)    <= sub_wire5(18);
+	sub_wire2(0, 19)    <= sub_wire5(19);
+	sub_wire2(0, 20)    <= sub_wire5(20);
+	sub_wire2(0, 21)    <= sub_wire5(21);
+	sub_wire2(0, 22)    <= sub_wire5(22);
+	sub_wire2(0, 23)    <= sub_wire5(23);
+	sub_wire2(0, 24)    <= sub_wire5(24);
+	sub_wire2(0, 25)    <= sub_wire5(25);
+	sub_wire2(0, 26)    <= sub_wire5(26);
+	sub_wire2(0, 27)    <= sub_wire5(27);
+	sub_wire2(0, 28)    <= sub_wire5(28);
+	sub_wire2(0, 29)    <= sub_wire5(29);
+	sub_wire2(0, 30)    <= sub_wire5(30);
+	sub_wire2(0, 31)    <= sub_wire5(31);
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_pipeline => 4,
+		lpm_size => 4,
+		lpm_type => "LPM_MUX",
+		lpm_width => 32,
+		lpm_widths => 2
+	)
+	PORT MAP (
+		sel => sel,
+		clock => clock,
+		data => sub_wire2,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data0x 0 0 32 0 INPUT NODEFVAL data0x[31..0]
+-- Retrieval info: USED_PORT: data1x 0 0 32 0 INPUT NODEFVAL data1x[31..0]
+-- Retrieval info: USED_PORT: data2x 0 0 32 0 INPUT NODEFVAL data2x[31..0]
+-- Retrieval info: USED_PORT: data3x 0 0 32 0 INPUT NODEFVAL data3x[31..0]
+-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
+-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
+-- Retrieval info: CONNECT: @data 1 3 32 0 data3x 0 0 32 0
+-- Retrieval info: CONNECT: @data 1 2 32 0 data2x 0 0 32 0
+-- Retrieval info: CONNECT: @data 1 1 32 0 data1x 0 0 32 0
+-- Retrieval info: CONNECT: @data 1 0 32 0 data0x 0 0 32 0
+-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_mux1.bsf b/FPGA_quartus_GE/Video/lpm_mux1.bsf
new file mode 100644
index 0000000..24ee953
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux1.bsf
@@ -0,0 +1,111 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 152 192)
+	(text "lpm_mux1" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 176 25 188)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data7x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data7x[15..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 72 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data6x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data6x[15..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 72 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "data5x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data5x[15..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 72 72)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "data4x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data4x[15..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 72 88)(line_width 3))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "data3x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[15..0]" (rect 4 91 66 104)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 72 104)(line_width 3))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "data2x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[15..0]" (rect 4 107 66 120)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 72 120)(line_width 3))
+	)
+	(port
+		(pt 0 136)
+		(input)
+		(text "data1x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[15..0]" (rect 4 123 66 136)(font "Arial" (font_size 8)))
+		(line (pt 0 136)(pt 72 136)(line_width 3))
+	)
+	(port
+		(pt 0 152)
+		(input)
+		(text "data0x[15..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[15..0]" (rect 4 139 66 152)(font "Arial" (font_size 8)))
+		(line (pt 0 152)(pt 72 152)(line_width 3))
+	)
+	(port
+		(pt 0 168)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 155 27 168)(font "Arial" (font_size 8)))
+		(line (pt 0 168)(pt 72 168)(line_width 1))
+	)
+	(port
+		(pt 80 192)
+		(input)
+		(text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[2..0]" (rect 84 179 121 192)(font "Arial" (font_size 8)))
+		(line (pt 80 192)(pt 80 180)(line_width 3))
+	)
+	(port
+		(pt 152 104)
+		(output)
+		(text "result[15..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[15..0]" (rect 92 91 147 104)(font "Arial" (font_size 8)))
+		(line (pt 152 104)(pt 88 104)(line_width 3))
+	)
+	(drawing
+		(line (pt 72 24)(pt 72 184)(line_width 1))
+		(line (pt 88 32)(pt 88 176)(line_width 1))
+		(line (pt 72 24)(pt 88 32)(line_width 1))
+		(line (pt 72 184)(pt 88 176)(line_width 1))
+		(line (pt 72 162)(pt 78 168)(line_width 1))
+		(line (pt 78 168)(pt 72 174)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_mux1.inc b/FPGA_quartus_GE/Video/lpm_mux1.inc
new file mode 100644
index 0000000..e2f94a4
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux1.inc
@@ -0,0 +1,32 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_mux1 
+(
+	clock,
+	data0x[15..0],
+	data1x[15..0],
+	data2x[15..0],
+	data3x[15..0],
+	data4x[15..0],
+	data5x[15..0],
+	data6x[15..0],
+	data7x[15..0],
+	sel[2..0]
+)
+
+RETURNS (
+	result[15..0]
+);
diff --git a/FPGA_quartus_GE/Video/lpm_mux1.qip b/FPGA_quartus_GE/Video/lpm_mux1.qip
new file mode 100644
index 0000000..8a445b2
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux1.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_mux1.vhd b/FPGA_quartus_GE/Video/lpm_mux1.vhd
new file mode 100644
index 0000000..a9ad991
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux1.vhd
@@ -0,0 +1,271 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_mux1.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_mux1 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data0x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+END lpm_mux1;
+
+
+ARCHITECTURE SYN OF lpm_mux1 IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (7 DOWNTO 0, 15 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (15 DOWNTO 0);
+
+BEGIN
+	sub_wire9    <= data0x(15 DOWNTO 0);
+	sub_wire8    <= data1x(15 DOWNTO 0);
+	sub_wire7    <= data2x(15 DOWNTO 0);
+	sub_wire6    <= data3x(15 DOWNTO 0);
+	sub_wire5    <= data4x(15 DOWNTO 0);
+	sub_wire4    <= data5x(15 DOWNTO 0);
+	sub_wire3    <= data6x(15 DOWNTO 0);
+	result    <= sub_wire0(15 DOWNTO 0);
+	sub_wire1    <= data7x(15 DOWNTO 0);
+	sub_wire2(7, 0)    <= sub_wire1(0);
+	sub_wire2(7, 1)    <= sub_wire1(1);
+	sub_wire2(7, 2)    <= sub_wire1(2);
+	sub_wire2(7, 3)    <= sub_wire1(3);
+	sub_wire2(7, 4)    <= sub_wire1(4);
+	sub_wire2(7, 5)    <= sub_wire1(5);
+	sub_wire2(7, 6)    <= sub_wire1(6);
+	sub_wire2(7, 7)    <= sub_wire1(7);
+	sub_wire2(7, 8)    <= sub_wire1(8);
+	sub_wire2(7, 9)    <= sub_wire1(9);
+	sub_wire2(7, 10)    <= sub_wire1(10);
+	sub_wire2(7, 11)    <= sub_wire1(11);
+	sub_wire2(7, 12)    <= sub_wire1(12);
+	sub_wire2(7, 13)    <= sub_wire1(13);
+	sub_wire2(7, 14)    <= sub_wire1(14);
+	sub_wire2(7, 15)    <= sub_wire1(15);
+	sub_wire2(6, 0)    <= sub_wire3(0);
+	sub_wire2(6, 1)    <= sub_wire3(1);
+	sub_wire2(6, 2)    <= sub_wire3(2);
+	sub_wire2(6, 3)    <= sub_wire3(3);
+	sub_wire2(6, 4)    <= sub_wire3(4);
+	sub_wire2(6, 5)    <= sub_wire3(5);
+	sub_wire2(6, 6)    <= sub_wire3(6);
+	sub_wire2(6, 7)    <= sub_wire3(7);
+	sub_wire2(6, 8)    <= sub_wire3(8);
+	sub_wire2(6, 9)    <= sub_wire3(9);
+	sub_wire2(6, 10)    <= sub_wire3(10);
+	sub_wire2(6, 11)    <= sub_wire3(11);
+	sub_wire2(6, 12)    <= sub_wire3(12);
+	sub_wire2(6, 13)    <= sub_wire3(13);
+	sub_wire2(6, 14)    <= sub_wire3(14);
+	sub_wire2(6, 15)    <= sub_wire3(15);
+	sub_wire2(5, 0)    <= sub_wire4(0);
+	sub_wire2(5, 1)    <= sub_wire4(1);
+	sub_wire2(5, 2)    <= sub_wire4(2);
+	sub_wire2(5, 3)    <= sub_wire4(3);
+	sub_wire2(5, 4)    <= sub_wire4(4);
+	sub_wire2(5, 5)    <= sub_wire4(5);
+	sub_wire2(5, 6)    <= sub_wire4(6);
+	sub_wire2(5, 7)    <= sub_wire4(7);
+	sub_wire2(5, 8)    <= sub_wire4(8);
+	sub_wire2(5, 9)    <= sub_wire4(9);
+	sub_wire2(5, 10)    <= sub_wire4(10);
+	sub_wire2(5, 11)    <= sub_wire4(11);
+	sub_wire2(5, 12)    <= sub_wire4(12);
+	sub_wire2(5, 13)    <= sub_wire4(13);
+	sub_wire2(5, 14)    <= sub_wire4(14);
+	sub_wire2(5, 15)    <= sub_wire4(15);
+	sub_wire2(4, 0)    <= sub_wire5(0);
+	sub_wire2(4, 1)    <= sub_wire5(1);
+	sub_wire2(4, 2)    <= sub_wire5(2);
+	sub_wire2(4, 3)    <= sub_wire5(3);
+	sub_wire2(4, 4)    <= sub_wire5(4);
+	sub_wire2(4, 5)    <= sub_wire5(5);
+	sub_wire2(4, 6)    <= sub_wire5(6);
+	sub_wire2(4, 7)    <= sub_wire5(7);
+	sub_wire2(4, 8)    <= sub_wire5(8);
+	sub_wire2(4, 9)    <= sub_wire5(9);
+	sub_wire2(4, 10)    <= sub_wire5(10);
+	sub_wire2(4, 11)    <= sub_wire5(11);
+	sub_wire2(4, 12)    <= sub_wire5(12);
+	sub_wire2(4, 13)    <= sub_wire5(13);
+	sub_wire2(4, 14)    <= sub_wire5(14);
+	sub_wire2(4, 15)    <= sub_wire5(15);
+	sub_wire2(3, 0)    <= sub_wire6(0);
+	sub_wire2(3, 1)    <= sub_wire6(1);
+	sub_wire2(3, 2)    <= sub_wire6(2);
+	sub_wire2(3, 3)    <= sub_wire6(3);
+	sub_wire2(3, 4)    <= sub_wire6(4);
+	sub_wire2(3, 5)    <= sub_wire6(5);
+	sub_wire2(3, 6)    <= sub_wire6(6);
+	sub_wire2(3, 7)    <= sub_wire6(7);
+	sub_wire2(3, 8)    <= sub_wire6(8);
+	sub_wire2(3, 9)    <= sub_wire6(9);
+	sub_wire2(3, 10)    <= sub_wire6(10);
+	sub_wire2(3, 11)    <= sub_wire6(11);
+	sub_wire2(3, 12)    <= sub_wire6(12);
+	sub_wire2(3, 13)    <= sub_wire6(13);
+	sub_wire2(3, 14)    <= sub_wire6(14);
+	sub_wire2(3, 15)    <= sub_wire6(15);
+	sub_wire2(2, 0)    <= sub_wire7(0);
+	sub_wire2(2, 1)    <= sub_wire7(1);
+	sub_wire2(2, 2)    <= sub_wire7(2);
+	sub_wire2(2, 3)    <= sub_wire7(3);
+	sub_wire2(2, 4)    <= sub_wire7(4);
+	sub_wire2(2, 5)    <= sub_wire7(5);
+	sub_wire2(2, 6)    <= sub_wire7(6);
+	sub_wire2(2, 7)    <= sub_wire7(7);
+	sub_wire2(2, 8)    <= sub_wire7(8);
+	sub_wire2(2, 9)    <= sub_wire7(9);
+	sub_wire2(2, 10)    <= sub_wire7(10);
+	sub_wire2(2, 11)    <= sub_wire7(11);
+	sub_wire2(2, 12)    <= sub_wire7(12);
+	sub_wire2(2, 13)    <= sub_wire7(13);
+	sub_wire2(2, 14)    <= sub_wire7(14);
+	sub_wire2(2, 15)    <= sub_wire7(15);
+	sub_wire2(1, 0)    <= sub_wire8(0);
+	sub_wire2(1, 1)    <= sub_wire8(1);
+	sub_wire2(1, 2)    <= sub_wire8(2);
+	sub_wire2(1, 3)    <= sub_wire8(3);
+	sub_wire2(1, 4)    <= sub_wire8(4);
+	sub_wire2(1, 5)    <= sub_wire8(5);
+	sub_wire2(1, 6)    <= sub_wire8(6);
+	sub_wire2(1, 7)    <= sub_wire8(7);
+	sub_wire2(1, 8)    <= sub_wire8(8);
+	sub_wire2(1, 9)    <= sub_wire8(9);
+	sub_wire2(1, 10)    <= sub_wire8(10);
+	sub_wire2(1, 11)    <= sub_wire8(11);
+	sub_wire2(1, 12)    <= sub_wire8(12);
+	sub_wire2(1, 13)    <= sub_wire8(13);
+	sub_wire2(1, 14)    <= sub_wire8(14);
+	sub_wire2(1, 15)    <= sub_wire8(15);
+	sub_wire2(0, 0)    <= sub_wire9(0);
+	sub_wire2(0, 1)    <= sub_wire9(1);
+	sub_wire2(0, 2)    <= sub_wire9(2);
+	sub_wire2(0, 3)    <= sub_wire9(3);
+	sub_wire2(0, 4)    <= sub_wire9(4);
+	sub_wire2(0, 5)    <= sub_wire9(5);
+	sub_wire2(0, 6)    <= sub_wire9(6);
+	sub_wire2(0, 7)    <= sub_wire9(7);
+	sub_wire2(0, 8)    <= sub_wire9(8);
+	sub_wire2(0, 9)    <= sub_wire9(9);
+	sub_wire2(0, 10)    <= sub_wire9(10);
+	sub_wire2(0, 11)    <= sub_wire9(11);
+	sub_wire2(0, 12)    <= sub_wire9(12);
+	sub_wire2(0, 13)    <= sub_wire9(13);
+	sub_wire2(0, 14)    <= sub_wire9(14);
+	sub_wire2(0, 15)    <= sub_wire9(15);
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_pipeline => 4,
+		lpm_size => 8,
+		lpm_type => "LPM_MUX",
+		lpm_width => 16,
+		lpm_widths => 3
+	)
+	PORT MAP (
+		sel => sel,
+		clock => clock,
+		data => sub_wire2,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL data0x[15..0]
+-- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL data1x[15..0]
+-- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL data2x[15..0]
+-- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL data3x[15..0]
+-- Retrieval info: USED_PORT: data4x 0 0 16 0 INPUT NODEFVAL data4x[15..0]
+-- Retrieval info: USED_PORT: data5x 0 0 16 0 INPUT NODEFVAL data5x[15..0]
+-- Retrieval info: USED_PORT: data6x 0 0 16 0 INPUT NODEFVAL data6x[15..0]
+-- Retrieval info: USED_PORT: data7x 0 0 16 0 INPUT NODEFVAL data7x[15..0]
+-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
+-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL sel[2..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 7 16 0 data7x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 6 16 0 data6x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 5 16 0 data5x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 4 16 0 data4x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0
+-- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0
+-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_mux2.bsf b/FPGA_quartus_GE/Video/lpm_mux2.bsf
new file mode 100644
index 0000000..b37c425
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux2.bsf
@@ -0,0 +1,167 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 320)
+	(text "lpm_mux2" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 304 25 316)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data15x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data15x[7..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 72 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data14x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data14x[7..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 72 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "data13x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data13x[7..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 72 72)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "data12x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data12x[7..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 72 88)(line_width 3))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "data11x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data11x[7..0]" (rect 4 91 66 104)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 72 104)(line_width 3))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "data10x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data10x[7..0]" (rect 4 107 66 120)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 72 120)(line_width 3))
+	)
+	(port
+		(pt 0 136)
+		(input)
+		(text "data9x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data9x[7..0]" (rect 4 123 60 136)(font "Arial" (font_size 8)))
+		(line (pt 0 136)(pt 72 136)(line_width 3))
+	)
+	(port
+		(pt 0 152)
+		(input)
+		(text "data8x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data8x[7..0]" (rect 4 139 60 152)(font "Arial" (font_size 8)))
+		(line (pt 0 152)(pt 72 152)(line_width 3))
+	)
+	(port
+		(pt 0 168)
+		(input)
+		(text "data7x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data7x[7..0]" (rect 4 155 60 168)(font "Arial" (font_size 8)))
+		(line (pt 0 168)(pt 72 168)(line_width 3))
+	)
+	(port
+		(pt 0 184)
+		(input)
+		(text "data6x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data6x[7..0]" (rect 4 171 60 184)(font "Arial" (font_size 8)))
+		(line (pt 0 184)(pt 72 184)(line_width 3))
+	)
+	(port
+		(pt 0 200)
+		(input)
+		(text "data5x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data5x[7..0]" (rect 4 187 60 200)(font "Arial" (font_size 8)))
+		(line (pt 0 200)(pt 72 200)(line_width 3))
+	)
+	(port
+		(pt 0 216)
+		(input)
+		(text "data4x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data4x[7..0]" (rect 4 203 60 216)(font "Arial" (font_size 8)))
+		(line (pt 0 216)(pt 72 216)(line_width 3))
+	)
+	(port
+		(pt 0 232)
+		(input)
+		(text "data3x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data3x[7..0]" (rect 4 219 60 232)(font "Arial" (font_size 8)))
+		(line (pt 0 232)(pt 72 232)(line_width 3))
+	)
+	(port
+		(pt 0 248)
+		(input)
+		(text "data2x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data2x[7..0]" (rect 4 235 60 248)(font "Arial" (font_size 8)))
+		(line (pt 0 248)(pt 72 248)(line_width 3))
+	)
+	(port
+		(pt 0 264)
+		(input)
+		(text "data1x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data1x[7..0]" (rect 4 251 60 264)(font "Arial" (font_size 8)))
+		(line (pt 0 264)(pt 72 264)(line_width 3))
+	)
+	(port
+		(pt 0 280)
+		(input)
+		(text "data0x[7..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data0x[7..0]" (rect 4 267 60 280)(font "Arial" (font_size 8)))
+		(line (pt 0 280)(pt 72 280)(line_width 3))
+	)
+	(port
+		(pt 0 296)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 283 27 296)(font "Arial" (font_size 8)))
+		(line (pt 0 296)(pt 72 296)(line_width 1))
+	)
+	(port
+		(pt 80 320)
+		(input)
+		(text "sel[3..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[3..0]" (rect 84 307 121 320)(font "Arial" (font_size 8)))
+		(line (pt 80 320)(pt 80 308)(line_width 3))
+	)
+	(port
+		(pt 144 168)
+		(output)
+		(text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[7..0]" (rect 90 155 139 168)(font "Arial" (font_size 8)))
+		(line (pt 144 168)(pt 88 168)(line_width 3))
+	)
+	(drawing
+		(line (pt 72 24)(pt 72 312)(line_width 1))
+		(line (pt 88 32)(pt 88 304)(line_width 1))
+		(line (pt 72 24)(pt 88 32)(line_width 1))
+		(line (pt 72 312)(pt 88 304)(line_width 1))
+		(line (pt 72 290)(pt 78 296)(line_width 1))
+		(line (pt 78 296)(pt 72 302)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_mux2.inc b/FPGA_quartus_GE/Video/lpm_mux2.inc
new file mode 100644
index 0000000..2334c7e
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux2.inc
@@ -0,0 +1,40 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_mux2 
+(
+	clock,
+	data0x[7..0],
+	data10x[7..0],
+	data11x[7..0],
+	data12x[7..0],
+	data13x[7..0],
+	data14x[7..0],
+	data15x[7..0],
+	data1x[7..0],
+	data2x[7..0],
+	data3x[7..0],
+	data4x[7..0],
+	data5x[7..0],
+	data6x[7..0],
+	data7x[7..0],
+	data8x[7..0],
+	data9x[7..0],
+	sel[3..0]
+)
+
+RETURNS (
+	result[7..0]
+);
diff --git a/FPGA_quartus_GE/Video/lpm_mux2.qip b/FPGA_quartus_GE/Video/lpm_mux2.qip
new file mode 100644
index 0000000..7b5db74
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux2.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux2.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_mux2.vhd b/FPGA_quartus_GE/Video/lpm_mux2.vhd
new file mode 100644
index 0000000..cfece2e
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux2.vhd
@@ -0,0 +1,311 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_mux2.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_mux2 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data0x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data10x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data11x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data12x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data13x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data14x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data15x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data8x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data9x		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END lpm_mux2;
+
+
+ARCHITECTURE SYN OF lpm_mux2 IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (15 DOWNTO 0, 7 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire10	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire11	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire12	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire13	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire14	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire15	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire16	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire17	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+BEGIN
+	sub_wire17    <= data0x(7 DOWNTO 0);
+	sub_wire16    <= data1x(7 DOWNTO 0);
+	sub_wire15    <= data2x(7 DOWNTO 0);
+	sub_wire14    <= data3x(7 DOWNTO 0);
+	sub_wire13    <= data4x(7 DOWNTO 0);
+	sub_wire12    <= data5x(7 DOWNTO 0);
+	sub_wire11    <= data6x(7 DOWNTO 0);
+	sub_wire10    <= data7x(7 DOWNTO 0);
+	sub_wire9    <= data8x(7 DOWNTO 0);
+	sub_wire8    <= data9x(7 DOWNTO 0);
+	sub_wire7    <= data10x(7 DOWNTO 0);
+	sub_wire6    <= data11x(7 DOWNTO 0);
+	sub_wire5    <= data12x(7 DOWNTO 0);
+	sub_wire4    <= data13x(7 DOWNTO 0);
+	sub_wire3    <= data14x(7 DOWNTO 0);
+	result    <= sub_wire0(7 DOWNTO 0);
+	sub_wire1    <= data15x(7 DOWNTO 0);
+	sub_wire2(15, 0)    <= sub_wire1(0);
+	sub_wire2(15, 1)    <= sub_wire1(1);
+	sub_wire2(15, 2)    <= sub_wire1(2);
+	sub_wire2(15, 3)    <= sub_wire1(3);
+	sub_wire2(15, 4)    <= sub_wire1(4);
+	sub_wire2(15, 5)    <= sub_wire1(5);
+	sub_wire2(15, 6)    <= sub_wire1(6);
+	sub_wire2(15, 7)    <= sub_wire1(7);
+	sub_wire2(14, 0)    <= sub_wire3(0);
+	sub_wire2(14, 1)    <= sub_wire3(1);
+	sub_wire2(14, 2)    <= sub_wire3(2);
+	sub_wire2(14, 3)    <= sub_wire3(3);
+	sub_wire2(14, 4)    <= sub_wire3(4);
+	sub_wire2(14, 5)    <= sub_wire3(5);
+	sub_wire2(14, 6)    <= sub_wire3(6);
+	sub_wire2(14, 7)    <= sub_wire3(7);
+	sub_wire2(13, 0)    <= sub_wire4(0);
+	sub_wire2(13, 1)    <= sub_wire4(1);
+	sub_wire2(13, 2)    <= sub_wire4(2);
+	sub_wire2(13, 3)    <= sub_wire4(3);
+	sub_wire2(13, 4)    <= sub_wire4(4);
+	sub_wire2(13, 5)    <= sub_wire4(5);
+	sub_wire2(13, 6)    <= sub_wire4(6);
+	sub_wire2(13, 7)    <= sub_wire4(7);
+	sub_wire2(12, 0)    <= sub_wire5(0);
+	sub_wire2(12, 1)    <= sub_wire5(1);
+	sub_wire2(12, 2)    <= sub_wire5(2);
+	sub_wire2(12, 3)    <= sub_wire5(3);
+	sub_wire2(12, 4)    <= sub_wire5(4);
+	sub_wire2(12, 5)    <= sub_wire5(5);
+	sub_wire2(12, 6)    <= sub_wire5(6);
+	sub_wire2(12, 7)    <= sub_wire5(7);
+	sub_wire2(11, 0)    <= sub_wire6(0);
+	sub_wire2(11, 1)    <= sub_wire6(1);
+	sub_wire2(11, 2)    <= sub_wire6(2);
+	sub_wire2(11, 3)    <= sub_wire6(3);
+	sub_wire2(11, 4)    <= sub_wire6(4);
+	sub_wire2(11, 5)    <= sub_wire6(5);
+	sub_wire2(11, 6)    <= sub_wire6(6);
+	sub_wire2(11, 7)    <= sub_wire6(7);
+	sub_wire2(10, 0)    <= sub_wire7(0);
+	sub_wire2(10, 1)    <= sub_wire7(1);
+	sub_wire2(10, 2)    <= sub_wire7(2);
+	sub_wire2(10, 3)    <= sub_wire7(3);
+	sub_wire2(10, 4)    <= sub_wire7(4);
+	sub_wire2(10, 5)    <= sub_wire7(5);
+	sub_wire2(10, 6)    <= sub_wire7(6);
+	sub_wire2(10, 7)    <= sub_wire7(7);
+	sub_wire2(9, 0)    <= sub_wire8(0);
+	sub_wire2(9, 1)    <= sub_wire8(1);
+	sub_wire2(9, 2)    <= sub_wire8(2);
+	sub_wire2(9, 3)    <= sub_wire8(3);
+	sub_wire2(9, 4)    <= sub_wire8(4);
+	sub_wire2(9, 5)    <= sub_wire8(5);
+	sub_wire2(9, 6)    <= sub_wire8(6);
+	sub_wire2(9, 7)    <= sub_wire8(7);
+	sub_wire2(8, 0)    <= sub_wire9(0);
+	sub_wire2(8, 1)    <= sub_wire9(1);
+	sub_wire2(8, 2)    <= sub_wire9(2);
+	sub_wire2(8, 3)    <= sub_wire9(3);
+	sub_wire2(8, 4)    <= sub_wire9(4);
+	sub_wire2(8, 5)    <= sub_wire9(5);
+	sub_wire2(8, 6)    <= sub_wire9(6);
+	sub_wire2(8, 7)    <= sub_wire9(7);
+	sub_wire2(7, 0)    <= sub_wire10(0);
+	sub_wire2(7, 1)    <= sub_wire10(1);
+	sub_wire2(7, 2)    <= sub_wire10(2);
+	sub_wire2(7, 3)    <= sub_wire10(3);
+	sub_wire2(7, 4)    <= sub_wire10(4);
+	sub_wire2(7, 5)    <= sub_wire10(5);
+	sub_wire2(7, 6)    <= sub_wire10(6);
+	sub_wire2(7, 7)    <= sub_wire10(7);
+	sub_wire2(6, 0)    <= sub_wire11(0);
+	sub_wire2(6, 1)    <= sub_wire11(1);
+	sub_wire2(6, 2)    <= sub_wire11(2);
+	sub_wire2(6, 3)    <= sub_wire11(3);
+	sub_wire2(6, 4)    <= sub_wire11(4);
+	sub_wire2(6, 5)    <= sub_wire11(5);
+	sub_wire2(6, 6)    <= sub_wire11(6);
+	sub_wire2(6, 7)    <= sub_wire11(7);
+	sub_wire2(5, 0)    <= sub_wire12(0);
+	sub_wire2(5, 1)    <= sub_wire12(1);
+	sub_wire2(5, 2)    <= sub_wire12(2);
+	sub_wire2(5, 3)    <= sub_wire12(3);
+	sub_wire2(5, 4)    <= sub_wire12(4);
+	sub_wire2(5, 5)    <= sub_wire12(5);
+	sub_wire2(5, 6)    <= sub_wire12(6);
+	sub_wire2(5, 7)    <= sub_wire12(7);
+	sub_wire2(4, 0)    <= sub_wire13(0);
+	sub_wire2(4, 1)    <= sub_wire13(1);
+	sub_wire2(4, 2)    <= sub_wire13(2);
+	sub_wire2(4, 3)    <= sub_wire13(3);
+	sub_wire2(4, 4)    <= sub_wire13(4);
+	sub_wire2(4, 5)    <= sub_wire13(5);
+	sub_wire2(4, 6)    <= sub_wire13(6);
+	sub_wire2(4, 7)    <= sub_wire13(7);
+	sub_wire2(3, 0)    <= sub_wire14(0);
+	sub_wire2(3, 1)    <= sub_wire14(1);
+	sub_wire2(3, 2)    <= sub_wire14(2);
+	sub_wire2(3, 3)    <= sub_wire14(3);
+	sub_wire2(3, 4)    <= sub_wire14(4);
+	sub_wire2(3, 5)    <= sub_wire14(5);
+	sub_wire2(3, 6)    <= sub_wire14(6);
+	sub_wire2(3, 7)    <= sub_wire14(7);
+	sub_wire2(2, 0)    <= sub_wire15(0);
+	sub_wire2(2, 1)    <= sub_wire15(1);
+	sub_wire2(2, 2)    <= sub_wire15(2);
+	sub_wire2(2, 3)    <= sub_wire15(3);
+	sub_wire2(2, 4)    <= sub_wire15(4);
+	sub_wire2(2, 5)    <= sub_wire15(5);
+	sub_wire2(2, 6)    <= sub_wire15(6);
+	sub_wire2(2, 7)    <= sub_wire15(7);
+	sub_wire2(1, 0)    <= sub_wire16(0);
+	sub_wire2(1, 1)    <= sub_wire16(1);
+	sub_wire2(1, 2)    <= sub_wire16(2);
+	sub_wire2(1, 3)    <= sub_wire16(3);
+	sub_wire2(1, 4)    <= sub_wire16(4);
+	sub_wire2(1, 5)    <= sub_wire16(5);
+	sub_wire2(1, 6)    <= sub_wire16(6);
+	sub_wire2(1, 7)    <= sub_wire16(7);
+	sub_wire2(0, 0)    <= sub_wire17(0);
+	sub_wire2(0, 1)    <= sub_wire17(1);
+	sub_wire2(0, 2)    <= sub_wire17(2);
+	sub_wire2(0, 3)    <= sub_wire17(3);
+	sub_wire2(0, 4)    <= sub_wire17(4);
+	sub_wire2(0, 5)    <= sub_wire17(5);
+	sub_wire2(0, 6)    <= sub_wire17(6);
+	sub_wire2(0, 7)    <= sub_wire17(7);
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_pipeline => 2,
+		lpm_size => 16,
+		lpm_type => "LPM_MUX",
+		lpm_width => 8,
+		lpm_widths => 4
+	)
+	PORT MAP (
+		sel => sel,
+		clock => clock,
+		data => sub_wire2,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data0x 0 0 8 0 INPUT NODEFVAL data0x[7..0]
+-- Retrieval info: USED_PORT: data10x 0 0 8 0 INPUT NODEFVAL data10x[7..0]
+-- Retrieval info: USED_PORT: data11x 0 0 8 0 INPUT NODEFVAL data11x[7..0]
+-- Retrieval info: USED_PORT: data12x 0 0 8 0 INPUT NODEFVAL data12x[7..0]
+-- Retrieval info: USED_PORT: data13x 0 0 8 0 INPUT NODEFVAL data13x[7..0]
+-- Retrieval info: USED_PORT: data14x 0 0 8 0 INPUT NODEFVAL data14x[7..0]
+-- Retrieval info: USED_PORT: data15x 0 0 8 0 INPUT NODEFVAL data15x[7..0]
+-- Retrieval info: USED_PORT: data1x 0 0 8 0 INPUT NODEFVAL data1x[7..0]
+-- Retrieval info: USED_PORT: data2x 0 0 8 0 INPUT NODEFVAL data2x[7..0]
+-- Retrieval info: USED_PORT: data3x 0 0 8 0 INPUT NODEFVAL data3x[7..0]
+-- Retrieval info: USED_PORT: data4x 0 0 8 0 INPUT NODEFVAL data4x[7..0]
+-- Retrieval info: USED_PORT: data5x 0 0 8 0 INPUT NODEFVAL data5x[7..0]
+-- Retrieval info: USED_PORT: data6x 0 0 8 0 INPUT NODEFVAL data6x[7..0]
+-- Retrieval info: USED_PORT: data7x 0 0 8 0 INPUT NODEFVAL data7x[7..0]
+-- Retrieval info: USED_PORT: data8x 0 0 8 0 INPUT NODEFVAL data8x[7..0]
+-- Retrieval info: USED_PORT: data9x 0 0 8 0 INPUT NODEFVAL data9x[7..0]
+-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
+-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL sel[3..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 15 8 0 data15x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 14 8 0 data14x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 13 8 0 data13x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 12 8 0 data12x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 11 8 0 data11x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 10 8 0 data10x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 9 8 0 data9x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 8 8 0 data8x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 7 8 0 data7x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 6 8 0 data6x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 5 8 0 data5x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 4 8 0 data4x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 3 8 0 data3x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 2 8 0 data2x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 1 8 0 data1x 0 0 8 0
+-- Retrieval info: CONNECT: @data 1 0 8 0 data0x 0 0 8 0
+-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux2_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_mux3.bsf b/FPGA_quartus_GE/Video/lpm_mux3.bsf
new file mode 100644
index 0000000..c389543
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux3.bsf
@@ -0,0 +1,60 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 80 80)
+	(text "lpm_mux3" (rect 10 2 80 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data1" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "data1" (rect 4 27 31 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 32 40)(line_width 1))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "data0" (rect 4 43 31 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 32 56)(line_width 1))
+	)
+	(port
+		(pt 40 80)
+		(input)
+		(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "sel" (rect 44 67 57 80)(font "Arial" (font_size 8)))
+		(line (pt 40 80)(pt 40 68)(line_width 1))
+	)
+	(port
+		(pt 80 48)
+		(output)
+		(text "result" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "result" (rect 50 35 75 48)(font "Arial" (font_size 8)))
+		(line (pt 80 48)(pt 48 48)(line_width 1))
+	)
+	(drawing
+		(line (pt 32 24)(pt 32 72)(line_width 1))
+		(line (pt 48 32)(pt 48 64)(line_width 1))
+		(line (pt 32 24)(pt 48 32)(line_width 1))
+		(line (pt 32 72)(pt 48 64)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_mux3.qip b/FPGA_quartus_GE/Video/lpm_mux3.qip
new file mode 100644
index 0000000..ca1e672
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux3.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux3.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux3.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_mux3.vhd b/FPGA_quartus_GE/Video/lpm_mux3.vhd
new file mode 100644
index 0000000..b975686
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux3.vhd
@@ -0,0 +1,115 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_mux3.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_mux3 IS
+	PORT
+	(
+		data0		: IN STD_LOGIC ;
+		data1		: IN STD_LOGIC ;
+		sel		: IN STD_LOGIC ;
+		result		: OUT STD_LOGIC 
+	);
+END lpm_mux3;
+
+
+ARCHITECTURE SYN OF lpm_mux3 IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC ;
+
+BEGIN
+	sub_wire6    <= data0;
+	sub_wire1    <= sub_wire0(0);
+	result    <= sub_wire1;
+	sub_wire2    <= sel;
+	sub_wire3(0)    <= sub_wire2;
+	sub_wire4    <= data1;
+	sub_wire5(1, 0)    <= sub_wire4;
+	sub_wire5(0, 0)    <= sub_wire6;
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_size => 2,
+		lpm_type => "LPM_MUX",
+		lpm_width => 1,
+		lpm_widths => 1
+	)
+	PORT MAP (
+		sel => sub_wire3,
+		data => sub_wire5,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
+-- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL data0
+-- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL data1
+-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result
+-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel
+-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
+-- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0
+-- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0
+-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux3_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_mux4.bsf b/FPGA_quartus_GE/Video/lpm_mux4.bsf
new file mode 100644
index 0000000..a1c9ca0
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux4.bsf
@@ -0,0 +1,60 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 136 80)
+	(text "lpm_mux4" (rect 42 2 112 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data1x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data1x[6..0]" (rect 4 27 60 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 64 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data0x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "data0x[6..0]" (rect 4 43 60 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 64 56)(line_width 3))
+	)
+	(port
+		(pt 72 80)
+		(input)
+		(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "sel" (rect 76 67 89 80)(font "Arial" (font_size 8)))
+		(line (pt 72 80)(pt 72 68)(line_width 1))
+	)
+	(port
+		(pt 136 48)
+		(output)
+		(text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "result[6..0]" (rect 82 35 131 48)(font "Arial" (font_size 8)))
+		(line (pt 136 48)(pt 80 48)(line_width 3))
+	)
+	(drawing
+		(line (pt 64 24)(pt 64 72)(line_width 1))
+		(line (pt 80 32)(pt 80 64)(line_width 1))
+		(line (pt 64 24)(pt 80 32)(line_width 1))
+		(line (pt 64 72)(pt 80 64)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_mux4.qip b/FPGA_quartus_GE/Video/lpm_mux4.qip
new file mode 100644
index 0000000..7712e39
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux4.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux4.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux4.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_mux4.vhd b/FPGA_quartus_GE/Video/lpm_mux4.vhd
new file mode 100644
index 0000000..854a491
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux4.vhd
@@ -0,0 +1,125 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_mux4.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_mux4 IS
+	PORT
+	(
+		data0x		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+		sel		: IN STD_LOGIC ;
+		result		: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
+	);
+END lpm_mux4;
+
+
+ARCHITECTURE SYN OF lpm_mux4 IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (6 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (6 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_2D (1 DOWNTO 0, 6 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (6 DOWNTO 0);
+
+BEGIN
+	sub_wire5    <= data0x(6 DOWNTO 0);
+	result    <= sub_wire0(6 DOWNTO 0);
+	sub_wire1    <= sel;
+	sub_wire2(0)    <= sub_wire1;
+	sub_wire3    <= data1x(6 DOWNTO 0);
+	sub_wire4(1, 0)    <= sub_wire3(0);
+	sub_wire4(1, 1)    <= sub_wire3(1);
+	sub_wire4(1, 2)    <= sub_wire3(2);
+	sub_wire4(1, 3)    <= sub_wire3(3);
+	sub_wire4(1, 4)    <= sub_wire3(4);
+	sub_wire4(1, 5)    <= sub_wire3(5);
+	sub_wire4(1, 6)    <= sub_wire3(6);
+	sub_wire4(0, 0)    <= sub_wire5(0);
+	sub_wire4(0, 1)    <= sub_wire5(1);
+	sub_wire4(0, 2)    <= sub_wire5(2);
+	sub_wire4(0, 3)    <= sub_wire5(3);
+	sub_wire4(0, 4)    <= sub_wire5(4);
+	sub_wire4(0, 5)    <= sub_wire5(5);
+	sub_wire4(0, 6)    <= sub_wire5(6);
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_size => 2,
+		lpm_type => "LPM_MUX",
+		lpm_width => 7,
+		lpm_widths => 1
+	)
+	PORT MAP (
+		sel => sub_wire2,
+		data => sub_wire4,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
+-- Retrieval info: USED_PORT: data0x 0 0 7 0 INPUT NODEFVAL data0x[6..0]
+-- Retrieval info: USED_PORT: data1x 0 0 7 0 INPUT NODEFVAL data1x[6..0]
+-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL result[6..0]
+-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel
+-- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0
+-- Retrieval info: CONNECT: @data 1 1 7 0 data1x 0 0 7 0
+-- Retrieval info: CONNECT: @data 1 0 7 0 data0x 0 0 7 0
+-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux4_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_mux5.bsf b/FPGA_quartus_GE/Video/lpm_mux5.bsf
new file mode 100644
index 0000000..e63ce50
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux5.bsf
@@ -0,0 +1,74 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 152 112)
+	(text "lpm_mux5" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 96 25 108)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data3x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[63..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 72 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data2x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[63..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 72 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "data1x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[63..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 72 72)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "data0x[63..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[63..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 72 88)(line_width 3))
+	)
+	(port
+		(pt 80 112)
+		(input)
+		(text "sel[1..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[1..0]" (rect 84 99 121 112)(font "Arial" (font_size 8)))
+		(line (pt 80 112)(pt 80 100)(line_width 3))
+	)
+	(port
+		(pt 152 64)
+		(output)
+		(text "result[63..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[63..0]" (rect 92 51 147 64)(font "Arial" (font_size 8)))
+		(line (pt 152 64)(pt 88 64)(line_width 3))
+	)
+	(drawing
+		(line (pt 72 24)(pt 72 104)(line_width 1))
+		(line (pt 88 32)(pt 88 96)(line_width 1))
+		(line (pt 72 24)(pt 88 32)(line_width 1))
+		(line (pt 72 104)(pt 88 96)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_mux5.inc b/FPGA_quartus_GE/Video/lpm_mux5.inc
new file mode 100644
index 0000000..a063f55
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux5.inc
@@ -0,0 +1,27 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_mux5 
+(
+	data0x[63..0],
+	data1x[63..0],
+	data2x[63..0],
+	data3x[63..0],
+	sel[1..0]
+)
+
+RETURNS (
+	result[63..0]
+);
diff --git a/FPGA_quartus_GE/Video/lpm_mux5.qip b/FPGA_quartus_GE/Video/lpm_mux5.qip
new file mode 100644
index 0000000..08b2e74
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux5.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux5.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux5.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_mux5.vhd b/FPGA_quartus_GE/Video/lpm_mux5.vhd
new file mode 100644
index 0000000..1d35347
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux5.vhd
@@ -0,0 +1,373 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_mux5.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_mux5 IS
+	PORT
+	(
+		data0x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
+	);
+END lpm_mux5;
+
+
+ARCHITECTURE SYN OF lpm_mux5 IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (63 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (63 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (3 DOWNTO 0, 63 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (63 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (63 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (63 DOWNTO 0);
+
+BEGIN
+	sub_wire5    <= data0x(63 DOWNTO 0);
+	sub_wire4    <= data1x(63 DOWNTO 0);
+	sub_wire3    <= data2x(63 DOWNTO 0);
+	result    <= sub_wire0(63 DOWNTO 0);
+	sub_wire1    <= data3x(63 DOWNTO 0);
+	sub_wire2(3, 0)    <= sub_wire1(0);
+	sub_wire2(3, 1)    <= sub_wire1(1);
+	sub_wire2(3, 2)    <= sub_wire1(2);
+	sub_wire2(3, 3)    <= sub_wire1(3);
+	sub_wire2(3, 4)    <= sub_wire1(4);
+	sub_wire2(3, 5)    <= sub_wire1(5);
+	sub_wire2(3, 6)    <= sub_wire1(6);
+	sub_wire2(3, 7)    <= sub_wire1(7);
+	sub_wire2(3, 8)    <= sub_wire1(8);
+	sub_wire2(3, 9)    <= sub_wire1(9);
+	sub_wire2(3, 10)    <= sub_wire1(10);
+	sub_wire2(3, 11)    <= sub_wire1(11);
+	sub_wire2(3, 12)    <= sub_wire1(12);
+	sub_wire2(3, 13)    <= sub_wire1(13);
+	sub_wire2(3, 14)    <= sub_wire1(14);
+	sub_wire2(3, 15)    <= sub_wire1(15);
+	sub_wire2(3, 16)    <= sub_wire1(16);
+	sub_wire2(3, 17)    <= sub_wire1(17);
+	sub_wire2(3, 18)    <= sub_wire1(18);
+	sub_wire2(3, 19)    <= sub_wire1(19);
+	sub_wire2(3, 20)    <= sub_wire1(20);
+	sub_wire2(3, 21)    <= sub_wire1(21);
+	sub_wire2(3, 22)    <= sub_wire1(22);
+	sub_wire2(3, 23)    <= sub_wire1(23);
+	sub_wire2(3, 24)    <= sub_wire1(24);
+	sub_wire2(3, 25)    <= sub_wire1(25);
+	sub_wire2(3, 26)    <= sub_wire1(26);
+	sub_wire2(3, 27)    <= sub_wire1(27);
+	sub_wire2(3, 28)    <= sub_wire1(28);
+	sub_wire2(3, 29)    <= sub_wire1(29);
+	sub_wire2(3, 30)    <= sub_wire1(30);
+	sub_wire2(3, 31)    <= sub_wire1(31);
+	sub_wire2(3, 32)    <= sub_wire1(32);
+	sub_wire2(3, 33)    <= sub_wire1(33);
+	sub_wire2(3, 34)    <= sub_wire1(34);
+	sub_wire2(3, 35)    <= sub_wire1(35);
+	sub_wire2(3, 36)    <= sub_wire1(36);
+	sub_wire2(3, 37)    <= sub_wire1(37);
+	sub_wire2(3, 38)    <= sub_wire1(38);
+	sub_wire2(3, 39)    <= sub_wire1(39);
+	sub_wire2(3, 40)    <= sub_wire1(40);
+	sub_wire2(3, 41)    <= sub_wire1(41);
+	sub_wire2(3, 42)    <= sub_wire1(42);
+	sub_wire2(3, 43)    <= sub_wire1(43);
+	sub_wire2(3, 44)    <= sub_wire1(44);
+	sub_wire2(3, 45)    <= sub_wire1(45);
+	sub_wire2(3, 46)    <= sub_wire1(46);
+	sub_wire2(3, 47)    <= sub_wire1(47);
+	sub_wire2(3, 48)    <= sub_wire1(48);
+	sub_wire2(3, 49)    <= sub_wire1(49);
+	sub_wire2(3, 50)    <= sub_wire1(50);
+	sub_wire2(3, 51)    <= sub_wire1(51);
+	sub_wire2(3, 52)    <= sub_wire1(52);
+	sub_wire2(3, 53)    <= sub_wire1(53);
+	sub_wire2(3, 54)    <= sub_wire1(54);
+	sub_wire2(3, 55)    <= sub_wire1(55);
+	sub_wire2(3, 56)    <= sub_wire1(56);
+	sub_wire2(3, 57)    <= sub_wire1(57);
+	sub_wire2(3, 58)    <= sub_wire1(58);
+	sub_wire2(3, 59)    <= sub_wire1(59);
+	sub_wire2(3, 60)    <= sub_wire1(60);
+	sub_wire2(3, 61)    <= sub_wire1(61);
+	sub_wire2(3, 62)    <= sub_wire1(62);
+	sub_wire2(3, 63)    <= sub_wire1(63);
+	sub_wire2(2, 0)    <= sub_wire3(0);
+	sub_wire2(2, 1)    <= sub_wire3(1);
+	sub_wire2(2, 2)    <= sub_wire3(2);
+	sub_wire2(2, 3)    <= sub_wire3(3);
+	sub_wire2(2, 4)    <= sub_wire3(4);
+	sub_wire2(2, 5)    <= sub_wire3(5);
+	sub_wire2(2, 6)    <= sub_wire3(6);
+	sub_wire2(2, 7)    <= sub_wire3(7);
+	sub_wire2(2, 8)    <= sub_wire3(8);
+	sub_wire2(2, 9)    <= sub_wire3(9);
+	sub_wire2(2, 10)    <= sub_wire3(10);
+	sub_wire2(2, 11)    <= sub_wire3(11);
+	sub_wire2(2, 12)    <= sub_wire3(12);
+	sub_wire2(2, 13)    <= sub_wire3(13);
+	sub_wire2(2, 14)    <= sub_wire3(14);
+	sub_wire2(2, 15)    <= sub_wire3(15);
+	sub_wire2(2, 16)    <= sub_wire3(16);
+	sub_wire2(2, 17)    <= sub_wire3(17);
+	sub_wire2(2, 18)    <= sub_wire3(18);
+	sub_wire2(2, 19)    <= sub_wire3(19);
+	sub_wire2(2, 20)    <= sub_wire3(20);
+	sub_wire2(2, 21)    <= sub_wire3(21);
+	sub_wire2(2, 22)    <= sub_wire3(22);
+	sub_wire2(2, 23)    <= sub_wire3(23);
+	sub_wire2(2, 24)    <= sub_wire3(24);
+	sub_wire2(2, 25)    <= sub_wire3(25);
+	sub_wire2(2, 26)    <= sub_wire3(26);
+	sub_wire2(2, 27)    <= sub_wire3(27);
+	sub_wire2(2, 28)    <= sub_wire3(28);
+	sub_wire2(2, 29)    <= sub_wire3(29);
+	sub_wire2(2, 30)    <= sub_wire3(30);
+	sub_wire2(2, 31)    <= sub_wire3(31);
+	sub_wire2(2, 32)    <= sub_wire3(32);
+	sub_wire2(2, 33)    <= sub_wire3(33);
+	sub_wire2(2, 34)    <= sub_wire3(34);
+	sub_wire2(2, 35)    <= sub_wire3(35);
+	sub_wire2(2, 36)    <= sub_wire3(36);
+	sub_wire2(2, 37)    <= sub_wire3(37);
+	sub_wire2(2, 38)    <= sub_wire3(38);
+	sub_wire2(2, 39)    <= sub_wire3(39);
+	sub_wire2(2, 40)    <= sub_wire3(40);
+	sub_wire2(2, 41)    <= sub_wire3(41);
+	sub_wire2(2, 42)    <= sub_wire3(42);
+	sub_wire2(2, 43)    <= sub_wire3(43);
+	sub_wire2(2, 44)    <= sub_wire3(44);
+	sub_wire2(2, 45)    <= sub_wire3(45);
+	sub_wire2(2, 46)    <= sub_wire3(46);
+	sub_wire2(2, 47)    <= sub_wire3(47);
+	sub_wire2(2, 48)    <= sub_wire3(48);
+	sub_wire2(2, 49)    <= sub_wire3(49);
+	sub_wire2(2, 50)    <= sub_wire3(50);
+	sub_wire2(2, 51)    <= sub_wire3(51);
+	sub_wire2(2, 52)    <= sub_wire3(52);
+	sub_wire2(2, 53)    <= sub_wire3(53);
+	sub_wire2(2, 54)    <= sub_wire3(54);
+	sub_wire2(2, 55)    <= sub_wire3(55);
+	sub_wire2(2, 56)    <= sub_wire3(56);
+	sub_wire2(2, 57)    <= sub_wire3(57);
+	sub_wire2(2, 58)    <= sub_wire3(58);
+	sub_wire2(2, 59)    <= sub_wire3(59);
+	sub_wire2(2, 60)    <= sub_wire3(60);
+	sub_wire2(2, 61)    <= sub_wire3(61);
+	sub_wire2(2, 62)    <= sub_wire3(62);
+	sub_wire2(2, 63)    <= sub_wire3(63);
+	sub_wire2(1, 0)    <= sub_wire4(0);
+	sub_wire2(1, 1)    <= sub_wire4(1);
+	sub_wire2(1, 2)    <= sub_wire4(2);
+	sub_wire2(1, 3)    <= sub_wire4(3);
+	sub_wire2(1, 4)    <= sub_wire4(4);
+	sub_wire2(1, 5)    <= sub_wire4(5);
+	sub_wire2(1, 6)    <= sub_wire4(6);
+	sub_wire2(1, 7)    <= sub_wire4(7);
+	sub_wire2(1, 8)    <= sub_wire4(8);
+	sub_wire2(1, 9)    <= sub_wire4(9);
+	sub_wire2(1, 10)    <= sub_wire4(10);
+	sub_wire2(1, 11)    <= sub_wire4(11);
+	sub_wire2(1, 12)    <= sub_wire4(12);
+	sub_wire2(1, 13)    <= sub_wire4(13);
+	sub_wire2(1, 14)    <= sub_wire4(14);
+	sub_wire2(1, 15)    <= sub_wire4(15);
+	sub_wire2(1, 16)    <= sub_wire4(16);
+	sub_wire2(1, 17)    <= sub_wire4(17);
+	sub_wire2(1, 18)    <= sub_wire4(18);
+	sub_wire2(1, 19)    <= sub_wire4(19);
+	sub_wire2(1, 20)    <= sub_wire4(20);
+	sub_wire2(1, 21)    <= sub_wire4(21);
+	sub_wire2(1, 22)    <= sub_wire4(22);
+	sub_wire2(1, 23)    <= sub_wire4(23);
+	sub_wire2(1, 24)    <= sub_wire4(24);
+	sub_wire2(1, 25)    <= sub_wire4(25);
+	sub_wire2(1, 26)    <= sub_wire4(26);
+	sub_wire2(1, 27)    <= sub_wire4(27);
+	sub_wire2(1, 28)    <= sub_wire4(28);
+	sub_wire2(1, 29)    <= sub_wire4(29);
+	sub_wire2(1, 30)    <= sub_wire4(30);
+	sub_wire2(1, 31)    <= sub_wire4(31);
+	sub_wire2(1, 32)    <= sub_wire4(32);
+	sub_wire2(1, 33)    <= sub_wire4(33);
+	sub_wire2(1, 34)    <= sub_wire4(34);
+	sub_wire2(1, 35)    <= sub_wire4(35);
+	sub_wire2(1, 36)    <= sub_wire4(36);
+	sub_wire2(1, 37)    <= sub_wire4(37);
+	sub_wire2(1, 38)    <= sub_wire4(38);
+	sub_wire2(1, 39)    <= sub_wire4(39);
+	sub_wire2(1, 40)    <= sub_wire4(40);
+	sub_wire2(1, 41)    <= sub_wire4(41);
+	sub_wire2(1, 42)    <= sub_wire4(42);
+	sub_wire2(1, 43)    <= sub_wire4(43);
+	sub_wire2(1, 44)    <= sub_wire4(44);
+	sub_wire2(1, 45)    <= sub_wire4(45);
+	sub_wire2(1, 46)    <= sub_wire4(46);
+	sub_wire2(1, 47)    <= sub_wire4(47);
+	sub_wire2(1, 48)    <= sub_wire4(48);
+	sub_wire2(1, 49)    <= sub_wire4(49);
+	sub_wire2(1, 50)    <= sub_wire4(50);
+	sub_wire2(1, 51)    <= sub_wire4(51);
+	sub_wire2(1, 52)    <= sub_wire4(52);
+	sub_wire2(1, 53)    <= sub_wire4(53);
+	sub_wire2(1, 54)    <= sub_wire4(54);
+	sub_wire2(1, 55)    <= sub_wire4(55);
+	sub_wire2(1, 56)    <= sub_wire4(56);
+	sub_wire2(1, 57)    <= sub_wire4(57);
+	sub_wire2(1, 58)    <= sub_wire4(58);
+	sub_wire2(1, 59)    <= sub_wire4(59);
+	sub_wire2(1, 60)    <= sub_wire4(60);
+	sub_wire2(1, 61)    <= sub_wire4(61);
+	sub_wire2(1, 62)    <= sub_wire4(62);
+	sub_wire2(1, 63)    <= sub_wire4(63);
+	sub_wire2(0, 0)    <= sub_wire5(0);
+	sub_wire2(0, 1)    <= sub_wire5(1);
+	sub_wire2(0, 2)    <= sub_wire5(2);
+	sub_wire2(0, 3)    <= sub_wire5(3);
+	sub_wire2(0, 4)    <= sub_wire5(4);
+	sub_wire2(0, 5)    <= sub_wire5(5);
+	sub_wire2(0, 6)    <= sub_wire5(6);
+	sub_wire2(0, 7)    <= sub_wire5(7);
+	sub_wire2(0, 8)    <= sub_wire5(8);
+	sub_wire2(0, 9)    <= sub_wire5(9);
+	sub_wire2(0, 10)    <= sub_wire5(10);
+	sub_wire2(0, 11)    <= sub_wire5(11);
+	sub_wire2(0, 12)    <= sub_wire5(12);
+	sub_wire2(0, 13)    <= sub_wire5(13);
+	sub_wire2(0, 14)    <= sub_wire5(14);
+	sub_wire2(0, 15)    <= sub_wire5(15);
+	sub_wire2(0, 16)    <= sub_wire5(16);
+	sub_wire2(0, 17)    <= sub_wire5(17);
+	sub_wire2(0, 18)    <= sub_wire5(18);
+	sub_wire2(0, 19)    <= sub_wire5(19);
+	sub_wire2(0, 20)    <= sub_wire5(20);
+	sub_wire2(0, 21)    <= sub_wire5(21);
+	sub_wire2(0, 22)    <= sub_wire5(22);
+	sub_wire2(0, 23)    <= sub_wire5(23);
+	sub_wire2(0, 24)    <= sub_wire5(24);
+	sub_wire2(0, 25)    <= sub_wire5(25);
+	sub_wire2(0, 26)    <= sub_wire5(26);
+	sub_wire2(0, 27)    <= sub_wire5(27);
+	sub_wire2(0, 28)    <= sub_wire5(28);
+	sub_wire2(0, 29)    <= sub_wire5(29);
+	sub_wire2(0, 30)    <= sub_wire5(30);
+	sub_wire2(0, 31)    <= sub_wire5(31);
+	sub_wire2(0, 32)    <= sub_wire5(32);
+	sub_wire2(0, 33)    <= sub_wire5(33);
+	sub_wire2(0, 34)    <= sub_wire5(34);
+	sub_wire2(0, 35)    <= sub_wire5(35);
+	sub_wire2(0, 36)    <= sub_wire5(36);
+	sub_wire2(0, 37)    <= sub_wire5(37);
+	sub_wire2(0, 38)    <= sub_wire5(38);
+	sub_wire2(0, 39)    <= sub_wire5(39);
+	sub_wire2(0, 40)    <= sub_wire5(40);
+	sub_wire2(0, 41)    <= sub_wire5(41);
+	sub_wire2(0, 42)    <= sub_wire5(42);
+	sub_wire2(0, 43)    <= sub_wire5(43);
+	sub_wire2(0, 44)    <= sub_wire5(44);
+	sub_wire2(0, 45)    <= sub_wire5(45);
+	sub_wire2(0, 46)    <= sub_wire5(46);
+	sub_wire2(0, 47)    <= sub_wire5(47);
+	sub_wire2(0, 48)    <= sub_wire5(48);
+	sub_wire2(0, 49)    <= sub_wire5(49);
+	sub_wire2(0, 50)    <= sub_wire5(50);
+	sub_wire2(0, 51)    <= sub_wire5(51);
+	sub_wire2(0, 52)    <= sub_wire5(52);
+	sub_wire2(0, 53)    <= sub_wire5(53);
+	sub_wire2(0, 54)    <= sub_wire5(54);
+	sub_wire2(0, 55)    <= sub_wire5(55);
+	sub_wire2(0, 56)    <= sub_wire5(56);
+	sub_wire2(0, 57)    <= sub_wire5(57);
+	sub_wire2(0, 58)    <= sub_wire5(58);
+	sub_wire2(0, 59)    <= sub_wire5(59);
+	sub_wire2(0, 60)    <= sub_wire5(60);
+	sub_wire2(0, 61)    <= sub_wire5(61);
+	sub_wire2(0, 62)    <= sub_wire5(62);
+	sub_wire2(0, 63)    <= sub_wire5(63);
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_size => 4,
+		lpm_type => "LPM_MUX",
+		lpm_width => 64,
+		lpm_widths => 2
+	)
+	PORT MAP (
+		sel => sel,
+		data => sub_wire2,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
+-- Retrieval info: USED_PORT: data0x 0 0 64 0 INPUT NODEFVAL data0x[63..0]
+-- Retrieval info: USED_PORT: data1x 0 0 64 0 INPUT NODEFVAL data1x[63..0]
+-- Retrieval info: USED_PORT: data2x 0 0 64 0 INPUT NODEFVAL data2x[63..0]
+-- Retrieval info: USED_PORT: data3x 0 0 64 0 INPUT NODEFVAL data3x[63..0]
+-- Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL result[63..0]
+-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL sel[1..0]
+-- Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
+-- Retrieval info: CONNECT: @data 1 3 64 0 data3x 0 0 64 0
+-- Retrieval info: CONNECT: @data 1 2 64 0 data2x 0 0 64 0
+-- Retrieval info: CONNECT: @data 1 1 64 0 data1x 0 0 64 0
+-- Retrieval info: CONNECT: @data 1 0 64 0 data0x 0 0 64 0
+-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux5_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_mux6.bsf b/FPGA_quartus_GE/Video/lpm_mux6.bsf
new file mode 100644
index 0000000..2196842
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux6.bsf
@@ -0,0 +1,111 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 152 192)
+	(text "lpm_mux6" (rect 50 2 120 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 176 25 188)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data7x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data7x[23..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 72 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data6x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data6x[23..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 72 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "data5x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data5x[23..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 72 72)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "data4x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data4x[23..0]" (rect 4 75 66 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 72 88)(line_width 3))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "data3x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data3x[23..0]" (rect 4 91 66 104)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 72 104)(line_width 3))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "data2x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data2x[23..0]" (rect 4 107 66 120)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 72 120)(line_width 3))
+	)
+	(port
+		(pt 0 136)
+		(input)
+		(text "data1x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data1x[23..0]" (rect 4 123 66 136)(font "Arial" (font_size 8)))
+		(line (pt 0 136)(pt 72 136)(line_width 3))
+	)
+	(port
+		(pt 0 152)
+		(input)
+		(text "data0x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "data0x[23..0]" (rect 4 139 66 152)(font "Arial" (font_size 8)))
+		(line (pt 0 152)(pt 72 152)(line_width 3))
+	)
+	(port
+		(pt 0 168)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 155 27 168)(font "Arial" (font_size 8)))
+		(line (pt 0 168)(pt 72 168)(line_width 1))
+	)
+	(port
+		(pt 80 192)
+		(input)
+		(text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[2..0]" (rect 84 179 121 192)(font "Arial" (font_size 8)))
+		(line (pt 80 192)(pt 80 180)(line_width 3))
+	)
+	(port
+		(pt 152 104)
+		(output)
+		(text "result[23..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[23..0]" (rect 92 91 147 104)(font "Arial" (font_size 8)))
+		(line (pt 152 104)(pt 88 104)(line_width 3))
+	)
+	(drawing
+		(line (pt 72 24)(pt 72 184)(line_width 1))
+		(line (pt 88 32)(pt 88 176)(line_width 1))
+		(line (pt 72 24)(pt 88 32)(line_width 1))
+		(line (pt 72 184)(pt 88 176)(line_width 1))
+		(line (pt 72 162)(pt 78 168)(line_width 1))
+		(line (pt 78 168)(pt 72 174)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_mux6.inc b/FPGA_quartus_GE/Video/lpm_mux6.inc
new file mode 100644
index 0000000..3cf223d
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux6.inc
@@ -0,0 +1,32 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_mux6 
+(
+	clock,
+	data0x[23..0],
+	data1x[23..0],
+	data2x[23..0],
+	data3x[23..0],
+	data4x[23..0],
+	data5x[23..0],
+	data6x[23..0],
+	data7x[23..0],
+	sel[2..0]
+)
+
+RETURNS (
+	result[23..0]
+);
diff --git a/FPGA_quartus_GE/Video/lpm_mux6.qip b/FPGA_quartus_GE/Video/lpm_mux6.qip
new file mode 100644
index 0000000..051a945
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux6.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux6.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux6.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_mux6.vhd b/FPGA_quartus_GE/Video/lpm_mux6.vhd
new file mode 100644
index 0000000..42d5aae
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_mux6.vhd
@@ -0,0 +1,335 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_mux6.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_mux6 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data0x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (23 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
+	);
+END lpm_mux6;
+
+
+ARCHITECTURE SYN OF lpm_mux6 IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (7 DOWNTO 0, 23 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (23 DOWNTO 0);
+
+BEGIN
+	sub_wire9    <= data0x(23 DOWNTO 0);
+	sub_wire8    <= data1x(23 DOWNTO 0);
+	sub_wire7    <= data2x(23 DOWNTO 0);
+	sub_wire6    <= data3x(23 DOWNTO 0);
+	sub_wire5    <= data4x(23 DOWNTO 0);
+	sub_wire4    <= data5x(23 DOWNTO 0);
+	sub_wire3    <= data6x(23 DOWNTO 0);
+	result    <= sub_wire0(23 DOWNTO 0);
+	sub_wire1    <= data7x(23 DOWNTO 0);
+	sub_wire2(7, 0)    <= sub_wire1(0);
+	sub_wire2(7, 1)    <= sub_wire1(1);
+	sub_wire2(7, 2)    <= sub_wire1(2);
+	sub_wire2(7, 3)    <= sub_wire1(3);
+	sub_wire2(7, 4)    <= sub_wire1(4);
+	sub_wire2(7, 5)    <= sub_wire1(5);
+	sub_wire2(7, 6)    <= sub_wire1(6);
+	sub_wire2(7, 7)    <= sub_wire1(7);
+	sub_wire2(7, 8)    <= sub_wire1(8);
+	sub_wire2(7, 9)    <= sub_wire1(9);
+	sub_wire2(7, 10)    <= sub_wire1(10);
+	sub_wire2(7, 11)    <= sub_wire1(11);
+	sub_wire2(7, 12)    <= sub_wire1(12);
+	sub_wire2(7, 13)    <= sub_wire1(13);
+	sub_wire2(7, 14)    <= sub_wire1(14);
+	sub_wire2(7, 15)    <= sub_wire1(15);
+	sub_wire2(7, 16)    <= sub_wire1(16);
+	sub_wire2(7, 17)    <= sub_wire1(17);
+	sub_wire2(7, 18)    <= sub_wire1(18);
+	sub_wire2(7, 19)    <= sub_wire1(19);
+	sub_wire2(7, 20)    <= sub_wire1(20);
+	sub_wire2(7, 21)    <= sub_wire1(21);
+	sub_wire2(7, 22)    <= sub_wire1(22);
+	sub_wire2(7, 23)    <= sub_wire1(23);
+	sub_wire2(6, 0)    <= sub_wire3(0);
+	sub_wire2(6, 1)    <= sub_wire3(1);
+	sub_wire2(6, 2)    <= sub_wire3(2);
+	sub_wire2(6, 3)    <= sub_wire3(3);
+	sub_wire2(6, 4)    <= sub_wire3(4);
+	sub_wire2(6, 5)    <= sub_wire3(5);
+	sub_wire2(6, 6)    <= sub_wire3(6);
+	sub_wire2(6, 7)    <= sub_wire3(7);
+	sub_wire2(6, 8)    <= sub_wire3(8);
+	sub_wire2(6, 9)    <= sub_wire3(9);
+	sub_wire2(6, 10)    <= sub_wire3(10);
+	sub_wire2(6, 11)    <= sub_wire3(11);
+	sub_wire2(6, 12)    <= sub_wire3(12);
+	sub_wire2(6, 13)    <= sub_wire3(13);
+	sub_wire2(6, 14)    <= sub_wire3(14);
+	sub_wire2(6, 15)    <= sub_wire3(15);
+	sub_wire2(6, 16)    <= sub_wire3(16);
+	sub_wire2(6, 17)    <= sub_wire3(17);
+	sub_wire2(6, 18)    <= sub_wire3(18);
+	sub_wire2(6, 19)    <= sub_wire3(19);
+	sub_wire2(6, 20)    <= sub_wire3(20);
+	sub_wire2(6, 21)    <= sub_wire3(21);
+	sub_wire2(6, 22)    <= sub_wire3(22);
+	sub_wire2(6, 23)    <= sub_wire3(23);
+	sub_wire2(5, 0)    <= sub_wire4(0);
+	sub_wire2(5, 1)    <= sub_wire4(1);
+	sub_wire2(5, 2)    <= sub_wire4(2);
+	sub_wire2(5, 3)    <= sub_wire4(3);
+	sub_wire2(5, 4)    <= sub_wire4(4);
+	sub_wire2(5, 5)    <= sub_wire4(5);
+	sub_wire2(5, 6)    <= sub_wire4(6);
+	sub_wire2(5, 7)    <= sub_wire4(7);
+	sub_wire2(5, 8)    <= sub_wire4(8);
+	sub_wire2(5, 9)    <= sub_wire4(9);
+	sub_wire2(5, 10)    <= sub_wire4(10);
+	sub_wire2(5, 11)    <= sub_wire4(11);
+	sub_wire2(5, 12)    <= sub_wire4(12);
+	sub_wire2(5, 13)    <= sub_wire4(13);
+	sub_wire2(5, 14)    <= sub_wire4(14);
+	sub_wire2(5, 15)    <= sub_wire4(15);
+	sub_wire2(5, 16)    <= sub_wire4(16);
+	sub_wire2(5, 17)    <= sub_wire4(17);
+	sub_wire2(5, 18)    <= sub_wire4(18);
+	sub_wire2(5, 19)    <= sub_wire4(19);
+	sub_wire2(5, 20)    <= sub_wire4(20);
+	sub_wire2(5, 21)    <= sub_wire4(21);
+	sub_wire2(5, 22)    <= sub_wire4(22);
+	sub_wire2(5, 23)    <= sub_wire4(23);
+	sub_wire2(4, 0)    <= sub_wire5(0);
+	sub_wire2(4, 1)    <= sub_wire5(1);
+	sub_wire2(4, 2)    <= sub_wire5(2);
+	sub_wire2(4, 3)    <= sub_wire5(3);
+	sub_wire2(4, 4)    <= sub_wire5(4);
+	sub_wire2(4, 5)    <= sub_wire5(5);
+	sub_wire2(4, 6)    <= sub_wire5(6);
+	sub_wire2(4, 7)    <= sub_wire5(7);
+	sub_wire2(4, 8)    <= sub_wire5(8);
+	sub_wire2(4, 9)    <= sub_wire5(9);
+	sub_wire2(4, 10)    <= sub_wire5(10);
+	sub_wire2(4, 11)    <= sub_wire5(11);
+	sub_wire2(4, 12)    <= sub_wire5(12);
+	sub_wire2(4, 13)    <= sub_wire5(13);
+	sub_wire2(4, 14)    <= sub_wire5(14);
+	sub_wire2(4, 15)    <= sub_wire5(15);
+	sub_wire2(4, 16)    <= sub_wire5(16);
+	sub_wire2(4, 17)    <= sub_wire5(17);
+	sub_wire2(4, 18)    <= sub_wire5(18);
+	sub_wire2(4, 19)    <= sub_wire5(19);
+	sub_wire2(4, 20)    <= sub_wire5(20);
+	sub_wire2(4, 21)    <= sub_wire5(21);
+	sub_wire2(4, 22)    <= sub_wire5(22);
+	sub_wire2(4, 23)    <= sub_wire5(23);
+	sub_wire2(3, 0)    <= sub_wire6(0);
+	sub_wire2(3, 1)    <= sub_wire6(1);
+	sub_wire2(3, 2)    <= sub_wire6(2);
+	sub_wire2(3, 3)    <= sub_wire6(3);
+	sub_wire2(3, 4)    <= sub_wire6(4);
+	sub_wire2(3, 5)    <= sub_wire6(5);
+	sub_wire2(3, 6)    <= sub_wire6(6);
+	sub_wire2(3, 7)    <= sub_wire6(7);
+	sub_wire2(3, 8)    <= sub_wire6(8);
+	sub_wire2(3, 9)    <= sub_wire6(9);
+	sub_wire2(3, 10)    <= sub_wire6(10);
+	sub_wire2(3, 11)    <= sub_wire6(11);
+	sub_wire2(3, 12)    <= sub_wire6(12);
+	sub_wire2(3, 13)    <= sub_wire6(13);
+	sub_wire2(3, 14)    <= sub_wire6(14);
+	sub_wire2(3, 15)    <= sub_wire6(15);
+	sub_wire2(3, 16)    <= sub_wire6(16);
+	sub_wire2(3, 17)    <= sub_wire6(17);
+	sub_wire2(3, 18)    <= sub_wire6(18);
+	sub_wire2(3, 19)    <= sub_wire6(19);
+	sub_wire2(3, 20)    <= sub_wire6(20);
+	sub_wire2(3, 21)    <= sub_wire6(21);
+	sub_wire2(3, 22)    <= sub_wire6(22);
+	sub_wire2(3, 23)    <= sub_wire6(23);
+	sub_wire2(2, 0)    <= sub_wire7(0);
+	sub_wire2(2, 1)    <= sub_wire7(1);
+	sub_wire2(2, 2)    <= sub_wire7(2);
+	sub_wire2(2, 3)    <= sub_wire7(3);
+	sub_wire2(2, 4)    <= sub_wire7(4);
+	sub_wire2(2, 5)    <= sub_wire7(5);
+	sub_wire2(2, 6)    <= sub_wire7(6);
+	sub_wire2(2, 7)    <= sub_wire7(7);
+	sub_wire2(2, 8)    <= sub_wire7(8);
+	sub_wire2(2, 9)    <= sub_wire7(9);
+	sub_wire2(2, 10)    <= sub_wire7(10);
+	sub_wire2(2, 11)    <= sub_wire7(11);
+	sub_wire2(2, 12)    <= sub_wire7(12);
+	sub_wire2(2, 13)    <= sub_wire7(13);
+	sub_wire2(2, 14)    <= sub_wire7(14);
+	sub_wire2(2, 15)    <= sub_wire7(15);
+	sub_wire2(2, 16)    <= sub_wire7(16);
+	sub_wire2(2, 17)    <= sub_wire7(17);
+	sub_wire2(2, 18)    <= sub_wire7(18);
+	sub_wire2(2, 19)    <= sub_wire7(19);
+	sub_wire2(2, 20)    <= sub_wire7(20);
+	sub_wire2(2, 21)    <= sub_wire7(21);
+	sub_wire2(2, 22)    <= sub_wire7(22);
+	sub_wire2(2, 23)    <= sub_wire7(23);
+	sub_wire2(1, 0)    <= sub_wire8(0);
+	sub_wire2(1, 1)    <= sub_wire8(1);
+	sub_wire2(1, 2)    <= sub_wire8(2);
+	sub_wire2(1, 3)    <= sub_wire8(3);
+	sub_wire2(1, 4)    <= sub_wire8(4);
+	sub_wire2(1, 5)    <= sub_wire8(5);
+	sub_wire2(1, 6)    <= sub_wire8(6);
+	sub_wire2(1, 7)    <= sub_wire8(7);
+	sub_wire2(1, 8)    <= sub_wire8(8);
+	sub_wire2(1, 9)    <= sub_wire8(9);
+	sub_wire2(1, 10)    <= sub_wire8(10);
+	sub_wire2(1, 11)    <= sub_wire8(11);
+	sub_wire2(1, 12)    <= sub_wire8(12);
+	sub_wire2(1, 13)    <= sub_wire8(13);
+	sub_wire2(1, 14)    <= sub_wire8(14);
+	sub_wire2(1, 15)    <= sub_wire8(15);
+	sub_wire2(1, 16)    <= sub_wire8(16);
+	sub_wire2(1, 17)    <= sub_wire8(17);
+	sub_wire2(1, 18)    <= sub_wire8(18);
+	sub_wire2(1, 19)    <= sub_wire8(19);
+	sub_wire2(1, 20)    <= sub_wire8(20);
+	sub_wire2(1, 21)    <= sub_wire8(21);
+	sub_wire2(1, 22)    <= sub_wire8(22);
+	sub_wire2(1, 23)    <= sub_wire8(23);
+	sub_wire2(0, 0)    <= sub_wire9(0);
+	sub_wire2(0, 1)    <= sub_wire9(1);
+	sub_wire2(0, 2)    <= sub_wire9(2);
+	sub_wire2(0, 3)    <= sub_wire9(3);
+	sub_wire2(0, 4)    <= sub_wire9(4);
+	sub_wire2(0, 5)    <= sub_wire9(5);
+	sub_wire2(0, 6)    <= sub_wire9(6);
+	sub_wire2(0, 7)    <= sub_wire9(7);
+	sub_wire2(0, 8)    <= sub_wire9(8);
+	sub_wire2(0, 9)    <= sub_wire9(9);
+	sub_wire2(0, 10)    <= sub_wire9(10);
+	sub_wire2(0, 11)    <= sub_wire9(11);
+	sub_wire2(0, 12)    <= sub_wire9(12);
+	sub_wire2(0, 13)    <= sub_wire9(13);
+	sub_wire2(0, 14)    <= sub_wire9(14);
+	sub_wire2(0, 15)    <= sub_wire9(15);
+	sub_wire2(0, 16)    <= sub_wire9(16);
+	sub_wire2(0, 17)    <= sub_wire9(17);
+	sub_wire2(0, 18)    <= sub_wire9(18);
+	sub_wire2(0, 19)    <= sub_wire9(19);
+	sub_wire2(0, 20)    <= sub_wire9(20);
+	sub_wire2(0, 21)    <= sub_wire9(21);
+	sub_wire2(0, 22)    <= sub_wire9(22);
+	sub_wire2(0, 23)    <= sub_wire9(23);
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_pipeline => 2,
+		lpm_size => 8,
+		lpm_type => "LPM_MUX",
+		lpm_width => 24,
+		lpm_widths => 3
+	)
+	PORT MAP (
+		sel => sel,
+		clock => clock,
+		data => sub_wire2,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data0x 0 0 24 0 INPUT NODEFVAL data0x[23..0]
+-- Retrieval info: USED_PORT: data1x 0 0 24 0 INPUT NODEFVAL data1x[23..0]
+-- Retrieval info: USED_PORT: data2x 0 0 24 0 INPUT NODEFVAL data2x[23..0]
+-- Retrieval info: USED_PORT: data3x 0 0 24 0 INPUT NODEFVAL data3x[23..0]
+-- Retrieval info: USED_PORT: data4x 0 0 24 0 INPUT NODEFVAL data4x[23..0]
+-- Retrieval info: USED_PORT: data5x 0 0 24 0 INPUT NODEFVAL data5x[23..0]
+-- Retrieval info: USED_PORT: data6x 0 0 24 0 INPUT NODEFVAL data6x[23..0]
+-- Retrieval info: USED_PORT: data7x 0 0 24 0 INPUT NODEFVAL data7x[23..0]
+-- Retrieval info: USED_PORT: result 0 0 24 0 OUTPUT NODEFVAL result[23..0]
+-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL sel[2..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: result 0 0 24 0 @result 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 7 24 0 data7x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 6 24 0 data6x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 5 24 0 data5x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 4 24 0 data4x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 3 24 0 data3x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 2 24 0 data2x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 1 24 0 data1x 0 0 24 0
+-- Retrieval info: CONNECT: @data 1 0 24 0 data0x 0 0 24 0
+-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux6_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_muxDZ.bsf b/FPGA_quartus_GE/Video/lpm_muxDZ.bsf
new file mode 100644
index 0000000..f4f1c7d
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_muxDZ.bsf
@@ -0,0 +1,76 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 168 112)
+	(text "lpm_muxDZ" (rect 54 2 135 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 96 25 108)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data1x[127..0]" (rect 4 27 72 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 80 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data0x[127..0]" (rect 4 43 72 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 80 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 59 27 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 80 72)(line_width 1))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clken" (rect 4 75 28 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 80 88)(line_width 1))
+	)
+	(port
+		(pt 88 112)
+		(input)
+		(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "sel" (rect 92 99 105 112)(font "Arial" (font_size 8)))
+		(line (pt 88 112)(pt 88 100)(line_width 1))
+	)
+	(port
+		(pt 168 64)
+		(output)
+		(text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "result[127..0]" (rect 102 51 163 64)(font "Arial" (font_size 8)))
+		(line (pt 168 64)(pt 96 64)(line_width 3))
+	)
+	(drawing
+		(line (pt 80 24)(pt 80 104)(line_width 1))
+		(line (pt 96 32)(pt 96 96)(line_width 1))
+		(line (pt 80 24)(pt 96 32)(line_width 1))
+		(line (pt 80 104)(pt 96 96)(line_width 1))
+		(line (pt 80 66)(pt 86 72)(line_width 1))
+		(line (pt 86 72)(pt 80 78)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_muxDZ.qip b/FPGA_quartus_GE/Video/lpm_muxDZ.qip
new file mode 100644
index 0000000..34ffc75
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_muxDZ.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxDZ.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_muxDZ.vhd b/FPGA_quartus_GE/Video/lpm_muxDZ.vhd
new file mode 100644
index 0000000..e9bd32e
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_muxDZ.vhd
@@ -0,0 +1,377 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_muxDZ.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 222 10/21/2009 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_muxDZ IS
+	PORT
+	(
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC ;
+		data0x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		sel		: IN STD_LOGIC ;
+		result		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+END lpm_muxDZ;
+
+
+ARCHITECTURE SYN OF lpm_muxdz IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_2D (1 DOWNTO 0, 127 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+
+BEGIN
+	sub_wire5    <= data0x(127 DOWNTO 0);
+	result    <= sub_wire0(127 DOWNTO 0);
+	sub_wire1    <= sel;
+	sub_wire2(0)    <= sub_wire1;
+	sub_wire3    <= data1x(127 DOWNTO 0);
+	sub_wire4(1, 0)    <= sub_wire3(0);
+	sub_wire4(1, 1)    <= sub_wire3(1);
+	sub_wire4(1, 2)    <= sub_wire3(2);
+	sub_wire4(1, 3)    <= sub_wire3(3);
+	sub_wire4(1, 4)    <= sub_wire3(4);
+	sub_wire4(1, 5)    <= sub_wire3(5);
+	sub_wire4(1, 6)    <= sub_wire3(6);
+	sub_wire4(1, 7)    <= sub_wire3(7);
+	sub_wire4(1, 8)    <= sub_wire3(8);
+	sub_wire4(1, 9)    <= sub_wire3(9);
+	sub_wire4(1, 10)    <= sub_wire3(10);
+	sub_wire4(1, 11)    <= sub_wire3(11);
+	sub_wire4(1, 12)    <= sub_wire3(12);
+	sub_wire4(1, 13)    <= sub_wire3(13);
+	sub_wire4(1, 14)    <= sub_wire3(14);
+	sub_wire4(1, 15)    <= sub_wire3(15);
+	sub_wire4(1, 16)    <= sub_wire3(16);
+	sub_wire4(1, 17)    <= sub_wire3(17);
+	sub_wire4(1, 18)    <= sub_wire3(18);
+	sub_wire4(1, 19)    <= sub_wire3(19);
+	sub_wire4(1, 20)    <= sub_wire3(20);
+	sub_wire4(1, 21)    <= sub_wire3(21);
+	sub_wire4(1, 22)    <= sub_wire3(22);
+	sub_wire4(1, 23)    <= sub_wire3(23);
+	sub_wire4(1, 24)    <= sub_wire3(24);
+	sub_wire4(1, 25)    <= sub_wire3(25);
+	sub_wire4(1, 26)    <= sub_wire3(26);
+	sub_wire4(1, 27)    <= sub_wire3(27);
+	sub_wire4(1, 28)    <= sub_wire3(28);
+	sub_wire4(1, 29)    <= sub_wire3(29);
+	sub_wire4(1, 30)    <= sub_wire3(30);
+	sub_wire4(1, 31)    <= sub_wire3(31);
+	sub_wire4(1, 32)    <= sub_wire3(32);
+	sub_wire4(1, 33)    <= sub_wire3(33);
+	sub_wire4(1, 34)    <= sub_wire3(34);
+	sub_wire4(1, 35)    <= sub_wire3(35);
+	sub_wire4(1, 36)    <= sub_wire3(36);
+	sub_wire4(1, 37)    <= sub_wire3(37);
+	sub_wire4(1, 38)    <= sub_wire3(38);
+	sub_wire4(1, 39)    <= sub_wire3(39);
+	sub_wire4(1, 40)    <= sub_wire3(40);
+	sub_wire4(1, 41)    <= sub_wire3(41);
+	sub_wire4(1, 42)    <= sub_wire3(42);
+	sub_wire4(1, 43)    <= sub_wire3(43);
+	sub_wire4(1, 44)    <= sub_wire3(44);
+	sub_wire4(1, 45)    <= sub_wire3(45);
+	sub_wire4(1, 46)    <= sub_wire3(46);
+	sub_wire4(1, 47)    <= sub_wire3(47);
+	sub_wire4(1, 48)    <= sub_wire3(48);
+	sub_wire4(1, 49)    <= sub_wire3(49);
+	sub_wire4(1, 50)    <= sub_wire3(50);
+	sub_wire4(1, 51)    <= sub_wire3(51);
+	sub_wire4(1, 52)    <= sub_wire3(52);
+	sub_wire4(1, 53)    <= sub_wire3(53);
+	sub_wire4(1, 54)    <= sub_wire3(54);
+	sub_wire4(1, 55)    <= sub_wire3(55);
+	sub_wire4(1, 56)    <= sub_wire3(56);
+	sub_wire4(1, 57)    <= sub_wire3(57);
+	sub_wire4(1, 58)    <= sub_wire3(58);
+	sub_wire4(1, 59)    <= sub_wire3(59);
+	sub_wire4(1, 60)    <= sub_wire3(60);
+	sub_wire4(1, 61)    <= sub_wire3(61);
+	sub_wire4(1, 62)    <= sub_wire3(62);
+	sub_wire4(1, 63)    <= sub_wire3(63);
+	sub_wire4(1, 64)    <= sub_wire3(64);
+	sub_wire4(1, 65)    <= sub_wire3(65);
+	sub_wire4(1, 66)    <= sub_wire3(66);
+	sub_wire4(1, 67)    <= sub_wire3(67);
+	sub_wire4(1, 68)    <= sub_wire3(68);
+	sub_wire4(1, 69)    <= sub_wire3(69);
+	sub_wire4(1, 70)    <= sub_wire3(70);
+	sub_wire4(1, 71)    <= sub_wire3(71);
+	sub_wire4(1, 72)    <= sub_wire3(72);
+	sub_wire4(1, 73)    <= sub_wire3(73);
+	sub_wire4(1, 74)    <= sub_wire3(74);
+	sub_wire4(1, 75)    <= sub_wire3(75);
+	sub_wire4(1, 76)    <= sub_wire3(76);
+	sub_wire4(1, 77)    <= sub_wire3(77);
+	sub_wire4(1, 78)    <= sub_wire3(78);
+	sub_wire4(1, 79)    <= sub_wire3(79);
+	sub_wire4(1, 80)    <= sub_wire3(80);
+	sub_wire4(1, 81)    <= sub_wire3(81);
+	sub_wire4(1, 82)    <= sub_wire3(82);
+	sub_wire4(1, 83)    <= sub_wire3(83);
+	sub_wire4(1, 84)    <= sub_wire3(84);
+	sub_wire4(1, 85)    <= sub_wire3(85);
+	sub_wire4(1, 86)    <= sub_wire3(86);
+	sub_wire4(1, 87)    <= sub_wire3(87);
+	sub_wire4(1, 88)    <= sub_wire3(88);
+	sub_wire4(1, 89)    <= sub_wire3(89);
+	sub_wire4(1, 90)    <= sub_wire3(90);
+	sub_wire4(1, 91)    <= sub_wire3(91);
+	sub_wire4(1, 92)    <= sub_wire3(92);
+	sub_wire4(1, 93)    <= sub_wire3(93);
+	sub_wire4(1, 94)    <= sub_wire3(94);
+	sub_wire4(1, 95)    <= sub_wire3(95);
+	sub_wire4(1, 96)    <= sub_wire3(96);
+	sub_wire4(1, 97)    <= sub_wire3(97);
+	sub_wire4(1, 98)    <= sub_wire3(98);
+	sub_wire4(1, 99)    <= sub_wire3(99);
+	sub_wire4(1, 100)    <= sub_wire3(100);
+	sub_wire4(1, 101)    <= sub_wire3(101);
+	sub_wire4(1, 102)    <= sub_wire3(102);
+	sub_wire4(1, 103)    <= sub_wire3(103);
+	sub_wire4(1, 104)    <= sub_wire3(104);
+	sub_wire4(1, 105)    <= sub_wire3(105);
+	sub_wire4(1, 106)    <= sub_wire3(106);
+	sub_wire4(1, 107)    <= sub_wire3(107);
+	sub_wire4(1, 108)    <= sub_wire3(108);
+	sub_wire4(1, 109)    <= sub_wire3(109);
+	sub_wire4(1, 110)    <= sub_wire3(110);
+	sub_wire4(1, 111)    <= sub_wire3(111);
+	sub_wire4(1, 112)    <= sub_wire3(112);
+	sub_wire4(1, 113)    <= sub_wire3(113);
+	sub_wire4(1, 114)    <= sub_wire3(114);
+	sub_wire4(1, 115)    <= sub_wire3(115);
+	sub_wire4(1, 116)    <= sub_wire3(116);
+	sub_wire4(1, 117)    <= sub_wire3(117);
+	sub_wire4(1, 118)    <= sub_wire3(118);
+	sub_wire4(1, 119)    <= sub_wire3(119);
+	sub_wire4(1, 120)    <= sub_wire3(120);
+	sub_wire4(1, 121)    <= sub_wire3(121);
+	sub_wire4(1, 122)    <= sub_wire3(122);
+	sub_wire4(1, 123)    <= sub_wire3(123);
+	sub_wire4(1, 124)    <= sub_wire3(124);
+	sub_wire4(1, 125)    <= sub_wire3(125);
+	sub_wire4(1, 126)    <= sub_wire3(126);
+	sub_wire4(1, 127)    <= sub_wire3(127);
+	sub_wire4(0, 0)    <= sub_wire5(0);
+	sub_wire4(0, 1)    <= sub_wire5(1);
+	sub_wire4(0, 2)    <= sub_wire5(2);
+	sub_wire4(0, 3)    <= sub_wire5(3);
+	sub_wire4(0, 4)    <= sub_wire5(4);
+	sub_wire4(0, 5)    <= sub_wire5(5);
+	sub_wire4(0, 6)    <= sub_wire5(6);
+	sub_wire4(0, 7)    <= sub_wire5(7);
+	sub_wire4(0, 8)    <= sub_wire5(8);
+	sub_wire4(0, 9)    <= sub_wire5(9);
+	sub_wire4(0, 10)    <= sub_wire5(10);
+	sub_wire4(0, 11)    <= sub_wire5(11);
+	sub_wire4(0, 12)    <= sub_wire5(12);
+	sub_wire4(0, 13)    <= sub_wire5(13);
+	sub_wire4(0, 14)    <= sub_wire5(14);
+	sub_wire4(0, 15)    <= sub_wire5(15);
+	sub_wire4(0, 16)    <= sub_wire5(16);
+	sub_wire4(0, 17)    <= sub_wire5(17);
+	sub_wire4(0, 18)    <= sub_wire5(18);
+	sub_wire4(0, 19)    <= sub_wire5(19);
+	sub_wire4(0, 20)    <= sub_wire5(20);
+	sub_wire4(0, 21)    <= sub_wire5(21);
+	sub_wire4(0, 22)    <= sub_wire5(22);
+	sub_wire4(0, 23)    <= sub_wire5(23);
+	sub_wire4(0, 24)    <= sub_wire5(24);
+	sub_wire4(0, 25)    <= sub_wire5(25);
+	sub_wire4(0, 26)    <= sub_wire5(26);
+	sub_wire4(0, 27)    <= sub_wire5(27);
+	sub_wire4(0, 28)    <= sub_wire5(28);
+	sub_wire4(0, 29)    <= sub_wire5(29);
+	sub_wire4(0, 30)    <= sub_wire5(30);
+	sub_wire4(0, 31)    <= sub_wire5(31);
+	sub_wire4(0, 32)    <= sub_wire5(32);
+	sub_wire4(0, 33)    <= sub_wire5(33);
+	sub_wire4(0, 34)    <= sub_wire5(34);
+	sub_wire4(0, 35)    <= sub_wire5(35);
+	sub_wire4(0, 36)    <= sub_wire5(36);
+	sub_wire4(0, 37)    <= sub_wire5(37);
+	sub_wire4(0, 38)    <= sub_wire5(38);
+	sub_wire4(0, 39)    <= sub_wire5(39);
+	sub_wire4(0, 40)    <= sub_wire5(40);
+	sub_wire4(0, 41)    <= sub_wire5(41);
+	sub_wire4(0, 42)    <= sub_wire5(42);
+	sub_wire4(0, 43)    <= sub_wire5(43);
+	sub_wire4(0, 44)    <= sub_wire5(44);
+	sub_wire4(0, 45)    <= sub_wire5(45);
+	sub_wire4(0, 46)    <= sub_wire5(46);
+	sub_wire4(0, 47)    <= sub_wire5(47);
+	sub_wire4(0, 48)    <= sub_wire5(48);
+	sub_wire4(0, 49)    <= sub_wire5(49);
+	sub_wire4(0, 50)    <= sub_wire5(50);
+	sub_wire4(0, 51)    <= sub_wire5(51);
+	sub_wire4(0, 52)    <= sub_wire5(52);
+	sub_wire4(0, 53)    <= sub_wire5(53);
+	sub_wire4(0, 54)    <= sub_wire5(54);
+	sub_wire4(0, 55)    <= sub_wire5(55);
+	sub_wire4(0, 56)    <= sub_wire5(56);
+	sub_wire4(0, 57)    <= sub_wire5(57);
+	sub_wire4(0, 58)    <= sub_wire5(58);
+	sub_wire4(0, 59)    <= sub_wire5(59);
+	sub_wire4(0, 60)    <= sub_wire5(60);
+	sub_wire4(0, 61)    <= sub_wire5(61);
+	sub_wire4(0, 62)    <= sub_wire5(62);
+	sub_wire4(0, 63)    <= sub_wire5(63);
+	sub_wire4(0, 64)    <= sub_wire5(64);
+	sub_wire4(0, 65)    <= sub_wire5(65);
+	sub_wire4(0, 66)    <= sub_wire5(66);
+	sub_wire4(0, 67)    <= sub_wire5(67);
+	sub_wire4(0, 68)    <= sub_wire5(68);
+	sub_wire4(0, 69)    <= sub_wire5(69);
+	sub_wire4(0, 70)    <= sub_wire5(70);
+	sub_wire4(0, 71)    <= sub_wire5(71);
+	sub_wire4(0, 72)    <= sub_wire5(72);
+	sub_wire4(0, 73)    <= sub_wire5(73);
+	sub_wire4(0, 74)    <= sub_wire5(74);
+	sub_wire4(0, 75)    <= sub_wire5(75);
+	sub_wire4(0, 76)    <= sub_wire5(76);
+	sub_wire4(0, 77)    <= sub_wire5(77);
+	sub_wire4(0, 78)    <= sub_wire5(78);
+	sub_wire4(0, 79)    <= sub_wire5(79);
+	sub_wire4(0, 80)    <= sub_wire5(80);
+	sub_wire4(0, 81)    <= sub_wire5(81);
+	sub_wire4(0, 82)    <= sub_wire5(82);
+	sub_wire4(0, 83)    <= sub_wire5(83);
+	sub_wire4(0, 84)    <= sub_wire5(84);
+	sub_wire4(0, 85)    <= sub_wire5(85);
+	sub_wire4(0, 86)    <= sub_wire5(86);
+	sub_wire4(0, 87)    <= sub_wire5(87);
+	sub_wire4(0, 88)    <= sub_wire5(88);
+	sub_wire4(0, 89)    <= sub_wire5(89);
+	sub_wire4(0, 90)    <= sub_wire5(90);
+	sub_wire4(0, 91)    <= sub_wire5(91);
+	sub_wire4(0, 92)    <= sub_wire5(92);
+	sub_wire4(0, 93)    <= sub_wire5(93);
+	sub_wire4(0, 94)    <= sub_wire5(94);
+	sub_wire4(0, 95)    <= sub_wire5(95);
+	sub_wire4(0, 96)    <= sub_wire5(96);
+	sub_wire4(0, 97)    <= sub_wire5(97);
+	sub_wire4(0, 98)    <= sub_wire5(98);
+	sub_wire4(0, 99)    <= sub_wire5(99);
+	sub_wire4(0, 100)    <= sub_wire5(100);
+	sub_wire4(0, 101)    <= sub_wire5(101);
+	sub_wire4(0, 102)    <= sub_wire5(102);
+	sub_wire4(0, 103)    <= sub_wire5(103);
+	sub_wire4(0, 104)    <= sub_wire5(104);
+	sub_wire4(0, 105)    <= sub_wire5(105);
+	sub_wire4(0, 106)    <= sub_wire5(106);
+	sub_wire4(0, 107)    <= sub_wire5(107);
+	sub_wire4(0, 108)    <= sub_wire5(108);
+	sub_wire4(0, 109)    <= sub_wire5(109);
+	sub_wire4(0, 110)    <= sub_wire5(110);
+	sub_wire4(0, 111)    <= sub_wire5(111);
+	sub_wire4(0, 112)    <= sub_wire5(112);
+	sub_wire4(0, 113)    <= sub_wire5(113);
+	sub_wire4(0, 114)    <= sub_wire5(114);
+	sub_wire4(0, 115)    <= sub_wire5(115);
+	sub_wire4(0, 116)    <= sub_wire5(116);
+	sub_wire4(0, 117)    <= sub_wire5(117);
+	sub_wire4(0, 118)    <= sub_wire5(118);
+	sub_wire4(0, 119)    <= sub_wire5(119);
+	sub_wire4(0, 120)    <= sub_wire5(120);
+	sub_wire4(0, 121)    <= sub_wire5(121);
+	sub_wire4(0, 122)    <= sub_wire5(122);
+	sub_wire4(0, 123)    <= sub_wire5(123);
+	sub_wire4(0, 124)    <= sub_wire5(124);
+	sub_wire4(0, 125)    <= sub_wire5(125);
+	sub_wire4(0, 126)    <= sub_wire5(126);
+	sub_wire4(0, 127)    <= sub_wire5(127);
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_pipeline => 1,
+		lpm_size => 2,
+		lpm_type => "LPM_MUX",
+		lpm_width => 128,
+		lpm_widths => 1
+	)
+	PORT MAP (
+		sel => sub_wire2,
+		clken => clken,
+		clock => clock,
+		data => sub_wire4,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
+-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL data0x[127..0]
+-- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL data1x[127..0]
+-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0]
+-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
+-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0
+-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_muxDZ2.bsf b/FPGA_quartus_GE/Video/lpm_muxDZ2.bsf
new file mode 100644
index 0000000..b7e3184
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_muxDZ2.bsf
@@ -0,0 +1,60 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 96 80)
+	(text "lpm_muxDZ2" (rect 10 2 99 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data1" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "data1" (rect 4 27 31 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 40 40)(line_width 1))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "data0" (rect 4 43 31 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 40 56)(line_width 1))
+	)
+	(port
+		(pt 48 80)
+		(input)
+		(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "sel" (rect 52 67 65 80)(font "Arial" (font_size 8)))
+		(line (pt 48 80)(pt 48 68)(line_width 1))
+	)
+	(port
+		(pt 96 48)
+		(output)
+		(text "result" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "result" (rect 66 35 91 48)(font "Arial" (font_size 8)))
+		(line (pt 96 48)(pt 56 48)(line_width 1))
+	)
+	(drawing
+		(line (pt 40 24)(pt 40 72)(line_width 1))
+		(line (pt 56 32)(pt 56 64)(line_width 1))
+		(line (pt 40 24)(pt 56 32)(line_width 1))
+		(line (pt 40 72)(pt 56 64)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_muxDZ2.qip b/FPGA_quartus_GE/Video/lpm_muxDZ2.qip
new file mode 100644
index 0000000..8203bc6
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_muxDZ2.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxDZ2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxDZ2.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_muxDZ2.vhd b/FPGA_quartus_GE/Video/lpm_muxDZ2.vhd
new file mode 100644
index 0000000..42e0c81
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_muxDZ2.vhd
@@ -0,0 +1,115 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_muxDZ2.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 222 10/21/2009 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_muxDZ2 IS
+	PORT
+	(
+		data0		: IN STD_LOGIC ;
+		data1		: IN STD_LOGIC ;
+		sel		: IN STD_LOGIC ;
+		result		: OUT STD_LOGIC 
+	);
+END lpm_muxDZ2;
+
+
+ARCHITECTURE SYN OF lpm_muxdz2 IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_2D (1 DOWNTO 0, 0 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC ;
+
+BEGIN
+	sub_wire6    <= data0;
+	sub_wire1    <= sub_wire0(0);
+	result    <= sub_wire1;
+	sub_wire2    <= sel;
+	sub_wire3(0)    <= sub_wire2;
+	sub_wire4    <= data1;
+	sub_wire5(1, 0)    <= sub_wire4;
+	sub_wire5(0, 0)    <= sub_wire6;
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_size => 2,
+		lpm_type => "LPM_MUX",
+		lpm_width => 1,
+		lpm_widths => 1
+	)
+	PORT MAP (
+		sel => sub_wire3,
+		data => sub_wire5,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "1"
+-- Retrieval info: USED_PORT: data0 0 0 0 0 INPUT NODEFVAL data0
+-- Retrieval info: USED_PORT: data1 0 0 0 0 INPUT NODEFVAL data1
+-- Retrieval info: USED_PORT: result 0 0 0 0 OUTPUT NODEFVAL result
+-- Retrieval info: USED_PORT: sel 0 0 0 0 INPUT NODEFVAL sel
+-- Retrieval info: CONNECT: result 0 0 0 0 @result 0 0 1 0
+-- Retrieval info: CONNECT: @data 1 1 1 0 data1 0 0 0 0
+-- Retrieval info: CONNECT: @data 1 0 1 0 data0 0 0 0 0
+-- Retrieval info: CONNECT: @sel 0 0 1 0 sel 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxDZ2_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_muxVDM.bsf b/FPGA_quartus_GE/Video/lpm_muxVDM.bsf
new file mode 100644
index 0000000..42d235c
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_muxVDM.bsf
@@ -0,0 +1,158 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 168 304)
+	(text "lpm_muxVDM" (rect 47 2 143 18)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 288 25 300)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "data15x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data15x[127..0]" (rect 4 27 78 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 80 40)(line_width 3))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "data14x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data14x[127..0]" (rect 4 43 78 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 80 56)(line_width 3))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "data13x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data13x[127..0]" (rect 4 59 78 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 80 72)(line_width 3))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "data12x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data12x[127..0]" (rect 4 75 78 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 80 88)(line_width 3))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "data11x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data11x[127..0]" (rect 4 91 78 104)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 80 104)(line_width 3))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "data10x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
+		(text "data10x[127..0]" (rect 4 107 78 120)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 80 120)(line_width 3))
+	)
+	(port
+		(pt 0 136)
+		(input)
+		(text "data9x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data9x[127..0]" (rect 4 123 72 136)(font "Arial" (font_size 8)))
+		(line (pt 0 136)(pt 80 136)(line_width 3))
+	)
+	(port
+		(pt 0 152)
+		(input)
+		(text "data8x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data8x[127..0]" (rect 4 139 72 152)(font "Arial" (font_size 8)))
+		(line (pt 0 152)(pt 80 152)(line_width 3))
+	)
+	(port
+		(pt 0 168)
+		(input)
+		(text "data7x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data7x[127..0]" (rect 4 155 72 168)(font "Arial" (font_size 8)))
+		(line (pt 0 168)(pt 80 168)(line_width 3))
+	)
+	(port
+		(pt 0 184)
+		(input)
+		(text "data6x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data6x[127..0]" (rect 4 171 72 184)(font "Arial" (font_size 8)))
+		(line (pt 0 184)(pt 80 184)(line_width 3))
+	)
+	(port
+		(pt 0 200)
+		(input)
+		(text "data5x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data5x[127..0]" (rect 4 187 72 200)(font "Arial" (font_size 8)))
+		(line (pt 0 200)(pt 80 200)(line_width 3))
+	)
+	(port
+		(pt 0 216)
+		(input)
+		(text "data4x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data4x[127..0]" (rect 4 203 72 216)(font "Arial" (font_size 8)))
+		(line (pt 0 216)(pt 80 216)(line_width 3))
+	)
+	(port
+		(pt 0 232)
+		(input)
+		(text "data3x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data3x[127..0]" (rect 4 219 72 232)(font "Arial" (font_size 8)))
+		(line (pt 0 232)(pt 80 232)(line_width 3))
+	)
+	(port
+		(pt 0 248)
+		(input)
+		(text "data2x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data2x[127..0]" (rect 4 235 72 248)(font "Arial" (font_size 8)))
+		(line (pt 0 248)(pt 80 248)(line_width 3))
+	)
+	(port
+		(pt 0 264)
+		(input)
+		(text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data1x[127..0]" (rect 4 251 72 264)(font "Arial" (font_size 8)))
+		(line (pt 0 264)(pt 80 264)(line_width 3))
+	)
+	(port
+		(pt 0 280)
+		(input)
+		(text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
+		(text "data0x[127..0]" (rect 4 267 72 280)(font "Arial" (font_size 8)))
+		(line (pt 0 280)(pt 80 280)(line_width 3))
+	)
+	(port
+		(pt 88 304)
+		(input)
+		(text "sel[3..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
+		(text "sel[3..0]" (rect 92 291 129 304)(font "Arial" (font_size 8)))
+		(line (pt 88 304)(pt 88 292)(line_width 3))
+	)
+	(port
+		(pt 168 160)
+		(output)
+		(text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
+		(text "result[127..0]" (rect 102 147 163 160)(font "Arial" (font_size 8)))
+		(line (pt 168 160)(pt 96 160)(line_width 3))
+	)
+	(drawing
+		(line (pt 80 24)(pt 80 296)(line_width 1))
+		(line (pt 96 32)(pt 96 288)(line_width 1))
+		(line (pt 80 24)(pt 96 32)(line_width 1))
+		(line (pt 80 296)(pt 96 288)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_muxVDM.qip b/FPGA_quartus_GE/Video/lpm_muxVDM.qip
new file mode 100644
index 0000000..08a824e
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_muxVDM.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_MUX"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_muxVDM.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_muxVDM.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_muxVDM.vhd b/FPGA_quartus_GE/Video/lpm_muxVDM.vhd
new file mode 100644
index 0000000..662c8be
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_muxVDM.vhd
@@ -0,0 +1,2225 @@
+-- megafunction wizard: %LPM_MUX%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_mux 
+
+-- ============================================================
+-- File Name: lpm_muxVDM.vhd
+-- Megafunction Name(s):
+-- 			lpm_mux
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 222 10/21/2009 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2009 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.lpm_components.all;
+
+ENTITY lpm_muxVDM IS
+	PORT
+	(
+		data0x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data10x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data11x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data12x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data13x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data14x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data15x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data1x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data2x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data3x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data4x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data5x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data6x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data7x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data8x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		data9x		: IN STD_LOGIC_VECTOR (127 DOWNTO 0);
+		sel		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		result		: OUT STD_LOGIC_VECTOR (127 DOWNTO 0)
+	);
+END lpm_muxVDM;
+
+
+ARCHITECTURE SYN OF lpm_muxvdm IS
+
+--	type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC_2D (15 DOWNTO 0, 127 DOWNTO 0);
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire9	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire10	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire11	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire12	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire13	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire14	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire15	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire16	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+	SIGNAL sub_wire17	: STD_LOGIC_VECTOR (127 DOWNTO 0);
+
+BEGIN
+	sub_wire17    <= data0x(127 DOWNTO 0);
+	sub_wire16    <= data1x(127 DOWNTO 0);
+	sub_wire15    <= data2x(127 DOWNTO 0);
+	sub_wire14    <= data3x(127 DOWNTO 0);
+	sub_wire13    <= data4x(127 DOWNTO 0);
+	sub_wire12    <= data5x(127 DOWNTO 0);
+	sub_wire11    <= data6x(127 DOWNTO 0);
+	sub_wire10    <= data7x(127 DOWNTO 0);
+	sub_wire9    <= data8x(127 DOWNTO 0);
+	sub_wire8    <= data9x(127 DOWNTO 0);
+	sub_wire7    <= data10x(127 DOWNTO 0);
+	sub_wire6    <= data11x(127 DOWNTO 0);
+	sub_wire5    <= data12x(127 DOWNTO 0);
+	sub_wire4    <= data13x(127 DOWNTO 0);
+	sub_wire3    <= data14x(127 DOWNTO 0);
+	result    <= sub_wire0(127 DOWNTO 0);
+	sub_wire1    <= data15x(127 DOWNTO 0);
+	sub_wire2(15, 0)    <= sub_wire1(0);
+	sub_wire2(15, 1)    <= sub_wire1(1);
+	sub_wire2(15, 2)    <= sub_wire1(2);
+	sub_wire2(15, 3)    <= sub_wire1(3);
+	sub_wire2(15, 4)    <= sub_wire1(4);
+	sub_wire2(15, 5)    <= sub_wire1(5);
+	sub_wire2(15, 6)    <= sub_wire1(6);
+	sub_wire2(15, 7)    <= sub_wire1(7);
+	sub_wire2(15, 8)    <= sub_wire1(8);
+	sub_wire2(15, 9)    <= sub_wire1(9);
+	sub_wire2(15, 10)    <= sub_wire1(10);
+	sub_wire2(15, 11)    <= sub_wire1(11);
+	sub_wire2(15, 12)    <= sub_wire1(12);
+	sub_wire2(15, 13)    <= sub_wire1(13);
+	sub_wire2(15, 14)    <= sub_wire1(14);
+	sub_wire2(15, 15)    <= sub_wire1(15);
+	sub_wire2(15, 16)    <= sub_wire1(16);
+	sub_wire2(15, 17)    <= sub_wire1(17);
+	sub_wire2(15, 18)    <= sub_wire1(18);
+	sub_wire2(15, 19)    <= sub_wire1(19);
+	sub_wire2(15, 20)    <= sub_wire1(20);
+	sub_wire2(15, 21)    <= sub_wire1(21);
+	sub_wire2(15, 22)    <= sub_wire1(22);
+	sub_wire2(15, 23)    <= sub_wire1(23);
+	sub_wire2(15, 24)    <= sub_wire1(24);
+	sub_wire2(15, 25)    <= sub_wire1(25);
+	sub_wire2(15, 26)    <= sub_wire1(26);
+	sub_wire2(15, 27)    <= sub_wire1(27);
+	sub_wire2(15, 28)    <= sub_wire1(28);
+	sub_wire2(15, 29)    <= sub_wire1(29);
+	sub_wire2(15, 30)    <= sub_wire1(30);
+	sub_wire2(15, 31)    <= sub_wire1(31);
+	sub_wire2(15, 32)    <= sub_wire1(32);
+	sub_wire2(15, 33)    <= sub_wire1(33);
+	sub_wire2(15, 34)    <= sub_wire1(34);
+	sub_wire2(15, 35)    <= sub_wire1(35);
+	sub_wire2(15, 36)    <= sub_wire1(36);
+	sub_wire2(15, 37)    <= sub_wire1(37);
+	sub_wire2(15, 38)    <= sub_wire1(38);
+	sub_wire2(15, 39)    <= sub_wire1(39);
+	sub_wire2(15, 40)    <= sub_wire1(40);
+	sub_wire2(15, 41)    <= sub_wire1(41);
+	sub_wire2(15, 42)    <= sub_wire1(42);
+	sub_wire2(15, 43)    <= sub_wire1(43);
+	sub_wire2(15, 44)    <= sub_wire1(44);
+	sub_wire2(15, 45)    <= sub_wire1(45);
+	sub_wire2(15, 46)    <= sub_wire1(46);
+	sub_wire2(15, 47)    <= sub_wire1(47);
+	sub_wire2(15, 48)    <= sub_wire1(48);
+	sub_wire2(15, 49)    <= sub_wire1(49);
+	sub_wire2(15, 50)    <= sub_wire1(50);
+	sub_wire2(15, 51)    <= sub_wire1(51);
+	sub_wire2(15, 52)    <= sub_wire1(52);
+	sub_wire2(15, 53)    <= sub_wire1(53);
+	sub_wire2(15, 54)    <= sub_wire1(54);
+	sub_wire2(15, 55)    <= sub_wire1(55);
+	sub_wire2(15, 56)    <= sub_wire1(56);
+	sub_wire2(15, 57)    <= sub_wire1(57);
+	sub_wire2(15, 58)    <= sub_wire1(58);
+	sub_wire2(15, 59)    <= sub_wire1(59);
+	sub_wire2(15, 60)    <= sub_wire1(60);
+	sub_wire2(15, 61)    <= sub_wire1(61);
+	sub_wire2(15, 62)    <= sub_wire1(62);
+	sub_wire2(15, 63)    <= sub_wire1(63);
+	sub_wire2(15, 64)    <= sub_wire1(64);
+	sub_wire2(15, 65)    <= sub_wire1(65);
+	sub_wire2(15, 66)    <= sub_wire1(66);
+	sub_wire2(15, 67)    <= sub_wire1(67);
+	sub_wire2(15, 68)    <= sub_wire1(68);
+	sub_wire2(15, 69)    <= sub_wire1(69);
+	sub_wire2(15, 70)    <= sub_wire1(70);
+	sub_wire2(15, 71)    <= sub_wire1(71);
+	sub_wire2(15, 72)    <= sub_wire1(72);
+	sub_wire2(15, 73)    <= sub_wire1(73);
+	sub_wire2(15, 74)    <= sub_wire1(74);
+	sub_wire2(15, 75)    <= sub_wire1(75);
+	sub_wire2(15, 76)    <= sub_wire1(76);
+	sub_wire2(15, 77)    <= sub_wire1(77);
+	sub_wire2(15, 78)    <= sub_wire1(78);
+	sub_wire2(15, 79)    <= sub_wire1(79);
+	sub_wire2(15, 80)    <= sub_wire1(80);
+	sub_wire2(15, 81)    <= sub_wire1(81);
+	sub_wire2(15, 82)    <= sub_wire1(82);
+	sub_wire2(15, 83)    <= sub_wire1(83);
+	sub_wire2(15, 84)    <= sub_wire1(84);
+	sub_wire2(15, 85)    <= sub_wire1(85);
+	sub_wire2(15, 86)    <= sub_wire1(86);
+	sub_wire2(15, 87)    <= sub_wire1(87);
+	sub_wire2(15, 88)    <= sub_wire1(88);
+	sub_wire2(15, 89)    <= sub_wire1(89);
+	sub_wire2(15, 90)    <= sub_wire1(90);
+	sub_wire2(15, 91)    <= sub_wire1(91);
+	sub_wire2(15, 92)    <= sub_wire1(92);
+	sub_wire2(15, 93)    <= sub_wire1(93);
+	sub_wire2(15, 94)    <= sub_wire1(94);
+	sub_wire2(15, 95)    <= sub_wire1(95);
+	sub_wire2(15, 96)    <= sub_wire1(96);
+	sub_wire2(15, 97)    <= sub_wire1(97);
+	sub_wire2(15, 98)    <= sub_wire1(98);
+	sub_wire2(15, 99)    <= sub_wire1(99);
+	sub_wire2(15, 100)    <= sub_wire1(100);
+	sub_wire2(15, 101)    <= sub_wire1(101);
+	sub_wire2(15, 102)    <= sub_wire1(102);
+	sub_wire2(15, 103)    <= sub_wire1(103);
+	sub_wire2(15, 104)    <= sub_wire1(104);
+	sub_wire2(15, 105)    <= sub_wire1(105);
+	sub_wire2(15, 106)    <= sub_wire1(106);
+	sub_wire2(15, 107)    <= sub_wire1(107);
+	sub_wire2(15, 108)    <= sub_wire1(108);
+	sub_wire2(15, 109)    <= sub_wire1(109);
+	sub_wire2(15, 110)    <= sub_wire1(110);
+	sub_wire2(15, 111)    <= sub_wire1(111);
+	sub_wire2(15, 112)    <= sub_wire1(112);
+	sub_wire2(15, 113)    <= sub_wire1(113);
+	sub_wire2(15, 114)    <= sub_wire1(114);
+	sub_wire2(15, 115)    <= sub_wire1(115);
+	sub_wire2(15, 116)    <= sub_wire1(116);
+	sub_wire2(15, 117)    <= sub_wire1(117);
+	sub_wire2(15, 118)    <= sub_wire1(118);
+	sub_wire2(15, 119)    <= sub_wire1(119);
+	sub_wire2(15, 120)    <= sub_wire1(120);
+	sub_wire2(15, 121)    <= sub_wire1(121);
+	sub_wire2(15, 122)    <= sub_wire1(122);
+	sub_wire2(15, 123)    <= sub_wire1(123);
+	sub_wire2(15, 124)    <= sub_wire1(124);
+	sub_wire2(15, 125)    <= sub_wire1(125);
+	sub_wire2(15, 126)    <= sub_wire1(126);
+	sub_wire2(15, 127)    <= sub_wire1(127);
+	sub_wire2(14, 0)    <= sub_wire3(0);
+	sub_wire2(14, 1)    <= sub_wire3(1);
+	sub_wire2(14, 2)    <= sub_wire3(2);
+	sub_wire2(14, 3)    <= sub_wire3(3);
+	sub_wire2(14, 4)    <= sub_wire3(4);
+	sub_wire2(14, 5)    <= sub_wire3(5);
+	sub_wire2(14, 6)    <= sub_wire3(6);
+	sub_wire2(14, 7)    <= sub_wire3(7);
+	sub_wire2(14, 8)    <= sub_wire3(8);
+	sub_wire2(14, 9)    <= sub_wire3(9);
+	sub_wire2(14, 10)    <= sub_wire3(10);
+	sub_wire2(14, 11)    <= sub_wire3(11);
+	sub_wire2(14, 12)    <= sub_wire3(12);
+	sub_wire2(14, 13)    <= sub_wire3(13);
+	sub_wire2(14, 14)    <= sub_wire3(14);
+	sub_wire2(14, 15)    <= sub_wire3(15);
+	sub_wire2(14, 16)    <= sub_wire3(16);
+	sub_wire2(14, 17)    <= sub_wire3(17);
+	sub_wire2(14, 18)    <= sub_wire3(18);
+	sub_wire2(14, 19)    <= sub_wire3(19);
+	sub_wire2(14, 20)    <= sub_wire3(20);
+	sub_wire2(14, 21)    <= sub_wire3(21);
+	sub_wire2(14, 22)    <= sub_wire3(22);
+	sub_wire2(14, 23)    <= sub_wire3(23);
+	sub_wire2(14, 24)    <= sub_wire3(24);
+	sub_wire2(14, 25)    <= sub_wire3(25);
+	sub_wire2(14, 26)    <= sub_wire3(26);
+	sub_wire2(14, 27)    <= sub_wire3(27);
+	sub_wire2(14, 28)    <= sub_wire3(28);
+	sub_wire2(14, 29)    <= sub_wire3(29);
+	sub_wire2(14, 30)    <= sub_wire3(30);
+	sub_wire2(14, 31)    <= sub_wire3(31);
+	sub_wire2(14, 32)    <= sub_wire3(32);
+	sub_wire2(14, 33)    <= sub_wire3(33);
+	sub_wire2(14, 34)    <= sub_wire3(34);
+	sub_wire2(14, 35)    <= sub_wire3(35);
+	sub_wire2(14, 36)    <= sub_wire3(36);
+	sub_wire2(14, 37)    <= sub_wire3(37);
+	sub_wire2(14, 38)    <= sub_wire3(38);
+	sub_wire2(14, 39)    <= sub_wire3(39);
+	sub_wire2(14, 40)    <= sub_wire3(40);
+	sub_wire2(14, 41)    <= sub_wire3(41);
+	sub_wire2(14, 42)    <= sub_wire3(42);
+	sub_wire2(14, 43)    <= sub_wire3(43);
+	sub_wire2(14, 44)    <= sub_wire3(44);
+	sub_wire2(14, 45)    <= sub_wire3(45);
+	sub_wire2(14, 46)    <= sub_wire3(46);
+	sub_wire2(14, 47)    <= sub_wire3(47);
+	sub_wire2(14, 48)    <= sub_wire3(48);
+	sub_wire2(14, 49)    <= sub_wire3(49);
+	sub_wire2(14, 50)    <= sub_wire3(50);
+	sub_wire2(14, 51)    <= sub_wire3(51);
+	sub_wire2(14, 52)    <= sub_wire3(52);
+	sub_wire2(14, 53)    <= sub_wire3(53);
+	sub_wire2(14, 54)    <= sub_wire3(54);
+	sub_wire2(14, 55)    <= sub_wire3(55);
+	sub_wire2(14, 56)    <= sub_wire3(56);
+	sub_wire2(14, 57)    <= sub_wire3(57);
+	sub_wire2(14, 58)    <= sub_wire3(58);
+	sub_wire2(14, 59)    <= sub_wire3(59);
+	sub_wire2(14, 60)    <= sub_wire3(60);
+	sub_wire2(14, 61)    <= sub_wire3(61);
+	sub_wire2(14, 62)    <= sub_wire3(62);
+	sub_wire2(14, 63)    <= sub_wire3(63);
+	sub_wire2(14, 64)    <= sub_wire3(64);
+	sub_wire2(14, 65)    <= sub_wire3(65);
+	sub_wire2(14, 66)    <= sub_wire3(66);
+	sub_wire2(14, 67)    <= sub_wire3(67);
+	sub_wire2(14, 68)    <= sub_wire3(68);
+	sub_wire2(14, 69)    <= sub_wire3(69);
+	sub_wire2(14, 70)    <= sub_wire3(70);
+	sub_wire2(14, 71)    <= sub_wire3(71);
+	sub_wire2(14, 72)    <= sub_wire3(72);
+	sub_wire2(14, 73)    <= sub_wire3(73);
+	sub_wire2(14, 74)    <= sub_wire3(74);
+	sub_wire2(14, 75)    <= sub_wire3(75);
+	sub_wire2(14, 76)    <= sub_wire3(76);
+	sub_wire2(14, 77)    <= sub_wire3(77);
+	sub_wire2(14, 78)    <= sub_wire3(78);
+	sub_wire2(14, 79)    <= sub_wire3(79);
+	sub_wire2(14, 80)    <= sub_wire3(80);
+	sub_wire2(14, 81)    <= sub_wire3(81);
+	sub_wire2(14, 82)    <= sub_wire3(82);
+	sub_wire2(14, 83)    <= sub_wire3(83);
+	sub_wire2(14, 84)    <= sub_wire3(84);
+	sub_wire2(14, 85)    <= sub_wire3(85);
+	sub_wire2(14, 86)    <= sub_wire3(86);
+	sub_wire2(14, 87)    <= sub_wire3(87);
+	sub_wire2(14, 88)    <= sub_wire3(88);
+	sub_wire2(14, 89)    <= sub_wire3(89);
+	sub_wire2(14, 90)    <= sub_wire3(90);
+	sub_wire2(14, 91)    <= sub_wire3(91);
+	sub_wire2(14, 92)    <= sub_wire3(92);
+	sub_wire2(14, 93)    <= sub_wire3(93);
+	sub_wire2(14, 94)    <= sub_wire3(94);
+	sub_wire2(14, 95)    <= sub_wire3(95);
+	sub_wire2(14, 96)    <= sub_wire3(96);
+	sub_wire2(14, 97)    <= sub_wire3(97);
+	sub_wire2(14, 98)    <= sub_wire3(98);
+	sub_wire2(14, 99)    <= sub_wire3(99);
+	sub_wire2(14, 100)    <= sub_wire3(100);
+	sub_wire2(14, 101)    <= sub_wire3(101);
+	sub_wire2(14, 102)    <= sub_wire3(102);
+	sub_wire2(14, 103)    <= sub_wire3(103);
+	sub_wire2(14, 104)    <= sub_wire3(104);
+	sub_wire2(14, 105)    <= sub_wire3(105);
+	sub_wire2(14, 106)    <= sub_wire3(106);
+	sub_wire2(14, 107)    <= sub_wire3(107);
+	sub_wire2(14, 108)    <= sub_wire3(108);
+	sub_wire2(14, 109)    <= sub_wire3(109);
+	sub_wire2(14, 110)    <= sub_wire3(110);
+	sub_wire2(14, 111)    <= sub_wire3(111);
+	sub_wire2(14, 112)    <= sub_wire3(112);
+	sub_wire2(14, 113)    <= sub_wire3(113);
+	sub_wire2(14, 114)    <= sub_wire3(114);
+	sub_wire2(14, 115)    <= sub_wire3(115);
+	sub_wire2(14, 116)    <= sub_wire3(116);
+	sub_wire2(14, 117)    <= sub_wire3(117);
+	sub_wire2(14, 118)    <= sub_wire3(118);
+	sub_wire2(14, 119)    <= sub_wire3(119);
+	sub_wire2(14, 120)    <= sub_wire3(120);
+	sub_wire2(14, 121)    <= sub_wire3(121);
+	sub_wire2(14, 122)    <= sub_wire3(122);
+	sub_wire2(14, 123)    <= sub_wire3(123);
+	sub_wire2(14, 124)    <= sub_wire3(124);
+	sub_wire2(14, 125)    <= sub_wire3(125);
+	sub_wire2(14, 126)    <= sub_wire3(126);
+	sub_wire2(14, 127)    <= sub_wire3(127);
+	sub_wire2(13, 0)    <= sub_wire4(0);
+	sub_wire2(13, 1)    <= sub_wire4(1);
+	sub_wire2(13, 2)    <= sub_wire4(2);
+	sub_wire2(13, 3)    <= sub_wire4(3);
+	sub_wire2(13, 4)    <= sub_wire4(4);
+	sub_wire2(13, 5)    <= sub_wire4(5);
+	sub_wire2(13, 6)    <= sub_wire4(6);
+	sub_wire2(13, 7)    <= sub_wire4(7);
+	sub_wire2(13, 8)    <= sub_wire4(8);
+	sub_wire2(13, 9)    <= sub_wire4(9);
+	sub_wire2(13, 10)    <= sub_wire4(10);
+	sub_wire2(13, 11)    <= sub_wire4(11);
+	sub_wire2(13, 12)    <= sub_wire4(12);
+	sub_wire2(13, 13)    <= sub_wire4(13);
+	sub_wire2(13, 14)    <= sub_wire4(14);
+	sub_wire2(13, 15)    <= sub_wire4(15);
+	sub_wire2(13, 16)    <= sub_wire4(16);
+	sub_wire2(13, 17)    <= sub_wire4(17);
+	sub_wire2(13, 18)    <= sub_wire4(18);
+	sub_wire2(13, 19)    <= sub_wire4(19);
+	sub_wire2(13, 20)    <= sub_wire4(20);
+	sub_wire2(13, 21)    <= sub_wire4(21);
+	sub_wire2(13, 22)    <= sub_wire4(22);
+	sub_wire2(13, 23)    <= sub_wire4(23);
+	sub_wire2(13, 24)    <= sub_wire4(24);
+	sub_wire2(13, 25)    <= sub_wire4(25);
+	sub_wire2(13, 26)    <= sub_wire4(26);
+	sub_wire2(13, 27)    <= sub_wire4(27);
+	sub_wire2(13, 28)    <= sub_wire4(28);
+	sub_wire2(13, 29)    <= sub_wire4(29);
+	sub_wire2(13, 30)    <= sub_wire4(30);
+	sub_wire2(13, 31)    <= sub_wire4(31);
+	sub_wire2(13, 32)    <= sub_wire4(32);
+	sub_wire2(13, 33)    <= sub_wire4(33);
+	sub_wire2(13, 34)    <= sub_wire4(34);
+	sub_wire2(13, 35)    <= sub_wire4(35);
+	sub_wire2(13, 36)    <= sub_wire4(36);
+	sub_wire2(13, 37)    <= sub_wire4(37);
+	sub_wire2(13, 38)    <= sub_wire4(38);
+	sub_wire2(13, 39)    <= sub_wire4(39);
+	sub_wire2(13, 40)    <= sub_wire4(40);
+	sub_wire2(13, 41)    <= sub_wire4(41);
+	sub_wire2(13, 42)    <= sub_wire4(42);
+	sub_wire2(13, 43)    <= sub_wire4(43);
+	sub_wire2(13, 44)    <= sub_wire4(44);
+	sub_wire2(13, 45)    <= sub_wire4(45);
+	sub_wire2(13, 46)    <= sub_wire4(46);
+	sub_wire2(13, 47)    <= sub_wire4(47);
+	sub_wire2(13, 48)    <= sub_wire4(48);
+	sub_wire2(13, 49)    <= sub_wire4(49);
+	sub_wire2(13, 50)    <= sub_wire4(50);
+	sub_wire2(13, 51)    <= sub_wire4(51);
+	sub_wire2(13, 52)    <= sub_wire4(52);
+	sub_wire2(13, 53)    <= sub_wire4(53);
+	sub_wire2(13, 54)    <= sub_wire4(54);
+	sub_wire2(13, 55)    <= sub_wire4(55);
+	sub_wire2(13, 56)    <= sub_wire4(56);
+	sub_wire2(13, 57)    <= sub_wire4(57);
+	sub_wire2(13, 58)    <= sub_wire4(58);
+	sub_wire2(13, 59)    <= sub_wire4(59);
+	sub_wire2(13, 60)    <= sub_wire4(60);
+	sub_wire2(13, 61)    <= sub_wire4(61);
+	sub_wire2(13, 62)    <= sub_wire4(62);
+	sub_wire2(13, 63)    <= sub_wire4(63);
+	sub_wire2(13, 64)    <= sub_wire4(64);
+	sub_wire2(13, 65)    <= sub_wire4(65);
+	sub_wire2(13, 66)    <= sub_wire4(66);
+	sub_wire2(13, 67)    <= sub_wire4(67);
+	sub_wire2(13, 68)    <= sub_wire4(68);
+	sub_wire2(13, 69)    <= sub_wire4(69);
+	sub_wire2(13, 70)    <= sub_wire4(70);
+	sub_wire2(13, 71)    <= sub_wire4(71);
+	sub_wire2(13, 72)    <= sub_wire4(72);
+	sub_wire2(13, 73)    <= sub_wire4(73);
+	sub_wire2(13, 74)    <= sub_wire4(74);
+	sub_wire2(13, 75)    <= sub_wire4(75);
+	sub_wire2(13, 76)    <= sub_wire4(76);
+	sub_wire2(13, 77)    <= sub_wire4(77);
+	sub_wire2(13, 78)    <= sub_wire4(78);
+	sub_wire2(13, 79)    <= sub_wire4(79);
+	sub_wire2(13, 80)    <= sub_wire4(80);
+	sub_wire2(13, 81)    <= sub_wire4(81);
+	sub_wire2(13, 82)    <= sub_wire4(82);
+	sub_wire2(13, 83)    <= sub_wire4(83);
+	sub_wire2(13, 84)    <= sub_wire4(84);
+	sub_wire2(13, 85)    <= sub_wire4(85);
+	sub_wire2(13, 86)    <= sub_wire4(86);
+	sub_wire2(13, 87)    <= sub_wire4(87);
+	sub_wire2(13, 88)    <= sub_wire4(88);
+	sub_wire2(13, 89)    <= sub_wire4(89);
+	sub_wire2(13, 90)    <= sub_wire4(90);
+	sub_wire2(13, 91)    <= sub_wire4(91);
+	sub_wire2(13, 92)    <= sub_wire4(92);
+	sub_wire2(13, 93)    <= sub_wire4(93);
+	sub_wire2(13, 94)    <= sub_wire4(94);
+	sub_wire2(13, 95)    <= sub_wire4(95);
+	sub_wire2(13, 96)    <= sub_wire4(96);
+	sub_wire2(13, 97)    <= sub_wire4(97);
+	sub_wire2(13, 98)    <= sub_wire4(98);
+	sub_wire2(13, 99)    <= sub_wire4(99);
+	sub_wire2(13, 100)    <= sub_wire4(100);
+	sub_wire2(13, 101)    <= sub_wire4(101);
+	sub_wire2(13, 102)    <= sub_wire4(102);
+	sub_wire2(13, 103)    <= sub_wire4(103);
+	sub_wire2(13, 104)    <= sub_wire4(104);
+	sub_wire2(13, 105)    <= sub_wire4(105);
+	sub_wire2(13, 106)    <= sub_wire4(106);
+	sub_wire2(13, 107)    <= sub_wire4(107);
+	sub_wire2(13, 108)    <= sub_wire4(108);
+	sub_wire2(13, 109)    <= sub_wire4(109);
+	sub_wire2(13, 110)    <= sub_wire4(110);
+	sub_wire2(13, 111)    <= sub_wire4(111);
+	sub_wire2(13, 112)    <= sub_wire4(112);
+	sub_wire2(13, 113)    <= sub_wire4(113);
+	sub_wire2(13, 114)    <= sub_wire4(114);
+	sub_wire2(13, 115)    <= sub_wire4(115);
+	sub_wire2(13, 116)    <= sub_wire4(116);
+	sub_wire2(13, 117)    <= sub_wire4(117);
+	sub_wire2(13, 118)    <= sub_wire4(118);
+	sub_wire2(13, 119)    <= sub_wire4(119);
+	sub_wire2(13, 120)    <= sub_wire4(120);
+	sub_wire2(13, 121)    <= sub_wire4(121);
+	sub_wire2(13, 122)    <= sub_wire4(122);
+	sub_wire2(13, 123)    <= sub_wire4(123);
+	sub_wire2(13, 124)    <= sub_wire4(124);
+	sub_wire2(13, 125)    <= sub_wire4(125);
+	sub_wire2(13, 126)    <= sub_wire4(126);
+	sub_wire2(13, 127)    <= sub_wire4(127);
+	sub_wire2(12, 0)    <= sub_wire5(0);
+	sub_wire2(12, 1)    <= sub_wire5(1);
+	sub_wire2(12, 2)    <= sub_wire5(2);
+	sub_wire2(12, 3)    <= sub_wire5(3);
+	sub_wire2(12, 4)    <= sub_wire5(4);
+	sub_wire2(12, 5)    <= sub_wire5(5);
+	sub_wire2(12, 6)    <= sub_wire5(6);
+	sub_wire2(12, 7)    <= sub_wire5(7);
+	sub_wire2(12, 8)    <= sub_wire5(8);
+	sub_wire2(12, 9)    <= sub_wire5(9);
+	sub_wire2(12, 10)    <= sub_wire5(10);
+	sub_wire2(12, 11)    <= sub_wire5(11);
+	sub_wire2(12, 12)    <= sub_wire5(12);
+	sub_wire2(12, 13)    <= sub_wire5(13);
+	sub_wire2(12, 14)    <= sub_wire5(14);
+	sub_wire2(12, 15)    <= sub_wire5(15);
+	sub_wire2(12, 16)    <= sub_wire5(16);
+	sub_wire2(12, 17)    <= sub_wire5(17);
+	sub_wire2(12, 18)    <= sub_wire5(18);
+	sub_wire2(12, 19)    <= sub_wire5(19);
+	sub_wire2(12, 20)    <= sub_wire5(20);
+	sub_wire2(12, 21)    <= sub_wire5(21);
+	sub_wire2(12, 22)    <= sub_wire5(22);
+	sub_wire2(12, 23)    <= sub_wire5(23);
+	sub_wire2(12, 24)    <= sub_wire5(24);
+	sub_wire2(12, 25)    <= sub_wire5(25);
+	sub_wire2(12, 26)    <= sub_wire5(26);
+	sub_wire2(12, 27)    <= sub_wire5(27);
+	sub_wire2(12, 28)    <= sub_wire5(28);
+	sub_wire2(12, 29)    <= sub_wire5(29);
+	sub_wire2(12, 30)    <= sub_wire5(30);
+	sub_wire2(12, 31)    <= sub_wire5(31);
+	sub_wire2(12, 32)    <= sub_wire5(32);
+	sub_wire2(12, 33)    <= sub_wire5(33);
+	sub_wire2(12, 34)    <= sub_wire5(34);
+	sub_wire2(12, 35)    <= sub_wire5(35);
+	sub_wire2(12, 36)    <= sub_wire5(36);
+	sub_wire2(12, 37)    <= sub_wire5(37);
+	sub_wire2(12, 38)    <= sub_wire5(38);
+	sub_wire2(12, 39)    <= sub_wire5(39);
+	sub_wire2(12, 40)    <= sub_wire5(40);
+	sub_wire2(12, 41)    <= sub_wire5(41);
+	sub_wire2(12, 42)    <= sub_wire5(42);
+	sub_wire2(12, 43)    <= sub_wire5(43);
+	sub_wire2(12, 44)    <= sub_wire5(44);
+	sub_wire2(12, 45)    <= sub_wire5(45);
+	sub_wire2(12, 46)    <= sub_wire5(46);
+	sub_wire2(12, 47)    <= sub_wire5(47);
+	sub_wire2(12, 48)    <= sub_wire5(48);
+	sub_wire2(12, 49)    <= sub_wire5(49);
+	sub_wire2(12, 50)    <= sub_wire5(50);
+	sub_wire2(12, 51)    <= sub_wire5(51);
+	sub_wire2(12, 52)    <= sub_wire5(52);
+	sub_wire2(12, 53)    <= sub_wire5(53);
+	sub_wire2(12, 54)    <= sub_wire5(54);
+	sub_wire2(12, 55)    <= sub_wire5(55);
+	sub_wire2(12, 56)    <= sub_wire5(56);
+	sub_wire2(12, 57)    <= sub_wire5(57);
+	sub_wire2(12, 58)    <= sub_wire5(58);
+	sub_wire2(12, 59)    <= sub_wire5(59);
+	sub_wire2(12, 60)    <= sub_wire5(60);
+	sub_wire2(12, 61)    <= sub_wire5(61);
+	sub_wire2(12, 62)    <= sub_wire5(62);
+	sub_wire2(12, 63)    <= sub_wire5(63);
+	sub_wire2(12, 64)    <= sub_wire5(64);
+	sub_wire2(12, 65)    <= sub_wire5(65);
+	sub_wire2(12, 66)    <= sub_wire5(66);
+	sub_wire2(12, 67)    <= sub_wire5(67);
+	sub_wire2(12, 68)    <= sub_wire5(68);
+	sub_wire2(12, 69)    <= sub_wire5(69);
+	sub_wire2(12, 70)    <= sub_wire5(70);
+	sub_wire2(12, 71)    <= sub_wire5(71);
+	sub_wire2(12, 72)    <= sub_wire5(72);
+	sub_wire2(12, 73)    <= sub_wire5(73);
+	sub_wire2(12, 74)    <= sub_wire5(74);
+	sub_wire2(12, 75)    <= sub_wire5(75);
+	sub_wire2(12, 76)    <= sub_wire5(76);
+	sub_wire2(12, 77)    <= sub_wire5(77);
+	sub_wire2(12, 78)    <= sub_wire5(78);
+	sub_wire2(12, 79)    <= sub_wire5(79);
+	sub_wire2(12, 80)    <= sub_wire5(80);
+	sub_wire2(12, 81)    <= sub_wire5(81);
+	sub_wire2(12, 82)    <= sub_wire5(82);
+	sub_wire2(12, 83)    <= sub_wire5(83);
+	sub_wire2(12, 84)    <= sub_wire5(84);
+	sub_wire2(12, 85)    <= sub_wire5(85);
+	sub_wire2(12, 86)    <= sub_wire5(86);
+	sub_wire2(12, 87)    <= sub_wire5(87);
+	sub_wire2(12, 88)    <= sub_wire5(88);
+	sub_wire2(12, 89)    <= sub_wire5(89);
+	sub_wire2(12, 90)    <= sub_wire5(90);
+	sub_wire2(12, 91)    <= sub_wire5(91);
+	sub_wire2(12, 92)    <= sub_wire5(92);
+	sub_wire2(12, 93)    <= sub_wire5(93);
+	sub_wire2(12, 94)    <= sub_wire5(94);
+	sub_wire2(12, 95)    <= sub_wire5(95);
+	sub_wire2(12, 96)    <= sub_wire5(96);
+	sub_wire2(12, 97)    <= sub_wire5(97);
+	sub_wire2(12, 98)    <= sub_wire5(98);
+	sub_wire2(12, 99)    <= sub_wire5(99);
+	sub_wire2(12, 100)    <= sub_wire5(100);
+	sub_wire2(12, 101)    <= sub_wire5(101);
+	sub_wire2(12, 102)    <= sub_wire5(102);
+	sub_wire2(12, 103)    <= sub_wire5(103);
+	sub_wire2(12, 104)    <= sub_wire5(104);
+	sub_wire2(12, 105)    <= sub_wire5(105);
+	sub_wire2(12, 106)    <= sub_wire5(106);
+	sub_wire2(12, 107)    <= sub_wire5(107);
+	sub_wire2(12, 108)    <= sub_wire5(108);
+	sub_wire2(12, 109)    <= sub_wire5(109);
+	sub_wire2(12, 110)    <= sub_wire5(110);
+	sub_wire2(12, 111)    <= sub_wire5(111);
+	sub_wire2(12, 112)    <= sub_wire5(112);
+	sub_wire2(12, 113)    <= sub_wire5(113);
+	sub_wire2(12, 114)    <= sub_wire5(114);
+	sub_wire2(12, 115)    <= sub_wire5(115);
+	sub_wire2(12, 116)    <= sub_wire5(116);
+	sub_wire2(12, 117)    <= sub_wire5(117);
+	sub_wire2(12, 118)    <= sub_wire5(118);
+	sub_wire2(12, 119)    <= sub_wire5(119);
+	sub_wire2(12, 120)    <= sub_wire5(120);
+	sub_wire2(12, 121)    <= sub_wire5(121);
+	sub_wire2(12, 122)    <= sub_wire5(122);
+	sub_wire2(12, 123)    <= sub_wire5(123);
+	sub_wire2(12, 124)    <= sub_wire5(124);
+	sub_wire2(12, 125)    <= sub_wire5(125);
+	sub_wire2(12, 126)    <= sub_wire5(126);
+	sub_wire2(12, 127)    <= sub_wire5(127);
+	sub_wire2(11, 0)    <= sub_wire6(0);
+	sub_wire2(11, 1)    <= sub_wire6(1);
+	sub_wire2(11, 2)    <= sub_wire6(2);
+	sub_wire2(11, 3)    <= sub_wire6(3);
+	sub_wire2(11, 4)    <= sub_wire6(4);
+	sub_wire2(11, 5)    <= sub_wire6(5);
+	sub_wire2(11, 6)    <= sub_wire6(6);
+	sub_wire2(11, 7)    <= sub_wire6(7);
+	sub_wire2(11, 8)    <= sub_wire6(8);
+	sub_wire2(11, 9)    <= sub_wire6(9);
+	sub_wire2(11, 10)    <= sub_wire6(10);
+	sub_wire2(11, 11)    <= sub_wire6(11);
+	sub_wire2(11, 12)    <= sub_wire6(12);
+	sub_wire2(11, 13)    <= sub_wire6(13);
+	sub_wire2(11, 14)    <= sub_wire6(14);
+	sub_wire2(11, 15)    <= sub_wire6(15);
+	sub_wire2(11, 16)    <= sub_wire6(16);
+	sub_wire2(11, 17)    <= sub_wire6(17);
+	sub_wire2(11, 18)    <= sub_wire6(18);
+	sub_wire2(11, 19)    <= sub_wire6(19);
+	sub_wire2(11, 20)    <= sub_wire6(20);
+	sub_wire2(11, 21)    <= sub_wire6(21);
+	sub_wire2(11, 22)    <= sub_wire6(22);
+	sub_wire2(11, 23)    <= sub_wire6(23);
+	sub_wire2(11, 24)    <= sub_wire6(24);
+	sub_wire2(11, 25)    <= sub_wire6(25);
+	sub_wire2(11, 26)    <= sub_wire6(26);
+	sub_wire2(11, 27)    <= sub_wire6(27);
+	sub_wire2(11, 28)    <= sub_wire6(28);
+	sub_wire2(11, 29)    <= sub_wire6(29);
+	sub_wire2(11, 30)    <= sub_wire6(30);
+	sub_wire2(11, 31)    <= sub_wire6(31);
+	sub_wire2(11, 32)    <= sub_wire6(32);
+	sub_wire2(11, 33)    <= sub_wire6(33);
+	sub_wire2(11, 34)    <= sub_wire6(34);
+	sub_wire2(11, 35)    <= sub_wire6(35);
+	sub_wire2(11, 36)    <= sub_wire6(36);
+	sub_wire2(11, 37)    <= sub_wire6(37);
+	sub_wire2(11, 38)    <= sub_wire6(38);
+	sub_wire2(11, 39)    <= sub_wire6(39);
+	sub_wire2(11, 40)    <= sub_wire6(40);
+	sub_wire2(11, 41)    <= sub_wire6(41);
+	sub_wire2(11, 42)    <= sub_wire6(42);
+	sub_wire2(11, 43)    <= sub_wire6(43);
+	sub_wire2(11, 44)    <= sub_wire6(44);
+	sub_wire2(11, 45)    <= sub_wire6(45);
+	sub_wire2(11, 46)    <= sub_wire6(46);
+	sub_wire2(11, 47)    <= sub_wire6(47);
+	sub_wire2(11, 48)    <= sub_wire6(48);
+	sub_wire2(11, 49)    <= sub_wire6(49);
+	sub_wire2(11, 50)    <= sub_wire6(50);
+	sub_wire2(11, 51)    <= sub_wire6(51);
+	sub_wire2(11, 52)    <= sub_wire6(52);
+	sub_wire2(11, 53)    <= sub_wire6(53);
+	sub_wire2(11, 54)    <= sub_wire6(54);
+	sub_wire2(11, 55)    <= sub_wire6(55);
+	sub_wire2(11, 56)    <= sub_wire6(56);
+	sub_wire2(11, 57)    <= sub_wire6(57);
+	sub_wire2(11, 58)    <= sub_wire6(58);
+	sub_wire2(11, 59)    <= sub_wire6(59);
+	sub_wire2(11, 60)    <= sub_wire6(60);
+	sub_wire2(11, 61)    <= sub_wire6(61);
+	sub_wire2(11, 62)    <= sub_wire6(62);
+	sub_wire2(11, 63)    <= sub_wire6(63);
+	sub_wire2(11, 64)    <= sub_wire6(64);
+	sub_wire2(11, 65)    <= sub_wire6(65);
+	sub_wire2(11, 66)    <= sub_wire6(66);
+	sub_wire2(11, 67)    <= sub_wire6(67);
+	sub_wire2(11, 68)    <= sub_wire6(68);
+	sub_wire2(11, 69)    <= sub_wire6(69);
+	sub_wire2(11, 70)    <= sub_wire6(70);
+	sub_wire2(11, 71)    <= sub_wire6(71);
+	sub_wire2(11, 72)    <= sub_wire6(72);
+	sub_wire2(11, 73)    <= sub_wire6(73);
+	sub_wire2(11, 74)    <= sub_wire6(74);
+	sub_wire2(11, 75)    <= sub_wire6(75);
+	sub_wire2(11, 76)    <= sub_wire6(76);
+	sub_wire2(11, 77)    <= sub_wire6(77);
+	sub_wire2(11, 78)    <= sub_wire6(78);
+	sub_wire2(11, 79)    <= sub_wire6(79);
+	sub_wire2(11, 80)    <= sub_wire6(80);
+	sub_wire2(11, 81)    <= sub_wire6(81);
+	sub_wire2(11, 82)    <= sub_wire6(82);
+	sub_wire2(11, 83)    <= sub_wire6(83);
+	sub_wire2(11, 84)    <= sub_wire6(84);
+	sub_wire2(11, 85)    <= sub_wire6(85);
+	sub_wire2(11, 86)    <= sub_wire6(86);
+	sub_wire2(11, 87)    <= sub_wire6(87);
+	sub_wire2(11, 88)    <= sub_wire6(88);
+	sub_wire2(11, 89)    <= sub_wire6(89);
+	sub_wire2(11, 90)    <= sub_wire6(90);
+	sub_wire2(11, 91)    <= sub_wire6(91);
+	sub_wire2(11, 92)    <= sub_wire6(92);
+	sub_wire2(11, 93)    <= sub_wire6(93);
+	sub_wire2(11, 94)    <= sub_wire6(94);
+	sub_wire2(11, 95)    <= sub_wire6(95);
+	sub_wire2(11, 96)    <= sub_wire6(96);
+	sub_wire2(11, 97)    <= sub_wire6(97);
+	sub_wire2(11, 98)    <= sub_wire6(98);
+	sub_wire2(11, 99)    <= sub_wire6(99);
+	sub_wire2(11, 100)    <= sub_wire6(100);
+	sub_wire2(11, 101)    <= sub_wire6(101);
+	sub_wire2(11, 102)    <= sub_wire6(102);
+	sub_wire2(11, 103)    <= sub_wire6(103);
+	sub_wire2(11, 104)    <= sub_wire6(104);
+	sub_wire2(11, 105)    <= sub_wire6(105);
+	sub_wire2(11, 106)    <= sub_wire6(106);
+	sub_wire2(11, 107)    <= sub_wire6(107);
+	sub_wire2(11, 108)    <= sub_wire6(108);
+	sub_wire2(11, 109)    <= sub_wire6(109);
+	sub_wire2(11, 110)    <= sub_wire6(110);
+	sub_wire2(11, 111)    <= sub_wire6(111);
+	sub_wire2(11, 112)    <= sub_wire6(112);
+	sub_wire2(11, 113)    <= sub_wire6(113);
+	sub_wire2(11, 114)    <= sub_wire6(114);
+	sub_wire2(11, 115)    <= sub_wire6(115);
+	sub_wire2(11, 116)    <= sub_wire6(116);
+	sub_wire2(11, 117)    <= sub_wire6(117);
+	sub_wire2(11, 118)    <= sub_wire6(118);
+	sub_wire2(11, 119)    <= sub_wire6(119);
+	sub_wire2(11, 120)    <= sub_wire6(120);
+	sub_wire2(11, 121)    <= sub_wire6(121);
+	sub_wire2(11, 122)    <= sub_wire6(122);
+	sub_wire2(11, 123)    <= sub_wire6(123);
+	sub_wire2(11, 124)    <= sub_wire6(124);
+	sub_wire2(11, 125)    <= sub_wire6(125);
+	sub_wire2(11, 126)    <= sub_wire6(126);
+	sub_wire2(11, 127)    <= sub_wire6(127);
+	sub_wire2(10, 0)    <= sub_wire7(0);
+	sub_wire2(10, 1)    <= sub_wire7(1);
+	sub_wire2(10, 2)    <= sub_wire7(2);
+	sub_wire2(10, 3)    <= sub_wire7(3);
+	sub_wire2(10, 4)    <= sub_wire7(4);
+	sub_wire2(10, 5)    <= sub_wire7(5);
+	sub_wire2(10, 6)    <= sub_wire7(6);
+	sub_wire2(10, 7)    <= sub_wire7(7);
+	sub_wire2(10, 8)    <= sub_wire7(8);
+	sub_wire2(10, 9)    <= sub_wire7(9);
+	sub_wire2(10, 10)    <= sub_wire7(10);
+	sub_wire2(10, 11)    <= sub_wire7(11);
+	sub_wire2(10, 12)    <= sub_wire7(12);
+	sub_wire2(10, 13)    <= sub_wire7(13);
+	sub_wire2(10, 14)    <= sub_wire7(14);
+	sub_wire2(10, 15)    <= sub_wire7(15);
+	sub_wire2(10, 16)    <= sub_wire7(16);
+	sub_wire2(10, 17)    <= sub_wire7(17);
+	sub_wire2(10, 18)    <= sub_wire7(18);
+	sub_wire2(10, 19)    <= sub_wire7(19);
+	sub_wire2(10, 20)    <= sub_wire7(20);
+	sub_wire2(10, 21)    <= sub_wire7(21);
+	sub_wire2(10, 22)    <= sub_wire7(22);
+	sub_wire2(10, 23)    <= sub_wire7(23);
+	sub_wire2(10, 24)    <= sub_wire7(24);
+	sub_wire2(10, 25)    <= sub_wire7(25);
+	sub_wire2(10, 26)    <= sub_wire7(26);
+	sub_wire2(10, 27)    <= sub_wire7(27);
+	sub_wire2(10, 28)    <= sub_wire7(28);
+	sub_wire2(10, 29)    <= sub_wire7(29);
+	sub_wire2(10, 30)    <= sub_wire7(30);
+	sub_wire2(10, 31)    <= sub_wire7(31);
+	sub_wire2(10, 32)    <= sub_wire7(32);
+	sub_wire2(10, 33)    <= sub_wire7(33);
+	sub_wire2(10, 34)    <= sub_wire7(34);
+	sub_wire2(10, 35)    <= sub_wire7(35);
+	sub_wire2(10, 36)    <= sub_wire7(36);
+	sub_wire2(10, 37)    <= sub_wire7(37);
+	sub_wire2(10, 38)    <= sub_wire7(38);
+	sub_wire2(10, 39)    <= sub_wire7(39);
+	sub_wire2(10, 40)    <= sub_wire7(40);
+	sub_wire2(10, 41)    <= sub_wire7(41);
+	sub_wire2(10, 42)    <= sub_wire7(42);
+	sub_wire2(10, 43)    <= sub_wire7(43);
+	sub_wire2(10, 44)    <= sub_wire7(44);
+	sub_wire2(10, 45)    <= sub_wire7(45);
+	sub_wire2(10, 46)    <= sub_wire7(46);
+	sub_wire2(10, 47)    <= sub_wire7(47);
+	sub_wire2(10, 48)    <= sub_wire7(48);
+	sub_wire2(10, 49)    <= sub_wire7(49);
+	sub_wire2(10, 50)    <= sub_wire7(50);
+	sub_wire2(10, 51)    <= sub_wire7(51);
+	sub_wire2(10, 52)    <= sub_wire7(52);
+	sub_wire2(10, 53)    <= sub_wire7(53);
+	sub_wire2(10, 54)    <= sub_wire7(54);
+	sub_wire2(10, 55)    <= sub_wire7(55);
+	sub_wire2(10, 56)    <= sub_wire7(56);
+	sub_wire2(10, 57)    <= sub_wire7(57);
+	sub_wire2(10, 58)    <= sub_wire7(58);
+	sub_wire2(10, 59)    <= sub_wire7(59);
+	sub_wire2(10, 60)    <= sub_wire7(60);
+	sub_wire2(10, 61)    <= sub_wire7(61);
+	sub_wire2(10, 62)    <= sub_wire7(62);
+	sub_wire2(10, 63)    <= sub_wire7(63);
+	sub_wire2(10, 64)    <= sub_wire7(64);
+	sub_wire2(10, 65)    <= sub_wire7(65);
+	sub_wire2(10, 66)    <= sub_wire7(66);
+	sub_wire2(10, 67)    <= sub_wire7(67);
+	sub_wire2(10, 68)    <= sub_wire7(68);
+	sub_wire2(10, 69)    <= sub_wire7(69);
+	sub_wire2(10, 70)    <= sub_wire7(70);
+	sub_wire2(10, 71)    <= sub_wire7(71);
+	sub_wire2(10, 72)    <= sub_wire7(72);
+	sub_wire2(10, 73)    <= sub_wire7(73);
+	sub_wire2(10, 74)    <= sub_wire7(74);
+	sub_wire2(10, 75)    <= sub_wire7(75);
+	sub_wire2(10, 76)    <= sub_wire7(76);
+	sub_wire2(10, 77)    <= sub_wire7(77);
+	sub_wire2(10, 78)    <= sub_wire7(78);
+	sub_wire2(10, 79)    <= sub_wire7(79);
+	sub_wire2(10, 80)    <= sub_wire7(80);
+	sub_wire2(10, 81)    <= sub_wire7(81);
+	sub_wire2(10, 82)    <= sub_wire7(82);
+	sub_wire2(10, 83)    <= sub_wire7(83);
+	sub_wire2(10, 84)    <= sub_wire7(84);
+	sub_wire2(10, 85)    <= sub_wire7(85);
+	sub_wire2(10, 86)    <= sub_wire7(86);
+	sub_wire2(10, 87)    <= sub_wire7(87);
+	sub_wire2(10, 88)    <= sub_wire7(88);
+	sub_wire2(10, 89)    <= sub_wire7(89);
+	sub_wire2(10, 90)    <= sub_wire7(90);
+	sub_wire2(10, 91)    <= sub_wire7(91);
+	sub_wire2(10, 92)    <= sub_wire7(92);
+	sub_wire2(10, 93)    <= sub_wire7(93);
+	sub_wire2(10, 94)    <= sub_wire7(94);
+	sub_wire2(10, 95)    <= sub_wire7(95);
+	sub_wire2(10, 96)    <= sub_wire7(96);
+	sub_wire2(10, 97)    <= sub_wire7(97);
+	sub_wire2(10, 98)    <= sub_wire7(98);
+	sub_wire2(10, 99)    <= sub_wire7(99);
+	sub_wire2(10, 100)    <= sub_wire7(100);
+	sub_wire2(10, 101)    <= sub_wire7(101);
+	sub_wire2(10, 102)    <= sub_wire7(102);
+	sub_wire2(10, 103)    <= sub_wire7(103);
+	sub_wire2(10, 104)    <= sub_wire7(104);
+	sub_wire2(10, 105)    <= sub_wire7(105);
+	sub_wire2(10, 106)    <= sub_wire7(106);
+	sub_wire2(10, 107)    <= sub_wire7(107);
+	sub_wire2(10, 108)    <= sub_wire7(108);
+	sub_wire2(10, 109)    <= sub_wire7(109);
+	sub_wire2(10, 110)    <= sub_wire7(110);
+	sub_wire2(10, 111)    <= sub_wire7(111);
+	sub_wire2(10, 112)    <= sub_wire7(112);
+	sub_wire2(10, 113)    <= sub_wire7(113);
+	sub_wire2(10, 114)    <= sub_wire7(114);
+	sub_wire2(10, 115)    <= sub_wire7(115);
+	sub_wire2(10, 116)    <= sub_wire7(116);
+	sub_wire2(10, 117)    <= sub_wire7(117);
+	sub_wire2(10, 118)    <= sub_wire7(118);
+	sub_wire2(10, 119)    <= sub_wire7(119);
+	sub_wire2(10, 120)    <= sub_wire7(120);
+	sub_wire2(10, 121)    <= sub_wire7(121);
+	sub_wire2(10, 122)    <= sub_wire7(122);
+	sub_wire2(10, 123)    <= sub_wire7(123);
+	sub_wire2(10, 124)    <= sub_wire7(124);
+	sub_wire2(10, 125)    <= sub_wire7(125);
+	sub_wire2(10, 126)    <= sub_wire7(126);
+	sub_wire2(10, 127)    <= sub_wire7(127);
+	sub_wire2(9, 0)    <= sub_wire8(0);
+	sub_wire2(9, 1)    <= sub_wire8(1);
+	sub_wire2(9, 2)    <= sub_wire8(2);
+	sub_wire2(9, 3)    <= sub_wire8(3);
+	sub_wire2(9, 4)    <= sub_wire8(4);
+	sub_wire2(9, 5)    <= sub_wire8(5);
+	sub_wire2(9, 6)    <= sub_wire8(6);
+	sub_wire2(9, 7)    <= sub_wire8(7);
+	sub_wire2(9, 8)    <= sub_wire8(8);
+	sub_wire2(9, 9)    <= sub_wire8(9);
+	sub_wire2(9, 10)    <= sub_wire8(10);
+	sub_wire2(9, 11)    <= sub_wire8(11);
+	sub_wire2(9, 12)    <= sub_wire8(12);
+	sub_wire2(9, 13)    <= sub_wire8(13);
+	sub_wire2(9, 14)    <= sub_wire8(14);
+	sub_wire2(9, 15)    <= sub_wire8(15);
+	sub_wire2(9, 16)    <= sub_wire8(16);
+	sub_wire2(9, 17)    <= sub_wire8(17);
+	sub_wire2(9, 18)    <= sub_wire8(18);
+	sub_wire2(9, 19)    <= sub_wire8(19);
+	sub_wire2(9, 20)    <= sub_wire8(20);
+	sub_wire2(9, 21)    <= sub_wire8(21);
+	sub_wire2(9, 22)    <= sub_wire8(22);
+	sub_wire2(9, 23)    <= sub_wire8(23);
+	sub_wire2(9, 24)    <= sub_wire8(24);
+	sub_wire2(9, 25)    <= sub_wire8(25);
+	sub_wire2(9, 26)    <= sub_wire8(26);
+	sub_wire2(9, 27)    <= sub_wire8(27);
+	sub_wire2(9, 28)    <= sub_wire8(28);
+	sub_wire2(9, 29)    <= sub_wire8(29);
+	sub_wire2(9, 30)    <= sub_wire8(30);
+	sub_wire2(9, 31)    <= sub_wire8(31);
+	sub_wire2(9, 32)    <= sub_wire8(32);
+	sub_wire2(9, 33)    <= sub_wire8(33);
+	sub_wire2(9, 34)    <= sub_wire8(34);
+	sub_wire2(9, 35)    <= sub_wire8(35);
+	sub_wire2(9, 36)    <= sub_wire8(36);
+	sub_wire2(9, 37)    <= sub_wire8(37);
+	sub_wire2(9, 38)    <= sub_wire8(38);
+	sub_wire2(9, 39)    <= sub_wire8(39);
+	sub_wire2(9, 40)    <= sub_wire8(40);
+	sub_wire2(9, 41)    <= sub_wire8(41);
+	sub_wire2(9, 42)    <= sub_wire8(42);
+	sub_wire2(9, 43)    <= sub_wire8(43);
+	sub_wire2(9, 44)    <= sub_wire8(44);
+	sub_wire2(9, 45)    <= sub_wire8(45);
+	sub_wire2(9, 46)    <= sub_wire8(46);
+	sub_wire2(9, 47)    <= sub_wire8(47);
+	sub_wire2(9, 48)    <= sub_wire8(48);
+	sub_wire2(9, 49)    <= sub_wire8(49);
+	sub_wire2(9, 50)    <= sub_wire8(50);
+	sub_wire2(9, 51)    <= sub_wire8(51);
+	sub_wire2(9, 52)    <= sub_wire8(52);
+	sub_wire2(9, 53)    <= sub_wire8(53);
+	sub_wire2(9, 54)    <= sub_wire8(54);
+	sub_wire2(9, 55)    <= sub_wire8(55);
+	sub_wire2(9, 56)    <= sub_wire8(56);
+	sub_wire2(9, 57)    <= sub_wire8(57);
+	sub_wire2(9, 58)    <= sub_wire8(58);
+	sub_wire2(9, 59)    <= sub_wire8(59);
+	sub_wire2(9, 60)    <= sub_wire8(60);
+	sub_wire2(9, 61)    <= sub_wire8(61);
+	sub_wire2(9, 62)    <= sub_wire8(62);
+	sub_wire2(9, 63)    <= sub_wire8(63);
+	sub_wire2(9, 64)    <= sub_wire8(64);
+	sub_wire2(9, 65)    <= sub_wire8(65);
+	sub_wire2(9, 66)    <= sub_wire8(66);
+	sub_wire2(9, 67)    <= sub_wire8(67);
+	sub_wire2(9, 68)    <= sub_wire8(68);
+	sub_wire2(9, 69)    <= sub_wire8(69);
+	sub_wire2(9, 70)    <= sub_wire8(70);
+	sub_wire2(9, 71)    <= sub_wire8(71);
+	sub_wire2(9, 72)    <= sub_wire8(72);
+	sub_wire2(9, 73)    <= sub_wire8(73);
+	sub_wire2(9, 74)    <= sub_wire8(74);
+	sub_wire2(9, 75)    <= sub_wire8(75);
+	sub_wire2(9, 76)    <= sub_wire8(76);
+	sub_wire2(9, 77)    <= sub_wire8(77);
+	sub_wire2(9, 78)    <= sub_wire8(78);
+	sub_wire2(9, 79)    <= sub_wire8(79);
+	sub_wire2(9, 80)    <= sub_wire8(80);
+	sub_wire2(9, 81)    <= sub_wire8(81);
+	sub_wire2(9, 82)    <= sub_wire8(82);
+	sub_wire2(9, 83)    <= sub_wire8(83);
+	sub_wire2(9, 84)    <= sub_wire8(84);
+	sub_wire2(9, 85)    <= sub_wire8(85);
+	sub_wire2(9, 86)    <= sub_wire8(86);
+	sub_wire2(9, 87)    <= sub_wire8(87);
+	sub_wire2(9, 88)    <= sub_wire8(88);
+	sub_wire2(9, 89)    <= sub_wire8(89);
+	sub_wire2(9, 90)    <= sub_wire8(90);
+	sub_wire2(9, 91)    <= sub_wire8(91);
+	sub_wire2(9, 92)    <= sub_wire8(92);
+	sub_wire2(9, 93)    <= sub_wire8(93);
+	sub_wire2(9, 94)    <= sub_wire8(94);
+	sub_wire2(9, 95)    <= sub_wire8(95);
+	sub_wire2(9, 96)    <= sub_wire8(96);
+	sub_wire2(9, 97)    <= sub_wire8(97);
+	sub_wire2(9, 98)    <= sub_wire8(98);
+	sub_wire2(9, 99)    <= sub_wire8(99);
+	sub_wire2(9, 100)    <= sub_wire8(100);
+	sub_wire2(9, 101)    <= sub_wire8(101);
+	sub_wire2(9, 102)    <= sub_wire8(102);
+	sub_wire2(9, 103)    <= sub_wire8(103);
+	sub_wire2(9, 104)    <= sub_wire8(104);
+	sub_wire2(9, 105)    <= sub_wire8(105);
+	sub_wire2(9, 106)    <= sub_wire8(106);
+	sub_wire2(9, 107)    <= sub_wire8(107);
+	sub_wire2(9, 108)    <= sub_wire8(108);
+	sub_wire2(9, 109)    <= sub_wire8(109);
+	sub_wire2(9, 110)    <= sub_wire8(110);
+	sub_wire2(9, 111)    <= sub_wire8(111);
+	sub_wire2(9, 112)    <= sub_wire8(112);
+	sub_wire2(9, 113)    <= sub_wire8(113);
+	sub_wire2(9, 114)    <= sub_wire8(114);
+	sub_wire2(9, 115)    <= sub_wire8(115);
+	sub_wire2(9, 116)    <= sub_wire8(116);
+	sub_wire2(9, 117)    <= sub_wire8(117);
+	sub_wire2(9, 118)    <= sub_wire8(118);
+	sub_wire2(9, 119)    <= sub_wire8(119);
+	sub_wire2(9, 120)    <= sub_wire8(120);
+	sub_wire2(9, 121)    <= sub_wire8(121);
+	sub_wire2(9, 122)    <= sub_wire8(122);
+	sub_wire2(9, 123)    <= sub_wire8(123);
+	sub_wire2(9, 124)    <= sub_wire8(124);
+	sub_wire2(9, 125)    <= sub_wire8(125);
+	sub_wire2(9, 126)    <= sub_wire8(126);
+	sub_wire2(9, 127)    <= sub_wire8(127);
+	sub_wire2(8, 0)    <= sub_wire9(0);
+	sub_wire2(8, 1)    <= sub_wire9(1);
+	sub_wire2(8, 2)    <= sub_wire9(2);
+	sub_wire2(8, 3)    <= sub_wire9(3);
+	sub_wire2(8, 4)    <= sub_wire9(4);
+	sub_wire2(8, 5)    <= sub_wire9(5);
+	sub_wire2(8, 6)    <= sub_wire9(6);
+	sub_wire2(8, 7)    <= sub_wire9(7);
+	sub_wire2(8, 8)    <= sub_wire9(8);
+	sub_wire2(8, 9)    <= sub_wire9(9);
+	sub_wire2(8, 10)    <= sub_wire9(10);
+	sub_wire2(8, 11)    <= sub_wire9(11);
+	sub_wire2(8, 12)    <= sub_wire9(12);
+	sub_wire2(8, 13)    <= sub_wire9(13);
+	sub_wire2(8, 14)    <= sub_wire9(14);
+	sub_wire2(8, 15)    <= sub_wire9(15);
+	sub_wire2(8, 16)    <= sub_wire9(16);
+	sub_wire2(8, 17)    <= sub_wire9(17);
+	sub_wire2(8, 18)    <= sub_wire9(18);
+	sub_wire2(8, 19)    <= sub_wire9(19);
+	sub_wire2(8, 20)    <= sub_wire9(20);
+	sub_wire2(8, 21)    <= sub_wire9(21);
+	sub_wire2(8, 22)    <= sub_wire9(22);
+	sub_wire2(8, 23)    <= sub_wire9(23);
+	sub_wire2(8, 24)    <= sub_wire9(24);
+	sub_wire2(8, 25)    <= sub_wire9(25);
+	sub_wire2(8, 26)    <= sub_wire9(26);
+	sub_wire2(8, 27)    <= sub_wire9(27);
+	sub_wire2(8, 28)    <= sub_wire9(28);
+	sub_wire2(8, 29)    <= sub_wire9(29);
+	sub_wire2(8, 30)    <= sub_wire9(30);
+	sub_wire2(8, 31)    <= sub_wire9(31);
+	sub_wire2(8, 32)    <= sub_wire9(32);
+	sub_wire2(8, 33)    <= sub_wire9(33);
+	sub_wire2(8, 34)    <= sub_wire9(34);
+	sub_wire2(8, 35)    <= sub_wire9(35);
+	sub_wire2(8, 36)    <= sub_wire9(36);
+	sub_wire2(8, 37)    <= sub_wire9(37);
+	sub_wire2(8, 38)    <= sub_wire9(38);
+	sub_wire2(8, 39)    <= sub_wire9(39);
+	sub_wire2(8, 40)    <= sub_wire9(40);
+	sub_wire2(8, 41)    <= sub_wire9(41);
+	sub_wire2(8, 42)    <= sub_wire9(42);
+	sub_wire2(8, 43)    <= sub_wire9(43);
+	sub_wire2(8, 44)    <= sub_wire9(44);
+	sub_wire2(8, 45)    <= sub_wire9(45);
+	sub_wire2(8, 46)    <= sub_wire9(46);
+	sub_wire2(8, 47)    <= sub_wire9(47);
+	sub_wire2(8, 48)    <= sub_wire9(48);
+	sub_wire2(8, 49)    <= sub_wire9(49);
+	sub_wire2(8, 50)    <= sub_wire9(50);
+	sub_wire2(8, 51)    <= sub_wire9(51);
+	sub_wire2(8, 52)    <= sub_wire9(52);
+	sub_wire2(8, 53)    <= sub_wire9(53);
+	sub_wire2(8, 54)    <= sub_wire9(54);
+	sub_wire2(8, 55)    <= sub_wire9(55);
+	sub_wire2(8, 56)    <= sub_wire9(56);
+	sub_wire2(8, 57)    <= sub_wire9(57);
+	sub_wire2(8, 58)    <= sub_wire9(58);
+	sub_wire2(8, 59)    <= sub_wire9(59);
+	sub_wire2(8, 60)    <= sub_wire9(60);
+	sub_wire2(8, 61)    <= sub_wire9(61);
+	sub_wire2(8, 62)    <= sub_wire9(62);
+	sub_wire2(8, 63)    <= sub_wire9(63);
+	sub_wire2(8, 64)    <= sub_wire9(64);
+	sub_wire2(8, 65)    <= sub_wire9(65);
+	sub_wire2(8, 66)    <= sub_wire9(66);
+	sub_wire2(8, 67)    <= sub_wire9(67);
+	sub_wire2(8, 68)    <= sub_wire9(68);
+	sub_wire2(8, 69)    <= sub_wire9(69);
+	sub_wire2(8, 70)    <= sub_wire9(70);
+	sub_wire2(8, 71)    <= sub_wire9(71);
+	sub_wire2(8, 72)    <= sub_wire9(72);
+	sub_wire2(8, 73)    <= sub_wire9(73);
+	sub_wire2(8, 74)    <= sub_wire9(74);
+	sub_wire2(8, 75)    <= sub_wire9(75);
+	sub_wire2(8, 76)    <= sub_wire9(76);
+	sub_wire2(8, 77)    <= sub_wire9(77);
+	sub_wire2(8, 78)    <= sub_wire9(78);
+	sub_wire2(8, 79)    <= sub_wire9(79);
+	sub_wire2(8, 80)    <= sub_wire9(80);
+	sub_wire2(8, 81)    <= sub_wire9(81);
+	sub_wire2(8, 82)    <= sub_wire9(82);
+	sub_wire2(8, 83)    <= sub_wire9(83);
+	sub_wire2(8, 84)    <= sub_wire9(84);
+	sub_wire2(8, 85)    <= sub_wire9(85);
+	sub_wire2(8, 86)    <= sub_wire9(86);
+	sub_wire2(8, 87)    <= sub_wire9(87);
+	sub_wire2(8, 88)    <= sub_wire9(88);
+	sub_wire2(8, 89)    <= sub_wire9(89);
+	sub_wire2(8, 90)    <= sub_wire9(90);
+	sub_wire2(8, 91)    <= sub_wire9(91);
+	sub_wire2(8, 92)    <= sub_wire9(92);
+	sub_wire2(8, 93)    <= sub_wire9(93);
+	sub_wire2(8, 94)    <= sub_wire9(94);
+	sub_wire2(8, 95)    <= sub_wire9(95);
+	sub_wire2(8, 96)    <= sub_wire9(96);
+	sub_wire2(8, 97)    <= sub_wire9(97);
+	sub_wire2(8, 98)    <= sub_wire9(98);
+	sub_wire2(8, 99)    <= sub_wire9(99);
+	sub_wire2(8, 100)    <= sub_wire9(100);
+	sub_wire2(8, 101)    <= sub_wire9(101);
+	sub_wire2(8, 102)    <= sub_wire9(102);
+	sub_wire2(8, 103)    <= sub_wire9(103);
+	sub_wire2(8, 104)    <= sub_wire9(104);
+	sub_wire2(8, 105)    <= sub_wire9(105);
+	sub_wire2(8, 106)    <= sub_wire9(106);
+	sub_wire2(8, 107)    <= sub_wire9(107);
+	sub_wire2(8, 108)    <= sub_wire9(108);
+	sub_wire2(8, 109)    <= sub_wire9(109);
+	sub_wire2(8, 110)    <= sub_wire9(110);
+	sub_wire2(8, 111)    <= sub_wire9(111);
+	sub_wire2(8, 112)    <= sub_wire9(112);
+	sub_wire2(8, 113)    <= sub_wire9(113);
+	sub_wire2(8, 114)    <= sub_wire9(114);
+	sub_wire2(8, 115)    <= sub_wire9(115);
+	sub_wire2(8, 116)    <= sub_wire9(116);
+	sub_wire2(8, 117)    <= sub_wire9(117);
+	sub_wire2(8, 118)    <= sub_wire9(118);
+	sub_wire2(8, 119)    <= sub_wire9(119);
+	sub_wire2(8, 120)    <= sub_wire9(120);
+	sub_wire2(8, 121)    <= sub_wire9(121);
+	sub_wire2(8, 122)    <= sub_wire9(122);
+	sub_wire2(8, 123)    <= sub_wire9(123);
+	sub_wire2(8, 124)    <= sub_wire9(124);
+	sub_wire2(8, 125)    <= sub_wire9(125);
+	sub_wire2(8, 126)    <= sub_wire9(126);
+	sub_wire2(8, 127)    <= sub_wire9(127);
+	sub_wire2(7, 0)    <= sub_wire10(0);
+	sub_wire2(7, 1)    <= sub_wire10(1);
+	sub_wire2(7, 2)    <= sub_wire10(2);
+	sub_wire2(7, 3)    <= sub_wire10(3);
+	sub_wire2(7, 4)    <= sub_wire10(4);
+	sub_wire2(7, 5)    <= sub_wire10(5);
+	sub_wire2(7, 6)    <= sub_wire10(6);
+	sub_wire2(7, 7)    <= sub_wire10(7);
+	sub_wire2(7, 8)    <= sub_wire10(8);
+	sub_wire2(7, 9)    <= sub_wire10(9);
+	sub_wire2(7, 10)    <= sub_wire10(10);
+	sub_wire2(7, 11)    <= sub_wire10(11);
+	sub_wire2(7, 12)    <= sub_wire10(12);
+	sub_wire2(7, 13)    <= sub_wire10(13);
+	sub_wire2(7, 14)    <= sub_wire10(14);
+	sub_wire2(7, 15)    <= sub_wire10(15);
+	sub_wire2(7, 16)    <= sub_wire10(16);
+	sub_wire2(7, 17)    <= sub_wire10(17);
+	sub_wire2(7, 18)    <= sub_wire10(18);
+	sub_wire2(7, 19)    <= sub_wire10(19);
+	sub_wire2(7, 20)    <= sub_wire10(20);
+	sub_wire2(7, 21)    <= sub_wire10(21);
+	sub_wire2(7, 22)    <= sub_wire10(22);
+	sub_wire2(7, 23)    <= sub_wire10(23);
+	sub_wire2(7, 24)    <= sub_wire10(24);
+	sub_wire2(7, 25)    <= sub_wire10(25);
+	sub_wire2(7, 26)    <= sub_wire10(26);
+	sub_wire2(7, 27)    <= sub_wire10(27);
+	sub_wire2(7, 28)    <= sub_wire10(28);
+	sub_wire2(7, 29)    <= sub_wire10(29);
+	sub_wire2(7, 30)    <= sub_wire10(30);
+	sub_wire2(7, 31)    <= sub_wire10(31);
+	sub_wire2(7, 32)    <= sub_wire10(32);
+	sub_wire2(7, 33)    <= sub_wire10(33);
+	sub_wire2(7, 34)    <= sub_wire10(34);
+	sub_wire2(7, 35)    <= sub_wire10(35);
+	sub_wire2(7, 36)    <= sub_wire10(36);
+	sub_wire2(7, 37)    <= sub_wire10(37);
+	sub_wire2(7, 38)    <= sub_wire10(38);
+	sub_wire2(7, 39)    <= sub_wire10(39);
+	sub_wire2(7, 40)    <= sub_wire10(40);
+	sub_wire2(7, 41)    <= sub_wire10(41);
+	sub_wire2(7, 42)    <= sub_wire10(42);
+	sub_wire2(7, 43)    <= sub_wire10(43);
+	sub_wire2(7, 44)    <= sub_wire10(44);
+	sub_wire2(7, 45)    <= sub_wire10(45);
+	sub_wire2(7, 46)    <= sub_wire10(46);
+	sub_wire2(7, 47)    <= sub_wire10(47);
+	sub_wire2(7, 48)    <= sub_wire10(48);
+	sub_wire2(7, 49)    <= sub_wire10(49);
+	sub_wire2(7, 50)    <= sub_wire10(50);
+	sub_wire2(7, 51)    <= sub_wire10(51);
+	sub_wire2(7, 52)    <= sub_wire10(52);
+	sub_wire2(7, 53)    <= sub_wire10(53);
+	sub_wire2(7, 54)    <= sub_wire10(54);
+	sub_wire2(7, 55)    <= sub_wire10(55);
+	sub_wire2(7, 56)    <= sub_wire10(56);
+	sub_wire2(7, 57)    <= sub_wire10(57);
+	sub_wire2(7, 58)    <= sub_wire10(58);
+	sub_wire2(7, 59)    <= sub_wire10(59);
+	sub_wire2(7, 60)    <= sub_wire10(60);
+	sub_wire2(7, 61)    <= sub_wire10(61);
+	sub_wire2(7, 62)    <= sub_wire10(62);
+	sub_wire2(7, 63)    <= sub_wire10(63);
+	sub_wire2(7, 64)    <= sub_wire10(64);
+	sub_wire2(7, 65)    <= sub_wire10(65);
+	sub_wire2(7, 66)    <= sub_wire10(66);
+	sub_wire2(7, 67)    <= sub_wire10(67);
+	sub_wire2(7, 68)    <= sub_wire10(68);
+	sub_wire2(7, 69)    <= sub_wire10(69);
+	sub_wire2(7, 70)    <= sub_wire10(70);
+	sub_wire2(7, 71)    <= sub_wire10(71);
+	sub_wire2(7, 72)    <= sub_wire10(72);
+	sub_wire2(7, 73)    <= sub_wire10(73);
+	sub_wire2(7, 74)    <= sub_wire10(74);
+	sub_wire2(7, 75)    <= sub_wire10(75);
+	sub_wire2(7, 76)    <= sub_wire10(76);
+	sub_wire2(7, 77)    <= sub_wire10(77);
+	sub_wire2(7, 78)    <= sub_wire10(78);
+	sub_wire2(7, 79)    <= sub_wire10(79);
+	sub_wire2(7, 80)    <= sub_wire10(80);
+	sub_wire2(7, 81)    <= sub_wire10(81);
+	sub_wire2(7, 82)    <= sub_wire10(82);
+	sub_wire2(7, 83)    <= sub_wire10(83);
+	sub_wire2(7, 84)    <= sub_wire10(84);
+	sub_wire2(7, 85)    <= sub_wire10(85);
+	sub_wire2(7, 86)    <= sub_wire10(86);
+	sub_wire2(7, 87)    <= sub_wire10(87);
+	sub_wire2(7, 88)    <= sub_wire10(88);
+	sub_wire2(7, 89)    <= sub_wire10(89);
+	sub_wire2(7, 90)    <= sub_wire10(90);
+	sub_wire2(7, 91)    <= sub_wire10(91);
+	sub_wire2(7, 92)    <= sub_wire10(92);
+	sub_wire2(7, 93)    <= sub_wire10(93);
+	sub_wire2(7, 94)    <= sub_wire10(94);
+	sub_wire2(7, 95)    <= sub_wire10(95);
+	sub_wire2(7, 96)    <= sub_wire10(96);
+	sub_wire2(7, 97)    <= sub_wire10(97);
+	sub_wire2(7, 98)    <= sub_wire10(98);
+	sub_wire2(7, 99)    <= sub_wire10(99);
+	sub_wire2(7, 100)    <= sub_wire10(100);
+	sub_wire2(7, 101)    <= sub_wire10(101);
+	sub_wire2(7, 102)    <= sub_wire10(102);
+	sub_wire2(7, 103)    <= sub_wire10(103);
+	sub_wire2(7, 104)    <= sub_wire10(104);
+	sub_wire2(7, 105)    <= sub_wire10(105);
+	sub_wire2(7, 106)    <= sub_wire10(106);
+	sub_wire2(7, 107)    <= sub_wire10(107);
+	sub_wire2(7, 108)    <= sub_wire10(108);
+	sub_wire2(7, 109)    <= sub_wire10(109);
+	sub_wire2(7, 110)    <= sub_wire10(110);
+	sub_wire2(7, 111)    <= sub_wire10(111);
+	sub_wire2(7, 112)    <= sub_wire10(112);
+	sub_wire2(7, 113)    <= sub_wire10(113);
+	sub_wire2(7, 114)    <= sub_wire10(114);
+	sub_wire2(7, 115)    <= sub_wire10(115);
+	sub_wire2(7, 116)    <= sub_wire10(116);
+	sub_wire2(7, 117)    <= sub_wire10(117);
+	sub_wire2(7, 118)    <= sub_wire10(118);
+	sub_wire2(7, 119)    <= sub_wire10(119);
+	sub_wire2(7, 120)    <= sub_wire10(120);
+	sub_wire2(7, 121)    <= sub_wire10(121);
+	sub_wire2(7, 122)    <= sub_wire10(122);
+	sub_wire2(7, 123)    <= sub_wire10(123);
+	sub_wire2(7, 124)    <= sub_wire10(124);
+	sub_wire2(7, 125)    <= sub_wire10(125);
+	sub_wire2(7, 126)    <= sub_wire10(126);
+	sub_wire2(7, 127)    <= sub_wire10(127);
+	sub_wire2(6, 0)    <= sub_wire11(0);
+	sub_wire2(6, 1)    <= sub_wire11(1);
+	sub_wire2(6, 2)    <= sub_wire11(2);
+	sub_wire2(6, 3)    <= sub_wire11(3);
+	sub_wire2(6, 4)    <= sub_wire11(4);
+	sub_wire2(6, 5)    <= sub_wire11(5);
+	sub_wire2(6, 6)    <= sub_wire11(6);
+	sub_wire2(6, 7)    <= sub_wire11(7);
+	sub_wire2(6, 8)    <= sub_wire11(8);
+	sub_wire2(6, 9)    <= sub_wire11(9);
+	sub_wire2(6, 10)    <= sub_wire11(10);
+	sub_wire2(6, 11)    <= sub_wire11(11);
+	sub_wire2(6, 12)    <= sub_wire11(12);
+	sub_wire2(6, 13)    <= sub_wire11(13);
+	sub_wire2(6, 14)    <= sub_wire11(14);
+	sub_wire2(6, 15)    <= sub_wire11(15);
+	sub_wire2(6, 16)    <= sub_wire11(16);
+	sub_wire2(6, 17)    <= sub_wire11(17);
+	sub_wire2(6, 18)    <= sub_wire11(18);
+	sub_wire2(6, 19)    <= sub_wire11(19);
+	sub_wire2(6, 20)    <= sub_wire11(20);
+	sub_wire2(6, 21)    <= sub_wire11(21);
+	sub_wire2(6, 22)    <= sub_wire11(22);
+	sub_wire2(6, 23)    <= sub_wire11(23);
+	sub_wire2(6, 24)    <= sub_wire11(24);
+	sub_wire2(6, 25)    <= sub_wire11(25);
+	sub_wire2(6, 26)    <= sub_wire11(26);
+	sub_wire2(6, 27)    <= sub_wire11(27);
+	sub_wire2(6, 28)    <= sub_wire11(28);
+	sub_wire2(6, 29)    <= sub_wire11(29);
+	sub_wire2(6, 30)    <= sub_wire11(30);
+	sub_wire2(6, 31)    <= sub_wire11(31);
+	sub_wire2(6, 32)    <= sub_wire11(32);
+	sub_wire2(6, 33)    <= sub_wire11(33);
+	sub_wire2(6, 34)    <= sub_wire11(34);
+	sub_wire2(6, 35)    <= sub_wire11(35);
+	sub_wire2(6, 36)    <= sub_wire11(36);
+	sub_wire2(6, 37)    <= sub_wire11(37);
+	sub_wire2(6, 38)    <= sub_wire11(38);
+	sub_wire2(6, 39)    <= sub_wire11(39);
+	sub_wire2(6, 40)    <= sub_wire11(40);
+	sub_wire2(6, 41)    <= sub_wire11(41);
+	sub_wire2(6, 42)    <= sub_wire11(42);
+	sub_wire2(6, 43)    <= sub_wire11(43);
+	sub_wire2(6, 44)    <= sub_wire11(44);
+	sub_wire2(6, 45)    <= sub_wire11(45);
+	sub_wire2(6, 46)    <= sub_wire11(46);
+	sub_wire2(6, 47)    <= sub_wire11(47);
+	sub_wire2(6, 48)    <= sub_wire11(48);
+	sub_wire2(6, 49)    <= sub_wire11(49);
+	sub_wire2(6, 50)    <= sub_wire11(50);
+	sub_wire2(6, 51)    <= sub_wire11(51);
+	sub_wire2(6, 52)    <= sub_wire11(52);
+	sub_wire2(6, 53)    <= sub_wire11(53);
+	sub_wire2(6, 54)    <= sub_wire11(54);
+	sub_wire2(6, 55)    <= sub_wire11(55);
+	sub_wire2(6, 56)    <= sub_wire11(56);
+	sub_wire2(6, 57)    <= sub_wire11(57);
+	sub_wire2(6, 58)    <= sub_wire11(58);
+	sub_wire2(6, 59)    <= sub_wire11(59);
+	sub_wire2(6, 60)    <= sub_wire11(60);
+	sub_wire2(6, 61)    <= sub_wire11(61);
+	sub_wire2(6, 62)    <= sub_wire11(62);
+	sub_wire2(6, 63)    <= sub_wire11(63);
+	sub_wire2(6, 64)    <= sub_wire11(64);
+	sub_wire2(6, 65)    <= sub_wire11(65);
+	sub_wire2(6, 66)    <= sub_wire11(66);
+	sub_wire2(6, 67)    <= sub_wire11(67);
+	sub_wire2(6, 68)    <= sub_wire11(68);
+	sub_wire2(6, 69)    <= sub_wire11(69);
+	sub_wire2(6, 70)    <= sub_wire11(70);
+	sub_wire2(6, 71)    <= sub_wire11(71);
+	sub_wire2(6, 72)    <= sub_wire11(72);
+	sub_wire2(6, 73)    <= sub_wire11(73);
+	sub_wire2(6, 74)    <= sub_wire11(74);
+	sub_wire2(6, 75)    <= sub_wire11(75);
+	sub_wire2(6, 76)    <= sub_wire11(76);
+	sub_wire2(6, 77)    <= sub_wire11(77);
+	sub_wire2(6, 78)    <= sub_wire11(78);
+	sub_wire2(6, 79)    <= sub_wire11(79);
+	sub_wire2(6, 80)    <= sub_wire11(80);
+	sub_wire2(6, 81)    <= sub_wire11(81);
+	sub_wire2(6, 82)    <= sub_wire11(82);
+	sub_wire2(6, 83)    <= sub_wire11(83);
+	sub_wire2(6, 84)    <= sub_wire11(84);
+	sub_wire2(6, 85)    <= sub_wire11(85);
+	sub_wire2(6, 86)    <= sub_wire11(86);
+	sub_wire2(6, 87)    <= sub_wire11(87);
+	sub_wire2(6, 88)    <= sub_wire11(88);
+	sub_wire2(6, 89)    <= sub_wire11(89);
+	sub_wire2(6, 90)    <= sub_wire11(90);
+	sub_wire2(6, 91)    <= sub_wire11(91);
+	sub_wire2(6, 92)    <= sub_wire11(92);
+	sub_wire2(6, 93)    <= sub_wire11(93);
+	sub_wire2(6, 94)    <= sub_wire11(94);
+	sub_wire2(6, 95)    <= sub_wire11(95);
+	sub_wire2(6, 96)    <= sub_wire11(96);
+	sub_wire2(6, 97)    <= sub_wire11(97);
+	sub_wire2(6, 98)    <= sub_wire11(98);
+	sub_wire2(6, 99)    <= sub_wire11(99);
+	sub_wire2(6, 100)    <= sub_wire11(100);
+	sub_wire2(6, 101)    <= sub_wire11(101);
+	sub_wire2(6, 102)    <= sub_wire11(102);
+	sub_wire2(6, 103)    <= sub_wire11(103);
+	sub_wire2(6, 104)    <= sub_wire11(104);
+	sub_wire2(6, 105)    <= sub_wire11(105);
+	sub_wire2(6, 106)    <= sub_wire11(106);
+	sub_wire2(6, 107)    <= sub_wire11(107);
+	sub_wire2(6, 108)    <= sub_wire11(108);
+	sub_wire2(6, 109)    <= sub_wire11(109);
+	sub_wire2(6, 110)    <= sub_wire11(110);
+	sub_wire2(6, 111)    <= sub_wire11(111);
+	sub_wire2(6, 112)    <= sub_wire11(112);
+	sub_wire2(6, 113)    <= sub_wire11(113);
+	sub_wire2(6, 114)    <= sub_wire11(114);
+	sub_wire2(6, 115)    <= sub_wire11(115);
+	sub_wire2(6, 116)    <= sub_wire11(116);
+	sub_wire2(6, 117)    <= sub_wire11(117);
+	sub_wire2(6, 118)    <= sub_wire11(118);
+	sub_wire2(6, 119)    <= sub_wire11(119);
+	sub_wire2(6, 120)    <= sub_wire11(120);
+	sub_wire2(6, 121)    <= sub_wire11(121);
+	sub_wire2(6, 122)    <= sub_wire11(122);
+	sub_wire2(6, 123)    <= sub_wire11(123);
+	sub_wire2(6, 124)    <= sub_wire11(124);
+	sub_wire2(6, 125)    <= sub_wire11(125);
+	sub_wire2(6, 126)    <= sub_wire11(126);
+	sub_wire2(6, 127)    <= sub_wire11(127);
+	sub_wire2(5, 0)    <= sub_wire12(0);
+	sub_wire2(5, 1)    <= sub_wire12(1);
+	sub_wire2(5, 2)    <= sub_wire12(2);
+	sub_wire2(5, 3)    <= sub_wire12(3);
+	sub_wire2(5, 4)    <= sub_wire12(4);
+	sub_wire2(5, 5)    <= sub_wire12(5);
+	sub_wire2(5, 6)    <= sub_wire12(6);
+	sub_wire2(5, 7)    <= sub_wire12(7);
+	sub_wire2(5, 8)    <= sub_wire12(8);
+	sub_wire2(5, 9)    <= sub_wire12(9);
+	sub_wire2(5, 10)    <= sub_wire12(10);
+	sub_wire2(5, 11)    <= sub_wire12(11);
+	sub_wire2(5, 12)    <= sub_wire12(12);
+	sub_wire2(5, 13)    <= sub_wire12(13);
+	sub_wire2(5, 14)    <= sub_wire12(14);
+	sub_wire2(5, 15)    <= sub_wire12(15);
+	sub_wire2(5, 16)    <= sub_wire12(16);
+	sub_wire2(5, 17)    <= sub_wire12(17);
+	sub_wire2(5, 18)    <= sub_wire12(18);
+	sub_wire2(5, 19)    <= sub_wire12(19);
+	sub_wire2(5, 20)    <= sub_wire12(20);
+	sub_wire2(5, 21)    <= sub_wire12(21);
+	sub_wire2(5, 22)    <= sub_wire12(22);
+	sub_wire2(5, 23)    <= sub_wire12(23);
+	sub_wire2(5, 24)    <= sub_wire12(24);
+	sub_wire2(5, 25)    <= sub_wire12(25);
+	sub_wire2(5, 26)    <= sub_wire12(26);
+	sub_wire2(5, 27)    <= sub_wire12(27);
+	sub_wire2(5, 28)    <= sub_wire12(28);
+	sub_wire2(5, 29)    <= sub_wire12(29);
+	sub_wire2(5, 30)    <= sub_wire12(30);
+	sub_wire2(5, 31)    <= sub_wire12(31);
+	sub_wire2(5, 32)    <= sub_wire12(32);
+	sub_wire2(5, 33)    <= sub_wire12(33);
+	sub_wire2(5, 34)    <= sub_wire12(34);
+	sub_wire2(5, 35)    <= sub_wire12(35);
+	sub_wire2(5, 36)    <= sub_wire12(36);
+	sub_wire2(5, 37)    <= sub_wire12(37);
+	sub_wire2(5, 38)    <= sub_wire12(38);
+	sub_wire2(5, 39)    <= sub_wire12(39);
+	sub_wire2(5, 40)    <= sub_wire12(40);
+	sub_wire2(5, 41)    <= sub_wire12(41);
+	sub_wire2(5, 42)    <= sub_wire12(42);
+	sub_wire2(5, 43)    <= sub_wire12(43);
+	sub_wire2(5, 44)    <= sub_wire12(44);
+	sub_wire2(5, 45)    <= sub_wire12(45);
+	sub_wire2(5, 46)    <= sub_wire12(46);
+	sub_wire2(5, 47)    <= sub_wire12(47);
+	sub_wire2(5, 48)    <= sub_wire12(48);
+	sub_wire2(5, 49)    <= sub_wire12(49);
+	sub_wire2(5, 50)    <= sub_wire12(50);
+	sub_wire2(5, 51)    <= sub_wire12(51);
+	sub_wire2(5, 52)    <= sub_wire12(52);
+	sub_wire2(5, 53)    <= sub_wire12(53);
+	sub_wire2(5, 54)    <= sub_wire12(54);
+	sub_wire2(5, 55)    <= sub_wire12(55);
+	sub_wire2(5, 56)    <= sub_wire12(56);
+	sub_wire2(5, 57)    <= sub_wire12(57);
+	sub_wire2(5, 58)    <= sub_wire12(58);
+	sub_wire2(5, 59)    <= sub_wire12(59);
+	sub_wire2(5, 60)    <= sub_wire12(60);
+	sub_wire2(5, 61)    <= sub_wire12(61);
+	sub_wire2(5, 62)    <= sub_wire12(62);
+	sub_wire2(5, 63)    <= sub_wire12(63);
+	sub_wire2(5, 64)    <= sub_wire12(64);
+	sub_wire2(5, 65)    <= sub_wire12(65);
+	sub_wire2(5, 66)    <= sub_wire12(66);
+	sub_wire2(5, 67)    <= sub_wire12(67);
+	sub_wire2(5, 68)    <= sub_wire12(68);
+	sub_wire2(5, 69)    <= sub_wire12(69);
+	sub_wire2(5, 70)    <= sub_wire12(70);
+	sub_wire2(5, 71)    <= sub_wire12(71);
+	sub_wire2(5, 72)    <= sub_wire12(72);
+	sub_wire2(5, 73)    <= sub_wire12(73);
+	sub_wire2(5, 74)    <= sub_wire12(74);
+	sub_wire2(5, 75)    <= sub_wire12(75);
+	sub_wire2(5, 76)    <= sub_wire12(76);
+	sub_wire2(5, 77)    <= sub_wire12(77);
+	sub_wire2(5, 78)    <= sub_wire12(78);
+	sub_wire2(5, 79)    <= sub_wire12(79);
+	sub_wire2(5, 80)    <= sub_wire12(80);
+	sub_wire2(5, 81)    <= sub_wire12(81);
+	sub_wire2(5, 82)    <= sub_wire12(82);
+	sub_wire2(5, 83)    <= sub_wire12(83);
+	sub_wire2(5, 84)    <= sub_wire12(84);
+	sub_wire2(5, 85)    <= sub_wire12(85);
+	sub_wire2(5, 86)    <= sub_wire12(86);
+	sub_wire2(5, 87)    <= sub_wire12(87);
+	sub_wire2(5, 88)    <= sub_wire12(88);
+	sub_wire2(5, 89)    <= sub_wire12(89);
+	sub_wire2(5, 90)    <= sub_wire12(90);
+	sub_wire2(5, 91)    <= sub_wire12(91);
+	sub_wire2(5, 92)    <= sub_wire12(92);
+	sub_wire2(5, 93)    <= sub_wire12(93);
+	sub_wire2(5, 94)    <= sub_wire12(94);
+	sub_wire2(5, 95)    <= sub_wire12(95);
+	sub_wire2(5, 96)    <= sub_wire12(96);
+	sub_wire2(5, 97)    <= sub_wire12(97);
+	sub_wire2(5, 98)    <= sub_wire12(98);
+	sub_wire2(5, 99)    <= sub_wire12(99);
+	sub_wire2(5, 100)    <= sub_wire12(100);
+	sub_wire2(5, 101)    <= sub_wire12(101);
+	sub_wire2(5, 102)    <= sub_wire12(102);
+	sub_wire2(5, 103)    <= sub_wire12(103);
+	sub_wire2(5, 104)    <= sub_wire12(104);
+	sub_wire2(5, 105)    <= sub_wire12(105);
+	sub_wire2(5, 106)    <= sub_wire12(106);
+	sub_wire2(5, 107)    <= sub_wire12(107);
+	sub_wire2(5, 108)    <= sub_wire12(108);
+	sub_wire2(5, 109)    <= sub_wire12(109);
+	sub_wire2(5, 110)    <= sub_wire12(110);
+	sub_wire2(5, 111)    <= sub_wire12(111);
+	sub_wire2(5, 112)    <= sub_wire12(112);
+	sub_wire2(5, 113)    <= sub_wire12(113);
+	sub_wire2(5, 114)    <= sub_wire12(114);
+	sub_wire2(5, 115)    <= sub_wire12(115);
+	sub_wire2(5, 116)    <= sub_wire12(116);
+	sub_wire2(5, 117)    <= sub_wire12(117);
+	sub_wire2(5, 118)    <= sub_wire12(118);
+	sub_wire2(5, 119)    <= sub_wire12(119);
+	sub_wire2(5, 120)    <= sub_wire12(120);
+	sub_wire2(5, 121)    <= sub_wire12(121);
+	sub_wire2(5, 122)    <= sub_wire12(122);
+	sub_wire2(5, 123)    <= sub_wire12(123);
+	sub_wire2(5, 124)    <= sub_wire12(124);
+	sub_wire2(5, 125)    <= sub_wire12(125);
+	sub_wire2(5, 126)    <= sub_wire12(126);
+	sub_wire2(5, 127)    <= sub_wire12(127);
+	sub_wire2(4, 0)    <= sub_wire13(0);
+	sub_wire2(4, 1)    <= sub_wire13(1);
+	sub_wire2(4, 2)    <= sub_wire13(2);
+	sub_wire2(4, 3)    <= sub_wire13(3);
+	sub_wire2(4, 4)    <= sub_wire13(4);
+	sub_wire2(4, 5)    <= sub_wire13(5);
+	sub_wire2(4, 6)    <= sub_wire13(6);
+	sub_wire2(4, 7)    <= sub_wire13(7);
+	sub_wire2(4, 8)    <= sub_wire13(8);
+	sub_wire2(4, 9)    <= sub_wire13(9);
+	sub_wire2(4, 10)    <= sub_wire13(10);
+	sub_wire2(4, 11)    <= sub_wire13(11);
+	sub_wire2(4, 12)    <= sub_wire13(12);
+	sub_wire2(4, 13)    <= sub_wire13(13);
+	sub_wire2(4, 14)    <= sub_wire13(14);
+	sub_wire2(4, 15)    <= sub_wire13(15);
+	sub_wire2(4, 16)    <= sub_wire13(16);
+	sub_wire2(4, 17)    <= sub_wire13(17);
+	sub_wire2(4, 18)    <= sub_wire13(18);
+	sub_wire2(4, 19)    <= sub_wire13(19);
+	sub_wire2(4, 20)    <= sub_wire13(20);
+	sub_wire2(4, 21)    <= sub_wire13(21);
+	sub_wire2(4, 22)    <= sub_wire13(22);
+	sub_wire2(4, 23)    <= sub_wire13(23);
+	sub_wire2(4, 24)    <= sub_wire13(24);
+	sub_wire2(4, 25)    <= sub_wire13(25);
+	sub_wire2(4, 26)    <= sub_wire13(26);
+	sub_wire2(4, 27)    <= sub_wire13(27);
+	sub_wire2(4, 28)    <= sub_wire13(28);
+	sub_wire2(4, 29)    <= sub_wire13(29);
+	sub_wire2(4, 30)    <= sub_wire13(30);
+	sub_wire2(4, 31)    <= sub_wire13(31);
+	sub_wire2(4, 32)    <= sub_wire13(32);
+	sub_wire2(4, 33)    <= sub_wire13(33);
+	sub_wire2(4, 34)    <= sub_wire13(34);
+	sub_wire2(4, 35)    <= sub_wire13(35);
+	sub_wire2(4, 36)    <= sub_wire13(36);
+	sub_wire2(4, 37)    <= sub_wire13(37);
+	sub_wire2(4, 38)    <= sub_wire13(38);
+	sub_wire2(4, 39)    <= sub_wire13(39);
+	sub_wire2(4, 40)    <= sub_wire13(40);
+	sub_wire2(4, 41)    <= sub_wire13(41);
+	sub_wire2(4, 42)    <= sub_wire13(42);
+	sub_wire2(4, 43)    <= sub_wire13(43);
+	sub_wire2(4, 44)    <= sub_wire13(44);
+	sub_wire2(4, 45)    <= sub_wire13(45);
+	sub_wire2(4, 46)    <= sub_wire13(46);
+	sub_wire2(4, 47)    <= sub_wire13(47);
+	sub_wire2(4, 48)    <= sub_wire13(48);
+	sub_wire2(4, 49)    <= sub_wire13(49);
+	sub_wire2(4, 50)    <= sub_wire13(50);
+	sub_wire2(4, 51)    <= sub_wire13(51);
+	sub_wire2(4, 52)    <= sub_wire13(52);
+	sub_wire2(4, 53)    <= sub_wire13(53);
+	sub_wire2(4, 54)    <= sub_wire13(54);
+	sub_wire2(4, 55)    <= sub_wire13(55);
+	sub_wire2(4, 56)    <= sub_wire13(56);
+	sub_wire2(4, 57)    <= sub_wire13(57);
+	sub_wire2(4, 58)    <= sub_wire13(58);
+	sub_wire2(4, 59)    <= sub_wire13(59);
+	sub_wire2(4, 60)    <= sub_wire13(60);
+	sub_wire2(4, 61)    <= sub_wire13(61);
+	sub_wire2(4, 62)    <= sub_wire13(62);
+	sub_wire2(4, 63)    <= sub_wire13(63);
+	sub_wire2(4, 64)    <= sub_wire13(64);
+	sub_wire2(4, 65)    <= sub_wire13(65);
+	sub_wire2(4, 66)    <= sub_wire13(66);
+	sub_wire2(4, 67)    <= sub_wire13(67);
+	sub_wire2(4, 68)    <= sub_wire13(68);
+	sub_wire2(4, 69)    <= sub_wire13(69);
+	sub_wire2(4, 70)    <= sub_wire13(70);
+	sub_wire2(4, 71)    <= sub_wire13(71);
+	sub_wire2(4, 72)    <= sub_wire13(72);
+	sub_wire2(4, 73)    <= sub_wire13(73);
+	sub_wire2(4, 74)    <= sub_wire13(74);
+	sub_wire2(4, 75)    <= sub_wire13(75);
+	sub_wire2(4, 76)    <= sub_wire13(76);
+	sub_wire2(4, 77)    <= sub_wire13(77);
+	sub_wire2(4, 78)    <= sub_wire13(78);
+	sub_wire2(4, 79)    <= sub_wire13(79);
+	sub_wire2(4, 80)    <= sub_wire13(80);
+	sub_wire2(4, 81)    <= sub_wire13(81);
+	sub_wire2(4, 82)    <= sub_wire13(82);
+	sub_wire2(4, 83)    <= sub_wire13(83);
+	sub_wire2(4, 84)    <= sub_wire13(84);
+	sub_wire2(4, 85)    <= sub_wire13(85);
+	sub_wire2(4, 86)    <= sub_wire13(86);
+	sub_wire2(4, 87)    <= sub_wire13(87);
+	sub_wire2(4, 88)    <= sub_wire13(88);
+	sub_wire2(4, 89)    <= sub_wire13(89);
+	sub_wire2(4, 90)    <= sub_wire13(90);
+	sub_wire2(4, 91)    <= sub_wire13(91);
+	sub_wire2(4, 92)    <= sub_wire13(92);
+	sub_wire2(4, 93)    <= sub_wire13(93);
+	sub_wire2(4, 94)    <= sub_wire13(94);
+	sub_wire2(4, 95)    <= sub_wire13(95);
+	sub_wire2(4, 96)    <= sub_wire13(96);
+	sub_wire2(4, 97)    <= sub_wire13(97);
+	sub_wire2(4, 98)    <= sub_wire13(98);
+	sub_wire2(4, 99)    <= sub_wire13(99);
+	sub_wire2(4, 100)    <= sub_wire13(100);
+	sub_wire2(4, 101)    <= sub_wire13(101);
+	sub_wire2(4, 102)    <= sub_wire13(102);
+	sub_wire2(4, 103)    <= sub_wire13(103);
+	sub_wire2(4, 104)    <= sub_wire13(104);
+	sub_wire2(4, 105)    <= sub_wire13(105);
+	sub_wire2(4, 106)    <= sub_wire13(106);
+	sub_wire2(4, 107)    <= sub_wire13(107);
+	sub_wire2(4, 108)    <= sub_wire13(108);
+	sub_wire2(4, 109)    <= sub_wire13(109);
+	sub_wire2(4, 110)    <= sub_wire13(110);
+	sub_wire2(4, 111)    <= sub_wire13(111);
+	sub_wire2(4, 112)    <= sub_wire13(112);
+	sub_wire2(4, 113)    <= sub_wire13(113);
+	sub_wire2(4, 114)    <= sub_wire13(114);
+	sub_wire2(4, 115)    <= sub_wire13(115);
+	sub_wire2(4, 116)    <= sub_wire13(116);
+	sub_wire2(4, 117)    <= sub_wire13(117);
+	sub_wire2(4, 118)    <= sub_wire13(118);
+	sub_wire2(4, 119)    <= sub_wire13(119);
+	sub_wire2(4, 120)    <= sub_wire13(120);
+	sub_wire2(4, 121)    <= sub_wire13(121);
+	sub_wire2(4, 122)    <= sub_wire13(122);
+	sub_wire2(4, 123)    <= sub_wire13(123);
+	sub_wire2(4, 124)    <= sub_wire13(124);
+	sub_wire2(4, 125)    <= sub_wire13(125);
+	sub_wire2(4, 126)    <= sub_wire13(126);
+	sub_wire2(4, 127)    <= sub_wire13(127);
+	sub_wire2(3, 0)    <= sub_wire14(0);
+	sub_wire2(3, 1)    <= sub_wire14(1);
+	sub_wire2(3, 2)    <= sub_wire14(2);
+	sub_wire2(3, 3)    <= sub_wire14(3);
+	sub_wire2(3, 4)    <= sub_wire14(4);
+	sub_wire2(3, 5)    <= sub_wire14(5);
+	sub_wire2(3, 6)    <= sub_wire14(6);
+	sub_wire2(3, 7)    <= sub_wire14(7);
+	sub_wire2(3, 8)    <= sub_wire14(8);
+	sub_wire2(3, 9)    <= sub_wire14(9);
+	sub_wire2(3, 10)    <= sub_wire14(10);
+	sub_wire2(3, 11)    <= sub_wire14(11);
+	sub_wire2(3, 12)    <= sub_wire14(12);
+	sub_wire2(3, 13)    <= sub_wire14(13);
+	sub_wire2(3, 14)    <= sub_wire14(14);
+	sub_wire2(3, 15)    <= sub_wire14(15);
+	sub_wire2(3, 16)    <= sub_wire14(16);
+	sub_wire2(3, 17)    <= sub_wire14(17);
+	sub_wire2(3, 18)    <= sub_wire14(18);
+	sub_wire2(3, 19)    <= sub_wire14(19);
+	sub_wire2(3, 20)    <= sub_wire14(20);
+	sub_wire2(3, 21)    <= sub_wire14(21);
+	sub_wire2(3, 22)    <= sub_wire14(22);
+	sub_wire2(3, 23)    <= sub_wire14(23);
+	sub_wire2(3, 24)    <= sub_wire14(24);
+	sub_wire2(3, 25)    <= sub_wire14(25);
+	sub_wire2(3, 26)    <= sub_wire14(26);
+	sub_wire2(3, 27)    <= sub_wire14(27);
+	sub_wire2(3, 28)    <= sub_wire14(28);
+	sub_wire2(3, 29)    <= sub_wire14(29);
+	sub_wire2(3, 30)    <= sub_wire14(30);
+	sub_wire2(3, 31)    <= sub_wire14(31);
+	sub_wire2(3, 32)    <= sub_wire14(32);
+	sub_wire2(3, 33)    <= sub_wire14(33);
+	sub_wire2(3, 34)    <= sub_wire14(34);
+	sub_wire2(3, 35)    <= sub_wire14(35);
+	sub_wire2(3, 36)    <= sub_wire14(36);
+	sub_wire2(3, 37)    <= sub_wire14(37);
+	sub_wire2(3, 38)    <= sub_wire14(38);
+	sub_wire2(3, 39)    <= sub_wire14(39);
+	sub_wire2(3, 40)    <= sub_wire14(40);
+	sub_wire2(3, 41)    <= sub_wire14(41);
+	sub_wire2(3, 42)    <= sub_wire14(42);
+	sub_wire2(3, 43)    <= sub_wire14(43);
+	sub_wire2(3, 44)    <= sub_wire14(44);
+	sub_wire2(3, 45)    <= sub_wire14(45);
+	sub_wire2(3, 46)    <= sub_wire14(46);
+	sub_wire2(3, 47)    <= sub_wire14(47);
+	sub_wire2(3, 48)    <= sub_wire14(48);
+	sub_wire2(3, 49)    <= sub_wire14(49);
+	sub_wire2(3, 50)    <= sub_wire14(50);
+	sub_wire2(3, 51)    <= sub_wire14(51);
+	sub_wire2(3, 52)    <= sub_wire14(52);
+	sub_wire2(3, 53)    <= sub_wire14(53);
+	sub_wire2(3, 54)    <= sub_wire14(54);
+	sub_wire2(3, 55)    <= sub_wire14(55);
+	sub_wire2(3, 56)    <= sub_wire14(56);
+	sub_wire2(3, 57)    <= sub_wire14(57);
+	sub_wire2(3, 58)    <= sub_wire14(58);
+	sub_wire2(3, 59)    <= sub_wire14(59);
+	sub_wire2(3, 60)    <= sub_wire14(60);
+	sub_wire2(3, 61)    <= sub_wire14(61);
+	sub_wire2(3, 62)    <= sub_wire14(62);
+	sub_wire2(3, 63)    <= sub_wire14(63);
+	sub_wire2(3, 64)    <= sub_wire14(64);
+	sub_wire2(3, 65)    <= sub_wire14(65);
+	sub_wire2(3, 66)    <= sub_wire14(66);
+	sub_wire2(3, 67)    <= sub_wire14(67);
+	sub_wire2(3, 68)    <= sub_wire14(68);
+	sub_wire2(3, 69)    <= sub_wire14(69);
+	sub_wire2(3, 70)    <= sub_wire14(70);
+	sub_wire2(3, 71)    <= sub_wire14(71);
+	sub_wire2(3, 72)    <= sub_wire14(72);
+	sub_wire2(3, 73)    <= sub_wire14(73);
+	sub_wire2(3, 74)    <= sub_wire14(74);
+	sub_wire2(3, 75)    <= sub_wire14(75);
+	sub_wire2(3, 76)    <= sub_wire14(76);
+	sub_wire2(3, 77)    <= sub_wire14(77);
+	sub_wire2(3, 78)    <= sub_wire14(78);
+	sub_wire2(3, 79)    <= sub_wire14(79);
+	sub_wire2(3, 80)    <= sub_wire14(80);
+	sub_wire2(3, 81)    <= sub_wire14(81);
+	sub_wire2(3, 82)    <= sub_wire14(82);
+	sub_wire2(3, 83)    <= sub_wire14(83);
+	sub_wire2(3, 84)    <= sub_wire14(84);
+	sub_wire2(3, 85)    <= sub_wire14(85);
+	sub_wire2(3, 86)    <= sub_wire14(86);
+	sub_wire2(3, 87)    <= sub_wire14(87);
+	sub_wire2(3, 88)    <= sub_wire14(88);
+	sub_wire2(3, 89)    <= sub_wire14(89);
+	sub_wire2(3, 90)    <= sub_wire14(90);
+	sub_wire2(3, 91)    <= sub_wire14(91);
+	sub_wire2(3, 92)    <= sub_wire14(92);
+	sub_wire2(3, 93)    <= sub_wire14(93);
+	sub_wire2(3, 94)    <= sub_wire14(94);
+	sub_wire2(3, 95)    <= sub_wire14(95);
+	sub_wire2(3, 96)    <= sub_wire14(96);
+	sub_wire2(3, 97)    <= sub_wire14(97);
+	sub_wire2(3, 98)    <= sub_wire14(98);
+	sub_wire2(3, 99)    <= sub_wire14(99);
+	sub_wire2(3, 100)    <= sub_wire14(100);
+	sub_wire2(3, 101)    <= sub_wire14(101);
+	sub_wire2(3, 102)    <= sub_wire14(102);
+	sub_wire2(3, 103)    <= sub_wire14(103);
+	sub_wire2(3, 104)    <= sub_wire14(104);
+	sub_wire2(3, 105)    <= sub_wire14(105);
+	sub_wire2(3, 106)    <= sub_wire14(106);
+	sub_wire2(3, 107)    <= sub_wire14(107);
+	sub_wire2(3, 108)    <= sub_wire14(108);
+	sub_wire2(3, 109)    <= sub_wire14(109);
+	sub_wire2(3, 110)    <= sub_wire14(110);
+	sub_wire2(3, 111)    <= sub_wire14(111);
+	sub_wire2(3, 112)    <= sub_wire14(112);
+	sub_wire2(3, 113)    <= sub_wire14(113);
+	sub_wire2(3, 114)    <= sub_wire14(114);
+	sub_wire2(3, 115)    <= sub_wire14(115);
+	sub_wire2(3, 116)    <= sub_wire14(116);
+	sub_wire2(3, 117)    <= sub_wire14(117);
+	sub_wire2(3, 118)    <= sub_wire14(118);
+	sub_wire2(3, 119)    <= sub_wire14(119);
+	sub_wire2(3, 120)    <= sub_wire14(120);
+	sub_wire2(3, 121)    <= sub_wire14(121);
+	sub_wire2(3, 122)    <= sub_wire14(122);
+	sub_wire2(3, 123)    <= sub_wire14(123);
+	sub_wire2(3, 124)    <= sub_wire14(124);
+	sub_wire2(3, 125)    <= sub_wire14(125);
+	sub_wire2(3, 126)    <= sub_wire14(126);
+	sub_wire2(3, 127)    <= sub_wire14(127);
+	sub_wire2(2, 0)    <= sub_wire15(0);
+	sub_wire2(2, 1)    <= sub_wire15(1);
+	sub_wire2(2, 2)    <= sub_wire15(2);
+	sub_wire2(2, 3)    <= sub_wire15(3);
+	sub_wire2(2, 4)    <= sub_wire15(4);
+	sub_wire2(2, 5)    <= sub_wire15(5);
+	sub_wire2(2, 6)    <= sub_wire15(6);
+	sub_wire2(2, 7)    <= sub_wire15(7);
+	sub_wire2(2, 8)    <= sub_wire15(8);
+	sub_wire2(2, 9)    <= sub_wire15(9);
+	sub_wire2(2, 10)    <= sub_wire15(10);
+	sub_wire2(2, 11)    <= sub_wire15(11);
+	sub_wire2(2, 12)    <= sub_wire15(12);
+	sub_wire2(2, 13)    <= sub_wire15(13);
+	sub_wire2(2, 14)    <= sub_wire15(14);
+	sub_wire2(2, 15)    <= sub_wire15(15);
+	sub_wire2(2, 16)    <= sub_wire15(16);
+	sub_wire2(2, 17)    <= sub_wire15(17);
+	sub_wire2(2, 18)    <= sub_wire15(18);
+	sub_wire2(2, 19)    <= sub_wire15(19);
+	sub_wire2(2, 20)    <= sub_wire15(20);
+	sub_wire2(2, 21)    <= sub_wire15(21);
+	sub_wire2(2, 22)    <= sub_wire15(22);
+	sub_wire2(2, 23)    <= sub_wire15(23);
+	sub_wire2(2, 24)    <= sub_wire15(24);
+	sub_wire2(2, 25)    <= sub_wire15(25);
+	sub_wire2(2, 26)    <= sub_wire15(26);
+	sub_wire2(2, 27)    <= sub_wire15(27);
+	sub_wire2(2, 28)    <= sub_wire15(28);
+	sub_wire2(2, 29)    <= sub_wire15(29);
+	sub_wire2(2, 30)    <= sub_wire15(30);
+	sub_wire2(2, 31)    <= sub_wire15(31);
+	sub_wire2(2, 32)    <= sub_wire15(32);
+	sub_wire2(2, 33)    <= sub_wire15(33);
+	sub_wire2(2, 34)    <= sub_wire15(34);
+	sub_wire2(2, 35)    <= sub_wire15(35);
+	sub_wire2(2, 36)    <= sub_wire15(36);
+	sub_wire2(2, 37)    <= sub_wire15(37);
+	sub_wire2(2, 38)    <= sub_wire15(38);
+	sub_wire2(2, 39)    <= sub_wire15(39);
+	sub_wire2(2, 40)    <= sub_wire15(40);
+	sub_wire2(2, 41)    <= sub_wire15(41);
+	sub_wire2(2, 42)    <= sub_wire15(42);
+	sub_wire2(2, 43)    <= sub_wire15(43);
+	sub_wire2(2, 44)    <= sub_wire15(44);
+	sub_wire2(2, 45)    <= sub_wire15(45);
+	sub_wire2(2, 46)    <= sub_wire15(46);
+	sub_wire2(2, 47)    <= sub_wire15(47);
+	sub_wire2(2, 48)    <= sub_wire15(48);
+	sub_wire2(2, 49)    <= sub_wire15(49);
+	sub_wire2(2, 50)    <= sub_wire15(50);
+	sub_wire2(2, 51)    <= sub_wire15(51);
+	sub_wire2(2, 52)    <= sub_wire15(52);
+	sub_wire2(2, 53)    <= sub_wire15(53);
+	sub_wire2(2, 54)    <= sub_wire15(54);
+	sub_wire2(2, 55)    <= sub_wire15(55);
+	sub_wire2(2, 56)    <= sub_wire15(56);
+	sub_wire2(2, 57)    <= sub_wire15(57);
+	sub_wire2(2, 58)    <= sub_wire15(58);
+	sub_wire2(2, 59)    <= sub_wire15(59);
+	sub_wire2(2, 60)    <= sub_wire15(60);
+	sub_wire2(2, 61)    <= sub_wire15(61);
+	sub_wire2(2, 62)    <= sub_wire15(62);
+	sub_wire2(2, 63)    <= sub_wire15(63);
+	sub_wire2(2, 64)    <= sub_wire15(64);
+	sub_wire2(2, 65)    <= sub_wire15(65);
+	sub_wire2(2, 66)    <= sub_wire15(66);
+	sub_wire2(2, 67)    <= sub_wire15(67);
+	sub_wire2(2, 68)    <= sub_wire15(68);
+	sub_wire2(2, 69)    <= sub_wire15(69);
+	sub_wire2(2, 70)    <= sub_wire15(70);
+	sub_wire2(2, 71)    <= sub_wire15(71);
+	sub_wire2(2, 72)    <= sub_wire15(72);
+	sub_wire2(2, 73)    <= sub_wire15(73);
+	sub_wire2(2, 74)    <= sub_wire15(74);
+	sub_wire2(2, 75)    <= sub_wire15(75);
+	sub_wire2(2, 76)    <= sub_wire15(76);
+	sub_wire2(2, 77)    <= sub_wire15(77);
+	sub_wire2(2, 78)    <= sub_wire15(78);
+	sub_wire2(2, 79)    <= sub_wire15(79);
+	sub_wire2(2, 80)    <= sub_wire15(80);
+	sub_wire2(2, 81)    <= sub_wire15(81);
+	sub_wire2(2, 82)    <= sub_wire15(82);
+	sub_wire2(2, 83)    <= sub_wire15(83);
+	sub_wire2(2, 84)    <= sub_wire15(84);
+	sub_wire2(2, 85)    <= sub_wire15(85);
+	sub_wire2(2, 86)    <= sub_wire15(86);
+	sub_wire2(2, 87)    <= sub_wire15(87);
+	sub_wire2(2, 88)    <= sub_wire15(88);
+	sub_wire2(2, 89)    <= sub_wire15(89);
+	sub_wire2(2, 90)    <= sub_wire15(90);
+	sub_wire2(2, 91)    <= sub_wire15(91);
+	sub_wire2(2, 92)    <= sub_wire15(92);
+	sub_wire2(2, 93)    <= sub_wire15(93);
+	sub_wire2(2, 94)    <= sub_wire15(94);
+	sub_wire2(2, 95)    <= sub_wire15(95);
+	sub_wire2(2, 96)    <= sub_wire15(96);
+	sub_wire2(2, 97)    <= sub_wire15(97);
+	sub_wire2(2, 98)    <= sub_wire15(98);
+	sub_wire2(2, 99)    <= sub_wire15(99);
+	sub_wire2(2, 100)    <= sub_wire15(100);
+	sub_wire2(2, 101)    <= sub_wire15(101);
+	sub_wire2(2, 102)    <= sub_wire15(102);
+	sub_wire2(2, 103)    <= sub_wire15(103);
+	sub_wire2(2, 104)    <= sub_wire15(104);
+	sub_wire2(2, 105)    <= sub_wire15(105);
+	sub_wire2(2, 106)    <= sub_wire15(106);
+	sub_wire2(2, 107)    <= sub_wire15(107);
+	sub_wire2(2, 108)    <= sub_wire15(108);
+	sub_wire2(2, 109)    <= sub_wire15(109);
+	sub_wire2(2, 110)    <= sub_wire15(110);
+	sub_wire2(2, 111)    <= sub_wire15(111);
+	sub_wire2(2, 112)    <= sub_wire15(112);
+	sub_wire2(2, 113)    <= sub_wire15(113);
+	sub_wire2(2, 114)    <= sub_wire15(114);
+	sub_wire2(2, 115)    <= sub_wire15(115);
+	sub_wire2(2, 116)    <= sub_wire15(116);
+	sub_wire2(2, 117)    <= sub_wire15(117);
+	sub_wire2(2, 118)    <= sub_wire15(118);
+	sub_wire2(2, 119)    <= sub_wire15(119);
+	sub_wire2(2, 120)    <= sub_wire15(120);
+	sub_wire2(2, 121)    <= sub_wire15(121);
+	sub_wire2(2, 122)    <= sub_wire15(122);
+	sub_wire2(2, 123)    <= sub_wire15(123);
+	sub_wire2(2, 124)    <= sub_wire15(124);
+	sub_wire2(2, 125)    <= sub_wire15(125);
+	sub_wire2(2, 126)    <= sub_wire15(126);
+	sub_wire2(2, 127)    <= sub_wire15(127);
+	sub_wire2(1, 0)    <= sub_wire16(0);
+	sub_wire2(1, 1)    <= sub_wire16(1);
+	sub_wire2(1, 2)    <= sub_wire16(2);
+	sub_wire2(1, 3)    <= sub_wire16(3);
+	sub_wire2(1, 4)    <= sub_wire16(4);
+	sub_wire2(1, 5)    <= sub_wire16(5);
+	sub_wire2(1, 6)    <= sub_wire16(6);
+	sub_wire2(1, 7)    <= sub_wire16(7);
+	sub_wire2(1, 8)    <= sub_wire16(8);
+	sub_wire2(1, 9)    <= sub_wire16(9);
+	sub_wire2(1, 10)    <= sub_wire16(10);
+	sub_wire2(1, 11)    <= sub_wire16(11);
+	sub_wire2(1, 12)    <= sub_wire16(12);
+	sub_wire2(1, 13)    <= sub_wire16(13);
+	sub_wire2(1, 14)    <= sub_wire16(14);
+	sub_wire2(1, 15)    <= sub_wire16(15);
+	sub_wire2(1, 16)    <= sub_wire16(16);
+	sub_wire2(1, 17)    <= sub_wire16(17);
+	sub_wire2(1, 18)    <= sub_wire16(18);
+	sub_wire2(1, 19)    <= sub_wire16(19);
+	sub_wire2(1, 20)    <= sub_wire16(20);
+	sub_wire2(1, 21)    <= sub_wire16(21);
+	sub_wire2(1, 22)    <= sub_wire16(22);
+	sub_wire2(1, 23)    <= sub_wire16(23);
+	sub_wire2(1, 24)    <= sub_wire16(24);
+	sub_wire2(1, 25)    <= sub_wire16(25);
+	sub_wire2(1, 26)    <= sub_wire16(26);
+	sub_wire2(1, 27)    <= sub_wire16(27);
+	sub_wire2(1, 28)    <= sub_wire16(28);
+	sub_wire2(1, 29)    <= sub_wire16(29);
+	sub_wire2(1, 30)    <= sub_wire16(30);
+	sub_wire2(1, 31)    <= sub_wire16(31);
+	sub_wire2(1, 32)    <= sub_wire16(32);
+	sub_wire2(1, 33)    <= sub_wire16(33);
+	sub_wire2(1, 34)    <= sub_wire16(34);
+	sub_wire2(1, 35)    <= sub_wire16(35);
+	sub_wire2(1, 36)    <= sub_wire16(36);
+	sub_wire2(1, 37)    <= sub_wire16(37);
+	sub_wire2(1, 38)    <= sub_wire16(38);
+	sub_wire2(1, 39)    <= sub_wire16(39);
+	sub_wire2(1, 40)    <= sub_wire16(40);
+	sub_wire2(1, 41)    <= sub_wire16(41);
+	sub_wire2(1, 42)    <= sub_wire16(42);
+	sub_wire2(1, 43)    <= sub_wire16(43);
+	sub_wire2(1, 44)    <= sub_wire16(44);
+	sub_wire2(1, 45)    <= sub_wire16(45);
+	sub_wire2(1, 46)    <= sub_wire16(46);
+	sub_wire2(1, 47)    <= sub_wire16(47);
+	sub_wire2(1, 48)    <= sub_wire16(48);
+	sub_wire2(1, 49)    <= sub_wire16(49);
+	sub_wire2(1, 50)    <= sub_wire16(50);
+	sub_wire2(1, 51)    <= sub_wire16(51);
+	sub_wire2(1, 52)    <= sub_wire16(52);
+	sub_wire2(1, 53)    <= sub_wire16(53);
+	sub_wire2(1, 54)    <= sub_wire16(54);
+	sub_wire2(1, 55)    <= sub_wire16(55);
+	sub_wire2(1, 56)    <= sub_wire16(56);
+	sub_wire2(1, 57)    <= sub_wire16(57);
+	sub_wire2(1, 58)    <= sub_wire16(58);
+	sub_wire2(1, 59)    <= sub_wire16(59);
+	sub_wire2(1, 60)    <= sub_wire16(60);
+	sub_wire2(1, 61)    <= sub_wire16(61);
+	sub_wire2(1, 62)    <= sub_wire16(62);
+	sub_wire2(1, 63)    <= sub_wire16(63);
+	sub_wire2(1, 64)    <= sub_wire16(64);
+	sub_wire2(1, 65)    <= sub_wire16(65);
+	sub_wire2(1, 66)    <= sub_wire16(66);
+	sub_wire2(1, 67)    <= sub_wire16(67);
+	sub_wire2(1, 68)    <= sub_wire16(68);
+	sub_wire2(1, 69)    <= sub_wire16(69);
+	sub_wire2(1, 70)    <= sub_wire16(70);
+	sub_wire2(1, 71)    <= sub_wire16(71);
+	sub_wire2(1, 72)    <= sub_wire16(72);
+	sub_wire2(1, 73)    <= sub_wire16(73);
+	sub_wire2(1, 74)    <= sub_wire16(74);
+	sub_wire2(1, 75)    <= sub_wire16(75);
+	sub_wire2(1, 76)    <= sub_wire16(76);
+	sub_wire2(1, 77)    <= sub_wire16(77);
+	sub_wire2(1, 78)    <= sub_wire16(78);
+	sub_wire2(1, 79)    <= sub_wire16(79);
+	sub_wire2(1, 80)    <= sub_wire16(80);
+	sub_wire2(1, 81)    <= sub_wire16(81);
+	sub_wire2(1, 82)    <= sub_wire16(82);
+	sub_wire2(1, 83)    <= sub_wire16(83);
+	sub_wire2(1, 84)    <= sub_wire16(84);
+	sub_wire2(1, 85)    <= sub_wire16(85);
+	sub_wire2(1, 86)    <= sub_wire16(86);
+	sub_wire2(1, 87)    <= sub_wire16(87);
+	sub_wire2(1, 88)    <= sub_wire16(88);
+	sub_wire2(1, 89)    <= sub_wire16(89);
+	sub_wire2(1, 90)    <= sub_wire16(90);
+	sub_wire2(1, 91)    <= sub_wire16(91);
+	sub_wire2(1, 92)    <= sub_wire16(92);
+	sub_wire2(1, 93)    <= sub_wire16(93);
+	sub_wire2(1, 94)    <= sub_wire16(94);
+	sub_wire2(1, 95)    <= sub_wire16(95);
+	sub_wire2(1, 96)    <= sub_wire16(96);
+	sub_wire2(1, 97)    <= sub_wire16(97);
+	sub_wire2(1, 98)    <= sub_wire16(98);
+	sub_wire2(1, 99)    <= sub_wire16(99);
+	sub_wire2(1, 100)    <= sub_wire16(100);
+	sub_wire2(1, 101)    <= sub_wire16(101);
+	sub_wire2(1, 102)    <= sub_wire16(102);
+	sub_wire2(1, 103)    <= sub_wire16(103);
+	sub_wire2(1, 104)    <= sub_wire16(104);
+	sub_wire2(1, 105)    <= sub_wire16(105);
+	sub_wire2(1, 106)    <= sub_wire16(106);
+	sub_wire2(1, 107)    <= sub_wire16(107);
+	sub_wire2(1, 108)    <= sub_wire16(108);
+	sub_wire2(1, 109)    <= sub_wire16(109);
+	sub_wire2(1, 110)    <= sub_wire16(110);
+	sub_wire2(1, 111)    <= sub_wire16(111);
+	sub_wire2(1, 112)    <= sub_wire16(112);
+	sub_wire2(1, 113)    <= sub_wire16(113);
+	sub_wire2(1, 114)    <= sub_wire16(114);
+	sub_wire2(1, 115)    <= sub_wire16(115);
+	sub_wire2(1, 116)    <= sub_wire16(116);
+	sub_wire2(1, 117)    <= sub_wire16(117);
+	sub_wire2(1, 118)    <= sub_wire16(118);
+	sub_wire2(1, 119)    <= sub_wire16(119);
+	sub_wire2(1, 120)    <= sub_wire16(120);
+	sub_wire2(1, 121)    <= sub_wire16(121);
+	sub_wire2(1, 122)    <= sub_wire16(122);
+	sub_wire2(1, 123)    <= sub_wire16(123);
+	sub_wire2(1, 124)    <= sub_wire16(124);
+	sub_wire2(1, 125)    <= sub_wire16(125);
+	sub_wire2(1, 126)    <= sub_wire16(126);
+	sub_wire2(1, 127)    <= sub_wire16(127);
+	sub_wire2(0, 0)    <= sub_wire17(0);
+	sub_wire2(0, 1)    <= sub_wire17(1);
+	sub_wire2(0, 2)    <= sub_wire17(2);
+	sub_wire2(0, 3)    <= sub_wire17(3);
+	sub_wire2(0, 4)    <= sub_wire17(4);
+	sub_wire2(0, 5)    <= sub_wire17(5);
+	sub_wire2(0, 6)    <= sub_wire17(6);
+	sub_wire2(0, 7)    <= sub_wire17(7);
+	sub_wire2(0, 8)    <= sub_wire17(8);
+	sub_wire2(0, 9)    <= sub_wire17(9);
+	sub_wire2(0, 10)    <= sub_wire17(10);
+	sub_wire2(0, 11)    <= sub_wire17(11);
+	sub_wire2(0, 12)    <= sub_wire17(12);
+	sub_wire2(0, 13)    <= sub_wire17(13);
+	sub_wire2(0, 14)    <= sub_wire17(14);
+	sub_wire2(0, 15)    <= sub_wire17(15);
+	sub_wire2(0, 16)    <= sub_wire17(16);
+	sub_wire2(0, 17)    <= sub_wire17(17);
+	sub_wire2(0, 18)    <= sub_wire17(18);
+	sub_wire2(0, 19)    <= sub_wire17(19);
+	sub_wire2(0, 20)    <= sub_wire17(20);
+	sub_wire2(0, 21)    <= sub_wire17(21);
+	sub_wire2(0, 22)    <= sub_wire17(22);
+	sub_wire2(0, 23)    <= sub_wire17(23);
+	sub_wire2(0, 24)    <= sub_wire17(24);
+	sub_wire2(0, 25)    <= sub_wire17(25);
+	sub_wire2(0, 26)    <= sub_wire17(26);
+	sub_wire2(0, 27)    <= sub_wire17(27);
+	sub_wire2(0, 28)    <= sub_wire17(28);
+	sub_wire2(0, 29)    <= sub_wire17(29);
+	sub_wire2(0, 30)    <= sub_wire17(30);
+	sub_wire2(0, 31)    <= sub_wire17(31);
+	sub_wire2(0, 32)    <= sub_wire17(32);
+	sub_wire2(0, 33)    <= sub_wire17(33);
+	sub_wire2(0, 34)    <= sub_wire17(34);
+	sub_wire2(0, 35)    <= sub_wire17(35);
+	sub_wire2(0, 36)    <= sub_wire17(36);
+	sub_wire2(0, 37)    <= sub_wire17(37);
+	sub_wire2(0, 38)    <= sub_wire17(38);
+	sub_wire2(0, 39)    <= sub_wire17(39);
+	sub_wire2(0, 40)    <= sub_wire17(40);
+	sub_wire2(0, 41)    <= sub_wire17(41);
+	sub_wire2(0, 42)    <= sub_wire17(42);
+	sub_wire2(0, 43)    <= sub_wire17(43);
+	sub_wire2(0, 44)    <= sub_wire17(44);
+	sub_wire2(0, 45)    <= sub_wire17(45);
+	sub_wire2(0, 46)    <= sub_wire17(46);
+	sub_wire2(0, 47)    <= sub_wire17(47);
+	sub_wire2(0, 48)    <= sub_wire17(48);
+	sub_wire2(0, 49)    <= sub_wire17(49);
+	sub_wire2(0, 50)    <= sub_wire17(50);
+	sub_wire2(0, 51)    <= sub_wire17(51);
+	sub_wire2(0, 52)    <= sub_wire17(52);
+	sub_wire2(0, 53)    <= sub_wire17(53);
+	sub_wire2(0, 54)    <= sub_wire17(54);
+	sub_wire2(0, 55)    <= sub_wire17(55);
+	sub_wire2(0, 56)    <= sub_wire17(56);
+	sub_wire2(0, 57)    <= sub_wire17(57);
+	sub_wire2(0, 58)    <= sub_wire17(58);
+	sub_wire2(0, 59)    <= sub_wire17(59);
+	sub_wire2(0, 60)    <= sub_wire17(60);
+	sub_wire2(0, 61)    <= sub_wire17(61);
+	sub_wire2(0, 62)    <= sub_wire17(62);
+	sub_wire2(0, 63)    <= sub_wire17(63);
+	sub_wire2(0, 64)    <= sub_wire17(64);
+	sub_wire2(0, 65)    <= sub_wire17(65);
+	sub_wire2(0, 66)    <= sub_wire17(66);
+	sub_wire2(0, 67)    <= sub_wire17(67);
+	sub_wire2(0, 68)    <= sub_wire17(68);
+	sub_wire2(0, 69)    <= sub_wire17(69);
+	sub_wire2(0, 70)    <= sub_wire17(70);
+	sub_wire2(0, 71)    <= sub_wire17(71);
+	sub_wire2(0, 72)    <= sub_wire17(72);
+	sub_wire2(0, 73)    <= sub_wire17(73);
+	sub_wire2(0, 74)    <= sub_wire17(74);
+	sub_wire2(0, 75)    <= sub_wire17(75);
+	sub_wire2(0, 76)    <= sub_wire17(76);
+	sub_wire2(0, 77)    <= sub_wire17(77);
+	sub_wire2(0, 78)    <= sub_wire17(78);
+	sub_wire2(0, 79)    <= sub_wire17(79);
+	sub_wire2(0, 80)    <= sub_wire17(80);
+	sub_wire2(0, 81)    <= sub_wire17(81);
+	sub_wire2(0, 82)    <= sub_wire17(82);
+	sub_wire2(0, 83)    <= sub_wire17(83);
+	sub_wire2(0, 84)    <= sub_wire17(84);
+	sub_wire2(0, 85)    <= sub_wire17(85);
+	sub_wire2(0, 86)    <= sub_wire17(86);
+	sub_wire2(0, 87)    <= sub_wire17(87);
+	sub_wire2(0, 88)    <= sub_wire17(88);
+	sub_wire2(0, 89)    <= sub_wire17(89);
+	sub_wire2(0, 90)    <= sub_wire17(90);
+	sub_wire2(0, 91)    <= sub_wire17(91);
+	sub_wire2(0, 92)    <= sub_wire17(92);
+	sub_wire2(0, 93)    <= sub_wire17(93);
+	sub_wire2(0, 94)    <= sub_wire17(94);
+	sub_wire2(0, 95)    <= sub_wire17(95);
+	sub_wire2(0, 96)    <= sub_wire17(96);
+	sub_wire2(0, 97)    <= sub_wire17(97);
+	sub_wire2(0, 98)    <= sub_wire17(98);
+	sub_wire2(0, 99)    <= sub_wire17(99);
+	sub_wire2(0, 100)    <= sub_wire17(100);
+	sub_wire2(0, 101)    <= sub_wire17(101);
+	sub_wire2(0, 102)    <= sub_wire17(102);
+	sub_wire2(0, 103)    <= sub_wire17(103);
+	sub_wire2(0, 104)    <= sub_wire17(104);
+	sub_wire2(0, 105)    <= sub_wire17(105);
+	sub_wire2(0, 106)    <= sub_wire17(106);
+	sub_wire2(0, 107)    <= sub_wire17(107);
+	sub_wire2(0, 108)    <= sub_wire17(108);
+	sub_wire2(0, 109)    <= sub_wire17(109);
+	sub_wire2(0, 110)    <= sub_wire17(110);
+	sub_wire2(0, 111)    <= sub_wire17(111);
+	sub_wire2(0, 112)    <= sub_wire17(112);
+	sub_wire2(0, 113)    <= sub_wire17(113);
+	sub_wire2(0, 114)    <= sub_wire17(114);
+	sub_wire2(0, 115)    <= sub_wire17(115);
+	sub_wire2(0, 116)    <= sub_wire17(116);
+	sub_wire2(0, 117)    <= sub_wire17(117);
+	sub_wire2(0, 118)    <= sub_wire17(118);
+	sub_wire2(0, 119)    <= sub_wire17(119);
+	sub_wire2(0, 120)    <= sub_wire17(120);
+	sub_wire2(0, 121)    <= sub_wire17(121);
+	sub_wire2(0, 122)    <= sub_wire17(122);
+	sub_wire2(0, 123)    <= sub_wire17(123);
+	sub_wire2(0, 124)    <= sub_wire17(124);
+	sub_wire2(0, 125)    <= sub_wire17(125);
+	sub_wire2(0, 126)    <= sub_wire17(126);
+	sub_wire2(0, 127)    <= sub_wire17(127);
+
+	lpm_mux_component : lpm_mux
+	GENERIC MAP (
+		lpm_size => 16,
+		lpm_type => "LPM_MUX",
+		lpm_width => 128,
+		lpm_widths => 4
+	)
+	PORT MAP (
+		sel => sel,
+		data => sub_wire2,
+		result => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
+-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "4"
+-- Retrieval info: USED_PORT: data0x 0 0 128 0 INPUT NODEFVAL data0x[127..0]
+-- Retrieval info: USED_PORT: data10x 0 0 128 0 INPUT NODEFVAL data10x[127..0]
+-- Retrieval info: USED_PORT: data11x 0 0 128 0 INPUT NODEFVAL data11x[127..0]
+-- Retrieval info: USED_PORT: data12x 0 0 128 0 INPUT NODEFVAL data12x[127..0]
+-- Retrieval info: USED_PORT: data13x 0 0 128 0 INPUT NODEFVAL data13x[127..0]
+-- Retrieval info: USED_PORT: data14x 0 0 128 0 INPUT NODEFVAL data14x[127..0]
+-- Retrieval info: USED_PORT: data15x 0 0 128 0 INPUT NODEFVAL data15x[127..0]
+-- Retrieval info: USED_PORT: data1x 0 0 128 0 INPUT NODEFVAL data1x[127..0]
+-- Retrieval info: USED_PORT: data2x 0 0 128 0 INPUT NODEFVAL data2x[127..0]
+-- Retrieval info: USED_PORT: data3x 0 0 128 0 INPUT NODEFVAL data3x[127..0]
+-- Retrieval info: USED_PORT: data4x 0 0 128 0 INPUT NODEFVAL data4x[127..0]
+-- Retrieval info: USED_PORT: data5x 0 0 128 0 INPUT NODEFVAL data5x[127..0]
+-- Retrieval info: USED_PORT: data6x 0 0 128 0 INPUT NODEFVAL data6x[127..0]
+-- Retrieval info: USED_PORT: data7x 0 0 128 0 INPUT NODEFVAL data7x[127..0]
+-- Retrieval info: USED_PORT: data8x 0 0 128 0 INPUT NODEFVAL data8x[127..0]
+-- Retrieval info: USED_PORT: data9x 0 0 128 0 INPUT NODEFVAL data9x[127..0]
+-- Retrieval info: USED_PORT: result 0 0 128 0 OUTPUT NODEFVAL result[127..0]
+-- Retrieval info: USED_PORT: sel 0 0 4 0 INPUT NODEFVAL sel[3..0]
+-- Retrieval info: CONNECT: result 0 0 128 0 @result 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 15 128 0 data15x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 14 128 0 data14x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 13 128 0 data13x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 12 128 0 data12x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 11 128 0 data11x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 10 128 0 data10x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 9 128 0 data9x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 8 128 0 data8x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 7 128 0 data7x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 6 128 0 data6x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 5 128 0 data5x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 4 128 0 data4x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 3 128 0 data3x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 2 128 0 data2x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 1 128 0 data1x 0 0 128 0
+-- Retrieval info: CONNECT: @data 1 0 128 0 data0x 0 0 128 0
+-- Retrieval info: CONNECT: @sel 0 0 4 0 sel 0 0 4 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_muxVDM_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg0.bsf b/FPGA_quartus_GE/Video/lpm_shiftreg0.bsf
new file mode 100644
index 0000000..fb70a4b
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg0.bsf
@@ -0,0 +1,70 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 128)
+	(text "lpm_shiftreg0" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 112 25 124)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "load" (rect 0 0 23 14)(font "Arial" (font_size 8)))
+		(text "load" (rect 20 26 41 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect 20 42 71 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 74 49 87)(font "Arial" (font_size 8)))
+		(line (pt 0 80)(pt 16 80)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 90 48 103)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 16 96)(line_width 1))
+	)
+	(port
+		(pt 144 72)
+		(output)
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 66 123 79)(font "Arial" (font_size 8)))
+		(line (pt 144 72)(pt 128 72)(line_width 1))
+	)
+	(drawing
+		(text "left shift" (rect 92 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 112)(line_width 1))
+		(line (pt 128 112)(pt 16 112)(line_width 1))
+		(line (pt 16 112)(pt 16 16)(line_width 1))
+		(line (pt 16 74)(pt 22 80)(line_width 1))
+		(line (pt 22 80)(pt 16 86)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg0.inc b/FPGA_quartus_GE/Video/lpm_shiftreg0.inc
new file mode 100644
index 0000000..1c0c4a2
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg0.inc
@@ -0,0 +1,26 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_shiftreg0 
+(
+	clock,
+	data[15..0],
+	load,
+	shiftin
+)
+
+RETURNS (
+	shiftout
+);
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg0.qip b/FPGA_quartus_GE/Video/lpm_shiftreg0.qip
new file mode 100644
index 0000000..a233319
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg0.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg0.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg0.vhd b/FPGA_quartus_GE/Video/lpm_shiftreg0.vhd
new file mode 100644
index 0000000..6e5d954
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg0.vhd
@@ -0,0 +1,135 @@
+-- megafunction wizard: %LPM_SHIFTREG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_shiftreg 
+
+-- ============================================================
+-- File Name: lpm_shiftreg0.vhd
+-- Megafunction Name(s):
+-- 			lpm_shiftreg
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_shiftreg0 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		load		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		shiftout		: OUT STD_LOGIC 
+	);
+END lpm_shiftreg0;
+
+
+ARCHITECTURE SYN OF lpm_shiftreg0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+
+
+
+	COMPONENT lpm_shiftreg
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			load	: IN STD_LOGIC ;
+			clock	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+			shiftout	: OUT STD_LOGIC ;
+			shiftin	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	shiftout    <= sub_wire0;
+
+	lpm_shiftreg_component : lpm_shiftreg
+	GENERIC MAP (
+		lpm_direction => "LEFT",
+		lpm_type => "LPM_SHIFTREG",
+		lpm_width => 16
+	)
+	PORT MAP (
+		load => load,
+		clock => clock,
+		data => data,
+		shiftin => shiftin,
+		shiftout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "1"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "1"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "1"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: nBit NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+-- Retrieval info: USED_PORT: load 0 0 0 0 INPUT NODEFVAL load
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
+-- Retrieval info: CONNECT: @load 0 0 0 0 load 0 0 0 0
+-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg1.bsf b/FPGA_quartus_GE/Video/lpm_shiftreg1.bsf
new file mode 100644
index 0000000..aa20405
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg1.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_shiftreg1" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "q[1..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[1..0]" (rect 95 42 125 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
+	)
+	(drawing
+		(text "left shift" (rect 92 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg1.qip b/FPGA_quartus_GE/Video/lpm_shiftreg1.qip
new file mode 100644
index 0000000..8a8e8a5
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg1.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg1.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg1.vhd b/FPGA_quartus_GE/Video/lpm_shiftreg1.vhd
new file mode 100644
index 0000000..781fe1b
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg1.vhd
@@ -0,0 +1,125 @@
+-- megafunction wizard: %LPM_SHIFTREG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_shiftreg 
+
+-- ============================================================
+-- File Name: lpm_shiftreg1.vhd
+-- Megafunction Name(s):
+-- 			lpm_shiftreg
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_shiftreg1 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+END lpm_shiftreg1;
+
+
+ARCHITECTURE SYN OF lpm_shiftreg1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+
+
+
+	COMPONENT lpm_shiftreg
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
+			shiftin	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(1 DOWNTO 0);
+
+	lpm_shiftreg_component : lpm_shiftreg
+	GENERIC MAP (
+		lpm_direction => "LEFT",
+		lpm_type => "LPM_SHIFTREG",
+		lpm_width => 2
+	)
+	PORT MAP (
+		clock => clock,
+		shiftin => shiftin,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "1"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL q[1..0]
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 2 0 @q 0 0 2 0
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg1_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg2.bsf b/FPGA_quartus_GE/Video/lpm_shiftreg2.bsf
new file mode 100644
index 0000000..0caa084
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg2.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_shiftreg2" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 1))
+	)
+	(drawing
+		(text "right shift" (rect 88 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg2.qip b/FPGA_quartus_GE/Video/lpm_shiftreg2.qip
new file mode 100644
index 0000000..3c5305b
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg2.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg2.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg2.vhd b/FPGA_quartus_GE/Video/lpm_shiftreg2.vhd
new file mode 100644
index 0000000..ca02c26
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg2.vhd
@@ -0,0 +1,125 @@
+-- megafunction wizard: %LPM_SHIFTREG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_shiftreg 
+
+-- ============================================================
+-- File Name: lpm_shiftreg2.vhd
+-- Megafunction Name(s):
+-- 			lpm_shiftreg
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_shiftreg2 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		shiftout		: OUT STD_LOGIC 
+	);
+END lpm_shiftreg2;
+
+
+ARCHITECTURE SYN OF lpm_shiftreg2 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+
+
+
+	COMPONENT lpm_shiftreg
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			shiftout	: OUT STD_LOGIC ;
+			shiftin	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	shiftout    <= sub_wire0;
+
+	lpm_shiftreg_component : lpm_shiftreg
+	GENERIC MAP (
+		lpm_direction => "RIGHT",
+		lpm_type => "LPM_SHIFTREG",
+		lpm_width => 4
+	)
+	PORT MAP (
+		clock => clock,
+		shiftin => shiftin,
+		shiftout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "0"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: nBit NUMERIC "4"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg2_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg3.bsf b/FPGA_quartus_GE/Video/lpm_shiftreg3.bsf
new file mode 100644
index 0000000..d18b388
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg3.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_shiftreg3" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 1))
+	)
+	(drawing
+		(text "right shift" (rect 88 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg3.inc b/FPGA_quartus_GE/Video/lpm_shiftreg3.inc
new file mode 100644
index 0000000..4f70ce5
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg3.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_shiftreg3 
+(
+	clock,
+	shiftin
+)
+
+RETURNS (
+	shiftout
+);
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg3.qip b/FPGA_quartus_GE/Video/lpm_shiftreg3.qip
new file mode 100644
index 0000000..783fdea
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg3.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg3.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg3.vhd b/FPGA_quartus_GE/Video/lpm_shiftreg3.vhd
new file mode 100644
index 0000000..b87c221
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg3.vhd
@@ -0,0 +1,125 @@
+-- megafunction wizard: %LPM_SHIFTREG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_shiftreg 
+
+-- ============================================================
+-- File Name: lpm_shiftreg3.vhd
+-- Megafunction Name(s):
+-- 			lpm_shiftreg
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_shiftreg3 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		shiftout		: OUT STD_LOGIC 
+	);
+END lpm_shiftreg3;
+
+
+ARCHITECTURE SYN OF lpm_shiftreg3 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+
+
+
+	COMPONENT lpm_shiftreg
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			shiftout	: OUT STD_LOGIC ;
+			shiftin	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	shiftout    <= sub_wire0;
+
+	lpm_shiftreg_component : lpm_shiftreg
+	GENERIC MAP (
+		lpm_direction => "RIGHT",
+		lpm_type => "LPM_SHIFTREG",
+		lpm_width => 2
+	)
+	PORT MAP (
+		clock => clock,
+		shiftin => shiftin,
+		shiftout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "0"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: nBit NUMERIC "2"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "2"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg3_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg4.bsf b/FPGA_quartus_GE/Video/lpm_shiftreg4.bsf
new file mode 100644
index 0000000..658958d
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg4.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_shiftreg4" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 1))
+	)
+	(drawing
+		(text "right shift" (rect 88 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg4.inc b/FPGA_quartus_GE/Video/lpm_shiftreg4.inc
new file mode 100644
index 0000000..322863a
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg4.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_shiftreg4 
+(
+	clock,
+	shiftin
+)
+
+RETURNS (
+	shiftout
+);
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg4.qip b/FPGA_quartus_GE/Video/lpm_shiftreg4.qip
new file mode 100644
index 0000000..363cd59
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg4.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg4.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg4.vhd b/FPGA_quartus_GE/Video/lpm_shiftreg4.vhd
new file mode 100644
index 0000000..3d8f5d1
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg4.vhd
@@ -0,0 +1,125 @@
+-- megafunction wizard: %LPM_SHIFTREG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_shiftreg 
+
+-- ============================================================
+-- File Name: lpm_shiftreg4.vhd
+-- Megafunction Name(s):
+-- 			lpm_shiftreg
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_shiftreg4 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		shiftout		: OUT STD_LOGIC 
+	);
+END lpm_shiftreg4;
+
+
+ARCHITECTURE SYN OF lpm_shiftreg4 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC ;
+
+
+
+	COMPONENT lpm_shiftreg
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			shiftout	: OUT STD_LOGIC ;
+			shiftin	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	shiftout    <= sub_wire0;
+
+	lpm_shiftreg_component : lpm_shiftreg
+	GENERIC MAP (
+		lpm_direction => "RIGHT",
+		lpm_type => "LPM_SHIFTREG",
+		lpm_width => 5
+	)
+	PORT MAP (
+		clock => clock,
+		shiftin => shiftin,
+		shiftout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "0"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "0"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: nBit NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg4_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg5.bsf b/FPGA_quartus_GE/Video/lpm_shiftreg5.bsf
new file mode 100644
index 0000000..a528c96
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg5.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_shiftreg5" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[4..0]" (rect 95 42 125 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
+	)
+	(drawing
+		(text "right shift" (rect 88 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg5.inc b/FPGA_quartus_GE/Video/lpm_shiftreg5.inc
new file mode 100644
index 0000000..431ed2c
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg5.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_shiftreg5 
+(
+	clock,
+	shiftin
+)
+
+RETURNS (
+	q[4..0]
+);
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg5.qip b/FPGA_quartus_GE/Video/lpm_shiftreg5.qip
new file mode 100644
index 0000000..9b71f4b
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg5.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg5.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg5.vhd b/FPGA_quartus_GE/Video/lpm_shiftreg5.vhd
new file mode 100644
index 0000000..71a1232
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg5.vhd
@@ -0,0 +1,125 @@
+-- megafunction wizard: %LPM_SHIFTREG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_shiftreg 
+
+-- ============================================================
+-- File Name: lpm_shiftreg5.vhd
+-- Megafunction Name(s):
+-- 			lpm_shiftreg
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_shiftreg5 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+END lpm_shiftreg5;
+
+
+ARCHITECTURE SYN OF lpm_shiftreg5 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+
+
+
+	COMPONENT lpm_shiftreg
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			shiftin	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(4 DOWNTO 0);
+
+	lpm_shiftreg_component : lpm_shiftreg
+	GENERIC MAP (
+		lpm_direction => "RIGHT",
+		lpm_type => "LPM_SHIFTREG",
+		lpm_width => 5
+	)
+	PORT MAP (
+		clock => clock,
+		shiftin => shiftin,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "0"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0]
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg5_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg6.bsf b/FPGA_quartus_GE/Video/lpm_shiftreg6.bsf
new file mode 100644
index 0000000..aa0296b
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg6.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 80)
+	(text "lpm_shiftreg6" (rect 34 1 124 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
+		(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 144 48)
+		(output)
+		(text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[4..0]" (rect 95 42 125 55)(font "Arial" (font_size 8)))
+		(line (pt 144 48)(pt 128 48)(line_width 3))
+	)
+	(drawing
+		(text "right shift" (rect 88 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 64)(line_width 1))
+		(line (pt 128 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg6.inc b/FPGA_quartus_GE/Video/lpm_shiftreg6.inc
new file mode 100644
index 0000000..7767c57
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg6.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_shiftreg6 
+(
+	clock,
+	shiftin
+)
+
+RETURNS (
+	q[4..0]
+);
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg6.qip b/FPGA_quartus_GE/Video/lpm_shiftreg6.qip
new file mode 100644
index 0000000..adb4909
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg6.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_SHIFTREG"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_shiftreg6.cmp"]
diff --git a/FPGA_quartus_GE/Video/lpm_shiftreg6.vhd b/FPGA_quartus_GE/Video/lpm_shiftreg6.vhd
new file mode 100644
index 0000000..773243e
--- /dev/null
+++ b/FPGA_quartus_GE/Video/lpm_shiftreg6.vhd
@@ -0,0 +1,125 @@
+-- megafunction wizard: %LPM_SHIFTREG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_shiftreg 
+
+-- ============================================================
+-- File Name: lpm_shiftreg6.vhd
+-- Megafunction Name(s):
+-- 			lpm_shiftreg
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_shiftreg6 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		shiftin		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+END lpm_shiftreg6;
+
+
+ARCHITECTURE SYN OF lpm_shiftreg6 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+
+
+
+	COMPONENT lpm_shiftreg
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			shiftin	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(4 DOWNTO 0);
+
+	lpm_shiftreg_component : lpm_shiftreg
+	GENERIC MAP (
+		lpm_direction => "RIGHT",
+		lpm_type => "LPM_SHIFTREG",
+		lpm_width => 5
+	)
+	PORT MAP (
+		clock => clock,
+		shiftin => shiftin,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: LeftShift NUMERIC "0"
+-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
+-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
+-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "RIGHT"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: q 0 0 5 0 OUTPUT NODEFVAL q[4..0]
+-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 5 0 @q 0 0 5 0
+-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg6_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/Video/mux41_0.v b/FPGA_quartus_GE/Video/mux41_0.v
new file mode 100644
index 0000000..a1c3219
--- /dev/null
+++ b/FPGA_quartus_GE/Video/mux41_0.v
@@ -0,0 +1,30 @@
+// Copyright (C) 1991-2009 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// PROGRAM		"Quartus II 64-Bit"
+// VERSION		"Version 9.1 Build 222 10/21/2009 SJ Full Version"
+// CREATED		"Sat Mar 01 09:20:01 2014"
+
+
+module mux41_0(S0,S1,D0,INH,D1,Q);
+input S0;
+input S1;
+input D0;
+input INH;
+input D1;
+output Q;
+
+mux41	lpm_instance(.S0(S0),.S1(S1),.D0(D0),.INH(INH),.D1(D1),.Q(Q));
+
+endmodule
diff --git a/FPGA_quartus_GE/Video/mux41_0.vhd b/FPGA_quartus_GE/Video/mux41_0.vhd
new file mode 100644
index 0000000..5002edc
--- /dev/null
+++ b/FPGA_quartus_GE/Video/mux41_0.vhd
@@ -0,0 +1,52 @@
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 9.1 Build 222 10/21/2009 SJ Full Version"
+-- CREATED		"Sat Mar 01 09:19:30 2014"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY altera;
+USE altera.maxplus2.all; 
+
+LIBRARY work;
+
+ENTITY mux41_0 IS 
+PORT 
+( 
+	S0	:	IN	 STD_LOGIC;
+	S1	:	IN	 STD_LOGIC;
+	D0	:	IN	 STD_LOGIC;
+	INH	:	IN	 STD_LOGIC;
+	D1	:	IN	 STD_LOGIC;
+	Q	:	OUT	 STD_LOGIC
+); 
+END mux41_0;
+
+ARCHITECTURE bdf_type OF mux41_0 IS 
+BEGIN 
+
+-- instantiate macrofunction 
+
+b2v_inst40 : mux41
+PORT MAP(S0 => S0,
+		 S1 => S1,
+		 D0 => D0,
+		 INH => INH,
+		 D1 => D1,
+		 Q => Q);
+
+END bdf_type; 
\ No newline at end of file
diff --git a/FPGA_quartus_GE/Video/mux41_1.v b/FPGA_quartus_GE/Video/mux41_1.v
new file mode 100644
index 0000000..042a8ce
--- /dev/null
+++ b/FPGA_quartus_GE/Video/mux41_1.v
@@ -0,0 +1,30 @@
+// Copyright (C) 1991-2009 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// PROGRAM		"Quartus II 64-Bit"
+// VERSION		"Version 9.1 Build 222 10/21/2009 SJ Full Version"
+// CREATED		"Sat Mar 01 09:20:01 2014"
+
+
+module mux41_1(S0,S1,D0,INH,D1,Q);
+input S0;
+input S1;
+input D0;
+input INH;
+input D1;
+output Q;
+
+mux41	lpm_instance(.S0(S0),.S1(S1),.D0(D0),.INH(INH),.D1(D1),.Q(Q));
+
+endmodule
diff --git a/FPGA_quartus_GE/Video/mux41_1.vhd b/FPGA_quartus_GE/Video/mux41_1.vhd
new file mode 100644
index 0000000..fe14f8f
--- /dev/null
+++ b/FPGA_quartus_GE/Video/mux41_1.vhd
@@ -0,0 +1,52 @@
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 9.1 Build 222 10/21/2009 SJ Full Version"
+-- CREATED		"Sat Mar 01 09:19:30 2014"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY altera;
+USE altera.maxplus2.all; 
+
+LIBRARY work;
+
+ENTITY mux41_1 IS 
+PORT 
+( 
+	S0	:	IN	 STD_LOGIC;
+	S1	:	IN	 STD_LOGIC;
+	D0	:	IN	 STD_LOGIC;
+	INH	:	IN	 STD_LOGIC;
+	D1	:	IN	 STD_LOGIC;
+	Q	:	OUT	 STD_LOGIC
+); 
+END mux41_1;
+
+ARCHITECTURE bdf_type OF mux41_1 IS 
+BEGIN 
+
+-- instantiate macrofunction 
+
+b2v_inst41 : mux41
+PORT MAP(S0 => S0,
+		 S1 => S1,
+		 D0 => D0,
+		 INH => INH,
+		 D1 => D1,
+		 Q => Q);
+
+END bdf_type; 
\ No newline at end of file
diff --git a/FPGA_quartus_GE/Video/mux41_2.v b/FPGA_quartus_GE/Video/mux41_2.v
new file mode 100644
index 0000000..63aac29
--- /dev/null
+++ b/FPGA_quartus_GE/Video/mux41_2.v
@@ -0,0 +1,31 @@
+// Copyright (C) 1991-2009 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// PROGRAM		"Quartus II 64-Bit"
+// VERSION		"Version 9.1 Build 222 10/21/2009 SJ Full Version"
+// CREATED		"Sat Mar 01 09:20:01 2014"
+
+
+module mux41_2(S0,D2,S1,D0,INH,D1,Q);
+input S0;
+input D2;
+input S1;
+input D0;
+input INH;
+input D1;
+output Q;
+
+mux41	lpm_instance(.S0(S0),.D2(D2),.S1(S1),.D0(D0),.INH(INH),.D1(D1),.Q(Q));
+
+endmodule
diff --git a/FPGA_quartus_GE/Video/mux41_2.vhd b/FPGA_quartus_GE/Video/mux41_2.vhd
new file mode 100644
index 0000000..ce26e48
--- /dev/null
+++ b/FPGA_quartus_GE/Video/mux41_2.vhd
@@ -0,0 +1,54 @@
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 9.1 Build 222 10/21/2009 SJ Full Version"
+-- CREATED		"Sat Mar 01 09:19:30 2014"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY altera;
+USE altera.maxplus2.all; 
+
+LIBRARY work;
+
+ENTITY mux41_2 IS 
+PORT 
+( 
+	S0	:	IN	 STD_LOGIC;
+	D2	:	IN	 STD_LOGIC;
+	S1	:	IN	 STD_LOGIC;
+	D0	:	IN	 STD_LOGIC;
+	INH	:	IN	 STD_LOGIC;
+	D1	:	IN	 STD_LOGIC;
+	Q	:	OUT	 STD_LOGIC
+); 
+END mux41_2;
+
+ARCHITECTURE bdf_type OF mux41_2 IS 
+BEGIN 
+
+-- instantiate macrofunction 
+
+b2v_inst42 : mux41
+PORT MAP(S0 => S0,
+		 D2 => D2,
+		 S1 => S1,
+		 D0 => D0,
+		 INH => INH,
+		 D1 => D1,
+		 Q => Q);
+
+END bdf_type; 
\ No newline at end of file
diff --git a/FPGA_quartus_GE/Video/mux41_3.v b/FPGA_quartus_GE/Video/mux41_3.v
new file mode 100644
index 0000000..6676d45
--- /dev/null
+++ b/FPGA_quartus_GE/Video/mux41_3.v
@@ -0,0 +1,31 @@
+// Copyright (C) 1991-2009 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// PROGRAM		"Quartus II 64-Bit"
+// VERSION		"Version 9.1 Build 222 10/21/2009 SJ Full Version"
+// CREATED		"Sat Mar 01 09:20:01 2014"
+
+
+module mux41_3(S0,D2,S1,D0,INH,D1,Q);
+input S0;
+input D2;
+input S1;
+input D0;
+input INH;
+input D1;
+output Q;
+
+mux41	lpm_instance(.S0(S0),.D2(D2),.S1(S1),.D0(D0),.INH(INH),.D1(D1),.Q(Q));
+
+endmodule
diff --git a/FPGA_quartus_GE/Video/mux41_3.vhd b/FPGA_quartus_GE/Video/mux41_3.vhd
new file mode 100644
index 0000000..3a218f8
--- /dev/null
+++ b/FPGA_quartus_GE/Video/mux41_3.vhd
@@ -0,0 +1,54 @@
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 9.1 Build 222 10/21/2009 SJ Full Version"
+-- CREATED		"Sat Mar 01 09:19:30 2014"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY altera;
+USE altera.maxplus2.all; 
+
+LIBRARY work;
+
+ENTITY mux41_3 IS 
+PORT 
+( 
+	S0	:	IN	 STD_LOGIC;
+	D2	:	IN	 STD_LOGIC;
+	S1	:	IN	 STD_LOGIC;
+	D0	:	IN	 STD_LOGIC;
+	INH	:	IN	 STD_LOGIC;
+	D1	:	IN	 STD_LOGIC;
+	Q	:	OUT	 STD_LOGIC
+); 
+END mux41_3;
+
+ARCHITECTURE bdf_type OF mux41_3 IS 
+BEGIN 
+
+-- instantiate macrofunction 
+
+b2v_inst43 : mux41
+PORT MAP(S0 => S0,
+		 D2 => D2,
+		 S1 => S1,
+		 D0 => D0,
+		 INH => INH,
+		 D1 => D1,
+		 Q => Q);
+
+END bdf_type; 
\ No newline at end of file
diff --git a/FPGA_quartus_GE/Video/mux41_4.v b/FPGA_quartus_GE/Video/mux41_4.v
new file mode 100644
index 0000000..61e48cb
--- /dev/null
+++ b/FPGA_quartus_GE/Video/mux41_4.v
@@ -0,0 +1,31 @@
+// Copyright (C) 1991-2009 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// PROGRAM		"Quartus II 64-Bit"
+// VERSION		"Version 9.1 Build 222 10/21/2009 SJ Full Version"
+// CREATED		"Sat Mar 01 09:20:01 2014"
+
+
+module mux41_4(S0,D2,S1,D0,INH,D1,Q);
+input S0;
+input D2;
+input S1;
+input D0;
+input INH;
+input D1;
+output Q;
+
+mux41	lpm_instance(.S0(S0),.D2(D2),.S1(S1),.D0(D0),.INH(INH),.D1(D1),.Q(Q));
+
+endmodule
diff --git a/FPGA_quartus_GE/Video/mux41_4.vhd b/FPGA_quartus_GE/Video/mux41_4.vhd
new file mode 100644
index 0000000..09fa038
--- /dev/null
+++ b/FPGA_quartus_GE/Video/mux41_4.vhd
@@ -0,0 +1,54 @@
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 9.1 Build 222 10/21/2009 SJ Full Version"
+-- CREATED		"Sat Mar 01 09:19:30 2014"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY altera;
+USE altera.maxplus2.all; 
+
+LIBRARY work;
+
+ENTITY mux41_4 IS 
+PORT 
+( 
+	S0	:	IN	 STD_LOGIC;
+	D2	:	IN	 STD_LOGIC;
+	S1	:	IN	 STD_LOGIC;
+	D0	:	IN	 STD_LOGIC;
+	INH	:	IN	 STD_LOGIC;
+	D1	:	IN	 STD_LOGIC;
+	Q	:	OUT	 STD_LOGIC
+); 
+END mux41_4;
+
+ARCHITECTURE bdf_type OF mux41_4 IS 
+BEGIN 
+
+-- instantiate macrofunction 
+
+b2v_inst44 : mux41
+PORT MAP(S0 => S0,
+		 D2 => D2,
+		 S1 => S1,
+		 D0 => D0,
+		 INH => INH,
+		 D1 => D1,
+		 Q => Q);
+
+END bdf_type; 
\ No newline at end of file
diff --git a/FPGA_quartus_GE/Video/mux41_5.v b/FPGA_quartus_GE/Video/mux41_5.v
new file mode 100644
index 0000000..d2d0205
--- /dev/null
+++ b/FPGA_quartus_GE/Video/mux41_5.v
@@ -0,0 +1,31 @@
+// Copyright (C) 1991-2009 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// PROGRAM		"Quartus II 64-Bit"
+// VERSION		"Version 9.1 Build 222 10/21/2009 SJ Full Version"
+// CREATED		"Sat Mar 01 09:20:01 2014"
+
+
+module mux41_5(S0,D2,S1,D0,INH,D1,Q);
+input S0;
+input D2;
+input S1;
+input D0;
+input INH;
+input D1;
+output Q;
+
+mux41	lpm_instance(.S0(S0),.D2(D2),.S1(S1),.D0(D0),.INH(INH),.D1(D1),.Q(Q));
+
+endmodule
diff --git a/FPGA_quartus_GE/Video/mux41_5.vhd b/FPGA_quartus_GE/Video/mux41_5.vhd
new file mode 100644
index 0000000..c876641
--- /dev/null
+++ b/FPGA_quartus_GE/Video/mux41_5.vhd
@@ -0,0 +1,54 @@
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 9.1 Build 222 10/21/2009 SJ Full Version"
+-- CREATED		"Sat Mar 01 09:19:30 2014"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY altera;
+USE altera.maxplus2.all; 
+
+LIBRARY work;
+
+ENTITY mux41_5 IS 
+PORT 
+( 
+	S0	:	IN	 STD_LOGIC;
+	D2	:	IN	 STD_LOGIC;
+	S1	:	IN	 STD_LOGIC;
+	D0	:	IN	 STD_LOGIC;
+	INH	:	IN	 STD_LOGIC;
+	D1	:	IN	 STD_LOGIC;
+	Q	:	OUT	 STD_LOGIC
+); 
+END mux41_5;
+
+ARCHITECTURE bdf_type OF mux41_5 IS 
+BEGIN 
+
+-- instantiate macrofunction 
+
+b2v_inst45 : mux41
+PORT MAP(S0 => S0,
+		 D2 => D2,
+		 S1 => S1,
+		 D0 => D0,
+		 INH => INH,
+		 D1 => D1,
+		 Q => Q);
+
+END bdf_type; 
\ No newline at end of file
diff --git a/FPGA_quartus_GE/Video/video.v b/FPGA_quartus_GE/Video/video.v
new file mode 100644
index 0000000..6e447d3
--- /dev/null
+++ b/FPGA_quartus_GE/Video/video.v
@@ -0,0 +1,1288 @@
+// Copyright (C) 1991-2009 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// PROGRAM		"Quartus II 64-Bit"
+// VERSION		"Version 9.1 Build 222 10/21/2009 SJ Full Version"
+// CREATED		"Sat Mar 01 09:20:01 2014"
+
+module video(
+	MAIN_CLK,
+	nFB_CS1,
+	nFB_CS2,
+	nFB_CS3,
+	nFB_WR,
+	FB_SIZE0,
+	FB_SIZE1,
+	nRSTO,
+	nFB_OE,
+	FB_ALE,
+	DDR_SYNC_66M,
+	CLK33M,
+	CLK25M,
+	CLK_VIDEO,
+	VR_BUSY,
+	DDRCLK,
+	FB_ADR,
+	VR_D,
+	nBLANK,
+	nVWE,
+	nVCAS,
+	nVRAS,
+	nVCS,
+	nPD_VGA,
+	VCKE,
+	VSYNC,
+	HSYNC,
+	nSYNC,
+	VIDEO_TA,
+	PIXEL_CLK,
+	VIDEO_RECONFIG,
+	VR_WR,
+	VR_RD,
+	BA,
+	FB_AD,
+	VA,
+	VB,
+	VD,
+	VDM,
+	VDQS,
+	VG,
+	VR
+);
+
+
+input	MAIN_CLK;
+input	nFB_CS1;
+input	nFB_CS2;
+input	nFB_CS3;
+input	nFB_WR;
+input	FB_SIZE0;
+input	FB_SIZE1;
+input	nRSTO;
+input	nFB_OE;
+input	FB_ALE;
+input	DDR_SYNC_66M;
+input	CLK33M;
+input	CLK25M;
+input	CLK_VIDEO;
+input	VR_BUSY;
+input	[3:0] DDRCLK;
+input	[31:0] FB_ADR;
+input	[8:0] VR_D;
+output	nBLANK;
+output	nVWE;
+output	nVCAS;
+output	nVRAS;
+output	nVCS;
+output	nPD_VGA;
+output	VCKE;
+output	VSYNC;
+output	HSYNC;
+output	nSYNC;
+output	VIDEO_TA;
+output	PIXEL_CLK;
+output	VIDEO_RECONFIG;
+output	VR_WR;
+output	VR_RD;
+output	[1:0] BA;
+inout	[31:0] FB_AD;
+output	[12:0] VA;
+output	[7:0] VB;
+inout	[31:0] VD;
+output	[3:0] VDM;
+inout	[3:0] VDQS;
+output	[7:0] VG;
+output	[7:0] VR;
+
+wire	ACP_CLUT_RD;
+wire	[3:0] ACP_CLUT_WR;
+wire	[31:0] BLITTER_ADR;
+wire	[4:0] BLITTER_DACK;
+wire	[127:0] BLITTER_DIN;
+wire	[127:0] BLITTER_DOUT;
+wire	BLITTER_ON;
+wire	BLITTER_RUN;
+wire	BLITTER_SIG;
+wire	BLITTER_TA;
+wire	BLITTER_WR;
+wire	[23:0] CC16;
+wire	[31:0] CC24;
+wire	[23:0] CCA;
+wire	[23:0] CCF;
+wire	[23:0] CCR;
+wire	[23:0] CCS;
+wire	[2:0] CCSEL;
+wire	CLR_FIFO;
+wire	[7:0] CLUT_ADR;
+wire	CLUT_ADR1A;
+wire	CLUT_ADR2A;
+wire	CLUT_ADR3A;
+wire	CLUT_ADR4A;
+wire	CLUT_ADR5A;
+wire	CLUT_ADR6A;
+wire	CLUT_ADR7A;
+wire	[3:0] CLUT_MUX_ADR;
+wire	[3:0] CLUT_OFF;
+wire	COLOR1;
+wire	COLOR2;
+wire	COLOR4;
+wire	COLOR8;
+wire	[4:0] DDR_FB;
+reg	DDR_WR;
+reg	[1:0] DDRWR_D_SEL;
+wire	DOP_FIFO_CLR;
+wire	FALCON_CLUT_RDH;
+wire	FALCON_CLUT_RDL;
+wire	[3:0] FALCON_CLUT_WR;
+wire	[127:0] FB_DDR;
+wire	[3:0] FB_LE;
+wire	[3:0] FB_VDOE;
+wire	[127:0] FIFO_D;
+wire	[8:0] FIFO_MW;
+wire	FIFO_RDE;
+wire	FIFO_WRE;
+wire	INTER_ZEI;
+wire	nFB_BURST;
+wire	PIXEL_CLK_ALTERA_SYNTHESIZED;
+wire	SR_BLITTER_DACK;
+wire	SR_DDR_FB;
+wire	SR_DDR_WR;
+wire	SR_DDRWR_D_SEL;
+wire	SR_FIFO_WRE;
+wire	[7:0] SR_VDMP;
+wire	ST_CLUT_RD;
+wire	[1:0] ST_CLUT_WR;
+wire	[3:0] VDM_SEL;
+wire	[127:0] VDMA;
+wire	[127:0] VDMB;
+wire	[127:0] VDMC;
+wire	[7:0] VDMP;
+wire	VDOUT_OE;
+wire	[63:0] VDP_IN;
+wire	[63:0] VDP_OUT;
+wire	[31:0] VDR;
+wire	[127:0] VDVZ;
+wire	VIDEO_DDR_TA;
+wire	VIDEO_MOD_TA;
+wire	[15:0] VIDEO_RAM_CTR;
+wire	[7:0] ZR_C8;
+wire	[7:0] ZR_C8B;
+wire	SYNTHESIZED_WIRE_0;
+wire	SYNTHESIZED_WIRE_1;
+wire	SYNTHESIZED_WIRE_2;
+wire	SYNTHESIZED_WIRE_3;
+wire	SYNTHESIZED_WIRE_4;
+wire	SYNTHESIZED_WIRE_5;
+wire	SYNTHESIZED_WIRE_60;
+wire	[15:0] SYNTHESIZED_WIRE_7;
+reg	DFF_inst93;
+wire	SYNTHESIZED_WIRE_8;
+wire	SYNTHESIZED_WIRE_9;
+wire	SYNTHESIZED_WIRE_61;
+wire	[31:0] SYNTHESIZED_WIRE_11;
+wire	[7:0] SYNTHESIZED_WIRE_12;
+wire	[31:0] SYNTHESIZED_WIRE_13;
+wire	[31:0] SYNTHESIZED_WIRE_14;
+wire	[31:0] SYNTHESIZED_WIRE_15;
+wire	SYNTHESIZED_WIRE_16;
+wire	SYNTHESIZED_WIRE_18;
+wire	SYNTHESIZED_WIRE_19;
+wire	SYNTHESIZED_WIRE_20;
+wire	SYNTHESIZED_WIRE_21;
+wire	SYNTHESIZED_WIRE_22;
+wire	SYNTHESIZED_WIRE_23;
+wire	SYNTHESIZED_WIRE_24;
+wire	[23:0] SYNTHESIZED_WIRE_25;
+wire	[23:0] SYNTHESIZED_WIRE_26;
+wire	[23:0] SYNTHESIZED_WIRE_62;
+wire	[2:0] SYNTHESIZED_WIRE_29;
+wire	[7:0] SYNTHESIZED_WIRE_30;
+wire	[2:0] SYNTHESIZED_WIRE_31;
+wire	[7:0] SYNTHESIZED_WIRE_32;
+wire	[7:0] SYNTHESIZED_WIRE_33;
+wire	[2:0] SYNTHESIZED_WIRE_34;
+wire	[127:0] SYNTHESIZED_WIRE_63;
+wire	[127:0] SYNTHESIZED_WIRE_36;
+wire	SYNTHESIZED_WIRE_38;
+wire	SYNTHESIZED_WIRE_40;
+wire	[5:0] SYNTHESIZED_WIRE_41;
+wire	[23:0] SYNTHESIZED_WIRE_42;
+wire	[23:0] SYNTHESIZED_WIRE_43;
+wire	[5:0] SYNTHESIZED_WIRE_44;
+wire	[5:0] SYNTHESIZED_WIRE_45;
+wire	SYNTHESIZED_WIRE_46;
+wire	[6:0] SYNTHESIZED_WIRE_47;
+wire	[31:0] SYNTHESIZED_WIRE_48;
+reg	DFF_inst91;
+reg	SYNTHESIZED_WIRE_64;
+wire	SYNTHESIZED_WIRE_49;
+wire	SYNTHESIZED_WIRE_50;
+wire	SYNTHESIZED_WIRE_51;
+wire	SYNTHESIZED_WIRE_52;
+wire	SYNTHESIZED_WIRE_53;
+wire	SYNTHESIZED_WIRE_54;
+wire	SYNTHESIZED_WIRE_55;
+wire	SYNTHESIZED_WIRE_56;
+wire	SYNTHESIZED_WIRE_57;
+wire	[23:0] SYNTHESIZED_WIRE_65;
+
+assign	VB[7:0] = SYNTHESIZED_WIRE_65[7:0];
+assign	VG[7:0] = SYNTHESIZED_WIRE_65[15:8];
+assign	VR[7:0] = SYNTHESIZED_WIRE_65[23:16];
+assign	SYNTHESIZED_WIRE_0 = 0;
+assign	SYNTHESIZED_WIRE_1 = 0;
+assign	SYNTHESIZED_WIRE_2 = 0;
+assign	SYNTHESIZED_WIRE_3 = 0;
+assign	SYNTHESIZED_WIRE_4 = 0;
+assign	SYNTHESIZED_WIRE_5 = 0;
+assign	SYNTHESIZED_WIRE_19 = 0;
+assign	SYNTHESIZED_WIRE_20 = 0;
+assign	SYNTHESIZED_WIRE_21 = 0;
+assign	SYNTHESIZED_WIRE_22 = 0;
+assign	SYNTHESIZED_WIRE_23 = 0;
+assign	SYNTHESIZED_WIRE_24 = 0;
+assign	SYNTHESIZED_WIRE_55 = 0;
+assign	SYNTHESIZED_WIRE_56 = 0;
+assign	SYNTHESIZED_WIRE_57 = 0;
+wire	[127:0] GDFX_TEMP_SIGNAL_6;
+wire	[127:0] GDFX_TEMP_SIGNAL_7;
+wire	[127:0] GDFX_TEMP_SIGNAL_8;
+wire	[127:0] GDFX_TEMP_SIGNAL_9;
+wire	[127:0] GDFX_TEMP_SIGNAL_10;
+wire	[127:0] GDFX_TEMP_SIGNAL_11;
+wire	[127:0] GDFX_TEMP_SIGNAL_12;
+wire	[127:0] GDFX_TEMP_SIGNAL_13;
+wire	[127:0] GDFX_TEMP_SIGNAL_14;
+wire	[127:0] GDFX_TEMP_SIGNAL_0;
+wire	[127:0] GDFX_TEMP_SIGNAL_1;
+wire	[127:0] GDFX_TEMP_SIGNAL_2;
+wire	[127:0] GDFX_TEMP_SIGNAL_3;
+wire	[127:0] GDFX_TEMP_SIGNAL_4;
+wire	[127:0] GDFX_TEMP_SIGNAL_5;
+
+
+assign	GDFX_TEMP_SIGNAL_6 = {VDMB[119:0],VDMA[127:120]};
+assign	GDFX_TEMP_SIGNAL_7 = {VDMB[111:0],VDMA[127:112]};
+assign	GDFX_TEMP_SIGNAL_8 = {VDMB[103:0],VDMA[127:104]};
+assign	GDFX_TEMP_SIGNAL_9 = {VDMB[95:0],VDMA[127:96]};
+assign	GDFX_TEMP_SIGNAL_10 = {VDMB[87:0],VDMA[127:88]};
+assign	GDFX_TEMP_SIGNAL_11 = {VDMB[79:0],VDMA[127:80]};
+assign	GDFX_TEMP_SIGNAL_12 = {VDMB[71:0],VDMA[127:72]};
+assign	GDFX_TEMP_SIGNAL_13 = {VDMB[63:0],VDMA[127:64]};
+assign	GDFX_TEMP_SIGNAL_14 = {VDMB[55:0],VDMA[127:56]};
+assign	GDFX_TEMP_SIGNAL_0 = {VDMB[47:0],VDMA[127:48]};
+assign	GDFX_TEMP_SIGNAL_1 = {VDMB[39:0],VDMA[127:40]};
+assign	GDFX_TEMP_SIGNAL_2 = {VDMB[31:0],VDMA[127:32]};
+assign	GDFX_TEMP_SIGNAL_3 = {VDMB[23:0],VDMA[127:24]};
+assign	GDFX_TEMP_SIGNAL_4 = {VDMB[15:0],VDMA[127:16]};
+assign	GDFX_TEMP_SIGNAL_5 = {VDMB[7:0],VDMA[127:8]};
+
+
+altdpram2	b2v_ACP_CLUT_RAM(
+	.wren_a(ACP_CLUT_WR[3]),
+	.wren_b(SYNTHESIZED_WIRE_0),
+	.clock_a(MAIN_CLK),
+	.clock_b(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.address_a(FB_ADR[9:2]),
+	.address_b(ZR_C8B),
+	.data_a(FB_AD[7:0]),
+	
+	.q_a(SYNTHESIZED_WIRE_30),
+	.q_b(CCA[7:0]));
+
+
+altdpram2	b2v_ACP_CLUT_RAM54(
+	.wren_a(ACP_CLUT_WR[2]),
+	.wren_b(SYNTHESIZED_WIRE_1),
+	.clock_a(MAIN_CLK),
+	.clock_b(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.address_a(FB_ADR[9:2]),
+	.address_b(ZR_C8B),
+	.data_a(FB_AD[15:8]),
+	
+	.q_a(SYNTHESIZED_WIRE_32),
+	.q_b(CCA[15:8]));
+
+
+altdpram2	b2v_ACP_CLUT_RAM55(
+	.wren_a(ACP_CLUT_WR[1]),
+	.wren_b(SYNTHESIZED_WIRE_2),
+	.clock_a(MAIN_CLK),
+	.clock_b(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.address_a(FB_ADR[9:2]),
+	.address_b(ZR_C8B),
+	.data_a(FB_AD[23:16]),
+	
+	.q_a(SYNTHESIZED_WIRE_33),
+	.q_b(CCA[23:16]));
+
+
+BLITTER	b2v_BLITTER(
+	.nRSTO(nRSTO),
+	.MAIN_CLK(MAIN_CLK),
+	.FB_ALE(FB_ALE),
+	.nFB_WR(nFB_WR),
+	.nFB_OE(nFB_OE),
+	.FB_SIZE0(FB_SIZE0),
+	.FB_SIZE1(FB_SIZE1),
+	.BLITTER_ON(BLITTER_ON),
+	.nFB_CS1(nFB_CS1),
+	.nFB_CS2(nFB_CS2),
+	.nFB_CS3(nFB_CS3),
+	.DDRCLK0(DDRCLK[0]),
+	.BLITTER_DACK(BLITTER_DACK),
+	.BLITTER_DIN(BLITTER_DIN),
+	.FB_AD(FB_AD),
+	.FB_ADR(FB_ADR),
+	.VIDEO_RAM_CTR(VIDEO_RAM_CTR),
+	.BLITTER_RUN(BLITTER_RUN),
+	.BLITTER_SIG(BLITTER_SIG),
+	.BLITTER_WR(BLITTER_WR),
+	.BLITTER_TA(BLITTER_TA),
+	.BLITTER_ADR(BLITTER_ADR),
+	.BLITTER_DOUT(BLITTER_DOUT)
+	);
+
+
+DDR_CTR	b2v_DDR_CTR(
+	.nFB_CS1(nFB_CS1),
+	.nFB_CS2(nFB_CS2),
+	.nFB_CS3(nFB_CS3),
+	.nFB_OE(nFB_OE),
+	.FB_SIZE0(FB_SIZE0),
+	.FB_SIZE1(FB_SIZE1),
+	.nRSTO(nRSTO),
+	.MAIN_CLK(MAIN_CLK),
+	.FB_ALE(FB_ALE),
+	.nFB_WR(nFB_WR),
+	.DDR_SYNC_66M(DDR_SYNC_66M),
+	.BLITTER_SIG(BLITTER_SIG),
+	.BLITTER_WR(BLITTER_WR),
+	.DDRCLK0(DDRCLK[0]),
+	.CLK33M(CLK33M),
+	.CLR_FIFO(CLR_FIFO),
+	.BLITTER_ADR(BLITTER_ADR),
+	.FB_AD(FB_AD),
+	.FB_ADR(FB_ADR),
+	.FIFO_MW(FIFO_MW),
+	.VIDEO_RAM_CTR(VIDEO_RAM_CTR),
+	.nVWE(nVWE),
+	.nVRAS(nVRAS),
+	.nVCS(nVCS),
+	.VCKE(VCKE),
+	.nVCAS(nVCAS),
+	.SR_FIFO_WRE(SR_FIFO_WRE),
+	.SR_DDR_FB(SR_DDR_FB),
+	.SR_DDR_WR(SR_DDR_WR),
+	.SR_DDRWR_D_SEL(SR_DDRWR_D_SEL),
+	.VIDEO_DDR_TA(VIDEO_DDR_TA),
+	.SR_BLITTER_DACK(SR_BLITTER_DACK),
+	.DDRWR_D_SEL1(DDRWR_D_SEL[1]),
+	.BA(BA),
+	
+	.FB_LE(FB_LE),
+	.FB_VDOE(FB_VDOE),
+	.SR_VDMP(SR_VDMP),
+	.VA(VA),
+	.VDM_SEL(VDM_SEL));
+
+
+altdpram1	b2v_FALCON_CLUT_BLUE(
+	.wren_a(FALCON_CLUT_WR[3]),
+	.wren_b(SYNTHESIZED_WIRE_3),
+	.clock_a(MAIN_CLK),
+	.clock_b(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.address_a(FB_ADR[9:2]),
+	.address_b(CLUT_ADR),
+	.data_a(FB_AD[23:18]),
+	
+	.q_a(SYNTHESIZED_WIRE_45),
+	.q_b(CCF[7:2]));
+
+
+altdpram1	b2v_FALCON_CLUT_GREEN(
+	.wren_a(FALCON_CLUT_WR[1]),
+	.wren_b(SYNTHESIZED_WIRE_4),
+	.clock_a(MAIN_CLK),
+	.clock_b(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.address_a(FB_ADR[9:2]),
+	.address_b(CLUT_ADR),
+	.data_a(FB_AD[23:18]),
+	
+	.q_a(SYNTHESIZED_WIRE_44),
+	.q_b(CCF[15:10]));
+
+
+altdpram1	b2v_FALCON_CLUT_RED(
+	.wren_a(FALCON_CLUT_WR[0]),
+	.wren_b(SYNTHESIZED_WIRE_5),
+	.clock_a(MAIN_CLK),
+	.clock_b(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.address_a(FB_ADR[9:2]),
+	.address_b(CLUT_ADR),
+	.data_a(FB_AD[31:26]),
+	
+	.q_a(SYNTHESIZED_WIRE_41),
+	.q_b(CCF[23:18]));
+
+
+lpm_fifo_dc0	b2v_inst(
+	.wrreq(FIFO_WRE),
+	.wrclk(DDRCLK[0]),
+	.rdreq(SYNTHESIZED_WIRE_60),
+	.rdclk(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.aclr(CLR_FIFO),
+	.data(VDMC),
+	
+	.q(SYNTHESIZED_WIRE_63),
+	.wrusedw(FIFO_MW));
+
+
+altddio_bidir0	b2v_inst1(
+	.oe(VDOUT_OE),
+	.inclock(DDRCLK[1]),
+	.outclock(DDRCLK[3]),
+	.datain_h(VDP_OUT[63:32]),
+	.datain_l(VDP_OUT[31:0]),
+	.padio(VD),
+	.combout(SYNTHESIZED_WIRE_15),
+	.dataout_h(VDP_IN[31:0]),
+	.dataout_l(VDP_IN[63:32])
+	);
+
+
+lpm_ff4	b2v_inst10(
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.data(SYNTHESIZED_WIRE_7),
+	.q({CC16[23:19],CC16[15:10],CC16[7:3]}));
+
+
+lpm_muxVDM	b2v_inst100(
+	.data0x(VDMB),
+	.data10x(GDFX_TEMP_SIGNAL_0),
+	.data11x(GDFX_TEMP_SIGNAL_1),
+	.data12x(GDFX_TEMP_SIGNAL_2),
+	.data13x(GDFX_TEMP_SIGNAL_3),
+	.data14x(GDFX_TEMP_SIGNAL_4),
+	.data15x(GDFX_TEMP_SIGNAL_5),
+	.data1x(GDFX_TEMP_SIGNAL_6),
+	.data2x(GDFX_TEMP_SIGNAL_7),
+	.data3x(GDFX_TEMP_SIGNAL_8),
+	.data4x(GDFX_TEMP_SIGNAL_9),
+	.data5x(GDFX_TEMP_SIGNAL_10),
+	.data6x(GDFX_TEMP_SIGNAL_11),
+	.data7x(GDFX_TEMP_SIGNAL_12),
+	.data8x(GDFX_TEMP_SIGNAL_13),
+	.data9x(GDFX_TEMP_SIGNAL_14),
+	.sel(VDM_SEL),
+	.result(VDMC));
+
+
+lpm_mux3	b2v_inst102(
+	.data1(DFF_inst93),
+	.data0(ZR_C8[0]),
+	.sel(COLOR1),
+	.result(ZR_C8B[0]));
+
+assign	CLUT_ADR[4] = CLUT_OFF[0] | SYNTHESIZED_WIRE_8;
+
+assign	CLUT_ADR[6] = CLUT_OFF[2] | SYNTHESIZED_WIRE_9;
+
+assign	SYNTHESIZED_WIRE_61 = COLOR8 | COLOR4;
+
+assign	CLUT_ADR[2] = CLUT_ADR2A & SYNTHESIZED_WIRE_61;
+
+assign	SYNTHESIZED_WIRE_16 = COLOR4 | COLOR8 | COLOR2;
+
+
+lpm_bustri_LONG	b2v_inst108(
+	.enabledt(FB_VDOE[0]),
+	.data(VDR),
+	.tridata(FB_AD)
+	);
+
+
+lpm_bustri_LONG	b2v_inst109(
+	.enabledt(FB_VDOE[1]),
+	.data(SYNTHESIZED_WIRE_11),
+	.tridata(FB_AD)
+	);
+
+
+lpm_ff5	b2v_inst11(
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.data(SYNTHESIZED_WIRE_12),
+	.q(ZR_C8));
+
+
+lpm_bustri_LONG	b2v_inst110(
+	.enabledt(FB_VDOE[2]),
+	.data(SYNTHESIZED_WIRE_13),
+	.tridata(FB_AD)
+	);
+
+
+lpm_bustri_LONG	b2v_inst119(
+	.enabledt(FB_VDOE[3]),
+	.data(SYNTHESIZED_WIRE_14),
+	.tridata(FB_AD)
+	);
+
+
+lpm_ff1	b2v_inst12(
+	.clock(DDRCLK[0]),
+	.data(VDP_IN[31:0]),
+	.q(VDVZ[31:0]));
+
+
+lpm_ff0	b2v_inst13(
+	.clock(DDR_SYNC_66M),
+	.enable(FB_LE[0]),
+	.data(FB_AD),
+	.q(FB_DDR[127:96]));
+
+
+lpm_ff0	b2v_inst14(
+	.clock(DDR_SYNC_66M),
+	.enable(FB_LE[1]),
+	.data(FB_AD),
+	.q(FB_DDR[95:64]));
+
+
+lpm_ff0	b2v_inst15(
+	.clock(DDR_SYNC_66M),
+	.enable(FB_LE[2]),
+	.data(FB_AD),
+	.q(FB_DDR[63:32]));
+
+
+lpm_ff0	b2v_inst16(
+	.clock(DDR_SYNC_66M),
+	.enable(FB_LE[3]),
+	.data(FB_AD),
+	.q(FB_DDR[31:0]));
+
+
+lpm_ff0	b2v_inst17(
+	.clock(DDRCLK[0]),
+	.enable(DDR_FB[1]),
+	.data(VDP_IN[31:0]),
+	.q(SYNTHESIZED_WIRE_11));
+
+
+lpm_ff0	b2v_inst18(
+	.clock(DDRCLK[0]),
+	.enable(DDR_FB[0]),
+	.data(VDP_IN[63:32]),
+	.q(SYNTHESIZED_WIRE_13));
+
+
+lpm_ff0	b2v_inst19(
+	.clock(DDRCLK[0]),
+	.enable(DDR_FB[0]),
+	.data(VDP_IN[31:0]),
+	.q(SYNTHESIZED_WIRE_14));
+
+
+altddio_out0	b2v_inst2(
+	.outclock(DDRCLK[3]),
+	.datain_h(VDMP[7:4]),
+	.datain_l(VDMP[3:0]),
+	.dataout(VDM));
+
+
+lpm_ff1	b2v_inst20(
+	.clock(DDRCLK[0]),
+	.data(VDVZ[31:0]),
+	.q(VDVZ[95:64]));
+
+
+lpm_mux0	b2v_inst21(
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.data0x(FIFO_D[127:96]),
+	.data1x(FIFO_D[95:64]),
+	.data2x(FIFO_D[63:32]),
+	.data3x(FIFO_D[31:0]),
+	.sel(CLUT_MUX_ADR[1:0]),
+	.result(SYNTHESIZED_WIRE_48));
+
+
+lpm_mux5	b2v_inst22(
+	.data0x(FB_DDR[127:64]),
+	.data1x(FB_DDR[63:0]),
+	.data2x(BLITTER_DOUT[127:64]),
+	.data3x(BLITTER_DOUT[63:0]),
+	.sel(DDRWR_D_SEL),
+	.result(VDP_OUT));
+
+
+lpm_constant2	b2v_inst23(
+	.result({CC16[18:16],CC16[9:8],CC16[2:0]}));
+
+
+lpm_mux1	b2v_inst24(
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.data0x(FIFO_D[127:112]),
+	.data1x(FIFO_D[111:96]),
+	.data2x(FIFO_D[95:80]),
+	.data3x(FIFO_D[79:64]),
+	.data4x(FIFO_D[63:48]),
+	.data5x(FIFO_D[47:32]),
+	.data6x(FIFO_D[31:16]),
+	.data7x(FIFO_D[15:0]),
+	.sel(CLUT_MUX_ADR[2:0]),
+	.result(SYNTHESIZED_WIRE_7));
+
+
+lpm_mux2	b2v_inst25(
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.data0x(FIFO_D[127:120]),
+	.data10x(FIFO_D[47:40]),
+	.data11x(FIFO_D[39:32]),
+	.data12x(FIFO_D[31:24]),
+	.data13x(FIFO_D[23:16]),
+	.data14x(FIFO_D[15:8]),
+	.data15x(FIFO_D[7:0]),
+	.data1x(FIFO_D[119:112]),
+	.data2x(FIFO_D[111:104]),
+	.data3x(FIFO_D[103:96]),
+	.data4x(FIFO_D[95:88]),
+	.data5x(FIFO_D[87:80]),
+	.data6x(FIFO_D[79:72]),
+	.data7x(FIFO_D[71:64]),
+	.data8x(FIFO_D[63:56]),
+	.data9x(FIFO_D[55:48]),
+	.sel(CLUT_MUX_ADR),
+	.result(SYNTHESIZED_WIRE_12));
+
+
+lpm_shiftreg4	b2v_inst26(
+	.clock(DDRCLK[0]),
+	.shiftin(SR_FIFO_WRE),
+	.shiftout(FIFO_WRE));
+
+
+lpm_latch0	b2v_inst27(
+	.gate(DDR_SYNC_66M),
+	.data(SYNTHESIZED_WIRE_15),
+	.q(VDR));
+
+
+assign	CLUT_ADR[1] = CLUT_ADR1A & SYNTHESIZED_WIRE_16;
+
+
+lpm_ff1	b2v_inst3(
+	.clock(DDRCLK[0]),
+	.data(VDP_IN[63:32]),
+	.q(VDVZ[63:32]));
+
+assign	CLUT_ADR[3] = SYNTHESIZED_WIRE_61 & CLUT_ADR3A;
+
+assign	CLUT_ADR[5] = CLUT_OFF[1] | SYNTHESIZED_WIRE_18;
+
+assign	SYNTHESIZED_WIRE_8 = CLUT_ADR4A & COLOR8;
+
+assign	SYNTHESIZED_WIRE_18 = CLUT_ADR5A & COLOR8;
+
+assign	SYNTHESIZED_WIRE_9 = CLUT_ADR6A & COLOR8;
+
+assign	SYNTHESIZED_WIRE_46 = CLUT_ADR7A & COLOR8;
+
+
+lpm_ff6	b2v_inst36(
+	.clock(DDRCLK[0]),
+	.enable(BLITTER_DACK[0]),
+	.data(VDVZ),
+	.q(BLITTER_DIN));
+
+assign	VDOUT_OE = DDR_WR | SR_DDR_WR;
+
+
+assign	VIDEO_TA = BLITTER_TA | VIDEO_MOD_TA | VIDEO_DDR_TA;
+
+
+lpm_ff1	b2v_inst4(
+	.clock(DDRCLK[0]),
+	.data(VDVZ[63:32]),
+	.q(VDVZ[127:96]));
+
+
+mux41_0	b2v_inst40(
+	.S0(COLOR2),
+	
+	.S1(COLOR4),
+	
+	.D0(CLUT_ADR6A),
+	.INH(SYNTHESIZED_WIRE_19),
+	.D1(CLUT_ADR7A),
+	.Q(SYNTHESIZED_WIRE_54));
+
+
+mux41_1	b2v_inst41(
+	.S0(COLOR2),
+	
+	.S1(COLOR4),
+	
+	.D0(CLUT_ADR5A),
+	.INH(SYNTHESIZED_WIRE_20),
+	.D1(CLUT_ADR6A),
+	.Q(SYNTHESIZED_WIRE_53));
+
+
+mux41_2	b2v_inst42(
+	.S0(COLOR2),
+	.D2(CLUT_ADR7A),
+	.S1(COLOR4),
+	
+	.D0(CLUT_ADR4A),
+	.INH(SYNTHESIZED_WIRE_21),
+	.D1(CLUT_ADR5A),
+	.Q(SYNTHESIZED_WIRE_52));
+
+
+mux41_3	b2v_inst43(
+	.S0(COLOR2),
+	.D2(CLUT_ADR6A),
+	.S1(COLOR4),
+	
+	.D0(CLUT_ADR3A),
+	.INH(SYNTHESIZED_WIRE_22),
+	.D1(CLUT_ADR4A),
+	.Q(SYNTHESIZED_WIRE_51));
+
+
+mux41_4	b2v_inst44(
+	.S0(COLOR2),
+	.D2(CLUT_ADR5A),
+	.S1(COLOR4),
+	
+	.D0(CLUT_ADR2A),
+	.INH(SYNTHESIZED_WIRE_23),
+	.D1(CLUT_ADR3A),
+	.Q(SYNTHESIZED_WIRE_50));
+
+
+mux41_5	b2v_inst45(
+	.S0(COLOR2),
+	.D2(CLUT_ADR4A),
+	.S1(COLOR4),
+	
+	.D0(CLUT_ADR1A),
+	.INH(SYNTHESIZED_WIRE_24),
+	.D1(CLUT_ADR2A),
+	.Q(SYNTHESIZED_WIRE_49));
+
+
+lpm_ff3	b2v_inst46(
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.data(SYNTHESIZED_WIRE_25),
+	.q(SYNTHESIZED_WIRE_43));
+
+
+lpm_ff3	b2v_inst47(
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.data(CCF),
+	.q(SYNTHESIZED_WIRE_25));
+
+
+
+lpm_ff3	b2v_inst49(
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.data(SYNTHESIZED_WIRE_26),
+	.q(SYNTHESIZED_WIRE_42));
+
+
+altddio_out2	b2v_inst5(
+	.outclock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.datain_h(SYNTHESIZED_WIRE_62),
+	.datain_l(SYNTHESIZED_WIRE_62),
+	.dataout(SYNTHESIZED_WIRE_65));
+
+
+
+lpm_bustri1	b2v_inst51(
+	.enabledt(ST_CLUT_RD),
+	.data(SYNTHESIZED_WIRE_29),
+	.tridata(FB_AD[26:24])
+	);
+
+
+lpm_ff3	b2v_inst52(
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.data(CCS),
+	.q(SYNTHESIZED_WIRE_26));
+
+
+lpm_bustri_BYT	b2v_inst53(
+	.enabledt(ACP_CLUT_RD),
+	.data(SYNTHESIZED_WIRE_30),
+	.tridata(FB_AD[7:0])
+	);
+
+
+lpm_constant0	b2v_inst54(
+	.result(CCS[20:16]));
+
+
+
+lpm_bustri1	b2v_inst56(
+	.enabledt(ST_CLUT_RD),
+	.data(SYNTHESIZED_WIRE_31),
+	.tridata(FB_AD[22:20])
+	);
+
+
+lpm_bustri_BYT	b2v_inst57(
+	.enabledt(ACP_CLUT_RD),
+	.data(SYNTHESIZED_WIRE_32),
+	.tridata(FB_AD[15:8])
+	);
+
+
+lpm_bustri_BYT	b2v_inst58(
+	.enabledt(ACP_CLUT_RD),
+	.data(SYNTHESIZED_WIRE_33),
+	.tridata(FB_AD[23:16])
+	);
+
+
+lpm_constant0	b2v_inst59(
+	.result(CCS[12:8]));
+
+
+
+
+lpm_bustri1	b2v_inst61(
+	.enabledt(ST_CLUT_RD),
+	.data(SYNTHESIZED_WIRE_34),
+	.tridata(FB_AD[18:16])
+	);
+
+
+lpm_muxDZ	b2v_inst62(
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.clken(FIFO_RDE),
+	.sel(INTER_ZEI),
+	.data0x(SYNTHESIZED_WIRE_63),
+	.data1x(SYNTHESIZED_WIRE_36),
+	.result(FIFO_D));
+
+
+lpm_fifoDZ	b2v_inst63(
+	.wrreq(SYNTHESIZED_WIRE_60),
+	.rdreq(SYNTHESIZED_WIRE_38),
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.aclr(DOP_FIFO_CLR),
+	.data(SYNTHESIZED_WIRE_63),
+	.q(SYNTHESIZED_WIRE_36));
+
+
+lpm_constant0	b2v_inst64(
+	.result(CCS[4:0]));
+
+assign	SYNTHESIZED_WIRE_60 = FIFO_RDE & SYNTHESIZED_WIRE_40;
+
+
+lpm_bustri3	b2v_inst66(
+	.enabledt(FALCON_CLUT_RDH),
+	.data(SYNTHESIZED_WIRE_41),
+	.tridata(FB_AD[31:26])
+	);
+
+assign	SYNTHESIZED_WIRE_38 = FIFO_RDE & INTER_ZEI;
+
+
+assign	SYNTHESIZED_WIRE_40 =  ~INTER_ZEI;
+
+
+lpm_mux6	b2v_inst7(
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.data0x(SYNTHESIZED_WIRE_42),
+	.data1x(SYNTHESIZED_WIRE_43),
+	
+	
+	.data4x(CCA),
+	.data5x(CC16),
+	.data6x(CC24[23:0]),
+	.data7x(CCR),
+	.sel(CCSEL),
+	.result(SYNTHESIZED_WIRE_62));
+
+
+lpm_bustri3	b2v_inst70(
+	.enabledt(FALCON_CLUT_RDH),
+	.data(SYNTHESIZED_WIRE_44),
+	.tridata(FB_AD[23:18])
+	);
+
+
+lpm_ff6	b2v_inst71(
+	.clock(DDRCLK[0]),
+	.enable(FIFO_WRE),
+	.data(VDVZ),
+	.q(VDMA));
+
+
+
+
+lpm_bustri3	b2v_inst74(
+	.enabledt(FALCON_CLUT_RDL),
+	.data(SYNTHESIZED_WIRE_45),
+	.tridata(FB_AD[23:18])
+	);
+
+
+
+
+lpm_constant1	b2v_inst77(
+	.result(CCF[1:0]));
+
+
+assign	CLUT_ADR[7] = CLUT_OFF[3] | SYNTHESIZED_WIRE_46;
+
+
+
+lpm_constant1	b2v_inst80(
+	.result(CCF[9:8]));
+
+
+lpm_mux4	b2v_inst81(
+	.sel(COLOR1),
+	.data0x(ZR_C8[7:1]),
+	.data1x(SYNTHESIZED_WIRE_47),
+	.result(ZR_C8B[7:1]));
+
+
+lpm_constant3	b2v_inst82(
+	.result(SYNTHESIZED_WIRE_47));
+
+
+lpm_constant1	b2v_inst83(
+	.result(CCF[17:16]));
+
+assign	VDQS[3] = DDR_WR ? DDRCLK[0] : 1'bz;
+
+assign	VDQS[2] = DDR_WR ? DDRCLK[0] : 1'bz;
+
+assign	VDQS[1] = DDR_WR ? DDRCLK[0] : 1'bz;
+
+assign	VDQS[0] = DDR_WR ? DDRCLK[0] : 1'bz;
+
+
+always@(posedge DDRCLK[3])
+begin
+	begin
+	DDRWR_D_SEL[0] = SR_DDRWR_D_SEL;
+	end
+end
+
+
+lpm_shiftreg6	b2v_inst89(
+	.clock(DDRCLK[0]),
+	.shiftin(SR_BLITTER_DACK),
+	.q(BLITTER_DACK));
+
+
+lpm_ff1	b2v_inst9(
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.data(SYNTHESIZED_WIRE_48),
+	.q(CC24));
+
+
+always@(posedge DDRCLK[3])
+begin
+	begin
+	DDR_WR = SR_DDR_WR;
+	end
+end
+
+
+always@(posedge PIXEL_CLK_ALTERA_SYNTHESIZED)
+begin
+	begin
+	DFF_inst91 = CLUT_ADR[0];
+	end
+end
+
+
+lpm_shiftreg6	b2v_inst92(
+	.clock(DDRCLK[0]),
+	.shiftin(SR_DDR_FB),
+	.q(DDR_FB));
+
+
+always@(posedge PIXEL_CLK_ALTERA_SYNTHESIZED)
+begin
+	begin
+	DFF_inst93 = DFF_inst91;
+	end
+end
+
+
+lpm_ff6	b2v_inst94(
+	.clock(DDRCLK[0]),
+	.enable(FIFO_WRE),
+	.data(VDMA),
+	.q(VDMB));
+
+
+always@(posedge PIXEL_CLK_ALTERA_SYNTHESIZED)
+begin
+	begin
+	SYNTHESIZED_WIRE_64 = FIFO_RDE;
+	end
+end
+
+
+
+lpm_ff5	b2v_inst97(
+	.clock(DDRCLK[2]),
+	.data(SR_VDMP),
+	.q(VDMP));
+
+
+lpm_shiftreg0	b2v_sr0(
+	.load(SYNTHESIZED_WIRE_64),
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.shiftin(SYNTHESIZED_WIRE_49),
+	.data(FIFO_D[127:112]),
+	.shiftout(CLUT_ADR[0]));
+
+
+lpm_shiftreg0	b2v_sr1(
+	.load(SYNTHESIZED_WIRE_64),
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.shiftin(SYNTHESIZED_WIRE_50),
+	.data(FIFO_D[111:96]),
+	.shiftout(CLUT_ADR1A));
+
+
+lpm_shiftreg0	b2v_sr2(
+	.load(SYNTHESIZED_WIRE_64),
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.shiftin(SYNTHESIZED_WIRE_51),
+	.data(FIFO_D[95:80]),
+	.shiftout(CLUT_ADR2A));
+
+
+lpm_shiftreg0	b2v_sr3(
+	.load(SYNTHESIZED_WIRE_64),
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.shiftin(SYNTHESIZED_WIRE_52),
+	.data(FIFO_D[79:64]),
+	.shiftout(CLUT_ADR3A));
+
+
+lpm_shiftreg0	b2v_sr4(
+	.load(SYNTHESIZED_WIRE_64),
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.shiftin(SYNTHESIZED_WIRE_53),
+	.data(FIFO_D[63:48]),
+	.shiftout(CLUT_ADR4A));
+
+
+lpm_shiftreg0	b2v_sr5(
+	.load(SYNTHESIZED_WIRE_64),
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.shiftin(SYNTHESIZED_WIRE_54),
+	.data(FIFO_D[47:32]),
+	.shiftout(CLUT_ADR5A));
+
+
+lpm_shiftreg0	b2v_sr6(
+	.load(SYNTHESIZED_WIRE_64),
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.shiftin(CLUT_ADR7A),
+	.data(FIFO_D[31:16]),
+	.shiftout(CLUT_ADR6A));
+
+
+lpm_shiftreg0	b2v_sr7(
+	.load(SYNTHESIZED_WIRE_64),
+	.clock(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.shiftin(CLUT_ADR[0]),
+	.data(FIFO_D[15:0]),
+	.shiftout(CLUT_ADR7A));
+
+
+altdpram0	b2v_ST_CLUT_BLUE(
+	.wren_a(ST_CLUT_WR[1]),
+	.wren_b(SYNTHESIZED_WIRE_55),
+	.clock_a(MAIN_CLK),
+	.clock_b(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.address_a(FB_ADR[4:1]),
+	.address_b(CLUT_ADR[3:0]),
+	.data_a(FB_AD[18:16]),
+	
+	.q_a(SYNTHESIZED_WIRE_34),
+	.q_b(CCS[7:5]));
+
+
+altdpram0	b2v_ST_CLUT_GREEN(
+	.wren_a(ST_CLUT_WR[1]),
+	.wren_b(SYNTHESIZED_WIRE_56),
+	.clock_a(MAIN_CLK),
+	.clock_b(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.address_a(FB_ADR[4:1]),
+	.address_b(CLUT_ADR[3:0]),
+	.data_a(FB_AD[22:20]),
+	
+	.q_a(SYNTHESIZED_WIRE_31),
+	.q_b(CCS[15:13]));
+
+
+altdpram0	b2v_ST_CLUT_RED(
+	.wren_a(ST_CLUT_WR[0]),
+	.wren_b(SYNTHESIZED_WIRE_57),
+	.clock_a(MAIN_CLK),
+	.clock_b(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.address_a(FB_ADR[4:1]),
+	.address_b(CLUT_ADR[3:0]),
+	.data_a(FB_AD[26:24]),
+	
+	.q_a(SYNTHESIZED_WIRE_29),
+	.q_b(CCS[23:21]));
+
+
+VIDEO_MOD_MUX_CLUTCTR	b2v_VIDEO_MOD_MUX_CLUTCTR(
+	.nRSTO(nRSTO),
+	.MAIN_CLK(MAIN_CLK),
+	.nFB_CS1(nFB_CS1),
+	.nFB_CS2(nFB_CS2),
+	.nFB_CS3(nFB_CS3),
+	.nFB_WR(nFB_WR),
+	.nFB_OE(nFB_OE),
+	.FB_SIZE0(FB_SIZE0),
+	.FB_SIZE1(FB_SIZE1),
+	.nFB_BURST(nFB_BURST),
+	.CLK33M(CLK33M),
+	.CLK25M(CLK25M),
+	.BLITTER_RUN(BLITTER_RUN),
+	.CLK_VIDEO(CLK_VIDEO),
+	.VR_BUSY(VR_BUSY),
+	.FB_AD(FB_AD),
+	.FB_ADR(FB_ADR),
+	.VR_D(VR_D),
+	.COLOR8(COLOR8),
+	.ACP_CLUT_RD(ACP_CLUT_RD),
+	.COLOR1(COLOR1),
+	.FALCON_CLUT_RDH(FALCON_CLUT_RDH),
+	.FALCON_CLUT_RDL(FALCON_CLUT_RDL),
+	.ST_CLUT_RD(ST_CLUT_RD),
+	.HSYNC(HSYNC),
+	.VSYNC(VSYNC),
+	.nBLANK(nBLANK),
+	.nSYNC(nSYNC),
+	.nPD_VGA(nPD_VGA),
+	.FIFO_RDE(FIFO_RDE),
+	.COLOR2(COLOR2),
+	.COLOR4(COLOR4),
+	.PIXEL_CLK(PIXEL_CLK_ALTERA_SYNTHESIZED),
+	.BLITTER_ON(BLITTER_ON),
+	.VIDEO_MOD_TA(VIDEO_MOD_TA),
+	.INTER_ZEI(INTER_ZEI),
+	.DOP_FIFO_CLR(DOP_FIFO_CLR),
+	.VIDEO_RECONFIG(VIDEO_RECONFIG),
+	.VR_WR(VR_WR),
+	.VR_RD(VR_RD),
+	.CLR_FIFO(CLR_FIFO),
+	.ACP_CLUT_WR(ACP_CLUT_WR),
+	.CCR(CCR),
+	.CCSEL(CCSEL),
+	.CLUT_MUX_ADR(CLUT_MUX_ADR),
+	.CLUT_OFF(CLUT_OFF),
+	.FALCON_CLUT_WR(FALCON_CLUT_WR),
+	
+	.ST_CLUT_WR(ST_CLUT_WR),
+	.VIDEO_RAM_CTR(VIDEO_RAM_CTR));
+
+assign	PIXEL_CLK = PIXEL_CLK_ALTERA_SYNTHESIZED;
+
+endmodule
+
+module mux41_0(S0,S1,D0,INH,D1,Q);
+/* synthesis black_box */
+
+input S0;
+input S1;
+input D0;
+input INH;
+input D1;
+output Q;
+
+endmodule
+
+module mux41_1(S0,S1,D0,INH,D1,Q);
+/* synthesis black_box */
+
+input S0;
+input S1;
+input D0;
+input INH;
+input D1;
+output Q;
+
+endmodule
+
+module mux41_2(S0,D2,S1,D0,INH,D1,Q);
+/* synthesis black_box */
+
+input S0;
+input D2;
+input S1;
+input D0;
+input INH;
+input D1;
+output Q;
+
+endmodule
+
+module mux41_3(S0,D2,S1,D0,INH,D1,Q);
+/* synthesis black_box */
+
+input S0;
+input D2;
+input S1;
+input D0;
+input INH;
+input D1;
+output Q;
+
+endmodule
+
+module mux41_4(S0,D2,S1,D0,INH,D1,Q);
+/* synthesis black_box */
+
+input S0;
+input D2;
+input S1;
+input D0;
+input INH;
+input D1;
+output Q;
+
+endmodule
+
+module mux41_5(S0,D2,S1,D0,INH,D1,Q);
+/* synthesis black_box */
+
+input S0;
+input D2;
+input S1;
+input D0;
+input INH;
+input D1;
+output Q;
+
+endmodule
diff --git a/FPGA_quartus_GE/Video/video.vhd b/FPGA_quartus_GE/Video/video.vhd
new file mode 100644
index 0000000..7faebdc
--- /dev/null
+++ b/FPGA_quartus_GE/Video/video.vhd
@@ -0,0 +1,1755 @@
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 9.1 Build 222 10/21/2009 SJ Full Version"
+-- CREATED		"Sat Mar 01 09:19:30 2014"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY work;
+
+ENTITY video IS 
+	PORT
+	(
+		MAIN_CLK :  IN  STD_LOGIC;
+		nFB_CS1 :  IN  STD_LOGIC;
+		nFB_CS2 :  IN  STD_LOGIC;
+		nFB_CS3 :  IN  STD_LOGIC;
+		nFB_WR :  IN  STD_LOGIC;
+		FB_SIZE0 :  IN  STD_LOGIC;
+		FB_SIZE1 :  IN  STD_LOGIC;
+		nRSTO :  IN  STD_LOGIC;
+		nFB_OE :  IN  STD_LOGIC;
+		FB_ALE :  IN  STD_LOGIC;
+		DDR_SYNC_66M :  IN  STD_LOGIC;
+		CLK33M :  IN  STD_LOGIC;
+		CLK25M :  IN  STD_LOGIC;
+		CLK_VIDEO :  IN  STD_LOGIC;
+		VR_BUSY :  IN  STD_LOGIC;
+		DDRCLK :  IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		FB_AD :  INOUT  STD_LOGIC_VECTOR(31 DOWNTO 0);
+		FB_ADR :  IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+		VD :  INOUT  STD_LOGIC_VECTOR(31 DOWNTO 0);
+		VDQS :  INOUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VR_D :  IN  STD_LOGIC_VECTOR(8 DOWNTO 0);
+		nBLANK :  OUT  STD_LOGIC;
+		nVWE :  OUT  STD_LOGIC;
+		nVCAS :  OUT  STD_LOGIC;
+		nVRAS :  OUT  STD_LOGIC;
+		nVCS :  OUT  STD_LOGIC;
+		nPD_VGA :  OUT  STD_LOGIC;
+		VCKE :  OUT  STD_LOGIC;
+		VSYNC :  OUT  STD_LOGIC;
+		HSYNC :  OUT  STD_LOGIC;
+		nSYNC :  OUT  STD_LOGIC;
+		VIDEO_TA :  OUT  STD_LOGIC;
+		PIXEL_CLK :  OUT  STD_LOGIC;
+		VIDEO_RECONFIG :  OUT  STD_LOGIC;
+		VR_WR :  OUT  STD_LOGIC;
+		VR_RD :  OUT  STD_LOGIC;
+		BA :  OUT  STD_LOGIC_VECTOR(1 DOWNTO 0);
+		VA :  OUT  STD_LOGIC_VECTOR(12 DOWNTO 0);
+		VB :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		VDM :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VG :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		VR :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END video;
+
+ARCHITECTURE bdf_type OF video IS 
+
+ATTRIBUTE black_box : BOOLEAN;
+ATTRIBUTE noopt : BOOLEAN;
+
+COMPONENT mux41_0
+	PORT(S0 : IN STD_LOGIC;
+		 S1 : IN STD_LOGIC;
+		 D0 : IN STD_LOGIC;
+		 INH : IN STD_LOGIC;
+		 D1 : IN STD_LOGIC;
+		 Q : OUT STD_LOGIC);
+END COMPONENT;
+ATTRIBUTE black_box OF mux41_0: COMPONENT IS true;
+ATTRIBUTE noopt OF mux41_0: COMPONENT IS true;
+
+COMPONENT mux41_1
+	PORT(S0 : IN STD_LOGIC;
+		 S1 : IN STD_LOGIC;
+		 D0 : IN STD_LOGIC;
+		 INH : IN STD_LOGIC;
+		 D1 : IN STD_LOGIC;
+		 Q : OUT STD_LOGIC);
+END COMPONENT;
+ATTRIBUTE black_box OF mux41_1: COMPONENT IS true;
+ATTRIBUTE noopt OF mux41_1: COMPONENT IS true;
+
+COMPONENT mux41_2
+	PORT(S0 : IN STD_LOGIC;
+		 D2 : IN STD_LOGIC;
+		 S1 : IN STD_LOGIC;
+		 D0 : IN STD_LOGIC;
+		 INH : IN STD_LOGIC;
+		 D1 : IN STD_LOGIC;
+		 Q : OUT STD_LOGIC);
+END COMPONENT;
+ATTRIBUTE black_box OF mux41_2: COMPONENT IS true;
+ATTRIBUTE noopt OF mux41_2: COMPONENT IS true;
+
+COMPONENT mux41_3
+	PORT(S0 : IN STD_LOGIC;
+		 D2 : IN STD_LOGIC;
+		 S1 : IN STD_LOGIC;
+		 D0 : IN STD_LOGIC;
+		 INH : IN STD_LOGIC;
+		 D1 : IN STD_LOGIC;
+		 Q : OUT STD_LOGIC);
+END COMPONENT;
+ATTRIBUTE black_box OF mux41_3: COMPONENT IS true;
+ATTRIBUTE noopt OF mux41_3: COMPONENT IS true;
+
+COMPONENT mux41_4
+	PORT(S0 : IN STD_LOGIC;
+		 D2 : IN STD_LOGIC;
+		 S1 : IN STD_LOGIC;
+		 D0 : IN STD_LOGIC;
+		 INH : IN STD_LOGIC;
+		 D1 : IN STD_LOGIC;
+		 Q : OUT STD_LOGIC);
+END COMPONENT;
+ATTRIBUTE black_box OF mux41_4: COMPONENT IS true;
+ATTRIBUTE noopt OF mux41_4: COMPONENT IS true;
+
+COMPONENT mux41_5
+	PORT(S0 : IN STD_LOGIC;
+		 D2 : IN STD_LOGIC;
+		 S1 : IN STD_LOGIC;
+		 D0 : IN STD_LOGIC;
+		 INH : IN STD_LOGIC;
+		 D1 : IN STD_LOGIC;
+		 Q : OUT STD_LOGIC);
+END COMPONENT;
+ATTRIBUTE black_box OF mux41_5: COMPONENT IS true;
+ATTRIBUTE noopt OF mux41_5: COMPONENT IS true;
+
+COMPONENT altdpram2
+	PORT(wren_a : IN STD_LOGIC;
+		 wren_b : IN STD_LOGIC;
+		 clock_a : IN STD_LOGIC;
+		 clock_b : IN STD_LOGIC;
+		 address_a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 address_b : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data_a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data_b : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 q_a : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 q_b : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT blitter
+	PORT(nRSTO : IN STD_LOGIC;
+		 MAIN_CLK : IN STD_LOGIC;
+		 FB_ALE : IN STD_LOGIC;
+		 nFB_WR : IN STD_LOGIC;
+		 nFB_OE : IN STD_LOGIC;
+		 FB_SIZE0 : IN STD_LOGIC;
+		 FB_SIZE1 : IN STD_LOGIC;
+		 BLITTER_ON : IN STD_LOGIC;
+		 nFB_CS1 : IN STD_LOGIC;
+		 nFB_CS2 : IN STD_LOGIC;
+		 nFB_CS3 : IN STD_LOGIC;
+		 DDRCLK0 : IN STD_LOGIC;
+		 BLITTER_DACK : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 BLITTER_DIN : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 BLITTER_RUN : OUT STD_LOGIC;
+		 BLITTER_SIG : OUT STD_LOGIC;
+		 BLITTER_WR : OUT STD_LOGIC;
+		 BLITTER_TA : OUT STD_LOGIC;
+		 BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT ddr_ctr
+	PORT(nFB_CS1 : IN STD_LOGIC;
+		 nFB_CS2 : IN STD_LOGIC;
+		 nFB_CS3 : IN STD_LOGIC;
+		 nFB_OE : IN STD_LOGIC;
+		 FB_SIZE0 : IN STD_LOGIC;
+		 FB_SIZE1 : IN STD_LOGIC;
+		 nRSTO : IN STD_LOGIC;
+		 MAIN_CLK : IN STD_LOGIC;
+		 FB_ALE : IN STD_LOGIC;
+		 nFB_WR : IN STD_LOGIC;
+		 DDR_SYNC_66M : IN STD_LOGIC;
+		 BLITTER_SIG : IN STD_LOGIC;
+		 BLITTER_WR : IN STD_LOGIC;
+		 DDRCLK0 : IN STD_LOGIC;
+		 CLK33M : IN STD_LOGIC;
+		 CLR_FIFO : IN STD_LOGIC;
+		 BLITTER_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 FIFO_MW : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+		 VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 nVWE : OUT STD_LOGIC;
+		 nVRAS : OUT STD_LOGIC;
+		 nVCS : OUT STD_LOGIC;
+		 VCKE : OUT STD_LOGIC;
+		 nVCAS : OUT STD_LOGIC;
+		 SR_FIFO_WRE : OUT STD_LOGIC;
+		 SR_DDR_FB : OUT STD_LOGIC;
+		 SR_DDR_WR : OUT STD_LOGIC;
+		 SR_DDRWR_D_SEL : OUT STD_LOGIC;
+		 VIDEO_DDR_TA : OUT STD_LOGIC;
+		 SR_BLITTER_DACK : OUT STD_LOGIC;
+		 DDRWR_D_SEL1 : OUT STD_LOGIC;
+		 BA : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 FB_LE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 FB_VDOE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SR_VDMP : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
+		 VDM_SEL : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT altdpram1
+	PORT(wren_a : IN STD_LOGIC;
+		 wren_b : IN STD_LOGIC;
+		 clock_a : IN STD_LOGIC;
+		 clock_b : IN STD_LOGIC;
+		 address_a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 address_b : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data_a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 data_b : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 q_a : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 q_b : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_fifo_dc0
+	PORT(wrreq : IN STD_LOGIC;
+		 wrclk : IN STD_LOGIC;
+		 rdreq : IN STD_LOGIC;
+		 rdclk : IN STD_LOGIC;
+		 aclr : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 rdempty : OUT STD_LOGIC;
+		 q : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 wrusedw : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT altddio_bidir0
+	PORT(oe : IN STD_LOGIC;
+		 inclock : IN STD_LOGIC;
+		 outclock : IN STD_LOGIC;
+		 datain_h : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 datain_l : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 padio : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 combout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 dataout_h : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 dataout_l : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_ff4
+	PORT(clock : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_muxvdm
+	PORT(data0x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data10x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data11x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data12x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data13x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data14x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data15x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data1x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data2x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data3x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data4x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data5x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data6x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data7x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data8x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data9x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 result : OUT STD_LOGIC_VECTOR(127 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_mux3
+	PORT(data1 : IN STD_LOGIC;
+		 data0 : IN STD_LOGIC;
+		 sel : IN STD_LOGIC;
+		 result : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT lpm_bustri_long
+	PORT(enabledt : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 tridata : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_ff5
+	PORT(clock : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_ff1
+	PORT(clock : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_ff0
+	PORT(clock : IN STD_LOGIC;
+		 enable : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT altddio_out0
+	PORT(outclock : IN STD_LOGIC;
+		 datain_h : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 datain_l : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 dataout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_mux0
+	PORT(clock : IN STD_LOGIC;
+		 data0x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 data1x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 data2x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 data3x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_mux5
+	PORT(data0x : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+		 data1x : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+		 data2x : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+		 data3x : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+		 sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 result : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_constant2
+	PORT(		 result : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_mux1
+	PORT(clock : IN STD_LOGIC;
+		 data0x : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 data1x : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 data2x : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 data3x : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 data4x : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 data5x : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 data6x : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 data7x : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 result : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_mux2
+	PORT(clock : IN STD_LOGIC;
+		 data0x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data10x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data11x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data12x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data13x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data14x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data15x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data1x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data2x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data3x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data4x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data5x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data6x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data7x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data8x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 data9x : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 result : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_shiftreg4
+	PORT(clock : IN STD_LOGIC;
+		 shiftin : IN STD_LOGIC;
+		 shiftout : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT lpm_latch0
+	PORT(gate : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_ff6
+	PORT(clock : IN STD_LOGIC;
+		 enable : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(127 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_ff3
+	PORT(clock : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT altddio_out2
+	PORT(outclock : IN STD_LOGIC;
+		 datain_h : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 datain_l : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 dataout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_bustri1
+	PORT(enabledt : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 tridata : INOUT STD_LOGIC_VECTOR(2 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_bustri_byt
+	PORT(enabledt : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 tridata : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_constant0
+	PORT(		 result : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_muxdz
+	PORT(clock : IN STD_LOGIC;
+		 clken : IN STD_LOGIC;
+		 sel : IN STD_LOGIC;
+		 data0x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 data1x : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 result : OUT STD_LOGIC_VECTOR(127 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_fifodz
+	PORT(wrreq : IN STD_LOGIC;
+		 rdreq : IN STD_LOGIC;
+		 clock : IN STD_LOGIC;
+		 aclr : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(127 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_bustri3
+	PORT(enabledt : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 tridata : INOUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_mux6
+	PORT(clock : IN STD_LOGIC;
+		 data0x : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 data1x : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 data2x : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 data3x : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 data4x : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 data5x : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 data6x : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 data7x : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 result : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_constant1
+	PORT(		 result : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_mux4
+	PORT(sel : IN STD_LOGIC;
+		 data0x : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+		 data1x : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+		 result : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_constant3
+	PORT(		 result : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_shiftreg6
+	PORT(clock : IN STD_LOGIC;
+		 shiftin : IN STD_LOGIC;
+		 q : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT lpm_shiftreg0
+	PORT(load : IN STD_LOGIC;
+		 clock : IN STD_LOGIC;
+		 shiftin : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 shiftout : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT altdpram0
+	PORT(wren_a : IN STD_LOGIC;
+		 wren_b : IN STD_LOGIC;
+		 clock_a : IN STD_LOGIC;
+		 clock_b : IN STD_LOGIC;
+		 address_a : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 address_b : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 data_a : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 data_b : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 q_a : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 q_b : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT video_mod_mux_clutctr
+	PORT(nRSTO : IN STD_LOGIC;
+		 MAIN_CLK : IN STD_LOGIC;
+		 nFB_CS1 : IN STD_LOGIC;
+		 nFB_CS2 : IN STD_LOGIC;
+		 nFB_CS3 : IN STD_LOGIC;
+		 nFB_WR : IN STD_LOGIC;
+		 nFB_OE : IN STD_LOGIC;
+		 FB_SIZE0 : IN STD_LOGIC;
+		 FB_SIZE1 : IN STD_LOGIC;
+		 nFB_BURST : IN STD_LOGIC;
+		 CLK33M : IN STD_LOGIC;
+		 CLK25M : IN STD_LOGIC;
+		 BLITTER_RUN : IN STD_LOGIC;
+		 CLK_VIDEO : IN STD_LOGIC;
+		 VR_BUSY : IN STD_LOGIC;
+		 FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 VR_D : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+		 COLOR8 : OUT STD_LOGIC;
+		 ACP_CLUT_RD : OUT STD_LOGIC;
+		 COLOR1 : OUT STD_LOGIC;
+		 FALCON_CLUT_RDH : OUT STD_LOGIC;
+		 FALCON_CLUT_RDL : OUT STD_LOGIC;
+		 ST_CLUT_RD : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 VSYNC : OUT STD_LOGIC;
+		 nBLANK : OUT STD_LOGIC;
+		 nSYNC : OUT STD_LOGIC;
+		 nPD_VGA : OUT STD_LOGIC;
+		 FIFO_RDE : OUT STD_LOGIC;
+		 COLOR2 : OUT STD_LOGIC;
+		 COLOR4 : OUT STD_LOGIC;
+		 PIXEL_CLK : OUT STD_LOGIC;
+		 BLITTER_ON : OUT STD_LOGIC;
+		 VIDEO_MOD_TA : OUT STD_LOGIC;
+		 INTER_ZEI : OUT STD_LOGIC;
+		 DOP_FIFO_CLR : OUT STD_LOGIC;
+		 VIDEO_RECONFIG : OUT STD_LOGIC;
+		 VR_WR : OUT STD_LOGIC;
+		 VR_RD : OUT STD_LOGIC;
+		 CLR_FIFO : OUT STD_LOGIC;
+		 ACP_CLUT_WR : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CCR : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 CCSEL : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 CLUT_MUX_ADR : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CLUT_OFF : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 FALCON_CLUT_WR : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 ST_CLUT_WR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 VIDEO_RAM_CTR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+SIGNAL	ACP_CLUT_RD :  STD_LOGIC;
+SIGNAL	ACP_CLUT_WR :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	BLITTER_ADR :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	BLITTER_DACK :  STD_LOGIC_VECTOR(4 DOWNTO 0);
+SIGNAL	BLITTER_DIN :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	BLITTER_DOUT :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	BLITTER_ON :  STD_LOGIC;
+SIGNAL	BLITTER_RUN :  STD_LOGIC;
+SIGNAL	BLITTER_SIG :  STD_LOGIC;
+SIGNAL	BLITTER_TA :  STD_LOGIC;
+SIGNAL	BLITTER_WR :  STD_LOGIC;
+SIGNAL	CC16 :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	CC24 :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	CCA :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	CCF :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	CCR :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	CCS :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	CCSEL :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+SIGNAL	CLR_FIFO :  STD_LOGIC;
+SIGNAL	CLUT_ADR :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CLUT_ADR1A :  STD_LOGIC;
+SIGNAL	CLUT_ADR2A :  STD_LOGIC;
+SIGNAL	CLUT_ADR3A :  STD_LOGIC;
+SIGNAL	CLUT_ADR4A :  STD_LOGIC;
+SIGNAL	CLUT_ADR5A :  STD_LOGIC;
+SIGNAL	CLUT_ADR6A :  STD_LOGIC;
+SIGNAL	CLUT_ADR7A :  STD_LOGIC;
+SIGNAL	CLUT_MUX_ADR :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	CLUT_OFF :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	COLOR1 :  STD_LOGIC;
+SIGNAL	COLOR2 :  STD_LOGIC;
+SIGNAL	COLOR4 :  STD_LOGIC;
+SIGNAL	COLOR8 :  STD_LOGIC;
+SIGNAL	DDR_FB :  STD_LOGIC_VECTOR(4 DOWNTO 0);
+SIGNAL	DDR_WR :  STD_LOGIC;
+SIGNAL	DDRWR_D_SEL :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	DOP_FIFO_CLR :  STD_LOGIC;
+SIGNAL	FALCON_CLUT_RDH :  STD_LOGIC;
+SIGNAL	FALCON_CLUT_RDL :  STD_LOGIC;
+SIGNAL	FALCON_CLUT_WR :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	FB_DDR :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	FB_LE :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	FB_VDOE :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	FIFO_D :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	FIFO_MW :  STD_LOGIC_VECTOR(8 DOWNTO 0);
+SIGNAL	FIFO_RDE :  STD_LOGIC;
+SIGNAL	FIFO_WRE :  STD_LOGIC;
+SIGNAL	INTER_ZEI :  STD_LOGIC;
+SIGNAL	nFB_BURST :  STD_LOGIC;
+SIGNAL	PIXEL_CLK_ALTERA_SYNTHESIZED :  STD_LOGIC;
+SIGNAL	SR_BLITTER_DACK :  STD_LOGIC;
+SIGNAL	SR_DDR_FB :  STD_LOGIC;
+SIGNAL	SR_DDR_WR :  STD_LOGIC;
+SIGNAL	SR_DDRWR_D_SEL :  STD_LOGIC;
+SIGNAL	SR_FIFO_WRE :  STD_LOGIC;
+SIGNAL	SR_VDMP :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ST_CLUT_RD :  STD_LOGIC;
+SIGNAL	ST_CLUT_WR :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	VDM_SEL :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	VDMA :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	VDMB :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	VDMC :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	VDMP :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	VDOUT_OE :  STD_LOGIC;
+SIGNAL	VDP_IN :  STD_LOGIC_VECTOR(63 DOWNTO 0);
+SIGNAL	VDP_OUT :  STD_LOGIC_VECTOR(63 DOWNTO 0);
+SIGNAL	VDR :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	VDVZ :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	VIDEO_DDR_TA :  STD_LOGIC;
+SIGNAL	VIDEO_MOD_TA :  STD_LOGIC;
+SIGNAL	VIDEO_RAM_CTR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ZR_C8 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ZR_C8B :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_60 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	DFF_inst93 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_61 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_11 :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_12 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_13 :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_14 :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_15 :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_16 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_18 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_19 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_20 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_21 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_22 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_23 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_24 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_25 :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_26 :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_62 :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_29 :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_30 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_31 :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_32 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_33 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_34 :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_63 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_36 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_38 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_40 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_41 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_42 :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_43 :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_44 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_45 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_46 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_47 :  STD_LOGIC_VECTOR(6 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_48 :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	DFF_inst91 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_64 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_49 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_50 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_51 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_52 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_53 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_54 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_55 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_56 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_57 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_65 :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+
+SIGNAL	GDFX_TEMP_SIGNAL_7 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_8 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_9 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_10 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_11 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_12 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_13 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_14 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_15 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_1 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_2 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_3 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_4 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_5 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_6 :  STD_LOGIC_VECTOR(127 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_0 :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	GDFX_TEMP_SIGNAL_16 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+BEGIN 
+VB(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(7 DOWNTO 0);
+VG(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(15 DOWNTO 8);
+VR(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(23 DOWNTO 16);
+SYNTHESIZED_WIRE_0 <= '0';
+SYNTHESIZED_WIRE_1 <= '0';
+SYNTHESIZED_WIRE_2 <= '0';
+SYNTHESIZED_WIRE_3 <= '0';
+SYNTHESIZED_WIRE_4 <= '0';
+SYNTHESIZED_WIRE_5 <= '0';
+SYNTHESIZED_WIRE_19 <= '0';
+SYNTHESIZED_WIRE_20 <= '0';
+SYNTHESIZED_WIRE_21 <= '0';
+SYNTHESIZED_WIRE_22 <= '0';
+SYNTHESIZED_WIRE_23 <= '0';
+SYNTHESIZED_WIRE_24 <= '0';
+SYNTHESIZED_WIRE_55 <= '0';
+SYNTHESIZED_WIRE_56 <= '0';
+SYNTHESIZED_WIRE_57 <= '0';
+
+GDFX_TEMP_SIGNAL_7 <= (VDMB(119 DOWNTO 0) & VDMA(127 DOWNTO 120));
+GDFX_TEMP_SIGNAL_8 <= (VDMB(111 DOWNTO 0) & VDMA(127 DOWNTO 112));
+GDFX_TEMP_SIGNAL_9 <= (VDMB(103 DOWNTO 0) & VDMA(127 DOWNTO 104));
+GDFX_TEMP_SIGNAL_10 <= (VDMB(95 DOWNTO 0) & VDMA(127 DOWNTO 96));
+GDFX_TEMP_SIGNAL_11 <= (VDMB(87 DOWNTO 0) & VDMA(127 DOWNTO 88));
+GDFX_TEMP_SIGNAL_12 <= (VDMB(79 DOWNTO 0) & VDMA(127 DOWNTO 80));
+GDFX_TEMP_SIGNAL_13 <= (VDMB(71 DOWNTO 0) & VDMA(127 DOWNTO 72));
+GDFX_TEMP_SIGNAL_14 <= (VDMB(63 DOWNTO 0) & VDMA(127 DOWNTO 64));
+GDFX_TEMP_SIGNAL_15 <= (VDMB(55 DOWNTO 0) & VDMA(127 DOWNTO 56));
+GDFX_TEMP_SIGNAL_1 <= (VDMB(47 DOWNTO 0) & VDMA(127 DOWNTO 48));
+GDFX_TEMP_SIGNAL_2 <= (VDMB(39 DOWNTO 0) & VDMA(127 DOWNTO 40));
+GDFX_TEMP_SIGNAL_3 <= (VDMB(31 DOWNTO 0) & VDMA(127 DOWNTO 32));
+GDFX_TEMP_SIGNAL_4 <= (VDMB(23 DOWNTO 0) & VDMA(127 DOWNTO 24));
+GDFX_TEMP_SIGNAL_5 <= (VDMB(15 DOWNTO 0) & VDMA(127 DOWNTO 16));
+GDFX_TEMP_SIGNAL_6 <= (VDMB(7 DOWNTO 0) & VDMA(127 DOWNTO 8));
+CC16(23) <= GDFX_TEMP_SIGNAL_0(15);
+CC16(22) <= GDFX_TEMP_SIGNAL_0(14);
+CC16(21) <= GDFX_TEMP_SIGNAL_0(13);
+CC16(20) <= GDFX_TEMP_SIGNAL_0(12);
+CC16(19) <= GDFX_TEMP_SIGNAL_0(11);
+CC16(15) <= GDFX_TEMP_SIGNAL_0(10);
+CC16(14) <= GDFX_TEMP_SIGNAL_0(9);
+CC16(13) <= GDFX_TEMP_SIGNAL_0(8);
+CC16(12) <= GDFX_TEMP_SIGNAL_0(7);
+CC16(11) <= GDFX_TEMP_SIGNAL_0(6);
+CC16(10) <= GDFX_TEMP_SIGNAL_0(5);
+CC16(7) <= GDFX_TEMP_SIGNAL_0(4);
+CC16(6) <= GDFX_TEMP_SIGNAL_0(3);
+CC16(5) <= GDFX_TEMP_SIGNAL_0(2);
+CC16(4) <= GDFX_TEMP_SIGNAL_0(1);
+CC16(3) <= GDFX_TEMP_SIGNAL_0(0);
+
+CC16(18) <= GDFX_TEMP_SIGNAL_16(7);
+CC16(17) <= GDFX_TEMP_SIGNAL_16(6);
+CC16(16) <= GDFX_TEMP_SIGNAL_16(5);
+CC16(9) <= GDFX_TEMP_SIGNAL_16(4);
+CC16(8) <= GDFX_TEMP_SIGNAL_16(3);
+CC16(2) <= GDFX_TEMP_SIGNAL_16(2);
+CC16(1) <= GDFX_TEMP_SIGNAL_16(1);
+CC16(0) <= GDFX_TEMP_SIGNAL_16(0);
+
+
+
+b2v_ACP_CLUT_RAM : altdpram2
+PORT MAP(wren_a => ACP_CLUT_WR(3),
+		 wren_b => SYNTHESIZED_WIRE_0,
+		 clock_a => MAIN_CLK,
+		 clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 address_a => FB_ADR(9 DOWNTO 2),
+		 address_b => ZR_C8B,
+		 data_a => FB_AD(7 DOWNTO 0),
+		 q_a => SYNTHESIZED_WIRE_30,
+		 q_b => CCA(7 DOWNTO 0));
+
+
+b2v_ACP_CLUT_RAM54 : altdpram2
+PORT MAP(wren_a => ACP_CLUT_WR(2),
+		 wren_b => SYNTHESIZED_WIRE_1,
+		 clock_a => MAIN_CLK,
+		 clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 address_a => FB_ADR(9 DOWNTO 2),
+		 address_b => ZR_C8B,
+		 data_a => FB_AD(15 DOWNTO 8),
+		 q_a => SYNTHESIZED_WIRE_32,
+		 q_b => CCA(15 DOWNTO 8));
+
+
+b2v_ACP_CLUT_RAM55 : altdpram2
+PORT MAP(wren_a => ACP_CLUT_WR(1),
+		 wren_b => SYNTHESIZED_WIRE_2,
+		 clock_a => MAIN_CLK,
+		 clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 address_a => FB_ADR(9 DOWNTO 2),
+		 address_b => ZR_C8B,
+		 data_a => FB_AD(23 DOWNTO 16),
+		 q_a => SYNTHESIZED_WIRE_33,
+		 q_b => CCA(23 DOWNTO 16));
+
+
+b2v_BLITTER : blitter
+PORT MAP(nRSTO => nRSTO,
+		 MAIN_CLK => MAIN_CLK,
+		 FB_ALE => FB_ALE,
+		 nFB_WR => nFB_WR,
+		 nFB_OE => nFB_OE,
+		 FB_SIZE0 => FB_SIZE0,
+		 FB_SIZE1 => FB_SIZE1,
+		 BLITTER_ON => BLITTER_ON,
+		 nFB_CS1 => nFB_CS1,
+		 nFB_CS2 => nFB_CS2,
+		 nFB_CS3 => nFB_CS3,
+		 DDRCLK0 => DDRCLK(0),
+		 BLITTER_DACK => BLITTER_DACK,
+		 BLITTER_DIN => BLITTER_DIN,
+		 FB_AD => FB_AD,
+		 FB_ADR => FB_ADR,
+		 VIDEO_RAM_CTR => VIDEO_RAM_CTR,
+		 BLITTER_RUN => BLITTER_RUN,
+		 BLITTER_SIG => BLITTER_SIG,
+		 BLITTER_WR => BLITTER_WR,
+		 BLITTER_TA => BLITTER_TA,
+		 BLITTER_ADR => BLITTER_ADR,
+		 BLITTER_DOUT => BLITTER_DOUT);
+
+
+b2v_DDR_CTR : ddr_ctr
+PORT MAP(nFB_CS1 => nFB_CS1,
+		 nFB_CS2 => nFB_CS2,
+		 nFB_CS3 => nFB_CS3,
+		 nFB_OE => nFB_OE,
+		 FB_SIZE0 => FB_SIZE0,
+		 FB_SIZE1 => FB_SIZE1,
+		 nRSTO => nRSTO,
+		 MAIN_CLK => MAIN_CLK,
+		 FB_ALE => FB_ALE,
+		 nFB_WR => nFB_WR,
+		 DDR_SYNC_66M => DDR_SYNC_66M,
+		 BLITTER_SIG => BLITTER_SIG,
+		 BLITTER_WR => BLITTER_WR,
+		 DDRCLK0 => DDRCLK(0),
+		 CLK33M => CLK33M,
+		 CLR_FIFO => CLR_FIFO,
+		 BLITTER_ADR => BLITTER_ADR,
+		 FB_AD => FB_AD,
+		 FB_ADR => FB_ADR,
+		 FIFO_MW => FIFO_MW,
+		 VIDEO_RAM_CTR => VIDEO_RAM_CTR,
+		 nVWE => nVWE,
+		 nVRAS => nVRAS,
+		 nVCS => nVCS,
+		 VCKE => VCKE,
+		 nVCAS => nVCAS,
+		 SR_FIFO_WRE => SR_FIFO_WRE,
+		 SR_DDR_FB => SR_DDR_FB,
+		 SR_DDR_WR => SR_DDR_WR,
+		 SR_DDRWR_D_SEL => SR_DDRWR_D_SEL,
+		 VIDEO_DDR_TA => VIDEO_DDR_TA,
+		 SR_BLITTER_DACK => SR_BLITTER_DACK,
+		 DDRWR_D_SEL1 => DDRWR_D_SEL(1),
+		 BA => BA,
+		 FB_LE => FB_LE,
+		 FB_VDOE => FB_VDOE,
+		 SR_VDMP => SR_VDMP,
+		 VA => VA,
+		 VDM_SEL => VDM_SEL);
+
+
+b2v_FALCON_CLUT_BLUE : altdpram1
+PORT MAP(wren_a => FALCON_CLUT_WR(3),
+		 wren_b => SYNTHESIZED_WIRE_3,
+		 clock_a => MAIN_CLK,
+		 clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 address_a => FB_ADR(9 DOWNTO 2),
+		 address_b => CLUT_ADR,
+		 data_a => FB_AD(23 DOWNTO 18),
+		 q_a => SYNTHESIZED_WIRE_45,
+		 q_b => CCF(7 DOWNTO 2));
+
+
+b2v_FALCON_CLUT_GREEN : altdpram1
+PORT MAP(wren_a => FALCON_CLUT_WR(1),
+		 wren_b => SYNTHESIZED_WIRE_4,
+		 clock_a => MAIN_CLK,
+		 clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 address_a => FB_ADR(9 DOWNTO 2),
+		 address_b => CLUT_ADR,
+		 data_a => FB_AD(23 DOWNTO 18),
+		 q_a => SYNTHESIZED_WIRE_44,
+		 q_b => CCF(15 DOWNTO 10));
+
+
+b2v_FALCON_CLUT_RED : altdpram1
+PORT MAP(wren_a => FALCON_CLUT_WR(0),
+		 wren_b => SYNTHESIZED_WIRE_5,
+		 clock_a => MAIN_CLK,
+		 clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 address_a => FB_ADR(9 DOWNTO 2),
+		 address_b => CLUT_ADR,
+		 data_a => FB_AD(31 DOWNTO 26),
+		 q_a => SYNTHESIZED_WIRE_41,
+		 q_b => CCF(23 DOWNTO 18));
+
+
+b2v_inst : lpm_fifo_dc0
+PORT MAP(wrreq => FIFO_WRE,
+		 wrclk => DDRCLK(0),
+		 rdreq => SYNTHESIZED_WIRE_60,
+		 rdclk => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 aclr => CLR_FIFO,
+		 data => VDMC,
+		 q => SYNTHESIZED_WIRE_63,
+		 wrusedw => FIFO_MW);
+
+
+b2v_inst1 : altddio_bidir0
+PORT MAP(oe => VDOUT_OE,
+		 inclock => DDRCLK(1),
+		 outclock => DDRCLK(3),
+		 datain_h => VDP_OUT(63 DOWNTO 32),
+		 datain_l => VDP_OUT(31 DOWNTO 0),
+		 padio => VD,
+		 combout => SYNTHESIZED_WIRE_15,
+		 dataout_h => VDP_IN(31 DOWNTO 0),
+		 dataout_l => VDP_IN(63 DOWNTO 32));
+
+
+b2v_inst10 : lpm_ff4
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data => SYNTHESIZED_WIRE_7,
+		 q => GDFX_TEMP_SIGNAL_0);
+
+
+b2v_inst100 : lpm_muxvdm
+PORT MAP(data0x => VDMB,
+		 data10x => GDFX_TEMP_SIGNAL_1,
+		 data11x => GDFX_TEMP_SIGNAL_2,
+		 data12x => GDFX_TEMP_SIGNAL_3,
+		 data13x => GDFX_TEMP_SIGNAL_4,
+		 data14x => GDFX_TEMP_SIGNAL_5,
+		 data15x => GDFX_TEMP_SIGNAL_6,
+		 data1x => GDFX_TEMP_SIGNAL_7,
+		 data2x => GDFX_TEMP_SIGNAL_8,
+		 data3x => GDFX_TEMP_SIGNAL_9,
+		 data4x => GDFX_TEMP_SIGNAL_10,
+		 data5x => GDFX_TEMP_SIGNAL_11,
+		 data6x => GDFX_TEMP_SIGNAL_12,
+		 data7x => GDFX_TEMP_SIGNAL_13,
+		 data8x => GDFX_TEMP_SIGNAL_14,
+		 data9x => GDFX_TEMP_SIGNAL_15,
+		 sel => VDM_SEL,
+		 result => VDMC);
+
+
+b2v_inst102 : lpm_mux3
+PORT MAP(data1 => DFF_inst93,
+		 data0 => ZR_C8(0),
+		 sel => COLOR1,
+		 result => ZR_C8B(0));
+
+
+CLUT_ADR(4) <= CLUT_OFF(0) OR SYNTHESIZED_WIRE_8;
+
+
+CLUT_ADR(6) <= CLUT_OFF(2) OR SYNTHESIZED_WIRE_9;
+
+
+SYNTHESIZED_WIRE_61 <= COLOR8 OR COLOR4;
+
+
+CLUT_ADR(2) <= CLUT_ADR2A AND SYNTHESIZED_WIRE_61;
+
+
+SYNTHESIZED_WIRE_16 <= COLOR4 OR COLOR8 OR COLOR2;
+
+
+b2v_inst108 : lpm_bustri_long
+PORT MAP(enabledt => FB_VDOE(0),
+		 data => VDR,
+		 tridata => FB_AD);
+
+
+b2v_inst109 : lpm_bustri_long
+PORT MAP(enabledt => FB_VDOE(1),
+		 data => SYNTHESIZED_WIRE_11,
+		 tridata => FB_AD);
+
+
+b2v_inst11 : lpm_ff5
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data => SYNTHESIZED_WIRE_12,
+		 q => ZR_C8);
+
+
+b2v_inst110 : lpm_bustri_long
+PORT MAP(enabledt => FB_VDOE(2),
+		 data => SYNTHESIZED_WIRE_13,
+		 tridata => FB_AD);
+
+
+b2v_inst119 : lpm_bustri_long
+PORT MAP(enabledt => FB_VDOE(3),
+		 data => SYNTHESIZED_WIRE_14,
+		 tridata => FB_AD);
+
+
+b2v_inst12 : lpm_ff1
+PORT MAP(clock => DDRCLK(0),
+		 data => VDP_IN(31 DOWNTO 0),
+		 q => VDVZ(31 DOWNTO 0));
+
+
+b2v_inst13 : lpm_ff0
+PORT MAP(clock => DDR_SYNC_66M,
+		 enable => FB_LE(0),
+		 data => FB_AD,
+		 q => FB_DDR(127 DOWNTO 96));
+
+
+b2v_inst14 : lpm_ff0
+PORT MAP(clock => DDR_SYNC_66M,
+		 enable => FB_LE(1),
+		 data => FB_AD,
+		 q => FB_DDR(95 DOWNTO 64));
+
+
+b2v_inst15 : lpm_ff0
+PORT MAP(clock => DDR_SYNC_66M,
+		 enable => FB_LE(2),
+		 data => FB_AD,
+		 q => FB_DDR(63 DOWNTO 32));
+
+
+b2v_inst16 : lpm_ff0
+PORT MAP(clock => DDR_SYNC_66M,
+		 enable => FB_LE(3),
+		 data => FB_AD,
+		 q => FB_DDR(31 DOWNTO 0));
+
+
+b2v_inst17 : lpm_ff0
+PORT MAP(clock => DDRCLK(0),
+		 enable => DDR_FB(1),
+		 data => VDP_IN(31 DOWNTO 0),
+		 q => SYNTHESIZED_WIRE_11);
+
+
+b2v_inst18 : lpm_ff0
+PORT MAP(clock => DDRCLK(0),
+		 enable => DDR_FB(0),
+		 data => VDP_IN(63 DOWNTO 32),
+		 q => SYNTHESIZED_WIRE_13);
+
+
+b2v_inst19 : lpm_ff0
+PORT MAP(clock => DDRCLK(0),
+		 enable => DDR_FB(0),
+		 data => VDP_IN(31 DOWNTO 0),
+		 q => SYNTHESIZED_WIRE_14);
+
+
+b2v_inst2 : altddio_out0
+PORT MAP(outclock => DDRCLK(3),
+		 datain_h => VDMP(7 DOWNTO 4),
+		 datain_l => VDMP(3 DOWNTO 0),
+		 dataout => VDM);
+
+
+b2v_inst20 : lpm_ff1
+PORT MAP(clock => DDRCLK(0),
+		 data => VDVZ(31 DOWNTO 0),
+		 q => VDVZ(95 DOWNTO 64));
+
+
+b2v_inst21 : lpm_mux0
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data0x => FIFO_D(127 DOWNTO 96),
+		 data1x => FIFO_D(95 DOWNTO 64),
+		 data2x => FIFO_D(63 DOWNTO 32),
+		 data3x => FIFO_D(31 DOWNTO 0),
+		 sel => CLUT_MUX_ADR(1 DOWNTO 0),
+		 result => SYNTHESIZED_WIRE_48);
+
+
+b2v_inst22 : lpm_mux5
+PORT MAP(data0x => FB_DDR(127 DOWNTO 64),
+		 data1x => FB_DDR(63 DOWNTO 0),
+		 data2x => BLITTER_DOUT(127 DOWNTO 64),
+		 data3x => BLITTER_DOUT(63 DOWNTO 0),
+		 sel => DDRWR_D_SEL,
+		 result => VDP_OUT);
+
+
+b2v_inst23 : lpm_constant2
+PORT MAP(		 result => GDFX_TEMP_SIGNAL_16);
+
+
+b2v_inst24 : lpm_mux1
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data0x => FIFO_D(127 DOWNTO 112),
+		 data1x => FIFO_D(111 DOWNTO 96),
+		 data2x => FIFO_D(95 DOWNTO 80),
+		 data3x => FIFO_D(79 DOWNTO 64),
+		 data4x => FIFO_D(63 DOWNTO 48),
+		 data5x => FIFO_D(47 DOWNTO 32),
+		 data6x => FIFO_D(31 DOWNTO 16),
+		 data7x => FIFO_D(15 DOWNTO 0),
+		 sel => CLUT_MUX_ADR(2 DOWNTO 0),
+		 result => SYNTHESIZED_WIRE_7);
+
+
+b2v_inst25 : lpm_mux2
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data0x => FIFO_D(127 DOWNTO 120),
+		 data10x => FIFO_D(47 DOWNTO 40),
+		 data11x => FIFO_D(39 DOWNTO 32),
+		 data12x => FIFO_D(31 DOWNTO 24),
+		 data13x => FIFO_D(23 DOWNTO 16),
+		 data14x => FIFO_D(15 DOWNTO 8),
+		 data15x => FIFO_D(7 DOWNTO 0),
+		 data1x => FIFO_D(119 DOWNTO 112),
+		 data2x => FIFO_D(111 DOWNTO 104),
+		 data3x => FIFO_D(103 DOWNTO 96),
+		 data4x => FIFO_D(95 DOWNTO 88),
+		 data5x => FIFO_D(87 DOWNTO 80),
+		 data6x => FIFO_D(79 DOWNTO 72),
+		 data7x => FIFO_D(71 DOWNTO 64),
+		 data8x => FIFO_D(63 DOWNTO 56),
+		 data9x => FIFO_D(55 DOWNTO 48),
+		 sel => CLUT_MUX_ADR,
+		 result => SYNTHESIZED_WIRE_12);
+
+
+b2v_inst26 : lpm_shiftreg4
+PORT MAP(clock => DDRCLK(0),
+		 shiftin => SR_FIFO_WRE,
+		 shiftout => FIFO_WRE);
+
+
+b2v_inst27 : lpm_latch0
+PORT MAP(gate => DDR_SYNC_66M,
+		 data => SYNTHESIZED_WIRE_15,
+		 q => VDR);
+
+
+
+CLUT_ADR(1) <= CLUT_ADR1A AND SYNTHESIZED_WIRE_16;
+
+
+b2v_inst3 : lpm_ff1
+PORT MAP(clock => DDRCLK(0),
+		 data => VDP_IN(63 DOWNTO 32),
+		 q => VDVZ(63 DOWNTO 32));
+
+
+CLUT_ADR(3) <= SYNTHESIZED_WIRE_61 AND CLUT_ADR3A;
+
+
+CLUT_ADR(5) <= CLUT_OFF(1) OR SYNTHESIZED_WIRE_18;
+
+
+SYNTHESIZED_WIRE_8 <= CLUT_ADR4A AND COLOR8;
+
+
+SYNTHESIZED_WIRE_18 <= CLUT_ADR5A AND COLOR8;
+
+
+SYNTHESIZED_WIRE_9 <= CLUT_ADR6A AND COLOR8;
+
+
+SYNTHESIZED_WIRE_46 <= CLUT_ADR7A AND COLOR8;
+
+
+b2v_inst36 : lpm_ff6
+PORT MAP(clock => DDRCLK(0),
+		 enable => BLITTER_DACK(0),
+		 data => VDVZ,
+		 q => BLITTER_DIN);
+
+
+VDOUT_OE <= DDR_WR OR SR_DDR_WR;
+
+
+
+VIDEO_TA <= BLITTER_TA OR VIDEO_MOD_TA OR VIDEO_DDR_TA;
+
+
+b2v_inst4 : lpm_ff1
+PORT MAP(clock => DDRCLK(0),
+		 data => VDVZ(63 DOWNTO 32),
+		 q => VDVZ(127 DOWNTO 96));
+
+
+b2v_inst40 : mux41_0
+PORT MAP(S0 => COLOR2,
+		 S1 => COLOR4,
+		 D0 => CLUT_ADR6A,
+		 INH => SYNTHESIZED_WIRE_19,
+		 D1 => CLUT_ADR7A,
+		 Q => SYNTHESIZED_WIRE_54);
+
+
+b2v_inst41 : mux41_1
+PORT MAP(S0 => COLOR2,
+		 S1 => COLOR4,
+		 D0 => CLUT_ADR5A,
+		 INH => SYNTHESIZED_WIRE_20,
+		 D1 => CLUT_ADR6A,
+		 Q => SYNTHESIZED_WIRE_53);
+
+
+b2v_inst42 : mux41_2
+PORT MAP(S0 => COLOR2,
+		 D2 => CLUT_ADR7A,
+		 S1 => COLOR4,
+		 D0 => CLUT_ADR4A,
+		 INH => SYNTHESIZED_WIRE_21,
+		 D1 => CLUT_ADR5A,
+		 Q => SYNTHESIZED_WIRE_52);
+
+
+b2v_inst43 : mux41_3
+PORT MAP(S0 => COLOR2,
+		 D2 => CLUT_ADR6A,
+		 S1 => COLOR4,
+		 D0 => CLUT_ADR3A,
+		 INH => SYNTHESIZED_WIRE_22,
+		 D1 => CLUT_ADR4A,
+		 Q => SYNTHESIZED_WIRE_51);
+
+
+b2v_inst44 : mux41_4
+PORT MAP(S0 => COLOR2,
+		 D2 => CLUT_ADR5A,
+		 S1 => COLOR4,
+		 D0 => CLUT_ADR2A,
+		 INH => SYNTHESIZED_WIRE_23,
+		 D1 => CLUT_ADR3A,
+		 Q => SYNTHESIZED_WIRE_50);
+
+
+b2v_inst45 : mux41_5
+PORT MAP(S0 => COLOR2,
+		 D2 => CLUT_ADR4A,
+		 S1 => COLOR4,
+		 D0 => CLUT_ADR1A,
+		 INH => SYNTHESIZED_WIRE_24,
+		 D1 => CLUT_ADR2A,
+		 Q => SYNTHESIZED_WIRE_49);
+
+
+b2v_inst46 : lpm_ff3
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data => SYNTHESIZED_WIRE_25,
+		 q => SYNTHESIZED_WIRE_43);
+
+
+b2v_inst47 : lpm_ff3
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data => CCF,
+		 q => SYNTHESIZED_WIRE_25);
+
+
+
+b2v_inst49 : lpm_ff3
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data => SYNTHESIZED_WIRE_26,
+		 q => SYNTHESIZED_WIRE_42);
+
+
+b2v_inst5 : altddio_out2
+PORT MAP(outclock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 datain_h => SYNTHESIZED_WIRE_62,
+		 datain_l => SYNTHESIZED_WIRE_62,
+		 dataout => SYNTHESIZED_WIRE_65);
+
+
+
+b2v_inst51 : lpm_bustri1
+PORT MAP(enabledt => ST_CLUT_RD,
+		 data => SYNTHESIZED_WIRE_29,
+		 tridata => FB_AD(26 DOWNTO 24));
+
+
+b2v_inst52 : lpm_ff3
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data => CCS,
+		 q => SYNTHESIZED_WIRE_26);
+
+
+b2v_inst53 : lpm_bustri_byt
+PORT MAP(enabledt => ACP_CLUT_RD,
+		 data => SYNTHESIZED_WIRE_30,
+		 tridata => FB_AD(7 DOWNTO 0));
+
+
+b2v_inst54 : lpm_constant0
+PORT MAP(		 result => CCS(20 DOWNTO 16));
+
+
+
+b2v_inst56 : lpm_bustri1
+PORT MAP(enabledt => ST_CLUT_RD,
+		 data => SYNTHESIZED_WIRE_31,
+		 tridata => FB_AD(22 DOWNTO 20));
+
+
+b2v_inst57 : lpm_bustri_byt
+PORT MAP(enabledt => ACP_CLUT_RD,
+		 data => SYNTHESIZED_WIRE_32,
+		 tridata => FB_AD(15 DOWNTO 8));
+
+
+b2v_inst58 : lpm_bustri_byt
+PORT MAP(enabledt => ACP_CLUT_RD,
+		 data => SYNTHESIZED_WIRE_33,
+		 tridata => FB_AD(23 DOWNTO 16));
+
+
+b2v_inst59 : lpm_constant0
+PORT MAP(		 result => CCS(12 DOWNTO 8));
+
+
+
+
+b2v_inst61 : lpm_bustri1
+PORT MAP(enabledt => ST_CLUT_RD,
+		 data => SYNTHESIZED_WIRE_34,
+		 tridata => FB_AD(18 DOWNTO 16));
+
+
+b2v_inst62 : lpm_muxdz
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 clken => FIFO_RDE,
+		 sel => INTER_ZEI,
+		 data0x => SYNTHESIZED_WIRE_63,
+		 data1x => SYNTHESIZED_WIRE_36,
+		 result => FIFO_D);
+
+
+b2v_inst63 : lpm_fifodz
+PORT MAP(wrreq => SYNTHESIZED_WIRE_60,
+		 rdreq => SYNTHESIZED_WIRE_38,
+		 clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 aclr => DOP_FIFO_CLR,
+		 data => SYNTHESIZED_WIRE_63,
+		 q => SYNTHESIZED_WIRE_36);
+
+
+b2v_inst64 : lpm_constant0
+PORT MAP(		 result => CCS(4 DOWNTO 0));
+
+
+SYNTHESIZED_WIRE_60 <= FIFO_RDE AND SYNTHESIZED_WIRE_40;
+
+
+b2v_inst66 : lpm_bustri3
+PORT MAP(enabledt => FALCON_CLUT_RDH,
+		 data => SYNTHESIZED_WIRE_41,
+		 tridata => FB_AD(31 DOWNTO 26));
+
+
+SYNTHESIZED_WIRE_38 <= FIFO_RDE AND INTER_ZEI;
+
+
+
+SYNTHESIZED_WIRE_40 <= NOT(INTER_ZEI);
+
+
+
+b2v_inst7 : lpm_mux6
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data0x => SYNTHESIZED_WIRE_42,
+		 data1x => SYNTHESIZED_WIRE_43,
+		 data4x => CCA,
+		 data5x => CC16,
+		 data6x => CC24(23 DOWNTO 0),
+		 data7x => CCR,
+		 sel => CCSEL,
+		 result => SYNTHESIZED_WIRE_62);
+
+
+b2v_inst70 : lpm_bustri3
+PORT MAP(enabledt => FALCON_CLUT_RDH,
+		 data => SYNTHESIZED_WIRE_44,
+		 tridata => FB_AD(23 DOWNTO 18));
+
+
+b2v_inst71 : lpm_ff6
+PORT MAP(clock => DDRCLK(0),
+		 enable => FIFO_WRE,
+		 data => VDVZ,
+		 q => VDMA);
+
+
+
+
+b2v_inst74 : lpm_bustri3
+PORT MAP(enabledt => FALCON_CLUT_RDL,
+		 data => SYNTHESIZED_WIRE_45,
+		 tridata => FB_AD(23 DOWNTO 18));
+
+
+
+
+b2v_inst77 : lpm_constant1
+PORT MAP(		 result => CCF(1 DOWNTO 0));
+
+
+
+CLUT_ADR(7) <= CLUT_OFF(3) OR SYNTHESIZED_WIRE_46;
+
+
+
+b2v_inst80 : lpm_constant1
+PORT MAP(		 result => CCF(9 DOWNTO 8));
+
+
+b2v_inst81 : lpm_mux4
+PORT MAP(sel => COLOR1,
+		 data0x => ZR_C8(7 DOWNTO 1),
+		 data1x => SYNTHESIZED_WIRE_47,
+		 result => ZR_C8B(7 DOWNTO 1));
+
+
+b2v_inst82 : lpm_constant3
+PORT MAP(		 result => SYNTHESIZED_WIRE_47);
+
+
+b2v_inst83 : lpm_constant1
+PORT MAP(		 result => CCF(17 DOWNTO 16));
+
+
+PROCESS(DDRCLK(0),DDR_WR)
+BEGIN
+if (DDR_WR = '1') THEN
+	VDQS(3) <= DDRCLK(0);
+ELSE
+	VDQS(3) <= 'Z';
+END IF;
+END PROCESS;
+
+
+PROCESS(DDRCLK(0),DDR_WR)
+BEGIN
+if (DDR_WR = '1') THEN
+	VDQS(2) <= DDRCLK(0);
+ELSE
+	VDQS(2) <= 'Z';
+END IF;
+END PROCESS;
+
+
+PROCESS(DDRCLK(0),DDR_WR)
+BEGIN
+if (DDR_WR = '1') THEN
+	VDQS(1) <= DDRCLK(0);
+ELSE
+	VDQS(1) <= 'Z';
+END IF;
+END PROCESS;
+
+
+PROCESS(DDRCLK(0),DDR_WR)
+BEGIN
+if (DDR_WR = '1') THEN
+	VDQS(0) <= DDRCLK(0);
+ELSE
+	VDQS(0) <= 'Z';
+END IF;
+END PROCESS;
+
+
+PROCESS(DDRCLK(3))
+BEGIN
+IF (RISING_EDGE(DDRCLK(3))) THEN
+	DDRWR_D_SEL(0) <= SR_DDRWR_D_SEL;
+END IF;
+END PROCESS;
+
+
+b2v_inst89 : lpm_shiftreg6
+PORT MAP(clock => DDRCLK(0),
+		 shiftin => SR_BLITTER_DACK,
+		 q => BLITTER_DACK);
+
+
+b2v_inst9 : lpm_ff1
+PORT MAP(clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 data => SYNTHESIZED_WIRE_48,
+		 q => CC24);
+
+
+PROCESS(DDRCLK(3))
+BEGIN
+IF (RISING_EDGE(DDRCLK(3))) THEN
+	DDR_WR <= SR_DDR_WR;
+END IF;
+END PROCESS;
+
+
+PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED)
+BEGIN
+IF (RISING_EDGE(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN
+	DFF_inst91 <= CLUT_ADR(0);
+END IF;
+END PROCESS;
+
+
+b2v_inst92 : lpm_shiftreg6
+PORT MAP(clock => DDRCLK(0),
+		 shiftin => SR_DDR_FB,
+		 q => DDR_FB);
+
+
+PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED)
+BEGIN
+IF (RISING_EDGE(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN
+	DFF_inst93 <= DFF_inst91;
+END IF;
+END PROCESS;
+
+
+b2v_inst94 : lpm_ff6
+PORT MAP(clock => DDRCLK(0),
+		 enable => FIFO_WRE,
+		 data => VDMA,
+		 q => VDMB);
+
+
+PROCESS(PIXEL_CLK_ALTERA_SYNTHESIZED)
+BEGIN
+IF (RISING_EDGE(PIXEL_CLK_ALTERA_SYNTHESIZED)) THEN
+	SYNTHESIZED_WIRE_64 <= FIFO_RDE;
+END IF;
+END PROCESS;
+
+
+
+b2v_inst97 : lpm_ff5
+PORT MAP(clock => DDRCLK(2),
+		 data => SR_VDMP,
+		 q => VDMP);
+
+
+b2v_sr0 : lpm_shiftreg0
+PORT MAP(load => SYNTHESIZED_WIRE_64,
+		 clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 shiftin => SYNTHESIZED_WIRE_49,
+		 data => FIFO_D(127 DOWNTO 112),
+		 shiftout => CLUT_ADR(0));
+
+
+b2v_sr1 : lpm_shiftreg0
+PORT MAP(load => SYNTHESIZED_WIRE_64,
+		 clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 shiftin => SYNTHESIZED_WIRE_50,
+		 data => FIFO_D(111 DOWNTO 96),
+		 shiftout => CLUT_ADR1A);
+
+
+b2v_sr2 : lpm_shiftreg0
+PORT MAP(load => SYNTHESIZED_WIRE_64,
+		 clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 shiftin => SYNTHESIZED_WIRE_51,
+		 data => FIFO_D(95 DOWNTO 80),
+		 shiftout => CLUT_ADR2A);
+
+
+b2v_sr3 : lpm_shiftreg0
+PORT MAP(load => SYNTHESIZED_WIRE_64,
+		 clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 shiftin => SYNTHESIZED_WIRE_52,
+		 data => FIFO_D(79 DOWNTO 64),
+		 shiftout => CLUT_ADR3A);
+
+
+b2v_sr4 : lpm_shiftreg0
+PORT MAP(load => SYNTHESIZED_WIRE_64,
+		 clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 shiftin => SYNTHESIZED_WIRE_53,
+		 data => FIFO_D(63 DOWNTO 48),
+		 shiftout => CLUT_ADR4A);
+
+
+b2v_sr5 : lpm_shiftreg0
+PORT MAP(load => SYNTHESIZED_WIRE_64,
+		 clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 shiftin => SYNTHESIZED_WIRE_54,
+		 data => FIFO_D(47 DOWNTO 32),
+		 shiftout => CLUT_ADR5A);
+
+
+b2v_sr6 : lpm_shiftreg0
+PORT MAP(load => SYNTHESIZED_WIRE_64,
+		 clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 shiftin => CLUT_ADR7A,
+		 data => FIFO_D(31 DOWNTO 16),
+		 shiftout => CLUT_ADR6A);
+
+
+b2v_sr7 : lpm_shiftreg0
+PORT MAP(load => SYNTHESIZED_WIRE_64,
+		 clock => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 shiftin => CLUT_ADR(0),
+		 data => FIFO_D(15 DOWNTO 0),
+		 shiftout => CLUT_ADR7A);
+
+
+b2v_ST_CLUT_BLUE : altdpram0
+PORT MAP(wren_a => ST_CLUT_WR(1),
+		 wren_b => SYNTHESIZED_WIRE_55,
+		 clock_a => MAIN_CLK,
+		 clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 address_a => FB_ADR(4 DOWNTO 1),
+		 address_b => CLUT_ADR(3 DOWNTO 0),
+		 data_a => FB_AD(18 DOWNTO 16),
+		 q_a => SYNTHESIZED_WIRE_34,
+		 q_b => CCS(7 DOWNTO 5));
+
+
+b2v_ST_CLUT_GREEN : altdpram0
+PORT MAP(wren_a => ST_CLUT_WR(1),
+		 wren_b => SYNTHESIZED_WIRE_56,
+		 clock_a => MAIN_CLK,
+		 clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 address_a => FB_ADR(4 DOWNTO 1),
+		 address_b => CLUT_ADR(3 DOWNTO 0),
+		 data_a => FB_AD(22 DOWNTO 20),
+		 q_a => SYNTHESIZED_WIRE_31,
+		 q_b => CCS(15 DOWNTO 13));
+
+
+b2v_ST_CLUT_RED : altdpram0
+PORT MAP(wren_a => ST_CLUT_WR(0),
+		 wren_b => SYNTHESIZED_WIRE_57,
+		 clock_a => MAIN_CLK,
+		 clock_b => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 address_a => FB_ADR(4 DOWNTO 1),
+		 address_b => CLUT_ADR(3 DOWNTO 0),
+		 data_a => FB_AD(26 DOWNTO 24),
+		 q_a => SYNTHESIZED_WIRE_29,
+		 q_b => CCS(23 DOWNTO 21));
+
+
+b2v_VIDEO_MOD_MUX_CLUTCTR : video_mod_mux_clutctr
+PORT MAP(nRSTO => nRSTO,
+		 MAIN_CLK => MAIN_CLK,
+		 nFB_CS1 => nFB_CS1,
+		 nFB_CS2 => nFB_CS2,
+		 nFB_CS3 => nFB_CS3,
+		 nFB_WR => nFB_WR,
+		 nFB_OE => nFB_OE,
+		 FB_SIZE0 => FB_SIZE0,
+		 FB_SIZE1 => FB_SIZE1,
+		 nFB_BURST => nFB_BURST,
+		 CLK33M => CLK33M,
+		 CLK25M => CLK25M,
+		 BLITTER_RUN => BLITTER_RUN,
+		 CLK_VIDEO => CLK_VIDEO,
+		 VR_BUSY => VR_BUSY,
+		 FB_AD => FB_AD,
+		 FB_ADR => FB_ADR,
+		 VR_D => VR_D,
+		 COLOR8 => COLOR8,
+		 ACP_CLUT_RD => ACP_CLUT_RD,
+		 COLOR1 => COLOR1,
+		 FALCON_CLUT_RDH => FALCON_CLUT_RDH,
+		 FALCON_CLUT_RDL => FALCON_CLUT_RDL,
+		 ST_CLUT_RD => ST_CLUT_RD,
+		 HSYNC => HSYNC,
+		 VSYNC => VSYNC,
+		 nBLANK => nBLANK,
+		 nSYNC => nSYNC,
+		 nPD_VGA => nPD_VGA,
+		 FIFO_RDE => FIFO_RDE,
+		 COLOR2 => COLOR2,
+		 COLOR4 => COLOR4,
+		 PIXEL_CLK => PIXEL_CLK_ALTERA_SYNTHESIZED,
+		 BLITTER_ON => BLITTER_ON,
+		 VIDEO_MOD_TA => VIDEO_MOD_TA,
+		 INTER_ZEI => INTER_ZEI,
+		 DOP_FIFO_CLR => DOP_FIFO_CLR,
+		 VIDEO_RECONFIG => VIDEO_RECONFIG,
+		 VR_WR => VR_WR,
+		 VR_RD => VR_RD,
+		 CLR_FIFO => CLR_FIFO,
+		 ACP_CLUT_WR => ACP_CLUT_WR,
+		 CCR => CCR,
+		 CCSEL => CCSEL,
+		 CLUT_MUX_ADR => CLUT_MUX_ADR,
+		 CLUT_OFF => CLUT_OFF,
+		 FALCON_CLUT_WR => FALCON_CLUT_WR,
+		 ST_CLUT_WR => ST_CLUT_WR,
+		 VIDEO_RAM_CTR => VIDEO_RAM_CTR);
+
+PIXEL_CLK <= PIXEL_CLK_ALTERA_SYNTHESIZED;
+
+END bdf_type;
\ No newline at end of file
diff --git a/FPGA_quartus_GE/ahdl2v/DDR_CTR.tdf b/FPGA_quartus_GE/ahdl2v/DDR_CTR.tdf
new file mode 100644
index 0000000..1fe3049
--- /dev/null
+++ b/FPGA_quartus_GE/ahdl2v/DDR_CTR.tdf
@@ -0,0 +1,662 @@
+TITLE "DDR_CTR";
+
+-- CREATED BY FREDI ASCHWANDEN
+
+INCLUDE "lpm_bustri_BYT.inc";
+
+-- FIFO WATER MARK
+CONSTANT FIFO_LWM = 0;
+CONSTANT FIFO_MWM = 200;
+CONSTANT FIFO_HWM = 500;
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+SUBDESIGN DDR_CTR
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	FB_ADR[31..0] : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	nFB_CS3 : INPUT;
+	nFB_OE : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	nRSTO : INPUT;
+	MAIN_CLK : INPUT;
+	FB_ALE : INPUT;
+	nFB_WR : INPUT;
+	DDR_SYNC_66M : INPUT;
+	CLR_FIFO : INPUT;
+	VIDEO_RAM_CTR[15..0] : INPUT;
+	BLITTER_ADR[31..0] : INPUT;
+	BLITTER_SIG : INPUT;
+	BLITTER_WR : INPUT;
+	DDRCLK0 : INPUT;
+	CLK33M : INPUT;
+	FIFO_MW[8..0] : INPUT;
+	VA[12..0] : OUTPUT;
+	nVWE : OUTPUT;
+	nVRAS : OUTPUT;
+	nVCS : OUTPUT;
+	VCKE : OUTPUT;
+	nVCAS : OUTPUT;
+	FB_LE[3..0] : OUTPUT;
+	FB_VDOE[3..0] : OUTPUT;
+	SR_FIFO_WRE : OUTPUT;
+	SR_DDR_FB : OUTPUT;
+	SR_DDR_WR : OUTPUT;
+	SR_DDRWR_D_SEL : OUTPUT;
+	SR_VDMP[7..0] : OUTPUT;
+	VIDEO_DDR_TA : OUTPUT;
+	SR_BLITTER_DACK : OUTPUT;
+	BA[1..0] : OUTPUT;
+	DDRWR_D_SEL1 : OUTPUT;
+	VDM_SEL[3..0] : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	FB_REGDDR				:MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);	
+	DDR_SM					:MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8,					-- START (NORMAL 8 CYCLES TOTAL = 60ns)
+													   DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, 		 					-- CONFIG 
+												                   DS_T4R,DS_T5R,										-- READ CPU UND BLITTER,  
+												                   DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W,		 	-- WRITE CPU UND BLITTER
+												                   DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, 	-- READ FIFO
+																				 DS_CB6,       DS_CB8,					-- CLOSE FIFO BANK
+												       DS_R2,DS_R3,DS_R4, DS_R5, DS_R6);		 						-- REFRESH 10X7.5NS=75NS
+	LINE					:NODE;
+	FB_B[3..0]				:NODE;
+	VCAS					:NODE;
+	VRAS					:NODE;
+	VWE						:NODE;
+	VA_P[12..0]				:DFF;
+	BA_P[1..0]				:DFF;
+	VA_S[12..0]				:DFF;
+	BA_S[1..0]				:DFF;
+	MCS[1..0]				:DFF;
+	CPU_DDR_SYNC			:DFF;
+	DDR_SEL					:NODE;
+	DDR_CS					:DFFE;
+	DDR_CONFIG				:NODE;
+	SR_DDR_WR				:DFF;
+	SR_DDRWR_D_SEL			:DFF;
+	SR_VDMP[7..0] 			:DFF;
+	CPU_ROW_ADR[12..0]		:NODE;
+	CPU_BA[1..0]			:NODE;
+	CPU_COL_ADR[9..0]		:NODE;
+	CPU_SIG					:NODE;
+	CPU_REQ					:DFF;
+	CPU_AC					:DFF;
+	BUS_CYC					:DFF;
+	BUS_CYC_END				:NODE;
+	BLITTER_REQ				:DFF;
+	BLITTER_AC				:DFF;
+	BLITTER_ROW_ADR[12..0]	:NODE;
+	BLITTER_BA[1..0]		:NODE;
+	BLITTER_COL_ADR[9..0]	:NODE;
+	FIFO_REQ				:DFF;
+	FIFO_AC					:DFF;
+	FIFO_ROW_ADR[12..0]		:NODE;
+	FIFO_BA[1..0]			:NODE;
+	FIFO_COL_ADR[9..0]		:NODE;
+	FIFO_ACTIVE				:NODE;
+	CLR_FIFO_SYNC			:DFF;
+	CLEAR_FIFO_CNT			:DFF;
+	STOP					:DFF;
+	SR_FIFO_WRE				:DFF;
+	FIFO_BANK_OK			:DFF;
+	FIFO_BANK_NOT_OK		:NODE;
+	DDR_REFRESH_ON			:NODE;
+	DDR_REFRESH_CNT[10..0]	:DFF;
+	DDR_REFRESH_REQ			:DFF;
+	DDR_REFRESH_SIG[3..0]	:DFFE;
+	REFRESH_TIME			:DFF;
+	VIDEO_BASE_L_D[7..0]	:DFFE;
+	VIDEO_BASE_L			:NODE;
+	VIDEO_BASE_M_D[7..0]	:DFFE;
+	VIDEO_BASE_M			:NODE;
+	VIDEO_BASE_H_D[7..0]	:DFFE;
+	VIDEO_BASE_H			:NODE;
+	VIDEO_BASE_X_D[2..0]	:DFFE;
+	VIDEO_BASE_X_D_FULL[7..0]	:NODE;
+	VIDEO_ADR_CNT[22..0]	:DFFE;
+	VIDEO_CNT_L				:NODE;
+	VIDEO_CNT_M				:NODE;
+	VIDEO_CNT_H				:NODE;
+	VIDEO_BASE_ADR[22..0]	:NODE;
+	VIDEO_ACT_ADR[26..0]	:NODE;
+	
+BEGIN
+	LINE =  FB_SIZE0 &  FB_SIZE1;
+-- BYT SELECT
+	FB_B0 = FB_ADR[1..0]==0 								-- ADR==0
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR)  --------------------------------------------------
+	FB_REGDDR.CLK = MAIN_CLK;
+	CASE FB_REGDDR IS
+		WHEN FR_WAIT => 
+			FB_LE0   = !nFB_WR;
+			IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN		-- LOS WENN BEREIT ODER IMMER BEI LINE WRITE
+				FB_REGDDR = FR_S0;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S0 =>
+			IF DDR_CS THEN
+				FB_LE0   = !nFB_WR;
+				VIDEO_DDR_TA = VCC;
+				IF LINE THEN							
+					FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
+					FB_REGDDR = FR_S1;
+				ELSE
+					BUS_CYC_END = VCC;
+					FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
+					FB_REGDDR = FR_WAIT;
+				END IF;
+			ELSE
+				FB_REGDDR = FR_WAIT;	
+			END IF;
+		WHEN FR_S1 => 
+			IF DDR_CS THEN
+				FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
+				FB_LE1   = !nFB_WR;
+				VIDEO_DDR_TA = VCC;
+				FB_REGDDR = FR_S2;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S2 => 
+			IF DDR_CS THEN
+				FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
+				FB_LE2   = !nFB_WR;
+				IF !BUS_CYC & LINE & !nFB_WR THEN		-- BEI LINE WRITE EVT. WARTEN
+					FB_REGDDR = FR_S2;
+				ELSE
+					VIDEO_DDR_TA = VCC;
+					FB_REGDDR = FR_S3;
+				END IF;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+		WHEN FR_S3 => 
+			IF DDR_CS THEN
+				FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
+				FB_LE3   = !nFB_WR;
+				VIDEO_DDR_TA = VCC;
+				BUS_CYC_END = VCC;
+				FB_REGDDR = FR_WAIT;
+			ELSE
+				FB_REGDDR = FR_WAIT;
+			END IF;
+	END CASE;
+-- DDR STEUERUNG -----------------------------------------------------
+-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; 
+	VCKE = VIDEO_RAM_CTR0;
+	nVCS = !VIDEO_RAM_CTR1;
+	DDR_REFRESH_ON = VIDEO_RAM_CTR2;
+	DDR_CONFIG = VIDEO_RAM_CTR3;	
+	FIFO_ACTIVE = VIDEO_RAM_CTR8;
+--------------------------------
+	CPU_ROW_ADR[] = FB_ADR[26..14];
+	CPU_BA[] = FB_ADR[13..12];
+	CPU_COL_ADR[] = FB_ADR[11..2];
+	nVRAS = !VRAS;
+	nVCAS = !VCAS;
+	nVWE = !VWE;
+	SR_DDR_WR.CLK = DDRCLK0;
+	SR_DDRWR_D_SEL.CLK = DDRCLK0;
+	SR_VDMP[7..0].CLK = DDRCLK0;
+	SR_FIFO_WRE.CLK = DDRCLK0; 
+	CPU_AC.CLK = DDRCLK0;
+	FIFO_AC.CLK = DDRCLK0;
+	BLITTER_AC.CLK = DDRCLK0;
+	DDRWR_D_SEL1 = BLITTER_AC;
+-- SELECT LOGIC
+	DDR_SEL  = FB_ALE & FB_AD[31..30]==B"01";
+	DDR_CS.CLK = MAIN_CLK;
+	DDR_CS.ENA = FB_ALE;
+	DDR_CS	 = DDR_SEL;
+-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER
+	CPU_SIG = DDR_SEL & (nFB_WR # !LINE)  & !DDR_CONFIG					-- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
+			# DDR_SEL          			  &  DDR_CONFIG					-- CONFIG SOFORT LOS
+			# FB_REGDDR==FR_S1 & !nFB_WR; 								-- LINE WRITE SPÄTER
+	CPU_REQ.CLK = DDR_SYNC_66M;
+	CPU_REQ = CPU_SIG 
+			# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC;		-- HALTEN BUS CYC BEGONNEN ODER FERTIG
+	BUS_CYC.CLK = DDRCLK0;
+	BUS_CYC = BUS_CYC & !BUS_CYC_END;
+	-- STATE MACHINE SYNCHRONISIEREN -----------------
+	MCS[].CLK = DDRCLK0;
+	MCS0 = MAIN_CLK;
+	MCS1 = MCS0;		
+	CPU_DDR_SYNC.CLK = DDRCLK0;
+	CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS;				-- NUR 1 WENN EIN
+	---------------------------------------------------
+	VA_S[].CLK = DDRCLK0;
+	BA_S[].CLK = DDRCLK0;
+	VA[] =  VA_S[];
+	BA[] =  BA_S[];
+	VA_P[].CLK = DDRCLK0;
+	BA_P[].CLK = DDRCLK0;
+-- DDR STATE MACHINE  -----------------------------------------------
+	DDR_SM.CLK = DDRCLK0;
+	CASE DDR_SM IS
+		WHEN DS_T1 =>
+			IF DDR_REFRESH_REQ THEN
+				DDR_SM = DS_R2;
+			ELSE
+				IF CPU_DDR_SYNC THEN							-- SYNCHRON UND EIN?
+					IF DDR_CONFIG THEN							-- JA
+						DDR_SM = DS_C2;
+					ELSE
+						IF CPU_REQ THEN							-- BEI WAIT UND LINE WRITE
+							VA_S[] = CPU_ROW_ADR[];
+							BA_S[] = CPU_BA[];
+							CPU_AC = VCC;
+							BUS_CYC = VCC;
+							DDR_SM = DS_T2B;
+						ELSE
+							IF FIFO_REQ # !BLITTER_REQ THEN			-- FIFO IST DEFAULT
+								VA_P[] = FIFO_ROW_ADR[];
+								BA_P[] = FIFO_BA[];
+								FIFO_AC = VCC;						-- VORBESETZEN
+							ELSE
+								VA_P[] = BLITTER_ROW_ADR[];
+								BA_P[] = BLITTER_BA[];
+								BLITTER_AC = VCC;					-- VORBESETZEN
+							END IF;
+							DDR_SM = DS_T2A;
+						END IF;
+					END IF;
+				ELSE
+					DDR_SM = DS_T1;									-- NEIN ->SYNCHRONISIEREN
+				END IF;
+			END IF;
+			
+		WHEN DS_T2A =>												-- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK ***
+			IF DDR_SEL & (nFB_WR # !LINE) THEN
+				VRAS = VCC;
+				VA[] = FB_AD[26..14];
+				BA[] = FB_AD[13..12]; 
+				VA_S[10] = VCC;										-- AUTO PRECHARGE DA NICHT FIFO PAGE  
+				CPU_AC = VCC;
+				BUS_CYC = VCC;										-- BUS CYCLUS LOSTRETEN
+			ELSE
+				VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ;
+				VA[] = VA_P[];
+				BA[] = BA_P[]; 
+				VA_S[10] = !(FIFO_AC & FIFO_REQ);
+				FIFO_BANK_OK = FIFO_AC & FIFO_REQ;
+				FIFO_AC = FIFO_AC & FIFO_REQ;
+				BLITTER_AC = BLITTER_AC & BLITTER_REQ;
+			END IF;	
+			DDR_SM = DS_T3;
+
+		WHEN DS_T2B =>
+			VRAS = VCC;
+			FIFO_BANK_NOT_OK = VCC;
+			CPU_AC = VCC;
+			BUS_CYC = VCC;											-- BUS CYCLUS LOSTRETEN
+			DDR_SM = DS_T3;
+
+		WHEN DS_T3 =>
+			CPU_AC = CPU_AC;
+			FIFO_AC = FIFO_AC;
+			BLITTER_AC = BLITTER_AC;
+			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
+			IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN
+				DDR_SM = DS_T4W;
+			ELSE
+				IF CPU_AC THEN										-- CPU?
+					VA_S[9..0] = CPU_COL_ADR[];
+					BA_S[] = CPU_BA[];
+					DDR_SM = DS_T4R;												 
+				ELSE
+					IF FIFO_AC THEN									-- FIFO?
+						VA_S[9..0] = FIFO_COL_ADR[];
+						BA_S[] = FIFO_BA[];
+						DDR_SM = DS_T4F;
+					ELSE
+						IF BLITTER_AC THEN
+							VA_S[9..0] = BLITTER_COL_ADR[];
+							BA_S[] = BLITTER_BA[];
+							DDR_SM = DS_T4R;												 
+						ELSE
+							DDR_SM = DS_N8;
+						END IF;
+					END IF;
+				END IF;
+			END IF;
+-- READ			
+		WHEN DS_T4R =>
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			VCAS = VCC;															
+			SR_DDR_FB = CPU_AC;										-- READ DATEN FÜR CPU
+			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER DACK AND BLITTER LATCH DATEN
+			DDR_SM = DS_T5R;	
+			
+		WHEN DS_T5R =>
+ 			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			IF FIFO_REQ & FIFO_BANK_OK THEN							-- FIFO READ EINSCHIEBEN WENN BANK OK
+ 				VA_S[9..0] = FIFO_COL_ADR[];
+ 				VA_S[10] = GND;										-- MANUEL PRECHARGE
+ 				BA_S[] = FIFO_BA[];
+				DDR_SM = DS_T6F;
+ 			ELSE	
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
+				DDR_SM = DS_CB6;
+			END IF;
+-- WRITE			
+		WHEN DS_T4W =>
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			SR_BLITTER_DACK = BLITTER_AC;							-- BLITTER ACK AND BLITTER LATCH DATEN
+			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
+ 			DDR_SM = DS_T5W;
+			
+		WHEN DS_T5W =>
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			VA_S[9..0] = CPU_AC     & CPU_COL_ADR[]
+					   # BLITTER_AC & BLITTER_COL_ADR[];
+			VA_S[10] = VA_S[10]; 									-- AUTO PRECHARGE WENN NICHT FIFO PAGE  
+			BA_S[]  = CPU_AC     & CPU_BA[]
+				    # BLITTER_AC & BLITTER_BA[];
+			SR_VDMP[7..4] = FB_B[];									-- BYTE ENABLE WRITE
+			SR_VDMP[3..0] = LINE & B"1111";							-- LINE ENABLE WRITE
+			DDR_SM = DS_T6W;
+			
+		WHEN DS_T6W =>								 
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			VCAS = VCC;															
+			VWE  = VCC;
+			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITER
+			SR_DDRWR_D_SEL = VCC;									-- 2. HÄLFTE WRITE DATEN SELEKTIEREN
+			SR_VDMP[] = LINE & B"11111111";							-- WENN LINE DANN ACTIV 
+			DDR_SM = DS_T7W;
+
+		WHEN DS_T7W =>								 
+			CPU_AC = CPU_AC;
+			BLITTER_AC = BLITTER_AC;
+			SR_DDR_WR = VCC;										-- WRITE COMMAND CPU UND BLITTER IF WRITE
+			SR_DDRWR_D_SEL = VCC;									-- 2. HÄLFTE WRITE DATEN SELEKTIEREN
+			DDR_SM = DS_T8W;
+
+		WHEN DS_T8W =>								 
+			DDR_SM = DS_T9W;
+
+		WHEN DS_T9W =>								 
+			IF FIFO_REQ & FIFO_BANK_OK  THEN
+				VA_S[9..0] = FIFO_COL_ADR[];
+				VA_S[10] = GND;										-- NON AUTO PRECHARGE  
+				BA_S[] = FIFO_BA[];
+				DDR_SM = DS_T6F;
+			ELSE
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
+				DDR_SM = DS_CB6;
+			END IF;
+-- FIFO READ 
+		WHEN DS_T4F =>
+			VCAS = VCC;															
+			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
+			DDR_SM = DS_T5F;
+			
+		WHEN DS_T5F =>
+			IF FIFO_REQ THEN
+				IF VIDEO_ADR_CNT[7..0]==H"FF" THEN					-- NEUE PAGE?
+					VA_S[10] = VCC;									-- ALLE PAGES SCHLIESSEN  
+					DDR_SM = DS_CB6;								-- BANK SCHLIESSEN
+				ELSE
+					VA_S[9..0] = FIFO_COL_ADR[]+4;
+					VA_S[10] = GND;									-- NON AUTO PRECHARGE  
+					BA_S[] = FIFO_BA[];
+					DDR_SM = DS_T6F;
+				END IF;											 
+			ELSE
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESSEN  
+				DDR_SM = DS_CB6;									-- NOCH OFFEN LASSEN
+			END IF;
+			
+		WHEN DS_T6F =>
+			VCAS = VCC;															
+			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
+			DDR_SM = DS_T7F;
+																							 
+		WHEN DS_T7F =>
+			IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN	
+				VA_S[10] = VCC;										-- ALLE PAGES SCHLIESEN 
+				DDR_SM = DS_CB8;									-- BANK SCHLIESSEN
+			ELSE
+				IF FIFO_REQ THEN
+					IF VIDEO_ADR_CNT[7..0]==H"FF" THEN				-- NEUE PAGE?
+						VA_S[10] = VCC;								-- ALLE PAGES SCHLIESSEN 
+						DDR_SM = DS_CB8;							-- BANK SCHLIESSEN
+					ELSE
+						VA_S[9..0] = FIFO_COL_ADR[]+4;
+						VA_S[10] = GND;								-- NON AUTO PRECHARGE  
+						BA_S[] = FIFO_BA[];
+						DDR_SM = DS_T8F;
+					END IF;											 
+				ELSE
+					VA_S[10] = VCC;									-- ALLE PAGES SCHLIESEN 
+					DDR_SM = DS_CB8;								-- BANK SCHLIESSEN
+				END IF;
+			END IF;
+			
+		WHEN DS_T8F =>
+			VCAS = VCC;															
+			SR_FIFO_WRE = VCC;										-- DATEN WRITE FIFO
+			IF FIFO_MW[]<FIFO_LWM THEN								-- NOTFALL?
+				DDR_SM = DS_T5F;									-- JA->
+			ELSE
+				DDR_SM = DS_T9F;
+			END IF;																	 
+			
+		WHEN DS_T9F =>
+			IF FIFO_REQ THEN
+				IF VIDEO_ADR_CNT[7..0]==H"FF" THEN					-- NEUE PAGE?
+					VA_S[10] = VCC;									-- ALLE BANKS SCHLIESEN 
+					DDR_SM = DS_CB6;								-- BANK SCHLIESSEN
+				ELSE
+ 					VA_P[9..0] = FIFO_COL_ADR[]+4;
+					VA_P[10] = GND;									-- NON AUTO PRECHARGE  
+					BA_P[] = FIFO_BA[];
+					DDR_SM = DS_T10F;
+ 				END IF;											 
+			ELSE
+				VA_S[10] = VCC;										-- ALLE BANKS SCHLIESEN 
+				DDR_SM = DS_CB6;									-- BANK SCHLIESSEN
+			END IF;
+
+		WHEN DS_T10F =>
+ 			IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN
+ 				VRAS = VCC;
+ 				VA[] = FB_AD[26..14];
+ 				BA[] = FB_AD[13..12]; 
+ 				CPU_AC = VCC;
+ 				BUS_CYC = VCC;										-- BUS CYCLUS LOSTRETEN
+ 				VA_S[10] = VCC;										-- AUTO PRECHARGE DA NICHT FIFO BANK
+ 				DDR_SM = DS_T3;
+ 			ELSE
+				VCAS = VCC;
+				VA[] = VA_P[];
+				BA[] = BA_P[];
+				SR_FIFO_WRE = VCC;									-- DATEN WRITE FIFO
+				DDR_SM = DS_T7F;
+			END IF;	
+
+-- CONFIG CYCLUS
+		WHEN DS_C2 =>
+			DDR_SM = DS_C3;
+		WHEN DS_C3 =>
+			BUS_CYC = CPU_REQ;
+			DDR_SM = DS_C4;
+		WHEN DS_C4 =>
+			IF CPU_REQ THEN
+				DDR_SM = DS_C5;
+			ELSE
+				DDR_SM = DS_T1;
+			END IF;	
+		WHEN DS_C5 =>
+			DDR_SM = DS_C6;
+		WHEN DS_C6 =>
+			VA_S[] = FB_AD[12..0];
+			BA_S[] = FB_AD[14..13];
+			DDR_SM = DS_C7;
+		WHEN DS_C7 =>
+			VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
+			VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
+			VWE	 = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1;		-- NUR BEI LONG WRITE
+			DDR_SM = DS_N8;
+-- CLOSE FIFO BANK
+		WHEN DS_CB6 =>
+			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
+			VRAS = VCC;									-- BÄNKE SCHLIESSEN
+			VWE = VCC;
+			DDR_SM = DS_N7;
+		WHEN DS_CB8 =>
+			FIFO_BANK_NOT_OK = VCC;						-- AUF NOT OK 
+			VRAS = VCC;									-- BÄNKE SCHLIESSEN
+			VWE = VCC;
+			DDR_SM = DS_T1;
+-- REFRESH 70NS = 10 ZYCLEN
+		WHEN DS_R2 =>
+			IF DDR_REFRESH_SIG[]==9 THEN				-- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
+				VRAS = VCC;								-- ALLE BANKS SCHLIESSEN
+				VWE = VCC;		
+				VA[10] = VCC;
+				FIFO_BANK_NOT_OK = VCC;
+				DDR_SM = DS_R4;
+			ELSE
+				VCAS = VCC;
+				VRAS = VCC;
+				DDR_SM = DS_R3;
+			END IF;
+		WHEN DS_R3 =>
+			DDR_SM = DS_R4;
+		WHEN DS_R4 =>
+			DDR_SM = DS_R5;
+		WHEN DS_R5 =>
+			DDR_SM = DS_R6;
+		WHEN DS_R6 =>
+			DDR_SM = DS_N5;
+-- LEERSCHLAUFE			
+		WHEN DS_N5 =>
+			DDR_SM = DS_N6;
+		WHEN DS_N6 =>
+			DDR_SM = DS_N7;
+		WHEN DS_N7 =>
+			DDR_SM = DS_N8;
+		WHEN DS_N8 =>
+			DDR_SM = DS_T1;
+	END CASE;
+
+---------------------------------------------------------------
+-- BLITTER ----------------------
+-----------------------------------------
+	BLITTER_REQ.CLK = DDRCLK0;
+	BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
+	BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
+	BLITTER_BA1 = BLITTER_ADR13;
+	BLITTER_BA0 = BLITTER_ADR12;
+	BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
+------------------------------------------------------------------------------	
+-- FIFO ---------------------------------
+--------------------------------------------------------
+	FIFO_REQ.CLK = DDRCLK0;
+	FIFO_REQ = (FIFO_MW[]<FIFO_MWM
+			  # FIFO_MW[]<FIFO_HWM & FIFO_REQ) & FIFO_ACTIVE & !CLEAR_FIFO_CNT & !STOP & !DDR_CONFIG & VCKE & !nVCS;
+	FIFO_ROW_ADR[] = VIDEO_ADR_CNT[22..10];
+	FIFO_BA1 	   = VIDEO_ADR_CNT9;
+	FIFO_BA0 	   = VIDEO_ADR_CNT8;
+	FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
+	FIFO_BANK_OK.CLK = DDRCLK0;
+	FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
+	-- ZÄHLER RÜCKSETZEN WENN CLR FIFO ----------------
+	CLR_FIFO_SYNC.CLK =DDRCLK0;
+	CLR_FIFO_SYNC = CLR_FIFO;				-- SYNCHRONISIEREN
+	CLEAR_FIFO_CNT.CLK  = DDRCLK0;
+	CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
+	STOP.CLK = DDRCLK0;
+	STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
+	-- ZÄHLEN -----------------------------------------------
+	VIDEO_ADR_CNT[].CLK = DDRCLK0;
+	VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
+	VIDEO_ADR_CNT[] =  CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
+					# !CLEAR_FIFO_CNT & VIDEO_ADR_CNT[]+1;	
+	VIDEO_BASE_ADR[22..20] = VIDEO_BASE_X_D[];
+	VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
+	VIDEO_BASE_ADR[11..4]  = VIDEO_BASE_M_D[];
+	VIDEO_BASE_ADR[3..0]   = VIDEO_BASE_L_D[7..4];
+	VDM_SEL[] = VIDEO_BASE_L_D[3..0];
+	-- AKTUELLE VIDEO ADRESSE
+	VIDEO_ACT_ADR[26..4] = VIDEO_ADR_CNT[] - (0,FIFO_MW[]);
+	VIDEO_ACT_ADR[3..0] = VDM_SEL[];
+-----------------------------------------------------------------------------------------
+-- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
+-----------------------------------------------------------------------------------------
+	DDR_REFRESH_CNT[].CLK = CLK33M;
+	DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1;													-- ZÄHLEN 0-2047 
+	REFRESH_TIME.CLK = DDRCLK0;
+	REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK;											-- SYNC
+	DDR_REFRESH_SIG[].CLK = DDRCLK0;												
+	DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;				
+	DDR_REFRESH_SIG[] =  REFRESH_TIME & 9                     & DDR_REFRESH_ON & !DDR_CONFIG	-- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF)
+					  # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; 	-- MINUS 1 WENN GEMACHT
+	DDR_REFRESH_REQ.CLK = DDRCLK0;
+	DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;
+-----------------------------------------------------------	
+-- VIDEO REGISTER -----------------------
+---------------------------------------------------------------------------------------------------------------------
+	VIDEO_BASE_L_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; 								-- 820D/2
+	VIDEO_BASE_L_D[] = FB_AD[23..16];												-- SORRY, NUR 16 BYT GRENZEN
+	VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;	
+
+	VIDEO_BASE_M_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; 								-- 8203/2
+	VIDEO_BASE_M_D[] = FB_AD[23..16];
+	VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;	
+
+	VIDEO_BASE_H_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100";			 					-- 8200-1/2
+	VIDEO_BASE_H_D[] = FB_AD[23..16];
+	VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;	
+	VIDEO_BASE_X_D[].CLK = MAIN_CLK;
+	VIDEO_BASE_X_D[] = FB_AD[26..24];
+	VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;	
+
+	VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; 								-- 8209/2
+	VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; 								-- 8207/2
+	VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; 								-- 8204,5/2
+	
+	VIDEO_BASE_X_D_FULL[] = (0,VIDEO_BASE_X_D[]); -- GE
+
+	FB_AD[31..24] = lpm_bustri_BYT(
+						VIDEO_BASE_H  & VIDEO_BASE_X_D_FULL[]
+					  # VIDEO_CNT_H	  & (0,VIDEO_ACT_ADR[26..24])
+					  ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
+
+	FB_AD[23..16] = lpm_bustri_BYT(
+						VIDEO_BASE_L  & VIDEO_BASE_L_D[]
+					  # VIDEO_BASE_M  & VIDEO_BASE_M_D[]
+					  # VIDEO_BASE_H  & VIDEO_BASE_H_D[]
+					  # VIDEO_CNT_L	  & VIDEO_ACT_ADR[7..0]
+					  # VIDEO_CNT_M	  & VIDEO_ACT_ADR[15..8]
+					  # VIDEO_CNT_H	  & VIDEO_ACT_ADR[23..16]
+					  ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
+END;
+
diff --git a/FPGA_quartus_GE/ahdl2v/DDR_CTR.v b/FPGA_quartus_GE/ahdl2v/DDR_CTR.v
new file mode 100644
index 0000000..238a56b
--- /dev/null
+++ b/FPGA_quartus_GE/ahdl2v/DDR_CTR.v
@@ -0,0 +1,1095 @@
+// Xilinx XPort Language Converter, Version 4.1 (110)
+// 
+// AHDL    Design Source: DDR_CTR.tdf
+// Verilog Design Output: DDR_CTR.v
+// Created 03-Mar-2014 09:18 PM
+//
+// Copyright (c) 2014, Xilinx, Inc.  All Rights Reserved.
+// Xilinx Inc makes no warranty, expressed or implied, with respect to
+// the operation and/or functionality of the converted output files.
+// 
+
+// DDR_CTR
+
+
+//  CREATED BY FREDI ASCHWANDEN
+//  FIFO WATER MARK
+//  {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+//  {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+module DDR_CTR(FB_ADR, nFB_CS1, nFB_CS2, nFB_CS3, nFB_OE, FB_SIZE0, FB_SIZE1,
+      nRSTO, MAIN_CLK, FB_ALE, nFB_WR, DDR_SYNC_66M, CLR_FIFO, VIDEO_RAM_CTR,
+      BLITTER_ADR, BLITTER_SIG, BLITTER_WR, DDRCLK0, CLK33M, FIFO_MW, VA, nVWE,
+      nVRAS, nVCS, VCKE, nVCAS, FB_LE, FB_VDOE, SR_FIFO_WRE, SR_DDR_FB,
+      SR_DDR_WR, SR_DDRWR_D_SEL, SR_VDMP, VIDEO_DDR_TA, SR_BLITTER_DACK, BA,
+      DDRWR_D_SEL1, VDM_SEL, FB_AD);
+
+//  {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+//  {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+   input [31:0] FB_ADR;
+   input nFB_CS1, nFB_CS2, nFB_CS3, nFB_OE, FB_SIZE0, FB_SIZE1, nRSTO,
+	 MAIN_CLK, FB_ALE, nFB_WR, DDR_SYNC_66M, CLR_FIFO;
+   input [15:0] VIDEO_RAM_CTR;
+   input [31:0] BLITTER_ADR;
+   input BLITTER_SIG, BLITTER_WR, DDRCLK0, CLK33M;
+   input [8:0] FIFO_MW;
+   output [12:0] VA;
+   output nVWE, nVRAS, nVCS, VCKE, nVCAS;
+   output [3:0] FB_LE;
+   output [3:0] FB_VDOE;
+   output SR_FIFO_WRE, SR_DDR_FB, SR_DDR_WR, SR_DDRWR_D_SEL;
+   output [7:0] SR_VDMP;
+   output VIDEO_DDR_TA, SR_BLITTER_DACK;
+   output [1:0] BA;
+   output DDRWR_D_SEL1;
+   output [3:0] VDM_SEL;
+   reg [3:0] FB_LE;
+   reg [3:0] FB_VDOE;
+   reg SR_DDR_FB, VIDEO_DDR_TA, SR_BLITTER_DACK;
+   inout [31:0] FB_AD;
+
+//  START (NORMAL 8 CYCLES TOTAL = 60ns)
+//  CONFIG
+//  READ CPU UND BLITTER,
+//  WRITE CPU UND BLITTER
+//  READ FIFO
+//  CLOSE FIFO BANK
+//  REFRESH 10X7.5NS=75NS
+   wire [2:0] FB_REGDDR_;
+   wire [5:0] DDR_SM_;
+   wire LINE;
+   wire [3:0] FB_B;
+   wire [12:0] VA_P;
+   wire [1:0] BA_P;
+   wire [12:0] VA_S;
+   wire [1:0] BA_S;
+   wire [1:0] MCS;
+   wire [1:0] MCS_d;
+   wire CPU_DDR_SYNC, CPU_DDR_SYNC_d, CPU_DDR_SYNC_clk, DDR_SEL, DDR_CS,
+	 DDR_CS_d, DDR_CS_clk, DDR_CS_ena, DDR_CONFIG, SR_DDR_WR_clk,
+	 SR_DDRWR_D_SEL_clk;
+   wire [12:0] CPU_ROW_ADR;
+   wire [1:0] CPU_BA;
+   wire [9:0] CPU_COL_ADR;
+   wire CPU_SIG, CPU_REQ, CPU_REQ_d, CPU_REQ_clk, CPU_AC, CPU_AC_clk, BUS_CYC,
+	 BUS_CYC_d, BUS_CYC_clk, BLITTER_REQ, BLITTER_REQ_d, BLITTER_REQ_clk,
+	 BLITTER_AC, BLITTER_AC_clk;
+   wire [12:0] BLITTER_ROW_ADR;
+   wire [1:0] BLITTER_BA;
+   wire [9:0] BLITTER_COL_ADR;
+   wire FIFO_REQ, FIFO_REQ_d, FIFO_REQ_clk, FIFO_AC, FIFO_AC_clk;
+   wire [12:0] FIFO_ROW_ADR;
+   wire [1:0] FIFO_BA;
+   wire [9:0] FIFO_COL_ADR;
+   wire FIFO_ACTIVE, CLR_FIFO_SYNC, CLR_FIFO_SYNC_d, CLR_FIFO_SYNC_clk,
+	 CLEAR_FIFO_CNT, CLEAR_FIFO_CNT_d, CLEAR_FIFO_CNT_clk, STOP, STOP_d,
+	 STOP_clk, SR_FIFO_WRE_clk, FIFO_BANK_OK, FIFO_BANK_OK_d,
+	 FIFO_BANK_OK_clk, DDR_REFRESH_ON;
+   wire [10:0] DDR_REFRESH_CNT;
+   wire [10:0] DDR_REFRESH_CNT_d;
+   wire DDR_REFRESH_REQ, DDR_REFRESH_REQ_d, DDR_REFRESH_REQ_clk;
+   wire [3:0] DDR_REFRESH_SIG;
+   wire [3:0] DDR_REFRESH_SIG_d;
+   wire REFRESH_TIME, REFRESH_TIME_d, REFRESH_TIME_clk;
+   wire [7:0] VIDEO_BASE_L_D;
+   wire [7:0] VIDEO_BASE_L_D_d;
+   wire VIDEO_BASE_L;
+   wire [7:0] VIDEO_BASE_M_D;
+   wire [7:0] VIDEO_BASE_M_D_d;
+   wire VIDEO_BASE_M;
+   wire [7:0] VIDEO_BASE_H_D;
+   wire [7:0] VIDEO_BASE_H_D_d;
+   wire VIDEO_BASE_H;
+   wire [2:0] VIDEO_BASE_X_D;
+   wire [2:0] VIDEO_BASE_X_D_d;
+   wire [7:0] VIDEO_BASE_X_D_FULL;
+   wire [22:0] VIDEO_ADR_CNT;
+   wire [22:0] VIDEO_ADR_CNT_d;
+   wire VIDEO_CNT_L, VIDEO_CNT_M, VIDEO_CNT_H;
+   wire [22:0] VIDEO_BASE_ADR;
+   wire [26:0] VIDEO_ACT_ADR;
+   wire vcc, gnd;
+   wire [7:0] u0_data;
+   wire u0_enabledt;
+   wire [7:0] u0_tridata;
+   wire [7:0] u1_data;
+   wire u1_enabledt;
+   wire [7:0] u1_tridata;
+   wire FIFO_BANK_OK_d_2, BUS_CYC_d_1, BA0_1, BA1_1, VA0_1, VA1_1, VA2_1,
+	 VA3_1, VA4_1, VA5_1, VA6_1, VA7_1, VA8_1, VA9_1, VA10_1, VA11_1,
+	 VA12_1, VIDEO_BASE_X_D0_ena_ctrl, VIDEO_BASE_X_D0_clk_ctrl,
+	 VIDEO_BASE_H_D0_ena_ctrl, VIDEO_BASE_H_D0_clk_ctrl,
+	 VIDEO_BASE_M_D0_ena_ctrl, VIDEO_BASE_M_D0_clk_ctrl,
+	 VIDEO_BASE_L_D0_ena_ctrl, VIDEO_BASE_L_D0_clk_ctrl,
+	 DDR_REFRESH_SIG0_ena_ctrl, DDR_REFRESH_SIG0_clk_ctrl,
+	 DDR_REFRESH_CNT0_clk_ctrl, VIDEO_ADR_CNT0_ena_ctrl,
+	 VIDEO_ADR_CNT0_clk_ctrl, DDR_SM_0_clk_ctrl, BA_P0_clk_ctrl,
+	 VA_P0_clk_ctrl, BA_S0_clk_ctrl, VA_S0_clk_ctrl, MCS0_clk_ctrl,
+	 SR_VDMP0_clk_ctrl, FB_REGDDR_0_clk_ctrl;
+   reg [2:0] FB_REGDDR__d;
+   reg [2:0] FB_REGDDR__q;
+   reg [5:0] DDR_SM__d;
+   reg [5:0] DDR_SM__q;
+   reg VCAS, VRAS, VWE;
+   reg [12:0] VA_P_d;
+   reg [12:0] VA_P_q;
+   reg [1:0] BA_P_d;
+   reg [1:0] BA_P_q;
+   reg [12:0] VA_S_d;
+   reg [12:0] VA_S_q;
+   reg [1:0] BA_S_d;
+   reg [1:0] BA_S_q;
+   reg [1:0] MCS_q;
+   reg CPU_DDR_SYNC_q, DDR_CS_q, SR_DDR_WR_d, SR_DDR_WR_q, SR_DDRWR_D_SEL_d,
+	 SR_DDRWR_D_SEL_q;
+   reg [7:0] SR_VDMP_d;
+   reg [7:0] SR_VDMP_q;
+   reg CPU_REQ_q, CPU_AC_d, CPU_AC_q, BUS_CYC_q, BUS_CYC_END, BLITTER_REQ_q,
+	 BLITTER_AC_d, BLITTER_AC_q, FIFO_REQ_q, FIFO_AC_d, FIFO_AC_q,
+	 CLR_FIFO_SYNC_q, CLEAR_FIFO_CNT_q, STOP_q, SR_FIFO_WRE_d,
+	 SR_FIFO_WRE_q, FIFO_BANK_OK_q, FIFO_BANK_NOT_OK;
+   reg [10:0] DDR_REFRESH_CNT_q;
+   reg DDR_REFRESH_REQ_q;
+   reg [3:0] DDR_REFRESH_SIG_q;
+   reg REFRESH_TIME_q;
+   reg [7:0] VIDEO_BASE_L_D_q;
+   reg [7:0] VIDEO_BASE_M_D_q;
+   reg [7:0] VIDEO_BASE_H_D_q;
+   reg [2:0] VIDEO_BASE_X_D_q;
+   reg [22:0] VIDEO_ADR_CNT_q;
+   reg FIFO_BANK_OK_d_1, BUS_CYC_d_2, BA0_2, BA1_2, VA0_2, VA1_2, VA2_2, VA3_2,
+	 VA4_2, VA5_2, VA6_2, VA7_2, VA8_2, VA9_2, VA10_2, VA11_2, VA12_2;
+
+
+// Sub Module Section
+   lpm_bustri_BYT  u0 (.data(u0_data), .enabledt(u0_enabledt),
+	 .tridata(u0_tridata));
+
+   lpm_bustri_BYT  u1 (.data(u1_data), .enabledt(u1_enabledt),
+	 .tridata(u1_tridata));
+
+
+   assign SR_FIFO_WRE = SR_FIFO_WRE_q;
+   always @(posedge SR_FIFO_WRE_clk)
+      SR_FIFO_WRE_q <= SR_FIFO_WRE_d;
+
+   assign SR_DDR_WR = SR_DDR_WR_q;
+   always @(posedge SR_DDR_WR_clk)
+      SR_DDR_WR_q <= SR_DDR_WR_d;
+
+   assign SR_DDRWR_D_SEL = SR_DDRWR_D_SEL_q;
+   always @(posedge SR_DDRWR_D_SEL_clk)
+      SR_DDRWR_D_SEL_q <= SR_DDRWR_D_SEL_d;
+
+   assign SR_VDMP = SR_VDMP_q;
+   always @(posedge SR_VDMP0_clk_ctrl)
+      SR_VDMP_q <= SR_VDMP_d;
+
+   always @(posedge FB_REGDDR_0_clk_ctrl)
+      FB_REGDDR__q <= FB_REGDDR__d;
+
+   always @(posedge DDR_SM_0_clk_ctrl)
+      DDR_SM__q <= DDR_SM__d;
+
+   always @(posedge VA_P0_clk_ctrl)
+      VA_P_q <= VA_P_d;
+
+   always @(posedge BA_P0_clk_ctrl)
+      BA_P_q <= BA_P_d;
+
+   always @(posedge VA_S0_clk_ctrl)
+      VA_S_q <= VA_S_d;
+
+   always @(posedge BA_S0_clk_ctrl)
+      BA_S_q <= BA_S_d;
+
+   always @(posedge MCS0_clk_ctrl)
+      MCS_q <= MCS_d;
+
+   always @(posedge CPU_DDR_SYNC_clk)
+      CPU_DDR_SYNC_q <= CPU_DDR_SYNC_d;
+
+   always @(posedge DDR_CS_clk)
+      if (DDR_CS_ena)
+	 DDR_CS_q <= DDR_CS_d;
+
+   always @(posedge CPU_REQ_clk)
+      CPU_REQ_q <= CPU_REQ_d;
+
+   always @(posedge CPU_AC_clk)
+      CPU_AC_q <= CPU_AC_d;
+
+   always @(posedge BUS_CYC_clk)
+      BUS_CYC_q <= BUS_CYC_d;
+
+   always @(posedge BLITTER_REQ_clk)
+      BLITTER_REQ_q <= BLITTER_REQ_d;
+
+   always @(posedge BLITTER_AC_clk)
+      BLITTER_AC_q <= BLITTER_AC_d;
+
+   always @(posedge FIFO_REQ_clk)
+      FIFO_REQ_q <= FIFO_REQ_d;
+
+   always @(posedge FIFO_AC_clk)
+      FIFO_AC_q <= FIFO_AC_d;
+
+   always @(posedge CLR_FIFO_SYNC_clk)
+      CLR_FIFO_SYNC_q <= CLR_FIFO_SYNC_d;
+
+   always @(posedge CLEAR_FIFO_CNT_clk)
+      CLEAR_FIFO_CNT_q <= CLEAR_FIFO_CNT_d;
+
+   always @(posedge STOP_clk)
+      STOP_q <= STOP_d;
+
+   always @(posedge FIFO_BANK_OK_clk)
+      FIFO_BANK_OK_q <= FIFO_BANK_OK_d;
+
+   always @(posedge DDR_REFRESH_CNT0_clk_ctrl)
+      DDR_REFRESH_CNT_q <= DDR_REFRESH_CNT_d;
+
+   always @(posedge DDR_REFRESH_REQ_clk)
+      DDR_REFRESH_REQ_q <= DDR_REFRESH_REQ_d;
+
+   always @(posedge DDR_REFRESH_SIG0_clk_ctrl)
+      if (DDR_REFRESH_SIG0_ena_ctrl)
+	 DDR_REFRESH_SIG_q <= DDR_REFRESH_SIG_d;
+
+   always @(posedge REFRESH_TIME_clk)
+      REFRESH_TIME_q <= REFRESH_TIME_d;
+
+   always @(posedge VIDEO_BASE_L_D0_clk_ctrl)
+      if (VIDEO_BASE_L_D0_ena_ctrl)
+	 VIDEO_BASE_L_D_q <= VIDEO_BASE_L_D_d;
+
+   always @(posedge VIDEO_BASE_M_D0_clk_ctrl)
+      if (VIDEO_BASE_M_D0_ena_ctrl)
+	 VIDEO_BASE_M_D_q <= VIDEO_BASE_M_D_d;
+
+   always @(posedge VIDEO_BASE_H_D0_clk_ctrl)
+      if (VIDEO_BASE_H_D0_ena_ctrl)
+	 VIDEO_BASE_H_D_q <= VIDEO_BASE_H_D_d;
+
+   always @(posedge VIDEO_BASE_X_D0_clk_ctrl)
+      if (VIDEO_BASE_X_D0_ena_ctrl)
+	 VIDEO_BASE_X_D_q <= VIDEO_BASE_X_D_d;
+
+   always @(posedge VIDEO_ADR_CNT0_clk_ctrl)
+      if (VIDEO_ADR_CNT0_ena_ctrl)
+	 VIDEO_ADR_CNT_q <= VIDEO_ADR_CNT_d;
+
+// Start of original equations
+   assign LINE = FB_SIZE0 & FB_SIZE1;
+
+//  BYT SELECT
+//  ADR==0
+//  LONG UND LINE
+   assign FB_B[0] = FB_ADR[1:0] == 2'b00 | (FB_SIZE1 & FB_SIZE0) | ((!FB_SIZE1)
+	 & (!FB_SIZE0));
+
+//  ADR==1
+//  HIGH WORD
+//  LONG UND LINE
+   assign FB_B[1] = FB_ADR[1:0] == 2'b01 | (FB_SIZE1 & (!FB_SIZE0) &
+	 (!FB_ADR[1])) | (FB_SIZE1 & FB_SIZE0) | ((!FB_SIZE1) & (!FB_SIZE0));
+
+//  ADR==2
+//  LONG UND LINE
+   assign FB_B[2] = FB_ADR[1:0] == 2'b10 | (FB_SIZE1 & FB_SIZE0) | ((!FB_SIZE1)
+	 & (!FB_SIZE0));
+
+//  ADR==3
+//  LOW WORD
+//  LONG UND LINE
+   assign FB_B[3] = FB_ADR[1:0] == 2'b11 | (FB_SIZE1 & (!FB_SIZE0) & FB_ADR[1])
+	 | (FB_SIZE1 & FB_SIZE0) | ((!FB_SIZE1) & (!FB_SIZE0));
+
+//  CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR)  --------------------------------------------------
+   assign FB_REGDDR_0_clk_ctrl = MAIN_CLK;
+
+
+   always @(FB_REGDDR__q or DDR_SEL or BUS_CYC_q or LINE or DDR_CS_q or nFB_OE
+	 or MAIN_CLK or DDR_CONFIG or nFB_WR or vcc) begin
+      FB_REGDDR__d = FB_REGDDR__q;
+      {FB_VDOE[0], FB_VDOE[1]} = 2'b00;
+      {FB_LE[0], FB_LE[1], FB_VDOE[2], FB_LE[2], FB_VDOE[3], FB_LE[3],
+	    VIDEO_DDR_TA, BUS_CYC_END} = 8'b0000_0000;
+      casex (FB_REGDDR__q)
+      3'b000: begin
+	    FB_LE[0] = !nFB_WR;
+
+//  LOS WENN BEREIT ODER IMMER BEI LINE WRITE
+	    if (BUS_CYC_q | (DDR_SEL & LINE & (!nFB_WR))) begin
+	       FB_REGDDR__d = 3'b001;
+	    end else begin
+	       FB_REGDDR__d = 3'b000;
+	    end
+	 end
+      3'b001: begin
+	    if (DDR_CS_q) begin
+	       FB_LE[0] = !nFB_WR;
+	       VIDEO_DDR_TA = vcc;
+	       if (LINE) begin
+		  FB_VDOE[0] = (!nFB_OE) & (!DDR_CONFIG);
+		  FB_REGDDR__d = 3'b010;
+	       end else begin
+		  BUS_CYC_END = vcc;
+		  FB_VDOE[0] = (!nFB_OE) & (!MAIN_CLK) & (!DDR_CONFIG);
+		  FB_REGDDR__d = 3'b000;
+	       end
+	    end else begin
+	       FB_REGDDR__d = 3'b000;
+	    end
+	 end
+      3'b010: begin
+	    if (DDR_CS_q) begin
+	       FB_VDOE[1] = (!nFB_OE) & (!DDR_CONFIG);
+	       FB_LE[1] = !nFB_WR;
+	       VIDEO_DDR_TA = vcc;
+	       FB_REGDDR__d = 3'b011;
+	    end else begin
+	       FB_REGDDR__d = 3'b000;
+	    end
+	 end
+      3'b011: begin
+	    if (DDR_CS_q) begin
+	       FB_VDOE[2] = (!nFB_OE) & (!DDR_CONFIG);
+	       FB_LE[2] = !nFB_WR;
+
+//  BEI LINE WRITE EVT. WARTEN
+	       if ((!BUS_CYC_q) & LINE & (!nFB_WR)) begin
+		  FB_REGDDR__d = 3'b011;
+	       end else begin
+		  VIDEO_DDR_TA = vcc;
+		  FB_REGDDR__d = 3'b100;
+	       end
+	    end else begin
+	       FB_REGDDR__d = 3'b000;
+	    end
+	 end
+      3'b100: begin
+	    if (DDR_CS_q) begin
+	       FB_VDOE[3] = (!nFB_OE) & (!MAIN_CLK) & (!DDR_CONFIG);
+	       FB_LE[3] = !nFB_WR;
+	       VIDEO_DDR_TA = vcc;
+	       BUS_CYC_END = vcc;
+	       FB_REGDDR__d = 3'b000;
+	    end else begin
+	       FB_REGDDR__d = 3'b000;
+	    end
+	 end
+      endcase
+   end
+
+//  DDR STEUERUNG -----------------------------------------------------
+//  VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE;
+   assign VCKE = VIDEO_RAM_CTR[0];
+   assign nVCS = !VIDEO_RAM_CTR[1];
+   assign DDR_REFRESH_ON = VIDEO_RAM_CTR[2];
+   assign DDR_CONFIG = VIDEO_RAM_CTR[3];
+   assign FIFO_ACTIVE = VIDEO_RAM_CTR[8];
+
+// ------------------------------
+   assign CPU_ROW_ADR = FB_ADR[26:14];
+   assign CPU_BA = FB_ADR[13:12];
+   assign CPU_COL_ADR = FB_ADR[11:2];
+   assign nVRAS = !VRAS;
+   assign nVCAS = !VCAS;
+   assign nVWE = !VWE;
+   assign SR_DDR_WR_clk = DDRCLK0;
+   assign SR_DDRWR_D_SEL_clk = DDRCLK0;
+   assign SR_VDMP0_clk_ctrl = DDRCLK0;
+   assign SR_FIFO_WRE_clk = DDRCLK0;
+   assign CPU_AC_clk = DDRCLK0;
+   assign FIFO_AC_clk = DDRCLK0;
+   assign BLITTER_AC_clk = DDRCLK0;
+   assign DDRWR_D_SEL1 = BLITTER_AC_q;
+
+//  SELECT LOGIC
+   assign DDR_SEL = FB_ALE & FB_AD[31:30] == 2'b01;
+   assign DDR_CS_clk = MAIN_CLK;
+   assign DDR_CS_ena = FB_ALE;
+   assign DDR_CS_d = DDR_SEL;
+
+//  WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER
+//  NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
+//  CONFIG SOFORT LOS
+//  LINE WRITE SPÄTER
+   assign CPU_SIG = (DDR_SEL & (nFB_WR | (!LINE)) & (!DDR_CONFIG)) | (DDR_SEL &
+	 DDR_CONFIG) | (FB_REGDDR__q == 3'b010 & (!nFB_WR));
+   assign CPU_REQ_clk = DDR_SYNC_66M;
+
+//  HALTEN BUS CYC BEGONNEN ODER FERTIG
+   assign CPU_REQ_d = CPU_SIG | (CPU_REQ_q & FB_REGDDR__q != 3'b010 &
+	 FB_REGDDR__q != 3'b100 & (!BUS_CYC_END) & (!BUS_CYC_q));
+   assign BUS_CYC_clk = DDRCLK0;
+   assign BUS_CYC_d_1 = BUS_CYC_q & (!BUS_CYC_END);
+
+//  STATE MACHINE SYNCHRONISIEREN -----------------
+   assign MCS0_clk_ctrl = DDRCLK0;
+   assign MCS_d[0] = MAIN_CLK;
+   assign MCS_d[1] = MCS_q[0];
+   assign CPU_DDR_SYNC_clk = DDRCLK0;
+
+//  NUR 1 WENN EIN
+   assign CPU_DDR_SYNC_d = MCS_q == 2'b10 & VCKE & (!nVCS);
+
+// -------------------------------------------------
+   assign VA_S0_clk_ctrl = DDRCLK0;
+   assign BA_S0_clk_ctrl = DDRCLK0;
+   assign {VA12_1, VA11_1, VA10_1, VA9_1, VA8_1, VA7_1, VA6_1, VA5_1, VA4_1,
+	 VA3_1, VA2_1, VA1_1, VA0_1} = VA_S_q;
+   assign {BA1_1, BA0_1} = BA_S_q;
+   assign VA_P0_clk_ctrl = DDRCLK0;
+   assign BA_P0_clk_ctrl = DDRCLK0;
+
+//  DDR STATE MACHINE  -----------------------------------------------
+   assign DDR_SM_0_clk_ctrl = DDRCLK0;
+
+
+   always @(DDR_SM__q or DDR_REFRESH_REQ_q or CPU_DDR_SYNC_q or DDR_CONFIG or
+	 CPU_ROW_ADR or FIFO_ROW_ADR or BLITTER_ROW_ADR or BLITTER_REQ_q or
+	 BLITTER_WR or FIFO_AC_q or CPU_COL_ADR or BLITTER_COL_ADR or VA_S_q or
+	 CPU_BA or BLITTER_BA or FB_B or CPU_AC_q or BLITTER_AC_q or
+	 FIFO_BANK_OK_q or FIFO_MW or FIFO_REQ_q or VIDEO_ADR_CNT_q or
+	 FIFO_COL_ADR or gnd or DDR_SEL or LINE or FIFO_BA or FB_AD or VA_P_q
+	 or BA_P_q or CPU_REQ_q or nFB_WR or FB_SIZE0 or FB_SIZE1 or
+	 DDR_REFRESH_SIG_q or vcc) begin
+      DDR_SM__d = DDR_SM__q;
+      BA_S_d = 2'b00;
+      VA_S_d = 13'b0_0000_0000_0000;
+      BA_P_d = 2'b00;
+      {VA_P_d[9], VA_P_d[8], VA_P_d[7], VA_P_d[6], VA_P_d[5], VA_P_d[4],
+	    VA_P_d[3], VA_P_d[2], VA_P_d[1], VA_P_d[0], VA_P_d[10]} =
+	    11'b000_0000_0000;
+      SR_VDMP_d = 8'b0000_0000;
+      VA_P_d[12:11] = 2'b00;
+      {FIFO_BANK_OK_d_1, FIFO_AC_d, SR_DDR_FB, SR_BLITTER_DACK, BLITTER_AC_d,
+	    SR_DDR_WR_d, SR_DDRWR_D_SEL_d, CPU_AC_d, VA12_2, VA11_2, VA9_2,
+	    VA8_2, VA7_2, VA6_2, VA5_2, VA4_2, VA3_2, VA2_2, VA1_2, VA0_2,
+	    BA1_2, BA0_2, SR_FIFO_WRE_d, BUS_CYC_d_2, VWE, VA10_2,
+	    FIFO_BANK_NOT_OK, VCAS, VRAS} =
+	    29'b0_0000_0000_0000_0000_0000_0000_0000;
+      casex (DDR_SM__q)
+      6'b00_0000: begin
+	    if (DDR_REFRESH_REQ_q) begin
+	       DDR_SM__d = 6'b01_1111;
+
+//  SYNCHRON UND EIN?
+	    end else if (CPU_DDR_SYNC_q) begin
+
+//  JA
+	       if (DDR_CONFIG) begin
+		  DDR_SM__d = 6'b00_1000;
+
+//  BEI WAIT UND LINE WRITE
+	       end else if (CPU_REQ_q) begin
+		  VA_S_d = CPU_ROW_ADR;
+		  BA_S_d = CPU_BA;
+		  CPU_AC_d = vcc;
+		  BUS_CYC_d_2 = vcc;
+		  DDR_SM__d = 6'b00_0010;
+	       end else begin
+
+//  FIFO IST DEFAULT
+		  if (FIFO_REQ_q | (!BLITTER_REQ_q)) begin
+		     VA_P_d = FIFO_ROW_ADR;
+		     BA_P_d = FIFO_BA;
+
+//  VORBESETZEN
+		     FIFO_AC_d = vcc;
+		  end else begin
+		     VA_P_d = BLITTER_ROW_ADR;
+		     BA_P_d = BLITTER_BA;
+
+//  VORBESETZEN
+		     BLITTER_AC_d = vcc;
+		  end
+		  DDR_SM__d = 6'b00_0001;
+	       end
+	    end else begin
+
+//  NEIN ->SYNCHRONISIEREN
+	       DDR_SM__d = 6'b00_0000;
+	    end
+	 end
+      6'b00_0001: begin
+
+//  SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK ***
+	    if (DDR_SEL & (nFB_WR | (!LINE))) begin
+	       VRAS = vcc;
+	       {VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2,
+		     VA4_2, VA3_2, VA2_2, VA1_2, VA0_2} = FB_AD[26:14];
+	       {BA1_2, BA0_2} = FB_AD[13:12];
+
+//  AUTO PRECHARGE DA NICHT FIFO PAGE
+	       VA_S_d[10] = vcc;
+	       CPU_AC_d = vcc;
+
+//  BUS CYCLUS LOSTRETEN
+	       BUS_CYC_d_2 = vcc;
+	    end else begin
+	       VRAS = (FIFO_AC_q & FIFO_REQ_q) | (BLITTER_AC_q &
+		     BLITTER_REQ_q);
+	       {VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2,
+		     VA4_2, VA3_2, VA2_2, VA1_2, VA0_2} = VA_P_q;
+	       {BA1_2, BA0_2} = BA_P_q;
+	       VA_S_d[10] = !(FIFO_AC_q & FIFO_REQ_q);
+	       FIFO_BANK_OK_d_1 = FIFO_AC_q & FIFO_REQ_q;
+	       FIFO_AC_d = FIFO_AC_q & FIFO_REQ_q;
+	       BLITTER_AC_d = BLITTER_AC_q & BLITTER_REQ_q;
+	    end
+	    DDR_SM__d = 6'b00_0011;
+	 end
+      6'b00_0010: begin
+	    VRAS = vcc;
+	    FIFO_BANK_NOT_OK = vcc;
+	    CPU_AC_d = vcc;
+
+//  BUS CYCLUS LOSTRETEN
+	    BUS_CYC_d_2 = vcc;
+	    DDR_SM__d = 6'b00_0011;
+	 end
+      6'b00_0011: begin
+	    CPU_AC_d = CPU_AC_q;
+	    FIFO_AC_d = FIFO_AC_q;
+	    BLITTER_AC_d = BLITTER_AC_q;
+
+//  AUTO PRECHARGE WENN NICHT FIFO PAGE
+	    VA_S_d[10] = VA_S_q[10];
+	    if (((!nFB_WR) & CPU_AC_q) | (BLITTER_WR & BLITTER_AC_q)) begin
+	       DDR_SM__d = 6'b01_0000;
+
+//  CPU?
+	    end else if (CPU_AC_q) begin
+	       VA_S_d[9:0] = CPU_COL_ADR;
+	       BA_S_d = CPU_BA;
+	       DDR_SM__d = 6'b00_1110;
+
+//  FIFO?
+	    end else if (FIFO_AC_q) begin
+	       VA_S_d[9:0] = FIFO_COL_ADR;
+	       BA_S_d = FIFO_BA;
+	       DDR_SM__d = 6'b01_0110;
+	    end else if (BLITTER_AC_q) begin
+	       VA_S_d[9:0] = BLITTER_COL_ADR;
+	       BA_S_d = BLITTER_BA;
+	       DDR_SM__d = 6'b00_1110;
+	    end else begin
+
+//  READ
+	       DDR_SM__d = 6'b00_0111;
+	    end
+	 end
+      6'b00_1110: begin
+	    CPU_AC_d = CPU_AC_q;
+	    BLITTER_AC_d = BLITTER_AC_q;
+	    VCAS = vcc;
+
+//  READ DATEN FÜR CPU
+	    SR_DDR_FB = CPU_AC_q;
+
+//  BLITTER DACK AND BLITTER LATCH DATEN
+	    SR_BLITTER_DACK = BLITTER_AC_q;
+	    DDR_SM__d = 6'b00_1111;
+	 end
+      6'b00_1111: begin
+	    CPU_AC_d = CPU_AC_q;
+	    BLITTER_AC_d = BLITTER_AC_q;
+
+//  FIFO READ EINSCHIEBEN WENN BANK OK
+	    if (FIFO_REQ_q & FIFO_BANK_OK_q) begin
+	       VA_S_d[9:0] = FIFO_COL_ADR;
+
+//  MANUEL PRECHARGE
+	       VA_S_d[10] = gnd;
+	       BA_S_d = FIFO_BA;
+	       DDR_SM__d = 6'b01_1000;
+	    end else begin
+
+//  ALLE PAGES SCHLIESSEN
+	       VA_S_d[10] = vcc;
+
+//  WRITE
+	       DDR_SM__d = 6'b01_1101;
+	    end
+	 end
+      6'b01_0000: begin
+	    CPU_AC_d = CPU_AC_q;
+	    BLITTER_AC_d = BLITTER_AC_q;
+
+//  BLITTER ACK AND BLITTER LATCH DATEN
+	    SR_BLITTER_DACK = BLITTER_AC_q;
+
+//  AUTO PRECHARGE WENN NICHT FIFO PAGE
+	    VA_S_d[10] = VA_S_q[10];
+	    DDR_SM__d = 6'b01_0001;
+	 end
+      6'b01_0001: begin
+	    CPU_AC_d = CPU_AC_q;
+	    BLITTER_AC_d = BLITTER_AC_q;
+	    VA_S_d[9:0] = ({10{CPU_AC_q}} & CPU_COL_ADR) | ({10{BLITTER_AC_q}}
+		  & BLITTER_COL_ADR);
+
+//  AUTO PRECHARGE WENN NICHT FIFO PAGE
+	    VA_S_d[10] = VA_S_q[10];
+	    BA_S_d = ({2{CPU_AC_q}} & CPU_BA) | ({2{BLITTER_AC_q}} &
+		  BLITTER_BA);
+
+//  BYTE ENABLE WRITE
+	    SR_VDMP_d[7:4] = FB_B;
+
+//  LINE ENABLE WRITE
+	    SR_VDMP_d[3:0] = {4{LINE}} & 4'b1111;
+	    DDR_SM__d = 6'b01_0010;
+	 end
+      6'b01_0010: begin
+	    CPU_AC_d = CPU_AC_q;
+	    BLITTER_AC_d = BLITTER_AC_q;
+	    VCAS = vcc;
+	    VWE = vcc;
+
+//  WRITE COMMAND CPU UND BLITTER IF WRITER
+	    SR_DDR_WR_d = vcc;
+
+//  2. HÄLFTE WRITE DATEN SELEKTIEREN
+	    SR_DDRWR_D_SEL_d = vcc;
+
+//  WENN LINE DANN ACTIV
+	    SR_VDMP_d = {8{LINE}} & 8'b1111_1111;
+	    DDR_SM__d = 6'b01_0011;
+	 end
+      6'b01_0011: begin
+	    CPU_AC_d = CPU_AC_q;
+	    BLITTER_AC_d = BLITTER_AC_q;
+
+//  WRITE COMMAND CPU UND BLITTER IF WRITE
+	    SR_DDR_WR_d = vcc;
+
+//  2. HÄLFTE WRITE DATEN SELEKTIEREN
+	    SR_DDRWR_D_SEL_d = vcc;
+	    DDR_SM__d = 6'b01_0100;
+	 end
+      6'b01_0100: begin
+	    DDR_SM__d = 6'b01_0101;
+	 end
+      6'b01_0101: begin
+	    if (FIFO_REQ_q & FIFO_BANK_OK_q) begin
+	       VA_S_d[9:0] = FIFO_COL_ADR;
+
+//  NON AUTO PRECHARGE
+	       VA_S_d[10] = gnd;
+	       BA_S_d = FIFO_BA;
+	       DDR_SM__d = 6'b01_1000;
+	    end else begin
+
+//  ALLE PAGES SCHLIESSEN
+	       VA_S_d[10] = vcc;
+
+//  FIFO READ
+	       DDR_SM__d = 6'b01_1101;
+	    end
+	 end
+      6'b01_0110: begin
+	    VCAS = vcc;
+
+//  DATEN WRITE FIFO
+	    SR_FIFO_WRE_d = vcc;
+	    DDR_SM__d = 6'b01_0111;
+	 end
+      6'b01_0111: begin
+	    if (FIFO_REQ_q) begin
+
+//  NEUE PAGE?
+	       if (VIDEO_ADR_CNT_q[7:0] == 8'b1111_1111) begin
+
+//  ALLE PAGES SCHLIESSEN
+		  VA_S_d[10] = vcc;
+
+//  BANK SCHLIESSEN
+		  DDR_SM__d = 6'b01_1101;
+	       end else begin
+		  VA_S_d[9:0] = FIFO_COL_ADR + 10'b00_0000_0100;
+
+//  NON AUTO PRECHARGE
+		  VA_S_d[10] = gnd;
+		  BA_S_d = FIFO_BA;
+		  DDR_SM__d = 6'b01_1000;
+	       end
+	    end else begin
+
+//  ALLE PAGES SCHLIESSEN
+	       VA_S_d[10] = vcc;
+
+//  NOCH OFFEN LASSEN
+	       DDR_SM__d = 6'b01_1101;
+	    end
+	 end
+      6'b01_1000: begin
+	    VCAS = vcc;
+
+//  DATEN WRITE FIFO
+	    SR_FIFO_WRE_d = vcc;
+	    DDR_SM__d = 6'b01_1001;
+	 end
+      6'b01_1001: begin
+	    if (CPU_REQ_q & FIFO_MW > 9'b0_0000_0000) begin
+
+//  ALLE PAGES SCHLIESEN
+	       VA_S_d[10] = vcc;
+
+//  BANK SCHLIESSEN
+	       DDR_SM__d = 6'b01_1110;
+	    end else if (FIFO_REQ_q) begin
+
+//  NEUE PAGE?
+	       if (VIDEO_ADR_CNT_q[7:0] == 8'b1111_1111) begin
+
+//  ALLE PAGES SCHLIESSEN
+		  VA_S_d[10] = vcc;
+
+//  BANK SCHLIESSEN
+		  DDR_SM__d = 6'b01_1110;
+	       end else begin
+		  VA_S_d[9:0] = FIFO_COL_ADR + 10'b00_0000_0100;
+
+//  NON AUTO PRECHARGE
+		  VA_S_d[10] = gnd;
+		  BA_S_d = FIFO_BA;
+		  DDR_SM__d = 6'b01_1010;
+	       end
+	    end else begin
+
+//  ALLE PAGES SCHLIESEN
+	       VA_S_d[10] = vcc;
+
+//  BANK SCHLIESSEN
+	       DDR_SM__d = 6'b01_1110;
+	    end
+	 end
+      6'b01_1010: begin
+	    VCAS = vcc;
+
+//  DATEN WRITE FIFO
+	    SR_FIFO_WRE_d = vcc;
+
+//  NOTFALL?
+	    if (FIFO_MW < 9'b0_0000_0000) begin
+
+//  JA->
+	       DDR_SM__d = 6'b01_0111;
+	    end else begin
+	       DDR_SM__d = 6'b01_1011;
+	    end
+	 end
+      6'b01_1011: begin
+	    if (FIFO_REQ_q) begin
+
+//  NEUE PAGE?
+	       if (VIDEO_ADR_CNT_q[7:0] == 8'b1111_1111) begin
+
+//  ALLE BANKS SCHLIESEN
+		  VA_S_d[10] = vcc;
+
+//  BANK SCHLIESSEN
+		  DDR_SM__d = 6'b01_1101;
+	       end else begin
+		  VA_P_d[9:0] = FIFO_COL_ADR + 10'b00_0000_0100;
+
+//  NON AUTO PRECHARGE
+		  VA_P_d[10] = gnd;
+		  BA_P_d = FIFO_BA;
+		  DDR_SM__d = 6'b01_1100;
+	       end
+	    end else begin
+
+//  ALLE BANKS SCHLIESEN
+	       VA_S_d[10] = vcc;
+
+//  BANK SCHLIESSEN
+	       DDR_SM__d = 6'b01_1101;
+	    end
+	 end
+      6'b01_1100: begin
+	    if (DDR_SEL & (nFB_WR | (!LINE)) & FB_AD[13:12] != FIFO_BA) begin
+	       VRAS = vcc;
+	       {VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2,
+		     VA4_2, VA3_2, VA2_2, VA1_2, VA0_2} = FB_AD[26:14];
+	       {BA1_2, BA0_2} = FB_AD[13:12];
+	       CPU_AC_d = vcc;
+
+//  BUS CYCLUS LOSTRETEN
+	       BUS_CYC_d_2 = vcc;
+
+//  AUTO PRECHARGE DA NICHT FIFO BANK
+	       VA_S_d[10] = vcc;
+	       DDR_SM__d = 6'b00_0011;
+	    end else begin
+	       VCAS = vcc;
+	       {VA12_2, VA11_2, VA10_2, VA9_2, VA8_2, VA7_2, VA6_2, VA5_2,
+		     VA4_2, VA3_2, VA2_2, VA1_2, VA0_2} = VA_P_q;
+	       {BA1_2, BA0_2} = BA_P_q;
+
+//  DATEN WRITE FIFO
+	       SR_FIFO_WRE_d = vcc;
+
+//  CONFIG CYCLUS
+	       DDR_SM__d = 6'b01_1001;
+	    end
+	 end
+      6'b00_1000: begin
+	    DDR_SM__d = 6'b00_1001;
+	 end
+      6'b00_1001: begin
+	    BUS_CYC_d_2 = CPU_REQ_q;
+	    DDR_SM__d = 6'b00_1010;
+	 end
+      6'b00_1010: begin
+	    if (CPU_REQ_q) begin
+	       DDR_SM__d = 6'b00_1011;
+	    end else begin
+	       DDR_SM__d = 6'b00_0000;
+	    end
+	 end
+      6'b00_1011: begin
+	    DDR_SM__d = 6'b00_1100;
+	 end
+      6'b00_1100: begin
+	    VA_S_d = FB_AD[12:0];
+	    BA_S_d = FB_AD[14:13];
+	    DDR_SM__d = 6'b00_1101;
+	 end
+      6'b00_1101: begin
+
+//  NUR BEI LONG WRITE
+	    VRAS = FB_AD[18] & (!nFB_WR) & (!FB_SIZE0) & (!FB_SIZE1);
+
+//  NUR BEI LONG WRITE
+	    VCAS = FB_AD[17] & (!nFB_WR) & (!FB_SIZE0) & (!FB_SIZE1);
+
+//  NUR BEI LONG WRITE
+	    VWE = FB_AD[16] & (!nFB_WR) & (!FB_SIZE0) & (!FB_SIZE1);
+
+//  CLOSE FIFO BANK
+	    DDR_SM__d = 6'b00_0111;
+	 end
+      6'b01_1101: begin
+
+//  AUF NOT OK
+	    FIFO_BANK_NOT_OK = vcc;
+
+//  BÄNKE SCHLIESSEN
+	    VRAS = vcc;
+	    VWE = vcc;
+	    DDR_SM__d = 6'b00_0110;
+	 end
+      6'b01_1110: begin
+
+//  AUF NOT OK
+	    FIFO_BANK_NOT_OK = vcc;
+
+//  BÄNKE SCHLIESSEN
+	    VRAS = vcc;
+	    VWE = vcc;
+
+//  REFRESH 70NS = 10 ZYCLEN
+	    DDR_SM__d = 6'b00_0000;
+	 end
+      6'b01_1111: begin
+
+//  EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
+	    if (DDR_REFRESH_SIG_q == 4'b1001) begin
+
+//  ALLE BANKS SCHLIESSEN
+	       VRAS = vcc;
+	       VWE = vcc;
+	       VA10_2 = vcc;
+	       FIFO_BANK_NOT_OK = vcc;
+	       DDR_SM__d = 6'b10_0001;
+	    end else begin
+	       VCAS = vcc;
+	       VRAS = vcc;
+	       DDR_SM__d = 6'b10_0000;
+	    end
+	 end
+      6'b10_0000: begin
+	    DDR_SM__d = 6'b10_0001;
+	 end
+      6'b10_0001: begin
+	    DDR_SM__d = 6'b10_0010;
+	 end
+      6'b10_0010: begin
+	    DDR_SM__d = 6'b10_0011;
+	 end
+      6'b10_0011: begin
+
+//  LEERSCHLAUFE
+	    DDR_SM__d = 6'b00_0100;
+	 end
+      6'b00_0100: begin
+	    DDR_SM__d = 6'b00_0101;
+	 end
+      6'b00_0101: begin
+	    DDR_SM__d = 6'b00_0110;
+	 end
+      6'b00_0110: begin
+	    DDR_SM__d = 6'b00_0111;
+	 end
+      6'b00_0111: begin
+	    DDR_SM__d = 6'b00_0000;
+	 end
+      endcase
+   end
+
+// -------------------------------------------------------------
+//  BLITTER ----------------------
+// ---------------------------------------
+   assign BLITTER_REQ_clk = DDRCLK0;
+   assign BLITTER_REQ_d = BLITTER_SIG & (!DDR_CONFIG) & VCKE & (!nVCS);
+   assign BLITTER_ROW_ADR = BLITTER_ADR[26:14];
+   assign BLITTER_BA[1] = BLITTER_ADR[13];
+   assign BLITTER_BA[0] = BLITTER_ADR[12];
+   assign BLITTER_COL_ADR = BLITTER_ADR[11:2];
+
+// ----------------------------------------------------------------------------
+//  FIFO ---------------------------------
+// ------------------------------------------------------
+   assign FIFO_REQ_clk = DDRCLK0;
+   assign FIFO_REQ_d = (FIFO_MW < 9'b0_1100_1000 | (FIFO_MW < 9'b1_1111_0100 &
+	 FIFO_REQ_q)) & FIFO_ACTIVE & (!CLEAR_FIFO_CNT_q) & (!STOP_q) &
+	 (!DDR_CONFIG) & VCKE & (!nVCS);
+   assign FIFO_ROW_ADR = VIDEO_ADR_CNT_q[22:10];
+   assign FIFO_BA[1] = VIDEO_ADR_CNT_q[9];
+   assign FIFO_BA[0] = VIDEO_ADR_CNT_q[8];
+   assign FIFO_COL_ADR = {VIDEO_ADR_CNT_q[7], VIDEO_ADR_CNT_q[6],
+	 VIDEO_ADR_CNT_q[5], VIDEO_ADR_CNT_q[4], VIDEO_ADR_CNT_q[3],
+	 VIDEO_ADR_CNT_q[2], VIDEO_ADR_CNT_q[1], VIDEO_ADR_CNT_q[0], 2'b00};
+   assign FIFO_BANK_OK_clk = DDRCLK0;
+   assign FIFO_BANK_OK_d_2 = FIFO_BANK_OK_q & (!FIFO_BANK_NOT_OK);
+
+//  ZÄHLER RÜCKSETZEN WENN CLR FIFO ----------------
+   assign CLR_FIFO_SYNC_clk = DDRCLK0;
+
+//  SYNCHRONISIEREN
+   assign CLR_FIFO_SYNC_d = CLR_FIFO;
+   assign CLEAR_FIFO_CNT_clk = DDRCLK0;
+   assign CLEAR_FIFO_CNT_d = CLR_FIFO_SYNC_q | (!FIFO_ACTIVE);
+   assign STOP_clk = DDRCLK0;
+   assign STOP_d = CLR_FIFO_SYNC_q | CLEAR_FIFO_CNT_q;
+
+//  ZÄHLEN -----------------------------------------------
+   assign VIDEO_ADR_CNT0_clk_ctrl = DDRCLK0;
+   assign VIDEO_ADR_CNT0_ena_ctrl = SR_FIFO_WRE_q | CLEAR_FIFO_CNT_q;
+   assign VIDEO_ADR_CNT_d = ({23{CLEAR_FIFO_CNT_q}} & VIDEO_BASE_ADR) |
+	 ({23{!CLEAR_FIFO_CNT_q}} & (VIDEO_ADR_CNT_q + 23'h1));
+   assign VIDEO_BASE_ADR[22:20] = VIDEO_BASE_X_D_q;
+   assign VIDEO_BASE_ADR[19:12] = VIDEO_BASE_H_D_q;
+   assign VIDEO_BASE_ADR[11:4] = VIDEO_BASE_M_D_q;
+   assign VIDEO_BASE_ADR[3:0] = VIDEO_BASE_L_D_q[7:4];
+   assign VDM_SEL = VIDEO_BASE_L_D_q[3:0];
+
+//  AKTUELLE VIDEO ADRESSE
+   assign VIDEO_ACT_ADR[26:4] = VIDEO_ADR_CNT_q - {14'b00_0000_0000_0000,
+	 FIFO_MW};
+   assign VIDEO_ACT_ADR[3:0] = VDM_SEL;
+
+// ---------------------------------------------------------------------------------------
+//  REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
+// ---------------------------------------------------------------------------------------
+   assign DDR_REFRESH_CNT0_clk_ctrl = CLK33M;
+
+//  ZÄHLEN 0-2047
+   assign DDR_REFRESH_CNT_d = DDR_REFRESH_CNT_q + 11'b000_0000_0001;
+   assign REFRESH_TIME_clk = DDRCLK0;
+
+//  SYNC
+   assign REFRESH_TIME_d = DDR_REFRESH_CNT_q == 11'b000_0000_0000 &
+	 (!MAIN_CLK);
+   assign DDR_REFRESH_SIG0_clk_ctrl = DDRCLK0;
+   assign DDR_REFRESH_SIG0_ena_ctrl = REFRESH_TIME_q | DDR_SM__q == 6'b10_0011;
+
+//  9 STÜCK (8 REFRESH UND 1 ALS VORLAUF)
+//  MINUS 1 WENN GEMACHT
+   assign DDR_REFRESH_SIG_d = ({4{REFRESH_TIME_q}} & 4'b1001 &
+	 {4{DDR_REFRESH_ON}} & {4{!DDR_CONFIG}}) | ({4{!REFRESH_TIME_q}} &
+	 (DDR_REFRESH_SIG_q - 4'b0001) & {4{DDR_REFRESH_ON}} &
+	 {4{!DDR_CONFIG}});
+   assign DDR_REFRESH_REQ_clk = DDRCLK0;
+   assign DDR_REFRESH_REQ_d = DDR_REFRESH_SIG_q != 4'b0000 & DDR_REFRESH_ON &
+	 (!REFRESH_TIME_q) & (!DDR_CONFIG);
+
+// ---------------------------------------------------------
+//  VIDEO REGISTER -----------------------
+// -------------------------------------------------------------------------------------------------------------------
+   assign VIDEO_BASE_L_D0_clk_ctrl = MAIN_CLK;
+
+//  820D/2
+   assign VIDEO_BASE_L = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C106;
+
+//  SORRY, NUR 16 BYT GRENZEN
+   assign VIDEO_BASE_L_D_d = FB_AD[23:16];
+   assign VIDEO_BASE_L_D0_ena_ctrl = (!nFB_WR) & VIDEO_BASE_L & FB_B[1];
+   assign VIDEO_BASE_M_D0_clk_ctrl = MAIN_CLK;
+
+//  8203/2
+   assign VIDEO_BASE_M = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C101;
+   assign VIDEO_BASE_M_D_d = FB_AD[23:16];
+   assign VIDEO_BASE_M_D0_ena_ctrl = (!nFB_WR) & VIDEO_BASE_M & FB_B[3];
+   assign VIDEO_BASE_H_D0_clk_ctrl = MAIN_CLK;
+
+//  8200-1/2
+   assign VIDEO_BASE_H = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C100;
+   assign VIDEO_BASE_H_D_d = FB_AD[23:16];
+   assign VIDEO_BASE_H_D0_ena_ctrl = (!nFB_WR) & VIDEO_BASE_H & FB_B[1];
+   assign VIDEO_BASE_X_D0_clk_ctrl = MAIN_CLK;
+   assign VIDEO_BASE_X_D_d = FB_AD[26:24];
+   assign VIDEO_BASE_X_D0_ena_ctrl = (!nFB_WR) & VIDEO_BASE_H & FB_B[0];
+
+//  8209/2
+   assign VIDEO_CNT_L = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C104;
+
+//  8207/2
+   assign VIDEO_CNT_M = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C103;
+
+//  8204,5/2
+   assign VIDEO_CNT_H = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C102;
+
+//  GE
+   assign VIDEO_BASE_X_D_FULL = {5'b0_0000, VIDEO_BASE_X_D_q};
+   assign u0_data = ({8{VIDEO_BASE_H}} & VIDEO_BASE_X_D_FULL) |
+	 ({8{VIDEO_CNT_H}} & {5'b0_0000, VIDEO_ACT_ADR[26:24]});
+   assign u0_enabledt = (VIDEO_BASE_H | VIDEO_CNT_H) & (!nFB_OE);
+   assign FB_AD[31:24] = u0_tridata;
+   assign u1_data = ({8{VIDEO_BASE_L}} & VIDEO_BASE_L_D_q) | ({8{VIDEO_BASE_M}}
+	 & VIDEO_BASE_M_D_q) | ({8{VIDEO_BASE_H}} & VIDEO_BASE_H_D_q) |
+	 ({8{VIDEO_CNT_L}} & VIDEO_ACT_ADR[7:0]) | ({8{VIDEO_CNT_M}} &
+	 VIDEO_ACT_ADR[15:8]) | ({8{VIDEO_CNT_H}} & VIDEO_ACT_ADR[23:16]);
+   assign u1_enabledt = (VIDEO_BASE_L | VIDEO_BASE_M | VIDEO_BASE_H |
+	 VIDEO_CNT_L | VIDEO_CNT_M | VIDEO_CNT_H) & (!nFB_OE);
+   assign FB_AD[23:16] = u1_tridata;
+
+
+// Assignments added to explicitly combine the
+// effects of multiple drivers in the source
+   assign FIFO_BANK_OK_d = FIFO_BANK_OK_d_1 | FIFO_BANK_OK_d_2;
+   assign BUS_CYC_d = BUS_CYC_d_1 | BUS_CYC_d_2;
+   assign BA[0] = BA0_1 | BA0_2;
+   assign BA[1] = BA1_1 | BA1_2;
+   assign VA[0] = VA0_1 | VA0_2;
+   assign VA[1] = VA1_1 | VA1_2;
+   assign VA[2] = VA2_1 | VA2_2;
+   assign VA[3] = VA3_1 | VA3_2;
+   assign VA[4] = VA4_1 | VA4_2;
+   assign VA[5] = VA5_1 | VA5_2;
+   assign VA[6] = VA6_1 | VA6_2;
+   assign VA[7] = VA7_1 | VA7_2;
+   assign VA[8] = VA8_1 | VA8_2;
+   assign VA[9] = VA9_1 | VA9_2;
+   assign VA[10] = VA10_1 | VA10_2;
+   assign VA[11] = VA11_1 | VA11_2;
+   assign VA[12] = VA12_1 | VA12_2;
+
+// Define power signal(s)
+   assign vcc = 1'b1;
+   assign gnd = 1'b0;
+endmodule
diff --git a/FPGA_quartus_GE/ahdl2v/VIDEO_MOD_MUX_CLUTCTR.tdf b/FPGA_quartus_GE/ahdl2v/VIDEO_MOD_MUX_CLUTCTR.tdf
new file mode 100644
index 0000000..83c39d3
--- /dev/null
+++ b/FPGA_quartus_GE/ahdl2v/VIDEO_MOD_MUX_CLUTCTR.tdf
@@ -0,0 +1,684 @@
+TITLE "VIDEO MODUSE UND CLUT CONTROL";
+
+-- CREATED BY FREDI ASCHWANDEN
+
+-- GE http://quartushelp.altera.com/current/mergedProjects/hdl/ahdl/ahdl_elements_arithmetic_operators.htm
+
+INCLUDE "lpm_bustri_WORD.inc";
+INCLUDE "lpm_bustri_BYT.inc";
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	nRSTO : INPUT;
+	MAIN_CLK : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	nFB_CS3 : INPUT;
+	nFB_WR : INPUT;
+	nFB_OE : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	nFB_BURST : INPUT;
+	FB_ADR[31..0] : INPUT;
+	CLK33M : INPUT;
+	CLK25M : INPUT;
+	BLITTER_RUN : INPUT;
+	CLK_VIDEO : INPUT;
+	VR_D[8..0] : INPUT;
+	VR_BUSY : INPUT;
+	COLOR8 : OUTPUT;
+	ACP_CLUT_RD : OUTPUT;
+	COLOR1 : OUTPUT;
+	FALCON_CLUT_RDH : OUTPUT;
+	FALCON_CLUT_RDL : OUTPUT;
+	FALCON_CLUT_WR[3..0] : OUTPUT;
+	ST_CLUT_RD : OUTPUT;
+	ST_CLUT_WR[1..0] : OUTPUT;
+	CLUT_MUX_ADR[3..0] : OUTPUT;
+	HSYNC : OUTPUT;
+	VSYNC : OUTPUT;
+	nBLANK : OUTPUT;
+	nSYNC : OUTPUT;
+	nPD_VGA : OUTPUT;
+	FIFO_RDE : OUTPUT;
+	COLOR2 : OUTPUT;
+	COLOR4 : OUTPUT;
+	PIXEL_CLK : OUTPUT;
+	CLUT_OFF[3..0] : OUTPUT;
+	BLITTER_ON : OUTPUT;
+	VIDEO_RAM_CTR[15..0] : OUTPUT;
+	VIDEO_MOD_TA : OUTPUT;
+	CCR[23..0] : OUTPUT;
+	CCSEL[2..0] : OUTPUT;
+	ACP_CLUT_WR[3..0] : OUTPUT;
+	INTER_ZEI : OUTPUT;
+	DOP_FIFO_CLR : OUTPUT;
+	VIDEO_RECONFIG : OUTPUT;
+	VR_WR : OUTPUT;
+	VR_RD : OUTPUT;
+	CLR_FIFO : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	CLK17M						:DFF;
+	CLK13M						:DFF;
+	ACP_CLUT_CS					:NODE;
+	ACP_CLUT					:NODE;
+	VIDEO_PLL_CONFIG_CS			:NODE;
+	VR_WR						:DFF;
+	VR_DOUT[8..0]				:DFFE;
+	VR_FRQ[7..0]				:DFFE;
+	VIDEO_PLL_RECONFIG_CS		:NODE;
+	VIDEO_RECONFIG				:DFF;
+	FALCON_CLUT_CS				:NODE;
+	FALCON_CLUT					:NODE;
+	ST_CLUT_CS					:NODE;
+	ST_CLUT						:NODE;
+	FB_B[3..0]					:NODE;
+	FB_16B[1..0]				:NODE;
+	ST_SHIFT_MODE[1..0]			:DFFE;
+	ST_SHIFT_MODE_CS			:NODE;
+	FALCON_SHIFT_MODE[10..0]	:DFFE;
+	FALCON_SHIFT_MODE_CS		:NODE;
+	CLUT_MUX_ADR[3..0]			:DFF;
+	CLUT_MUX_AV[1..0][3..0]		:DFF;
+	ACP_VCTR_CS					:NODE;
+	ACP_VCTR[31..0]				:DFFE;
+	CCR_CS						:NODE;
+	CCR[23..0]					:DFFE;
+	ACP_VIDEO_ON				:NODE;
+	SYS_CTR[6..0]				:DFFE;
+	SYS_CTR_CS					:NODE;
+	VDL_LOF[15..0]				:DFFE;
+	VDL_LOF_CS					:NODE;
+	VDL_LWD[15..0]				:DFFE;
+	VDL_LWD_CS					:NODE;
+-- DIV. CONTROL REGISTER
+	CLUT_TA						:DFF;  			-- BRAUCHT EIN WAITSTAT
+	HSYNC						:DFF;
+	HSYNC_I[7..0]				:DFF;
+	HSY_LEN[7..0]				:DFF;			-- LÄNGE HSYNC PULS IN PIXEL_CLK
+	HSYNC_START					:DFF;
+	LAST						:DFF;			-- LETZTES PIXEL EINER ZEILE ERREICHT
+	VSYNC						:DFF;
+	VSYNC_START					:DFFE;
+	VSYNC_I[2..0]				:DFFE;
+	nBLANK						:DFF;
+	DISP_ON						:DFF;
+	DPO_ZL						:DFFE;
+	DPO_ON						:DFF;
+	DPO_OFF						:DFF;
+	VDTRON						:DFF;
+	VDO_ZL						:DFFE;
+	VDO_ON						:DFF;
+	VDO_OFF						:DFF;
+	VHCNT[11..0]				:DFF;
+	SUB_PIXEL_CNT[6..0]			:DFFE;
+	VVCNT[10..0]				:DFFE;
+	VERZ[2..0][9..0]			:DFF;
+	RAND[6..0]					:DFF;
+	RAND_ON						:NODE;
+	FIFO_RDE					:DFF;
+	CLR_FIFO					:DFFE;
+	START_ZEILE					:DFFE;
+	SYNC_PIX					:DFF;
+	SYNC_PIX1					:DFF;
+	SYNC_PIX2					:DFF;
+	CCSEL[2..0]					:DFF;
+	COLOR16						:NODE;
+	COLOR24						:NODE;
+-- ATARI RESOLUTION
+	ATARI_SYNC					:NODE;	 
+	ATARI_HH[31..0]				:DFFE;		-- HORIZONTAL TIMING 640x480
+	ATARI_HH_CS					:NODE;
+	ATARI_VH[31..0]				:DFFE;		-- VERTIKAL TIMING 640x480 
+	ATARI_VH_CS					:NODE;
+	ATARI_HL[31..0]				:DFFE;		-- HORIZONTAL TIMING 320x240
+	ATARI_HL_CS					:NODE;
+	ATARI_VL[31..0]				:DFFE;		-- VERTIKAL TIMING 320x240
+	ATARI_VL_CS					:NODE;
+-- HORIZONTAL
+	RAND_LINKS[11..0]			:NODE;
+	RAND_LINKS_FULL[23..0]		:NODE;		-- GE
+	HDIS_START[11..0]			:NODE;
+	HDIS_END[11..0]				:NODE;  
+	RAND_RECHTS[11..0]			:NODE;
+	HS_START[11..0]				:NODE;
+	HS_START_FULL[23..0]		:NODE;		-- GE
+	H_TOTAL[11..0]				:NODE;
+	H_TOTAL_FULL[23..0]			:NODE;		-- GE
+	HDIS_LEN[11..0]				:NODE;
+	MULF[5..0]					:NODE;
+	VDL_HHT[11..0]				:DFFE;
+	VDL_HHT_CS					:NODE;
+	VDL_HBE[11..0]				:DFFE;
+	VDL_HBE_CS					:NODE;
+	VDL_HDB[11..0]				:DFFE;
+	VDL_HDB_CS					:NODE;
+	VDL_HDE[11..0]				:DFFE;
+	VDL_HDE_CS					:NODE;
+	VDL_HBB[11..0]				:DFFE;
+	VDL_HBB_CS					:NODE;
+	VDL_HSS[11..0]				:DFFE;
+	VDL_HSS_CS					:NODE;
+-- VERTIKAL
+	RAND_OBEN[10..0]			:NODE; 
+	VDIS_START[10..0]			:NODE; 
+	VDIS_END[10..0]				:NODE; 
+	RAND_UNTEN[10..0]			:NODE; 
+	VS_START[10..0]				:NODE; 
+	V_TOTAL[10..0]				:NODE;  
+	FALCON_VIDEO				:NODE;
+	ST_VIDEO					:NODE;
+	INTER_ZEI					:DFF;
+	DOP_ZEI						:DFF;
+	DOP_FIFO_CLR				:DFF;
+	
+	VDL_VBE[10..0]				:DFFE;
+	VDL_VBE_CS					:NODE;
+	VDL_VDB[10..0]				:DFFE;
+	VDL_VDB_CS					:NODE;
+	VDL_VDE[10..0]				:DFFE;
+	VDL_VDE_CS					:NODE;
+	VDL_VBB[10..0]				:DFFE;
+	VDL_VBB_CS					:NODE;
+	VDL_VSS[10..0]				:DFFE;
+	VDL_VSS_CS					:NODE;
+	VDL_VFT[10..0]				:DFFE;
+	VDL_VFT_CS					:NODE;
+	VDL_VCT[8..0]				:DFFE;
+	VDL_VCT_CS					:NODE;
+	VDL_VMD[3..0]				:DFFE;
+	VDL_VMD_CS					:NODE;
+
+BEGIN
+-- BYT SELECT 32 BIT
+	FB_B0 = FB_ADR[1..0]==0;								-- ADR==0
+	FB_B1 = FB_ADR[1..0]==1									-- ADR==1
+		  # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1					-- HIGH WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B2 = FB_ADR[1..0]==2									-- ADR==2
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+	FB_B3 = FB_ADR[1..0]==3									-- ADR==3
+		  # FB_SIZE1 & !FB_SIZE0 &  FB_ADR1 				-- LOW WORD
+		  # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; 	-- LONG UND LINE
+-- BYT SELECT 16 BIT
+	FB_16B0 = FB_ADR[0]==0;									-- ADR==0
+	FB_16B1 = FB_ADR[0]==1									-- ADR==1
+		    # !(!FB_SIZE1 & FB_SIZE0);						-- NOT BYT
+-- ACP CLUT --
+	ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0";						-- 0-3FF/1024
+	ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
+	ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR;
+	CLUT_TA.CLK = MAIN_CLK;
+	CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA;
+--FALCON CLUT --
+	FALCON_CLUT_CS  = !nFB_CS1 & FB_ADR[19..10]==H"3E6";				-- $F9800/$400
+	FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1;				-- HIGH WORD
+	FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE &  FB_ADR1;				-- LOW WORD
+	FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
+	FALCON_CLUT_WR[3..2] = FB_16B[] &  FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
+-- ST CLUT --
+	ST_CLUT_CS  = !nFB_CS1 & FB_ADR[19..5]==H"7C12";					-- $F8240/$20
+	ST_CLUT_RD  = ST_CLUT_CS & !nFB_OE;
+	ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR;
+-- ST SHIFT MODE
+	ST_SHIFT_MODE[].CLK = MAIN_CLK;
+	ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130";				-- $F8260/2
+	ST_SHIFT_MODE[] = FB_AD[25..24];
+	ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
+	COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- MONO
+	COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 4 FARBEN
+	COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON;	-- 16 FARBEN
+-- FALCON SHIFT MODE
+	FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
+	FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133";			-- $F8266/2
+	FALCON_SHIFT_MODE[] = FB_AD[26..16];
+	FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
+	FALCON_SHIFT_MODE[7..0].ENA  = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
+	CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
+	COLOR1  = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR8  = FALCON_SHIFT_MODE4  & !COLOR16           & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR16 = FALCON_SHIFT_MODE8                       & FALCON_VIDEO & !ACP_VIDEO_ON;
+	COLOR4  = !COLOR1             & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
+-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
+	ACP_VCTR[].CLK = MAIN_CLK;
+	ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100";						-- $400/4
+	ACP_VCTR[31..8] = FB_AD[31..8];
+	ACP_VCTR[5..0] = FB_AD[5..0];
+	ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
+	ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR;
+	ACP_VCTR[15..8].ENA  = ACP_VCTR_CS & FB_B2 & !nFB_WR;
+	ACP_VCTR[5..0].ENA   = ACP_VCTR_CS & FB_B3 & !nFB_WR;
+	ACP_VIDEO_ON = ACP_VCTR0;
+	nPD_VGA = ACP_VCTR1;
+	-- ATARI MODUS
+	ATARI_SYNC = ACP_VCTR26;			-- WENN 1 AUTOMATISCHE AUFLÖSUNG
+	-- HORIZONTAL TIMING 640x480
+	ATARI_HH[].CLK = MAIN_CLK;
+	ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104";						-- $410/4
+	ATARI_HH[] = FB_AD[];
+	ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
+	ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
+	ATARI_HH[15..8].ENA  = ATARI_HH_CS & FB_B2 & !nFB_WR;
+	ATARI_HH[7..0].ENA   = ATARI_HH_CS & FB_B3 & !nFB_WR;
+	-- VERTIKAL TIMING 640x480
+	ATARI_VH[].CLK = MAIN_CLK;
+	ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105";						-- $414/4
+	ATARI_VH[] = FB_AD[];
+	ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
+	ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
+	ATARI_VH[15..8].ENA  = ATARI_VH_CS & FB_B2 & !nFB_WR;
+	ATARI_VH[7..0].ENA   = ATARI_VH_CS & FB_B3 & !nFB_WR;
+	-- HORIZONTAL TIMING 320x240
+	ATARI_HL[].CLK = MAIN_CLK;
+	ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106";						-- $418/4
+	ATARI_HL[] = FB_AD[];
+	ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
+	ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
+	ATARI_HL[15..8].ENA  = ATARI_HL_CS & FB_B2 & !nFB_WR;
+	ATARI_HL[7..0].ENA   = ATARI_HL_CS & FB_B3 & !nFB_WR;
+	-- VERTIKAL TIMING 320x240
+	ATARI_VL[].CLK = MAIN_CLK;
+	ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107";						-- $41C/4
+	ATARI_VL[] = FB_AD[];
+	ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
+	ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
+	ATARI_VL[15..8].ENA  = ATARI_VL_CS & FB_B2 & !nFB_WR;
+	ATARI_VL[7..0].ENA   = ATARI_VL_CS & FB_B3 & !nFB_WR;
+-- VIDEO PLL CONFIG
+	VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1;	-- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
+	VR_WR.CLK = MAIN_CLK;
+	VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
+	VR_RD = VIDEO_PLL_CONFIG_CS &  nFB_WR & !VR_BUSY;
+	VR_DOUT[].CLK = MAIN_CLK;
+	VR_DOUT[].ENA = !VR_BUSY;
+	VR_DOUT[] = VR_D[];
+	VR_FRQ[].CLK = MAIN_CLK;
+	VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
+	VR_FRQ[] = FB_AD[23..16];
+-- VIDEO PLL RECONFIG
+	VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0;		-- $(F)000'0800 
+	VIDEO_RECONFIG.CLK = MAIN_CLK;
+	VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
+------------------------------------------------------------------------------------------------------------------------
+	VIDEO_RAM_CTR[] = ACP_VCTR[31..16];
+-------------- COLOR MODE IM ACP SETZEN	
+	COLOR1   = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
+	COLOR8   = 			    ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
+	COLOR16  = 				   		     ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
+	COLOR24  = 										  ACP_VCTR2 & ACP_VIDEO_ON;
+	ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
+-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
+	ACP_VCTR7          = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
+	ACP_VCTR6          = ST_SHIFT_MODE_CS     & !nFB_WR & !ACP_VIDEO_ON;
+	ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
+	FALCON_VIDEO	   = ACP_VCTR7;
+	FALCON_CLUT        = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
+	ST_VIDEO		   = ACP_VCTR6;
+	ST_CLUT            = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1;
+	CCSEL[].CLK = PIXEL_CLK;
+	CCSEL[] = B"000" & ST_CLUT				-- ONLY FOR INFORMATION
+			# B"001" & FALCON_CLUT
+			# B"100" & ACP_CLUT
+			# B"101" & COLOR16
+			# B"110" & COLOR24
+			# B"111" & RAND_ON;
+-- DIVERSE (VIDEO)-REGISTER ----------------------------
+-- RANDFARBE
+	CCR[].CLK = MAIN_CLK;
+	CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101";						-- $404/4
+	CCR[] = FB_AD[23..0];
+	CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
+	CCR[15..8].ENA  = CCR_CS & FB_B2 & !nFB_WR;
+	CCR[7..0].ENA   = CCR_CS & FB_B3 & !nFB_WR;
+--SYS CTR
+	SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003";						-- $8006/2
+	SYS_CTR[].CLK = MAIN_CLK;
+	SYS_CTR[6..0] = FB_AD[22..16];
+	SYS_CTR[6..0].ENA  = SYS_CTR_CS & !nFB_WR & FB_B3;
+	BLITTER_ON = !SYS_CTR3;
+--VDL_LOF
+	VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107";						-- $820E/2
+	VDL_LOF[].CLK = MAIN_CLK;
+	VDL_LOF[] = FB_AD[31..16];
+	VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
+	VDL_LOF[7..0].ENA  = VDL_LOF_CS & !nFB_WR & FB_B3;
+--VDL_LWD
+	VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108";						-- $8210/2
+	VDL_LWD[].CLK = MAIN_CLK;
+	VDL_LWD[] = FB_AD[31..16];
+	VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
+	VDL_LWD[7..0].ENA  = VDL_LWD_CS & !nFB_WR & FB_B1;
+-- HORIZONTAL
+-- VDL_HHT
+	VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141";						-- $8282/2
+	VDL_HHT[].CLK = MAIN_CLK;
+	VDL_HHT[] = FB_AD[27..16];
+	VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
+	VDL_HHT[7..0].ENA  = VDL_HHT_CS & !nFB_WR & FB_B3;
+-- VDL_HBE
+	VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143";						-- $8286/2
+	VDL_HBE[].CLK = MAIN_CLK;
+	VDL_HBE[] = FB_AD[27..16];
+	VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
+	VDL_HBE[7..0].ENA  = VDL_HBE_CS & !nFB_WR & FB_B3;
+-- VDL_HDB
+	VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144";						-- $8288/2
+	VDL_HDB[].CLK = MAIN_CLK;
+	VDL_HDB[] = FB_AD[27..16];
+	VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
+	VDL_HDB[7..0].ENA  = VDL_HDB_CS & !nFB_WR & FB_B1;
+-- VDL_HDE
+	VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145";						-- $828A/2
+	VDL_HDE[].CLK = MAIN_CLK;
+	VDL_HDE[] = FB_AD[27..16];
+	VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
+	VDL_HDE[7..0].ENA  = VDL_HDE_CS & !nFB_WR & FB_B3;
+-- VDL_HBB
+	VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142";						-- $8284/2
+	VDL_HBB[].CLK = MAIN_CLK;
+	VDL_HBB[] = FB_AD[27..16];
+	VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
+	VDL_HBB[7..0].ENA  = VDL_HBB_CS & !nFB_WR & FB_B1;
+-- VDL_HSS
+	VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146";						-- $828C/2
+	VDL_HSS[].CLK = MAIN_CLK;
+	VDL_HSS[] = FB_AD[27..16];
+	VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
+	VDL_HSS[7..0].ENA  = VDL_HSS_CS & !nFB_WR & FB_B1;
+-- VERTIKAL
+-- VDL_VBE
+	VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153";						-- $82A6/2
+	VDL_VBE[].CLK = MAIN_CLK;
+	VDL_VBE[] = FB_AD[26..16];
+	VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
+	VDL_VBE[7..0].ENA  = VDL_VBE_CS & !nFB_WR & FB_B3;
+-- VDL_VDB
+	VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154";						-- $82A8/2
+	VDL_VDB[].CLK = MAIN_CLK;
+	VDL_VDB[] = FB_AD[26..16];
+	VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
+	VDL_VDB[7..0].ENA  = VDL_VDB_CS & !nFB_WR & FB_B1;
+-- VDL_VDE
+	VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155";						-- $82AA/2
+	VDL_VDE[].CLK = MAIN_CLK;
+	VDL_VDE[] = FB_AD[26..16];
+	VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
+	VDL_VDE[7..0].ENA  = VDL_VDE_CS & !nFB_WR & FB_B3;
+-- VDL_VBB
+	VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152";						-- $82A4/2
+	VDL_VBB[].CLK = MAIN_CLK;
+	VDL_VBB[] = FB_AD[26..16];
+	VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
+	VDL_VBB[7..0].ENA  = VDL_VBB_CS & !nFB_WR & FB_B1;
+-- VDL_VSS
+	VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156";						-- $82AC/2
+	VDL_VSS[].CLK = MAIN_CLK;
+	VDL_VSS[] = FB_AD[26..16];
+	VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
+	VDL_VSS[7..0].ENA  = VDL_VSS_CS & !nFB_WR & FB_B1;
+-- VDL_VFT
+	VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151";						-- $82A2/2
+	VDL_VFT[].CLK = MAIN_CLK;
+	VDL_VFT[] = FB_AD[26..16];
+	VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
+	VDL_VFT[7..0].ENA  = VDL_VFT_CS & !nFB_WR & FB_B3;
+-- VDL_VCT
+	VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160";						-- $82C0/2
+	VDL_VCT[].CLK = MAIN_CLK;
+	VDL_VCT[] = FB_AD[24..16];
+	VDL_VCT[8].ENA 		= VDL_VCT_CS & !nFB_WR & FB_B0;
+	VDL_VCT[7..0].ENA  	= VDL_VCT_CS & !nFB_WR & FB_B1;
+-- VDL_VMD
+	VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161";						-- $82C2/2
+	VDL_VMD[].CLK = MAIN_CLK;
+	VDL_VMD[] = FB_AD[19..16];
+	VDL_VMD[3..0].ENA  	= VDL_VMD_CS & !nFB_WR & FB_B3;
+--- REGISTER OUT
+	FB_AD[31..16] = lpm_bustri_WORD(
+						ST_SHIFT_MODE_CS 		& (0,ST_SHIFT_MODE[],B"00000000") 
+					  #	FALCON_SHIFT_MODE_CS 	& (0,FALCON_SHIFT_MODE[])
+					  # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0])	 
+					  # VDL_LOF_CS & VDL_LOF[]
+					  # VDL_LWD_CS & VDL_LWD[]
+					  #	VDL_HBE_CS & (0,VDL_HBE[])
+					  #	VDL_HDB_CS & (0,VDL_HDB[])
+					  #	VDL_HDE_CS & (0,VDL_HDE[])
+					  #	VDL_HBB_CS & (0,VDL_HBB[])
+					  #	VDL_HSS_CS & (0,VDL_HSS[])
+					  #	VDL_HHT_CS & (0,VDL_HHT[])
+					  #	VDL_VBE_CS & (0,VDL_VBE[])
+					  #	VDL_VDB_CS & (0,VDL_VDB[])
+					  #	VDL_VDE_CS & (0,VDL_VDE[])
+					  #	VDL_VBB_CS & (0,VDL_VBB[])
+					  #	VDL_VSS_CS & (0,VDL_VSS[])
+					  #	VDL_VFT_CS & (0,VDL_VFT[])
+					  #	VDL_VCT_CS & (0,VDL_VCT[])			 
+					  #	VDL_VMD_CS & (0,VDL_VMD[])
+ 					  #	ACP_VCTR_CS & ACP_VCTR[31..16]
+ 					  #	ATARI_HH_CS & ATARI_HH[31..16]
+					  #	ATARI_VH_CS & ATARI_VH[31..16]
+					  #	ATARI_HL_CS & ATARI_HL[31..16]
+					  #	ATARI_VL_CS & ATARI_VL[31..16]
+					  #	CCR_CS & (0,CCR[23..16])
+ 					  #	VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
+ 					  #	VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
+					  ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
+					 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS 
+					 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
+					 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE);
+
+ 	FB_AD[15..0] = lpm_bustri_WORD(
+ 					   	ACP_VCTR_CS & ACP_VCTR[15..0]
+					  #	ATARI_HH_CS & ATARI_HH[15..0]
+					  #	ATARI_VH_CS & ATARI_VH[15..0]
+					  #	ATARI_HL_CS & ATARI_HL[15..0]
+					  #	ATARI_VL_CS & ATARI_VL[15..0]
+ 					  #	CCR_CS & CCR[15..0]
+ 					  ,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
+
+	VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS 
+			   	 # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
+				 # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
+				 # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
+	
+-- VIDEO AUSGABE SETZEN
+	CLK17M.CLK = CLK33M;
+	CLK17M = !CLK17M;
+	CLK13M.CLK = CLK25M;
+	CLK13M = !CLK13M;
+	PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0) 
+			#	CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
+			#	CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
+			#	CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
+			#	CLK25M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	CLK33M     & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#	CLK_VIDEO  & ACP_VIDEO_ON & ACP_VCTR[9];
+--------------------------------------------------------------
+-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK
+----------------------------------------------------------------
+	HSY_LEN[].CLK = MAIN_CLK;		
+	HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 &  VDL_VCT2 #  VDL_VCT0)
+			#	16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 #  VDL_VCT0)
+			#	28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 &  VDL_VCT2 & !VDL_VCT0
+			#	32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) &  !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
+			#	28 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
+			#	32 &  ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
+			#   16 + (0,VR_FRQ[7..1]) &  ACP_VIDEO_ON & ACP_VCTR[9];			-- hsync puls length in pixeln=frequenz/ = 500ns
+
+ 	MULF[] =  2  & !ST_VIDEO &  VDL_VMD2						-- MULTIPLIKATIONS FAKTOR
+			# 4  & !ST_VIDEO & !VDL_VMD2
+			# 16 &  ST_VIDEO &  VDL_VMD2
+			# 32 &  ST_VIDEO & !VDL_VMD2;
+	 	
+	 	
+	HDIS_LEN[] =  320 &  VDL_VMD2								-- BREITE IN PIXELN
+			   #  640 & !VDL_VMD2;
+					
+-- DOPPELZEILENMODUS
+	DOP_ZEI.CLK = MAIN_CLK;
+	DOP_ZEI = VDL_VMD0 & ST_VIDEO;								-- ZEILENVERDOPPELUNG EIN AUS
+	INTER_ZEI.CLK = PIXEL_CLK;
+	INTER_ZEI =  DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) 	    -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
+	          #  DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); 		-- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
+	DOP_FIFO_CLR.CLK = PIXEL_CLK;
+	DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX;				-- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
+
+	RAND_LINKS_FULL[] = VDL_HBE[] * (0,MULF[5..1]);	-- GE
+	HS_START_FULL[] = (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1]);	-- GE
+	H_TOTAL_FULL[] = (VDL_HHT[]+2) * (0,MULF[]); -- GE
+					
+	RAND_LINKS[] 	=  VDL_HBE[] 									&  ACP_VIDEO_ON
+					#  21											& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  42											& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					#  RAND_LINKS_FULL[11..0]						& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  					
+	HDIS_START[] 	=  VDL_HDB[] 									&  ACP_VIDEO_ON
+					#  RAND_LINKS[]+1 								& !ACP_VIDEO_ON;						--  
+	HDIS_END[]	 	=  VDL_HDE[] 									&  ACP_VIDEO_ON
+					#  RAND_LINKS[]+HDIS_LEN[]						& !ACP_VIDEO_ON; 						--  
+	RAND_RECHTS[] 	=  VDL_HBB[] 									&  ACP_VIDEO_ON
+					#  HDIS_END[]+1									& !ACP_VIDEO_ON; 						--  
+	HS_START[]		=  VDL_HSS[] 									&  ACP_VIDEO_ON
+					#  ATARI_HL[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_HH[11..0]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					#  HS_START_FULL[11..0]							& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
+	H_TOTAL[] 		=  VDL_HHT[] 									&  ACP_VIDEO_ON
+					#  ATARI_HL[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_HH[27..16]								& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					#  H_TOTAL_FULL[11..0]	 						& !ACP_VIDEO_ON & !ATARI_SYNC; 			--  
+					
+	RAND_OBEN[]		=  VDL_VBE[]					&  ACP_VIDEO_ON
+					#  31							& !ACP_VIDEO_ON &  ATARI_SYNC 
+					# (0,VDL_VBE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
+	VDIS_START[]	=  VDL_VDB[]					&  ACP_VIDEO_ON
+					#  32							& !ACP_VIDEO_ON &  ATARI_SYNC 
+					# (0,VDL_VDB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
+	VDIS_END[]		=  VDL_VDE[]					&  ACP_VIDEO_ON
+					#  431							& !ACP_VIDEO_ON &  ATARI_SYNC &  ST_VIDEO
+					#  511							& !ACP_VIDEO_ON &  ATARI_SYNC & !ST_VIDEO
+					# (0,VDL_VDE[10..1]) 			& !ACP_VIDEO_ON & !ATARI_SYNC; 	 
+	RAND_UNTEN[]	=  VDL_VBB[]					&  ACP_VIDEO_ON
+					#  VDIS_END[]+1					& !ACP_VIDEO_ON &  ATARI_SYNC 
+					# (0,VDL_VBB[10..1])+1  		& !ACP_VIDEO_ON & !ATARI_SYNC;  
+	VS_START[]		=  VDL_VSS[]					&  ACP_VIDEO_ON
+					#  ATARI_VL[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_VH[10..0]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (0,VDL_VSS[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
+	V_TOTAL[] 		=  VDL_VFT[]					&  ACP_VIDEO_ON
+					#  ATARI_VL[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC &  VDL_VMD2
+					#  ATARI_VH[26..16]				& !ACP_VIDEO_ON &  ATARI_SYNC & !VDL_VMD2
+					# (0,VDL_VFT[10..1])			& !ACP_VIDEO_ON & !ATARI_SYNC;
+-- ZÄHLER
+	LAST.CLK = PIXEL_CLK;
+	LAST = VHCNT[]==(H_TOTAL[]-2);
+	VHCNT[].CLK = PIXEL_CLK;
+	VHCNT[] = (VHCNT[] + 1) & !LAST;
+	VVCNT[].CLK = PIXEL_CLK;
+	VVCNT[].ENA = LAST;
+	VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
+-- DISPLAY ON OFF
+	DPO_ZL.CLK = PIXEL_CLK;
+	DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1);	-- 1 ZEILE DAVOR ON OFF
+	DPO_ZL.ENA = LAST;												-- AM ZEILENENDE ÜBERNEHMEN
+	DPO_ON.CLK = PIXEL_CLK;
+	DPO_ON = VHCNT[]==RAND_LINKS[];									-- BESSER EINZELN WEGEN TIMING
+	DPO_OFF.CLK = PIXEL_CLK;
+	DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1);
+	DISP_ON.CLK = PIXEL_CLK;
+	DISP_ON = DISP_ON & !DPO_OFF 
+			# DPO_ON & DPO_ZL;
+-- DATENTRANSFER ON OFF
+	VDO_ON.CLK = PIXEL_CLK;
+	VDO_ON = VHCNT[]==(HDIS_START[]-1);								-- BESSER EINZELN WEGEN TIMING
+	VDO_OFF.CLK = PIXEL_CLK;
+	VDO_OFF = VHCNT[]==HDIS_END[];
+	VDO_ZL.CLK = PIXEL_CLK;
+	VDO_ZL.ENA = LAST;												-- AM ZEILENENDE ÜBERNEHMEN
+	VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]);	-- 1 ZEILE DAVOR ON OFF
+	VDTRON.CLK = PIXEL_CLK;
+	VDTRON = VDTRON & !VDO_OFF
+		   # VDO_ON & VDO_ZL;
+-- VERZÖGERUNG UND SYNC	
+	HSYNC_START.CLK = PIXEL_CLK;
+	HSYNC_START = VHCNT[]==HS_START[]-3;
+	HSYNC_I[].CLK = PIXEL_CLK;
+	HSYNC_I[] = HSY_LEN[]    &  HSYNC_START
+			 # (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
+	VSYNC_START.CLK = PIXEL_CLK;
+	VSYNC_START.ENA = LAST;
+	VSYNC_START = VVCNT[]==(VS_START[]-3);						-- start am ende der Zeile vor dem vsync		
+	VSYNC_I[].CLK = PIXEL_CLK;
+	VSYNC_I[].ENA = LAST;										-- start am ende der Zeile vor dem vsync
+	VSYNC_I[] =   3 	    &  VSYNC_START						-- 3 zeilen vsync length
+			# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0;		-- runterzählen bis 0
+	VERZ[][].CLK = PIXEL_CLK;
+	VERZ[][1] = VERZ[][0];
+	VERZ[][2] = VERZ[][1];
+	VERZ[][3] = VERZ[][2];
+	VERZ[][4] = VERZ[][3];
+	VERZ[][5] = VERZ[][4];
+	VERZ[][6] = VERZ[][5];
+	VERZ[][7] = VERZ[][6];
+	VERZ[][8] = VERZ[][7];
+	VERZ[][9] = VERZ[][8];
+	VERZ[0][0] = DISP_ON;
+	VERZ[1][0] = HSYNC_I[]!=0;
+	VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
+				#  ACP_VCTR15 &  VDL_VCT6  & HSYNC_I[]==0;		-- NUR MÖGLICH WENN BEIDE
+	VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
+				#  ACP_VCTR15 &  VDL_VCT5  & VSYNC_I[]==0;		-- NUR MÖGLICH WENN BEIDE
+	nBLANK.CLK = PIXEL_CLK;
+	nBLANK =  VERZ[0][8];
+	HSYNC.CLK = PIXEL_CLK;
+	HSYNC  =  VERZ[1][9];
+	VSYNC.CLK = PIXEL_CLK;
+	VSYNC  =  VERZ[2][9];
+	nSYNC  = GND;
+-- RANDFARBE MACHEN ------------------------------------
+	RAND[].CLK = PIXEL_CLK;
+	RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
+	RAND[1] = RAND[0];
+	RAND[2] = RAND[1];
+	RAND[3] = RAND[2];
+	RAND[4] = RAND[3];
+	RAND[5] = RAND[4];
+	RAND[6] = RAND[5];
+	RAND_ON = RAND[6];
+----------------------------------------------------------
+	CLR_FIFO.CLK = PIXEL_CLK;
+	CLR_FIFO.ENA = LAST;
+	CLR_FIFO = VVCNT[]==V_TOTAL[]-2;								-- IN LETZTER ZEILE LÖSCHEN
+	START_ZEILE.CLK = PIXEL_CLK;
+	START_ZEILE.ENA = LAST;
+	START_ZEILE = VVCNT[]==0;										-- ZEILE 1
+	SYNC_PIX.CLK = PIXEL_CLK;
+	SYNC_PIX  = VHCNT[]==3 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SYNC_PIX1.CLK = PIXEL_CLK;
+	SYNC_PIX1 = VHCNT[]==5 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SYNC_PIX2.CLK = PIXEL_CLK;
+	SYNC_PIX2 = VHCNT[]==7 & START_ZEILE;							-- SUB PIXEL ZÄHLER SYNCHRONISIEREN
+	SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
+	SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
+	SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX;			--count up if display on sonst clear bei sync pix		
+	FIFO_RDE.CLK = PIXEL_CLK;	
+	FIFO_RDE = (SUB_PIXEL_CNT[6..0]==1 & COLOR1
+			  # SUB_PIXEL_CNT[5..0]==1 & COLOR2 
+			  # SUB_PIXEL_CNT[4..0]==1 & COLOR4 
+			  # SUB_PIXEL_CNT[3..0]==1 & COLOR8 
+			  # SUB_PIXEL_CNT[2..0]==1 & COLOR16 
+			  # SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON
+			  # SYNC_PIX # SYNC_PIX1 # SYNC_PIX2;				-- 3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
+	
+	CLUT_MUX_ADR[].CLK = PIXEL_CLK;
+	CLUT_MUX_AV[][].CLK = PIXEL_CLK; 
+	CLUT_MUX_AV[0][]  = SUB_PIXEL_CNT[3..0];
+	CLUT_MUX_AV[1][]  = CLUT_MUX_AV[0][];
+	CLUT_MUX_ADR[] = CLUT_MUX_AV[1][];
+END;
diff --git a/FPGA_quartus_GE/ahdl2v/VIDEO_MOD_MUX_CLUTCTR.v b/FPGA_quartus_GE/ahdl2v/VIDEO_MOD_MUX_CLUTCTR.v
new file mode 100644
index 0000000..acb5de0
--- /dev/null
+++ b/FPGA_quartus_GE/ahdl2v/VIDEO_MOD_MUX_CLUTCTR.v
@@ -0,0 +1,1474 @@
+// Xilinx XPort Language Converter, Version 4.1 (110)
+// 
+// AHDL    Design Source: VIDEO_MOD_MUX_CLUTCTR.tdf
+// Verilog Design Output: VIDEO_MOD_MUX_CLUTCTR.v
+// Created 02-Mar-2014 04:36 PM
+//
+// Copyright (c) 2014, Xilinx, Inc.  All Rights Reserved.
+// Xilinx Inc makes no warranty, expressed or implied, with respect to
+// the operation and/or functionality of the converted output files.
+// 
+
+// VIDEO MODUSE UND CLUT CONTROL
+
+
+//  CREATED BY FREDI ASCHWANDEN
+//  GE http://quartushelp.altera.com/current/mergedProjects/hdl/ahdl/ahdl_elements_arithmetic_operators.htm
+//  {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+//  {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+module VIDEO_MOD_MUX_CLUTCTR(nRSTO, MAIN_CLK, nFB_CS1, nFB_CS2, nFB_CS3,
+      nFB_WR, nFB_OE, FB_SIZE0, FB_SIZE1, nFB_BURST, FB_ADR, CLK33M, CLK25M,
+      BLITTER_RUN, CLK_VIDEO, VR_D, VR_BUSY, COLOR8, ACP_CLUT_RD, COLOR1,
+      FALCON_CLUT_RDH, FALCON_CLUT_RDL, FALCON_CLUT_WR, ST_CLUT_RD, ST_CLUT_WR,
+      CLUT_MUX_ADR, HSYNC, VSYNC, nBLANK, nSYNC, nPD_VGA, FIFO_RDE, COLOR2,
+      COLOR4, PIXEL_CLK, CLUT_OFF, BLITTER_ON, VIDEO_RAM_CTR, VIDEO_MOD_TA,
+      CCR, CCSEL, ACP_CLUT_WR, INTER_ZEI, DOP_FIFO_CLR, VIDEO_RECONFIG, VR_WR,
+      VR_RD, CLR_FIFO, FB_AD);
+
+//  {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+//  {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+   input nRSTO, MAIN_CLK, nFB_CS1, nFB_CS2, nFB_CS3, nFB_WR, nFB_OE, FB_SIZE0,
+	 FB_SIZE1, nFB_BURST;
+   input [31:0] FB_ADR;
+   input CLK33M, CLK25M, BLITTER_RUN, CLK_VIDEO;
+   input [8:0] VR_D;
+   input VR_BUSY;
+   output COLOR8, ACP_CLUT_RD, COLOR1, FALCON_CLUT_RDH, FALCON_CLUT_RDL;
+   output [3:0] FALCON_CLUT_WR;
+   output ST_CLUT_RD;
+   output [1:0] ST_CLUT_WR;
+   output [3:0] CLUT_MUX_ADR;
+   output HSYNC, VSYNC, nBLANK, nSYNC, nPD_VGA, FIFO_RDE, COLOR2, COLOR4,
+	 PIXEL_CLK;
+   output [3:0] CLUT_OFF;
+   output BLITTER_ON;
+   output [15:0] VIDEO_RAM_CTR;
+   output VIDEO_MOD_TA;
+   output [23:0] CCR;
+   output [2:0] CCSEL;
+   output [3:0] ACP_CLUT_WR;
+   output INTER_ZEI, DOP_FIFO_CLR, VIDEO_RECONFIG, VR_WR, VR_RD, CLR_FIFO;
+   inout [31:0] FB_AD;
+
+//  DIV. CONTROL REGISTER
+//  BRAUCHT EIN WAITSTAT
+//  LÄNGE HSYNC PULS IN PIXEL_CLK
+//  LETZTES PIXEL EINER ZEILE ERREICHT
+//  ATARI RESOLUTION
+//  HORIZONTAL TIMING 640x480
+//  VERTIKAL TIMING 640x480
+//  HORIZONTAL TIMING 320x240
+//  VERTIKAL TIMING 320x240
+//  HORIZONTAL
+//  GE
+//  GE
+//  GE
+//  VERTIKAL
+   wire CLK17M, CLK17M_d, CLK17M_clk, CLK13M, CLK13M_d, CLK13M_clk,
+	 ACP_CLUT_CS, ACP_CLUT, VIDEO_PLL_CONFIG_CS, VR_WR_d, VR_WR_clk;
+   wire [8:0] VR_DOUT;
+   wire [8:0] VR_DOUT_d;
+   wire [7:0] VR_FRQ;
+   wire [7:0] VR_FRQ_d;
+   wire VIDEO_PLL_RECONFIG_CS, VIDEO_RECONFIG_d, VIDEO_RECONFIG_clk,
+	 FALCON_CLUT_CS, FALCON_CLUT, ST_CLUT_CS, ST_CLUT;
+   wire [3:0] FB_B;
+   wire [1:0] FB_16B;
+   wire [1:0] ST_SHIFT_MODE;
+   wire [1:0] ST_SHIFT_MODE_d;
+   wire ST_SHIFT_MODE_CS;
+   wire [10:0] FALCON_SHIFT_MODE;
+   wire [10:0] FALCON_SHIFT_MODE_d;
+   wire FALCON_SHIFT_MODE_CS;
+   wire [3:0] CLUT_MUX_ADR_d;
+   wire [3:0] CLUT_MUX_AV1_;
+   wire [3:0] CLUT_MUX_AV1__d;
+   wire [3:0] CLUT_MUX_AV0_;
+   wire [3:0] CLUT_MUX_AV0__d;
+   wire ACP_VCTR_CS;
+   wire [31:0] ACP_VCTR;
+   wire [31:0] ACP_VCTR_d;
+   wire CCR_CS;
+   wire [23:0] CCR_d;
+   wire ACP_VIDEO_ON;
+   wire [6:0] SYS_CTR;
+   wire [6:0] SYS_CTR_d;
+   wire SYS_CTR_CS;
+   wire [15:0] VDL_LOF;
+   wire [15:0] VDL_LOF_d;
+   wire VDL_LOF_CS;
+   wire [15:0] VDL_LWD;
+   wire [15:0] VDL_LWD_d;
+   wire VDL_LWD_CS, CLUT_TA, CLUT_TA_d, CLUT_TA_clk, HSYNC_d, HSYNC_clk;
+   wire [7:0] HSYNC_I;
+   wire [7:0] HSYNC_I_d;
+   wire [7:0] HSY_LEN;
+   wire [7:0] HSY_LEN_d;
+   wire HSYNC_START, HSYNC_START_d, HSYNC_START_clk, LAST, LAST_d, LAST_clk,
+	 VSYNC_d, VSYNC_clk, VSYNC_START, VSYNC_START_d, VSYNC_START_clk,
+	 VSYNC_START_ena;
+   wire [2:0] VSYNC_I;
+   wire [2:0] VSYNC_I_d;
+   wire nBLANK_d, nBLANK_clk, DISP_ON, DISP_ON_d, DISP_ON_clk, DPO_ZL,
+	 DPO_ZL_d, DPO_ZL_clk, DPO_ZL_ena, DPO_ON, DPO_ON_d, DPO_ON_clk,
+	 DPO_OFF, DPO_OFF_d, DPO_OFF_clk, VDTRON, VDTRON_d, VDTRON_clk, VDO_ZL,
+	 VDO_ZL_d, VDO_ZL_clk, VDO_ZL_ena, VDO_ON, VDO_ON_d, VDO_ON_clk,
+	 VDO_OFF, VDO_OFF_d, VDO_OFF_clk;
+   wire [11:0] VHCNT;
+   wire [11:0] VHCNT_d;
+   wire [6:0] SUB_PIXEL_CNT;
+   wire [6:0] SUB_PIXEL_CNT_d;
+   wire [10:0] VVCNT;
+   wire [10:0] VVCNT_d;
+   wire [9:0] VERZ2_;
+   wire [9:0] VERZ2__d;
+   wire [9:0] VERZ1_;
+   wire [9:0] VERZ1__d;
+   wire [9:0] VERZ0_;
+   wire [9:0] VERZ0__d;
+   wire [6:0] RAND;
+   wire [6:0] RAND_d;
+   wire RAND_ON, FIFO_RDE_d, FIFO_RDE_clk, CLR_FIFO_d, CLR_FIFO_clk,
+	 CLR_FIFO_ena, START_ZEILE, START_ZEILE_d, START_ZEILE_clk,
+	 START_ZEILE_ena, SYNC_PIX, SYNC_PIX_d, SYNC_PIX_clk, SYNC_PIX1,
+	 SYNC_PIX1_d, SYNC_PIX1_clk, SYNC_PIX2, SYNC_PIX2_d, SYNC_PIX2_clk;
+   wire [2:0] CCSEL_d;
+   wire COLOR16, COLOR24, ATARI_SYNC;
+   wire [31:0] ATARI_HH;
+   wire [31:0] ATARI_HH_d;
+   wire ATARI_HH_CS;
+   wire [31:0] ATARI_VH;
+   wire [31:0] ATARI_VH_d;
+   wire ATARI_VH_CS;
+   wire [31:0] ATARI_HL;
+   wire [31:0] ATARI_HL_d;
+   wire ATARI_HL_CS;
+   wire [31:0] ATARI_VL;
+   wire [31:0] ATARI_VL_d;
+   wire ATARI_VL_CS;
+   wire [11:0] RAND_LINKS;
+   wire [23:0] RAND_LINKS_FULL;
+   wire [11:0] HDIS_START;
+   wire [11:0] HDIS_END;
+   wire [11:0] RAND_RECHTS;
+   wire [11:0] HS_START;
+   wire [23:0] HS_START_FULL;
+   wire [11:0] H_TOTAL;
+   wire [23:0] H_TOTAL_FULL;
+   wire [11:0] HDIS_LEN;
+   wire [5:0] MULF;
+   wire [11:0] VDL_HHT;
+   wire [11:0] VDL_HHT_d;
+   wire VDL_HHT_CS;
+   wire [11:0] VDL_HBE;
+   wire [11:0] VDL_HBE_d;
+   wire VDL_HBE_CS;
+   wire [11:0] VDL_HDB;
+   wire [11:0] VDL_HDB_d;
+   wire VDL_HDB_CS;
+   wire [11:0] VDL_HDE;
+   wire [11:0] VDL_HDE_d;
+   wire VDL_HDE_CS;
+   wire [11:0] VDL_HBB;
+   wire [11:0] VDL_HBB_d;
+   wire VDL_HBB_CS;
+   wire [11:0] VDL_HSS;
+   wire [11:0] VDL_HSS_d;
+   wire VDL_HSS_CS;
+   wire [10:0] RAND_OBEN;
+   wire [10:0] VDIS_START;
+   wire [10:0] VDIS_END;
+   wire [10:0] RAND_UNTEN;
+   wire [10:0] VS_START;
+   wire [10:0] V_TOTAL;
+   wire FALCON_VIDEO, ST_VIDEO, INTER_ZEI_d, INTER_ZEI_clk, DOP_ZEI, DOP_ZEI_d,
+	 DOP_ZEI_clk, DOP_FIFO_CLR_d, DOP_FIFO_CLR_clk;
+   wire [10:0] VDL_VBE;
+   wire [10:0] VDL_VBE_d;
+   wire VDL_VBE_CS;
+   wire [10:0] VDL_VDB;
+   wire [10:0] VDL_VDB_d;
+   wire VDL_VDB_CS;
+   wire [10:0] VDL_VDE;
+   wire [10:0] VDL_VDE_d;
+   wire VDL_VDE_CS;
+   wire [10:0] VDL_VBB;
+   wire [10:0] VDL_VBB_d;
+   wire VDL_VBB_CS;
+   wire [10:0] VDL_VSS;
+   wire [10:0] VDL_VSS_d;
+   wire VDL_VSS_CS;
+   wire [10:0] VDL_VFT;
+   wire [10:0] VDL_VFT_d;
+   wire VDL_VFT_CS;
+   wire [8:0] VDL_VCT;
+   wire [8:0] VDL_VCT_d;
+   wire VDL_VCT8_ena, VDL_VCT_CS;
+   wire [3:0] VDL_VMD;
+   wire [3:0] VDL_VMD_d;
+   wire VDL_VMD_CS;
+   wire [15:0] u0_data;
+   wire u0_enabledt;
+   wire [15:0] u0_tridata;
+   wire [15:0] u1_data;
+   wire u1_enabledt;
+   wire [15:0] u1_tridata;
+   wire gnd, COLOR16_1, COLOR16_2, VERZ1_0_d_1, VERZ1_0_d_2, COLOR4_1,
+	 COLOR4_2, COLOR1_1, COLOR1_2, COLOR1_3, COLOR8_1, COLOR8_2,
+	 CLUT_MUX_AV0_0_clk_ctrl, CLUT_MUX_AV1_0_clk_ctrl,
+	 CLUT_MUX_ADR0_clk_ctrl, SUB_PIXEL_CNT0_ena_ctrl,
+	 SUB_PIXEL_CNT0_clk_ctrl, RAND0_clk_ctrl, VERZ0_0_clk_ctrl,
+	 VERZ1_0_clk_ctrl, VERZ2_0_clk_ctrl, VSYNC_I0_ena_ctrl,
+	 VSYNC_I0_clk_ctrl, HSYNC_I0_clk_ctrl, VVCNT0_ena_ctrl,
+	 VVCNT0_clk_ctrl, VHCNT0_clk_ctrl, HSY_LEN0_clk_ctrl,
+	 VDL_VMD0_ena_ctrl, VDL_VMD0_clk_ctrl, VDL_VCT0_ena_ctrl,
+	 VDL_VCT0_clk_ctrl, VDL_VFT0_ena_ctrl, VDL_VFT8_ena_ctrl,
+	 VDL_VFT0_clk_ctrl, VDL_VSS0_ena_ctrl, VDL_VSS8_ena_ctrl,
+	 VDL_VSS0_clk_ctrl, VDL_VBB0_ena_ctrl, VDL_VBB8_ena_ctrl,
+	 VDL_VBB0_clk_ctrl, VDL_VDE0_ena_ctrl, VDL_VDE8_ena_ctrl,
+	 VDL_VDE0_clk_ctrl, VDL_VDB0_ena_ctrl, VDL_VDB8_ena_ctrl,
+	 VDL_VDB0_clk_ctrl, VDL_VBE0_ena_ctrl, VDL_VBE8_ena_ctrl,
+	 VDL_VBE0_clk_ctrl, VDL_HSS0_ena_ctrl, VDL_HSS8_ena_ctrl,
+	 VDL_HSS0_clk_ctrl, VDL_HBB0_ena_ctrl, VDL_HBB8_ena_ctrl,
+	 VDL_HBB0_clk_ctrl, VDL_HDE0_ena_ctrl, VDL_HDE8_ena_ctrl,
+	 VDL_HDE0_clk_ctrl, VDL_HDB0_ena_ctrl, VDL_HDB8_ena_ctrl,
+	 VDL_HDB0_clk_ctrl, VDL_HBE0_ena_ctrl, VDL_HBE8_ena_ctrl,
+	 VDL_HBE0_clk_ctrl, VDL_HHT0_ena_ctrl, VDL_HHT8_ena_ctrl,
+	 VDL_HHT0_clk_ctrl, VDL_LWD0_ena_ctrl, VDL_LWD8_ena_ctrl,
+	 VDL_LWD0_clk_ctrl, VDL_LOF0_ena_ctrl, VDL_LOF8_ena_ctrl,
+	 VDL_LOF0_clk_ctrl, SYS_CTR0_ena_ctrl, SYS_CTR0_clk_ctrl,
+	 CCR0_ena_ctrl, CCR8_ena_ctrl, CCR16_ena_ctrl, CCR0_clk_ctrl,
+	 CCSEL0_clk_ctrl, ACP_VCTR6_ena_ctrl, VR_FRQ0_ena_ctrl,
+	 VR_FRQ0_clk_ctrl, VR_DOUT0_ena_ctrl, VR_DOUT0_clk_ctrl,
+	 ATARI_VL0_ena_ctrl, ATARI_VL8_ena_ctrl, ATARI_VL16_ena_ctrl,
+	 ATARI_VL24_ena_ctrl, ATARI_VL0_clk_ctrl, ATARI_HL0_ena_ctrl,
+	 ATARI_HL8_ena_ctrl, ATARI_HL16_ena_ctrl, ATARI_HL24_ena_ctrl,
+	 ATARI_HL0_clk_ctrl, ATARI_VH0_ena_ctrl, ATARI_VH8_ena_ctrl,
+	 ATARI_VH16_ena_ctrl, ATARI_VH24_ena_ctrl, ATARI_VH0_clk_ctrl,
+	 ATARI_HH0_ena_ctrl, ATARI_HH8_ena_ctrl, ATARI_HH16_ena_ctrl,
+	 ATARI_HH24_ena_ctrl, ATARI_HH0_clk_ctrl, ACP_VCTR0_ena_ctrl,
+	 ACP_VCTR8_ena_ctrl, ACP_VCTR16_ena_ctrl, ACP_VCTR24_ena_ctrl,
+	 ACP_VCTR0_clk_ctrl, FALCON_SHIFT_MODE0_ena_ctrl,
+	 FALCON_SHIFT_MODE8_ena_ctrl, FALCON_SHIFT_MODE0_clk_ctrl,
+	 ST_SHIFT_MODE0_ena_ctrl, ST_SHIFT_MODE0_clk_ctrl;
+   reg CLK17M_q, CLK13M_q, VR_WR_q;
+   reg [8:0] VR_DOUT_q;
+   reg [7:0] VR_FRQ_q;
+   reg VIDEO_RECONFIG_q;
+   reg [1:0] ST_SHIFT_MODE_q;
+   reg [10:0] FALCON_SHIFT_MODE_q;
+   reg [3:0] CLUT_MUX_ADR_q;
+   reg [3:0] CLUT_MUX_AV1__q;
+   reg [3:0] CLUT_MUX_AV0__q;
+   reg [31:0] ACP_VCTR_q;
+   reg [23:0] CCR_q;
+   reg [6:0] SYS_CTR_q;
+   reg [15:0] VDL_LOF_q;
+   reg [15:0] VDL_LWD_q;
+   reg CLUT_TA_q, HSYNC_q;
+   reg [7:0] HSYNC_I_q;
+   reg [7:0] HSY_LEN_q;
+   reg HSYNC_START_q, LAST_q, VSYNC_q, VSYNC_START_q;
+   reg [2:0] VSYNC_I_q;
+   reg nBLANK_q, DISP_ON_q, DPO_ZL_q, DPO_ON_q, DPO_OFF_q, VDTRON_q, VDO_ZL_q,
+	 VDO_ON_q, VDO_OFF_q;
+   reg [11:0] VHCNT_q;
+   reg [6:0] SUB_PIXEL_CNT_q;
+   reg [10:0] VVCNT_q;
+   reg [9:0] VERZ2__q;
+   reg [9:0] VERZ1__q;
+   reg [9:0] VERZ0__q;
+   reg [6:0] RAND_q;
+   reg FIFO_RDE_q, CLR_FIFO_q, START_ZEILE_q, SYNC_PIX_q, SYNC_PIX1_q,
+	 SYNC_PIX2_q;
+   reg [2:0] CCSEL_q;
+   reg [31:0] ATARI_HH_q;
+   reg [31:0] ATARI_VH_q;
+   reg [31:0] ATARI_HL_q;
+   reg [31:0] ATARI_VL_q;
+   reg [11:0] VDL_HHT_q;
+   reg [11:0] VDL_HBE_q;
+   reg [11:0] VDL_HDB_q;
+   reg [11:0] VDL_HDE_q;
+   reg [11:0] VDL_HBB_q;
+   reg [11:0] VDL_HSS_q;
+   reg INTER_ZEI_q, DOP_ZEI_q, DOP_FIFO_CLR_q;
+   reg [10:0] VDL_VBE_q;
+   reg [10:0] VDL_VDB_q;
+   reg [10:0] VDL_VDE_q;
+   reg [10:0] VDL_VBB_q;
+   reg [10:0] VDL_VSS_q;
+   reg [10:0] VDL_VFT_q;
+   reg [8:0] VDL_VCT_q;
+   reg [3:0] VDL_VMD_q;
+
+
+// Sub Module Section
+   lpm_bustri_WORD  u0 (.data(u0_data), .enabledt(u0_enabledt),
+	 .tridata(u0_tridata));
+
+   lpm_bustri_WORD  u1 (.data(u1_data), .enabledt(u1_enabledt),
+	 .tridata(u1_tridata));
+
+
+   assign CLUT_MUX_ADR = CLUT_MUX_ADR_q;
+   always @(posedge CLUT_MUX_ADR0_clk_ctrl)
+      CLUT_MUX_ADR_q <= CLUT_MUX_ADR_d;
+
+   assign HSYNC = HSYNC_q;
+   always @(posedge HSYNC_clk)
+      HSYNC_q <= HSYNC_d;
+
+   assign VSYNC = VSYNC_q;
+   always @(posedge VSYNC_clk)
+      VSYNC_q <= VSYNC_d;
+
+   assign nBLANK = nBLANK_q;
+   always @(posedge nBLANK_clk)
+      nBLANK_q <= nBLANK_d;
+
+   assign FIFO_RDE = FIFO_RDE_q;
+   always @(posedge FIFO_RDE_clk)
+      FIFO_RDE_q <= FIFO_RDE_d;
+
+   assign CCR[23:16] = CCR_q[23:16];
+   always @(posedge CCR0_clk_ctrl)
+      if (CCR16_ena_ctrl)
+	 {CCR_q[23], CCR_q[22], CCR_q[21], CCR_q[20], CCR_q[19], CCR_q[18],
+	       CCR_q[17], CCR_q[16]} <= CCR_d[23:16];
+
+   assign CCR[15:8] = CCR_q[15:8];
+   always @(posedge CCR0_clk_ctrl)
+      if (CCR8_ena_ctrl)
+	 {CCR_q[15], CCR_q[14], CCR_q[13], CCR_q[12], CCR_q[11], CCR_q[10],
+	       CCR_q[9], CCR_q[8]} <= CCR_d[15:8];
+
+   assign CCR[7:0] = CCR_q[7:0];
+   always @(posedge CCR0_clk_ctrl)
+      if (CCR0_ena_ctrl)
+	 {CCR_q[7], CCR_q[6], CCR_q[5], CCR_q[4], CCR_q[3], CCR_q[2], CCR_q[1],
+	       CCR_q[0]} <= CCR_d[7:0];
+
+   assign CCSEL = CCSEL_q;
+   always @(posedge CCSEL0_clk_ctrl)
+      CCSEL_q <= CCSEL_d;
+
+   assign INTER_ZEI = INTER_ZEI_q;
+   always @(posedge INTER_ZEI_clk)
+      INTER_ZEI_q <= INTER_ZEI_d;
+
+   assign DOP_FIFO_CLR = DOP_FIFO_CLR_q;
+   always @(posedge DOP_FIFO_CLR_clk)
+      DOP_FIFO_CLR_q <= DOP_FIFO_CLR_d;
+
+   assign VIDEO_RECONFIG = VIDEO_RECONFIG_q;
+   always @(posedge VIDEO_RECONFIG_clk)
+      VIDEO_RECONFIG_q <= VIDEO_RECONFIG_d;
+
+   assign VR_WR = VR_WR_q;
+   always @(posedge VR_WR_clk)
+      VR_WR_q <= VR_WR_d;
+
+   assign CLR_FIFO = CLR_FIFO_q;
+   always @(posedge CLR_FIFO_clk)
+      if (CLR_FIFO_ena)
+	 CLR_FIFO_q <= CLR_FIFO_d;
+
+   always @(posedge CLK17M_clk)
+      CLK17M_q <= CLK17M_d;
+
+   always @(posedge CLK13M_clk)
+      CLK13M_q <= CLK13M_d;
+
+   always @(posedge VR_DOUT0_clk_ctrl)
+      if (VR_DOUT0_ena_ctrl)
+	 VR_DOUT_q <= VR_DOUT_d;
+
+   always @(posedge VR_FRQ0_clk_ctrl)
+      if (VR_FRQ0_ena_ctrl)
+	 VR_FRQ_q <= VR_FRQ_d;
+
+   always @(posedge ST_SHIFT_MODE0_clk_ctrl)
+      if (ST_SHIFT_MODE0_ena_ctrl)
+	 ST_SHIFT_MODE_q <= ST_SHIFT_MODE_d;
+
+   always @(posedge FALCON_SHIFT_MODE0_clk_ctrl)
+      if (FALCON_SHIFT_MODE8_ena_ctrl)
+	 {FALCON_SHIFT_MODE_q[10], FALCON_SHIFT_MODE_q[9],
+	       FALCON_SHIFT_MODE_q[8]} <= FALCON_SHIFT_MODE_d[10:8];
+
+   always @(posedge FALCON_SHIFT_MODE0_clk_ctrl)
+      if (FALCON_SHIFT_MODE0_ena_ctrl)
+	 {FALCON_SHIFT_MODE_q[7], FALCON_SHIFT_MODE_q[6],
+	       FALCON_SHIFT_MODE_q[5], FALCON_SHIFT_MODE_q[4],
+	       FALCON_SHIFT_MODE_q[3], FALCON_SHIFT_MODE_q[2],
+	       FALCON_SHIFT_MODE_q[1], FALCON_SHIFT_MODE_q[0]} <=
+	       FALCON_SHIFT_MODE_d[7:0];
+
+   always @(posedge CLUT_MUX_AV1_0_clk_ctrl)
+      CLUT_MUX_AV1__q <= CLUT_MUX_AV1__d;
+
+   always @(posedge CLUT_MUX_AV0_0_clk_ctrl)
+      CLUT_MUX_AV0__q <= CLUT_MUX_AV0__d;
+
+   always @(posedge ACP_VCTR0_clk_ctrl)
+      if (ACP_VCTR24_ena_ctrl)
+	 {ACP_VCTR_q[31], ACP_VCTR_q[30], ACP_VCTR_q[29], ACP_VCTR_q[28],
+	       ACP_VCTR_q[27], ACP_VCTR_q[26], ACP_VCTR_q[25], ACP_VCTR_q[24]}
+	       <= ACP_VCTR_d[31:24];
+
+   always @(posedge ACP_VCTR0_clk_ctrl)
+      if (ACP_VCTR16_ena_ctrl)
+	 {ACP_VCTR_q[23], ACP_VCTR_q[22], ACP_VCTR_q[21], ACP_VCTR_q[20],
+	       ACP_VCTR_q[19], ACP_VCTR_q[18], ACP_VCTR_q[17], ACP_VCTR_q[16]}
+	       <= ACP_VCTR_d[23:16];
+
+   always @(posedge ACP_VCTR0_clk_ctrl)
+      if (ACP_VCTR8_ena_ctrl)
+	 {ACP_VCTR_q[15], ACP_VCTR_q[14], ACP_VCTR_q[13], ACP_VCTR_q[12],
+	       ACP_VCTR_q[11], ACP_VCTR_q[10], ACP_VCTR_q[9], ACP_VCTR_q[8]} <=
+	       ACP_VCTR_d[15:8];
+
+   always @(posedge ACP_VCTR0_clk_ctrl)
+      if (ACP_VCTR6_ena_ctrl)
+	 {ACP_VCTR_q[7], ACP_VCTR_q[6]} <= ACP_VCTR_d[7:6];
+
+   always @(posedge ACP_VCTR0_clk_ctrl)
+      if (ACP_VCTR0_ena_ctrl)
+	 {ACP_VCTR_q[5], ACP_VCTR_q[4], ACP_VCTR_q[3], ACP_VCTR_q[2],
+	       ACP_VCTR_q[1], ACP_VCTR_q[0]} <= ACP_VCTR_d[5:0];
+
+   always @(posedge SYS_CTR0_clk_ctrl)
+      if (SYS_CTR0_ena_ctrl)
+	 SYS_CTR_q <= SYS_CTR_d;
+
+   always @(posedge VDL_LOF0_clk_ctrl)
+      if (VDL_LOF8_ena_ctrl)
+	 {VDL_LOF_q[15], VDL_LOF_q[14], VDL_LOF_q[13], VDL_LOF_q[12],
+	       VDL_LOF_q[11], VDL_LOF_q[10], VDL_LOF_q[9], VDL_LOF_q[8]} <=
+	       VDL_LOF_d[15:8];
+
+   always @(posedge VDL_LOF0_clk_ctrl)
+      if (VDL_LOF0_ena_ctrl)
+	 {VDL_LOF_q[7], VDL_LOF_q[6], VDL_LOF_q[5], VDL_LOF_q[4], VDL_LOF_q[3],
+	       VDL_LOF_q[2], VDL_LOF_q[1], VDL_LOF_q[0]} <= VDL_LOF_d[7:0];
+
+   always @(posedge VDL_LWD0_clk_ctrl)
+      if (VDL_LWD8_ena_ctrl)
+	 {VDL_LWD_q[15], VDL_LWD_q[14], VDL_LWD_q[13], VDL_LWD_q[12],
+	       VDL_LWD_q[11], VDL_LWD_q[10], VDL_LWD_q[9], VDL_LWD_q[8]} <=
+	       VDL_LWD_d[15:8];
+
+   always @(posedge VDL_LWD0_clk_ctrl)
+      if (VDL_LWD0_ena_ctrl)
+	 {VDL_LWD_q[7], VDL_LWD_q[6], VDL_LWD_q[5], VDL_LWD_q[4], VDL_LWD_q[3],
+	       VDL_LWD_q[2], VDL_LWD_q[1], VDL_LWD_q[0]} <= VDL_LWD_d[7:0];
+
+   always @(posedge CLUT_TA_clk)
+      CLUT_TA_q <= CLUT_TA_d;
+
+   always @(posedge HSYNC_I0_clk_ctrl)
+      HSYNC_I_q <= HSYNC_I_d;
+
+   always @(posedge HSY_LEN0_clk_ctrl)
+      HSY_LEN_q <= HSY_LEN_d;
+
+   always @(posedge HSYNC_START_clk)
+      HSYNC_START_q <= HSYNC_START_d;
+
+   always @(posedge LAST_clk)
+      LAST_q <= LAST_d;
+
+   always @(posedge VSYNC_START_clk)
+      if (VSYNC_START_ena)
+	 VSYNC_START_q <= VSYNC_START_d;
+
+   always @(posedge VSYNC_I0_clk_ctrl)
+      if (VSYNC_I0_ena_ctrl)
+	 VSYNC_I_q <= VSYNC_I_d;
+
+   always @(posedge DISP_ON_clk)
+      DISP_ON_q <= DISP_ON_d;
+
+   always @(posedge DPO_ZL_clk)
+      if (DPO_ZL_ena)
+	 DPO_ZL_q <= DPO_ZL_d;
+
+   always @(posedge DPO_ON_clk)
+      DPO_ON_q <= DPO_ON_d;
+
+   always @(posedge DPO_OFF_clk)
+      DPO_OFF_q <= DPO_OFF_d;
+
+   always @(posedge VDTRON_clk)
+      VDTRON_q <= VDTRON_d;
+
+   always @(posedge VDO_ZL_clk)
+      if (VDO_ZL_ena)
+	 VDO_ZL_q <= VDO_ZL_d;
+
+   always @(posedge VDO_ON_clk)
+      VDO_ON_q <= VDO_ON_d;
+
+   always @(posedge VDO_OFF_clk)
+      VDO_OFF_q <= VDO_OFF_d;
+
+   always @(posedge VHCNT0_clk_ctrl)
+      VHCNT_q <= VHCNT_d;
+
+   always @(posedge SUB_PIXEL_CNT0_clk_ctrl)
+      if (SUB_PIXEL_CNT0_ena_ctrl)
+	 SUB_PIXEL_CNT_q <= SUB_PIXEL_CNT_d;
+
+   always @(posedge VVCNT0_clk_ctrl)
+      if (VVCNT0_ena_ctrl)
+	 VVCNT_q <= VVCNT_d;
+
+   always @(posedge VERZ2_0_clk_ctrl)
+      VERZ2__q <= VERZ2__d;
+
+   always @(posedge VERZ1_0_clk_ctrl)
+      VERZ1__q <= VERZ1__d;
+
+   always @(posedge VERZ0_0_clk_ctrl)
+      VERZ0__q <= VERZ0__d;
+
+   always @(posedge RAND0_clk_ctrl)
+      RAND_q <= RAND_d;
+
+   always @(posedge START_ZEILE_clk)
+      if (START_ZEILE_ena)
+	 START_ZEILE_q <= START_ZEILE_d;
+
+   always @(posedge SYNC_PIX_clk)
+      SYNC_PIX_q <= SYNC_PIX_d;
+
+   always @(posedge SYNC_PIX1_clk)
+      SYNC_PIX1_q <= SYNC_PIX1_d;
+
+   always @(posedge SYNC_PIX2_clk)
+      SYNC_PIX2_q <= SYNC_PIX2_d;
+
+   always @(posedge ATARI_HH0_clk_ctrl)
+      if (ATARI_HH24_ena_ctrl)
+	 {ATARI_HH_q[31], ATARI_HH_q[30], ATARI_HH_q[29], ATARI_HH_q[28],
+	       ATARI_HH_q[27], ATARI_HH_q[26], ATARI_HH_q[25], ATARI_HH_q[24]}
+	       <= ATARI_HH_d[31:24];
+
+   always @(posedge ATARI_HH0_clk_ctrl)
+      if (ATARI_HH16_ena_ctrl)
+	 {ATARI_HH_q[23], ATARI_HH_q[22], ATARI_HH_q[21], ATARI_HH_q[20],
+	       ATARI_HH_q[19], ATARI_HH_q[18], ATARI_HH_q[17], ATARI_HH_q[16]}
+	       <= ATARI_HH_d[23:16];
+
+   always @(posedge ATARI_HH0_clk_ctrl)
+      if (ATARI_HH8_ena_ctrl)
+	 {ATARI_HH_q[15], ATARI_HH_q[14], ATARI_HH_q[13], ATARI_HH_q[12],
+	       ATARI_HH_q[11], ATARI_HH_q[10], ATARI_HH_q[9], ATARI_HH_q[8]} <=
+	       ATARI_HH_d[15:8];
+
+   always @(posedge ATARI_HH0_clk_ctrl)
+      if (ATARI_HH0_ena_ctrl)
+	 {ATARI_HH_q[7], ATARI_HH_q[6], ATARI_HH_q[5], ATARI_HH_q[4],
+	       ATARI_HH_q[3], ATARI_HH_q[2], ATARI_HH_q[1], ATARI_HH_q[0]} <=
+	       ATARI_HH_d[7:0];
+
+   always @(posedge ATARI_VH0_clk_ctrl)
+      if (ATARI_VH24_ena_ctrl)
+	 {ATARI_VH_q[31], ATARI_VH_q[30], ATARI_VH_q[29], ATARI_VH_q[28],
+	       ATARI_VH_q[27], ATARI_VH_q[26], ATARI_VH_q[25], ATARI_VH_q[24]}
+	       <= ATARI_VH_d[31:24];
+
+   always @(posedge ATARI_VH0_clk_ctrl)
+      if (ATARI_VH16_ena_ctrl)
+	 {ATARI_VH_q[23], ATARI_VH_q[22], ATARI_VH_q[21], ATARI_VH_q[20],
+	       ATARI_VH_q[19], ATARI_VH_q[18], ATARI_VH_q[17], ATARI_VH_q[16]}
+	       <= ATARI_VH_d[23:16];
+
+   always @(posedge ATARI_VH0_clk_ctrl)
+      if (ATARI_VH8_ena_ctrl)
+	 {ATARI_VH_q[15], ATARI_VH_q[14], ATARI_VH_q[13], ATARI_VH_q[12],
+	       ATARI_VH_q[11], ATARI_VH_q[10], ATARI_VH_q[9], ATARI_VH_q[8]} <=
+	       ATARI_VH_d[15:8];
+
+   always @(posedge ATARI_VH0_clk_ctrl)
+      if (ATARI_VH0_ena_ctrl)
+	 {ATARI_VH_q[7], ATARI_VH_q[6], ATARI_VH_q[5], ATARI_VH_q[4],
+	       ATARI_VH_q[3], ATARI_VH_q[2], ATARI_VH_q[1], ATARI_VH_q[0]} <=
+	       ATARI_VH_d[7:0];
+
+   always @(posedge ATARI_HL0_clk_ctrl)
+      if (ATARI_HL24_ena_ctrl)
+	 {ATARI_HL_q[31], ATARI_HL_q[30], ATARI_HL_q[29], ATARI_HL_q[28],
+	       ATARI_HL_q[27], ATARI_HL_q[26], ATARI_HL_q[25], ATARI_HL_q[24]}
+	       <= ATARI_HL_d[31:24];
+
+   always @(posedge ATARI_HL0_clk_ctrl)
+      if (ATARI_HL16_ena_ctrl)
+	 {ATARI_HL_q[23], ATARI_HL_q[22], ATARI_HL_q[21], ATARI_HL_q[20],
+	       ATARI_HL_q[19], ATARI_HL_q[18], ATARI_HL_q[17], ATARI_HL_q[16]}
+	       <= ATARI_HL_d[23:16];
+
+   always @(posedge ATARI_HL0_clk_ctrl)
+      if (ATARI_HL8_ena_ctrl)
+	 {ATARI_HL_q[15], ATARI_HL_q[14], ATARI_HL_q[13], ATARI_HL_q[12],
+	       ATARI_HL_q[11], ATARI_HL_q[10], ATARI_HL_q[9], ATARI_HL_q[8]} <=
+	       ATARI_HL_d[15:8];
+
+   always @(posedge ATARI_HL0_clk_ctrl)
+      if (ATARI_HL0_ena_ctrl)
+	 {ATARI_HL_q[7], ATARI_HL_q[6], ATARI_HL_q[5], ATARI_HL_q[4],
+	       ATARI_HL_q[3], ATARI_HL_q[2], ATARI_HL_q[1], ATARI_HL_q[0]} <=
+	       ATARI_HL_d[7:0];
+
+   always @(posedge ATARI_VL0_clk_ctrl)
+      if (ATARI_VL24_ena_ctrl)
+	 {ATARI_VL_q[31], ATARI_VL_q[30], ATARI_VL_q[29], ATARI_VL_q[28],
+	       ATARI_VL_q[27], ATARI_VL_q[26], ATARI_VL_q[25], ATARI_VL_q[24]}
+	       <= ATARI_VL_d[31:24];
+
+   always @(posedge ATARI_VL0_clk_ctrl)
+      if (ATARI_VL16_ena_ctrl)
+	 {ATARI_VL_q[23], ATARI_VL_q[22], ATARI_VL_q[21], ATARI_VL_q[20],
+	       ATARI_VL_q[19], ATARI_VL_q[18], ATARI_VL_q[17], ATARI_VL_q[16]}
+	       <= ATARI_VL_d[23:16];
+
+   always @(posedge ATARI_VL0_clk_ctrl)
+      if (ATARI_VL8_ena_ctrl)
+	 {ATARI_VL_q[15], ATARI_VL_q[14], ATARI_VL_q[13], ATARI_VL_q[12],
+	       ATARI_VL_q[11], ATARI_VL_q[10], ATARI_VL_q[9], ATARI_VL_q[8]} <=
+	       ATARI_VL_d[15:8];
+
+   always @(posedge ATARI_VL0_clk_ctrl)
+      if (ATARI_VL0_ena_ctrl)
+	 {ATARI_VL_q[7], ATARI_VL_q[6], ATARI_VL_q[5], ATARI_VL_q[4],
+	       ATARI_VL_q[3], ATARI_VL_q[2], ATARI_VL_q[1], ATARI_VL_q[0]} <=
+	       ATARI_VL_d[7:0];
+
+   always @(posedge VDL_HHT0_clk_ctrl)
+      if (VDL_HHT8_ena_ctrl)
+	 {VDL_HHT_q[11], VDL_HHT_q[10], VDL_HHT_q[9], VDL_HHT_q[8]} <=
+	       VDL_HHT_d[11:8];
+
+   always @(posedge VDL_HHT0_clk_ctrl)
+      if (VDL_HHT0_ena_ctrl)
+	 {VDL_HHT_q[7], VDL_HHT_q[6], VDL_HHT_q[5], VDL_HHT_q[4], VDL_HHT_q[3],
+	       VDL_HHT_q[2], VDL_HHT_q[1], VDL_HHT_q[0]} <= VDL_HHT_d[7:0];
+
+   always @(posedge VDL_HBE0_clk_ctrl)
+      if (VDL_HBE8_ena_ctrl)
+	 {VDL_HBE_q[11], VDL_HBE_q[10], VDL_HBE_q[9], VDL_HBE_q[8]} <=
+	       VDL_HBE_d[11:8];
+
+   always @(posedge VDL_HBE0_clk_ctrl)
+      if (VDL_HBE0_ena_ctrl)
+	 {VDL_HBE_q[7], VDL_HBE_q[6], VDL_HBE_q[5], VDL_HBE_q[4], VDL_HBE_q[3],
+	       VDL_HBE_q[2], VDL_HBE_q[1], VDL_HBE_q[0]} <= VDL_HBE_d[7:0];
+
+   always @(posedge VDL_HDB0_clk_ctrl)
+      if (VDL_HDB8_ena_ctrl)
+	 {VDL_HDB_q[11], VDL_HDB_q[10], VDL_HDB_q[9], VDL_HDB_q[8]} <=
+	       VDL_HDB_d[11:8];
+
+   always @(posedge VDL_HDB0_clk_ctrl)
+      if (VDL_HDB0_ena_ctrl)
+	 {VDL_HDB_q[7], VDL_HDB_q[6], VDL_HDB_q[5], VDL_HDB_q[4], VDL_HDB_q[3],
+	       VDL_HDB_q[2], VDL_HDB_q[1], VDL_HDB_q[0]} <= VDL_HDB_d[7:0];
+
+   always @(posedge VDL_HDE0_clk_ctrl)
+      if (VDL_HDE8_ena_ctrl)
+	 {VDL_HDE_q[11], VDL_HDE_q[10], VDL_HDE_q[9], VDL_HDE_q[8]} <=
+	       VDL_HDE_d[11:8];
+
+   always @(posedge VDL_HDE0_clk_ctrl)
+      if (VDL_HDE0_ena_ctrl)
+	 {VDL_HDE_q[7], VDL_HDE_q[6], VDL_HDE_q[5], VDL_HDE_q[4], VDL_HDE_q[3],
+	       VDL_HDE_q[2], VDL_HDE_q[1], VDL_HDE_q[0]} <= VDL_HDE_d[7:0];
+
+   always @(posedge VDL_HBB0_clk_ctrl)
+      if (VDL_HBB8_ena_ctrl)
+	 {VDL_HBB_q[11], VDL_HBB_q[10], VDL_HBB_q[9], VDL_HBB_q[8]} <=
+	       VDL_HBB_d[11:8];
+
+   always @(posedge VDL_HBB0_clk_ctrl)
+      if (VDL_HBB0_ena_ctrl)
+	 {VDL_HBB_q[7], VDL_HBB_q[6], VDL_HBB_q[5], VDL_HBB_q[4], VDL_HBB_q[3],
+	       VDL_HBB_q[2], VDL_HBB_q[1], VDL_HBB_q[0]} <= VDL_HBB_d[7:0];
+
+   always @(posedge VDL_HSS0_clk_ctrl)
+      if (VDL_HSS8_ena_ctrl)
+	 {VDL_HSS_q[11], VDL_HSS_q[10], VDL_HSS_q[9], VDL_HSS_q[8]} <=
+	       VDL_HSS_d[11:8];
+
+   always @(posedge VDL_HSS0_clk_ctrl)
+      if (VDL_HSS0_ena_ctrl)
+	 {VDL_HSS_q[7], VDL_HSS_q[6], VDL_HSS_q[5], VDL_HSS_q[4], VDL_HSS_q[3],
+	       VDL_HSS_q[2], VDL_HSS_q[1], VDL_HSS_q[0]} <= VDL_HSS_d[7:0];
+
+   always @(posedge DOP_ZEI_clk)
+      DOP_ZEI_q <= DOP_ZEI_d;
+
+   always @(posedge VDL_VBE0_clk_ctrl)
+      if (VDL_VBE8_ena_ctrl)
+	 {VDL_VBE_q[10], VDL_VBE_q[9], VDL_VBE_q[8]} <= VDL_VBE_d[10:8];
+
+   always @(posedge VDL_VBE0_clk_ctrl)
+      if (VDL_VBE0_ena_ctrl)
+	 {VDL_VBE_q[7], VDL_VBE_q[6], VDL_VBE_q[5], VDL_VBE_q[4], VDL_VBE_q[3],
+	       VDL_VBE_q[2], VDL_VBE_q[1], VDL_VBE_q[0]} <= VDL_VBE_d[7:0];
+
+   always @(posedge VDL_VDB0_clk_ctrl)
+      if (VDL_VDB8_ena_ctrl)
+	 {VDL_VDB_q[10], VDL_VDB_q[9], VDL_VDB_q[8]} <= VDL_VDB_d[10:8];
+
+   always @(posedge VDL_VDB0_clk_ctrl)
+      if (VDL_VDB0_ena_ctrl)
+	 {VDL_VDB_q[7], VDL_VDB_q[6], VDL_VDB_q[5], VDL_VDB_q[4], VDL_VDB_q[3],
+	       VDL_VDB_q[2], VDL_VDB_q[1], VDL_VDB_q[0]} <= VDL_VDB_d[7:0];
+
+   always @(posedge VDL_VDE0_clk_ctrl)
+      if (VDL_VDE8_ena_ctrl)
+	 {VDL_VDE_q[10], VDL_VDE_q[9], VDL_VDE_q[8]} <= VDL_VDE_d[10:8];
+
+   always @(posedge VDL_VDE0_clk_ctrl)
+      if (VDL_VDE0_ena_ctrl)
+	 {VDL_VDE_q[7], VDL_VDE_q[6], VDL_VDE_q[5], VDL_VDE_q[4], VDL_VDE_q[3],
+	       VDL_VDE_q[2], VDL_VDE_q[1], VDL_VDE_q[0]} <= VDL_VDE_d[7:0];
+
+   always @(posedge VDL_VBB0_clk_ctrl)
+      if (VDL_VBB8_ena_ctrl)
+	 {VDL_VBB_q[10], VDL_VBB_q[9], VDL_VBB_q[8]} <= VDL_VBB_d[10:8];
+
+   always @(posedge VDL_VBB0_clk_ctrl)
+      if (VDL_VBB0_ena_ctrl)
+	 {VDL_VBB_q[7], VDL_VBB_q[6], VDL_VBB_q[5], VDL_VBB_q[4], VDL_VBB_q[3],
+	       VDL_VBB_q[2], VDL_VBB_q[1], VDL_VBB_q[0]} <= VDL_VBB_d[7:0];
+
+   always @(posedge VDL_VSS0_clk_ctrl)
+      if (VDL_VSS8_ena_ctrl)
+	 {VDL_VSS_q[10], VDL_VSS_q[9], VDL_VSS_q[8]} <= VDL_VSS_d[10:8];
+
+   always @(posedge VDL_VSS0_clk_ctrl)
+      if (VDL_VSS0_ena_ctrl)
+	 {VDL_VSS_q[7], VDL_VSS_q[6], VDL_VSS_q[5], VDL_VSS_q[4], VDL_VSS_q[3],
+	       VDL_VSS_q[2], VDL_VSS_q[1], VDL_VSS_q[0]} <= VDL_VSS_d[7:0];
+
+   always @(posedge VDL_VFT0_clk_ctrl)
+      if (VDL_VFT8_ena_ctrl)
+	 {VDL_VFT_q[10], VDL_VFT_q[9], VDL_VFT_q[8]} <= VDL_VFT_d[10:8];
+
+   always @(posedge VDL_VFT0_clk_ctrl)
+      if (VDL_VFT0_ena_ctrl)
+	 {VDL_VFT_q[7], VDL_VFT_q[6], VDL_VFT_q[5], VDL_VFT_q[4], VDL_VFT_q[3],
+	       VDL_VFT_q[2], VDL_VFT_q[1], VDL_VFT_q[0]} <= VDL_VFT_d[7:0];
+
+   always @(posedge VDL_VCT0_clk_ctrl)
+      if (VDL_VCT8_ena)
+	 VDL_VCT_q[8] <= VDL_VCT_d[8];
+
+   always @(posedge VDL_VCT0_clk_ctrl)
+      if (VDL_VCT0_ena_ctrl)
+	 {VDL_VCT_q[7], VDL_VCT_q[6], VDL_VCT_q[5], VDL_VCT_q[4], VDL_VCT_q[3],
+	       VDL_VCT_q[2], VDL_VCT_q[1], VDL_VCT_q[0]} <= VDL_VCT_d[7:0];
+
+   always @(posedge VDL_VMD0_clk_ctrl)
+      if (VDL_VMD0_ena_ctrl)
+	 VDL_VMD_q <= VDL_VMD_d;
+
+// Start of original equations
+
+//  BYT SELECT 32 BIT
+//  ADR==0
+   assign FB_B[0] = FB_ADR[1:0] == 2'b00;
+
+//  ADR==1
+//  HIGH WORD
+//  LONG UND LINE
+   assign FB_B[1] = FB_ADR[1:0] == 2'b01 | (FB_SIZE1 & (!FB_SIZE0) &
+	 (!FB_ADR[1])) | (FB_SIZE1 & FB_SIZE0) | ((!FB_SIZE1) & (!FB_SIZE0));
+
+//  ADR==2
+//  LONG UND LINE
+   assign FB_B[2] = FB_ADR[1:0] == 2'b10 | (FB_SIZE1 & FB_SIZE0) | ((!FB_SIZE1)
+	 & (!FB_SIZE0));
+
+//  ADR==3
+//  LOW WORD
+//  LONG UND LINE
+   assign FB_B[3] = FB_ADR[1:0] == 2'b11 | (FB_SIZE1 & (!FB_SIZE0) & FB_ADR[1])
+	 | (FB_SIZE1 & FB_SIZE0) | ((!FB_SIZE1) & (!FB_SIZE0));
+
+//  BYT SELECT 16 BIT
+//  ADR==0
+   assign FB_16B[0] = FB_ADR[0] == 1'b0;
+
+//  ADR==1
+//  NOT BYT
+   assign FB_16B[1] = FB_ADR[0] == 1'b1 | (!((!FB_SIZE1) & FB_SIZE0));
+
+//  ACP CLUT --
+//  0-3FF/1024
+   assign ACP_CLUT_CS = (!nFB_CS2) & FB_ADR[27:10] == 18'h0;
+   assign ACP_CLUT_RD = ACP_CLUT_CS & (!nFB_OE);
+   assign ACP_CLUT_WR = FB_B & {4{ACP_CLUT_CS}} & {4{!nFB_WR}};
+   assign CLUT_TA_clk = MAIN_CLK;
+   assign CLUT_TA_d = (ACP_CLUT_CS | FALCON_CLUT_CS | ST_CLUT_CS) &
+	 (!VIDEO_MOD_TA);
+
+// FALCON CLUT --
+//  $F9800/$400
+   assign FALCON_CLUT_CS = (!nFB_CS1) & FB_ADR[19:10] == 10'b11_1110_0110;
+
+//  HIGH WORD
+   assign FALCON_CLUT_RDH = FALCON_CLUT_CS & (!nFB_OE) & (!FB_ADR[1]);
+
+//  LOW WORD
+   assign FALCON_CLUT_RDL = FALCON_CLUT_CS & (!nFB_OE) & FB_ADR[1];
+   assign FALCON_CLUT_WR[1:0] = FB_16B & {2{!FB_ADR[1]}} & {2{FALCON_CLUT_CS}}
+	 & {2{!nFB_WR}};
+   assign FALCON_CLUT_WR[3:2] = FB_16B & {2{FB_ADR[1]}} & {2{FALCON_CLUT_CS}} &
+	 {2{!nFB_WR}};
+
+//  ST CLUT --
+//  $F8240/$20
+   assign ST_CLUT_CS = (!nFB_CS1) & FB_ADR[19:5] == 15'b111_1100_0001_0010;
+   assign ST_CLUT_RD = ST_CLUT_CS & (!nFB_OE);
+   assign ST_CLUT_WR = FB_16B & {2{ST_CLUT_CS}} & {2{!nFB_WR}};
+
+//  ST SHIFT MODE
+   assign ST_SHIFT_MODE0_clk_ctrl = MAIN_CLK;
+
+//  $F8260/2
+   assign ST_SHIFT_MODE_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C130;
+   assign ST_SHIFT_MODE_d = FB_AD[25:24];
+   assign ST_SHIFT_MODE0_ena_ctrl = ST_SHIFT_MODE_CS & (!nFB_WR) & FB_B[0];
+
+//  MONO
+   assign COLOR1_1 = ST_SHIFT_MODE_q == 2'b10 & (!COLOR8) & ST_VIDEO &
+	 (!ACP_VIDEO_ON);
+
+//  4 FARBEN
+   assign COLOR2 = ST_SHIFT_MODE_q == 2'b01 & (!COLOR8) & ST_VIDEO &
+	 (!ACP_VIDEO_ON);
+
+//  16 FARBEN
+   assign COLOR4_1 = ST_SHIFT_MODE_q == 2'b00 & (!COLOR8) & ST_VIDEO &
+	 (!ACP_VIDEO_ON);
+
+//  FALCON SHIFT MODE
+   assign FALCON_SHIFT_MODE0_clk_ctrl = MAIN_CLK;
+
+//  $F8266/2
+   assign FALCON_SHIFT_MODE_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C133;
+   assign FALCON_SHIFT_MODE_d = FB_AD[26:16];
+   assign FALCON_SHIFT_MODE8_ena_ctrl = FALCON_SHIFT_MODE_CS & (!nFB_WR) &
+	 FB_B[2];
+   assign FALCON_SHIFT_MODE0_ena_ctrl = FALCON_SHIFT_MODE_CS & (!nFB_WR) &
+	 FB_B[3];
+   assign CLUT_OFF = FALCON_SHIFT_MODE_q[3:0] & {4{COLOR4}};
+   assign COLOR1_2 = FALCON_SHIFT_MODE_q[10] & (!COLOR16) & (!COLOR8) &
+	 FALCON_VIDEO & (!ACP_VIDEO_ON);
+   assign COLOR8_1 = FALCON_SHIFT_MODE_q[4] & (!COLOR16) & FALCON_VIDEO &
+	 (!ACP_VIDEO_ON);
+   assign COLOR16_1 = FALCON_SHIFT_MODE_q[8] & FALCON_VIDEO & (!ACP_VIDEO_ON);
+   assign COLOR4_2 = (!COLOR1) & (!COLOR16) & (!COLOR8) & FALCON_VIDEO &
+	 (!ACP_VIDEO_ON);
+
+//  ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
+   assign ACP_VCTR0_clk_ctrl = MAIN_CLK;
+
+//  $400/4
+   assign ACP_VCTR_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h100;
+   assign ACP_VCTR_d[31:8] = FB_AD[31:8];
+   assign ACP_VCTR_d[5:0] = FB_AD[5:0];
+   assign ACP_VCTR24_ena_ctrl = ACP_VCTR_CS & FB_B[0] & (!nFB_WR);
+   assign ACP_VCTR16_ena_ctrl = ACP_VCTR_CS & FB_B[1] & (!nFB_WR);
+   assign ACP_VCTR8_ena_ctrl = ACP_VCTR_CS & FB_B[2] & (!nFB_WR);
+   assign ACP_VCTR0_ena_ctrl = ACP_VCTR_CS & FB_B[3] & (!nFB_WR);
+   assign ACP_VIDEO_ON = ACP_VCTR_q[0];
+   assign nPD_VGA = ACP_VCTR_q[1];
+
+//  ATARI MODUS
+//  WENN 1 AUTOMATISCHE AUFLÖSUNG
+   assign ATARI_SYNC = ACP_VCTR_q[26];
+
+//  HORIZONTAL TIMING 640x480
+   assign ATARI_HH0_clk_ctrl = MAIN_CLK;
+
+//  $410/4
+   assign ATARI_HH_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h104;
+   assign ATARI_HH_d = FB_AD;
+   assign ATARI_HH24_ena_ctrl = ATARI_HH_CS & FB_B[0] & (!nFB_WR);
+   assign ATARI_HH16_ena_ctrl = ATARI_HH_CS & FB_B[1] & (!nFB_WR);
+   assign ATARI_HH8_ena_ctrl = ATARI_HH_CS & FB_B[2] & (!nFB_WR);
+   assign ATARI_HH0_ena_ctrl = ATARI_HH_CS & FB_B[3] & (!nFB_WR);
+
+//  VERTIKAL TIMING 640x480
+   assign ATARI_VH0_clk_ctrl = MAIN_CLK;
+
+//  $414/4
+   assign ATARI_VH_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h105;
+   assign ATARI_VH_d = FB_AD;
+   assign ATARI_VH24_ena_ctrl = ATARI_VH_CS & FB_B[0] & (!nFB_WR);
+   assign ATARI_VH16_ena_ctrl = ATARI_VH_CS & FB_B[1] & (!nFB_WR);
+   assign ATARI_VH8_ena_ctrl = ATARI_VH_CS & FB_B[2] & (!nFB_WR);
+   assign ATARI_VH0_ena_ctrl = ATARI_VH_CS & FB_B[3] & (!nFB_WR);
+
+//  HORIZONTAL TIMING 320x240
+   assign ATARI_HL0_clk_ctrl = MAIN_CLK;
+
+//  $418/4
+   assign ATARI_HL_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h106;
+   assign ATARI_HL_d = FB_AD;
+   assign ATARI_HL24_ena_ctrl = ATARI_HL_CS & FB_B[0] & (!nFB_WR);
+   assign ATARI_HL16_ena_ctrl = ATARI_HL_CS & FB_B[1] & (!nFB_WR);
+   assign ATARI_HL8_ena_ctrl = ATARI_HL_CS & FB_B[2] & (!nFB_WR);
+   assign ATARI_HL0_ena_ctrl = ATARI_HL_CS & FB_B[3] & (!nFB_WR);
+
+//  VERTIKAL TIMING 320x240
+   assign ATARI_VL0_clk_ctrl = MAIN_CLK;
+
+//  $41C/4
+   assign ATARI_VL_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h107;
+   assign ATARI_VL_d = FB_AD;
+   assign ATARI_VL24_ena_ctrl = ATARI_VL_CS & FB_B[0] & (!nFB_WR);
+   assign ATARI_VL16_ena_ctrl = ATARI_VL_CS & FB_B[1] & (!nFB_WR);
+   assign ATARI_VL8_ena_ctrl = ATARI_VL_CS & FB_B[2] & (!nFB_WR);
+   assign ATARI_VL0_ena_ctrl = ATARI_VL_CS & FB_B[3] & (!nFB_WR);
+
+//  VIDEO PLL CONFIG
+//  $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
+   assign VIDEO_PLL_CONFIG_CS = (!nFB_CS2) & FB_ADR[27:9] == 19'h3 & FB_B[0] &
+	 FB_B[1];
+   assign VR_WR_clk = MAIN_CLK;
+   assign VR_WR_d = VIDEO_PLL_CONFIG_CS & (!nFB_WR) & (!VR_BUSY) & (!VR_WR_q);
+   assign VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & (!VR_BUSY);
+   assign VR_DOUT0_clk_ctrl = MAIN_CLK;
+   assign VR_DOUT0_ena_ctrl = !VR_BUSY;
+   assign VR_DOUT_d = VR_D;
+   assign VR_FRQ0_clk_ctrl = MAIN_CLK;
+   assign VR_FRQ0_ena_ctrl = VR_WR_q & FB_ADR[8:0] == 9'b0_0000_0100;
+   assign VR_FRQ_d = FB_AD[23:16];
+
+//  VIDEO PLL RECONFIG
+//  $(F)000'0800
+   assign VIDEO_PLL_RECONFIG_CS = (!nFB_CS2) & FB_ADR[27:0] == 28'h800 &
+	 FB_B[0];
+   assign VIDEO_RECONFIG_clk = MAIN_CLK;
+   assign VIDEO_RECONFIG_d = VIDEO_PLL_RECONFIG_CS & (!nFB_WR) & (!VR_BUSY) &
+	 (!VIDEO_RECONFIG_q);
+
+// ----------------------------------------------------------------------------------------------------------------------
+   assign VIDEO_RAM_CTR = ACP_VCTR_q[31:16];
+
+// ------------ COLOR MODE IM ACP SETZEN
+   assign COLOR1_3 = ACP_VCTR_q[5] & (!ACP_VCTR_q[4]) & (!ACP_VCTR_q[3]) &
+	 (!ACP_VCTR_q[2]) & ACP_VIDEO_ON;
+   assign COLOR8_2 = ACP_VCTR_q[4] & (!ACP_VCTR_q[3]) & (!ACP_VCTR_q[2]) &
+	 ACP_VIDEO_ON;
+   assign COLOR16_2 = ACP_VCTR_q[3] & (!ACP_VCTR_q[2]) & ACP_VIDEO_ON;
+   assign COLOR24 = ACP_VCTR_q[2] & ACP_VIDEO_ON;
+   assign ACP_CLUT = (ACP_VIDEO_ON & (COLOR1 | COLOR8)) | (ST_VIDEO & COLOR1);
+
+//  ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
+   assign ACP_VCTR_d[7] = FALCON_SHIFT_MODE_CS & (!nFB_WR) & (!ACP_VIDEO_ON);
+   assign ACP_VCTR_d[6] = ST_SHIFT_MODE_CS & (!nFB_WR) & (!ACP_VIDEO_ON);
+   assign ACP_VCTR6_ena_ctrl = (FALCON_SHIFT_MODE_CS & (!nFB_WR)) |
+	 (ST_SHIFT_MODE_CS & (!nFB_WR)) | (ACP_VCTR_CS & FB_B[3] & (!nFB_WR) &
+	 FB_AD[0]);
+   assign FALCON_VIDEO = ACP_VCTR_q[7];
+   assign FALCON_CLUT = FALCON_VIDEO & (!ACP_VIDEO_ON) & (!COLOR16);
+   assign ST_VIDEO = ACP_VCTR_q[6];
+   assign ST_CLUT = ST_VIDEO & (!ACP_VIDEO_ON) & (!FALCON_CLUT) & (!COLOR1);
+   assign CCSEL0_clk_ctrl = PIXEL_CLK;
+
+//  ONLY FOR INFORMATION
+   assign CCSEL_d = (3'b000 & {3{ST_CLUT}}) | (3'b001 & {3{FALCON_CLUT}}) |
+	 (3'b100 & {3{ACP_CLUT}}) | (3'b101 & {3{COLOR16}}) | (3'b110 &
+	 {3{COLOR24}}) | (3'b111 & {3{RAND_ON}});
+
+//  DIVERSE (VIDEO)-REGISTER ----------------------------
+//  RANDFARBE
+   assign CCR0_clk_ctrl = MAIN_CLK;
+
+//  $404/4
+   assign CCR_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h101;
+   assign CCR_d = FB_AD[23:0];
+   assign CCR16_ena_ctrl = CCR_CS & FB_B[1] & (!nFB_WR);
+   assign CCR8_ena_ctrl = CCR_CS & FB_B[2] & (!nFB_WR);
+   assign CCR0_ena_ctrl = CCR_CS & FB_B[3] & (!nFB_WR);
+
+// SYS CTR
+//  $8006/2
+   assign SYS_CTR_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C003;
+   assign SYS_CTR0_clk_ctrl = MAIN_CLK;
+   assign SYS_CTR_d = FB_AD[22:16];
+   assign SYS_CTR0_ena_ctrl = SYS_CTR_CS & (!nFB_WR) & FB_B[3];
+   assign BLITTER_ON = !SYS_CTR_q[3];
+
+// VDL_LOF
+//  $820E/2
+   assign VDL_LOF_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C107;
+   assign VDL_LOF0_clk_ctrl = MAIN_CLK;
+   assign VDL_LOF_d = FB_AD[31:16];
+   assign VDL_LOF8_ena_ctrl = VDL_LOF_CS & (!nFB_WR) & FB_B[2];
+   assign VDL_LOF0_ena_ctrl = VDL_LOF_CS & (!nFB_WR) & FB_B[3];
+
+// VDL_LWD
+//  $8210/2
+   assign VDL_LWD_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C108;
+   assign VDL_LWD0_clk_ctrl = MAIN_CLK;
+   assign VDL_LWD_d = FB_AD[31:16];
+   assign VDL_LWD8_ena_ctrl = VDL_LWD_CS & (!nFB_WR) & FB_B[0];
+   assign VDL_LWD0_ena_ctrl = VDL_LWD_CS & (!nFB_WR) & FB_B[1];
+
+//  HORIZONTAL
+//  VDL_HHT
+//  $8282/2
+   assign VDL_HHT_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C141;
+   assign VDL_HHT0_clk_ctrl = MAIN_CLK;
+   assign VDL_HHT_d = FB_AD[27:16];
+   assign VDL_HHT8_ena_ctrl = VDL_HHT_CS & (!nFB_WR) & FB_B[2];
+   assign VDL_HHT0_ena_ctrl = VDL_HHT_CS & (!nFB_WR) & FB_B[3];
+
+//  VDL_HBE
+//  $8286/2
+   assign VDL_HBE_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C143;
+   assign VDL_HBE0_clk_ctrl = MAIN_CLK;
+   assign VDL_HBE_d = FB_AD[27:16];
+   assign VDL_HBE8_ena_ctrl = VDL_HBE_CS & (!nFB_WR) & FB_B[2];
+   assign VDL_HBE0_ena_ctrl = VDL_HBE_CS & (!nFB_WR) & FB_B[3];
+
+//  VDL_HDB
+//  $8288/2
+   assign VDL_HDB_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C144;
+   assign VDL_HDB0_clk_ctrl = MAIN_CLK;
+   assign VDL_HDB_d = FB_AD[27:16];
+   assign VDL_HDB8_ena_ctrl = VDL_HDB_CS & (!nFB_WR) & FB_B[0];
+   assign VDL_HDB0_ena_ctrl = VDL_HDB_CS & (!nFB_WR) & FB_B[1];
+
+//  VDL_HDE
+//  $828A/2
+   assign VDL_HDE_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C145;
+   assign VDL_HDE0_clk_ctrl = MAIN_CLK;
+   assign VDL_HDE_d = FB_AD[27:16];
+   assign VDL_HDE8_ena_ctrl = VDL_HDE_CS & (!nFB_WR) & FB_B[2];
+   assign VDL_HDE0_ena_ctrl = VDL_HDE_CS & (!nFB_WR) & FB_B[3];
+
+//  VDL_HBB
+//  $8284/2
+   assign VDL_HBB_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C142;
+   assign VDL_HBB0_clk_ctrl = MAIN_CLK;
+   assign VDL_HBB_d = FB_AD[27:16];
+   assign VDL_HBB8_ena_ctrl = VDL_HBB_CS & (!nFB_WR) & FB_B[0];
+   assign VDL_HBB0_ena_ctrl = VDL_HBB_CS & (!nFB_WR) & FB_B[1];
+
+//  VDL_HSS
+//  $828C/2
+   assign VDL_HSS_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C146;
+   assign VDL_HSS0_clk_ctrl = MAIN_CLK;
+   assign VDL_HSS_d = FB_AD[27:16];
+   assign VDL_HSS8_ena_ctrl = VDL_HSS_CS & (!nFB_WR) & FB_B[0];
+   assign VDL_HSS0_ena_ctrl = VDL_HSS_CS & (!nFB_WR) & FB_B[1];
+
+//  VERTIKAL
+//  VDL_VBE
+//  $82A6/2
+   assign VDL_VBE_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C153;
+   assign VDL_VBE0_clk_ctrl = MAIN_CLK;
+   assign VDL_VBE_d = FB_AD[26:16];
+   assign VDL_VBE8_ena_ctrl = VDL_VBE_CS & (!nFB_WR) & FB_B[2];
+   assign VDL_VBE0_ena_ctrl = VDL_VBE_CS & (!nFB_WR) & FB_B[3];
+
+//  VDL_VDB
+//  $82A8/2
+   assign VDL_VDB_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C154;
+   assign VDL_VDB0_clk_ctrl = MAIN_CLK;
+   assign VDL_VDB_d = FB_AD[26:16];
+   assign VDL_VDB8_ena_ctrl = VDL_VDB_CS & (!nFB_WR) & FB_B[0];
+   assign VDL_VDB0_ena_ctrl = VDL_VDB_CS & (!nFB_WR) & FB_B[1];
+
+//  VDL_VDE
+//  $82AA/2
+   assign VDL_VDE_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C155;
+   assign VDL_VDE0_clk_ctrl = MAIN_CLK;
+   assign VDL_VDE_d = FB_AD[26:16];
+   assign VDL_VDE8_ena_ctrl = VDL_VDE_CS & (!nFB_WR) & FB_B[2];
+   assign VDL_VDE0_ena_ctrl = VDL_VDE_CS & (!nFB_WR) & FB_B[3];
+
+//  VDL_VBB
+//  $82A4/2
+   assign VDL_VBB_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C152;
+   assign VDL_VBB0_clk_ctrl = MAIN_CLK;
+   assign VDL_VBB_d = FB_AD[26:16];
+   assign VDL_VBB8_ena_ctrl = VDL_VBB_CS & (!nFB_WR) & FB_B[0];
+   assign VDL_VBB0_ena_ctrl = VDL_VBB_CS & (!nFB_WR) & FB_B[1];
+
+//  VDL_VSS
+//  $82AC/2
+   assign VDL_VSS_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C156;
+   assign VDL_VSS0_clk_ctrl = MAIN_CLK;
+   assign VDL_VSS_d = FB_AD[26:16];
+   assign VDL_VSS8_ena_ctrl = VDL_VSS_CS & (!nFB_WR) & FB_B[0];
+   assign VDL_VSS0_ena_ctrl = VDL_VSS_CS & (!nFB_WR) & FB_B[1];
+
+//  VDL_VFT
+//  $82A2/2
+   assign VDL_VFT_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C151;
+   assign VDL_VFT0_clk_ctrl = MAIN_CLK;
+   assign VDL_VFT_d = FB_AD[26:16];
+   assign VDL_VFT8_ena_ctrl = VDL_VFT_CS & (!nFB_WR) & FB_B[2];
+   assign VDL_VFT0_ena_ctrl = VDL_VFT_CS & (!nFB_WR) & FB_B[3];
+
+//  VDL_VCT
+//  $82C0/2
+   assign VDL_VCT_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C160;
+   assign VDL_VCT0_clk_ctrl = MAIN_CLK;
+   assign VDL_VCT_d = FB_AD[24:16];
+   assign VDL_VCT8_ena = VDL_VCT_CS & (!nFB_WR) & FB_B[0];
+   assign VDL_VCT0_ena_ctrl = VDL_VCT_CS & (!nFB_WR) & FB_B[1];
+
+//  VDL_VMD
+//  $82C2/2
+   assign VDL_VMD_CS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C161;
+   assign VDL_VMD0_clk_ctrl = MAIN_CLK;
+   assign VDL_VMD_d = FB_AD[19:16];
+   assign VDL_VMD0_ena_ctrl = VDL_VMD_CS & (!nFB_WR) & FB_B[3];
+
+// - REGISTER OUT
+   assign u0_data = ({16{ST_SHIFT_MODE_CS}} & {6'b00_0000, ST_SHIFT_MODE_q,
+	 8'b0000_0000}) | ({16{FALCON_SHIFT_MODE_CS}} & {5'b0_0000,
+	 FALCON_SHIFT_MODE_q}) | ({16{SYS_CTR_CS}} & {9'b1_0000_0000,
+	 SYS_CTR_q[6:4], !BLITTER_RUN, SYS_CTR_q[2:0]}) | ({16{VDL_LOF_CS}} &
+	 VDL_LOF_q) | ({16{VDL_LWD_CS}} & VDL_LWD_q) | ({16{VDL_HBE_CS}} &
+	 {4'b0000, VDL_HBE_q}) | ({16{VDL_HDB_CS}} & {4'b0000, VDL_HDB_q}) |
+	 ({16{VDL_HDE_CS}} & {4'b0000, VDL_HDE_q}) | ({16{VDL_HBB_CS}} &
+	 {4'b0000, VDL_HBB_q}) | ({16{VDL_HSS_CS}} & {4'b0000, VDL_HSS_q}) |
+	 ({16{VDL_HHT_CS}} & {4'b0000, VDL_HHT_q}) | ({16{VDL_VBE_CS}} &
+	 {5'b0_0000, VDL_VBE_q}) | ({16{VDL_VDB_CS}} & {5'b0_0000, VDL_VDB_q})
+	 | ({16{VDL_VDE_CS}} & {5'b0_0000, VDL_VDE_q}) | ({16{VDL_VBB_CS}} &
+	 {5'b0_0000, VDL_VBB_q}) | ({16{VDL_VSS_CS}} & {5'b0_0000, VDL_VSS_q})
+	 | ({16{VDL_VFT_CS}} & {5'b0_0000, VDL_VFT_q}) | ({16{VDL_VCT_CS}} &
+	 {7'b000_0000, VDL_VCT_q}) | ({16{VDL_VMD_CS}} & {12'b0000_0000_0000,
+	 VDL_VMD_q}) | ({16{ACP_VCTR_CS}} & ACP_VCTR_q[31:16]) |
+	 ({16{ATARI_HH_CS}} & ATARI_HH_q[31:16]) | ({16{ATARI_VH_CS}} &
+	 ATARI_VH_q[31:16]) | ({16{ATARI_HL_CS}} & ATARI_HL_q[31:16]) |
+	 ({16{ATARI_VL_CS}} & ATARI_VL_q[31:16]) | ({16{CCR_CS}} &
+	 {8'b0000_0000, CCR_q[23:16]}) | ({16{VIDEO_PLL_CONFIG_CS}} &
+	 {7'b000_0000, VR_DOUT_q}) | ({16{VIDEO_PLL_RECONFIG_CS}} & {VR_BUSY,
+	 4'b0000, VR_WR_q, VR_RD, VIDEO_RECONFIG_q, 8'b1111_1010});
+   assign u0_enabledt = (ST_SHIFT_MODE_CS | FALCON_SHIFT_MODE_CS | ACP_VCTR_CS
+	 | CCR_CS | SYS_CTR_CS | VDL_LOF_CS | VDL_LWD_CS | VDL_HBE_CS |
+	 VDL_HDB_CS | VDL_HDE_CS | VDL_HBB_CS | VDL_HSS_CS | VDL_HHT_CS |
+	 ATARI_HH_CS | ATARI_VH_CS | ATARI_HL_CS | ATARI_VL_CS |
+	 VIDEO_PLL_CONFIG_CS | VIDEO_PLL_RECONFIG_CS | VDL_VBE_CS | VDL_VDB_CS
+	 | VDL_VDE_CS | VDL_VBB_CS | VDL_VSS_CS | VDL_VFT_CS | VDL_VCT_CS |
+	 VDL_VMD_CS) & (!nFB_OE);
+   assign FB_AD[31:16] = u0_tridata;
+   assign u1_data = ({16{ACP_VCTR_CS}} & ACP_VCTR_q[15:0]) | ({16{ATARI_HH_CS}}
+	 & ATARI_HH_q[15:0]) | ({16{ATARI_VH_CS}} & ATARI_VH_q[15:0]) |
+	 ({16{ATARI_HL_CS}} & ATARI_HL_q[15:0]) | ({16{ATARI_VL_CS}} &
+	 ATARI_VL_q[15:0]) | ({16{CCR_CS}} & CCR_q[15:0]);
+   assign u1_enabledt = (ACP_VCTR_CS | CCR_CS | ATARI_HH_CS | ATARI_VH_CS |
+	 ATARI_HL_CS | ATARI_VL_CS) & (!nFB_OE);
+   assign FB_AD[15:0] = u1_tridata;
+   assign VIDEO_MOD_TA = CLUT_TA_q | ST_SHIFT_MODE_CS | FALCON_SHIFT_MODE_CS |
+	 ACP_VCTR_CS | SYS_CTR_CS | VDL_LOF_CS | VDL_LWD_CS | VDL_HBE_CS |
+	 VDL_HDB_CS | VDL_HDE_CS | VDL_HBB_CS | VDL_HSS_CS | VDL_HHT_CS |
+	 ATARI_HH_CS | ATARI_VH_CS | ATARI_HL_CS | ATARI_VL_CS | VDL_VBE_CS |
+	 VDL_VDB_CS | VDL_VDE_CS | VDL_VBB_CS | VDL_VSS_CS | VDL_VFT_CS |
+	 VDL_VCT_CS | VDL_VMD_CS;
+
+//  VIDEO AUSGABE SETZEN
+   assign CLK17M_clk = CLK33M;
+   assign CLK17M_d = !CLK17M_q;
+   assign CLK13M_clk = CLK25M;
+   assign CLK13M_d = !CLK13M_q;
+   assign PIXEL_CLK = (CLK13M_q & (!ACP_VIDEO_ON) & (FALCON_VIDEO | ST_VIDEO) &
+	 ((VDL_VMD_q[2] & VDL_VCT_q[2]) | VDL_VCT_q[0])) | (CLK17M_q &
+	 (!ACP_VIDEO_ON) & (FALCON_VIDEO | ST_VIDEO) & ((VDL_VMD_q[2] &
+	 (!VDL_VCT_q[2])) | VDL_VCT_q[0])) | (CLK25M & (!ACP_VIDEO_ON) &
+	 (FALCON_VIDEO | ST_VIDEO) & (!VDL_VMD_q[2]) & VDL_VCT_q[2] &
+	 (!VDL_VCT_q[0])) | (CLK33M & (!ACP_VIDEO_ON) & (FALCON_VIDEO |
+	 ST_VIDEO) & (!VDL_VMD_q[2]) & (!VDL_VCT_q[2]) & (!VDL_VCT_q[0])) |
+	 (CLK25M & ACP_VIDEO_ON & ACP_VCTR_q[9:8] == 2'b00) | (CLK33M &
+	 ACP_VIDEO_ON & ACP_VCTR_q[9:8] == 2'b01) | (CLK_VIDEO & ACP_VIDEO_ON &
+	 ACP_VCTR_q[9]);
+
+// ------------------------------------------------------------
+//  HORIZONTALE SYNC LÄNGE in PIXEL_CLK
+// --------------------------------------------------------------
+   assign HSY_LEN0_clk_ctrl = MAIN_CLK;
+
+//  hsync puls length in pixeln=frequenz/ = 500ns
+   assign HSY_LEN_d = (8'b0000_1110 & {8{!ACP_VIDEO_ON}} & ({8{FALCON_VIDEO}} |
+	 {8{ST_VIDEO}}) & (({8{VDL_VMD_q[2]}} & {8{VDL_VCT_q[2]}}) |
+	 {8{VDL_VCT_q[0]}})) | (8'b0001_0000 & {8{!ACP_VIDEO_ON}} &
+	 ({8{FALCON_VIDEO}} | {8{ST_VIDEO}}) & (({8{VDL_VMD_q[2]}} &
+	 {8{!VDL_VCT_q[2]}}) | {8{VDL_VCT_q[0]}})) | (8'b0001_1100 &
+	 {8{!ACP_VIDEO_ON}} & ({8{FALCON_VIDEO}} | {8{ST_VIDEO}}) &
+	 {8{!VDL_VMD_q[2]}} & {8{VDL_VCT_q[2]}} & {8{!VDL_VCT_q[0]}}) |
+	 (8'b0010_0000 & {8{!ACP_VIDEO_ON}} & ({8{FALCON_VIDEO}} |
+	 {8{ST_VIDEO}}) & {8{!VDL_VMD_q[2]}} & {8{!VDL_VCT_q[2]}} &
+	 {8{!VDL_VCT_q[0]}}) | (8'b0001_1100 & {8{ACP_VIDEO_ON}} &
+	 {8{ACP_VCTR_q[9:8] == 2'b00}}) | (8'b0010_0000 & {8{ACP_VIDEO_ON}} &
+	 {8{ACP_VCTR_q[9:8] == 2'b01}}) | ((8'b0001_0000 + {1'b0,
+	 VR_FRQ_q[7:1]}) & {8{ACP_VIDEO_ON}} & {8{ACP_VCTR_q[9]}});
+
+//  MULTIPLIKATIONS FAKTOR
+   assign MULF = (6'b00_0010 & {6{!ST_VIDEO}} & {6{VDL_VMD_q[2]}}) |
+	 (6'b00_0100 & {6{!ST_VIDEO}} & {6{!VDL_VMD_q[2]}}) | (6'b01_0000 &
+	 {6{ST_VIDEO}} & {6{VDL_VMD_q[2]}}) | (6'b10_0000 & {6{ST_VIDEO}} &
+	 {6{!VDL_VMD_q[2]}});
+
+//  BREITE IN PIXELN
+   assign HDIS_LEN = (12'b0001_0100_0000 & {12{VDL_VMD_q[2]}}) |
+	 (12'b0010_1000_0000 & {12{!VDL_VMD_q[2]}});
+
+//  DOPPELZEILENMODUS
+   assign DOP_ZEI_clk = MAIN_CLK;
+
+//  ZEILENVERDOPPELUNG EIN AUS
+   assign DOP_ZEI_d = VDL_VMD_q[0] & ST_VIDEO;
+   assign INTER_ZEI_clk = PIXEL_CLK;
+
+//  EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
+//  EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
+   assign INTER_ZEI_d = (DOP_ZEI_q & VVCNT_q[0] != VDIS_START[0] & VVCNT_q !=
+	 11'b000_0000_0000 & VHCNT_q < (HDIS_END - 12'b0000_0000_0001)) |
+	 (DOP_ZEI_q & VVCNT_q[0] == VDIS_START[0] & VVCNT_q !=
+	 11'b000_0000_0000 & VHCNT_q > (HDIS_END - 12'b0000_0000_0010));
+   assign DOP_FIFO_CLR_clk = PIXEL_CLK;
+
+//  DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
+   assign DOP_FIFO_CLR_d = (INTER_ZEI_q & HSYNC_START_q) | SYNC_PIX_q;
+
+//  GE
+   assign RAND_LINKS_FULL = VDL_HBE_q * {7'b000_0000, MULF[5:1]};
+
+//  GE
+   assign HS_START_FULL = ((VDL_HHT_q + 24'h1) + VDL_HSS_q) * {7'b000_0000,
+	 MULF[5:1]};
+
+//  GE
+   assign H_TOTAL_FULL = (VDL_HHT_q + 24'h2) * {6'b00_0000, MULF};
+   assign RAND_LINKS = (VDL_HBE_q & {12{ACP_VIDEO_ON}}) | (12'b0000_0001_0101 &
+	 {12{!ACP_VIDEO_ON}} & {12{ATARI_SYNC}} & {12{VDL_VMD_q[2]}}) |
+	 (12'b0000_0010_1010 & {12{!ACP_VIDEO_ON}} & {12{ATARI_SYNC}} &
+	 {12{!VDL_VMD_q[2]}}) | (RAND_LINKS_FULL[11:0] & {12{!ACP_VIDEO_ON}} &
+	 {12{!ATARI_SYNC}});
+   assign HDIS_START = (VDL_HDB_q & {12{ACP_VIDEO_ON}}) | ((RAND_LINKS +
+	 12'b0000_0000_0001) & {12{!ACP_VIDEO_ON}});
+   assign HDIS_END = (VDL_HDE_q & {12{ACP_VIDEO_ON}}) | ((RAND_LINKS +
+	 HDIS_LEN) & {12{!ACP_VIDEO_ON}});
+   assign RAND_RECHTS = (VDL_HBB_q & {12{ACP_VIDEO_ON}}) | ((HDIS_END +
+	 12'b0000_0000_0001) & {12{!ACP_VIDEO_ON}});
+   assign HS_START = (VDL_HSS_q & {12{ACP_VIDEO_ON}}) | (ATARI_HL_q[11:0] &
+	 {12{!ACP_VIDEO_ON}} & {12{ATARI_SYNC}} & {12{VDL_VMD_q[2]}}) |
+	 (ATARI_HH_q[11:0] & {12{!ACP_VIDEO_ON}} & {12{ATARI_SYNC}} &
+	 {12{!VDL_VMD_q[2]}}) | (HS_START_FULL[11:0] & {12{!ACP_VIDEO_ON}} &
+	 {12{!ATARI_SYNC}});
+   assign H_TOTAL = (VDL_HHT_q & {12{ACP_VIDEO_ON}}) | (ATARI_HL_q[27:16] &
+	 {12{!ACP_VIDEO_ON}} & {12{ATARI_SYNC}} & {12{VDL_VMD_q[2]}}) |
+	 (ATARI_HH_q[27:16] & {12{!ACP_VIDEO_ON}} & {12{ATARI_SYNC}} &
+	 {12{!VDL_VMD_q[2]}}) | (H_TOTAL_FULL[11:0] & {12{!ACP_VIDEO_ON}} &
+	 {12{!ATARI_SYNC}});
+   assign RAND_OBEN = (VDL_VBE_q & {11{ACP_VIDEO_ON}}) | (11'b000_0001_1111 &
+	 {11{!ACP_VIDEO_ON}} & {11{ATARI_SYNC}}) | ({1'b0, VDL_VBE_q[10:1]} &
+	 {11{!ACP_VIDEO_ON}} & {11{!ATARI_SYNC}});
+   assign VDIS_START = (VDL_VDB_q & {11{ACP_VIDEO_ON}}) | (11'b000_0010_0000 &
+	 {11{!ACP_VIDEO_ON}} & {11{ATARI_SYNC}}) | (({1'b0, VDL_VDB_q[10:1]} +
+	 11'b000_0000_0001) & {11{!ACP_VIDEO_ON}} & {11{!ATARI_SYNC}});
+   assign VDIS_END = (VDL_VDE_q & {11{ACP_VIDEO_ON}}) | (11'b001_1010_1111 &
+	 {11{!ACP_VIDEO_ON}} & {11{ATARI_SYNC}} & {11{ST_VIDEO}}) |
+	 (11'b001_1111_1111 & {11{!ACP_VIDEO_ON}} & {11{ATARI_SYNC}} &
+	 {11{!ST_VIDEO}}) | ({1'b0, VDL_VDE_q[10:1]} & {11{!ACP_VIDEO_ON}} &
+	 {11{!ATARI_SYNC}});
+   assign RAND_UNTEN = (VDL_VBB_q & {11{ACP_VIDEO_ON}}) | ((VDIS_END +
+	 11'b000_0000_0001) & {11{!ACP_VIDEO_ON}} & {11{ATARI_SYNC}}) |
+	 (({1'b0, VDL_VBB_q[10:1]} + 11'b000_0000_0001) & {11{!ACP_VIDEO_ON}} &
+	 {11{!ATARI_SYNC}});
+   assign VS_START = (VDL_VSS_q & {11{ACP_VIDEO_ON}}) | (ATARI_VL_q[10:0] &
+	 {11{!ACP_VIDEO_ON}} & {11{ATARI_SYNC}} & {11{VDL_VMD_q[2]}}) |
+	 (ATARI_VH_q[10:0] & {11{!ACP_VIDEO_ON}} & {11{ATARI_SYNC}} &
+	 {11{!VDL_VMD_q[2]}}) | ({1'b0, VDL_VSS_q[10:1]} & {11{!ACP_VIDEO_ON}}
+	 & {11{!ATARI_SYNC}});
+   assign V_TOTAL = (VDL_VFT_q & {11{ACP_VIDEO_ON}}) | (ATARI_VL_q[26:16] &
+	 {11{!ACP_VIDEO_ON}} & {11{ATARI_SYNC}} & {11{VDL_VMD_q[2]}}) |
+	 (ATARI_VH_q[26:16] & {11{!ACP_VIDEO_ON}} & {11{ATARI_SYNC}} &
+	 {11{!VDL_VMD_q[2]}}) | ({1'b0, VDL_VFT_q[10:1]} & {11{!ACP_VIDEO_ON}}
+	 & {11{!ATARI_SYNC}});
+
+//  ZÄHLER
+   assign LAST_clk = PIXEL_CLK;
+   assign LAST_d = VHCNT_q == (H_TOTAL - 12'b0000_0000_0010);
+   assign VHCNT0_clk_ctrl = PIXEL_CLK;
+   assign VHCNT_d = (VHCNT_q + 12'b0000_0000_0001) & {12{!LAST_q}};
+   assign VVCNT0_clk_ctrl = PIXEL_CLK;
+   assign VVCNT0_ena_ctrl = LAST_q;
+   assign VVCNT_d = (VVCNT_q + 11'b000_0000_0001) & {11{VVCNT_q != (V_TOTAL -
+	 11'b000_0000_0001)}};
+
+//  DISPLAY ON OFF
+   assign DPO_ZL_clk = PIXEL_CLK;
+
+//  1 ZEILE DAVOR ON OFF
+   assign DPO_ZL_d = VVCNT_q > (RAND_OBEN - 11'b000_0000_0001) & VVCNT_q <
+	 (RAND_UNTEN - 11'b000_0000_0001);
+
+//  AM ZEILENENDE ÜBERNEHMEN
+   assign DPO_ZL_ena = LAST_q;
+   assign DPO_ON_clk = PIXEL_CLK;
+
+//  BESSER EINZELN WEGEN TIMING
+   assign DPO_ON_d = VHCNT_q == RAND_LINKS;
+   assign DPO_OFF_clk = PIXEL_CLK;
+   assign DPO_OFF_d = VHCNT_q == (RAND_RECHTS - 12'b0000_0000_0001);
+   assign DISP_ON_clk = PIXEL_CLK;
+   assign DISP_ON_d = (DISP_ON_q & (!DPO_OFF_q)) | (DPO_ON_q & DPO_ZL_q);
+
+//  DATENTRANSFER ON OFF
+   assign VDO_ON_clk = PIXEL_CLK;
+
+//  BESSER EINZELN WEGEN TIMING
+   assign VDO_ON_d = VHCNT_q == (HDIS_START - 12'b0000_0000_0001);
+   assign VDO_OFF_clk = PIXEL_CLK;
+   assign VDO_OFF_d = VHCNT_q == HDIS_END;
+   assign VDO_ZL_clk = PIXEL_CLK;
+
+//  AM ZEILENENDE ÜBERNEHMEN
+   assign VDO_ZL_ena = LAST_q;
+
+//  1 ZEILE DAVOR ON OFF
+   assign VDO_ZL_d = VVCNT_q >= (VDIS_START - 11'b000_0000_0001) & VVCNT_q <
+	 VDIS_END;
+   assign VDTRON_clk = PIXEL_CLK;
+   assign VDTRON_d = (VDTRON_q & (!VDO_OFF_q)) | (VDO_ON_q & VDO_ZL_q);
+
+//  VERZÖGERUNG UND SYNC
+   assign HSYNC_START_clk = PIXEL_CLK;
+   assign HSYNC_START_d = VHCNT_q == (HS_START - 12'b0000_0000_0011);
+   assign HSYNC_I0_clk_ctrl = PIXEL_CLK;
+   assign HSYNC_I_d = (HSY_LEN_q & {8{HSYNC_START_q}}) | ((HSYNC_I_q -
+	 8'b0000_0001) & {8{!HSYNC_START_q}} & {8{HSYNC_I_q != 8'b0000_0000}});
+   assign VSYNC_START_clk = PIXEL_CLK;
+   assign VSYNC_START_ena = LAST_q;
+
+//  start am ende der Zeile vor dem vsync
+   assign VSYNC_START_d = VVCNT_q == (VS_START - 11'b000_0000_0011);
+   assign VSYNC_I0_clk_ctrl = PIXEL_CLK;
+
+//  start am ende der Zeile vor dem vsync
+   assign VSYNC_I0_ena_ctrl = LAST_q;
+
+//  3 zeilen vsync length
+//  runterzählen bis 0
+   assign VSYNC_I_d = (3'b011 & {3{VSYNC_START_q}}) | ((VSYNC_I_q - 3'b001) &
+	 {3{!VSYNC_START_q}} & {3{VSYNC_I_q != 3'b000}});
+   assign VERZ2_0_clk_ctrl = PIXEL_CLK;
+   assign VERZ1_0_clk_ctrl = PIXEL_CLK;
+   assign VERZ0_0_clk_ctrl = PIXEL_CLK;
+   assign {VERZ2__d[1], VERZ1__d[1], VERZ0__d[1]} = {VERZ2__q[0], VERZ1__q[0],
+	 VERZ0__q[0]};
+   assign {VERZ2__d[2], VERZ1__d[2], VERZ0__d[2]} = {VERZ2__q[1], VERZ1__q[1],
+	 VERZ0__q[1]};
+   assign {VERZ2__d[3], VERZ1__d[3], VERZ0__d[3]} = {VERZ2__q[2], VERZ1__q[2],
+	 VERZ0__q[2]};
+   assign {VERZ2__d[4], VERZ1__d[4], VERZ0__d[4]} = {VERZ2__q[3], VERZ1__q[3],
+	 VERZ0__q[3]};
+   assign {VERZ2__d[5], VERZ1__d[5], VERZ0__d[5]} = {VERZ2__q[4], VERZ1__q[4],
+	 VERZ0__q[4]};
+   assign {VERZ2__d[6], VERZ1__d[6], VERZ0__d[6]} = {VERZ2__q[5], VERZ1__q[5],
+	 VERZ0__q[5]};
+   assign {VERZ2__d[7], VERZ1__d[7], VERZ0__d[7]} = {VERZ2__q[6], VERZ1__q[6],
+	 VERZ0__q[6]};
+   assign {VERZ2__d[8], VERZ1__d[8], VERZ0__d[8]} = {VERZ2__q[7], VERZ1__q[7],
+	 VERZ0__q[7]};
+   assign {VERZ2__d[9], VERZ1__d[9], VERZ0__d[9]} = {VERZ2__q[8], VERZ1__q[8],
+	 VERZ0__q[8]};
+   assign VERZ0__d[0] = DISP_ON_q;
+   assign VERZ1_0_d_1 = HSYNC_I_q != 8'b0000_0000;
+
+//  NUR MÖGLICH WENN BEIDE
+   assign VERZ1_0_d_2 = (((!ACP_VCTR_q[15]) | (!VDL_VCT_q[6])) & HSYNC_I_q !=
+	 8'b0000_0000) | (ACP_VCTR_q[15] & VDL_VCT_q[6] & HSYNC_I_q ==
+	 8'b0000_0000);
+
+//  NUR MÖGLICH WENN BEIDE
+   assign VERZ2__d[0] = (((!ACP_VCTR_q[15]) | (!VDL_VCT_q[5])) & VSYNC_I_q !=
+	 3'b000) | (ACP_VCTR_q[15] & VDL_VCT_q[5] & VSYNC_I_q == 3'b000);
+   assign nBLANK_clk = PIXEL_CLK;
+   assign nBLANK_d = VERZ0__q[8];
+   assign HSYNC_clk = PIXEL_CLK;
+   assign HSYNC_d = VERZ1__q[9];
+   assign VSYNC_clk = PIXEL_CLK;
+   assign VSYNC_d = VERZ2__q[9];
+   assign nSYNC = gnd;
+
+//  RANDFARBE MACHEN ------------------------------------
+   assign RAND0_clk_ctrl = PIXEL_CLK;
+   assign RAND_d[0] = DISP_ON_q & (!VDTRON_q) & ACP_VCTR_q[25];
+   assign RAND_d[1] = RAND_q[0];
+   assign RAND_d[2] = RAND_q[1];
+   assign RAND_d[3] = RAND_q[2];
+   assign RAND_d[4] = RAND_q[3];
+   assign RAND_d[5] = RAND_q[4];
+   assign RAND_d[6] = RAND_q[5];
+   assign RAND_ON = RAND_q[6];
+
+// --------------------------------------------------------
+   assign CLR_FIFO_clk = PIXEL_CLK;
+   assign CLR_FIFO_ena = LAST_q;
+
+//  IN LETZTER ZEILE LÖSCHEN
+   assign CLR_FIFO_d = VVCNT_q == (V_TOTAL - 11'b000_0000_0010);
+   assign START_ZEILE_clk = PIXEL_CLK;
+   assign START_ZEILE_ena = LAST_q;
+
+//  ZEILE 1
+   assign START_ZEILE_d = VVCNT_q == 11'b000_0000_0000;
+   assign SYNC_PIX_clk = PIXEL_CLK;
+
+//  SUB PIXEL ZÄHLER SYNCHRONISIEREN
+   assign SYNC_PIX_d = VHCNT_q == 12'b0000_0000_0011 & START_ZEILE_q;
+   assign SYNC_PIX1_clk = PIXEL_CLK;
+
+//  SUB PIXEL ZÄHLER SYNCHRONISIEREN
+   assign SYNC_PIX1_d = VHCNT_q == 12'b0000_0000_0101 & START_ZEILE_q;
+   assign SYNC_PIX2_clk = PIXEL_CLK;
+
+//  SUB PIXEL ZÄHLER SYNCHRONISIEREN
+   assign SYNC_PIX2_d = VHCNT_q == 12'b0000_0000_0111 & START_ZEILE_q;
+   assign SUB_PIXEL_CNT0_clk_ctrl = PIXEL_CLK;
+   assign SUB_PIXEL_CNT0_ena_ctrl = VDTRON_q | SYNC_PIX_q;
+
+// count up if display on sonst clear bei sync pix
+   assign SUB_PIXEL_CNT_d = (SUB_PIXEL_CNT_q + 7'b000_0001) & {7{!SYNC_PIX_q}};
+   assign FIFO_RDE_clk = PIXEL_CLK;
+
+//  3 CLOCK ZUSÄTZLICH FÜR FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
+   assign FIFO_RDE_d = (((SUB_PIXEL_CNT_q == 7'b000_0001 & COLOR1) |
+	 (SUB_PIXEL_CNT_q[5:0] == 6'b00_0001 & COLOR2) | (SUB_PIXEL_CNT_q[4:0]
+	 == 5'b0_0001 & COLOR4) | (SUB_PIXEL_CNT_q[3:0] == 4'b0001 & COLOR8) |
+	 (SUB_PIXEL_CNT_q[2:0] == 3'b001 & COLOR16) | (SUB_PIXEL_CNT_q[1:0] ==
+	 2'b01 & COLOR24)) & VDTRON_q) | SYNC_PIX_q | SYNC_PIX1_q |
+	 SYNC_PIX2_q;
+   assign CLUT_MUX_ADR0_clk_ctrl = PIXEL_CLK;
+   assign CLUT_MUX_AV1_0_clk_ctrl = PIXEL_CLK;
+   assign CLUT_MUX_AV0_0_clk_ctrl = PIXEL_CLK;
+   assign CLUT_MUX_AV0__d = SUB_PIXEL_CNT_q[3:0];
+   assign CLUT_MUX_AV1__d = CLUT_MUX_AV0__q;
+   assign CLUT_MUX_ADR_d = CLUT_MUX_AV1__q;
+
+
+// Assignments added to explicitly combine the
+// effects of multiple drivers in the source
+   assign COLOR16 = COLOR16_1 | COLOR16_2;
+   assign VERZ1__d[0] = VERZ1_0_d_1 | VERZ1_0_d_2;
+   assign COLOR4 = COLOR4_1 | COLOR4_2;
+   assign COLOR1 = COLOR1_1 | COLOR1_2 | COLOR1_3;
+   assign COLOR8 = COLOR8_1 | COLOR8_2;
+
+// Define power signal(s)
+   assign gnd = 1'b0;
+endmodule
diff --git a/FPGA_quartus_GE/ahdl2v/interrupt_handler.tdf b/FPGA_quartus_GE/ahdl2v/interrupt_handler.tdf
new file mode 100644
index 0000000..a455469
--- /dev/null
+++ b/FPGA_quartus_GE/ahdl2v/interrupt_handler.tdf
@@ -0,0 +1,478 @@
+TITLE "INTERRUPT HANDLER UND C1287";
+
+-- CREATED BY FREDI ASCHWANDEN
+
+INCLUDE "lpm_bustri_LONG.inc";
+INCLUDE "lpm_bustri_BYT.inc";
+
+
+--  Parameters Statement (optional)
+
+-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+
+
+--  Subdesign Section
+
+SUBDESIGN interrupt_handler
+(
+	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+	MAIN_CLK : INPUT;
+	nFB_WR : INPUT;
+	nFB_CS1 : INPUT;
+	nFB_CS2 : INPUT;
+	FB_SIZE0 : INPUT;
+	FB_SIZE1 : INPUT;
+	FB_ADR[31..0] : INPUT;
+	PIC_INT : INPUT;
+	E0_INT : INPUT;
+	DVI_INT : INPUT;
+	nPCI_INTA : INPUT;
+	nPCI_INTB : INPUT;
+	nPCI_INTC : INPUT;
+	nPCI_INTD : INPUT;
+	nMFP_INT : INPUT;
+	nFB_OE : INPUT;
+	DSP_INT : INPUT;
+	VSYNC : INPUT;
+	HSYNC : INPUT;
+	DMA_DRQ : INPUT;
+	nIRQ[7..2] : OUTPUT;
+	INT_HANDLER_TA : OUTPUT;
+	ACP_CONF[31..0] : OUTPUT;
+	TIN0 : OUTPUT;
+	FB_AD[31..0] : BIDIR;
+	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+)
+
+VARIABLE
+	FB_B[3..0]				:NODE;
+	INT_CTR[31..0]			:DFFE;
+	INT_CTR_CS				:NODE;
+	INT_LATCH[31..0]		:DFF;
+	INT_LATCH_CS			:NODE;
+	INT_CLEAR[31..0]		:DFF;
+	INT_CLEAR_CS			:NODE;
+	INT_IN[31..0]			:NODE;
+	INT_ENA[31..0]			:DFFE;
+	INT_ENA_CS				:NODE;
+	ACP_CONF[31..0]			:DFFE;
+	ACP_CONF_CS				:NODE;
+	PSEUDO_BUS_ERROR		:NODE;
+	UHR_AS					:NODE;
+	UHR_DS					:NODE;
+	RTC_ADR[5..0]			:DFFE;
+	ACHTELSEKUNDEN[2..0]	:DFFE;
+	WERTE[7..0][63..0]		:DFFE;			-- WERTE REGISTER 0-63
+	PIC_INT_SYNC[2..0]		:DFF;
+	INC_SEC					:NODE;
+	INC_MIN					:NODE;
+	INC_STD					:NODE;
+	INC_TAG					:NODE;
+	ANZAHL_TAGE_DES_MONATS[7..0]:NODE;
+	WINTERZEIT				:NODE;
+	SOMMERZEIT				:NODE;
+	INC_MONAT				:NODE;
+	INC_JAHR				:NODE;
+	UPDATE_ON				:NODE;
+	
+BEGIN
+-- BYT SELECT
+	FB_B0 =  FB_SIZE1 & !FB_SIZE0 & !FB_ADR1				-- HWORD
+		# !FB_SIZE1 &  FB_SIZE0 & !FB_ADR1 & !FB_ADR0	-- HHBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+	FB_B1 =  FB_SIZE1 & !FB_SIZE0 & !FB_ADR1				-- HWORD
+		# !FB_SIZE1 &  FB_SIZE0 & !FB_ADR1 &  FB_ADR0	-- HLBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+	FB_B2 =  FB_SIZE1 & !FB_SIZE0 &  FB_ADR1				-- LWORD
+		# !FB_SIZE1 &  FB_SIZE0 &  FB_ADR1 & !FB_ADR0	-- LHBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+	FB_B3 =  FB_SIZE1 & !FB_SIZE0 &  FB_ADR1				-- LWORD
+		# !FB_SIZE1 &  FB_SIZE0 &  FB_ADR1 &  FB_ADR0	-- LLBYT
+		# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0;	-- LONG UND LINE
+
+-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN
+	INT_CTR[].CLK = MAIN_CLK;
+	INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000";						-- $10000/4
+	INT_CTR[] = FB_AD[];
+	INT_CTR[31..24].ENA = INT_CTR_CS & FB_B0 & !nFB_WR;
+	INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR;
+	INT_CTR[15..8].ENA  = INT_CTR_CS & FB_B2 & !nFB_WR;
+	INT_CTR[7..0].ENA   = INT_CTR_CS & FB_B3 & !nFB_WR;
+-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
+	INT_ENA[].CLK = MAIN_CLK;
+	INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001";						-- $10004/4
+	INT_ENA[] = FB_AD[];
+	INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR;
+	INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR;
+	INT_ENA[15..8].ENA  = INT_ENA_CS & FB_B2 & !nFB_WR;
+	INT_ENA[7..0].ENA   = INT_ENA_CS & FB_B3 & !nFB_WR;
+-- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR
+	INT_CLEAR[].CLK = MAIN_CLK;
+	INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002";						-- $10008/4
+	INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR;
+	INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR;
+	INT_CLEAR[15..8]  = FB_AD[15..8]  & INT_CLEAR_CS & FB_B2 & !nFB_WR;
+	INT_CLEAR[7..0]   = FB_AD[7..0]   & INT_CLEAR_CS & FB_B3 & !nFB_WR;
+-- INTERRUPT LATCH REGISTER READ ONLY
+	INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003";						-- $1000C/4
+-- INTERRUPT
+	!nIRQ2 = HSYNC 						& INT_ENA[26];
+	!nIRQ3 = INT_CTR0 					& INT_ENA[27];
+	!nIRQ4 = VSYNC 						& INT_ENA[28];
+	 nIRQ5 = INT_LATCH[]==H"00000000" 	& INT_ENA[29];
+	!nIRQ6 = !nMFP_INT 					& INT_ENA[30];
+	!nIRQ7 = PSEUDO_BUS_ERROR			& INT_ENA[31];
+
+PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8"			-- SCC
+							#  FB_ADR[19..4]==H"F8E0"			-- VME
+							#  FB_ADR[19..4]==H"F920"			-- PADDLE
+							#  FB_ADR[19..4]==H"F921"			-- PADDLE
+							#  FB_ADR[19..4]==H"F922"			-- PADDLE
+							#  FB_ADR[19..4]==H"FFA8"			-- MFP2
+							#  FB_ADR[19..4]==H"FFA9"			-- MFP2
+							#  FB_ADR[19..4]==H"FFAA"			-- MFP2
+							#  FB_ADR[19..4]==H"FFA8"			-- MFP2
+							#  FB_ADR[19..8]==H"F87"			-- TT SCSI
+							#  FB_ADR[19..4]==H"FFC2"			-- ST UHR
+							#  FB_ADR[19..4]==H"FFC3"			-- ST UHR
+							#  FB_ADR[19..4]==H"F890"			-- DMA SOUND
+							#  FB_ADR[19..4]==H"F891"			-- DMA SOUND
+							#  FB_ADR[19..4]==H"F892");			-- DMA SOUND
+-- IF VIDEO ADR CHANGE
+TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR;			-- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
+
+-- INTERRUPT LATCH
+	INT_LATCH[] = H"FFFFFFFF";
+	INT_LATCH0.CLK = PIC_INT & INT_ENA[0];
+	INT_LATCH1.CLK = E0_INT & INT_ENA[1];
+	INT_LATCH2.CLK = DVI_INT & INT_ENA[2];
+	INT_LATCH3.CLK = !nPCI_INTA & INT_ENA[3];
+	INT_LATCH4.CLK = !nPCI_INTB & INT_ENA[4];
+	INT_LATCH5.CLK = !nPCI_INTC & INT_ENA[5];
+	INT_LATCH6.CLK = !nPCI_INTD & INT_ENA[6];
+	INT_LATCH7.CLK = DSP_INT & INT_ENA[7];
+	INT_LATCH8.CLK = VSYNC & INT_ENA[8];
+	INT_LATCH9.CLK = HSYNC & INT_ENA[9];
+	
+-- INTERRUPT CLEAR
+	INT_LATCH[].CLRN = !INT_CLEAR[];
+	
+-- INT_IN
+	INT_IN0 = PIC_INT;
+	INT_IN1 = E0_INT;
+	INT_IN2 = DVI_INT;
+	INT_IN3 = !nPCI_INTA;
+	INT_IN4 = !nPCI_INTB;
+	INT_IN5 = !nPCI_INTC;
+	INT_IN6 = !nPCI_INTD;
+	INT_IN7 = DSP_INT;
+	INT_IN8 = VSYNC;
+	INT_IN9 = HSYNC;
+	INT_IN[25..10] = H"0";
+	INT_IN26 = HSYNC; 
+	INT_IN27 = INT_CTR0; 
+	INT_IN28 = VSYNC; 
+	INT_IN29 = INT_LATCH[]!=H"00000000";
+	INT_IN30 = !nMFP_INT; 
+	INT_IN31 = DMA_DRQ; 
+--***************************************************************************************
+-- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE 
+	ACP_CONF[].CLK = MAIN_CLK;
+	ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000";		-- $4'0000/4
+	ACP_CONF[] = FB_AD[];
+	ACP_CONF[31..24].ENA = ACP_CONF_CS & FB_B0 & !nFB_WR;
+	ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR;
+	ACP_CONF[15..8].ENA  = ACP_CONF_CS & FB_B2 & !nFB_WR;
+	ACP_CONF[7..0].ENA   = ACP_CONF_CS & FB_B3 & !nFB_WR;
+--***************************************************************************************
+	
+--------------------------------------------------------------	
+-- C1287   0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR
+----------------------------------------------------------
+	RTC_ADR[].CLK = MAIN_CLK;
+	RTC_ADR[] = FB_AD[21..16];
+	UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1;	-- FFFF8961 
+	UHR_DS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B1" & FB_B3;	-- FFFF8963
+	RTC_ADR[].ENA = UHR_AS & !nFB_WR;
+	WERTE[][].CLK = MAIN_CLK;
+	WERTE[7..0][0] = FB_AD[23..16] & RTC_ADR[]==0 & UHR_DS & !nFB_WR;
+	WERTE[7..0][1] = FB_AD[23..16];
+	WERTE[7..0][2] = FB_AD[23..16] & RTC_ADR[]==2 & UHR_DS & !nFB_WR;
+	WERTE[7..0][3] = FB_AD[23..16];
+	WERTE[7..0][4] = FB_AD[23..16] & RTC_ADR[]==4 & UHR_DS & !nFB_WR;
+	WERTE[7..0][5] = FB_AD[23..16];
+	WERTE[7..0][6] = FB_AD[23..16] & RTC_ADR[]==6 & UHR_DS & !nFB_WR;
+	WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR;
+	WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR;
+	WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR;
+	WERTE[7..0][10] = FB_AD[23..16];
+	WERTE[7..0][11] = FB_AD[23..16];
+	WERTE[7..0][12] = FB_AD[23..16];
+	WERTE[7..0][13] = FB_AD[23..16];
+	WERTE[7..0][14] = FB_AD[23..16];
+	WERTE[7..0][15] = FB_AD[23..16];
+	WERTE[7..0][16] = FB_AD[23..16];
+	WERTE[7..0][17] = FB_AD[23..16];
+	WERTE[7..0][18] = FB_AD[23..16];
+	WERTE[7..0][19] = FB_AD[23..16];
+	WERTE[7..0][20] = FB_AD[23..16];
+	WERTE[7..0][21] = FB_AD[23..16];
+	WERTE[7..0][22] = FB_AD[23..16];
+	WERTE[7..0][23] = FB_AD[23..16];
+	WERTE[7..0][24] = FB_AD[23..16];
+	WERTE[7..0][25] = FB_AD[23..16];
+	WERTE[7..0][26] = FB_AD[23..16];
+	WERTE[7..0][27] = FB_AD[23..16];
+	WERTE[7..0][28] = FB_AD[23..16];
+	WERTE[7..0][29] = FB_AD[23..16];
+	WERTE[7..0][30] = FB_AD[23..16];
+	WERTE[7..0][31] = FB_AD[23..16];
+	WERTE[7..0][32] = FB_AD[23..16];
+	WERTE[7..0][33] = FB_AD[23..16];
+	WERTE[7..0][34] = FB_AD[23..16];
+	WERTE[7..0][35] = FB_AD[23..16];
+	WERTE[7..0][36] = FB_AD[23..16];
+	WERTE[7..0][37] = FB_AD[23..16];
+	WERTE[7..0][38] = FB_AD[23..16];
+	WERTE[7..0][39] = FB_AD[23..16];
+	WERTE[7..0][40] = FB_AD[23..16];
+	WERTE[7..0][41] = FB_AD[23..16];
+	WERTE[7..0][42] = FB_AD[23..16];
+	WERTE[7..0][43] = FB_AD[23..16];
+	WERTE[7..0][44] = FB_AD[23..16];
+	WERTE[7..0][45] = FB_AD[23..16];
+	WERTE[7..0][46] = FB_AD[23..16];
+	WERTE[7..0][47] = FB_AD[23..16];
+	WERTE[7..0][48] = FB_AD[23..16];
+	WERTE[7..0][49] = FB_AD[23..16];
+	WERTE[7..0][50] = FB_AD[23..16];
+	WERTE[7..0][51] = FB_AD[23..16];
+	WERTE[7..0][52] = FB_AD[23..16];
+	WERTE[7..0][53] = FB_AD[23..16];
+	WERTE[7..0][54] = FB_AD[23..16];
+	WERTE[7..0][55] = FB_AD[23..16];
+	WERTE[7..0][56] = FB_AD[23..16];
+	WERTE[7..0][57] = FB_AD[23..16];
+	WERTE[7..0][58] = FB_AD[23..16];
+	WERTE[7..0][59] = FB_AD[23..16];
+	WERTE[7..0][60] = FB_AD[23..16];
+	WERTE[7..0][61] = FB_AD[23..16];
+	WERTE[7..0][62] = FB_AD[23..16];
+	WERTE[7..0][63] = FB_AD[23..16];
+	WERTE[][0].ENA = RTC_ADR[]==0 & UHR_DS & !nFB_WR;
+	WERTE[][1].ENA = RTC_ADR[]==1 & UHR_DS & !nFB_WR;
+	WERTE[][2].ENA = RTC_ADR[]==2 & UHR_DS & !nFB_WR;
+	WERTE[][3].ENA = RTC_ADR[]==3 & UHR_DS & !nFB_WR;
+	WERTE[][4].ENA = RTC_ADR[]==4 & UHR_DS & !nFB_WR;
+	WERTE[][5].ENA = RTC_ADR[]==5 & UHR_DS & !nFB_WR;
+	WERTE[][6].ENA = RTC_ADR[]==6 & UHR_DS & !nFB_WR;
+	WERTE[][7].ENA = RTC_ADR[]==7 & UHR_DS & !nFB_WR;
+	WERTE[][8].ENA = RTC_ADR[]==8 & UHR_DS & !nFB_WR;
+	WERTE[][9].ENA = RTC_ADR[]==9 & UHR_DS & !nFB_WR;
+	WERTE[][10].ENA = RTC_ADR[]==10 & UHR_DS & !nFB_WR;
+	WERTE[][11].ENA = RTC_ADR[]==11 & UHR_DS & !nFB_WR;
+	WERTE[][12].ENA = RTC_ADR[]==12 & UHR_DS & !nFB_WR;
+	WERTE[][13].ENA = RTC_ADR[]==13 & UHR_DS & !nFB_WR;
+	WERTE[][14].ENA = RTC_ADR[]==14 & UHR_DS & !nFB_WR;
+	WERTE[][15].ENA = RTC_ADR[]==15 & UHR_DS & !nFB_WR;
+	WERTE[][16].ENA = RTC_ADR[]==16 & UHR_DS & !nFB_WR;
+	WERTE[][17].ENA = RTC_ADR[]==17 & UHR_DS & !nFB_WR;
+	WERTE[][18].ENA = RTC_ADR[]==18 & UHR_DS & !nFB_WR;
+	WERTE[][19].ENA = RTC_ADR[]==19 & UHR_DS & !nFB_WR;
+	WERTE[][20].ENA = RTC_ADR[]==20 & UHR_DS & !nFB_WR;
+	WERTE[][21].ENA = RTC_ADR[]==21 & UHR_DS & !nFB_WR;
+	WERTE[][22].ENA = RTC_ADR[]==22 & UHR_DS & !nFB_WR;
+	WERTE[][23].ENA = RTC_ADR[]==23 & UHR_DS & !nFB_WR;
+	WERTE[][24].ENA = RTC_ADR[]==24 & UHR_DS & !nFB_WR;
+	WERTE[][25].ENA = RTC_ADR[]==25 & UHR_DS & !nFB_WR;
+	WERTE[][26].ENA = RTC_ADR[]==26 & UHR_DS & !nFB_WR;
+	WERTE[][27].ENA = RTC_ADR[]==27 & UHR_DS & !nFB_WR;
+	WERTE[][28].ENA = RTC_ADR[]==28 & UHR_DS & !nFB_WR;
+	WERTE[][29].ENA = RTC_ADR[]==29 & UHR_DS & !nFB_WR;
+	WERTE[][30].ENA = RTC_ADR[]==30 & UHR_DS & !nFB_WR;
+	WERTE[][31].ENA = RTC_ADR[]==31 & UHR_DS & !nFB_WR;
+	WERTE[][32].ENA = RTC_ADR[]==32 & UHR_DS & !nFB_WR;
+	WERTE[][33].ENA = RTC_ADR[]==33 & UHR_DS & !nFB_WR;
+	WERTE[][34].ENA = RTC_ADR[]==34 & UHR_DS & !nFB_WR;
+	WERTE[][35].ENA = RTC_ADR[]==35 & UHR_DS & !nFB_WR;
+	WERTE[][36].ENA = RTC_ADR[]==36 & UHR_DS & !nFB_WR;
+	WERTE[][37].ENA = RTC_ADR[]==37 & UHR_DS & !nFB_WR;
+	WERTE[][38].ENA = RTC_ADR[]==38 & UHR_DS & !nFB_WR;
+	WERTE[][39].ENA = RTC_ADR[]==39 & UHR_DS & !nFB_WR;
+	WERTE[][40].ENA = RTC_ADR[]==40 & UHR_DS & !nFB_WR;
+	WERTE[][41].ENA = RTC_ADR[]==41 & UHR_DS & !nFB_WR;
+	WERTE[][42].ENA = RTC_ADR[]==42 & UHR_DS & !nFB_WR;
+	WERTE[][43].ENA = RTC_ADR[]==43 & UHR_DS & !nFB_WR;
+	WERTE[][44].ENA = RTC_ADR[]==44 & UHR_DS & !nFB_WR;
+	WERTE[][45].ENA = RTC_ADR[]==45 & UHR_DS & !nFB_WR;
+	WERTE[][46].ENA = RTC_ADR[]==46 & UHR_DS & !nFB_WR;
+	WERTE[][47].ENA = RTC_ADR[]==47 & UHR_DS & !nFB_WR;
+	WERTE[][48].ENA = RTC_ADR[]==48 & UHR_DS & !nFB_WR;
+	WERTE[][49].ENA = RTC_ADR[]==49 & UHR_DS & !nFB_WR;
+	WERTE[][50].ENA = RTC_ADR[]==50 & UHR_DS & !nFB_WR;
+	WERTE[][51].ENA = RTC_ADR[]==51 & UHR_DS & !nFB_WR;
+	WERTE[][52].ENA = RTC_ADR[]==52 & UHR_DS & !nFB_WR;
+	WERTE[][53].ENA = RTC_ADR[]==53 & UHR_DS & !nFB_WR;
+	WERTE[][54].ENA = RTC_ADR[]==54 & UHR_DS & !nFB_WR;
+	WERTE[][55].ENA = RTC_ADR[]==55 & UHR_DS & !nFB_WR;
+	WERTE[][56].ENA = RTC_ADR[]==56 & UHR_DS & !nFB_WR;
+	WERTE[][57].ENA = RTC_ADR[]==57 & UHR_DS & !nFB_WR;
+	WERTE[][58].ENA = RTC_ADR[]==58 & UHR_DS & !nFB_WR;
+	WERTE[][59].ENA = RTC_ADR[]==59 & UHR_DS & !nFB_WR;
+	WERTE[][60].ENA = RTC_ADR[]==60 & UHR_DS & !nFB_WR;
+	WERTE[][61].ENA = RTC_ADR[]==61 & UHR_DS & !nFB_WR;
+	WERTE[][62].ENA = RTC_ADR[]==62 & UHR_DS & !nFB_WR;
+	WERTE[][63].ENA = RTC_ADR[]==63 & UHR_DS & !nFB_WR;
+	PIC_INT_SYNC[].CLK = MAIN_CLK;	PIC_INT_SYNC[0] = PIC_INT;
+	PIC_INT_SYNC[1] = PIC_INT_SYNC[0];
+	PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0];
+	UPDATE_ON = !WERTE[7][11];		
+	WERTE[6][10].CLRN = GND;	-- KEIN UIP
+	UPDATE_ON = !WERTE[7][11];	-- UPDATE ON OFF
+	WERTE[2][11] = VCC;	-- IMMER BINARY
+	WERTE[1][11] = VCC;	-- IMMER 24H FORMAT
+	WERTE[0][11] = VCC;	-- IMMER SOMMERZEITKORREKTUR
+	WERTE[7][13] = VCC;	-- IMMER RICHTIG
+-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG)
+	SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4  & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL
+	WERTE[0][13] = SOMMERZEIT;
+	WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT);
+	WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13];  --LETZTER SONNTAG IM OKTOBER
+-- ACHTELSEKUNDEN
+	ACHTELSEKUNDEN[].CLK = MAIN_CLK;
+	ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1;
+	ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON;
+-- SEKUNDEN
+	INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON;   
+	WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);			-- SEKUNDEN ZÄHLEN BIS 59
+	WERTE[][0].ENA  = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);	
+-- MINUTEN
+	INC_MIN = INC_SEC & WERTE[][0]==59;							--  
+	WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);			-- MINUTEN ZÄHLEN BIS 59
+	WERTE[][2].ENA  = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR);								--  
+-- STUNDEN
+	INC_STD = INC_MIN & WERTE[][2]==59;							  
+	WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);  -- STUNDEN ZÄHLEN BIS 23
+	WERTE[][4].ENA  = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR);		-- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT	 
+-- WOCHENTAG UND TAG 
+	INC_TAG = INC_STD & WERTE[][2]==23;						
+	WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR)				-- WOCHENTAG ZÄHLEN BIS 7
+			   # 1              & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);			-- DANN BEI 1 WEITER
+	WERTE[][6].ENA  = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);
+	ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12)
+							 # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11)  
+							 # 29 &  WERTE[][8]==2 & WERTE[1..0][9]==0  
+							 # 28 &  WERTE[][8]==2 & WERTE[1..0][9]!=0;  
+	WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR)  	-- TAG ZÄHLEN BIS MONATSENDE
+			   # 1              & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR);		-- DANN BEI 1 WEITER
+	WERTE[][7].ENA  = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR);								--  
+-- MONATE
+	INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[];							--  
+	WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR)					-- MONATE ZÄHLEN BIS 12
+			   # 1              & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);					-- DANN BEI 1 WEITER
+	WERTE[][8].ENA  = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);
+-- JAHR		   
+	INC_JAHR = INC_MONAT & WERTE[][8]==12;							--  
+	WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);					-- JAHRE ZÄHLEN BIS 99
+	WERTE[][9].ENA  = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);
+-- TRISTATE OUTPUT
+
+	FB_AD[31..24] = lpm_bustri_BYT(
+					INT_CTR_CS   & INT_CTR[31..24] 
+				  #	INT_ENA_CS   & INT_ENA[31..24]
+				  #	INT_LATCH_CS & INT_LATCH[31..24]
+				  # INT_CLEAR_CS & INT_IN[31..24]
+				  # ACP_CONF_CS  & ACP_CONF[31..24]
+				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+	FB_AD[23..16] = lpm_bustri_BYT(
+				   WERTE[][0] & RTC_ADR[]==0 & UHR_DS 
+				 # WERTE[][1] & RTC_ADR[]==1 & UHR_DS
+				 # WERTE[][2] & RTC_ADR[]==2 & UHR_DS
+				 # WERTE[][3] & RTC_ADR[]==3 & UHR_DS
+				 # WERTE[][4] & RTC_ADR[]==4 & UHR_DS
+				 # WERTE[][5] & RTC_ADR[]==5 & UHR_DS
+				 # WERTE[][6] & RTC_ADR[]==6 & UHR_DS
+				 # WERTE[][7] & RTC_ADR[]==7 & UHR_DS
+				 # WERTE[][8] & RTC_ADR[]==8 & UHR_DS
+				 # WERTE[][9] & RTC_ADR[]==9 & UHR_DS
+				 # WERTE[][10] & RTC_ADR[]==10 & UHR_DS
+				 # WERTE[][11] & RTC_ADR[]==11 & UHR_DS
+				 # WERTE[][12] & RTC_ADR[]==12 & UHR_DS
+				 # WERTE[][13] & RTC_ADR[]==13 & UHR_DS
+				 # WERTE[][14] & RTC_ADR[]==14 & UHR_DS
+				 # WERTE[][15] & RTC_ADR[]==15 & UHR_DS
+				 # WERTE[][16] & RTC_ADR[]==16 & UHR_DS
+				 # WERTE[][17] & RTC_ADR[]==17 & UHR_DS
+				 # WERTE[][18] & RTC_ADR[]==18 & UHR_DS
+				 # WERTE[][19] & RTC_ADR[]==19 & UHR_DS
+				 # WERTE[][20] & RTC_ADR[]==20 & UHR_DS
+				 # WERTE[][21] & RTC_ADR[]==21 & UHR_DS
+				 # WERTE[][22] & RTC_ADR[]==22 & UHR_DS
+				 # WERTE[][23] & RTC_ADR[]==23 & UHR_DS
+				 # WERTE[][24] & RTC_ADR[]==24 & UHR_DS
+				 # WERTE[][25] & RTC_ADR[]==25 & UHR_DS
+				 # WERTE[][26] & RTC_ADR[]==26 & UHR_DS
+				 # WERTE[][27] & RTC_ADR[]==27 & UHR_DS
+				 # WERTE[][28] & RTC_ADR[]==28 & UHR_DS
+				 # WERTE[][29] & RTC_ADR[]==29 & UHR_DS
+				 # WERTE[][30] & RTC_ADR[]==30 & UHR_DS
+				 # WERTE[][31] & RTC_ADR[]==31 & UHR_DS
+				 # WERTE[][32] & RTC_ADR[]==32 & UHR_DS
+				 # WERTE[][33] & RTC_ADR[]==33 & UHR_DS
+				 # WERTE[][34] & RTC_ADR[]==34 & UHR_DS
+				 # WERTE[][35] & RTC_ADR[]==35 & UHR_DS
+				 # WERTE[][36] & RTC_ADR[]==36 & UHR_DS
+				 # WERTE[][37] & RTC_ADR[]==37 & UHR_DS
+				 # WERTE[][38] & RTC_ADR[]==38 & UHR_DS
+				 # WERTE[][39] & RTC_ADR[]==39 & UHR_DS
+				 # WERTE[][40] & RTC_ADR[]==40 & UHR_DS
+				 # WERTE[][41] & RTC_ADR[]==41 & UHR_DS
+				 # WERTE[][42] & RTC_ADR[]==42 & UHR_DS
+				 # WERTE[][43] & RTC_ADR[]==43 & UHR_DS
+				 # WERTE[][44] & RTC_ADR[]==44 & UHR_DS
+				 # WERTE[][45] & RTC_ADR[]==45 & UHR_DS
+				 # WERTE[][46] & RTC_ADR[]==46 & UHR_DS
+				 # WERTE[][47] & RTC_ADR[]==47 & UHR_DS
+				 # WERTE[][48] & RTC_ADR[]==48 & UHR_DS
+				 # WERTE[][49] & RTC_ADR[]==49 & UHR_DS
+				 # WERTE[][50] & RTC_ADR[]==50 & UHR_DS
+				 # WERTE[][51] & RTC_ADR[]==51 & UHR_DS
+				 # WERTE[][52] & RTC_ADR[]==52 & UHR_DS
+				 # WERTE[][53] & RTC_ADR[]==53 & UHR_DS
+				 # WERTE[][54] & RTC_ADR[]==54 & UHR_DS
+				 # WERTE[][55] & RTC_ADR[]==55 & UHR_DS
+				 # WERTE[][56] & RTC_ADR[]==56 & UHR_DS
+				 # WERTE[][57] & RTC_ADR[]==57 & UHR_DS
+				 # WERTE[][58] & RTC_ADR[]==58 & UHR_DS
+				 # WERTE[][59] & RTC_ADR[]==59 & UHR_DS
+				 # WERTE[][60] & RTC_ADR[]==60 & UHR_DS
+				 # WERTE[][61] & RTC_ADR[]==61 & UHR_DS
+				 # WERTE[][62] & RTC_ADR[]==62 & UHR_DS
+				 # WERTE[][63] & RTC_ADR[]==63 & UHR_DS
+				 # (0,RTC_ADR[])			   & UHR_AS
+				 # INT_CTR_CS   & INT_CTR[23..16] 
+				 # INT_ENA_CS   & INT_ENA[23..16]
+				 # INT_LATCH_CS & INT_LATCH[23..16]
+				 # INT_CLEAR_CS & INT_IN[23..16]
+				 # ACP_CONF_CS  & ACP_CONF[23..16]
+				  ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+	FB_AD[15..8] = lpm_bustri_BYT(
+					INT_CTR_CS   & INT_CTR[15..8] 
+				  #	INT_ENA_CS   & INT_ENA[15..8]
+				  #	INT_LATCH_CS & INT_LATCH[15..8]
+				  # INT_CLEAR_CS & INT_IN[15..8]
+				  # ACP_CONF_CS  & ACP_CONF[15..8]
+				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+	FB_AD[7..0] = lpm_bustri_BYT(
+					INT_CTR_CS   & INT_CTR[7..0] 
+				  #	INT_ENA_CS   & INT_ENA[7..0]
+				  #	INT_LATCH_CS & INT_LATCH[7..0]
+				  # INT_CLEAR_CS & INT_IN[7..0]
+				  # ACP_CONF_CS  & ACP_CONF[7..0]
+				  ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE);
+
+	INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS;
+END;
+
+
diff --git a/FPGA_quartus_GE/ahdl2v/interrupt_handler.v b/FPGA_quartus_GE/ahdl2v/interrupt_handler.v
new file mode 100644
index 0000000..b8562a5
--- /dev/null
+++ b/FPGA_quartus_GE/ahdl2v/interrupt_handler.v
@@ -0,0 +1,3578 @@
+// Xilinx XPort Language Converter, Version 4.1 (110)
+// 
+// AHDL    Design Source: interrupt_handler.tdf
+// Verilog Design Output: interrupt_handler.v
+// Created 23-Feb-2014 10:34 AM
+//
+// Copyright (c) 2014, Xilinx, Inc.  All Rights Reserved.
+// Xilinx Inc makes no warranty, expressed or implied, with respect to
+// the operation and/or functionality of the converted output files.
+// 
+
+// INTERRUPT HANDLER UND C1287
+
+
+//  CREATED BY FREDI ASCHWANDEN
+//   Parameters Statement (optional)
+//  {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
+//  {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
+//   Subdesign Section
+module interrupt_handler(MAIN_CLK, nFB_WR, nFB_CS1, nFB_CS2, FB_SIZE0,
+      FB_SIZE1, FB_ADR, PIC_INT, E0_INT, DVI_INT, nPCI_INTA, nPCI_INTB,
+      nPCI_INTC, nPCI_INTD, nMFP_INT, nFB_OE, DSP_INT, VSYNC, HSYNC, DMA_DRQ,
+      nIRQ, INT_HANDLER_TA, ACP_CONF, TIN0, FB_AD);
+
+//  {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
+//  {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
+   input MAIN_CLK, nFB_WR, nFB_CS1, nFB_CS2, FB_SIZE0, FB_SIZE1;
+   input [31:0] FB_ADR;
+   input PIC_INT, E0_INT, DVI_INT, nPCI_INTA, nPCI_INTB, nPCI_INTC, nPCI_INTD,
+	 nMFP_INT, nFB_OE, DSP_INT, VSYNC, HSYNC, DMA_DRQ;
+   output [7:2] nIRQ;
+   output INT_HANDLER_TA;
+   output [31:0] ACP_CONF;
+   output TIN0;
+   inout [31:0] FB_AD;
+
+//  WERTE REGISTER 0-63
+   wire [3:0] FB_B;
+   wire [31:0] INT_CTR;
+   wire [31:0] INT_CTR_d;
+   wire INT_CTR_CS;
+   wire [31:0] INT_LATCH;
+   wire [31:0] INT_LATCH_d;
+   wire [31:0] INT_LATCH_clk;
+   wire INT_LATCH31_clrn, INT_LATCH30_clrn, INT_LATCH29_clrn, INT_LATCH28_clrn,
+	 INT_LATCH27_clrn, INT_LATCH26_clrn, INT_LATCH25_clrn,
+	 INT_LATCH24_clrn, INT_LATCH23_clrn, INT_LATCH22_clrn,
+	 INT_LATCH21_clrn, INT_LATCH20_clrn, INT_LATCH19_clrn,
+	 INT_LATCH18_clrn, INT_LATCH17_clrn, INT_LATCH16_clrn,
+	 INT_LATCH15_clrn, INT_LATCH14_clrn, INT_LATCH13_clrn,
+	 INT_LATCH12_clrn, INT_LATCH11_clrn, INT_LATCH10_clrn, INT_LATCH9_clrn,
+	 INT_LATCH8_clrn, INT_LATCH7_clrn, INT_LATCH6_clrn, INT_LATCH5_clrn,
+	 INT_LATCH4_clrn, INT_LATCH3_clrn, INT_LATCH2_clrn, INT_LATCH1_clrn,
+	 INT_LATCH0_clrn, INT_LATCH_CS;
+   wire [31:0] INT_CLEAR;
+   wire [31:0] INT_CLEAR_d;
+   wire INT_CLEAR_CS;
+   wire [31:0] INT_IN;
+   wire [31:0] INT_ENA;
+   wire [31:0] INT_ENA_d;
+   wire INT_ENA_CS;
+   wire [31:0] ACP_CONF_d;
+   wire ACP_CONF_CS, PSEUDO_BUS_ERROR, UHR_AS, UHR_DS;
+   wire [5:0] RTC_ADR;
+   wire [5:0] RTC_ADR_d;
+   wire [2:0] ACHTELSEKUNDEN;
+   wire [2:0] ACHTELSEKUNDEN_d;
+   wire [63:0] WERTE7_;
+   wire [63:0] WERTE7__d;
+   wire WERTE7_13_ena, WERTE7_9_ena, WERTE7_8_ena, WERTE7_7_ena, WERTE7_6_ena,
+	 WERTE7_4_ena, WERTE7_2_ena, WERTE7_0_ena;
+   wire [63:0] WERTE6_;
+   wire [63:0] WERTE6__d;
+   wire WERTE6_10_clrn, WERTE6_13_ena, WERTE6_9_ena, WERTE6_8_ena,
+	 WERTE6_7_ena, WERTE6_6_ena, WERTE6_4_ena, WERTE6_2_ena, WERTE6_0_ena;
+   wire [63:0] WERTE5_;
+   wire [63:0] WERTE5__d;
+   wire WERTE5_13_ena, WERTE5_9_ena, WERTE5_8_ena, WERTE5_7_ena, WERTE5_6_ena,
+	 WERTE5_4_ena, WERTE5_2_ena, WERTE5_0_ena;
+   wire [63:0] WERTE4_;
+   wire [63:0] WERTE4__d;
+   wire WERTE4_13_ena, WERTE4_9_ena, WERTE4_8_ena, WERTE4_7_ena, WERTE4_6_ena,
+	 WERTE4_4_ena, WERTE4_2_ena, WERTE4_0_ena;
+   wire [63:0] WERTE3_;
+   wire [63:0] WERTE3__d;
+   wire WERTE3_13_ena, WERTE3_9_ena, WERTE3_8_ena, WERTE3_7_ena, WERTE3_6_ena,
+	 WERTE3_4_ena, WERTE3_2_ena, WERTE3_0_ena;
+   wire [63:0] WERTE2_;
+   wire [63:0] WERTE2__d;
+   wire WERTE2_13_ena, WERTE2_9_ena, WERTE2_8_ena, WERTE2_7_ena, WERTE2_6_ena,
+	 WERTE2_4_ena, WERTE2_2_ena, WERTE2_0_ena;
+   wire [63:0] WERTE1_;
+   wire [63:0] WERTE1__d;
+   wire WERTE1_13_ena, WERTE1_9_ena, WERTE1_8_ena, WERTE1_7_ena, WERTE1_6_ena,
+	 WERTE1_4_ena, WERTE1_2_ena, WERTE1_0_ena;
+   wire [63:0] WERTE0_;
+   wire [63:0] WERTE0__d;
+   wire WERTE0_13_ena, WERTE0_9_ena, WERTE0_8_ena, WERTE0_7_ena, WERTE0_6_ena,
+	 WERTE0_4_ena, WERTE0_2_ena, WERTE0_0_ena;
+   wire [2:0] PIC_INT_SYNC;
+   wire [2:0] PIC_INT_SYNC_d;
+   wire INC_SEC, INC_MIN, INC_STD, INC_TAG;
+   wire [7:0] ANZAHL_TAGE_DES_MONATS;
+   wire WINTERZEIT, SOMMERZEIT, INC_MONAT, INC_JAHR, UPDATE_ON, gnd, vcc;
+   wire [7:0] u0_data;
+   wire u0_enabledt;
+   wire [7:0] u0_tridata;
+   wire [7:0] u1_data;
+   wire u1_enabledt;
+   wire [7:0] u1_tridata;
+   wire [7:0] u2_data;
+   wire u2_enabledt;
+   wire [7:0] u2_tridata;
+   wire [7:0] u3_data;
+   wire u3_enabledt;
+   wire [7:0] u3_tridata;
+   wire UPDATE_ON_1, UPDATE_ON_2, WERTE0_0_ena_1, WERTE0_0_ena_2,
+	 WERTE0_2_ena_1, WERTE0_2_ena_2, WERTE0_4_ena_1, WERTE0_4_ena_2,
+	 WERTE0_6_ena_1, WERTE0_6_ena_2, WERTE0_7_ena_1, WERTE0_7_ena_2,
+	 WERTE0_8_ena_1, WERTE0_8_ena_2, WERTE0_9_ena_1, WERTE0_9_ena_2,
+	 WERTE0_13_ena_1, WERTE0_13_ena_2, WERTE0_0_d_1, WERTE0_0_d_2,
+	 WERTE0_2_d_1, WERTE0_2_d_2, WERTE0_4_d_1, WERTE0_4_d_2, WERTE0_6_d_1,
+	 WERTE0_6_d_2, WERTE0_7_d_1, WERTE0_7_d_2, WERTE0_8_d_1, WERTE0_8_d_2,
+	 WERTE0_9_d_1, WERTE0_9_d_2, WERTE0_11_d_1, WERTE0_11_d_2,
+	 WERTE0_13_d_1, WERTE0_13_d_2, WERTE1_0_ena_1, WERTE1_0_ena_2,
+	 WERTE1_2_ena_1, WERTE1_2_ena_2, WERTE1_4_ena_1, WERTE1_4_ena_2,
+	 WERTE1_6_ena_1, WERTE1_6_ena_2, WERTE1_7_ena_1, WERTE1_7_ena_2,
+	 WERTE1_8_ena_1, WERTE1_8_ena_2, WERTE1_9_ena_1, WERTE1_9_ena_2,
+	 WERTE1_0_d_1, WERTE1_0_d_2, WERTE1_2_d_1, WERTE1_2_d_2, WERTE1_4_d_1,
+	 WERTE1_4_d_2, WERTE1_6_d_1, WERTE1_6_d_2, WERTE1_7_d_1, WERTE1_7_d_2,
+	 WERTE1_8_d_1, WERTE1_8_d_2, WERTE1_9_d_1, WERTE1_9_d_2, WERTE1_11_d_1,
+	 WERTE1_11_d_2, WERTE2_0_ena_1, WERTE2_0_ena_2, WERTE2_2_ena_1,
+	 WERTE2_2_ena_2, WERTE2_4_ena_1, WERTE2_4_ena_2, WERTE2_6_ena_1,
+	 WERTE2_6_ena_2, WERTE2_7_ena_1, WERTE2_7_ena_2, WERTE2_8_ena_1,
+	 WERTE2_8_ena_2, WERTE2_9_ena_1, WERTE2_9_ena_2, WERTE2_0_d_1,
+	 WERTE2_0_d_2, WERTE2_2_d_1, WERTE2_2_d_2, WERTE2_4_d_1, WERTE2_4_d_2,
+	 WERTE2_6_d_1, WERTE2_6_d_2, WERTE2_7_d_1, WERTE2_7_d_2, WERTE2_8_d_1,
+	 WERTE2_8_d_2, WERTE2_9_d_1, WERTE2_9_d_2, WERTE2_11_d_1,
+	 WERTE2_11_d_2, WERTE3_0_ena_1, WERTE3_0_ena_2, WERTE3_2_ena_1,
+	 WERTE3_2_ena_2, WERTE3_4_ena_1, WERTE3_4_ena_2, WERTE3_6_ena_1,
+	 WERTE3_6_ena_2, WERTE3_7_ena_1, WERTE3_7_ena_2, WERTE3_8_ena_1,
+	 WERTE3_8_ena_2, WERTE3_9_ena_1, WERTE3_9_ena_2, WERTE3_0_d_1,
+	 WERTE3_0_d_2, WERTE3_2_d_1, WERTE3_2_d_2, WERTE3_4_d_1, WERTE3_4_d_2,
+	 WERTE3_6_d_1, WERTE3_6_d_2, WERTE3_7_d_1, WERTE3_7_d_2, WERTE3_8_d_1,
+	 WERTE3_8_d_2, WERTE3_9_d_1, WERTE3_9_d_2, WERTE4_0_ena_1,
+	 WERTE4_0_ena_2, WERTE4_2_ena_1, WERTE4_2_ena_2, WERTE4_4_ena_1,
+	 WERTE4_4_ena_2, WERTE4_6_ena_1, WERTE4_6_ena_2, WERTE4_7_ena_1,
+	 WERTE4_7_ena_2, WERTE4_8_ena_1, WERTE4_8_ena_2, WERTE4_9_ena_1,
+	 WERTE4_9_ena_2, WERTE4_0_d_1, WERTE4_0_d_2, WERTE4_2_d_1,
+	 WERTE4_2_d_2, WERTE4_4_d_1, WERTE4_4_d_2, WERTE4_6_d_1, WERTE4_6_d_2,
+	 WERTE4_7_d_1, WERTE4_7_d_2, WERTE4_8_d_1, WERTE4_8_d_2, WERTE4_9_d_1,
+	 WERTE4_9_d_2, WERTE5_0_ena_1, WERTE5_0_ena_2, WERTE5_2_ena_1,
+	 WERTE5_2_ena_2, WERTE5_4_ena_1, WERTE5_4_ena_2, WERTE5_6_ena_1,
+	 WERTE5_6_ena_2, WERTE5_7_ena_1, WERTE5_7_ena_2, WERTE5_8_ena_1,
+	 WERTE5_8_ena_2, WERTE5_9_ena_1, WERTE5_9_ena_2, WERTE5_0_d_1,
+	 WERTE5_0_d_2, WERTE5_2_d_1, WERTE5_2_d_2, WERTE5_4_d_1, WERTE5_4_d_2,
+	 WERTE5_6_d_1, WERTE5_6_d_2, WERTE5_7_d_1, WERTE5_7_d_2, WERTE5_8_d_1,
+	 WERTE5_8_d_2, WERTE5_9_d_1, WERTE5_9_d_2, WERTE6_0_ena_1,
+	 WERTE6_0_ena_2, WERTE6_2_ena_1, WERTE6_2_ena_2, WERTE6_4_ena_1,
+	 WERTE6_4_ena_2, WERTE6_6_ena_1, WERTE6_6_ena_2, WERTE6_7_ena_1,
+	 WERTE6_7_ena_2, WERTE6_8_ena_1, WERTE6_8_ena_2, WERTE6_9_ena_1,
+	 WERTE6_9_ena_2, WERTE6_0_d_1, WERTE6_0_d_2, WERTE6_2_d_1,
+	 WERTE6_2_d_2, WERTE6_4_d_1, WERTE6_4_d_2, WERTE6_6_d_1, WERTE6_6_d_2,
+	 WERTE6_7_d_1, WERTE6_7_d_2, WERTE6_8_d_1, WERTE6_8_d_2, WERTE6_9_d_1,
+	 WERTE6_9_d_2, WERTE7_0_ena_1, WERTE7_0_ena_2, WERTE7_2_ena_1,
+	 WERTE7_2_ena_2, WERTE7_4_ena_1, WERTE7_4_ena_2, WERTE7_6_ena_1,
+	 WERTE7_6_ena_2, WERTE7_7_ena_1, WERTE7_7_ena_2, WERTE7_8_ena_1,
+	 WERTE7_8_ena_2, WERTE7_9_ena_1, WERTE7_9_ena_2, WERTE7_0_d_1,
+	 WERTE7_0_d_2, WERTE7_2_d_1, WERTE7_2_d_2, WERTE7_4_d_1, WERTE7_4_d_2,
+	 WERTE7_6_d_1, WERTE7_6_d_2, WERTE7_7_d_1, WERTE7_7_d_2, WERTE7_8_d_1,
+	 WERTE7_8_d_2, WERTE7_9_d_1, WERTE7_9_d_2, WERTE7_13_d_1,
+	 WERTE7_13_d_2, ACHTELSEKUNDEN0_ena_ctrl, ACHTELSEKUNDEN0_clk_ctrl,
+	 PIC_INT_SYNC0_clk_ctrl, WERTE0_63_ena_ctrl, WERTE0_62_ena_ctrl,
+	 WERTE0_61_ena_ctrl, WERTE0_60_ena_ctrl, WERTE0_59_ena_ctrl,
+	 WERTE0_58_ena_ctrl, WERTE0_57_ena_ctrl, WERTE0_56_ena_ctrl,
+	 WERTE0_55_ena_ctrl, WERTE0_54_ena_ctrl, WERTE0_53_ena_ctrl,
+	 WERTE0_52_ena_ctrl, WERTE0_51_ena_ctrl, WERTE0_50_ena_ctrl,
+	 WERTE0_49_ena_ctrl, WERTE0_48_ena_ctrl, WERTE0_47_ena_ctrl,
+	 WERTE0_46_ena_ctrl, WERTE0_45_ena_ctrl, WERTE0_44_ena_ctrl,
+	 WERTE0_43_ena_ctrl, WERTE0_42_ena_ctrl, WERTE0_41_ena_ctrl,
+	 WERTE0_40_ena_ctrl, WERTE0_39_ena_ctrl, WERTE0_38_ena_ctrl,
+	 WERTE0_37_ena_ctrl, WERTE0_36_ena_ctrl, WERTE0_35_ena_ctrl,
+	 WERTE0_34_ena_ctrl, WERTE0_33_ena_ctrl, WERTE0_32_ena_ctrl,
+	 WERTE0_31_ena_ctrl, WERTE0_30_ena_ctrl, WERTE0_29_ena_ctrl,
+	 WERTE0_28_ena_ctrl, WERTE0_27_ena_ctrl, WERTE0_26_ena_ctrl,
+	 WERTE0_25_ena_ctrl, WERTE0_24_ena_ctrl, WERTE0_23_ena_ctrl,
+	 WERTE0_22_ena_ctrl, WERTE0_21_ena_ctrl, WERTE0_20_ena_ctrl,
+	 WERTE0_19_ena_ctrl, WERTE0_18_ena_ctrl, WERTE0_17_ena_ctrl,
+	 WERTE0_16_ena_ctrl, WERTE0_15_ena_ctrl, WERTE0_14_ena_ctrl,
+	 WERTE0_12_ena_ctrl, WERTE0_11_ena_ctrl, WERTE0_10_ena_ctrl,
+	 WERTE0_5_ena_ctrl, WERTE0_3_ena_ctrl, WERTE0_1_ena_ctrl,
+	 WERTE0_0_clk_ctrl, WERTE1_0_clk_ctrl, WERTE2_0_clk_ctrl,
+	 WERTE3_0_clk_ctrl, WERTE4_0_clk_ctrl, WERTE5_0_clk_ctrl,
+	 WERTE6_0_clk_ctrl, WERTE7_0_clk_ctrl, RTC_ADR0_ena_ctrl,
+	 RTC_ADR0_clk_ctrl, ACP_CONF0_ena_ctrl, ACP_CONF8_ena_ctrl,
+	 ACP_CONF16_ena_ctrl, ACP_CONF24_ena_ctrl, ACP_CONF0_clk_ctrl,
+	 INT_CLEAR0_clk_ctrl, INT_ENA0_ena_ctrl, INT_ENA8_ena_ctrl,
+	 INT_ENA16_ena_ctrl, INT_ENA24_ena_ctrl, INT_ENA0_clk_ctrl,
+	 INT_CTR0_ena_ctrl, INT_CTR8_ena_ctrl, INT_CTR16_ena_ctrl,
+	 INT_CTR24_ena_ctrl, INT_CTR0_clk_ctrl, INT_LATCH9_clk_1,
+	 INT_LATCH8_clk_1, INT_LATCH7_clk_1, INT_LATCH6_clk_1,
+	 INT_LATCH5_clk_1, INT_LATCH4_clk_1, INT_LATCH3_clk_1,
+	 INT_LATCH2_clk_1, INT_LATCH1_clk_1, INT_LATCH0_clk_1;
+   reg [31:0] INT_CTR_q;
+   reg [31:0] INT_LATCH_q;
+   reg [31:0] INT_CLEAR_q;
+   reg [31:0] INT_ENA_q;
+   reg [31:0] ACP_CONF_q;
+   reg [5:0] RTC_ADR_q;
+   reg [2:0] ACHTELSEKUNDEN_q;
+   reg [63:0] WERTE7__q;
+   reg [63:0] WERTE6__q;
+   reg [63:0] WERTE5__q;
+   reg [63:0] WERTE4__q;
+   reg [63:0] WERTE3__q;
+   reg [63:0] WERTE2__q;
+   reg [63:0] WERTE1__q;
+   reg [63:0] WERTE0__q;
+   reg [2:0] PIC_INT_SYNC_q;
+
+
+// Sub Module Section
+   lpm_bustri_BYT  u0 (.data(u0_data), .enabledt(u0_enabledt),
+	 .tridata(u0_tridata));
+
+   lpm_bustri_BYT  u1 (.data(u1_data), .enabledt(u1_enabledt),
+	 .tridata(u1_tridata));
+
+   lpm_bustri_BYT  u2 (.data(u2_data), .enabledt(u2_enabledt),
+	 .tridata(u2_tridata));
+
+   lpm_bustri_BYT  u3 (.data(u3_data), .enabledt(u3_enabledt),
+	 .tridata(u3_tridata));
+
+
+   assign ACP_CONF[31:24] = ACP_CONF_q[31:24];
+   always @(posedge ACP_CONF0_clk_ctrl)
+      if (ACP_CONF24_ena_ctrl)
+	 {ACP_CONF_q[31], ACP_CONF_q[30], ACP_CONF_q[29], ACP_CONF_q[28],
+	       ACP_CONF_q[27], ACP_CONF_q[26], ACP_CONF_q[25], ACP_CONF_q[24]}
+	       <= ACP_CONF_d[31:24];
+
+   assign ACP_CONF[23:16] = ACP_CONF_q[23:16];
+   always @(posedge ACP_CONF0_clk_ctrl)
+      if (ACP_CONF16_ena_ctrl)
+	 {ACP_CONF_q[23], ACP_CONF_q[22], ACP_CONF_q[21], ACP_CONF_q[20],
+	       ACP_CONF_q[19], ACP_CONF_q[18], ACP_CONF_q[17], ACP_CONF_q[16]}
+	       <= ACP_CONF_d[23:16];
+
+   assign ACP_CONF[15:8] = ACP_CONF_q[15:8];
+   always @(posedge ACP_CONF0_clk_ctrl)
+      if (ACP_CONF8_ena_ctrl)
+	 {ACP_CONF_q[15], ACP_CONF_q[14], ACP_CONF_q[13], ACP_CONF_q[12],
+	       ACP_CONF_q[11], ACP_CONF_q[10], ACP_CONF_q[9], ACP_CONF_q[8]} <=
+	       ACP_CONF_d[15:8];
+
+   assign ACP_CONF[7:0] = ACP_CONF_q[7:0];
+   always @(posedge ACP_CONF0_clk_ctrl)
+      if (ACP_CONF0_ena_ctrl)
+	 {ACP_CONF_q[7], ACP_CONF_q[6], ACP_CONF_q[5], ACP_CONF_q[4],
+	       ACP_CONF_q[3], ACP_CONF_q[2], ACP_CONF_q[1], ACP_CONF_q[0]} <=
+	       ACP_CONF_d[7:0];
+
+   always @(posedge INT_CTR0_clk_ctrl)
+      if (INT_CTR24_ena_ctrl)
+	 {INT_CTR_q[31], INT_CTR_q[30], INT_CTR_q[29], INT_CTR_q[28],
+	       INT_CTR_q[27], INT_CTR_q[26], INT_CTR_q[25], INT_CTR_q[24]} <=
+	       INT_CTR_d[31:24];
+
+   always @(posedge INT_CTR0_clk_ctrl)
+      if (INT_CTR16_ena_ctrl)
+	 {INT_CTR_q[23], INT_CTR_q[22], INT_CTR_q[21], INT_CTR_q[20],
+	       INT_CTR_q[19], INT_CTR_q[18], INT_CTR_q[17], INT_CTR_q[16]} <=
+	       INT_CTR_d[23:16];
+
+   always @(posedge INT_CTR0_clk_ctrl)
+      if (INT_CTR8_ena_ctrl)
+	 {INT_CTR_q[15], INT_CTR_q[14], INT_CTR_q[13], INT_CTR_q[12],
+	       INT_CTR_q[11], INT_CTR_q[10], INT_CTR_q[9], INT_CTR_q[8]} <=
+	       INT_CTR_d[15:8];
+
+   always @(posedge INT_CTR0_clk_ctrl)
+      if (INT_CTR0_ena_ctrl)
+	 {INT_CTR_q[7], INT_CTR_q[6], INT_CTR_q[5], INT_CTR_q[4], INT_CTR_q[3],
+	       INT_CTR_q[2], INT_CTR_q[1], INT_CTR_q[0]} <= INT_CTR_d[7:0];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH31_clrn)
+      if (!INT_LATCH31_clrn)
+	 INT_LATCH_q[31] <= 1'h0;
+      else
+	 INT_LATCH_q[31] <= INT_LATCH_d[31];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH30_clrn)
+      if (!INT_LATCH30_clrn)
+	 INT_LATCH_q[30] <= 1'h0;
+      else
+	 INT_LATCH_q[30] <= INT_LATCH_d[30];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH29_clrn)
+      if (!INT_LATCH29_clrn)
+	 INT_LATCH_q[29] <= 1'h0;
+      else
+	 INT_LATCH_q[29] <= INT_LATCH_d[29];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH28_clrn)
+      if (!INT_LATCH28_clrn)
+	 INT_LATCH_q[28] <= 1'h0;
+      else
+	 INT_LATCH_q[28] <= INT_LATCH_d[28];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH27_clrn)
+      if (!INT_LATCH27_clrn)
+	 INT_LATCH_q[27] <= 1'h0;
+      else
+	 INT_LATCH_q[27] <= INT_LATCH_d[27];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH26_clrn)
+      if (!INT_LATCH26_clrn)
+	 INT_LATCH_q[26] <= 1'h0;
+      else
+	 INT_LATCH_q[26] <= INT_LATCH_d[26];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH25_clrn)
+      if (!INT_LATCH25_clrn)
+	 INT_LATCH_q[25] <= 1'h0;
+      else
+	 INT_LATCH_q[25] <= INT_LATCH_d[25];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH24_clrn)
+      if (!INT_LATCH24_clrn)
+	 INT_LATCH_q[24] <= 1'h0;
+      else
+	 INT_LATCH_q[24] <= INT_LATCH_d[24];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH23_clrn)
+      if (!INT_LATCH23_clrn)
+	 INT_LATCH_q[23] <= 1'h0;
+      else
+	 INT_LATCH_q[23] <= INT_LATCH_d[23];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH22_clrn)
+      if (!INT_LATCH22_clrn)
+	 INT_LATCH_q[22] <= 1'h0;
+      else
+	 INT_LATCH_q[22] <= INT_LATCH_d[22];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH21_clrn)
+      if (!INT_LATCH21_clrn)
+	 INT_LATCH_q[21] <= 1'h0;
+      else
+	 INT_LATCH_q[21] <= INT_LATCH_d[21];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH20_clrn)
+      if (!INT_LATCH20_clrn)
+	 INT_LATCH_q[20] <= 1'h0;
+      else
+	 INT_LATCH_q[20] <= INT_LATCH_d[20];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH19_clrn)
+      if (!INT_LATCH19_clrn)
+	 INT_LATCH_q[19] <= 1'h0;
+      else
+	 INT_LATCH_q[19] <= INT_LATCH_d[19];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH18_clrn)
+      if (!INT_LATCH18_clrn)
+	 INT_LATCH_q[18] <= 1'h0;
+      else
+	 INT_LATCH_q[18] <= INT_LATCH_d[18];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH17_clrn)
+      if (!INT_LATCH17_clrn)
+	 INT_LATCH_q[17] <= 1'h0;
+      else
+	 INT_LATCH_q[17] <= INT_LATCH_d[17];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH16_clrn)
+      if (!INT_LATCH16_clrn)
+	 INT_LATCH_q[16] <= 1'h0;
+      else
+	 INT_LATCH_q[16] <= INT_LATCH_d[16];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH15_clrn)
+      if (!INT_LATCH15_clrn)
+	 INT_LATCH_q[15] <= 1'h0;
+      else
+	 INT_LATCH_q[15] <= INT_LATCH_d[15];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH14_clrn)
+      if (!INT_LATCH14_clrn)
+	 INT_LATCH_q[14] <= 1'h0;
+      else
+	 INT_LATCH_q[14] <= INT_LATCH_d[14];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH13_clrn)
+      if (!INT_LATCH13_clrn)
+	 INT_LATCH_q[13] <= 1'h0;
+      else
+	 INT_LATCH_q[13] <= INT_LATCH_d[13];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH12_clrn)
+      if (!INT_LATCH12_clrn)
+	 INT_LATCH_q[12] <= 1'h0;
+      else
+	 INT_LATCH_q[12] <= INT_LATCH_d[12];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH11_clrn)
+      if (!INT_LATCH11_clrn)
+	 INT_LATCH_q[11] <= 1'h0;
+      else
+	 INT_LATCH_q[11] <= INT_LATCH_d[11];
+
+   always @(posedge INT_LATCH_clk or negedge INT_LATCH10_clrn)
+      if (!INT_LATCH10_clrn)
+	 INT_LATCH_q[10] <= 1'h0;
+      else
+	 INT_LATCH_q[10] <= INT_LATCH_d[10];
+
+   always @(posedge INT_LATCH9_clk_1 or negedge INT_LATCH9_clrn)
+      if (!INT_LATCH9_clrn)
+	 INT_LATCH_q[9] <= 1'h0;
+      else
+	 INT_LATCH_q[9] <= INT_LATCH_d[9];
+
+   always @(posedge INT_LATCH8_clk_1 or negedge INT_LATCH8_clrn)
+      if (!INT_LATCH8_clrn)
+	 INT_LATCH_q[8] <= 1'h0;
+      else
+	 INT_LATCH_q[8] <= INT_LATCH_d[8];
+
+   always @(posedge INT_LATCH7_clk_1 or negedge INT_LATCH7_clrn)
+      if (!INT_LATCH7_clrn)
+	 INT_LATCH_q[7] <= 1'h0;
+      else
+	 INT_LATCH_q[7] <= INT_LATCH_d[7];
+
+   always @(posedge INT_LATCH6_clk_1 or negedge INT_LATCH6_clrn)
+      if (!INT_LATCH6_clrn)
+	 INT_LATCH_q[6] <= 1'h0;
+      else
+	 INT_LATCH_q[6] <= INT_LATCH_d[6];
+
+   always @(posedge INT_LATCH5_clk_1 or negedge INT_LATCH5_clrn)
+      if (!INT_LATCH5_clrn)
+	 INT_LATCH_q[5] <= 1'h0;
+      else
+	 INT_LATCH_q[5] <= INT_LATCH_d[5];
+
+   always @(posedge INT_LATCH4_clk_1 or negedge INT_LATCH4_clrn)
+      if (!INT_LATCH4_clrn)
+	 INT_LATCH_q[4] <= 1'h0;
+      else
+	 INT_LATCH_q[4] <= INT_LATCH_d[4];
+
+   always @(posedge INT_LATCH3_clk_1 or negedge INT_LATCH3_clrn)
+      if (!INT_LATCH3_clrn)
+	 INT_LATCH_q[3] <= 1'h0;
+      else
+	 INT_LATCH_q[3] <= INT_LATCH_d[3];
+
+   always @(posedge INT_LATCH2_clk_1 or negedge INT_LATCH2_clrn)
+      if (!INT_LATCH2_clrn)
+	 INT_LATCH_q[2] <= 1'h0;
+      else
+	 INT_LATCH_q[2] <= INT_LATCH_d[2];
+
+   always @(posedge INT_LATCH1_clk_1 or negedge INT_LATCH1_clrn)
+      if (!INT_LATCH1_clrn)
+	 INT_LATCH_q[1] <= 1'h0;
+      else
+	 INT_LATCH_q[1] <= INT_LATCH_d[1];
+
+   always @(posedge INT_LATCH0_clk_1 or negedge INT_LATCH0_clrn)
+      if (!INT_LATCH0_clrn)
+	 INT_LATCH_q[0] <= 1'h0;
+      else
+	 INT_LATCH_q[0] <= INT_LATCH_d[0];
+
+   always @(posedge INT_CLEAR0_clk_ctrl)
+      INT_CLEAR_q <= INT_CLEAR_d;
+
+   always @(posedge INT_ENA0_clk_ctrl)
+      if (INT_ENA24_ena_ctrl)
+	 {INT_ENA_q[31], INT_ENA_q[30], INT_ENA_q[29], INT_ENA_q[28],
+	       INT_ENA_q[27], INT_ENA_q[26], INT_ENA_q[25], INT_ENA_q[24]} <=
+	       INT_ENA_d[31:24];
+
+   always @(posedge INT_ENA0_clk_ctrl)
+      if (INT_ENA16_ena_ctrl)
+	 {INT_ENA_q[23], INT_ENA_q[22], INT_ENA_q[21], INT_ENA_q[20],
+	       INT_ENA_q[19], INT_ENA_q[18], INT_ENA_q[17], INT_ENA_q[16]} <=
+	       INT_ENA_d[23:16];
+
+   always @(posedge INT_ENA0_clk_ctrl)
+      if (INT_ENA8_ena_ctrl)
+	 {INT_ENA_q[15], INT_ENA_q[14], INT_ENA_q[13], INT_ENA_q[12],
+	       INT_ENA_q[11], INT_ENA_q[10], INT_ENA_q[9], INT_ENA_q[8]} <=
+	       INT_ENA_d[15:8];
+
+   always @(posedge INT_ENA0_clk_ctrl)
+      if (INT_ENA0_ena_ctrl)
+	 {INT_ENA_q[7], INT_ENA_q[6], INT_ENA_q[5], INT_ENA_q[4], INT_ENA_q[3],
+	       INT_ENA_q[2], INT_ENA_q[1], INT_ENA_q[0]} <= INT_ENA_d[7:0];
+
+   always @(posedge RTC_ADR0_clk_ctrl)
+      if (RTC_ADR0_ena_ctrl)
+	 RTC_ADR_q <= RTC_ADR_d;
+
+   always @(posedge ACHTELSEKUNDEN0_clk_ctrl)
+      if (ACHTELSEKUNDEN0_ena_ctrl)
+	 ACHTELSEKUNDEN_q <= ACHTELSEKUNDEN_d;
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_63_ena_ctrl)
+	 WERTE7__q[63] <= WERTE7__d[63];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_62_ena_ctrl)
+	 WERTE7__q[62] <= WERTE7__d[62];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_61_ena_ctrl)
+	 WERTE7__q[61] <= WERTE7__d[61];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_60_ena_ctrl)
+	 WERTE7__q[60] <= WERTE7__d[60];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_59_ena_ctrl)
+	 WERTE7__q[59] <= WERTE7__d[59];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_58_ena_ctrl)
+	 WERTE7__q[58] <= WERTE7__d[58];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_57_ena_ctrl)
+	 WERTE7__q[57] <= WERTE7__d[57];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_56_ena_ctrl)
+	 WERTE7__q[56] <= WERTE7__d[56];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_55_ena_ctrl)
+	 WERTE7__q[55] <= WERTE7__d[55];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_54_ena_ctrl)
+	 WERTE7__q[54] <= WERTE7__d[54];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_53_ena_ctrl)
+	 WERTE7__q[53] <= WERTE7__d[53];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_52_ena_ctrl)
+	 WERTE7__q[52] <= WERTE7__d[52];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_51_ena_ctrl)
+	 WERTE7__q[51] <= WERTE7__d[51];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_50_ena_ctrl)
+	 WERTE7__q[50] <= WERTE7__d[50];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_49_ena_ctrl)
+	 WERTE7__q[49] <= WERTE7__d[49];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_48_ena_ctrl)
+	 WERTE7__q[48] <= WERTE7__d[48];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_47_ena_ctrl)
+	 WERTE7__q[47] <= WERTE7__d[47];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_46_ena_ctrl)
+	 WERTE7__q[46] <= WERTE7__d[46];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_45_ena_ctrl)
+	 WERTE7__q[45] <= WERTE7__d[45];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_44_ena_ctrl)
+	 WERTE7__q[44] <= WERTE7__d[44];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_43_ena_ctrl)
+	 WERTE7__q[43] <= WERTE7__d[43];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_42_ena_ctrl)
+	 WERTE7__q[42] <= WERTE7__d[42];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_41_ena_ctrl)
+	 WERTE7__q[41] <= WERTE7__d[41];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_40_ena_ctrl)
+	 WERTE7__q[40] <= WERTE7__d[40];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_39_ena_ctrl)
+	 WERTE7__q[39] <= WERTE7__d[39];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_38_ena_ctrl)
+	 WERTE7__q[38] <= WERTE7__d[38];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_37_ena_ctrl)
+	 WERTE7__q[37] <= WERTE7__d[37];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_36_ena_ctrl)
+	 WERTE7__q[36] <= WERTE7__d[36];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_35_ena_ctrl)
+	 WERTE7__q[35] <= WERTE7__d[35];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_34_ena_ctrl)
+	 WERTE7__q[34] <= WERTE7__d[34];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_33_ena_ctrl)
+	 WERTE7__q[33] <= WERTE7__d[33];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_32_ena_ctrl)
+	 WERTE7__q[32] <= WERTE7__d[32];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_31_ena_ctrl)
+	 WERTE7__q[31] <= WERTE7__d[31];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_30_ena_ctrl)
+	 WERTE7__q[30] <= WERTE7__d[30];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_29_ena_ctrl)
+	 WERTE7__q[29] <= WERTE7__d[29];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_28_ena_ctrl)
+	 WERTE7__q[28] <= WERTE7__d[28];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_27_ena_ctrl)
+	 WERTE7__q[27] <= WERTE7__d[27];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_26_ena_ctrl)
+	 WERTE7__q[26] <= WERTE7__d[26];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_25_ena_ctrl)
+	 WERTE7__q[25] <= WERTE7__d[25];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_24_ena_ctrl)
+	 WERTE7__q[24] <= WERTE7__d[24];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_23_ena_ctrl)
+	 WERTE7__q[23] <= WERTE7__d[23];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_22_ena_ctrl)
+	 WERTE7__q[22] <= WERTE7__d[22];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_21_ena_ctrl)
+	 WERTE7__q[21] <= WERTE7__d[21];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_20_ena_ctrl)
+	 WERTE7__q[20] <= WERTE7__d[20];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_19_ena_ctrl)
+	 WERTE7__q[19] <= WERTE7__d[19];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_18_ena_ctrl)
+	 WERTE7__q[18] <= WERTE7__d[18];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_17_ena_ctrl)
+	 WERTE7__q[17] <= WERTE7__d[17];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_16_ena_ctrl)
+	 WERTE7__q[16] <= WERTE7__d[16];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_15_ena_ctrl)
+	 WERTE7__q[15] <= WERTE7__d[15];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_14_ena_ctrl)
+	 WERTE7__q[14] <= WERTE7__d[14];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE7_13_ena)
+	 WERTE7__q[13] <= WERTE7__d[13];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_12_ena_ctrl)
+	 WERTE7__q[12] <= WERTE7__d[12];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_11_ena_ctrl)
+	 WERTE7__q[11] <= WERTE7__d[11];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_10_ena_ctrl)
+	 WERTE7__q[10] <= WERTE7__d[10];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE7_9_ena)
+	 WERTE7__q[9] <= WERTE7__d[9];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE7_8_ena)
+	 WERTE7__q[8] <= WERTE7__d[8];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE7_7_ena)
+	 WERTE7__q[7] <= WERTE7__d[7];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE7_6_ena)
+	 WERTE7__q[6] <= WERTE7__d[6];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_5_ena_ctrl)
+	 WERTE7__q[5] <= WERTE7__d[5];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE7_4_ena)
+	 WERTE7__q[4] <= WERTE7__d[4];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_3_ena_ctrl)
+	 WERTE7__q[3] <= WERTE7__d[3];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE7_2_ena)
+	 WERTE7__q[2] <= WERTE7__d[2];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE0_1_ena_ctrl)
+	 WERTE7__q[1] <= WERTE7__d[1];
+
+   always @(posedge WERTE7_0_clk_ctrl)
+      if (WERTE7_0_ena)
+	 WERTE7__q[0] <= WERTE7__d[0];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_63_ena_ctrl)
+	 WERTE6__q[63] <= WERTE6__d[63];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_62_ena_ctrl)
+	 WERTE6__q[62] <= WERTE6__d[62];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_61_ena_ctrl)
+	 WERTE6__q[61] <= WERTE6__d[61];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_60_ena_ctrl)
+	 WERTE6__q[60] <= WERTE6__d[60];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_59_ena_ctrl)
+	 WERTE6__q[59] <= WERTE6__d[59];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_58_ena_ctrl)
+	 WERTE6__q[58] <= WERTE6__d[58];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_57_ena_ctrl)
+	 WERTE6__q[57] <= WERTE6__d[57];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_56_ena_ctrl)
+	 WERTE6__q[56] <= WERTE6__d[56];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_55_ena_ctrl)
+	 WERTE6__q[55] <= WERTE6__d[55];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_54_ena_ctrl)
+	 WERTE6__q[54] <= WERTE6__d[54];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_53_ena_ctrl)
+	 WERTE6__q[53] <= WERTE6__d[53];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_52_ena_ctrl)
+	 WERTE6__q[52] <= WERTE6__d[52];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_51_ena_ctrl)
+	 WERTE6__q[51] <= WERTE6__d[51];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_50_ena_ctrl)
+	 WERTE6__q[50] <= WERTE6__d[50];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_49_ena_ctrl)
+	 WERTE6__q[49] <= WERTE6__d[49];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_48_ena_ctrl)
+	 WERTE6__q[48] <= WERTE6__d[48];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_47_ena_ctrl)
+	 WERTE6__q[47] <= WERTE6__d[47];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_46_ena_ctrl)
+	 WERTE6__q[46] <= WERTE6__d[46];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_45_ena_ctrl)
+	 WERTE6__q[45] <= WERTE6__d[45];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_44_ena_ctrl)
+	 WERTE6__q[44] <= WERTE6__d[44];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_43_ena_ctrl)
+	 WERTE6__q[43] <= WERTE6__d[43];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_42_ena_ctrl)
+	 WERTE6__q[42] <= WERTE6__d[42];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_41_ena_ctrl)
+	 WERTE6__q[41] <= WERTE6__d[41];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_40_ena_ctrl)
+	 WERTE6__q[40] <= WERTE6__d[40];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_39_ena_ctrl)
+	 WERTE6__q[39] <= WERTE6__d[39];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_38_ena_ctrl)
+	 WERTE6__q[38] <= WERTE6__d[38];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_37_ena_ctrl)
+	 WERTE6__q[37] <= WERTE6__d[37];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_36_ena_ctrl)
+	 WERTE6__q[36] <= WERTE6__d[36];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_35_ena_ctrl)
+	 WERTE6__q[35] <= WERTE6__d[35];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_34_ena_ctrl)
+	 WERTE6__q[34] <= WERTE6__d[34];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_33_ena_ctrl)
+	 WERTE6__q[33] <= WERTE6__d[33];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_32_ena_ctrl)
+	 WERTE6__q[32] <= WERTE6__d[32];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_31_ena_ctrl)
+	 WERTE6__q[31] <= WERTE6__d[31];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_30_ena_ctrl)
+	 WERTE6__q[30] <= WERTE6__d[30];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_29_ena_ctrl)
+	 WERTE6__q[29] <= WERTE6__d[29];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_28_ena_ctrl)
+	 WERTE6__q[28] <= WERTE6__d[28];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_27_ena_ctrl)
+	 WERTE6__q[27] <= WERTE6__d[27];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_26_ena_ctrl)
+	 WERTE6__q[26] <= WERTE6__d[26];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_25_ena_ctrl)
+	 WERTE6__q[25] <= WERTE6__d[25];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_24_ena_ctrl)
+	 WERTE6__q[24] <= WERTE6__d[24];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_23_ena_ctrl)
+	 WERTE6__q[23] <= WERTE6__d[23];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_22_ena_ctrl)
+	 WERTE6__q[22] <= WERTE6__d[22];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_21_ena_ctrl)
+	 WERTE6__q[21] <= WERTE6__d[21];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_20_ena_ctrl)
+	 WERTE6__q[20] <= WERTE6__d[20];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_19_ena_ctrl)
+	 WERTE6__q[19] <= WERTE6__d[19];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_18_ena_ctrl)
+	 WERTE6__q[18] <= WERTE6__d[18];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_17_ena_ctrl)
+	 WERTE6__q[17] <= WERTE6__d[17];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_16_ena_ctrl)
+	 WERTE6__q[16] <= WERTE6__d[16];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_15_ena_ctrl)
+	 WERTE6__q[15] <= WERTE6__d[15];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_14_ena_ctrl)
+	 WERTE6__q[14] <= WERTE6__d[14];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE6_13_ena)
+	 WERTE6__q[13] <= WERTE6__d[13];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_12_ena_ctrl)
+	 WERTE6__q[12] <= WERTE6__d[12];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_11_ena_ctrl)
+	 WERTE6__q[11] <= WERTE6__d[11];
+
+   always @(posedge WERTE6_0_clk_ctrl or negedge WERTE6_10_clrn)
+      if (!WERTE6_10_clrn)
+	 WERTE6__q[10] <= 1'h0;
+      else
+	 if (WERTE0_10_ena_ctrl)
+	    WERTE6__q[10] <= WERTE6__d[10];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE6_9_ena)
+	 WERTE6__q[9] <= WERTE6__d[9];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE6_8_ena)
+	 WERTE6__q[8] <= WERTE6__d[8];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE6_7_ena)
+	 WERTE6__q[7] <= WERTE6__d[7];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE6_6_ena)
+	 WERTE6__q[6] <= WERTE6__d[6];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_5_ena_ctrl)
+	 WERTE6__q[5] <= WERTE6__d[5];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE6_4_ena)
+	 WERTE6__q[4] <= WERTE6__d[4];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_3_ena_ctrl)
+	 WERTE6__q[3] <= WERTE6__d[3];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE6_2_ena)
+	 WERTE6__q[2] <= WERTE6__d[2];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE0_1_ena_ctrl)
+	 WERTE6__q[1] <= WERTE6__d[1];
+
+   always @(posedge WERTE6_0_clk_ctrl)
+      if (WERTE6_0_ena)
+	 WERTE6__q[0] <= WERTE6__d[0];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_63_ena_ctrl)
+	 WERTE5__q[63] <= WERTE5__d[63];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_62_ena_ctrl)
+	 WERTE5__q[62] <= WERTE5__d[62];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_61_ena_ctrl)
+	 WERTE5__q[61] <= WERTE5__d[61];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_60_ena_ctrl)
+	 WERTE5__q[60] <= WERTE5__d[60];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_59_ena_ctrl)
+	 WERTE5__q[59] <= WERTE5__d[59];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_58_ena_ctrl)
+	 WERTE5__q[58] <= WERTE5__d[58];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_57_ena_ctrl)
+	 WERTE5__q[57] <= WERTE5__d[57];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_56_ena_ctrl)
+	 WERTE5__q[56] <= WERTE5__d[56];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_55_ena_ctrl)
+	 WERTE5__q[55] <= WERTE5__d[55];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_54_ena_ctrl)
+	 WERTE5__q[54] <= WERTE5__d[54];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_53_ena_ctrl)
+	 WERTE5__q[53] <= WERTE5__d[53];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_52_ena_ctrl)
+	 WERTE5__q[52] <= WERTE5__d[52];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_51_ena_ctrl)
+	 WERTE5__q[51] <= WERTE5__d[51];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_50_ena_ctrl)
+	 WERTE5__q[50] <= WERTE5__d[50];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_49_ena_ctrl)
+	 WERTE5__q[49] <= WERTE5__d[49];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_48_ena_ctrl)
+	 WERTE5__q[48] <= WERTE5__d[48];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_47_ena_ctrl)
+	 WERTE5__q[47] <= WERTE5__d[47];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_46_ena_ctrl)
+	 WERTE5__q[46] <= WERTE5__d[46];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_45_ena_ctrl)
+	 WERTE5__q[45] <= WERTE5__d[45];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_44_ena_ctrl)
+	 WERTE5__q[44] <= WERTE5__d[44];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_43_ena_ctrl)
+	 WERTE5__q[43] <= WERTE5__d[43];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_42_ena_ctrl)
+	 WERTE5__q[42] <= WERTE5__d[42];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_41_ena_ctrl)
+	 WERTE5__q[41] <= WERTE5__d[41];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_40_ena_ctrl)
+	 WERTE5__q[40] <= WERTE5__d[40];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_39_ena_ctrl)
+	 WERTE5__q[39] <= WERTE5__d[39];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_38_ena_ctrl)
+	 WERTE5__q[38] <= WERTE5__d[38];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_37_ena_ctrl)
+	 WERTE5__q[37] <= WERTE5__d[37];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_36_ena_ctrl)
+	 WERTE5__q[36] <= WERTE5__d[36];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_35_ena_ctrl)
+	 WERTE5__q[35] <= WERTE5__d[35];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_34_ena_ctrl)
+	 WERTE5__q[34] <= WERTE5__d[34];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_33_ena_ctrl)
+	 WERTE5__q[33] <= WERTE5__d[33];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_32_ena_ctrl)
+	 WERTE5__q[32] <= WERTE5__d[32];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_31_ena_ctrl)
+	 WERTE5__q[31] <= WERTE5__d[31];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_30_ena_ctrl)
+	 WERTE5__q[30] <= WERTE5__d[30];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_29_ena_ctrl)
+	 WERTE5__q[29] <= WERTE5__d[29];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_28_ena_ctrl)
+	 WERTE5__q[28] <= WERTE5__d[28];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_27_ena_ctrl)
+	 WERTE5__q[27] <= WERTE5__d[27];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_26_ena_ctrl)
+	 WERTE5__q[26] <= WERTE5__d[26];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_25_ena_ctrl)
+	 WERTE5__q[25] <= WERTE5__d[25];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_24_ena_ctrl)
+	 WERTE5__q[24] <= WERTE5__d[24];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_23_ena_ctrl)
+	 WERTE5__q[23] <= WERTE5__d[23];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_22_ena_ctrl)
+	 WERTE5__q[22] <= WERTE5__d[22];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_21_ena_ctrl)
+	 WERTE5__q[21] <= WERTE5__d[21];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_20_ena_ctrl)
+	 WERTE5__q[20] <= WERTE5__d[20];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_19_ena_ctrl)
+	 WERTE5__q[19] <= WERTE5__d[19];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_18_ena_ctrl)
+	 WERTE5__q[18] <= WERTE5__d[18];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_17_ena_ctrl)
+	 WERTE5__q[17] <= WERTE5__d[17];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_16_ena_ctrl)
+	 WERTE5__q[16] <= WERTE5__d[16];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_15_ena_ctrl)
+	 WERTE5__q[15] <= WERTE5__d[15];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_14_ena_ctrl)
+	 WERTE5__q[14] <= WERTE5__d[14];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE5_13_ena)
+	 WERTE5__q[13] <= WERTE5__d[13];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_12_ena_ctrl)
+	 WERTE5__q[12] <= WERTE5__d[12];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_11_ena_ctrl)
+	 WERTE5__q[11] <= WERTE5__d[11];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_10_ena_ctrl)
+	 WERTE5__q[10] <= WERTE5__d[10];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE5_9_ena)
+	 WERTE5__q[9] <= WERTE5__d[9];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE5_8_ena)
+	 WERTE5__q[8] <= WERTE5__d[8];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE5_7_ena)
+	 WERTE5__q[7] <= WERTE5__d[7];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE5_6_ena)
+	 WERTE5__q[6] <= WERTE5__d[6];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_5_ena_ctrl)
+	 WERTE5__q[5] <= WERTE5__d[5];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE5_4_ena)
+	 WERTE5__q[4] <= WERTE5__d[4];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_3_ena_ctrl)
+	 WERTE5__q[3] <= WERTE5__d[3];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE5_2_ena)
+	 WERTE5__q[2] <= WERTE5__d[2];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE0_1_ena_ctrl)
+	 WERTE5__q[1] <= WERTE5__d[1];
+
+   always @(posedge WERTE5_0_clk_ctrl)
+      if (WERTE5_0_ena)
+	 WERTE5__q[0] <= WERTE5__d[0];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_63_ena_ctrl)
+	 WERTE4__q[63] <= WERTE4__d[63];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_62_ena_ctrl)
+	 WERTE4__q[62] <= WERTE4__d[62];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_61_ena_ctrl)
+	 WERTE4__q[61] <= WERTE4__d[61];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_60_ena_ctrl)
+	 WERTE4__q[60] <= WERTE4__d[60];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_59_ena_ctrl)
+	 WERTE4__q[59] <= WERTE4__d[59];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_58_ena_ctrl)
+	 WERTE4__q[58] <= WERTE4__d[58];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_57_ena_ctrl)
+	 WERTE4__q[57] <= WERTE4__d[57];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_56_ena_ctrl)
+	 WERTE4__q[56] <= WERTE4__d[56];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_55_ena_ctrl)
+	 WERTE4__q[55] <= WERTE4__d[55];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_54_ena_ctrl)
+	 WERTE4__q[54] <= WERTE4__d[54];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_53_ena_ctrl)
+	 WERTE4__q[53] <= WERTE4__d[53];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_52_ena_ctrl)
+	 WERTE4__q[52] <= WERTE4__d[52];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_51_ena_ctrl)
+	 WERTE4__q[51] <= WERTE4__d[51];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_50_ena_ctrl)
+	 WERTE4__q[50] <= WERTE4__d[50];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_49_ena_ctrl)
+	 WERTE4__q[49] <= WERTE4__d[49];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_48_ena_ctrl)
+	 WERTE4__q[48] <= WERTE4__d[48];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_47_ena_ctrl)
+	 WERTE4__q[47] <= WERTE4__d[47];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_46_ena_ctrl)
+	 WERTE4__q[46] <= WERTE4__d[46];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_45_ena_ctrl)
+	 WERTE4__q[45] <= WERTE4__d[45];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_44_ena_ctrl)
+	 WERTE4__q[44] <= WERTE4__d[44];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_43_ena_ctrl)
+	 WERTE4__q[43] <= WERTE4__d[43];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_42_ena_ctrl)
+	 WERTE4__q[42] <= WERTE4__d[42];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_41_ena_ctrl)
+	 WERTE4__q[41] <= WERTE4__d[41];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_40_ena_ctrl)
+	 WERTE4__q[40] <= WERTE4__d[40];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_39_ena_ctrl)
+	 WERTE4__q[39] <= WERTE4__d[39];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_38_ena_ctrl)
+	 WERTE4__q[38] <= WERTE4__d[38];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_37_ena_ctrl)
+	 WERTE4__q[37] <= WERTE4__d[37];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_36_ena_ctrl)
+	 WERTE4__q[36] <= WERTE4__d[36];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_35_ena_ctrl)
+	 WERTE4__q[35] <= WERTE4__d[35];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_34_ena_ctrl)
+	 WERTE4__q[34] <= WERTE4__d[34];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_33_ena_ctrl)
+	 WERTE4__q[33] <= WERTE4__d[33];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_32_ena_ctrl)
+	 WERTE4__q[32] <= WERTE4__d[32];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_31_ena_ctrl)
+	 WERTE4__q[31] <= WERTE4__d[31];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_30_ena_ctrl)
+	 WERTE4__q[30] <= WERTE4__d[30];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_29_ena_ctrl)
+	 WERTE4__q[29] <= WERTE4__d[29];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_28_ena_ctrl)
+	 WERTE4__q[28] <= WERTE4__d[28];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_27_ena_ctrl)
+	 WERTE4__q[27] <= WERTE4__d[27];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_26_ena_ctrl)
+	 WERTE4__q[26] <= WERTE4__d[26];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_25_ena_ctrl)
+	 WERTE4__q[25] <= WERTE4__d[25];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_24_ena_ctrl)
+	 WERTE4__q[24] <= WERTE4__d[24];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_23_ena_ctrl)
+	 WERTE4__q[23] <= WERTE4__d[23];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_22_ena_ctrl)
+	 WERTE4__q[22] <= WERTE4__d[22];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_21_ena_ctrl)
+	 WERTE4__q[21] <= WERTE4__d[21];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_20_ena_ctrl)
+	 WERTE4__q[20] <= WERTE4__d[20];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_19_ena_ctrl)
+	 WERTE4__q[19] <= WERTE4__d[19];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_18_ena_ctrl)
+	 WERTE4__q[18] <= WERTE4__d[18];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_17_ena_ctrl)
+	 WERTE4__q[17] <= WERTE4__d[17];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_16_ena_ctrl)
+	 WERTE4__q[16] <= WERTE4__d[16];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_15_ena_ctrl)
+	 WERTE4__q[15] <= WERTE4__d[15];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_14_ena_ctrl)
+	 WERTE4__q[14] <= WERTE4__d[14];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE4_13_ena)
+	 WERTE4__q[13] <= WERTE4__d[13];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_12_ena_ctrl)
+	 WERTE4__q[12] <= WERTE4__d[12];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_11_ena_ctrl)
+	 WERTE4__q[11] <= WERTE4__d[11];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_10_ena_ctrl)
+	 WERTE4__q[10] <= WERTE4__d[10];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE4_9_ena)
+	 WERTE4__q[9] <= WERTE4__d[9];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE4_8_ena)
+	 WERTE4__q[8] <= WERTE4__d[8];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE4_7_ena)
+	 WERTE4__q[7] <= WERTE4__d[7];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE4_6_ena)
+	 WERTE4__q[6] <= WERTE4__d[6];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_5_ena_ctrl)
+	 WERTE4__q[5] <= WERTE4__d[5];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE4_4_ena)
+	 WERTE4__q[4] <= WERTE4__d[4];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_3_ena_ctrl)
+	 WERTE4__q[3] <= WERTE4__d[3];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE4_2_ena)
+	 WERTE4__q[2] <= WERTE4__d[2];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE0_1_ena_ctrl)
+	 WERTE4__q[1] <= WERTE4__d[1];
+
+   always @(posedge WERTE4_0_clk_ctrl)
+      if (WERTE4_0_ena)
+	 WERTE4__q[0] <= WERTE4__d[0];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_63_ena_ctrl)
+	 WERTE3__q[63] <= WERTE3__d[63];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_62_ena_ctrl)
+	 WERTE3__q[62] <= WERTE3__d[62];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_61_ena_ctrl)
+	 WERTE3__q[61] <= WERTE3__d[61];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_60_ena_ctrl)
+	 WERTE3__q[60] <= WERTE3__d[60];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_59_ena_ctrl)
+	 WERTE3__q[59] <= WERTE3__d[59];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_58_ena_ctrl)
+	 WERTE3__q[58] <= WERTE3__d[58];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_57_ena_ctrl)
+	 WERTE3__q[57] <= WERTE3__d[57];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_56_ena_ctrl)
+	 WERTE3__q[56] <= WERTE3__d[56];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_55_ena_ctrl)
+	 WERTE3__q[55] <= WERTE3__d[55];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_54_ena_ctrl)
+	 WERTE3__q[54] <= WERTE3__d[54];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_53_ena_ctrl)
+	 WERTE3__q[53] <= WERTE3__d[53];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_52_ena_ctrl)
+	 WERTE3__q[52] <= WERTE3__d[52];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_51_ena_ctrl)
+	 WERTE3__q[51] <= WERTE3__d[51];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_50_ena_ctrl)
+	 WERTE3__q[50] <= WERTE3__d[50];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_49_ena_ctrl)
+	 WERTE3__q[49] <= WERTE3__d[49];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_48_ena_ctrl)
+	 WERTE3__q[48] <= WERTE3__d[48];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_47_ena_ctrl)
+	 WERTE3__q[47] <= WERTE3__d[47];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_46_ena_ctrl)
+	 WERTE3__q[46] <= WERTE3__d[46];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_45_ena_ctrl)
+	 WERTE3__q[45] <= WERTE3__d[45];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_44_ena_ctrl)
+	 WERTE3__q[44] <= WERTE3__d[44];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_43_ena_ctrl)
+	 WERTE3__q[43] <= WERTE3__d[43];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_42_ena_ctrl)
+	 WERTE3__q[42] <= WERTE3__d[42];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_41_ena_ctrl)
+	 WERTE3__q[41] <= WERTE3__d[41];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_40_ena_ctrl)
+	 WERTE3__q[40] <= WERTE3__d[40];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_39_ena_ctrl)
+	 WERTE3__q[39] <= WERTE3__d[39];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_38_ena_ctrl)
+	 WERTE3__q[38] <= WERTE3__d[38];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_37_ena_ctrl)
+	 WERTE3__q[37] <= WERTE3__d[37];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_36_ena_ctrl)
+	 WERTE3__q[36] <= WERTE3__d[36];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_35_ena_ctrl)
+	 WERTE3__q[35] <= WERTE3__d[35];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_34_ena_ctrl)
+	 WERTE3__q[34] <= WERTE3__d[34];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_33_ena_ctrl)
+	 WERTE3__q[33] <= WERTE3__d[33];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_32_ena_ctrl)
+	 WERTE3__q[32] <= WERTE3__d[32];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_31_ena_ctrl)
+	 WERTE3__q[31] <= WERTE3__d[31];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_30_ena_ctrl)
+	 WERTE3__q[30] <= WERTE3__d[30];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_29_ena_ctrl)
+	 WERTE3__q[29] <= WERTE3__d[29];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_28_ena_ctrl)
+	 WERTE3__q[28] <= WERTE3__d[28];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_27_ena_ctrl)
+	 WERTE3__q[27] <= WERTE3__d[27];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_26_ena_ctrl)
+	 WERTE3__q[26] <= WERTE3__d[26];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_25_ena_ctrl)
+	 WERTE3__q[25] <= WERTE3__d[25];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_24_ena_ctrl)
+	 WERTE3__q[24] <= WERTE3__d[24];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_23_ena_ctrl)
+	 WERTE3__q[23] <= WERTE3__d[23];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_22_ena_ctrl)
+	 WERTE3__q[22] <= WERTE3__d[22];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_21_ena_ctrl)
+	 WERTE3__q[21] <= WERTE3__d[21];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_20_ena_ctrl)
+	 WERTE3__q[20] <= WERTE3__d[20];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_19_ena_ctrl)
+	 WERTE3__q[19] <= WERTE3__d[19];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_18_ena_ctrl)
+	 WERTE3__q[18] <= WERTE3__d[18];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_17_ena_ctrl)
+	 WERTE3__q[17] <= WERTE3__d[17];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_16_ena_ctrl)
+	 WERTE3__q[16] <= WERTE3__d[16];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_15_ena_ctrl)
+	 WERTE3__q[15] <= WERTE3__d[15];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_14_ena_ctrl)
+	 WERTE3__q[14] <= WERTE3__d[14];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE3_13_ena)
+	 WERTE3__q[13] <= WERTE3__d[13];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_12_ena_ctrl)
+	 WERTE3__q[12] <= WERTE3__d[12];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_11_ena_ctrl)
+	 WERTE3__q[11] <= WERTE3__d[11];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_10_ena_ctrl)
+	 WERTE3__q[10] <= WERTE3__d[10];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE3_9_ena)
+	 WERTE3__q[9] <= WERTE3__d[9];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE3_8_ena)
+	 WERTE3__q[8] <= WERTE3__d[8];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE3_7_ena)
+	 WERTE3__q[7] <= WERTE3__d[7];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE3_6_ena)
+	 WERTE3__q[6] <= WERTE3__d[6];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_5_ena_ctrl)
+	 WERTE3__q[5] <= WERTE3__d[5];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE3_4_ena)
+	 WERTE3__q[4] <= WERTE3__d[4];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_3_ena_ctrl)
+	 WERTE3__q[3] <= WERTE3__d[3];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE3_2_ena)
+	 WERTE3__q[2] <= WERTE3__d[2];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE0_1_ena_ctrl)
+	 WERTE3__q[1] <= WERTE3__d[1];
+
+   always @(posedge WERTE3_0_clk_ctrl)
+      if (WERTE3_0_ena)
+	 WERTE3__q[0] <= WERTE3__d[0];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_63_ena_ctrl)
+	 WERTE2__q[63] <= WERTE2__d[63];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_62_ena_ctrl)
+	 WERTE2__q[62] <= WERTE2__d[62];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_61_ena_ctrl)
+	 WERTE2__q[61] <= WERTE2__d[61];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_60_ena_ctrl)
+	 WERTE2__q[60] <= WERTE2__d[60];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_59_ena_ctrl)
+	 WERTE2__q[59] <= WERTE2__d[59];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_58_ena_ctrl)
+	 WERTE2__q[58] <= WERTE2__d[58];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_57_ena_ctrl)
+	 WERTE2__q[57] <= WERTE2__d[57];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_56_ena_ctrl)
+	 WERTE2__q[56] <= WERTE2__d[56];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_55_ena_ctrl)
+	 WERTE2__q[55] <= WERTE2__d[55];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_54_ena_ctrl)
+	 WERTE2__q[54] <= WERTE2__d[54];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_53_ena_ctrl)
+	 WERTE2__q[53] <= WERTE2__d[53];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_52_ena_ctrl)
+	 WERTE2__q[52] <= WERTE2__d[52];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_51_ena_ctrl)
+	 WERTE2__q[51] <= WERTE2__d[51];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_50_ena_ctrl)
+	 WERTE2__q[50] <= WERTE2__d[50];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_49_ena_ctrl)
+	 WERTE2__q[49] <= WERTE2__d[49];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_48_ena_ctrl)
+	 WERTE2__q[48] <= WERTE2__d[48];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_47_ena_ctrl)
+	 WERTE2__q[47] <= WERTE2__d[47];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_46_ena_ctrl)
+	 WERTE2__q[46] <= WERTE2__d[46];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_45_ena_ctrl)
+	 WERTE2__q[45] <= WERTE2__d[45];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_44_ena_ctrl)
+	 WERTE2__q[44] <= WERTE2__d[44];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_43_ena_ctrl)
+	 WERTE2__q[43] <= WERTE2__d[43];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_42_ena_ctrl)
+	 WERTE2__q[42] <= WERTE2__d[42];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_41_ena_ctrl)
+	 WERTE2__q[41] <= WERTE2__d[41];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_40_ena_ctrl)
+	 WERTE2__q[40] <= WERTE2__d[40];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_39_ena_ctrl)
+	 WERTE2__q[39] <= WERTE2__d[39];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_38_ena_ctrl)
+	 WERTE2__q[38] <= WERTE2__d[38];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_37_ena_ctrl)
+	 WERTE2__q[37] <= WERTE2__d[37];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_36_ena_ctrl)
+	 WERTE2__q[36] <= WERTE2__d[36];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_35_ena_ctrl)
+	 WERTE2__q[35] <= WERTE2__d[35];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_34_ena_ctrl)
+	 WERTE2__q[34] <= WERTE2__d[34];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_33_ena_ctrl)
+	 WERTE2__q[33] <= WERTE2__d[33];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_32_ena_ctrl)
+	 WERTE2__q[32] <= WERTE2__d[32];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_31_ena_ctrl)
+	 WERTE2__q[31] <= WERTE2__d[31];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_30_ena_ctrl)
+	 WERTE2__q[30] <= WERTE2__d[30];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_29_ena_ctrl)
+	 WERTE2__q[29] <= WERTE2__d[29];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_28_ena_ctrl)
+	 WERTE2__q[28] <= WERTE2__d[28];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_27_ena_ctrl)
+	 WERTE2__q[27] <= WERTE2__d[27];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_26_ena_ctrl)
+	 WERTE2__q[26] <= WERTE2__d[26];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_25_ena_ctrl)
+	 WERTE2__q[25] <= WERTE2__d[25];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_24_ena_ctrl)
+	 WERTE2__q[24] <= WERTE2__d[24];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_23_ena_ctrl)
+	 WERTE2__q[23] <= WERTE2__d[23];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_22_ena_ctrl)
+	 WERTE2__q[22] <= WERTE2__d[22];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_21_ena_ctrl)
+	 WERTE2__q[21] <= WERTE2__d[21];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_20_ena_ctrl)
+	 WERTE2__q[20] <= WERTE2__d[20];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_19_ena_ctrl)
+	 WERTE2__q[19] <= WERTE2__d[19];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_18_ena_ctrl)
+	 WERTE2__q[18] <= WERTE2__d[18];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_17_ena_ctrl)
+	 WERTE2__q[17] <= WERTE2__d[17];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_16_ena_ctrl)
+	 WERTE2__q[16] <= WERTE2__d[16];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_15_ena_ctrl)
+	 WERTE2__q[15] <= WERTE2__d[15];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_14_ena_ctrl)
+	 WERTE2__q[14] <= WERTE2__d[14];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE2_13_ena)
+	 WERTE2__q[13] <= WERTE2__d[13];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_12_ena_ctrl)
+	 WERTE2__q[12] <= WERTE2__d[12];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_11_ena_ctrl)
+	 WERTE2__q[11] <= WERTE2__d[11];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_10_ena_ctrl)
+	 WERTE2__q[10] <= WERTE2__d[10];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE2_9_ena)
+	 WERTE2__q[9] <= WERTE2__d[9];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE2_8_ena)
+	 WERTE2__q[8] <= WERTE2__d[8];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE2_7_ena)
+	 WERTE2__q[7] <= WERTE2__d[7];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE2_6_ena)
+	 WERTE2__q[6] <= WERTE2__d[6];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_5_ena_ctrl)
+	 WERTE2__q[5] <= WERTE2__d[5];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE2_4_ena)
+	 WERTE2__q[4] <= WERTE2__d[4];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_3_ena_ctrl)
+	 WERTE2__q[3] <= WERTE2__d[3];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE2_2_ena)
+	 WERTE2__q[2] <= WERTE2__d[2];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE0_1_ena_ctrl)
+	 WERTE2__q[1] <= WERTE2__d[1];
+
+   always @(posedge WERTE2_0_clk_ctrl)
+      if (WERTE2_0_ena)
+	 WERTE2__q[0] <= WERTE2__d[0];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_63_ena_ctrl)
+	 WERTE1__q[63] <= WERTE1__d[63];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_62_ena_ctrl)
+	 WERTE1__q[62] <= WERTE1__d[62];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_61_ena_ctrl)
+	 WERTE1__q[61] <= WERTE1__d[61];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_60_ena_ctrl)
+	 WERTE1__q[60] <= WERTE1__d[60];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_59_ena_ctrl)
+	 WERTE1__q[59] <= WERTE1__d[59];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_58_ena_ctrl)
+	 WERTE1__q[58] <= WERTE1__d[58];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_57_ena_ctrl)
+	 WERTE1__q[57] <= WERTE1__d[57];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_56_ena_ctrl)
+	 WERTE1__q[56] <= WERTE1__d[56];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_55_ena_ctrl)
+	 WERTE1__q[55] <= WERTE1__d[55];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_54_ena_ctrl)
+	 WERTE1__q[54] <= WERTE1__d[54];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_53_ena_ctrl)
+	 WERTE1__q[53] <= WERTE1__d[53];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_52_ena_ctrl)
+	 WERTE1__q[52] <= WERTE1__d[52];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_51_ena_ctrl)
+	 WERTE1__q[51] <= WERTE1__d[51];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_50_ena_ctrl)
+	 WERTE1__q[50] <= WERTE1__d[50];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_49_ena_ctrl)
+	 WERTE1__q[49] <= WERTE1__d[49];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_48_ena_ctrl)
+	 WERTE1__q[48] <= WERTE1__d[48];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_47_ena_ctrl)
+	 WERTE1__q[47] <= WERTE1__d[47];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_46_ena_ctrl)
+	 WERTE1__q[46] <= WERTE1__d[46];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_45_ena_ctrl)
+	 WERTE1__q[45] <= WERTE1__d[45];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_44_ena_ctrl)
+	 WERTE1__q[44] <= WERTE1__d[44];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_43_ena_ctrl)
+	 WERTE1__q[43] <= WERTE1__d[43];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_42_ena_ctrl)
+	 WERTE1__q[42] <= WERTE1__d[42];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_41_ena_ctrl)
+	 WERTE1__q[41] <= WERTE1__d[41];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_40_ena_ctrl)
+	 WERTE1__q[40] <= WERTE1__d[40];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_39_ena_ctrl)
+	 WERTE1__q[39] <= WERTE1__d[39];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_38_ena_ctrl)
+	 WERTE1__q[38] <= WERTE1__d[38];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_37_ena_ctrl)
+	 WERTE1__q[37] <= WERTE1__d[37];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_36_ena_ctrl)
+	 WERTE1__q[36] <= WERTE1__d[36];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_35_ena_ctrl)
+	 WERTE1__q[35] <= WERTE1__d[35];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_34_ena_ctrl)
+	 WERTE1__q[34] <= WERTE1__d[34];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_33_ena_ctrl)
+	 WERTE1__q[33] <= WERTE1__d[33];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_32_ena_ctrl)
+	 WERTE1__q[32] <= WERTE1__d[32];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_31_ena_ctrl)
+	 WERTE1__q[31] <= WERTE1__d[31];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_30_ena_ctrl)
+	 WERTE1__q[30] <= WERTE1__d[30];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_29_ena_ctrl)
+	 WERTE1__q[29] <= WERTE1__d[29];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_28_ena_ctrl)
+	 WERTE1__q[28] <= WERTE1__d[28];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_27_ena_ctrl)
+	 WERTE1__q[27] <= WERTE1__d[27];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_26_ena_ctrl)
+	 WERTE1__q[26] <= WERTE1__d[26];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_25_ena_ctrl)
+	 WERTE1__q[25] <= WERTE1__d[25];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_24_ena_ctrl)
+	 WERTE1__q[24] <= WERTE1__d[24];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_23_ena_ctrl)
+	 WERTE1__q[23] <= WERTE1__d[23];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_22_ena_ctrl)
+	 WERTE1__q[22] <= WERTE1__d[22];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_21_ena_ctrl)
+	 WERTE1__q[21] <= WERTE1__d[21];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_20_ena_ctrl)
+	 WERTE1__q[20] <= WERTE1__d[20];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_19_ena_ctrl)
+	 WERTE1__q[19] <= WERTE1__d[19];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_18_ena_ctrl)
+	 WERTE1__q[18] <= WERTE1__d[18];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_17_ena_ctrl)
+	 WERTE1__q[17] <= WERTE1__d[17];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_16_ena_ctrl)
+	 WERTE1__q[16] <= WERTE1__d[16];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_15_ena_ctrl)
+	 WERTE1__q[15] <= WERTE1__d[15];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_14_ena_ctrl)
+	 WERTE1__q[14] <= WERTE1__d[14];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE1_13_ena)
+	 WERTE1__q[13] <= WERTE1__d[13];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_12_ena_ctrl)
+	 WERTE1__q[12] <= WERTE1__d[12];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_11_ena_ctrl)
+	 WERTE1__q[11] <= WERTE1__d[11];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_10_ena_ctrl)
+	 WERTE1__q[10] <= WERTE1__d[10];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE1_9_ena)
+	 WERTE1__q[9] <= WERTE1__d[9];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE1_8_ena)
+	 WERTE1__q[8] <= WERTE1__d[8];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE1_7_ena)
+	 WERTE1__q[7] <= WERTE1__d[7];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE1_6_ena)
+	 WERTE1__q[6] <= WERTE1__d[6];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_5_ena_ctrl)
+	 WERTE1__q[5] <= WERTE1__d[5];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE1_4_ena)
+	 WERTE1__q[4] <= WERTE1__d[4];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_3_ena_ctrl)
+	 WERTE1__q[3] <= WERTE1__d[3];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE1_2_ena)
+	 WERTE1__q[2] <= WERTE1__d[2];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE0_1_ena_ctrl)
+	 WERTE1__q[1] <= WERTE1__d[1];
+
+   always @(posedge WERTE1_0_clk_ctrl)
+      if (WERTE1_0_ena)
+	 WERTE1__q[0] <= WERTE1__d[0];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_63_ena_ctrl)
+	 WERTE0__q[63] <= WERTE0__d[63];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_62_ena_ctrl)
+	 WERTE0__q[62] <= WERTE0__d[62];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_61_ena_ctrl)
+	 WERTE0__q[61] <= WERTE0__d[61];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_60_ena_ctrl)
+	 WERTE0__q[60] <= WERTE0__d[60];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_59_ena_ctrl)
+	 WERTE0__q[59] <= WERTE0__d[59];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_58_ena_ctrl)
+	 WERTE0__q[58] <= WERTE0__d[58];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_57_ena_ctrl)
+	 WERTE0__q[57] <= WERTE0__d[57];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_56_ena_ctrl)
+	 WERTE0__q[56] <= WERTE0__d[56];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_55_ena_ctrl)
+	 WERTE0__q[55] <= WERTE0__d[55];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_54_ena_ctrl)
+	 WERTE0__q[54] <= WERTE0__d[54];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_53_ena_ctrl)
+	 WERTE0__q[53] <= WERTE0__d[53];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_52_ena_ctrl)
+	 WERTE0__q[52] <= WERTE0__d[52];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_51_ena_ctrl)
+	 WERTE0__q[51] <= WERTE0__d[51];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_50_ena_ctrl)
+	 WERTE0__q[50] <= WERTE0__d[50];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_49_ena_ctrl)
+	 WERTE0__q[49] <= WERTE0__d[49];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_48_ena_ctrl)
+	 WERTE0__q[48] <= WERTE0__d[48];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_47_ena_ctrl)
+	 WERTE0__q[47] <= WERTE0__d[47];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_46_ena_ctrl)
+	 WERTE0__q[46] <= WERTE0__d[46];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_45_ena_ctrl)
+	 WERTE0__q[45] <= WERTE0__d[45];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_44_ena_ctrl)
+	 WERTE0__q[44] <= WERTE0__d[44];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_43_ena_ctrl)
+	 WERTE0__q[43] <= WERTE0__d[43];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_42_ena_ctrl)
+	 WERTE0__q[42] <= WERTE0__d[42];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_41_ena_ctrl)
+	 WERTE0__q[41] <= WERTE0__d[41];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_40_ena_ctrl)
+	 WERTE0__q[40] <= WERTE0__d[40];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_39_ena_ctrl)
+	 WERTE0__q[39] <= WERTE0__d[39];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_38_ena_ctrl)
+	 WERTE0__q[38] <= WERTE0__d[38];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_37_ena_ctrl)
+	 WERTE0__q[37] <= WERTE0__d[37];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_36_ena_ctrl)
+	 WERTE0__q[36] <= WERTE0__d[36];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_35_ena_ctrl)
+	 WERTE0__q[35] <= WERTE0__d[35];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_34_ena_ctrl)
+	 WERTE0__q[34] <= WERTE0__d[34];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_33_ena_ctrl)
+	 WERTE0__q[33] <= WERTE0__d[33];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_32_ena_ctrl)
+	 WERTE0__q[32] <= WERTE0__d[32];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_31_ena_ctrl)
+	 WERTE0__q[31] <= WERTE0__d[31];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_30_ena_ctrl)
+	 WERTE0__q[30] <= WERTE0__d[30];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_29_ena_ctrl)
+	 WERTE0__q[29] <= WERTE0__d[29];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_28_ena_ctrl)
+	 WERTE0__q[28] <= WERTE0__d[28];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_27_ena_ctrl)
+	 WERTE0__q[27] <= WERTE0__d[27];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_26_ena_ctrl)
+	 WERTE0__q[26] <= WERTE0__d[26];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_25_ena_ctrl)
+	 WERTE0__q[25] <= WERTE0__d[25];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_24_ena_ctrl)
+	 WERTE0__q[24] <= WERTE0__d[24];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_23_ena_ctrl)
+	 WERTE0__q[23] <= WERTE0__d[23];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_22_ena_ctrl)
+	 WERTE0__q[22] <= WERTE0__d[22];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_21_ena_ctrl)
+	 WERTE0__q[21] <= WERTE0__d[21];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_20_ena_ctrl)
+	 WERTE0__q[20] <= WERTE0__d[20];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_19_ena_ctrl)
+	 WERTE0__q[19] <= WERTE0__d[19];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_18_ena_ctrl)
+	 WERTE0__q[18] <= WERTE0__d[18];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_17_ena_ctrl)
+	 WERTE0__q[17] <= WERTE0__d[17];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_16_ena_ctrl)
+	 WERTE0__q[16] <= WERTE0__d[16];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_15_ena_ctrl)
+	 WERTE0__q[15] <= WERTE0__d[15];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_14_ena_ctrl)
+	 WERTE0__q[14] <= WERTE0__d[14];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_13_ena)
+	 WERTE0__q[13] <= WERTE0__d[13];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_12_ena_ctrl)
+	 WERTE0__q[12] <= WERTE0__d[12];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_11_ena_ctrl)
+	 WERTE0__q[11] <= WERTE0__d[11];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_10_ena_ctrl)
+	 WERTE0__q[10] <= WERTE0__d[10];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_9_ena)
+	 WERTE0__q[9] <= WERTE0__d[9];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_8_ena)
+	 WERTE0__q[8] <= WERTE0__d[8];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_7_ena)
+	 WERTE0__q[7] <= WERTE0__d[7];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_6_ena)
+	 WERTE0__q[6] <= WERTE0__d[6];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_5_ena_ctrl)
+	 WERTE0__q[5] <= WERTE0__d[5];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_4_ena)
+	 WERTE0__q[4] <= WERTE0__d[4];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_3_ena_ctrl)
+	 WERTE0__q[3] <= WERTE0__d[3];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_2_ena)
+	 WERTE0__q[2] <= WERTE0__d[2];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_1_ena_ctrl)
+	 WERTE0__q[1] <= WERTE0__d[1];
+
+   always @(posedge WERTE0_0_clk_ctrl)
+      if (WERTE0_0_ena)
+	 WERTE0__q[0] <= WERTE0__d[0];
+
+   always @(posedge PIC_INT_SYNC0_clk_ctrl)
+      PIC_INT_SYNC_q <= PIC_INT_SYNC_d;
+
+// Start of original equations
+
+//  BYT SELECT
+//  HWORD
+//  HHBYT
+//  LONG UND LINE
+   assign FB_B[0] = (FB_SIZE1 & (!FB_SIZE0) & (!FB_ADR[1])) | ((!FB_SIZE1) &
+	 FB_SIZE0 & (!FB_ADR[1]) & (!FB_ADR[0])) | ((!FB_SIZE1) & (!FB_SIZE0))
+	 | (FB_SIZE1 & FB_SIZE0);
+
+//  HWORD
+//  HLBYT
+//  LONG UND LINE
+   assign FB_B[1] = (FB_SIZE1 & (!FB_SIZE0) & (!FB_ADR[1])) | ((!FB_SIZE1) &
+	 FB_SIZE0 & (!FB_ADR[1]) & FB_ADR[0]) | ((!FB_SIZE1) & (!FB_SIZE0)) |
+	 (FB_SIZE1 & FB_SIZE0);
+
+//  LWORD
+//  LHBYT
+//  LONG UND LINE
+   assign FB_B[2] = (FB_SIZE1 & (!FB_SIZE0) & FB_ADR[1]) | ((!FB_SIZE1) &
+	 FB_SIZE0 & FB_ADR[1] & (!FB_ADR[0])) | ((!FB_SIZE1) & (!FB_SIZE0)) |
+	 (FB_SIZE1 & FB_SIZE0);
+
+//  LWORD
+//  LLBYT
+//  LONG UND LINE
+   assign FB_B[3] = (FB_SIZE1 & (!FB_SIZE0) & FB_ADR[1]) | ((!FB_SIZE1) &
+	 FB_SIZE0 & FB_ADR[1] & FB_ADR[0]) | ((!FB_SIZE1) & (!FB_SIZE0)) |
+	 (FB_SIZE1 & FB_SIZE0);
+
+//  INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN
+   assign INT_CTR0_clk_ctrl = MAIN_CLK;
+
+//  $10000/4
+   assign INT_CTR_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h4000;
+   assign INT_CTR_d = FB_AD;
+   assign INT_CTR24_ena_ctrl = INT_CTR_CS & FB_B[0] & (!nFB_WR);
+   assign INT_CTR16_ena_ctrl = INT_CTR_CS & FB_B[1] & (!nFB_WR);
+   assign INT_CTR8_ena_ctrl = INT_CTR_CS & FB_B[2] & (!nFB_WR);
+   assign INT_CTR0_ena_ctrl = INT_CTR_CS & FB_B[3] & (!nFB_WR);
+
+//  INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
+   assign INT_ENA0_clk_ctrl = MAIN_CLK;
+
+//  $10004/4
+   assign INT_ENA_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h4001;
+   assign INT_ENA_d = FB_AD;
+   assign INT_ENA24_ena_ctrl = INT_ENA_CS & FB_B[0] & (!nFB_WR);
+   assign INT_ENA16_ena_ctrl = INT_ENA_CS & FB_B[1] & (!nFB_WR);
+   assign INT_ENA8_ena_ctrl = INT_ENA_CS & FB_B[2] & (!nFB_WR);
+   assign INT_ENA0_ena_ctrl = INT_ENA_CS & FB_B[3] & (!nFB_WR);
+
+//  INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR
+   assign INT_CLEAR0_clk_ctrl = MAIN_CLK;
+
+//  $10008/4
+   assign INT_CLEAR_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h4002;
+   assign INT_CLEAR_d[31:24] = FB_AD[31:24] & {8{INT_CLEAR_CS}} & {8{FB_B[0]}}
+	 & {8{!nFB_WR}};
+   assign INT_CLEAR_d[23:16] = FB_AD[23:16] & {8{INT_CLEAR_CS}} & {8{FB_B[1]}}
+	 & {8{!nFB_WR}};
+   assign INT_CLEAR_d[15:8] = FB_AD[15:8] & {8{INT_CLEAR_CS}} & {8{FB_B[2]}} &
+	 {8{!nFB_WR}};
+   assign INT_CLEAR_d[7:0] = FB_AD[7:0] & {8{INT_CLEAR_CS}} & {8{FB_B[3]}} &
+	 {8{!nFB_WR}};
+
+//  INTERRUPT LATCH REGISTER READ ONLY
+//  $1000C/4
+   assign INT_LATCH_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h4003;
+
+//  INTERRUPT
+   assign nIRQ[2] = !(HSYNC & INT_ENA_q[26]);
+   assign nIRQ[3] = !(INT_CTR_q[0] & INT_ENA_q[27]);
+   assign nIRQ[4] = !(VSYNC & INT_ENA_q[28]);
+   assign nIRQ[5] = INT_LATCH_q == 32'h0 & INT_ENA_q[29];
+   assign nIRQ[6] = !((!nMFP_INT) & INT_ENA_q[30]);
+   assign nIRQ[7] = !(PSEUDO_BUS_ERROR & INT_ENA_q[31]);
+
+//  SCC
+//  VME
+//  PADDLE
+//  PADDLE
+//  PADDLE
+//  MFP2
+//  MFP2
+//  MFP2
+//  MFP2
+//  TT SCSI
+//  ST UHR
+//  ST UHR
+//  DMA SOUND
+//  DMA SOUND
+//  DMA SOUND
+   assign PSEUDO_BUS_ERROR = (!nFB_CS1) & (FB_ADR[19:4] == 16'hF8C8 |
+	 FB_ADR[19:4] == 16'hF8E0 | FB_ADR[19:4] == 16'hF920 | FB_ADR[19:4] ==
+	 16'hF921 | FB_ADR[19:4] == 16'hF922 | FB_ADR[19:4] == 16'hFFA8 |
+	 FB_ADR[19:4] == 16'hFFA9 | FB_ADR[19:4] == 16'hFFAA | FB_ADR[19:4] ==
+	 16'hFFA8 | FB_ADR[19:8] == 12'b1111_1000_0111 | FB_ADR[19:4] ==
+	 16'hFFC2 | FB_ADR[19:4] == 16'hFFC3 | FB_ADR[19:4] == 16'hF890 |
+	 FB_ADR[19:4] == 16'hF891 | FB_ADR[19:4] == 16'hF892);
+
+//  IF VIDEO ADR CHANGE
+//  WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
+   assign TIN0 = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C100 & (!nFB_WR);
+
+//  INTERRUPT LATCH
+   assign INT_LATCH_d = 32'hFFFF_FFFF;
+   assign INT_LATCH0_clk_1 = PIC_INT & INT_ENA_q[0];
+   assign INT_LATCH1_clk_1 = E0_INT & INT_ENA_q[1];
+   assign INT_LATCH2_clk_1 = DVI_INT & INT_ENA_q[2];
+   assign INT_LATCH3_clk_1 = (!nPCI_INTA) & INT_ENA_q[3];
+   assign INT_LATCH4_clk_1 = (!nPCI_INTB) & INT_ENA_q[4];
+   assign INT_LATCH5_clk_1 = (!nPCI_INTC) & INT_ENA_q[5];
+   assign INT_LATCH6_clk_1 = (!nPCI_INTD) & INT_ENA_q[6];
+   assign INT_LATCH7_clk_1 = DSP_INT & INT_ENA_q[7];
+   assign INT_LATCH8_clk_1 = VSYNC & INT_ENA_q[8];
+   assign INT_LATCH9_clk_1 = HSYNC & INT_ENA_q[9];
+
+//  INTERRUPT CLEAR
+   assign {INT_LATCH31_clrn, INT_LATCH30_clrn, INT_LATCH29_clrn,
+	 INT_LATCH28_clrn, INT_LATCH27_clrn, INT_LATCH26_clrn,
+	 INT_LATCH25_clrn, INT_LATCH24_clrn, INT_LATCH23_clrn,
+	 INT_LATCH22_clrn, INT_LATCH21_clrn, INT_LATCH20_clrn,
+	 INT_LATCH19_clrn, INT_LATCH18_clrn, INT_LATCH17_clrn,
+	 INT_LATCH16_clrn, INT_LATCH15_clrn, INT_LATCH14_clrn,
+	 INT_LATCH13_clrn, INT_LATCH12_clrn, INT_LATCH11_clrn,
+	 INT_LATCH10_clrn, INT_LATCH9_clrn, INT_LATCH8_clrn, INT_LATCH7_clrn,
+	 INT_LATCH6_clrn, INT_LATCH5_clrn, INT_LATCH4_clrn, INT_LATCH3_clrn,
+	 INT_LATCH2_clrn, INT_LATCH1_clrn, INT_LATCH0_clrn} = ~INT_CLEAR_q;
+
+//  INT_IN
+   assign INT_IN[0] = PIC_INT;
+   assign INT_IN[1] = E0_INT;
+   assign INT_IN[2] = DVI_INT;
+   assign INT_IN[3] = !nPCI_INTA;
+   assign INT_IN[4] = !nPCI_INTB;
+   assign INT_IN[5] = !nPCI_INTC;
+   assign INT_IN[6] = !nPCI_INTD;
+   assign INT_IN[7] = DSP_INT;
+   assign INT_IN[8] = VSYNC;
+   assign INT_IN[9] = HSYNC;
+   assign INT_IN[25:10] = 16'h0;
+   assign INT_IN[26] = HSYNC;
+   assign INT_IN[27] = INT_CTR_q[0];
+   assign INT_IN[28] = VSYNC;
+   assign INT_IN[29] = INT_LATCH_q != 32'h0;
+   assign INT_IN[30] = !nMFP_INT;
+   assign INT_IN[31] = DMA_DRQ;
+
+// ***************************************************************************************
+//  ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE
+   assign ACP_CONF0_clk_ctrl = MAIN_CLK;
+
+//  $4'0000/4
+   assign ACP_CONF_CS = (!nFB_CS2) & FB_ADR[27:2] == 26'h1_0000;
+   assign ACP_CONF_d = FB_AD;
+   assign ACP_CONF24_ena_ctrl = ACP_CONF_CS & FB_B[0] & (!nFB_WR);
+   assign ACP_CONF16_ena_ctrl = ACP_CONF_CS & FB_B[1] & (!nFB_WR);
+   assign ACP_CONF8_ena_ctrl = ACP_CONF_CS & FB_B[2] & (!nFB_WR);
+   assign ACP_CONF0_ena_ctrl = ACP_CONF_CS & FB_B[3] & (!nFB_WR);
+
+// ***************************************************************************************
+// ------------------------------------------------------------
+//  C1287   0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR
+// --------------------------------------------------------
+   assign RTC_ADR0_clk_ctrl = MAIN_CLK;
+   assign RTC_ADR_d = FB_AD[21:16];
+
+//  FFFF8961
+   assign UHR_AS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C4B0 & FB_B[1];
+
+//  FFFF8963
+   assign UHR_DS = (!nFB_CS1) & FB_ADR[19:1] == 19'h7_C4B1 & FB_B[3];
+   assign RTC_ADR0_ena_ctrl = UHR_AS & (!nFB_WR);
+   assign WERTE7_0_clk_ctrl = MAIN_CLK;
+   assign WERTE6_0_clk_ctrl = MAIN_CLK;
+   assign WERTE5_0_clk_ctrl = MAIN_CLK;
+   assign WERTE4_0_clk_ctrl = MAIN_CLK;
+   assign WERTE3_0_clk_ctrl = MAIN_CLK;
+   assign WERTE2_0_clk_ctrl = MAIN_CLK;
+   assign WERTE1_0_clk_ctrl = MAIN_CLK;
+   assign WERTE0_0_clk_ctrl = MAIN_CLK;
+   assign {WERTE7_0_d_1, WERTE6_0_d_1, WERTE5_0_d_1, WERTE4_0_d_1,
+	 WERTE3_0_d_1, WERTE2_0_d_1, WERTE1_0_d_1, WERTE0_0_d_1} = FB_AD[23:16]
+	 & {8{RTC_ADR_q == 6'b00_0000}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7__d[1], WERTE6__d[1], WERTE5__d[1], WERTE4__d[1],
+	 WERTE3__d[1], WERTE2__d[1], WERTE1__d[1], WERTE0__d[1]} =
+	 FB_AD[23:16];
+   assign {WERTE7_2_d_1, WERTE6_2_d_1, WERTE5_2_d_1, WERTE4_2_d_1,
+	 WERTE3_2_d_1, WERTE2_2_d_1, WERTE1_2_d_1, WERTE0_2_d_1} = FB_AD[23:16]
+	 & {8{RTC_ADR_q == 6'b00_0010}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7__d[3], WERTE6__d[3], WERTE5__d[3], WERTE4__d[3],
+	 WERTE3__d[3], WERTE2__d[3], WERTE1__d[3], WERTE0__d[3]} =
+	 FB_AD[23:16];
+   assign {WERTE7_4_d_1, WERTE6_4_d_1, WERTE5_4_d_1, WERTE4_4_d_1,
+	 WERTE3_4_d_1, WERTE2_4_d_1, WERTE1_4_d_1, WERTE0_4_d_1} = FB_AD[23:16]
+	 & {8{RTC_ADR_q == 6'b00_0100}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7__d[5], WERTE6__d[5], WERTE5__d[5], WERTE4__d[5],
+	 WERTE3__d[5], WERTE2__d[5], WERTE1__d[5], WERTE0__d[5]} =
+	 FB_AD[23:16];
+   assign {WERTE7_6_d_1, WERTE6_6_d_1, WERTE5_6_d_1, WERTE4_6_d_1,
+	 WERTE3_6_d_1, WERTE2_6_d_1, WERTE1_6_d_1, WERTE0_6_d_1} = FB_AD[23:16]
+	 & {8{RTC_ADR_q == 6'b00_0110}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7_7_d_1, WERTE6_7_d_1, WERTE5_7_d_1, WERTE4_7_d_1,
+	 WERTE3_7_d_1, WERTE2_7_d_1, WERTE1_7_d_1, WERTE0_7_d_1} = FB_AD[23:16]
+	 & {8{RTC_ADR_q == 6'b00_0111}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7_8_d_1, WERTE6_8_d_1, WERTE5_8_d_1, WERTE4_8_d_1,
+	 WERTE3_8_d_1, WERTE2_8_d_1, WERTE1_8_d_1, WERTE0_8_d_1} = FB_AD[23:16]
+	 & {8{RTC_ADR_q == 6'b00_1000}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7_9_d_1, WERTE6_9_d_1, WERTE5_9_d_1, WERTE4_9_d_1,
+	 WERTE3_9_d_1, WERTE2_9_d_1, WERTE1_9_d_1, WERTE0_9_d_1} = FB_AD[23:16]
+	 & {8{RTC_ADR_q == 6'b00_1001}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7__d[10], WERTE6__d[10], WERTE5__d[10], WERTE4__d[10],
+	 WERTE3__d[10], WERTE2__d[10], WERTE1__d[10], WERTE0__d[10]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[11], WERTE6__d[11], WERTE5__d[11], WERTE4__d[11],
+	 WERTE3__d[11], WERTE2_11_d_1, WERTE1_11_d_1, WERTE0_11_d_1} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[12], WERTE6__d[12], WERTE5__d[12], WERTE4__d[12],
+	 WERTE3__d[12], WERTE2__d[12], WERTE1__d[12], WERTE0__d[12]} =
+	 FB_AD[23:16];
+   assign {WERTE7_13_d_1, WERTE6__d[13], WERTE5__d[13], WERTE4__d[13],
+	 WERTE3__d[13], WERTE2__d[13], WERTE1__d[13], WERTE0_13_d_1} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[14], WERTE6__d[14], WERTE5__d[14], WERTE4__d[14],
+	 WERTE3__d[14], WERTE2__d[14], WERTE1__d[14], WERTE0__d[14]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[15], WERTE6__d[15], WERTE5__d[15], WERTE4__d[15],
+	 WERTE3__d[15], WERTE2__d[15], WERTE1__d[15], WERTE0__d[15]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[16], WERTE6__d[16], WERTE5__d[16], WERTE4__d[16],
+	 WERTE3__d[16], WERTE2__d[16], WERTE1__d[16], WERTE0__d[16]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[17], WERTE6__d[17], WERTE5__d[17], WERTE4__d[17],
+	 WERTE3__d[17], WERTE2__d[17], WERTE1__d[17], WERTE0__d[17]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[18], WERTE6__d[18], WERTE5__d[18], WERTE4__d[18],
+	 WERTE3__d[18], WERTE2__d[18], WERTE1__d[18], WERTE0__d[18]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[19], WERTE6__d[19], WERTE5__d[19], WERTE4__d[19],
+	 WERTE3__d[19], WERTE2__d[19], WERTE1__d[19], WERTE0__d[19]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[20], WERTE6__d[20], WERTE5__d[20], WERTE4__d[20],
+	 WERTE3__d[20], WERTE2__d[20], WERTE1__d[20], WERTE0__d[20]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[21], WERTE6__d[21], WERTE5__d[21], WERTE4__d[21],
+	 WERTE3__d[21], WERTE2__d[21], WERTE1__d[21], WERTE0__d[21]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[22], WERTE6__d[22], WERTE5__d[22], WERTE4__d[22],
+	 WERTE3__d[22], WERTE2__d[22], WERTE1__d[22], WERTE0__d[22]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[23], WERTE6__d[23], WERTE5__d[23], WERTE4__d[23],
+	 WERTE3__d[23], WERTE2__d[23], WERTE1__d[23], WERTE0__d[23]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[24], WERTE6__d[24], WERTE5__d[24], WERTE4__d[24],
+	 WERTE3__d[24], WERTE2__d[24], WERTE1__d[24], WERTE0__d[24]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[25], WERTE6__d[25], WERTE5__d[25], WERTE4__d[25],
+	 WERTE3__d[25], WERTE2__d[25], WERTE1__d[25], WERTE0__d[25]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[26], WERTE6__d[26], WERTE5__d[26], WERTE4__d[26],
+	 WERTE3__d[26], WERTE2__d[26], WERTE1__d[26], WERTE0__d[26]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[27], WERTE6__d[27], WERTE5__d[27], WERTE4__d[27],
+	 WERTE3__d[27], WERTE2__d[27], WERTE1__d[27], WERTE0__d[27]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[28], WERTE6__d[28], WERTE5__d[28], WERTE4__d[28],
+	 WERTE3__d[28], WERTE2__d[28], WERTE1__d[28], WERTE0__d[28]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[29], WERTE6__d[29], WERTE5__d[29], WERTE4__d[29],
+	 WERTE3__d[29], WERTE2__d[29], WERTE1__d[29], WERTE0__d[29]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[30], WERTE6__d[30], WERTE5__d[30], WERTE4__d[30],
+	 WERTE3__d[30], WERTE2__d[30], WERTE1__d[30], WERTE0__d[30]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[31], WERTE6__d[31], WERTE5__d[31], WERTE4__d[31],
+	 WERTE3__d[31], WERTE2__d[31], WERTE1__d[31], WERTE0__d[31]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[32], WERTE6__d[32], WERTE5__d[32], WERTE4__d[32],
+	 WERTE3__d[32], WERTE2__d[32], WERTE1__d[32], WERTE0__d[32]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[33], WERTE6__d[33], WERTE5__d[33], WERTE4__d[33],
+	 WERTE3__d[33], WERTE2__d[33], WERTE1__d[33], WERTE0__d[33]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[34], WERTE6__d[34], WERTE5__d[34], WERTE4__d[34],
+	 WERTE3__d[34], WERTE2__d[34], WERTE1__d[34], WERTE0__d[34]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[35], WERTE6__d[35], WERTE5__d[35], WERTE4__d[35],
+	 WERTE3__d[35], WERTE2__d[35], WERTE1__d[35], WERTE0__d[35]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[36], WERTE6__d[36], WERTE5__d[36], WERTE4__d[36],
+	 WERTE3__d[36], WERTE2__d[36], WERTE1__d[36], WERTE0__d[36]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[37], WERTE6__d[37], WERTE5__d[37], WERTE4__d[37],
+	 WERTE3__d[37], WERTE2__d[37], WERTE1__d[37], WERTE0__d[37]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[38], WERTE6__d[38], WERTE5__d[38], WERTE4__d[38],
+	 WERTE3__d[38], WERTE2__d[38], WERTE1__d[38], WERTE0__d[38]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[39], WERTE6__d[39], WERTE5__d[39], WERTE4__d[39],
+	 WERTE3__d[39], WERTE2__d[39], WERTE1__d[39], WERTE0__d[39]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[40], WERTE6__d[40], WERTE5__d[40], WERTE4__d[40],
+	 WERTE3__d[40], WERTE2__d[40], WERTE1__d[40], WERTE0__d[40]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[41], WERTE6__d[41], WERTE5__d[41], WERTE4__d[41],
+	 WERTE3__d[41], WERTE2__d[41], WERTE1__d[41], WERTE0__d[41]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[42], WERTE6__d[42], WERTE5__d[42], WERTE4__d[42],
+	 WERTE3__d[42], WERTE2__d[42], WERTE1__d[42], WERTE0__d[42]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[43], WERTE6__d[43], WERTE5__d[43], WERTE4__d[43],
+	 WERTE3__d[43], WERTE2__d[43], WERTE1__d[43], WERTE0__d[43]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[44], WERTE6__d[44], WERTE5__d[44], WERTE4__d[44],
+	 WERTE3__d[44], WERTE2__d[44], WERTE1__d[44], WERTE0__d[44]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[45], WERTE6__d[45], WERTE5__d[45], WERTE4__d[45],
+	 WERTE3__d[45], WERTE2__d[45], WERTE1__d[45], WERTE0__d[45]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[46], WERTE6__d[46], WERTE5__d[46], WERTE4__d[46],
+	 WERTE3__d[46], WERTE2__d[46], WERTE1__d[46], WERTE0__d[46]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[47], WERTE6__d[47], WERTE5__d[47], WERTE4__d[47],
+	 WERTE3__d[47], WERTE2__d[47], WERTE1__d[47], WERTE0__d[47]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[48], WERTE6__d[48], WERTE5__d[48], WERTE4__d[48],
+	 WERTE3__d[48], WERTE2__d[48], WERTE1__d[48], WERTE0__d[48]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[49], WERTE6__d[49], WERTE5__d[49], WERTE4__d[49],
+	 WERTE3__d[49], WERTE2__d[49], WERTE1__d[49], WERTE0__d[49]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[50], WERTE6__d[50], WERTE5__d[50], WERTE4__d[50],
+	 WERTE3__d[50], WERTE2__d[50], WERTE1__d[50], WERTE0__d[50]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[51], WERTE6__d[51], WERTE5__d[51], WERTE4__d[51],
+	 WERTE3__d[51], WERTE2__d[51], WERTE1__d[51], WERTE0__d[51]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[52], WERTE6__d[52], WERTE5__d[52], WERTE4__d[52],
+	 WERTE3__d[52], WERTE2__d[52], WERTE1__d[52], WERTE0__d[52]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[53], WERTE6__d[53], WERTE5__d[53], WERTE4__d[53],
+	 WERTE3__d[53], WERTE2__d[53], WERTE1__d[53], WERTE0__d[53]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[54], WERTE6__d[54], WERTE5__d[54], WERTE4__d[54],
+	 WERTE3__d[54], WERTE2__d[54], WERTE1__d[54], WERTE0__d[54]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[55], WERTE6__d[55], WERTE5__d[55], WERTE4__d[55],
+	 WERTE3__d[55], WERTE2__d[55], WERTE1__d[55], WERTE0__d[55]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[56], WERTE6__d[56], WERTE5__d[56], WERTE4__d[56],
+	 WERTE3__d[56], WERTE2__d[56], WERTE1__d[56], WERTE0__d[56]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[57], WERTE6__d[57], WERTE5__d[57], WERTE4__d[57],
+	 WERTE3__d[57], WERTE2__d[57], WERTE1__d[57], WERTE0__d[57]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[58], WERTE6__d[58], WERTE5__d[58], WERTE4__d[58],
+	 WERTE3__d[58], WERTE2__d[58], WERTE1__d[58], WERTE0__d[58]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[59], WERTE6__d[59], WERTE5__d[59], WERTE4__d[59],
+	 WERTE3__d[59], WERTE2__d[59], WERTE1__d[59], WERTE0__d[59]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[60], WERTE6__d[60], WERTE5__d[60], WERTE4__d[60],
+	 WERTE3__d[60], WERTE2__d[60], WERTE1__d[60], WERTE0__d[60]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[61], WERTE6__d[61], WERTE5__d[61], WERTE4__d[61],
+	 WERTE3__d[61], WERTE2__d[61], WERTE1__d[61], WERTE0__d[61]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[62], WERTE6__d[62], WERTE5__d[62], WERTE4__d[62],
+	 WERTE3__d[62], WERTE2__d[62], WERTE1__d[62], WERTE0__d[62]} =
+	 FB_AD[23:16];
+   assign {WERTE7__d[63], WERTE6__d[63], WERTE5__d[63], WERTE4__d[63],
+	 WERTE3__d[63], WERTE2__d[63], WERTE1__d[63], WERTE0__d[63]} =
+	 FB_AD[23:16];
+   assign {WERTE7_0_ena_1, WERTE6_0_ena_1, WERTE5_0_ena_1, WERTE4_0_ena_1,
+	 WERTE3_0_ena_1, WERTE2_0_ena_1, WERTE1_0_ena_1, WERTE0_0_ena_1} =
+	 {8{RTC_ADR_q == 6'b00_0000}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign WERTE0_1_ena_ctrl = RTC_ADR_q == 6'b00_0001 & UHR_DS & (!nFB_WR);
+   assign {WERTE7_2_ena_1, WERTE6_2_ena_1, WERTE5_2_ena_1, WERTE4_2_ena_1,
+	 WERTE3_2_ena_1, WERTE2_2_ena_1, WERTE1_2_ena_1, WERTE0_2_ena_1} =
+	 {8{RTC_ADR_q == 6'b00_0010}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign WERTE0_3_ena_ctrl = RTC_ADR_q == 6'b00_0011 & UHR_DS & (!nFB_WR);
+   assign {WERTE7_4_ena_1, WERTE6_4_ena_1, WERTE5_4_ena_1, WERTE4_4_ena_1,
+	 WERTE3_4_ena_1, WERTE2_4_ena_1, WERTE1_4_ena_1, WERTE0_4_ena_1} =
+	 {8{RTC_ADR_q == 6'b00_0100}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign WERTE0_5_ena_ctrl = RTC_ADR_q == 6'b00_0101 & UHR_DS & (!nFB_WR);
+   assign {WERTE7_6_ena_1, WERTE6_6_ena_1, WERTE5_6_ena_1, WERTE4_6_ena_1,
+	 WERTE3_6_ena_1, WERTE2_6_ena_1, WERTE1_6_ena_1, WERTE0_6_ena_1} =
+	 {8{RTC_ADR_q == 6'b00_0110}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7_7_ena_1, WERTE6_7_ena_1, WERTE5_7_ena_1, WERTE4_7_ena_1,
+	 WERTE3_7_ena_1, WERTE2_7_ena_1, WERTE1_7_ena_1, WERTE0_7_ena_1} =
+	 {8{RTC_ADR_q == 6'b00_0111}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7_8_ena_1, WERTE6_8_ena_1, WERTE5_8_ena_1, WERTE4_8_ena_1,
+	 WERTE3_8_ena_1, WERTE2_8_ena_1, WERTE1_8_ena_1, WERTE0_8_ena_1} =
+	 {8{RTC_ADR_q == 6'b00_1000}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign {WERTE7_9_ena_1, WERTE6_9_ena_1, WERTE5_9_ena_1, WERTE4_9_ena_1,
+	 WERTE3_9_ena_1, WERTE2_9_ena_1, WERTE1_9_ena_1, WERTE0_9_ena_1} =
+	 {8{RTC_ADR_q == 6'b00_1001}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign WERTE0_10_ena_ctrl = RTC_ADR_q == 6'b00_1010 & UHR_DS & (!nFB_WR);
+   assign WERTE0_11_ena_ctrl = RTC_ADR_q == 6'b00_1011 & UHR_DS & (!nFB_WR);
+   assign WERTE0_12_ena_ctrl = RTC_ADR_q == 6'b00_1100 & UHR_DS & (!nFB_WR);
+   assign {WERTE7_13_ena, WERTE6_13_ena, WERTE5_13_ena, WERTE4_13_ena,
+	 WERTE3_13_ena, WERTE2_13_ena, WERTE1_13_ena, WERTE0_13_ena_1} =
+	 {8{RTC_ADR_q == 6'b00_1101}} & {8{UHR_DS}} & {8{!nFB_WR}};
+   assign WERTE0_14_ena_ctrl = RTC_ADR_q == 6'b00_1110 & UHR_DS & (!nFB_WR);
+   assign WERTE0_15_ena_ctrl = RTC_ADR_q == 6'b00_1111 & UHR_DS & (!nFB_WR);
+   assign WERTE0_16_ena_ctrl = RTC_ADR_q == 6'b01_0000 & UHR_DS & (!nFB_WR);
+   assign WERTE0_17_ena_ctrl = RTC_ADR_q == 6'b01_0001 & UHR_DS & (!nFB_WR);
+   assign WERTE0_18_ena_ctrl = RTC_ADR_q == 6'b01_0010 & UHR_DS & (!nFB_WR);
+   assign WERTE0_19_ena_ctrl = RTC_ADR_q == 6'b01_0011 & UHR_DS & (!nFB_WR);
+   assign WERTE0_20_ena_ctrl = RTC_ADR_q == 6'b01_0100 & UHR_DS & (!nFB_WR);
+   assign WERTE0_21_ena_ctrl = RTC_ADR_q == 6'b01_0101 & UHR_DS & (!nFB_WR);
+   assign WERTE0_22_ena_ctrl = RTC_ADR_q == 6'b01_0110 & UHR_DS & (!nFB_WR);
+   assign WERTE0_23_ena_ctrl = RTC_ADR_q == 6'b01_0111 & UHR_DS & (!nFB_WR);
+   assign WERTE0_24_ena_ctrl = RTC_ADR_q == 6'b01_1000 & UHR_DS & (!nFB_WR);
+   assign WERTE0_25_ena_ctrl = RTC_ADR_q == 6'b01_1001 & UHR_DS & (!nFB_WR);
+   assign WERTE0_26_ena_ctrl = RTC_ADR_q == 6'b01_1010 & UHR_DS & (!nFB_WR);
+   assign WERTE0_27_ena_ctrl = RTC_ADR_q == 6'b01_1011 & UHR_DS & (!nFB_WR);
+   assign WERTE0_28_ena_ctrl = RTC_ADR_q == 6'b01_1100 & UHR_DS & (!nFB_WR);
+   assign WERTE0_29_ena_ctrl = RTC_ADR_q == 6'b01_1101 & UHR_DS & (!nFB_WR);
+   assign WERTE0_30_ena_ctrl = RTC_ADR_q == 6'b01_1110 & UHR_DS & (!nFB_WR);
+   assign WERTE0_31_ena_ctrl = RTC_ADR_q == 6'b01_1111 & UHR_DS & (!nFB_WR);
+   assign WERTE0_32_ena_ctrl = RTC_ADR_q == 6'b10_0000 & UHR_DS & (!nFB_WR);
+   assign WERTE0_33_ena_ctrl = RTC_ADR_q == 6'b10_0001 & UHR_DS & (!nFB_WR);
+   assign WERTE0_34_ena_ctrl = RTC_ADR_q == 6'b10_0010 & UHR_DS & (!nFB_WR);
+   assign WERTE0_35_ena_ctrl = RTC_ADR_q == 6'b10_0011 & UHR_DS & (!nFB_WR);
+   assign WERTE0_36_ena_ctrl = RTC_ADR_q == 6'b10_0100 & UHR_DS & (!nFB_WR);
+   assign WERTE0_37_ena_ctrl = RTC_ADR_q == 6'b10_0101 & UHR_DS & (!nFB_WR);
+   assign WERTE0_38_ena_ctrl = RTC_ADR_q == 6'b10_0110 & UHR_DS & (!nFB_WR);
+   assign WERTE0_39_ena_ctrl = RTC_ADR_q == 6'b10_0111 & UHR_DS & (!nFB_WR);
+   assign WERTE0_40_ena_ctrl = RTC_ADR_q == 6'b10_1000 & UHR_DS & (!nFB_WR);
+   assign WERTE0_41_ena_ctrl = RTC_ADR_q == 6'b10_1001 & UHR_DS & (!nFB_WR);
+   assign WERTE0_42_ena_ctrl = RTC_ADR_q == 6'b10_1010 & UHR_DS & (!nFB_WR);
+   assign WERTE0_43_ena_ctrl = RTC_ADR_q == 6'b10_1011 & UHR_DS & (!nFB_WR);
+   assign WERTE0_44_ena_ctrl = RTC_ADR_q == 6'b10_1100 & UHR_DS & (!nFB_WR);
+   assign WERTE0_45_ena_ctrl = RTC_ADR_q == 6'b10_1101 & UHR_DS & (!nFB_WR);
+   assign WERTE0_46_ena_ctrl = RTC_ADR_q == 6'b10_1110 & UHR_DS & (!nFB_WR);
+   assign WERTE0_47_ena_ctrl = RTC_ADR_q == 6'b10_1111 & UHR_DS & (!nFB_WR);
+   assign WERTE0_48_ena_ctrl = RTC_ADR_q == 6'b11_0000 & UHR_DS & (!nFB_WR);
+   assign WERTE0_49_ena_ctrl = RTC_ADR_q == 6'b11_0001 & UHR_DS & (!nFB_WR);
+   assign WERTE0_50_ena_ctrl = RTC_ADR_q == 6'b11_0010 & UHR_DS & (!nFB_WR);
+   assign WERTE0_51_ena_ctrl = RTC_ADR_q == 6'b11_0011 & UHR_DS & (!nFB_WR);
+   assign WERTE0_52_ena_ctrl = RTC_ADR_q == 6'b11_0100 & UHR_DS & (!nFB_WR);
+   assign WERTE0_53_ena_ctrl = RTC_ADR_q == 6'b11_0101 & UHR_DS & (!nFB_WR);
+   assign WERTE0_54_ena_ctrl = RTC_ADR_q == 6'b11_0110 & UHR_DS & (!nFB_WR);
+   assign WERTE0_55_ena_ctrl = RTC_ADR_q == 6'b11_0111 & UHR_DS & (!nFB_WR);
+   assign WERTE0_56_ena_ctrl = RTC_ADR_q == 6'b11_1000 & UHR_DS & (!nFB_WR);
+   assign WERTE0_57_ena_ctrl = RTC_ADR_q == 6'b11_1001 & UHR_DS & (!nFB_WR);
+   assign WERTE0_58_ena_ctrl = RTC_ADR_q == 6'b11_1010 & UHR_DS & (!nFB_WR);
+   assign WERTE0_59_ena_ctrl = RTC_ADR_q == 6'b11_1011 & UHR_DS & (!nFB_WR);
+   assign WERTE0_60_ena_ctrl = RTC_ADR_q == 6'b11_1100 & UHR_DS & (!nFB_WR);
+   assign WERTE0_61_ena_ctrl = RTC_ADR_q == 6'b11_1101 & UHR_DS & (!nFB_WR);
+   assign WERTE0_62_ena_ctrl = RTC_ADR_q == 6'b11_1110 & UHR_DS & (!nFB_WR);
+   assign WERTE0_63_ena_ctrl = RTC_ADR_q == 6'b11_1111 & UHR_DS & (!nFB_WR);
+   assign PIC_INT_SYNC0_clk_ctrl = MAIN_CLK;
+   assign PIC_INT_SYNC_d[0] = PIC_INT;
+   assign PIC_INT_SYNC_d[1] = PIC_INT_SYNC_q[0];
+   assign PIC_INT_SYNC_d[2] = (!PIC_INT_SYNC_q[1]) & PIC_INT_SYNC_q[0];
+   assign UPDATE_ON_1 = !WERTE7__q[11];
+
+//  KEIN UIP
+   assign WERTE6_10_clrn = gnd;
+
+//  UPDATE ON OFF
+   assign UPDATE_ON_2 = !WERTE7__q[11];
+
+//  IMMER BINARY
+   assign WERTE2_11_d_2 = vcc;
+
+//  IMMER 24H FORMAT
+   assign WERTE1_11_d_2 = vcc;
+
+//  IMMER SOMMERZEITKORREKTUR
+   assign WERTE0_11_d_2 = vcc;
+
+//  IMMER RICHTIG
+   assign WERTE7_13_d_2 = vcc;
+
+//  SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG)
+// LETZTER SONNTAG IM APRIL
+   assign SOMMERZEIT = {WERTE7__q[6], WERTE6__q[6], WERTE5__q[6], WERTE4__q[6],
+	 WERTE3__q[6], WERTE2__q[6], WERTE1__q[6], WERTE0__q[6]} ==
+	 8'b0000_0001 & {WERTE7__q[4], WERTE6__q[4], WERTE5__q[4],
+	 WERTE4__q[4], WERTE3__q[4], WERTE2__q[4], WERTE1__q[4], WERTE0__q[4]}
+	 == 8'b0000_0001 & {WERTE7__q[8], WERTE6__q[8], WERTE5__q[8],
+	 WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]}
+	 == 8'b0000_0100 & {WERTE7__q[7], WERTE6__q[7], WERTE5__q[7],
+	 WERTE4__q[7], WERTE3__q[7], WERTE2__q[7], WERTE1__q[7], WERTE0__q[7]}
+	 > 8'b0001_0111;
+   assign WERTE0_13_d_2 = SOMMERZEIT;
+   assign WERTE0_13_ena_2 = INC_STD & (SOMMERZEIT | WINTERZEIT);
+
+// LETZTER SONNTAG IM OKTOBER
+   assign WINTERZEIT = {WERTE7__q[6], WERTE6__q[6], WERTE5__q[6], WERTE4__q[6],
+	 WERTE3__q[6], WERTE2__q[6], WERTE1__q[6], WERTE0__q[6]} ==
+	 8'b0000_0001 & {WERTE7__q[4], WERTE6__q[4], WERTE5__q[4],
+	 WERTE4__q[4], WERTE3__q[4], WERTE2__q[4], WERTE1__q[4], WERTE0__q[4]}
+	 == 8'b0000_0001 & {WERTE7__q[8], WERTE6__q[8], WERTE5__q[8],
+	 WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]}
+	 == 8'b0000_1010 & {WERTE7__q[7], WERTE6__q[7], WERTE5__q[7],
+	 WERTE4__q[7], WERTE3__q[7], WERTE2__q[7], WERTE1__q[7], WERTE0__q[7]}
+	 > 8'b0001_1000 & WERTE0__q[13];
+
+//  ACHTELSEKUNDEN
+   assign ACHTELSEKUNDEN0_clk_ctrl = MAIN_CLK;
+   assign ACHTELSEKUNDEN_d = ACHTELSEKUNDEN_q + 3'b001;
+   assign ACHTELSEKUNDEN0_ena_ctrl = PIC_INT_SYNC_q[2] & UPDATE_ON;
+
+//  SEKUNDEN
+   assign INC_SEC = ACHTELSEKUNDEN_q == 3'b111 & PIC_INT_SYNC_q[2] & UPDATE_ON;
+
+//  SEKUNDEN ZÄHLEN BIS 59
+   assign {WERTE7_0_d_2, WERTE6_0_d_2, WERTE5_0_d_2, WERTE4_0_d_2,
+	 WERTE3_0_d_2, WERTE2_0_d_2, WERTE1_0_d_2, WERTE0_0_d_2} =
+	 ({WERTE7__q[0], WERTE6__q[0], WERTE5__q[0], WERTE4__q[0],
+	 WERTE3__q[0], WERTE2__q[0], WERTE1__q[0], WERTE0__q[0]} +
+	 8'b0000_0001) & {8{{WERTE7__q[0], WERTE6__q[0], WERTE5__q[0],
+	 WERTE4__q[0], WERTE3__q[0], WERTE2__q[0], WERTE1__q[0], WERTE0__q[0]}
+	 != 8'b0011_1011}} & (~({8{RTC_ADR_q == 6'b00_0000}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}));
+   assign {WERTE7_0_ena_2, WERTE6_0_ena_2, WERTE5_0_ena_2, WERTE4_0_ena_2,
+	 WERTE3_0_ena_2, WERTE2_0_ena_2, WERTE1_0_ena_2, WERTE0_0_ena_2} =
+	 {8{INC_SEC}} & (~({8{RTC_ADR_q == 6'b00_0000}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}));
+
+//  MINUTEN
+   assign INC_MIN = INC_SEC & {WERTE7__q[0], WERTE6__q[0], WERTE5__q[0],
+	 WERTE4__q[0], WERTE3__q[0], WERTE2__q[0], WERTE1__q[0], WERTE0__q[0]}
+	 == 8'b0011_1011;
+
+//  MINUTEN ZÄHLEN BIS 59
+   assign {WERTE7_2_d_2, WERTE6_2_d_2, WERTE5_2_d_2, WERTE4_2_d_2,
+	 WERTE3_2_d_2, WERTE2_2_d_2, WERTE1_2_d_2, WERTE0_2_d_2} =
+	 ({WERTE7__q[2], WERTE6__q[2], WERTE5__q[2], WERTE4__q[2],
+	 WERTE3__q[2], WERTE2__q[2], WERTE1__q[2], WERTE0__q[2]} +
+	 8'b0000_0001) & {8{{WERTE7__q[2], WERTE6__q[2], WERTE5__q[2],
+	 WERTE4__q[2], WERTE3__q[2], WERTE2__q[2], WERTE1__q[2], WERTE0__q[2]}
+	 != 8'b0011_1011}} & (~({8{RTC_ADR_q == 6'b00_0010}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}));
+   assign {WERTE7_2_ena_2, WERTE6_2_ena_2, WERTE5_2_ena_2, WERTE4_2_ena_2,
+	 WERTE3_2_ena_2, WERTE2_2_ena_2, WERTE1_2_ena_2, WERTE0_2_ena_2} =
+	 {8{INC_MIN}} & (~({8{RTC_ADR_q == 6'b00_0010}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}));
+
+//  STUNDEN
+   assign INC_STD = INC_MIN & {WERTE7__q[2], WERTE6__q[2], WERTE5__q[2],
+	 WERTE4__q[2], WERTE3__q[2], WERTE2__q[2], WERTE1__q[2], WERTE0__q[2]}
+	 == 8'b0011_1011;
+
+//  STUNDEN ZÄHLEN BIS 23
+   assign {WERTE7_4_d_2, WERTE6_4_d_2, WERTE5_4_d_2, WERTE4_4_d_2,
+	 WERTE3_4_d_2, WERTE2_4_d_2, WERTE1_4_d_2, WERTE0_4_d_2} =
+	 (({WERTE7__q[4], WERTE6__q[4], WERTE5__q[4], WERTE4__q[4],
+	 WERTE3__q[4], WERTE2__q[4], WERTE1__q[4], WERTE0__q[4]} +
+	 8'b0000_0001) + (8'b0000_0001 & {8{SOMMERZEIT}})) & {8{{WERTE7__q[4],
+	 WERTE6__q[4], WERTE5__q[4], WERTE4__q[4], WERTE3__q[4], WERTE2__q[4],
+	 WERTE1__q[4], WERTE0__q[4]} != 8'b0001_0111}} & (~({8{RTC_ADR_q ==
+	 6'b00_0100}} & {8{UHR_DS}} & {8{!nFB_WR}}));
+
+//  EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT
+   assign {WERTE7_4_ena_2, WERTE6_4_ena_2, WERTE5_4_ena_2, WERTE4_4_ena_2,
+	 WERTE3_4_ena_2, WERTE2_4_ena_2, WERTE1_4_ena_2, WERTE0_4_ena_2} =
+	 {8{INC_STD}} & (~({8{WINTERZEIT}} & {8{WERTE0__q[12]}})) &
+	 (~({8{RTC_ADR_q == 6'b00_0100}} & {8{UHR_DS}} & {8{!nFB_WR}}));
+
+//  WOCHENTAG UND TAG
+   assign INC_TAG = INC_STD & {WERTE7__q[2], WERTE6__q[2], WERTE5__q[2],
+	 WERTE4__q[2], WERTE3__q[2], WERTE2__q[2], WERTE1__q[2], WERTE0__q[2]}
+	 == 8'b0001_0111;
+
+//  WOCHENTAG ZÄHLEN BIS 7
+//  DANN BEI 1 WEITER
+   assign {WERTE7_6_d_2, WERTE6_6_d_2, WERTE5_6_d_2, WERTE4_6_d_2,
+	 WERTE3_6_d_2, WERTE2_6_d_2, WERTE1_6_d_2, WERTE0_6_d_2} =
+	 (({WERTE7__q[6], WERTE6__q[6], WERTE5__q[6], WERTE4__q[6],
+	 WERTE3__q[6], WERTE2__q[6], WERTE1__q[6], WERTE0__q[6]} +
+	 8'b0000_0001) & {8{{WERTE7__q[6], WERTE6__q[6], WERTE5__q[6],
+	 WERTE4__q[6], WERTE3__q[6], WERTE2__q[6], WERTE1__q[6], WERTE0__q[6]}
+	 != 8'b0000_0111}} & (~({8{RTC_ADR_q == 6'b00_0110}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}))) | (8'b0000_0001 & {8{{WERTE7__q[6], WERTE6__q[6],
+	 WERTE5__q[6], WERTE4__q[6], WERTE3__q[6], WERTE2__q[6], WERTE1__q[6],
+	 WERTE0__q[6]} == 8'b0000_0111}} & (~({8{RTC_ADR_q == 6'b00_0110}} &
+	 {8{UHR_DS}} & {8{!nFB_WR}})));
+   assign {WERTE7_6_ena_2, WERTE6_6_ena_2, WERTE5_6_ena_2, WERTE4_6_ena_2,
+	 WERTE3_6_ena_2, WERTE2_6_ena_2, WERTE1_6_ena_2, WERTE0_6_ena_2} =
+	 {8{INC_TAG}} & (~({8{RTC_ADR_q == 6'b00_0110}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}));
+   assign ANZAHL_TAGE_DES_MONATS = (8'b0001_1111 & ({8{{WERTE7__q[8],
+	 WERTE6__q[8], WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8],
+	 WERTE1__q[8], WERTE0__q[8]} == 8'b0000_0001}} | {8{{WERTE7__q[8],
+	 WERTE6__q[8], WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8],
+	 WERTE1__q[8], WERTE0__q[8]} == 8'b0000_0011}} | {8{{WERTE7__q[8],
+	 WERTE6__q[8], WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8],
+	 WERTE1__q[8], WERTE0__q[8]} == 8'b0000_0101}} | {8{{WERTE7__q[8],
+	 WERTE6__q[8], WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8],
+	 WERTE1__q[8], WERTE0__q[8]} == 8'b0000_0111}} | {8{{WERTE7__q[8],
+	 WERTE6__q[8], WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8],
+	 WERTE1__q[8], WERTE0__q[8]} == 8'b0000_1000}} | {8{{WERTE7__q[8],
+	 WERTE6__q[8], WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8],
+	 WERTE1__q[8], WERTE0__q[8]} == 8'b0000_1010}} | {8{{WERTE7__q[8],
+	 WERTE6__q[8], WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8],
+	 WERTE1__q[8], WERTE0__q[8]} == 8'b0000_1100}})) | (8'b0001_1110 &
+	 ({8{{WERTE7__q[8], WERTE6__q[8], WERTE5__q[8], WERTE4__q[8],
+	 WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]} ==
+	 8'b0000_0100}} | {8{{WERTE7__q[8], WERTE6__q[8], WERTE5__q[8],
+	 WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]}
+	 == 8'b0000_0110}} | {8{{WERTE7__q[8], WERTE6__q[8], WERTE5__q[8],
+	 WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]}
+	 == 8'b0000_1001}} | {8{{WERTE7__q[8], WERTE6__q[8], WERTE5__q[8],
+	 WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]}
+	 == 8'b0000_1011}})) | (8'b0001_1101 & {8{{WERTE7__q[8], WERTE6__q[8],
+	 WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8],
+	 WERTE0__q[8]} == 8'b0000_0010}} & {8{{WERTE1__q[9], WERTE0__q[9]} ==
+	 2'b00}}) | (8'b0001_1100 & {8{{WERTE7__q[8], WERTE6__q[8],
+	 WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8],
+	 WERTE0__q[8]} == 8'b0000_0010}} & {8{{WERTE1__q[9], WERTE0__q[9]} !=
+	 2'b00}});
+
+//  TAG ZÄHLEN BIS MONATSENDE
+//  DANN BEI 1 WEITER
+   assign {WERTE7_7_d_2, WERTE6_7_d_2, WERTE5_7_d_2, WERTE4_7_d_2,
+	 WERTE3_7_d_2, WERTE2_7_d_2, WERTE1_7_d_2, WERTE0_7_d_2} =
+	 (({WERTE7__q[7], WERTE6__q[7], WERTE5__q[7], WERTE4__q[7],
+	 WERTE3__q[7], WERTE2__q[7], WERTE1__q[7], WERTE0__q[7]} +
+	 8'b0000_0001) & {8{{WERTE7__q[7], WERTE6__q[7], WERTE5__q[7],
+	 WERTE4__q[7], WERTE3__q[7], WERTE2__q[7], WERTE1__q[7], WERTE0__q[7]}
+	 != ANZAHL_TAGE_DES_MONATS}} & (~({8{RTC_ADR_q == 6'b00_0111}} &
+	 {8{UHR_DS}} & {8{!nFB_WR}}))) | (8'b0000_0001 & {8{{WERTE7__q[7],
+	 WERTE6__q[7], WERTE5__q[7], WERTE4__q[7], WERTE3__q[7], WERTE2__q[7],
+	 WERTE1__q[7], WERTE0__q[7]} == ANZAHL_TAGE_DES_MONATS}} &
+	 (~({8{RTC_ADR_q == 6'b00_0111}} & {8{UHR_DS}} & {8{!nFB_WR}})));
+   assign {WERTE7_7_ena_2, WERTE6_7_ena_2, WERTE5_7_ena_2, WERTE4_7_ena_2,
+	 WERTE3_7_ena_2, WERTE2_7_ena_2, WERTE1_7_ena_2, WERTE0_7_ena_2} =
+	 {8{INC_TAG}} & (~({8{RTC_ADR_q == 6'b00_0111}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}));
+
+//  MONATE
+   assign INC_MONAT = INC_TAG & {WERTE7__q[7], WERTE6__q[7], WERTE5__q[7],
+	 WERTE4__q[7], WERTE3__q[7], WERTE2__q[7], WERTE1__q[7], WERTE0__q[7]}
+	 == ANZAHL_TAGE_DES_MONATS;
+
+//  MONATE ZÄHLEN BIS 12
+//  DANN BEI 1 WEITER
+   assign {WERTE7_8_d_2, WERTE6_8_d_2, WERTE5_8_d_2, WERTE4_8_d_2,
+	 WERTE3_8_d_2, WERTE2_8_d_2, WERTE1_8_d_2, WERTE0_8_d_2} =
+	 (({WERTE7__q[8], WERTE6__q[8], WERTE5__q[8], WERTE4__q[8],
+	 WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]} +
+	 8'b0000_0001) & {8{{WERTE7__q[8], WERTE6__q[8], WERTE5__q[8],
+	 WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]}
+	 != 8'b0000_1100}} & (~({8{RTC_ADR_q == 6'b00_1000}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}))) | (8'b0000_0001 & {8{{WERTE7__q[8], WERTE6__q[8],
+	 WERTE5__q[8], WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8],
+	 WERTE0__q[8]} == 8'b0000_1100}} & (~({8{RTC_ADR_q == 6'b00_1000}} &
+	 {8{UHR_DS}} & {8{!nFB_WR}})));
+   assign {WERTE7_8_ena_2, WERTE6_8_ena_2, WERTE5_8_ena_2, WERTE4_8_ena_2,
+	 WERTE3_8_ena_2, WERTE2_8_ena_2, WERTE1_8_ena_2, WERTE0_8_ena_2} =
+	 {8{INC_MONAT}} & (~({8{RTC_ADR_q == 6'b00_1000}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}));
+
+//  JAHR
+   assign INC_JAHR = INC_MONAT & {WERTE7__q[8], WERTE6__q[8], WERTE5__q[8],
+	 WERTE4__q[8], WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]}
+	 == 8'b0000_1100;
+
+//  JAHRE ZÄHLEN BIS 99
+   assign {WERTE7_9_d_2, WERTE6_9_d_2, WERTE5_9_d_2, WERTE4_9_d_2,
+	 WERTE3_9_d_2, WERTE2_9_d_2, WERTE1_9_d_2, WERTE0_9_d_2} =
+	 ({WERTE7__q[9], WERTE6__q[9], WERTE5__q[9], WERTE4__q[9],
+	 WERTE3__q[9], WERTE2__q[9], WERTE1__q[9], WERTE0__q[9]} +
+	 8'b0000_0001) & {8{{WERTE7__q[9], WERTE6__q[9], WERTE5__q[9],
+	 WERTE4__q[9], WERTE3__q[9], WERTE2__q[9], WERTE1__q[9], WERTE0__q[9]}
+	 != 8'b0110_0011}} & (~({8{RTC_ADR_q == 6'b00_1001}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}));
+   assign {WERTE7_9_ena_2, WERTE6_9_ena_2, WERTE5_9_ena_2, WERTE4_9_ena_2,
+	 WERTE3_9_ena_2, WERTE2_9_ena_2, WERTE1_9_ena_2, WERTE0_9_ena_2} =
+	 {8{INC_JAHR}} & (~({8{RTC_ADR_q == 6'b00_1001}} & {8{UHR_DS}} &
+	 {8{!nFB_WR}}));
+
+//  TRISTATE OUTPUT
+   assign u0_data = ({8{INT_CTR_CS}} & INT_CTR_q[31:24]) | ({8{INT_ENA_CS}} &
+	 INT_ENA_q[31:24]) | ({8{INT_LATCH_CS}} & INT_LATCH_q[31:24]) |
+	 ({8{INT_CLEAR_CS}} & INT_IN[31:24]) | ({8{ACP_CONF_CS}} &
+	 ACP_CONF_q[31:24]);
+   assign u0_enabledt = (INT_CTR_CS | INT_ENA_CS | INT_LATCH_CS | INT_CLEAR_CS
+	 | ACP_CONF_CS) & (!nFB_OE);
+   assign FB_AD[31:24] = u0_tridata;
+   assign u1_data = ({WERTE7__q[0], WERTE6__q[0], WERTE5__q[0], WERTE4__q[0],
+	 WERTE3__q[0], WERTE2__q[0], WERTE1__q[0], WERTE0__q[0]} & {8{RTC_ADR_q
+	 == 6'b00_0000}} & {8{UHR_DS}}) | ({WERTE7__q[1], WERTE6__q[1],
+	 WERTE5__q[1], WERTE4__q[1], WERTE3__q[1], WERTE2__q[1], WERTE1__q[1],
+	 WERTE0__q[1]} & {8{RTC_ADR_q == 6'b00_0001}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[2], WERTE6__q[2], WERTE5__q[2], WERTE4__q[2],
+	 WERTE3__q[2], WERTE2__q[2], WERTE1__q[2], WERTE0__q[2]} & {8{RTC_ADR_q
+	 == 6'b00_0010}} & {8{UHR_DS}}) | ({WERTE7__q[3], WERTE6__q[3],
+	 WERTE5__q[3], WERTE4__q[3], WERTE3__q[3], WERTE2__q[3], WERTE1__q[3],
+	 WERTE0__q[3]} & {8{RTC_ADR_q == 6'b00_0011}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[4], WERTE6__q[4], WERTE5__q[4], WERTE4__q[4],
+	 WERTE3__q[4], WERTE2__q[4], WERTE1__q[4], WERTE0__q[4]} & {8{RTC_ADR_q
+	 == 6'b00_0100}} & {8{UHR_DS}}) | ({WERTE7__q[5], WERTE6__q[5],
+	 WERTE5__q[5], WERTE4__q[5], WERTE3__q[5], WERTE2__q[5], WERTE1__q[5],
+	 WERTE0__q[5]} & {8{RTC_ADR_q == 6'b00_0101}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[6], WERTE6__q[6], WERTE5__q[6], WERTE4__q[6],
+	 WERTE3__q[6], WERTE2__q[6], WERTE1__q[6], WERTE0__q[6]} & {8{RTC_ADR_q
+	 == 6'b00_0110}} & {8{UHR_DS}}) | ({WERTE7__q[7], WERTE6__q[7],
+	 WERTE5__q[7], WERTE4__q[7], WERTE3__q[7], WERTE2__q[7], WERTE1__q[7],
+	 WERTE0__q[7]} & {8{RTC_ADR_q == 6'b00_0111}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[8], WERTE6__q[8], WERTE5__q[8], WERTE4__q[8],
+	 WERTE3__q[8], WERTE2__q[8], WERTE1__q[8], WERTE0__q[8]} & {8{RTC_ADR_q
+	 == 6'b00_1000}} & {8{UHR_DS}}) | ({WERTE7__q[9], WERTE6__q[9],
+	 WERTE5__q[9], WERTE4__q[9], WERTE3__q[9], WERTE2__q[9], WERTE1__q[9],
+	 WERTE0__q[9]} & {8{RTC_ADR_q == 6'b00_1001}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[10], WERTE6__q[10], WERTE5__q[10], WERTE4__q[10],
+	 WERTE3__q[10], WERTE2__q[10], WERTE1__q[10], WERTE0__q[10]} &
+	 {8{RTC_ADR_q == 6'b00_1010}} & {8{UHR_DS}}) | ({WERTE7__q[11],
+	 WERTE6__q[11], WERTE5__q[11], WERTE4__q[11], WERTE3__q[11],
+	 WERTE2__q[11], WERTE1__q[11], WERTE0__q[11]} & {8{RTC_ADR_q ==
+	 6'b00_1011}} & {8{UHR_DS}}) | ({WERTE7__q[12], WERTE6__q[12],
+	 WERTE5__q[12], WERTE4__q[12], WERTE3__q[12], WERTE2__q[12],
+	 WERTE1__q[12], WERTE0__q[12]} & {8{RTC_ADR_q == 6'b00_1100}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[13], WERTE6__q[13], WERTE5__q[13],
+	 WERTE4__q[13], WERTE3__q[13], WERTE2__q[13], WERTE1__q[13],
+	 WERTE0__q[13]} & {8{RTC_ADR_q == 6'b00_1101}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[14], WERTE6__q[14], WERTE5__q[14], WERTE4__q[14],
+	 WERTE3__q[14], WERTE2__q[14], WERTE1__q[14], WERTE0__q[14]} &
+	 {8{RTC_ADR_q == 6'b00_1110}} & {8{UHR_DS}}) | ({WERTE7__q[15],
+	 WERTE6__q[15], WERTE5__q[15], WERTE4__q[15], WERTE3__q[15],
+	 WERTE2__q[15], WERTE1__q[15], WERTE0__q[15]} & {8{RTC_ADR_q ==
+	 6'b00_1111}} & {8{UHR_DS}}) | ({WERTE7__q[16], WERTE6__q[16],
+	 WERTE5__q[16], WERTE4__q[16], WERTE3__q[16], WERTE2__q[16],
+	 WERTE1__q[16], WERTE0__q[16]} & {8{RTC_ADR_q == 6'b01_0000}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[17], WERTE6__q[17], WERTE5__q[17],
+	 WERTE4__q[17], WERTE3__q[17], WERTE2__q[17], WERTE1__q[17],
+	 WERTE0__q[17]} & {8{RTC_ADR_q == 6'b01_0001}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[18], WERTE6__q[18], WERTE5__q[18], WERTE4__q[18],
+	 WERTE3__q[18], WERTE2__q[18], WERTE1__q[18], WERTE0__q[18]} &
+	 {8{RTC_ADR_q == 6'b01_0010}} & {8{UHR_DS}}) | ({WERTE7__q[19],
+	 WERTE6__q[19], WERTE5__q[19], WERTE4__q[19], WERTE3__q[19],
+	 WERTE2__q[19], WERTE1__q[19], WERTE0__q[19]} & {8{RTC_ADR_q ==
+	 6'b01_0011}} & {8{UHR_DS}}) | ({WERTE7__q[20], WERTE6__q[20],
+	 WERTE5__q[20], WERTE4__q[20], WERTE3__q[20], WERTE2__q[20],
+	 WERTE1__q[20], WERTE0__q[20]} & {8{RTC_ADR_q == 6'b01_0100}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[21], WERTE6__q[21], WERTE5__q[21],
+	 WERTE4__q[21], WERTE3__q[21], WERTE2__q[21], WERTE1__q[21],
+	 WERTE0__q[21]} & {8{RTC_ADR_q == 6'b01_0101}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[22], WERTE6__q[22], WERTE5__q[22], WERTE4__q[22],
+	 WERTE3__q[22], WERTE2__q[22], WERTE1__q[22], WERTE0__q[22]} &
+	 {8{RTC_ADR_q == 6'b01_0110}} & {8{UHR_DS}}) | ({WERTE7__q[23],
+	 WERTE6__q[23], WERTE5__q[23], WERTE4__q[23], WERTE3__q[23],
+	 WERTE2__q[23], WERTE1__q[23], WERTE0__q[23]} & {8{RTC_ADR_q ==
+	 6'b01_0111}} & {8{UHR_DS}}) | ({WERTE7__q[24], WERTE6__q[24],
+	 WERTE5__q[24], WERTE4__q[24], WERTE3__q[24], WERTE2__q[24],
+	 WERTE1__q[24], WERTE0__q[24]} & {8{RTC_ADR_q == 6'b01_1000}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[25], WERTE6__q[25], WERTE5__q[25],
+	 WERTE4__q[25], WERTE3__q[25], WERTE2__q[25], WERTE1__q[25],
+	 WERTE0__q[25]} & {8{RTC_ADR_q == 6'b01_1001}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[26], WERTE6__q[26], WERTE5__q[26], WERTE4__q[26],
+	 WERTE3__q[26], WERTE2__q[26], WERTE1__q[26], WERTE0__q[26]} &
+	 {8{RTC_ADR_q == 6'b01_1010}} & {8{UHR_DS}}) | ({WERTE7__q[27],
+	 WERTE6__q[27], WERTE5__q[27], WERTE4__q[27], WERTE3__q[27],
+	 WERTE2__q[27], WERTE1__q[27], WERTE0__q[27]} & {8{RTC_ADR_q ==
+	 6'b01_1011}} & {8{UHR_DS}}) | ({WERTE7__q[28], WERTE6__q[28],
+	 WERTE5__q[28], WERTE4__q[28], WERTE3__q[28], WERTE2__q[28],
+	 WERTE1__q[28], WERTE0__q[28]} & {8{RTC_ADR_q == 6'b01_1100}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[29], WERTE6__q[29], WERTE5__q[29],
+	 WERTE4__q[29], WERTE3__q[29], WERTE2__q[29], WERTE1__q[29],
+	 WERTE0__q[29]} & {8{RTC_ADR_q == 6'b01_1101}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[30], WERTE6__q[30], WERTE5__q[30], WERTE4__q[30],
+	 WERTE3__q[30], WERTE2__q[30], WERTE1__q[30], WERTE0__q[30]} &
+	 {8{RTC_ADR_q == 6'b01_1110}} & {8{UHR_DS}}) | ({WERTE7__q[31],
+	 WERTE6__q[31], WERTE5__q[31], WERTE4__q[31], WERTE3__q[31],
+	 WERTE2__q[31], WERTE1__q[31], WERTE0__q[31]} & {8{RTC_ADR_q ==
+	 6'b01_1111}} & {8{UHR_DS}}) | ({WERTE7__q[32], WERTE6__q[32],
+	 WERTE5__q[32], WERTE4__q[32], WERTE3__q[32], WERTE2__q[32],
+	 WERTE1__q[32], WERTE0__q[32]} & {8{RTC_ADR_q == 6'b10_0000}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[33], WERTE6__q[33], WERTE5__q[33],
+	 WERTE4__q[33], WERTE3__q[33], WERTE2__q[33], WERTE1__q[33],
+	 WERTE0__q[33]} & {8{RTC_ADR_q == 6'b10_0001}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[34], WERTE6__q[34], WERTE5__q[34], WERTE4__q[34],
+	 WERTE3__q[34], WERTE2__q[34], WERTE1__q[34], WERTE0__q[34]} &
+	 {8{RTC_ADR_q == 6'b10_0010}} & {8{UHR_DS}}) | ({WERTE7__q[35],
+	 WERTE6__q[35], WERTE5__q[35], WERTE4__q[35], WERTE3__q[35],
+	 WERTE2__q[35], WERTE1__q[35], WERTE0__q[35]} & {8{RTC_ADR_q ==
+	 6'b10_0011}} & {8{UHR_DS}}) | ({WERTE7__q[36], WERTE6__q[36],
+	 WERTE5__q[36], WERTE4__q[36], WERTE3__q[36], WERTE2__q[36],
+	 WERTE1__q[36], WERTE0__q[36]} & {8{RTC_ADR_q == 6'b10_0100}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[37], WERTE6__q[37], WERTE5__q[37],
+	 WERTE4__q[37], WERTE3__q[37], WERTE2__q[37], WERTE1__q[37],
+	 WERTE0__q[37]} & {8{RTC_ADR_q == 6'b10_0101}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[38], WERTE6__q[38], WERTE5__q[38], WERTE4__q[38],
+	 WERTE3__q[38], WERTE2__q[38], WERTE1__q[38], WERTE0__q[38]} &
+	 {8{RTC_ADR_q == 6'b10_0110}} & {8{UHR_DS}}) | ({WERTE7__q[39],
+	 WERTE6__q[39], WERTE5__q[39], WERTE4__q[39], WERTE3__q[39],
+	 WERTE2__q[39], WERTE1__q[39], WERTE0__q[39]} & {8{RTC_ADR_q ==
+	 6'b10_0111}} & {8{UHR_DS}}) | ({WERTE7__q[40], WERTE6__q[40],
+	 WERTE5__q[40], WERTE4__q[40], WERTE3__q[40], WERTE2__q[40],
+	 WERTE1__q[40], WERTE0__q[40]} & {8{RTC_ADR_q == 6'b10_1000}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[41], WERTE6__q[41], WERTE5__q[41],
+	 WERTE4__q[41], WERTE3__q[41], WERTE2__q[41], WERTE1__q[41],
+	 WERTE0__q[41]} & {8{RTC_ADR_q == 6'b10_1001}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[42], WERTE6__q[42], WERTE5__q[42], WERTE4__q[42],
+	 WERTE3__q[42], WERTE2__q[42], WERTE1__q[42], WERTE0__q[42]} &
+	 {8{RTC_ADR_q == 6'b10_1010}} & {8{UHR_DS}}) | ({WERTE7__q[43],
+	 WERTE6__q[43], WERTE5__q[43], WERTE4__q[43], WERTE3__q[43],
+	 WERTE2__q[43], WERTE1__q[43], WERTE0__q[43]} & {8{RTC_ADR_q ==
+	 6'b10_1011}} & {8{UHR_DS}}) | ({WERTE7__q[44], WERTE6__q[44],
+	 WERTE5__q[44], WERTE4__q[44], WERTE3__q[44], WERTE2__q[44],
+	 WERTE1__q[44], WERTE0__q[44]} & {8{RTC_ADR_q == 6'b10_1100}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[45], WERTE6__q[45], WERTE5__q[45],
+	 WERTE4__q[45], WERTE3__q[45], WERTE2__q[45], WERTE1__q[45],
+	 WERTE0__q[45]} & {8{RTC_ADR_q == 6'b10_1101}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[46], WERTE6__q[46], WERTE5__q[46], WERTE4__q[46],
+	 WERTE3__q[46], WERTE2__q[46], WERTE1__q[46], WERTE0__q[46]} &
+	 {8{RTC_ADR_q == 6'b10_1110}} & {8{UHR_DS}}) | ({WERTE7__q[47],
+	 WERTE6__q[47], WERTE5__q[47], WERTE4__q[47], WERTE3__q[47],
+	 WERTE2__q[47], WERTE1__q[47], WERTE0__q[47]} & {8{RTC_ADR_q ==
+	 6'b10_1111}} & {8{UHR_DS}}) | ({WERTE7__q[48], WERTE6__q[48],
+	 WERTE5__q[48], WERTE4__q[48], WERTE3__q[48], WERTE2__q[48],
+	 WERTE1__q[48], WERTE0__q[48]} & {8{RTC_ADR_q == 6'b11_0000}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[49], WERTE6__q[49], WERTE5__q[49],
+	 WERTE4__q[49], WERTE3__q[49], WERTE2__q[49], WERTE1__q[49],
+	 WERTE0__q[49]} & {8{RTC_ADR_q == 6'b11_0001}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[50], WERTE6__q[50], WERTE5__q[50], WERTE4__q[50],
+	 WERTE3__q[50], WERTE2__q[50], WERTE1__q[50], WERTE0__q[50]} &
+	 {8{RTC_ADR_q == 6'b11_0010}} & {8{UHR_DS}}) | ({WERTE7__q[51],
+	 WERTE6__q[51], WERTE5__q[51], WERTE4__q[51], WERTE3__q[51],
+	 WERTE2__q[51], WERTE1__q[51], WERTE0__q[51]} & {8{RTC_ADR_q ==
+	 6'b11_0011}} & {8{UHR_DS}}) | ({WERTE7__q[52], WERTE6__q[52],
+	 WERTE5__q[52], WERTE4__q[52], WERTE3__q[52], WERTE2__q[52],
+	 WERTE1__q[52], WERTE0__q[52]} & {8{RTC_ADR_q == 6'b11_0100}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[53], WERTE6__q[53], WERTE5__q[53],
+	 WERTE4__q[53], WERTE3__q[53], WERTE2__q[53], WERTE1__q[53],
+	 WERTE0__q[53]} & {8{RTC_ADR_q == 6'b11_0101}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[54], WERTE6__q[54], WERTE5__q[54], WERTE4__q[54],
+	 WERTE3__q[54], WERTE2__q[54], WERTE1__q[54], WERTE0__q[54]} &
+	 {8{RTC_ADR_q == 6'b11_0110}} & {8{UHR_DS}}) | ({WERTE7__q[55],
+	 WERTE6__q[55], WERTE5__q[55], WERTE4__q[55], WERTE3__q[55],
+	 WERTE2__q[55], WERTE1__q[55], WERTE0__q[55]} & {8{RTC_ADR_q ==
+	 6'b11_0111}} & {8{UHR_DS}}) | ({WERTE7__q[56], WERTE6__q[56],
+	 WERTE5__q[56], WERTE4__q[56], WERTE3__q[56], WERTE2__q[56],
+	 WERTE1__q[56], WERTE0__q[56]} & {8{RTC_ADR_q == 6'b11_1000}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[57], WERTE6__q[57], WERTE5__q[57],
+	 WERTE4__q[57], WERTE3__q[57], WERTE2__q[57], WERTE1__q[57],
+	 WERTE0__q[57]} & {8{RTC_ADR_q == 6'b11_1001}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[58], WERTE6__q[58], WERTE5__q[58], WERTE4__q[58],
+	 WERTE3__q[58], WERTE2__q[58], WERTE1__q[58], WERTE0__q[58]} &
+	 {8{RTC_ADR_q == 6'b11_1010}} & {8{UHR_DS}}) | ({WERTE7__q[59],
+	 WERTE6__q[59], WERTE5__q[59], WERTE4__q[59], WERTE3__q[59],
+	 WERTE2__q[59], WERTE1__q[59], WERTE0__q[59]} & {8{RTC_ADR_q ==
+	 6'b11_1011}} & {8{UHR_DS}}) | ({WERTE7__q[60], WERTE6__q[60],
+	 WERTE5__q[60], WERTE4__q[60], WERTE3__q[60], WERTE2__q[60],
+	 WERTE1__q[60], WERTE0__q[60]} & {8{RTC_ADR_q == 6'b11_1100}} &
+	 {8{UHR_DS}}) | ({WERTE7__q[61], WERTE6__q[61], WERTE5__q[61],
+	 WERTE4__q[61], WERTE3__q[61], WERTE2__q[61], WERTE1__q[61],
+	 WERTE0__q[61]} & {8{RTC_ADR_q == 6'b11_1101}} & {8{UHR_DS}}) |
+	 ({WERTE7__q[62], WERTE6__q[62], WERTE5__q[62], WERTE4__q[62],
+	 WERTE3__q[62], WERTE2__q[62], WERTE1__q[62], WERTE0__q[62]} &
+	 {8{RTC_ADR_q == 6'b11_1110}} & {8{UHR_DS}}) | ({WERTE7__q[63],
+	 WERTE6__q[63], WERTE5__q[63], WERTE4__q[63], WERTE3__q[63],
+	 WERTE2__q[63], WERTE1__q[63], WERTE0__q[63]} & {8{RTC_ADR_q ==
+	 6'b11_1111}} & {8{UHR_DS}}) | ({2'b00, RTC_ADR_q} & {8{UHR_AS}}) |
+	 ({8{INT_CTR_CS}} & INT_CTR_q[23:16]) | ({8{INT_ENA_CS}} &
+	 INT_ENA_q[23:16]) | ({8{INT_LATCH_CS}} & INT_LATCH_q[23:16]) |
+	 ({8{INT_CLEAR_CS}} & INT_IN[23:16]) | ({8{ACP_CONF_CS}} &
+	 ACP_CONF_q[23:16]);
+   assign u1_enabledt = (UHR_DS | UHR_AS | INT_CTR_CS | INT_ENA_CS |
+	 INT_LATCH_CS | INT_CLEAR_CS | ACP_CONF_CS) & (!nFB_OE);
+   assign FB_AD[23:16] = u1_tridata;
+   assign u2_data = ({8{INT_CTR_CS}} & INT_CTR_q[15:8]) | ({8{INT_ENA_CS}} &
+	 INT_ENA_q[15:8]) | ({8{INT_LATCH_CS}} & INT_LATCH_q[15:8]) |
+	 ({8{INT_CLEAR_CS}} & INT_IN[15:8]) | ({8{ACP_CONF_CS}} &
+	 ACP_CONF_q[15:8]);
+   assign u2_enabledt = (INT_CTR_CS | INT_ENA_CS | INT_LATCH_CS | INT_CLEAR_CS
+	 | ACP_CONF_CS) & (!nFB_OE);
+   assign FB_AD[15:8] = u2_tridata;
+   assign u3_data = ({8{INT_CTR_CS}} & INT_CTR_q[7:0]) | ({8{INT_ENA_CS}} &
+	 INT_ENA_q[7:0]) | ({8{INT_LATCH_CS}} & INT_LATCH_q[7:0]) |
+	 ({8{INT_CLEAR_CS}} & INT_IN[7:0]) | ({8{ACP_CONF_CS}} &
+	 ACP_CONF_q[7:0]);
+   assign u3_enabledt = (INT_CTR_CS | INT_ENA_CS | INT_LATCH_CS | INT_CLEAR_CS
+	 | ACP_CONF_CS) & (!nFB_OE);
+   assign FB_AD[7:0] = u3_tridata;
+   assign INT_HANDLER_TA = INT_CTR_CS | INT_ENA_CS | INT_LATCH_CS |
+	 INT_CLEAR_CS;
+
+
+// Assignments added to explicitly combine the
+// effects of multiple drivers in the source
+   assign UPDATE_ON = UPDATE_ON_1 | UPDATE_ON_2;
+   assign WERTE0_0_ena = WERTE0_0_ena_1 | WERTE0_0_ena_2;
+   assign WERTE0_2_ena = WERTE0_2_ena_1 | WERTE0_2_ena_2;
+   assign WERTE0_4_ena = WERTE0_4_ena_1 | WERTE0_4_ena_2;
+   assign WERTE0_6_ena = WERTE0_6_ena_1 | WERTE0_6_ena_2;
+   assign WERTE0_7_ena = WERTE0_7_ena_1 | WERTE0_7_ena_2;
+   assign WERTE0_8_ena = WERTE0_8_ena_1 | WERTE0_8_ena_2;
+   assign WERTE0_9_ena = WERTE0_9_ena_1 | WERTE0_9_ena_2;
+   assign WERTE0_13_ena = WERTE0_13_ena_1 | WERTE0_13_ena_2;
+   assign WERTE0__d[0] = WERTE0_0_d_1 | WERTE0_0_d_2;
+   assign WERTE0__d[2] = WERTE0_2_d_1 | WERTE0_2_d_2;
+   assign WERTE0__d[4] = WERTE0_4_d_1 | WERTE0_4_d_2;
+   assign WERTE0__d[6] = WERTE0_6_d_1 | WERTE0_6_d_2;
+   assign WERTE0__d[7] = WERTE0_7_d_1 | WERTE0_7_d_2;
+   assign WERTE0__d[8] = WERTE0_8_d_1 | WERTE0_8_d_2;
+   assign WERTE0__d[9] = WERTE0_9_d_1 | WERTE0_9_d_2;
+   assign WERTE0__d[11] = WERTE0_11_d_1 | WERTE0_11_d_2;
+   assign WERTE0__d[13] = WERTE0_13_d_1 | WERTE0_13_d_2;
+   assign WERTE1_0_ena = WERTE1_0_ena_1 | WERTE1_0_ena_2;
+   assign WERTE1_2_ena = WERTE1_2_ena_1 | WERTE1_2_ena_2;
+   assign WERTE1_4_ena = WERTE1_4_ena_1 | WERTE1_4_ena_2;
+   assign WERTE1_6_ena = WERTE1_6_ena_1 | WERTE1_6_ena_2;
+   assign WERTE1_7_ena = WERTE1_7_ena_1 | WERTE1_7_ena_2;
+   assign WERTE1_8_ena = WERTE1_8_ena_1 | WERTE1_8_ena_2;
+   assign WERTE1_9_ena = WERTE1_9_ena_1 | WERTE1_9_ena_2;
+   assign WERTE1__d[0] = WERTE1_0_d_1 | WERTE1_0_d_2;
+   assign WERTE1__d[2] = WERTE1_2_d_1 | WERTE1_2_d_2;
+   assign WERTE1__d[4] = WERTE1_4_d_1 | WERTE1_4_d_2;
+   assign WERTE1__d[6] = WERTE1_6_d_1 | WERTE1_6_d_2;
+   assign WERTE1__d[7] = WERTE1_7_d_1 | WERTE1_7_d_2;
+   assign WERTE1__d[8] = WERTE1_8_d_1 | WERTE1_8_d_2;
+   assign WERTE1__d[9] = WERTE1_9_d_1 | WERTE1_9_d_2;
+   assign WERTE1__d[11] = WERTE1_11_d_1 | WERTE1_11_d_2;
+   assign WERTE2_0_ena = WERTE2_0_ena_1 | WERTE2_0_ena_2;
+   assign WERTE2_2_ena = WERTE2_2_ena_1 | WERTE2_2_ena_2;
+   assign WERTE2_4_ena = WERTE2_4_ena_1 | WERTE2_4_ena_2;
+   assign WERTE2_6_ena = WERTE2_6_ena_1 | WERTE2_6_ena_2;
+   assign WERTE2_7_ena = WERTE2_7_ena_1 | WERTE2_7_ena_2;
+   assign WERTE2_8_ena = WERTE2_8_ena_1 | WERTE2_8_ena_2;
+   assign WERTE2_9_ena = WERTE2_9_ena_1 | WERTE2_9_ena_2;
+   assign WERTE2__d[0] = WERTE2_0_d_1 | WERTE2_0_d_2;
+   assign WERTE2__d[2] = WERTE2_2_d_1 | WERTE2_2_d_2;
+   assign WERTE2__d[4] = WERTE2_4_d_1 | WERTE2_4_d_2;
+   assign WERTE2__d[6] = WERTE2_6_d_1 | WERTE2_6_d_2;
+   assign WERTE2__d[7] = WERTE2_7_d_1 | WERTE2_7_d_2;
+   assign WERTE2__d[8] = WERTE2_8_d_1 | WERTE2_8_d_2;
+   assign WERTE2__d[9] = WERTE2_9_d_1 | WERTE2_9_d_2;
+   assign WERTE2__d[11] = WERTE2_11_d_1 | WERTE2_11_d_2;
+   assign WERTE3_0_ena = WERTE3_0_ena_1 | WERTE3_0_ena_2;
+   assign WERTE3_2_ena = WERTE3_2_ena_1 | WERTE3_2_ena_2;
+   assign WERTE3_4_ena = WERTE3_4_ena_1 | WERTE3_4_ena_2;
+   assign WERTE3_6_ena = WERTE3_6_ena_1 | WERTE3_6_ena_2;
+   assign WERTE3_7_ena = WERTE3_7_ena_1 | WERTE3_7_ena_2;
+   assign WERTE3_8_ena = WERTE3_8_ena_1 | WERTE3_8_ena_2;
+   assign WERTE3_9_ena = WERTE3_9_ena_1 | WERTE3_9_ena_2;
+   assign WERTE3__d[0] = WERTE3_0_d_1 | WERTE3_0_d_2;
+   assign WERTE3__d[2] = WERTE3_2_d_1 | WERTE3_2_d_2;
+   assign WERTE3__d[4] = WERTE3_4_d_1 | WERTE3_4_d_2;
+   assign WERTE3__d[6] = WERTE3_6_d_1 | WERTE3_6_d_2;
+   assign WERTE3__d[7] = WERTE3_7_d_1 | WERTE3_7_d_2;
+   assign WERTE3__d[8] = WERTE3_8_d_1 | WERTE3_8_d_2;
+   assign WERTE3__d[9] = WERTE3_9_d_1 | WERTE3_9_d_2;
+   assign WERTE4_0_ena = WERTE4_0_ena_1 | WERTE4_0_ena_2;
+   assign WERTE4_2_ena = WERTE4_2_ena_1 | WERTE4_2_ena_2;
+   assign WERTE4_4_ena = WERTE4_4_ena_1 | WERTE4_4_ena_2;
+   assign WERTE4_6_ena = WERTE4_6_ena_1 | WERTE4_6_ena_2;
+   assign WERTE4_7_ena = WERTE4_7_ena_1 | WERTE4_7_ena_2;
+   assign WERTE4_8_ena = WERTE4_8_ena_1 | WERTE4_8_ena_2;
+   assign WERTE4_9_ena = WERTE4_9_ena_1 | WERTE4_9_ena_2;
+   assign WERTE4__d[0] = WERTE4_0_d_1 | WERTE4_0_d_2;
+   assign WERTE4__d[2] = WERTE4_2_d_1 | WERTE4_2_d_2;
+   assign WERTE4__d[4] = WERTE4_4_d_1 | WERTE4_4_d_2;
+   assign WERTE4__d[6] = WERTE4_6_d_1 | WERTE4_6_d_2;
+   assign WERTE4__d[7] = WERTE4_7_d_1 | WERTE4_7_d_2;
+   assign WERTE4__d[8] = WERTE4_8_d_1 | WERTE4_8_d_2;
+   assign WERTE4__d[9] = WERTE4_9_d_1 | WERTE4_9_d_2;
+   assign WERTE5_0_ena = WERTE5_0_ena_1 | WERTE5_0_ena_2;
+   assign WERTE5_2_ena = WERTE5_2_ena_1 | WERTE5_2_ena_2;
+   assign WERTE5_4_ena = WERTE5_4_ena_1 | WERTE5_4_ena_2;
+   assign WERTE5_6_ena = WERTE5_6_ena_1 | WERTE5_6_ena_2;
+   assign WERTE5_7_ena = WERTE5_7_ena_1 | WERTE5_7_ena_2;
+   assign WERTE5_8_ena = WERTE5_8_ena_1 | WERTE5_8_ena_2;
+   assign WERTE5_9_ena = WERTE5_9_ena_1 | WERTE5_9_ena_2;
+   assign WERTE5__d[0] = WERTE5_0_d_1 | WERTE5_0_d_2;
+   assign WERTE5__d[2] = WERTE5_2_d_1 | WERTE5_2_d_2;
+   assign WERTE5__d[4] = WERTE5_4_d_1 | WERTE5_4_d_2;
+   assign WERTE5__d[6] = WERTE5_6_d_1 | WERTE5_6_d_2;
+   assign WERTE5__d[7] = WERTE5_7_d_1 | WERTE5_7_d_2;
+   assign WERTE5__d[8] = WERTE5_8_d_1 | WERTE5_8_d_2;
+   assign WERTE5__d[9] = WERTE5_9_d_1 | WERTE5_9_d_2;
+   assign WERTE6_0_ena = WERTE6_0_ena_1 | WERTE6_0_ena_2;
+   assign WERTE6_2_ena = WERTE6_2_ena_1 | WERTE6_2_ena_2;
+   assign WERTE6_4_ena = WERTE6_4_ena_1 | WERTE6_4_ena_2;
+   assign WERTE6_6_ena = WERTE6_6_ena_1 | WERTE6_6_ena_2;
+   assign WERTE6_7_ena = WERTE6_7_ena_1 | WERTE6_7_ena_2;
+   assign WERTE6_8_ena = WERTE6_8_ena_1 | WERTE6_8_ena_2;
+   assign WERTE6_9_ena = WERTE6_9_ena_1 | WERTE6_9_ena_2;
+   assign WERTE6__d[0] = WERTE6_0_d_1 | WERTE6_0_d_2;
+   assign WERTE6__d[2] = WERTE6_2_d_1 | WERTE6_2_d_2;
+   assign WERTE6__d[4] = WERTE6_4_d_1 | WERTE6_4_d_2;
+   assign WERTE6__d[6] = WERTE6_6_d_1 | WERTE6_6_d_2;
+   assign WERTE6__d[7] = WERTE6_7_d_1 | WERTE6_7_d_2;
+   assign WERTE6__d[8] = WERTE6_8_d_1 | WERTE6_8_d_2;
+   assign WERTE6__d[9] = WERTE6_9_d_1 | WERTE6_9_d_2;
+   assign WERTE7_0_ena = WERTE7_0_ena_1 | WERTE7_0_ena_2;
+   assign WERTE7_2_ena = WERTE7_2_ena_1 | WERTE7_2_ena_2;
+   assign WERTE7_4_ena = WERTE7_4_ena_1 | WERTE7_4_ena_2;
+   assign WERTE7_6_ena = WERTE7_6_ena_1 | WERTE7_6_ena_2;
+   assign WERTE7_7_ena = WERTE7_7_ena_1 | WERTE7_7_ena_2;
+   assign WERTE7_8_ena = WERTE7_8_ena_1 | WERTE7_8_ena_2;
+   assign WERTE7_9_ena = WERTE7_9_ena_1 | WERTE7_9_ena_2;
+   assign WERTE7__d[0] = WERTE7_0_d_1 | WERTE7_0_d_2;
+   assign WERTE7__d[2] = WERTE7_2_d_1 | WERTE7_2_d_2;
+   assign WERTE7__d[4] = WERTE7_4_d_1 | WERTE7_4_d_2;
+   assign WERTE7__d[6] = WERTE7_6_d_1 | WERTE7_6_d_2;
+   assign WERTE7__d[7] = WERTE7_7_d_1 | WERTE7_7_d_2;
+   assign WERTE7__d[8] = WERTE7_8_d_1 | WERTE7_8_d_2;
+   assign WERTE7__d[9] = WERTE7_9_d_1 | WERTE7_9_d_2;
+   assign WERTE7__d[13] = WERTE7_13_d_1 | WERTE7_13_d_2;
+
+// Define power signal(s)
+   assign vcc = 1'b1;
+   assign gnd = 1'b0;
+endmodule
diff --git a/FPGA_quartus_GE/ahdl2v/lpm_bustri.tdf b/FPGA_quartus_GE/ahdl2v/lpm_bustri.tdf
new file mode 100644
index 0000000..abd780b
--- /dev/null
+++ b/FPGA_quartus_GE/ahdl2v/lpm_bustri.tdf
@@ -0,0 +1,78 @@
+--------------------------------------------------------------------
+--
+--	LPM_BUSTRI Parameterized Megafunction
+--
+--  Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions  
+--  and other software and tools, and its AMPP partner logic  
+--  functions, and any output files from any of the foregoing  
+--  (including device programming or simulation files), and any  
+--  associated documentation or information are expressly subject  
+--  to the terms and conditions of the Altera Program License  
+--  Subscription Agreement, Altera MegaCore Function License  
+--  Agreement, or other applicable license agreement, including,  
+--  without limitation, that your use is for the sole purpose of  
+--  programming logic devices manufactured by Altera and sold by  
+--  Altera or its authorized distributors.  Please refer to the  
+--  applicable agreement for further details. 
+--  
+--  Quartus II 13.1.0 Build 162 10/23/2013 
+--
+--	Version 2.0
+--
+--------------------------------------------------------------------
+
+
+PARAMETERS
+(
+	LPM_WIDTH
+);
+
+SUBDESIGN lpm_bustri
+(
+	tridata[LPM_WIDTH-1..0]	: BIDIR;
+	data[LPM_WIDTH-1..0]	: INPUT = VCC;
+	enabletr				: INPUT = VCC;
+	enabledt				: INPUT = VCC;
+	result[LPM_WIDTH-1..0]	: OUTPUT;
+)
+
+VARIABLE
+	% Are the enable inputs used? %
+	IF (USED(enabledt)) GENERATE
+		dout[LPM_WIDTH-1..0]	: TRI;
+	END GENERATE;
+	IF (USED(enabletr)) GENERATE
+		din[LPM_WIDTH-1..0]		: TRI;
+	END GENERATE;
+
+BEGIN
+
+	ASSERT (LPM_WIDTH > 0)
+			REPORT "Value of LPM_WIDTH parameter value must be greater than 0"
+			SEVERITY ERROR
+			HELP_ID LPM_BUSTRI_WIDTH;
+
+	ASSERT (USED(enabledt) & USED(data))
+		REPORT "lpm_bustri function requires data[] port -- Altera recommends using the TRI primitive instead"
+		SEVERITY ERROR
+		HELP_ID LPM_BUSTRI_DATA;
+
+	% Connect buffers if they are used %
+	IF (USED(enabledt)) GENERATE
+		dout[].oe = enabledt;
+		dout[] = data[];
+		tridata[] = dout[];
+	END GENERATE;
+
+	IF (USED(enabletr)) GENERATE
+		din[].oe = enabletr;
+		din[] = tridata[];
+		result[] = din[];
+	ELSE GENERATE
+		result[] = tridata[];
+	END GENERATE;
+	IF !USED(result) GENERATE
+		result[] = GND;
+	END GENERATE;
+END;
diff --git a/FPGA_quartus_GE/ahdl2v/lpm_bustri_BYT.inc b/FPGA_quartus_GE/ahdl2v/lpm_bustri_BYT.inc
new file mode 100644
index 0000000..8cb4941
--- /dev/null
+++ b/FPGA_quartus_GE/ahdl2v/lpm_bustri_BYT.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_bustri_BYT 
+(
+	data[7..0],
+	enabledt
+)
+
+RETURNS (
+	tridata[7..0]
+);
diff --git a/FPGA_quartus_GE/ahdl2v/lpm_bustri_BYT.tdf b/FPGA_quartus_GE/ahdl2v/lpm_bustri_BYT.tdf
new file mode 100644
index 0000000..84b70c8
--- /dev/null
+++ b/FPGA_quartus_GE/ahdl2v/lpm_bustri_BYT.tdf
@@ -0,0 +1,72 @@
+--------------------------------------------------------------------
+--
+--	LPM_BUSTRI Parameterized Megafunction
+--
+--  Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions  
+--  and other software and tools, and its AMPP partner logic  
+--  functions, and any output files from any of the foregoing  
+--  (including device programming or simulation files), and any  
+--  associated documentation or information are expressly subject  
+--  to the terms and conditions of the Altera Program License  
+--  Subscription Agreement, Altera MegaCore Function License  
+--  Agreement, or other applicable license agreement, including,  
+--  without limitation, that your use is for the sole purpose of  
+--  programming logic devices manufactured by Altera and sold by  
+--  Altera or its authorized distributors.  Please refer to the  
+--  applicable agreement for further details. 
+--  
+--  Quartus II 13.1.0 Build 162 10/23/2013 
+--
+--	Version 2.0
+--
+--------------------------------------------------------------------
+
+SUBDESIGN lpm_bustri_BYT
+(
+	tridata[8-1..0]	: BIDIR;
+	data[8-1..0]	: INPUT = VCC;
+	enabletr				: INPUT = VCC;
+	enabledt				: INPUT = VCC;
+	result[8-1..0]	: OUTPUT;
+)
+
+VARIABLE
+	% Are the enable inputs used? %
+	IF (USED(enabledt)) GENERATE
+		dout[8-1..0]	: TRI;
+	END GENERATE;
+	IF (USED(enabletr)) GENERATE
+		din[8-1..0]		: TRI;
+	END GENERATE;
+
+BEGIN
+
+	ASSERT (8 > 0)
+			REPORT "Value of 8 parameter value must be greater than 0"
+			SEVERITY ERROR
+			HELP_ID LPM_BUSTRI_WIDTH;
+
+	ASSERT (USED(enabledt) & USED(data))
+		REPORT "lpm_bustri function requires data[] port -- Altera recommends using the TRI primitive instead"
+		SEVERITY ERROR
+		HELP_ID LPM_BUSTRI_DATA;
+
+	% Connect buffers if they are used %
+	IF (USED(enabledt)) GENERATE
+		dout[].oe = enabledt;
+		dout[] = data[];
+		tridata[] = dout[];
+	END GENERATE;
+
+	IF (USED(enabletr)) GENERATE
+		din[].oe = enabletr;
+		din[] = tridata[];
+		result[] = din[];
+	ELSE GENERATE
+		result[] = tridata[];
+	END GENERATE;
+	IF !USED(result) GENERATE
+		result[] = GND;
+	END GENERATE;
+END;
diff --git a/FPGA_quartus_GE/ahdl2v/lpm_bustri_BYT.v b/FPGA_quartus_GE/ahdl2v/lpm_bustri_BYT.v
new file mode 100644
index 0000000..da23b16
--- /dev/null
+++ b/FPGA_quartus_GE/ahdl2v/lpm_bustri_BYT.v
@@ -0,0 +1,78 @@
+// Xilinx XPort Language Converter, Version 4.1 (110)
+// 
+// AHDL    Design Source: lpm_bustri_BYT.tdf
+// Verilog Design Output: lpm_bustri_BYT.v
+// Created 03-Mar-2014 09:18 PM
+//
+// Copyright (c) 2014, Xilinx, Inc.  All Rights Reserved.
+// Xilinx Inc makes no warranty, expressed or implied, with respect to
+// the operation and/or functionality of the converted output files.
+// 
+
+
+// ------------------------------------------------------------------
+//   LPM_BUSTRI Parameterized Megafunction
+//   Copyright (C) 1991-2013 Altera Corporation
+//   Your use of Altera Corporation's design tools, logic functions
+//   and other software and tools, and its AMPP partner logic
+//   functions, and any output files from any of the foregoing
+//   (including device programming or simulation files), and any
+//   associated documentation or information are expressly subject
+//   to the terms and conditions of the Altera Program License
+//   Subscription Agreement, Altera MegaCore Function License
+//   Agreement, or other applicable license agreement, including,
+//   without limitation, that your use is for the sole purpose of
+//   programming logic devices manufactured by Altera and sold by
+//   Altera or its authorized distributors.  Please refer to the
+//   applicable agreement for further details.
+//   Quartus II 13.1.0 Build 162 10/23/2013
+//   Version 2.0
+// ------------------------------------------------------------------
+module lpm_bustri_BYT(tridata, data, enabletr, enabledt, result);
+   input [7:0] data;
+   input enabletr, enabledt;
+   output [7:0] result;
+   inout [7:0] tridata;
+
+//  Are the enable inputs used? 
+   wire [7:0] dout;
+   wire [7:0] dout_in;
+   wire gnd, result0_1, result0_2, result1_1, result1_2, result2_1, result2_2,
+	 result3_1, result3_2, result4_1, result4_2, result5_1, result5_2,
+	 result6_1, result6_2, result7_1, result7_2, dout0_oe_ctrl;
+
+   assign dout[0] = (dout0_oe_ctrl) ? dout_in[0] : 1'bz;
+   assign dout[1] = (dout0_oe_ctrl) ? dout_in[1] : 1'bz;
+   assign dout[2] = (dout0_oe_ctrl) ? dout_in[2] : 1'bz;
+   assign dout[3] = (dout0_oe_ctrl) ? dout_in[3] : 1'bz;
+   assign dout[4] = (dout0_oe_ctrl) ? dout_in[4] : 1'bz;
+   assign dout[5] = (dout0_oe_ctrl) ? dout_in[5] : 1'bz;
+   assign dout[6] = (dout0_oe_ctrl) ? dout_in[6] : 1'bz;
+   assign dout[7] = (dout0_oe_ctrl) ? dout_in[7] : 1'bz;
+
+// Start of original equations
+
+//  Connect buffers if they are used 
+   assign dout0_oe_ctrl = enabledt;
+   assign dout_in = data;
+   assign tridata = dout;
+   assign {result7_1, result6_1, result5_1, result4_1, result3_1, result2_1,
+	 result1_1, result0_1} = tridata;
+   assign {result7_2, result6_2, result5_2, result4_2, result3_2, result2_2,
+	 result1_2, result0_2} = {8{gnd}};
+
+
+// Assignments added to explicitly combine the
+// effects of multiple drivers in the source
+   assign result[0] = result0_1 | result0_2;
+   assign result[1] = result1_1 | result1_2;
+   assign result[2] = result2_1 | result2_2;
+   assign result[3] = result3_1 | result3_2;
+   assign result[4] = result4_1 | result4_2;
+   assign result[5] = result5_1 | result5_2;
+   assign result[6] = result6_1 | result6_2;
+   assign result[7] = result7_1 | result7_2;
+
+// Define power signal(s)
+   assign gnd = 1'b0;
+endmodule
diff --git a/FPGA_quartus_GE/ahdl2v/lpm_bustri_LONG.inc b/FPGA_quartus_GE/ahdl2v/lpm_bustri_LONG.inc
new file mode 100644
index 0000000..f180c48
--- /dev/null
+++ b/FPGA_quartus_GE/ahdl2v/lpm_bustri_LONG.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_bustri_LONG 
+(
+	data[31..0],
+	enabledt
+)
+
+RETURNS (
+	tridata[31..0]
+);
diff --git a/FPGA_quartus_GE/ahdl2v/lpm_bustri_LONG.tdf b/FPGA_quartus_GE/ahdl2v/lpm_bustri_LONG.tdf
new file mode 100644
index 0000000..0ec70d1
--- /dev/null
+++ b/FPGA_quartus_GE/ahdl2v/lpm_bustri_LONG.tdf
@@ -0,0 +1,72 @@
+--------------------------------------------------------------------
+--
+--	LPM_BUSTRI Parameterized Megafunction
+--
+--  Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions  
+--  and other software and tools, and its AMPP partner logic  
+--  functions, and any output files from any of the foregoing  
+--  (including device programming or simulation files), and any  
+--  associated documentation or information are expressly subject  
+--  to the terms and conditions of the Altera Program License  
+--  Subscription Agreement, Altera MegaCore Function License  
+--  Agreement, or other applicable license agreement, including,  
+--  without limitation, that your use is for the sole purpose of  
+--  programming logic devices manufactured by Altera and sold by  
+--  Altera or its authorized distributors.  Please refer to the  
+--  applicable agreement for further details. 
+--  
+--  Quartus II 13.1.0 Build 162 10/23/2013 
+--
+--	Version 2.0
+--
+--------------------------------------------------------------------
+
+SUBDESIGN lpm_bustri_LONG
+(
+	tridata[32-1..0]	: BIDIR;
+	data[32-1..0]	: INPUT = VCC;
+	enabletr				: INPUT = VCC;
+	enabledt				: INPUT = VCC;
+	result[32-1..0]	: OUTPUT;
+)
+
+VARIABLE
+	% Are the enable inputs used? %
+	IF (USED(enabledt)) GENERATE
+		dout[32-1..0]	: TRI;
+	END GENERATE;
+	IF (USED(enabletr)) GENERATE
+		din[32-1..0]		: TRI;
+	END GENERATE;
+
+BEGIN
+
+	ASSERT (32 > 0)
+			REPORT "Value of 32 parameter value must be greater than 0"
+			SEVERITY ERROR
+			HELP_ID LPM_BUSTRI_WIDTH;
+
+	ASSERT (USED(enabledt) & USED(data))
+		REPORT "lpm_bustri function requires data[] port -- Altera recommends using the TRI primitive instead"
+		SEVERITY ERROR
+		HELP_ID LPM_BUSTRI_DATA;
+
+	% Connect buffers if they are used %
+	IF (USED(enabledt)) GENERATE
+		dout[].oe = enabledt;
+		dout[] = data[];
+		tridata[] = dout[];
+	END GENERATE;
+
+	IF (USED(enabletr)) GENERATE
+		din[].oe = enabletr;
+		din[] = tridata[];
+		result[] = din[];
+	ELSE GENERATE
+		result[] = tridata[];
+	END GENERATE;
+	IF !USED(result) GENERATE
+		result[] = GND;
+	END GENERATE;
+END;
diff --git a/FPGA_quartus_GE/ahdl2v/lpm_bustri_WORD.inc b/FPGA_quartus_GE/ahdl2v/lpm_bustri_WORD.inc
new file mode 100644
index 0000000..09f6251
--- /dev/null
+++ b/FPGA_quartus_GE/ahdl2v/lpm_bustri_WORD.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_bustri_WORD 
+(
+	data[15..0],
+	enabledt
+)
+
+RETURNS (
+	tridata[15..0]
+);
diff --git a/FPGA_quartus_GE/ahdl2v/lpm_bustri_WORD.tdf b/FPGA_quartus_GE/ahdl2v/lpm_bustri_WORD.tdf
new file mode 100644
index 0000000..3e2ac8b
--- /dev/null
+++ b/FPGA_quartus_GE/ahdl2v/lpm_bustri_WORD.tdf
@@ -0,0 +1,72 @@
+--------------------------------------------------------------------
+--
+--	LPM_BUSTRI Parameterized Megafunction
+--
+--  Copyright (C) 1991-2013 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions  
+--  and other software and tools, and its AMPP partner logic  
+--  functions, and any output files from any of the foregoing  
+--  (including device programming or simulation files), and any  
+--  associated documentation or information are expressly subject  
+--  to the terms and conditions of the Altera Program License  
+--  Subscription Agreement, Altera MegaCore Function License  
+--  Agreement, or other applicable license agreement, including,  
+--  without limitation, that your use is for the sole purpose of  
+--  programming logic devices manufactured by Altera and sold by  
+--  Altera or its authorized distributors.  Please refer to the  
+--  applicable agreement for further details. 
+--  
+--  Quartus II 13.1.0 Build 162 10/23/2013 
+--
+--	Version 2.0
+--
+--------------------------------------------------------------------
+
+SUBDESIGN lpm_bustri_WORD
+(
+	tridata[16-1..0]	: BIDIR;
+	data[16-1..0]	: INPUT = VCC;
+	enabletr				: INPUT = VCC;
+	enabledt				: INPUT = VCC;
+	result[16-1..0]	: OUTPUT;
+)
+
+VARIABLE
+	% Are the enable inputs used? %
+	IF (USED(enabledt)) GENERATE
+		dout[16-1..0]	: TRI;
+	END GENERATE;
+	IF (USED(enabletr)) GENERATE
+		din[16-1..0]		: TRI;
+	END GENERATE;
+
+BEGIN
+
+	ASSERT (16 > 0)
+			REPORT "Value of 16 parameter value must be greater than 0"
+			SEVERITY ERROR
+			HELP_ID LPM_BUSTRI_WIDTH;
+
+	ASSERT (USED(enabledt) & USED(data))
+		REPORT "lpm_bustri function requires data[] port -- Altera recommends using the TRI primitive instead"
+		SEVERITY ERROR
+		HELP_ID LPM_BUSTRI_DATA;
+
+	% Connect buffers if they are used %
+	IF (USED(enabledt)) GENERATE
+		dout[].oe = enabledt;
+		dout[] = data[];
+		tridata[] = dout[];
+	END GENERATE;
+
+	IF (USED(enabletr)) GENERATE
+		din[].oe = enabletr;
+		din[] = tridata[];
+		result[] = din[];
+	ELSE GENERATE
+		result[] = tridata[];
+	END GENERATE;
+	IF !USED(result) GENERATE
+		result[] = GND;
+	END GENERATE;
+END;
diff --git a/FPGA_quartus_GE/ahdl2v/lpm_bustri_WORD.v b/FPGA_quartus_GE/ahdl2v/lpm_bustri_WORD.v
new file mode 100644
index 0000000..cfd22d9
--- /dev/null
+++ b/FPGA_quartus_GE/ahdl2v/lpm_bustri_WORD.v
@@ -0,0 +1,99 @@
+// Xilinx XPort Language Converter, Version 4.1 (110)
+// 
+// AHDL    Design Source: lpm_bustri_WORD.tdf
+// Verilog Design Output: lpm_bustri_WORD.v
+// Created 02-Mar-2014 04:36 PM
+//
+// Copyright (c) 2014, Xilinx, Inc.  All Rights Reserved.
+// Xilinx Inc makes no warranty, expressed or implied, with respect to
+// the operation and/or functionality of the converted output files.
+// 
+
+
+// ------------------------------------------------------------------
+//   LPM_BUSTRI Parameterized Megafunction
+//   Copyright (C) 1991-2013 Altera Corporation
+//   Your use of Altera Corporation's design tools, logic functions
+//   and other software and tools, and its AMPP partner logic
+//   functions, and any output files from any of the foregoing
+//   (including device programming or simulation files), and any
+//   associated documentation or information are expressly subject
+//   to the terms and conditions of the Altera Program License
+//   Subscription Agreement, Altera MegaCore Function License
+//   Agreement, or other applicable license agreement, including,
+//   without limitation, that your use is for the sole purpose of
+//   programming logic devices manufactured by Altera and sold by
+//   Altera or its authorized distributors.  Please refer to the
+//   applicable agreement for further details.
+//   Quartus II 13.1.0 Build 162 10/23/2013
+//   Version 2.0
+// ------------------------------------------------------------------
+module lpm_bustri_WORD(tridata, data, enabletr, enabledt, result);
+   input [15:0] data;
+   input enabletr, enabledt;
+   output [15:0] result;
+   inout [15:0] tridata;
+
+//  Are the enable inputs used? 
+   wire [15:0] dout;
+   wire [15:0] dout_in;
+   wire gnd, result0_1, result0_2, result1_1, result1_2, result2_1, result2_2,
+	 result3_1, result3_2, result4_1, result4_2, result5_1, result5_2,
+	 result6_1, result6_2, result7_1, result7_2, result8_1, result8_2,
+	 result9_1, result9_2, result10_1, result10_2, result11_1, result11_2,
+	 result12_1, result12_2, result13_1, result13_2, result14_1,
+	 result14_2, result15_1, result15_2, dout0_oe_ctrl;
+
+   assign dout[0] = (dout0_oe_ctrl) ? dout_in[0] : 1'bz;
+   assign dout[1] = (dout0_oe_ctrl) ? dout_in[1] : 1'bz;
+   assign dout[2] = (dout0_oe_ctrl) ? dout_in[2] : 1'bz;
+   assign dout[3] = (dout0_oe_ctrl) ? dout_in[3] : 1'bz;
+   assign dout[4] = (dout0_oe_ctrl) ? dout_in[4] : 1'bz;
+   assign dout[5] = (dout0_oe_ctrl) ? dout_in[5] : 1'bz;
+   assign dout[6] = (dout0_oe_ctrl) ? dout_in[6] : 1'bz;
+   assign dout[7] = (dout0_oe_ctrl) ? dout_in[7] : 1'bz;
+   assign dout[8] = (dout0_oe_ctrl) ? dout_in[8] : 1'bz;
+   assign dout[9] = (dout0_oe_ctrl) ? dout_in[9] : 1'bz;
+   assign dout[10] = (dout0_oe_ctrl) ? dout_in[10] : 1'bz;
+   assign dout[11] = (dout0_oe_ctrl) ? dout_in[11] : 1'bz;
+   assign dout[12] = (dout0_oe_ctrl) ? dout_in[12] : 1'bz;
+   assign dout[13] = (dout0_oe_ctrl) ? dout_in[13] : 1'bz;
+   assign dout[14] = (dout0_oe_ctrl) ? dout_in[14] : 1'bz;
+   assign dout[15] = (dout0_oe_ctrl) ? dout_in[15] : 1'bz;
+
+// Start of original equations
+
+//  Connect buffers if they are used 
+   assign dout0_oe_ctrl = enabledt;
+   assign dout_in = data;
+   assign tridata = dout;
+   assign {result15_1, result14_1, result13_1, result12_1, result11_1,
+	 result10_1, result9_1, result8_1, result7_1, result6_1, result5_1,
+	 result4_1, result3_1, result2_1, result1_1, result0_1} = tridata;
+   assign {result15_2, result14_2, result13_2, result12_2, result11_2,
+	 result10_2, result9_2, result8_2, result7_2, result6_2, result5_2,
+	 result4_2, result3_2, result2_2, result1_2, result0_2} = {16{gnd}};
+
+
+// Assignments added to explicitly combine the
+// effects of multiple drivers in the source
+   assign result[0] = result0_1 | result0_2;
+   assign result[1] = result1_1 | result1_2;
+   assign result[2] = result2_1 | result2_2;
+   assign result[3] = result3_1 | result3_2;
+   assign result[4] = result4_1 | result4_2;
+   assign result[5] = result5_1 | result5_2;
+   assign result[6] = result6_1 | result6_2;
+   assign result[7] = result7_1 | result7_2;
+   assign result[8] = result8_1 | result8_2;
+   assign result[9] = result9_1 | result9_2;
+   assign result[10] = result10_1 | result10_2;
+   assign result[11] = result11_1 | result11_2;
+   assign result[12] = result12_1 | result12_2;
+   assign result[13] = result13_1 | result13_2;
+   assign result[14] = result14_1 | result14_2;
+   assign result[15] = result15_1 | result15_2;
+
+// Define power signal(s)
+   assign gnd = 1'b0;
+endmodule
diff --git a/FPGA_quartus_GE/ahdl2v/xport.exe b/FPGA_quartus_GE/ahdl2v/xport.exe
new file mode 100644
index 0000000000000000000000000000000000000000..16ea1b34b463aa7a1eb9d53948f1171c7289fb17
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diff --git a/FPGA_quartus_GE/altddio_out0.bsf b/FPGA_quartus_GE/altddio_out0.bsf
new file mode 100644
index 0000000..9889d79
--- /dev/null
+++ b/FPGA_quartus_GE/altddio_out0.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 232 120)
+	(text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 104 25 116)(font "Arial" ))
+	(port
+		(pt 0 24)
+		(input)
+		(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8)))
+		(line (pt 0 24)(pt 88 24)(line_width 1))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 88 40)(line_width 1))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 88 56)(line_width 1))
+	)
+	(port
+		(pt 232 24)
+		(output)
+		(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8)))
+		(line (pt 232 24)(pt 152 24)(line_width 1))
+	)
+	(drawing
+		(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
+		(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
+		(text "power up" (rect 92 74 129 86)(font "Arial" ))
+		(text "low" (rect 92 84 105 96)(font "Arial" ))
+		(line (pt 88 16)(pt 152 16)(line_width 1))
+		(line (pt 152 16)(pt 152 96)(line_width 1))
+		(line (pt 152 96)(pt 88 96)(line_width 1))
+		(line (pt 88 96)(pt 88 16)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/altddio_out0.inc b/FPGA_quartus_GE/altddio_out0.inc
new file mode 100644
index 0000000..030b327
--- /dev/null
+++ b/FPGA_quartus_GE/altddio_out0.inc
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altddio_out0 
+(
+	datain_h,
+	datain_l,
+	outclock
+)
+
+RETURNS (
+	dataout
+);
diff --git a/FPGA_quartus_GE/altddio_out0.ppf b/FPGA_quartus_GE/altddio_out0.ppf
new file mode 100644
index 0000000..4379977
--- /dev/null
+++ b/FPGA_quartus_GE/altddio_out0.ppf
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altddio_out0" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
+<global>
+<pin name="datain_h" direction="input" scope="external"  />
+<pin name="datain_l" direction="input" scope="external"  />
+<pin name="outclock" direction="input" scope="external" source="clock"  />
+<pin name="dataout" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_quartus_GE/altddio_out0.qip b/FPGA_quartus_GE/altddio_out0.qip
new file mode 100644
index 0000000..8193856
--- /dev/null
+++ b/FPGA_quartus_GE/altddio_out0.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out0.ppf"]
diff --git a/FPGA_quartus_GE/altddio_out0.vhd b/FPGA_quartus_GE/altddio_out0.vhd
new file mode 100644
index 0000000..ea6d708
--- /dev/null
+++ b/FPGA_quartus_GE/altddio_out0.vhd
@@ -0,0 +1,146 @@
+-- megafunction wizard: %ALTDDIO_OUT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altddio_out 
+
+-- ============================================================
+-- File Name: altddio_out0.vhd
+-- Megafunction Name(s):
+-- 			altddio_out
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altddio_out0 IS
+	PORT
+	(
+		datain_h		: IN STD_LOGIC ;
+		datain_l		: IN STD_LOGIC ;
+		outclock		: IN STD_LOGIC ;
+		dataout		: OUT STD_LOGIC 
+	);
+END altddio_out0;
+
+
+ARCHITECTURE SYN OF altddio_out0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altddio_out
+	GENERIC (
+		extend_oe_disable		: STRING;
+		intended_device_family		: STRING;
+		invert_output		: STRING;
+		lpm_type		: STRING;
+		oe_reg		: STRING;
+		power_up_high		: STRING;
+		width		: NATURAL
+	);
+	PORT (
+			dataout	: OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
+			outclock	: IN STD_LOGIC ;
+			datain_h	: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+			datain_l	: IN STD_LOGIC_VECTOR (0 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire1    <= sub_wire0(0);
+	dataout    <= sub_wire1;
+	sub_wire2    <= datain_h;
+	sub_wire3(0)    <= sub_wire2;
+	sub_wire4    <= datain_l;
+	sub_wire5(0)    <= sub_wire4;
+
+	altddio_out_component : altddio_out
+	GENERIC MAP (
+		extend_oe_disable => "UNUSED",
+		intended_device_family => "Cyclone III",
+		invert_output => "OFF",
+		lpm_type => "altddio_out",
+		oe_reg => "UNUSED",
+		power_up_high => "OFF",
+		width => 1
+	)
+	PORT MAP (
+		outclock => outclock,
+		datain_h => sub_wire3,
+		datain_l => sub_wire5,
+		dataout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: OE NUMERIC "0"
+-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: WIDTH NUMERIC "1"
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
+-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
+-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH NUMERIC "1"
+-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
+-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
+-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
+-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
+-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
+-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
+-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/altddio_out3.bsf b/FPGA_quartus_GE/altddio_out3.bsf
new file mode 100644
index 0000000..ba8c153
--- /dev/null
+++ b/FPGA_quartus_GE/altddio_out3.bsf
@@ -0,0 +1,64 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 232 120)
+	(text "altddio_out3" (rect 81 1 163 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 104 25 116)(font "Arial" ))
+	(port
+		(pt 0 24)
+		(input)
+		(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8)))
+		(line (pt 0 24)(pt 88 24)(line_width 1))
+	)
+	(port
+		(pt 0 40)
+		(input)
+		(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
+		(text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 88 40)(line_width 1))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 88 56)(line_width 1))
+	)
+	(port
+		(pt 232 24)
+		(output)
+		(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8)))
+		(line (pt 232 24)(pt 152 24)(line_width 1))
+	)
+	(drawing
+		(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
+		(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
+		(text "power up" (rect 92 74 129 86)(font "Arial" ))
+		(text "low" (rect 92 84 105 96)(font "Arial" ))
+		(line (pt 88 16)(pt 152 16)(line_width 1))
+		(line (pt 152 16)(pt 152 96)(line_width 1))
+		(line (pt 152 96)(pt 88 96)(line_width 1))
+		(line (pt 88 96)(pt 88 16)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/altddio_out3.inc b/FPGA_quartus_GE/altddio_out3.inc
new file mode 100644
index 0000000..f6b4097
--- /dev/null
+++ b/FPGA_quartus_GE/altddio_out3.inc
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altddio_out3 
+(
+	datain_h,
+	datain_l,
+	outclock
+)
+
+RETURNS (
+	dataout
+);
diff --git a/FPGA_quartus_GE/altddio_out3.ppf b/FPGA_quartus_GE/altddio_out3.ppf
new file mode 100644
index 0000000..e914df8
--- /dev/null
+++ b/FPGA_quartus_GE/altddio_out3.ppf
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altddio_out3" megafunction_name="ALTDDIO_OUT" specifies="all_ports">
+<global>
+<pin name="datain_h" direction="input" scope="external"  />
+<pin name="datain_l" direction="input" scope="external"  />
+<pin name="outclock" direction="input" scope="external" source="clock"  />
+<pin name="dataout" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_quartus_GE/altddio_out3.qip b/FPGA_quartus_GE/altddio_out3.qip
new file mode 100644
index 0000000..8f94ee3
--- /dev/null
+++ b/FPGA_quartus_GE/altddio_out3.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTDDIO_OUT"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altddio_out3.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altddio_out3.ppf"]
diff --git a/FPGA_quartus_GE/altddio_out3.vhd b/FPGA_quartus_GE/altddio_out3.vhd
new file mode 100644
index 0000000..e55160f
--- /dev/null
+++ b/FPGA_quartus_GE/altddio_out3.vhd
@@ -0,0 +1,146 @@
+-- megafunction wizard: %ALTDDIO_OUT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altddio_out 
+
+-- ============================================================
+-- File Name: altddio_out3.vhd
+-- Megafunction Name(s):
+-- 			altddio_out
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altddio_out3 IS
+	PORT
+	(
+		datain_h		: IN STD_LOGIC ;
+		datain_l		: IN STD_LOGIC ;
+		outclock		: IN STD_LOGIC ;
+		dataout		: OUT STD_LOGIC 
+	);
+END altddio_out3;
+
+
+ARCHITECTURE SYN OF altddio_out3 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altddio_out
+	GENERIC (
+		extend_oe_disable		: STRING;
+		intended_device_family		: STRING;
+		invert_output		: STRING;
+		lpm_type		: STRING;
+		oe_reg		: STRING;
+		power_up_high		: STRING;
+		width		: NATURAL
+	);
+	PORT (
+			dataout	: OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
+			outclock	: IN STD_LOGIC ;
+			datain_h	: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+			datain_l	: IN STD_LOGIC_VECTOR (0 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire1    <= sub_wire0(0);
+	dataout    <= sub_wire1;
+	sub_wire2    <= datain_h;
+	sub_wire3(0)    <= sub_wire2;
+	sub_wire4    <= datain_l;
+	sub_wire5(0)    <= sub_wire4;
+
+	altddio_out_component : altddio_out
+	GENERIC MAP (
+		extend_oe_disable => "UNUSED",
+		intended_device_family => "Cyclone III",
+		invert_output => "OFF",
+		lpm_type => "altddio_out",
+		oe_reg => "UNUSED",
+		power_up_high => "OFF",
+		width => 1
+	)
+	PORT MAP (
+		outclock => outclock,
+		datain_h => sub_wire3,
+		datain_l => sub_wire5,
+		dataout => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: OE NUMERIC "0"
+-- Retrieval info: PRIVATE: OE_REG NUMERIC "0"
+-- Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
+-- Retrieval info: PRIVATE: SRESET_MODE NUMERIC "2"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: WIDTH NUMERIC "1"
+-- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
+-- Retrieval info: CONSTANT: OE_REG STRING "UNUSED"
+-- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH NUMERIC "1"
+-- Retrieval info: USED_PORT: datain_h 0 0 0 0 INPUT NODEFVAL datain_h
+-- Retrieval info: USED_PORT: datain_l 0 0 0 0 INPUT NODEFVAL datain_l
+-- Retrieval info: USED_PORT: dataout 0 0 0 0 OUTPUT NODEFVAL dataout
+-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL outclock
+-- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 0 0
+-- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 0 0
+-- Retrieval info: CONNECT: dataout 0 0 0 0 @dataout 0 0 1 0
+-- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altddio_out3_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/altpll0.bsf b/FPGA_quartus_GE/altpll0.bsf
new file mode 100644
index 0000000..b9a2853
--- /dev/null
+++ b/FPGA_quartus_GE/altpll0.bsf
@@ -0,0 +1,117 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 280 248)
+	(text "altpll0" (rect 120 1 167 20)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 229 31 244)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 48 72)(line_width 1))
+	)
+	(port
+		(pt 280 72)
+		(output)
+		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c0" (rect 263 56 277 72)(font "Arial" (font_size 8)))
+		(line (pt 280 72)(pt 248 72)(line_width 1))
+	)
+	(port
+		(pt 280 96)
+		(output)
+		(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c1" (rect 263 80 277 96)(font "Arial" (font_size 8)))
+		(line (pt 280 96)(pt 248 96)(line_width 1))
+	)
+	(port
+		(pt 280 120)
+		(output)
+		(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c2" (rect 263 104 277 120)(font "Arial" (font_size 8)))
+		(line (pt 280 120)(pt 248 120)(line_width 1))
+	)
+	(port
+		(pt 280 144)
+		(output)
+		(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c3" (rect 263 128 277 144)(font "Arial" (font_size 8)))
+		(line (pt 280 144)(pt 248 144)(line_width 1))
+	)
+	(port
+		(pt 280 168)
+		(output)
+		(text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c4" (rect 263 152 277 168)(font "Arial" (font_size 8)))
+		(line (pt 280 168)(pt 248 168)(line_width 1))
+	)
+	(drawing
+		(text "Cyclone III" (rect 205 230 253 244)(font "Arial" ))
+		(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
+		(text "Operation Mode: Normal" (rect 58 84 173 98)(font "Arial" ))
+		(text "Clk " (rect 59 111 76 125)(font "Arial" ))
+		(text "Ratio" (rect 90 111 114 125)(font "Arial" ))
+		(text "Ph (dg)" (rect 128 111 163 125)(font "Arial" ))
+		(text "DC (%)" (rect 173 111 208 125)(font "Arial" ))
+		(text "c0" (rect 63 129 75 143)(font "Arial" ))
+		(text "16/11" (rect 89 129 116 143)(font "Arial" ))
+		(text "0.00" (rect 136 129 157 143)(font "Arial" ))
+		(text "50.00" (rect 178 129 205 143)(font "Arial" ))
+		(text "c1" (rect 63 147 75 161)(font "Arial" ))
+		(text "50/11" (rect 89 147 116 161)(font "Arial" ))
+		(text "0.00" (rect 136 147 157 161)(font "Arial" ))
+		(text "50.00" (rect 178 147 205 161)(font "Arial" ))
+		(text "c2" (rect 63 165 75 179)(font "Arial" ))
+		(text "40/11" (rect 89 165 116 179)(font "Arial" ))
+		(text "0.00" (rect 136 165 157 179)(font "Arial" ))
+		(text "50.00" (rect 178 165 205 179)(font "Arial" ))
+		(text "c3" (rect 63 183 75 197)(font "Arial" ))
+		(text "109/33" (rect 85 183 118 197)(font "Arial" ))
+		(text "0.00" (rect 136 183 157 197)(font "Arial" ))
+		(text "50.00" (rect 178 183 205 197)(font "Arial" ))
+		(text "c4" (rect 63 201 75 215)(font "Arial" ))
+		(text "109/39" (rect 85 201 118 215)(font "Arial" ))
+		(text "0.00" (rect 136 201 157 215)(font "Arial" ))
+		(text "50.00" (rect 178 201 205 215)(font "Arial" ))
+		(line (pt 0 0)(pt 281 0)(line_width 1))
+		(line (pt 281 0)(pt 281 249)(line_width 1))
+		(line (pt 0 249)(pt 281 249)(line_width 1))
+		(line (pt 0 0)(pt 0 249)(line_width 1))
+		(line (pt 56 108)(pt 215 108)(line_width 1))
+		(line (pt 56 125)(pt 215 125)(line_width 1))
+		(line (pt 56 143)(pt 215 143)(line_width 1))
+		(line (pt 56 161)(pt 215 161)(line_width 1))
+		(line (pt 56 179)(pt 215 179)(line_width 1))
+		(line (pt 56 197)(pt 215 197)(line_width 1))
+		(line (pt 56 215)(pt 215 215)(line_width 1))
+		(line (pt 56 108)(pt 56 215)(line_width 1))
+		(line (pt 82 108)(pt 82 215)(line_width 3))
+		(line (pt 125 108)(pt 125 215)(line_width 3))
+		(line (pt 170 108)(pt 170 215)(line_width 3))
+		(line (pt 214 108)(pt 214 215)(line_width 1))
+		(line (pt 48 56)(pt 248 56)(line_width 1))
+		(line (pt 248 56)(pt 248 232)(line_width 1))
+		(line (pt 48 232)(pt 248 232)(line_width 1))
+		(line (pt 48 56)(pt 48 232)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/altpll0.inc b/FPGA_quartus_GE/altpll0.inc
new file mode 100644
index 0000000..933af49
--- /dev/null
+++ b/FPGA_quartus_GE/altpll0.inc
@@ -0,0 +1,27 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altpll0 
+(
+	inclk0
+)
+
+RETURNS (
+	c0,
+	c1,
+	c2,
+	c3,
+	c4
+);
diff --git a/FPGA_quartus_GE/altpll0.ppf b/FPGA_quartus_GE/altpll0.ppf
new file mode 100644
index 0000000..521a742
--- /dev/null
+++ b/FPGA_quartus_GE/altpll0.ppf
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altpll0" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+<pin name="c4" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_quartus_GE/altpll0.qip b/FPGA_quartus_GE/altpll0.qip
new file mode 100644
index 0000000..1b4cd11
--- /dev/null
+++ b/FPGA_quartus_GE/altpll0.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll0.ppf"]
diff --git a/FPGA_quartus_GE/altpll0.vhd b/FPGA_quartus_GE/altpll0.vhd
new file mode 100644
index 0000000..b035bf5
--- /dev/null
+++ b/FPGA_quartus_GE/altpll0.vhd
@@ -0,0 +1,477 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: altpll0.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altpll0 IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC 
+	);
+END altpll0;
+
+
+ARCHITECTURE SYN OF altpll0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire8_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		clk4_divide_by		: NATURAL;
+		clk4_duty_cycle		: NATURAL;
+		clk4_multiply_by		: NATURAL;
+		clk4_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire8_bv(0 DOWNTO 0) <= "0";
+	sub_wire8    <= To_stdlogicvector(sub_wire8_bv);
+	sub_wire5    <= sub_wire0(4);
+	sub_wire4    <= sub_wire0(3);
+	sub_wire3    <= sub_wire0(2);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	c2    <= sub_wire3;
+	c3    <= sub_wire4;
+	c4    <= sub_wire5;
+	sub_wire6    <= inclk0;
+	sub_wire7    <= sub_wire8(0 DOWNTO 0) & sub_wire6;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 11,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 16,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 11,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 50,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 11,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 40,
+		clk2_phase_shift => "0",
+		clk3_divide_by => 33,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 109,
+		clk3_phase_shift => "0",
+		clk4_divide_by => 39,
+		clk4_duty_cycle => 50,
+		clk4_multiply_by => 109,
+		clk4_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 30303,
+		intended_device_family => "Cyclone III",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_USED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire7,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "75"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "36"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "39"
+-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "39"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "150.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "120.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "109.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "92.230766"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "109"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "109"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "109"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "109"
+-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "109"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "150.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "120.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "109.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "92.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll0.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "11"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "11"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "40"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "33"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "109"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "39"
+-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "109"
+-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll0_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/altpll1.bsf b/FPGA_quartus_GE/altpll1.bsf
new file mode 100644
index 0000000..d1e4a9e
--- /dev/null
+++ b/FPGA_quartus_GE/altpll1.bsf
@@ -0,0 +1,100 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 328 216)
+	(text "altpll1" (rect 144 1 191 20)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 197 31 212)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 48 72)(line_width 1))
+	)
+	(port
+		(pt 328 72)
+		(output)
+		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c0" (rect 311 56 325 72)(font "Arial" (font_size 8)))
+		(line (pt 328 72)(pt 272 72)(line_width 1))
+	)
+	(port
+		(pt 328 96)
+		(output)
+		(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c1" (rect 311 80 325 96)(font "Arial" (font_size 8)))
+		(line (pt 328 96)(pt 272 96)(line_width 1))
+	)
+	(port
+		(pt 328 120)
+		(output)
+		(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c2" (rect 311 104 325 120)(font "Arial" (font_size 8)))
+		(line (pt 328 120)(pt 272 120)(line_width 1))
+	)
+	(port
+		(pt 328 144)
+		(output)
+		(text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8)))
+		(text "locked" (rect 287 128 325 144)(font "Arial" (font_size 8)))
+		(line (pt 328 144)(pt 272 144)(line_width 1))
+	)
+	(drawing
+		(text "Cyclone III" (rect 253 198 301 212)(font "Arial" ))
+		(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
+		(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
+		(text "Clk " (rect 59 111 76 125)(font "Arial" ))
+		(text "Ratio" (rect 90 111 114 125)(font "Arial" ))
+		(text "Ph (dg)" (rect 128 111 163 125)(font "Arial" ))
+		(text "DC (%)" (rect 173 111 208 125)(font "Arial" ))
+		(text "c0" (rect 63 129 75 143)(font "Arial" ))
+		(text "1/66" (rect 92 129 113 143)(font "Arial" ))
+		(text "0.00" (rect 136 129 157 143)(font "Arial" ))
+		(text "50.00" (rect 178 129 205 143)(font "Arial" ))
+		(text "c1" (rect 63 147 75 161)(font "Arial" ))
+		(text "67/900" (rect 85 147 118 161)(font "Arial" ))
+		(text "0.00" (rect 136 147 157 161)(font "Arial" ))
+		(text "50.00" (rect 178 147 205 161)(font "Arial" ))
+		(text "c2" (rect 63 165 75 179)(font "Arial" ))
+		(text "67/90" (rect 89 165 116 179)(font "Arial" ))
+		(text "0.00" (rect 136 165 157 179)(font "Arial" ))
+		(text "50.00" (rect 178 165 205 179)(font "Arial" ))
+		(line (pt 0 0)(pt 329 0)(line_width 1))
+		(line (pt 329 0)(pt 329 217)(line_width 1))
+		(line (pt 0 217)(pt 329 217)(line_width 1))
+		(line (pt 0 0)(pt 0 217)(line_width 1))
+		(line (pt 56 108)(pt 215 108)(line_width 1))
+		(line (pt 56 125)(pt 215 125)(line_width 1))
+		(line (pt 56 143)(pt 215 143)(line_width 1))
+		(line (pt 56 161)(pt 215 161)(line_width 1))
+		(line (pt 56 179)(pt 215 179)(line_width 1))
+		(line (pt 56 108)(pt 56 179)(line_width 1))
+		(line (pt 82 108)(pt 82 179)(line_width 3))
+		(line (pt 125 108)(pt 125 179)(line_width 3))
+		(line (pt 170 108)(pt 170 179)(line_width 3))
+		(line (pt 214 108)(pt 214 179)(line_width 1))
+		(line (pt 48 56)(pt 272 56)(line_width 1))
+		(line (pt 272 56)(pt 272 200)(line_width 1))
+		(line (pt 48 200)(pt 272 200)(line_width 1))
+		(line (pt 48 56)(pt 48 200)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/altpll1.inc b/FPGA_quartus_GE/altpll1.inc
new file mode 100644
index 0000000..0923ad2
--- /dev/null
+++ b/FPGA_quartus_GE/altpll1.inc
@@ -0,0 +1,26 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altpll1 
+(
+	inclk0
+)
+
+RETURNS (
+	c0,
+	c1,
+	c2,
+	locked
+);
diff --git a/FPGA_quartus_GE/altpll1.ppf b/FPGA_quartus_GE/altpll1.ppf
new file mode 100644
index 0000000..0f38a28
--- /dev/null
+++ b/FPGA_quartus_GE/altpll1.ppf
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altpll1" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_quartus_GE/altpll1.qip b/FPGA_quartus_GE/altpll1.qip
new file mode 100644
index 0000000..ec03f05
--- /dev/null
+++ b/FPGA_quartus_GE/altpll1.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.ppf"]
diff --git a/FPGA_quartus_GE/altpll1.vhd b/FPGA_quartus_GE/altpll1.vhd
new file mode 100644
index 0000000..ab9bfaf
--- /dev/null
+++ b/FPGA_quartus_GE/altpll1.vhd
@@ -0,0 +1,423 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: altpll1.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altpll1 IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END altpll1;
+
+
+ARCHITECTURE SYN OF altpll1 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire3    <= sub_wire0(2);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	c2    <= sub_wire3;
+	locked    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 66,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 1,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 900,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 67,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 90,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 67,
+		clk2_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 30303,
+		intended_device_family => "Cyclone III",
+		lpm_type => "altpll",
+		operation_mode => "SOURCE_SYNCHRONOUS",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0,
+		locked => sub_wire4
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "90"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "2.456667"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.566668"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "67"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "0.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "2.45760000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll1.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "66"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "900"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "67"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "90"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "67"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/altpll2.bsf b/FPGA_quartus_GE/altpll2.bsf
new file mode 100644
index 0000000..79679d7
--- /dev/null
+++ b/FPGA_quartus_GE/altpll2.bsf
@@ -0,0 +1,117 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 304 248)
+	(text "altpll2" (rect 132 1 179 20)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 229 31 244)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 48 72)(line_width 1))
+	)
+	(port
+		(pt 304 72)
+		(output)
+		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8)))
+		(line (pt 304 72)(pt 272 72)(line_width 1))
+	)
+	(port
+		(pt 304 96)
+		(output)
+		(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8)))
+		(line (pt 304 96)(pt 272 96)(line_width 1))
+	)
+	(port
+		(pt 304 120)
+		(output)
+		(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8)))
+		(line (pt 304 120)(pt 272 120)(line_width 1))
+	)
+	(port
+		(pt 304 144)
+		(output)
+		(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8)))
+		(line (pt 304 144)(pt 272 144)(line_width 1))
+	)
+	(port
+		(pt 304 168)
+		(output)
+		(text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c4" (rect 287 152 301 168)(font "Arial" (font_size 8)))
+		(line (pt 304 168)(pt 272 168)(line_width 1))
+	)
+	(drawing
+		(text "Cyclone III" (rect 229 230 277 244)(font "Arial" ))
+		(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
+		(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
+		(text "Clk " (rect 59 111 76 125)(font "Arial" ))
+		(text "Ratio" (rect 85 111 109 125)(font "Arial" ))
+		(text "Ph (dg)" (rect 119 111 154 125)(font "Arial" ))
+		(text "DC (%)" (rect 164 111 199 125)(font "Arial" ))
+		(text "c0" (rect 63 129 75 143)(font "Arial" ))
+		(text "4/1" (rect 91 129 106 143)(font "Arial" ))
+		(text "240.00" (rect 120 129 153 143)(font "Arial" ))
+		(text "50.00" (rect 169 129 196 143)(font "Arial" ))
+		(text "c1" (rect 63 147 75 161)(font "Arial" ))
+		(text "4/1" (rect 91 147 106 161)(font "Arial" ))
+		(text "0.00" (rect 127 147 148 161)(font "Arial" ))
+		(text "50.00" (rect 169 147 196 161)(font "Arial" ))
+		(text "c2" (rect 63 165 75 179)(font "Arial" ))
+		(text "4/1" (rect 91 165 106 179)(font "Arial" ))
+		(text "180.00" (rect 120 165 153 179)(font "Arial" ))
+		(text "50.00" (rect 169 165 196 179)(font "Arial" ))
+		(text "c3" (rect 63 183 75 197)(font "Arial" ))
+		(text "4/1" (rect 91 183 106 197)(font "Arial" ))
+		(text "105.00" (rect 120 183 153 197)(font "Arial" ))
+		(text "50.00" (rect 169 183 196 197)(font "Arial" ))
+		(text "c4" (rect 63 201 75 215)(font "Arial" ))
+		(text "2/1" (rect 91 201 106 215)(font "Arial" ))
+		(text "270.00" (rect 120 201 153 215)(font "Arial" ))
+		(text "50.00" (rect 169 201 196 215)(font "Arial" ))
+		(line (pt 0 0)(pt 305 0)(line_width 1))
+		(line (pt 305 0)(pt 305 249)(line_width 1))
+		(line (pt 0 249)(pt 305 249)(line_width 1))
+		(line (pt 0 0)(pt 0 249)(line_width 1))
+		(line (pt 56 108)(pt 206 108)(line_width 1))
+		(line (pt 56 125)(pt 206 125)(line_width 1))
+		(line (pt 56 143)(pt 206 143)(line_width 1))
+		(line (pt 56 161)(pt 206 161)(line_width 1))
+		(line (pt 56 179)(pt 206 179)(line_width 1))
+		(line (pt 56 197)(pt 206 197)(line_width 1))
+		(line (pt 56 215)(pt 206 215)(line_width 1))
+		(line (pt 56 108)(pt 56 215)(line_width 1))
+		(line (pt 82 108)(pt 82 215)(line_width 3))
+		(line (pt 116 108)(pt 116 215)(line_width 3))
+		(line (pt 161 108)(pt 161 215)(line_width 3))
+		(line (pt 205 108)(pt 205 215)(line_width 1))
+		(line (pt 48 56)(pt 272 56)(line_width 1))
+		(line (pt 272 56)(pt 272 232)(line_width 1))
+		(line (pt 48 232)(pt 272 232)(line_width 1))
+		(line (pt 48 56)(pt 48 232)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/altpll2.inc b/FPGA_quartus_GE/altpll2.inc
new file mode 100644
index 0000000..e75913b
--- /dev/null
+++ b/FPGA_quartus_GE/altpll2.inc
@@ -0,0 +1,27 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altpll2 
+(
+	inclk0
+)
+
+RETURNS (
+	c0,
+	c1,
+	c2,
+	c3,
+	c4
+);
diff --git a/FPGA_quartus_GE/altpll2.ppf b/FPGA_quartus_GE/altpll2.ppf
new file mode 100644
index 0000000..b1c71cc
--- /dev/null
+++ b/FPGA_quartus_GE/altpll2.ppf
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altpll2" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+<pin name="c4" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_quartus_GE/altpll2.qip b/FPGA_quartus_GE/altpll2.qip
new file mode 100644
index 0000000..74cc641
--- /dev/null
+++ b/FPGA_quartus_GE/altpll2.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.ppf"]
diff --git a/FPGA_quartus_GE/altpll2.vhd b/FPGA_quartus_GE/altpll2.vhd
new file mode 100644
index 0000000..2c55f08
--- /dev/null
+++ b/FPGA_quartus_GE/altpll2.vhd
@@ -0,0 +1,477 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: altpll2.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altpll2 IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC ;
+		c4		: OUT STD_LOGIC 
+	);
+END altpll2;
+
+
+ARCHITECTURE SYN OF altpll2 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire8_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		clk4_divide_by		: NATURAL;
+		clk4_duty_cycle		: NATURAL;
+		clk4_multiply_by		: NATURAL;
+		clk4_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire8_bv(0 DOWNTO 0) <= "0";
+	sub_wire8    <= To_stdlogicvector(sub_wire8_bv);
+	sub_wire5    <= sub_wire0(4);
+	sub_wire4    <= sub_wire0(3);
+	sub_wire3    <= sub_wire0(2);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	c2    <= sub_wire3;
+	c3    <= sub_wire4;
+	c4    <= sub_wire5;
+	sub_wire6    <= inclk0;
+	sub_wire7    <= sub_wire8(0 DOWNTO 0) & sub_wire6;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 1,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 4,
+		clk0_phase_shift => "5051",
+		clk1_divide_by => 1,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 4,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 1,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 4,
+		clk2_phase_shift => "3788",
+		clk3_divide_by => 1,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 4,
+		clk3_phase_shift => "2210",
+		clk4_divide_by => 1,
+		clk4_duty_cycle => 50,
+		clk4_multiply_by => 2,
+		clk4_phase_shift => "11364",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 30303,
+		intended_device_family => "Cyclone III",
+		lpm_type => "altpll",
+		operation_mode => "SOURCE_SYNCHRONOUS",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_USED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire7,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "132.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "132.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "132.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "132.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "66.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK4 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "2"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "133.33333000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "133.33330000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "133.33330000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "133.33330000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "240.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "180.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "105.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "270.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll2.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK4 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA4 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "5051"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "3788"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "2210"
+-- Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "11364"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/altpll3.bsf b/FPGA_quartus_GE/altpll3.bsf
new file mode 100644
index 0000000..da30b0c
--- /dev/null
+++ b/FPGA_quartus_GE/altpll3.bsf
@@ -0,0 +1,105 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 304 232)
+	(text "altpll3" (rect 132 1 179 20)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 213 31 228)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 48 72)(line_width 1))
+	)
+	(port
+		(pt 304 72)
+		(output)
+		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8)))
+		(line (pt 304 72)(pt 272 72)(line_width 1))
+	)
+	(port
+		(pt 304 96)
+		(output)
+		(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8)))
+		(line (pt 304 96)(pt 272 96)(line_width 1))
+	)
+	(port
+		(pt 304 120)
+		(output)
+		(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8)))
+		(line (pt 304 120)(pt 272 120)(line_width 1))
+	)
+	(port
+		(pt 304 144)
+		(output)
+		(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8)))
+		(line (pt 304 144)(pt 272 144)(line_width 1))
+	)
+	(drawing
+		(text "Cyclone III" (rect 229 214 277 228)(font "Arial" ))
+		(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
+		(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
+		(text "Clk " (rect 59 111 76 125)(font "Arial" ))
+		(text "Ratio" (rect 86 111 110 125)(font "Arial" ))
+		(text "Ph (dg)" (rect 121 111 156 125)(font "Arial" ))
+		(text "DC (%)" (rect 166 111 201 125)(font "Arial" ))
+		(text "c0" (rect 63 129 75 143)(font "Arial" ))
+		(text "2/33" (rect 88 129 109 143)(font "Arial" ))
+		(text "0.00" (rect 129 129 150 143)(font "Arial" ))
+		(text "50.00" (rect 171 129 198 143)(font "Arial" ))
+		(text "c1" (rect 63 147 75 161)(font "Arial" ))
+		(text "16/33" (rect 85 147 112 161)(font "Arial" ))
+		(text "0.00" (rect 129 147 150 161)(font "Arial" ))
+		(text "50.00" (rect 171 147 198 161)(font "Arial" ))
+		(text "c2" (rect 63 165 75 179)(font "Arial" ))
+		(text "25/33" (rect 85 165 112 179)(font "Arial" ))
+		(text "0.00" (rect 129 165 150 179)(font "Arial" ))
+		(text "50.00" (rect 171 165 198 179)(font "Arial" ))
+		(text "c3" (rect 63 183 75 197)(font "Arial" ))
+		(text "16/11" (rect 85 183 112 197)(font "Arial" ))
+		(text "0.00" (rect 129 183 150 197)(font "Arial" ))
+		(text "50.00" (rect 171 183 198 197)(font "Arial" ))
+		(line (pt 0 0)(pt 305 0)(line_width 1))
+		(line (pt 305 0)(pt 305 233)(line_width 1))
+		(line (pt 0 233)(pt 305 233)(line_width 1))
+		(line (pt 0 0)(pt 0 233)(line_width 1))
+		(line (pt 56 108)(pt 208 108)(line_width 1))
+		(line (pt 56 125)(pt 208 125)(line_width 1))
+		(line (pt 56 143)(pt 208 143)(line_width 1))
+		(line (pt 56 161)(pt 208 161)(line_width 1))
+		(line (pt 56 179)(pt 208 179)(line_width 1))
+		(line (pt 56 197)(pt 208 197)(line_width 1))
+		(line (pt 56 108)(pt 56 197)(line_width 1))
+		(line (pt 82 108)(pt 82 197)(line_width 3))
+		(line (pt 118 108)(pt 118 197)(line_width 3))
+		(line (pt 163 108)(pt 163 197)(line_width 3))
+		(line (pt 207 108)(pt 207 197)(line_width 1))
+		(line (pt 48 56)(pt 272 56)(line_width 1))
+		(line (pt 272 56)(pt 272 216)(line_width 1))
+		(line (pt 48 216)(pt 272 216)(line_width 1))
+		(line (pt 48 56)(pt 48 216)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/altpll3.inc b/FPGA_quartus_GE/altpll3.inc
new file mode 100644
index 0000000..160ecad
--- /dev/null
+++ b/FPGA_quartus_GE/altpll3.inc
@@ -0,0 +1,26 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altpll3 
+(
+	inclk0
+)
+
+RETURNS (
+	c0,
+	c1,
+	c2,
+	c3
+);
diff --git a/FPGA_quartus_GE/altpll3.ppf b/FPGA_quartus_GE/altpll3.ppf
new file mode 100644
index 0000000..2a7b695
--- /dev/null
+++ b/FPGA_quartus_GE/altpll3.ppf
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altpll3" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="c3" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_quartus_GE/altpll3.qip b/FPGA_quartus_GE/altpll3.qip
new file mode 100644
index 0000000..8dd2955
--- /dev/null
+++ b/FPGA_quartus_GE/altpll3.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll3.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.ppf"]
diff --git a/FPGA_quartus_GE/altpll3.vhd b/FPGA_quartus_GE/altpll3.vhd
new file mode 100644
index 0000000..6ead1f5
--- /dev/null
+++ b/FPGA_quartus_GE/altpll3.vhd
@@ -0,0 +1,445 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: altpll3.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY altpll3 IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC 
+	);
+END altpll3;
+
+
+ARCHITECTURE SYN OF altpll3 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(3);
+	sub_wire3    <= sub_wire0(2);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	c2    <= sub_wire3;
+	c3    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 33,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 2,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 33,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 16,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 33,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 25,
+		clk2_phase_shift => "0",
+		clk3_divide_by => 11,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 16,
+		clk3_phase_shift => "0",
+		compensate_clock => "CLK1",
+		inclk0_input_frequency => 30303,
+		intended_device_family => "Cyclone III",
+		lpm_type => "altpll",
+		operation_mode => "SOURCE_SYNCHRONOUS",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c1"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "33"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "33"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "33.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "25"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "48"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "160.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll3.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "33"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "33"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "33"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "11"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "16"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK1"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/altpll4.bsf b/FPGA_quartus_GE/altpll4.bsf
new file mode 100644
index 0000000..e071d43
--- /dev/null
+++ b/FPGA_quartus_GE/altpll4.bsf
@@ -0,0 +1,125 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 376 232)
+	(text "altpll4" (rect 168 1 215 20)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 213 31 228)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 88 72)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "areset" (rect 0 0 42 16)(font "Arial" (font_size 8)))
+		(text "areset" (rect 4 80 40 96)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 88 96)(line_width 1))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "scanclk" (rect 0 0 53 16)(font "Arial" (font_size 8)))
+		(text "scanclk" (rect 4 104 49 120)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 88 120)(line_width 1))
+	)
+	(port
+		(pt 0 144)
+		(input)
+		(text "scandata" (rect 0 0 62 16)(font "Arial" (font_size 8)))
+		(text "scandata" (rect 4 128 57 144)(font "Arial" (font_size 8)))
+		(line (pt 0 144)(pt 88 144)(line_width 1))
+	)
+	(port
+		(pt 0 168)
+		(input)
+		(text "scanclkena" (rect 0 0 77 16)(font "Arial" (font_size 8)))
+		(text "scanclkena" (rect 4 152 70 168)(font "Arial" (font_size 8)))
+		(line (pt 0 168)(pt 88 168)(line_width 1))
+	)
+	(port
+		(pt 0 192)
+		(input)
+		(text "configupdate" (rect 0 0 86 16)(font "Arial" (font_size 8)))
+		(text "configupdate" (rect 4 176 77 192)(font "Arial" (font_size 8)))
+		(line (pt 0 192)(pt 88 192)(line_width 1))
+	)
+	(port
+		(pt 376 72)
+		(output)
+		(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
+		(text "c0" (rect 359 56 373 72)(font "Arial" (font_size 8)))
+		(line (pt 376 72)(pt 288 72)(line_width 1))
+	)
+	(port
+		(pt 376 96)
+		(output)
+		(text "scandataout" (rect 0 0 83 16)(font "Arial" (font_size 8)))
+		(text "scandataout" (rect 302 80 373 96)(font "Arial" (font_size 8)))
+		(line (pt 376 96)(pt 288 96)(line_width 1))
+	)
+	(port
+		(pt 376 120)
+		(output)
+		(text "scandone" (rect 0 0 66 16)(font "Arial" (font_size 8)))
+		(text "scandone" (rect 317 104 373 120)(font "Arial" (font_size 8)))
+		(line (pt 376 120)(pt 288 120)(line_width 1))
+	)
+	(port
+		(pt 376 144)
+		(output)
+		(text "locked" (rect 0 0 44 16)(font "Arial" (font_size 8)))
+		(text "locked" (rect 335 128 373 144)(font "Arial" (font_size 8)))
+		(line (pt 376 144)(pt 288 144)(line_width 1))
+	)
+	(drawing
+		(text "Cyclone III" (rect 301 214 349 228)(font "Arial" ))
+		(text "inclk0 frequency: 48.000 MHz" (rect 98 123 241 137)(font "Arial" ))
+		(text "Operation Mode: Normal" (rect 98 140 213 154)(font "Arial" ))
+		(text "Clk " (rect 99 167 116 181)(font "Arial" ))
+		(text "Ratio" (rect 125 167 149 181)(font "Arial" ))
+		(text "Ph (dg)" (rect 159 167 194 181)(font "Arial" ))
+		(text "DC (%)" (rect 204 167 239 181)(font "Arial" ))
+		(text "c0" (rect 103 185 115 199)(font "Arial" ))
+		(text "2/1" (rect 131 185 146 199)(font "Arial" ))
+		(text "0.00" (rect 167 185 188 199)(font "Arial" ))
+		(text "50.00" (rect 209 185 236 199)(font "Arial" ))
+		(line (pt 0 0)(pt 377 0)(line_width 1))
+		(line (pt 377 0)(pt 377 233)(line_width 1))
+		(line (pt 0 233)(pt 377 233)(line_width 1))
+		(line (pt 0 0)(pt 0 233)(line_width 1))
+		(line (pt 96 164)(pt 246 164)(line_width 1))
+		(line (pt 96 181)(pt 246 181)(line_width 1))
+		(line (pt 96 199)(pt 246 199)(line_width 1))
+		(line (pt 96 164)(pt 96 199)(line_width 1))
+		(line (pt 122 164)(pt 122 199)(line_width 3))
+		(line (pt 156 164)(pt 156 199)(line_width 3))
+		(line (pt 201 164)(pt 201 199)(line_width 3))
+		(line (pt 245 164)(pt 245 199)(line_width 1))
+		(line (pt 88 56)(pt 288 56)(line_width 1))
+		(line (pt 288 56)(pt 288 216)(line_width 1))
+		(line (pt 88 216)(pt 288 216)(line_width 1))
+		(line (pt 88 56)(pt 88 216)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/altpll4.inc b/FPGA_quartus_GE/altpll4.inc
new file mode 100644
index 0000000..39f54c9
--- /dev/null
+++ b/FPGA_quartus_GE/altpll4.inc
@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altpll4 
+(
+	areset,
+	configupdate,
+	inclk0,
+	scanclk,
+	scanclkena,
+	scandata
+)
+
+RETURNS (
+	c0,
+	locked,
+	scandataout,
+	scandone
+);
diff --git a/FPGA_quartus_GE/altpll4.mif b/FPGA_quartus_GE/altpll4.mif
new file mode 100644
index 0000000..e50eda2
--- /dev/null
+++ b/FPGA_quartus_GE/altpll4.mif
@@ -0,0 +1,174 @@
+-- Copyright (C) 1991-2010 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- MIF file representing initial state of PLL Scan Chain
+--    Device Family: Cyclone III
+--    Device Part: -
+--    Device Speed Grade: 8
+--    PLL Scan Chain: Fast PLL (144 bits)
+--    File Name: C:\FireBee\FPGA\altpll4.mif
+--    Generated: Mon Dec 06 01:47:24 2010
+
+WIDTH=1;
+DEPTH=144;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+	0    :   0; -- Reserved Bits = 0 (1 bit(s))
+	1    :   0; -- Reserved Bits = 0 (1 bit(s))
+	2    :   0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
+	3    :   0;
+	4    :   1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27)
+	5    :   1;
+	6    :   0;
+	7    :   1;
+	8    :   1;
+	9    :   0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
+	10   :   0; -- Reserved Bits = 0 (5 bit(s))
+	11   :   0;
+	12   :   0;
+	13   :   0;
+	14   :   0;
+	15   :   0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
+	16   :   0;
+	17   :   1;
+	18   :   1; -- N counter: Bypass = 1 (1 bit(s))
+	19   :   0; -- N counter: High Count = 0 (8 bit(s))
+	20   :   0;
+	21   :   0;
+	22   :   0;
+	23   :   0;
+	24   :   0;
+	25   :   0;
+	26   :   0;
+	27   :   0; -- N counter: Odd Division = 0 (1 bit(s))
+	28   :   0; -- N counter: Low Count = 0 (8 bit(s))
+	29   :   0;
+	30   :   0;
+	31   :   0;
+	32   :   0;
+	33   :   0;
+	34   :   0;
+	35   :   0;
+	36   :   0; -- M counter: Bypass = 0 (1 bit(s))
+	37   :   0; -- M counter: High Count = 6 (8 bit(s))
+	38   :   0;
+	39   :   0;
+	40   :   0;
+	41   :   0;
+	42   :   1;
+	43   :   1;
+	44   :   0;
+	45   :   0; -- M counter: Odd Division = 0 (1 bit(s))
+	46   :   0; -- M counter: Low Count = 6 (8 bit(s))
+	47   :   0;
+	48   :   0;
+	49   :   0;
+	50   :   0;
+	51   :   1;
+	52   :   1;
+	53   :   0;
+	54   :   0; -- clk0 counter: Bypass = 0 (1 bit(s))
+	55   :   0; -- clk0 counter: High Count = 3 (8 bit(s))
+	56   :   0;
+	57   :   0;
+	58   :   0;
+	59   :   0;
+	60   :   0;
+	61   :   1;
+	62   :   1;
+	63   :   0; -- clk0 counter: Odd Division = 0 (1 bit(s))
+	64   :   0; -- clk0 counter: Low Count = 3 (8 bit(s))
+	65   :   0;
+	66   :   0;
+	67   :   0;
+	68   :   0;
+	69   :   0;
+	70   :   1;
+	71   :   1;
+	72   :   1; -- clk1 counter: Bypass = 1 (1 bit(s))
+	73   :   0; -- clk1 counter: High Count = 0 (8 bit(s))
+	74   :   0;
+	75   :   0;
+	76   :   0;
+	77   :   0;
+	78   :   0;
+	79   :   0;
+	80   :   0;
+	81   :   0; -- clk1 counter: Odd Division = 0 (1 bit(s))
+	82   :   0; -- clk1 counter: Low Count = 0 (8 bit(s))
+	83   :   0;
+	84   :   0;
+	85   :   0;
+	86   :   0;
+	87   :   0;
+	88   :   0;
+	89   :   0;
+	90   :   1; -- clk2 counter: Bypass = 1 (1 bit(s))
+	91   :   0; -- clk2 counter: High Count = 0 (8 bit(s))
+	92   :   0;
+	93   :   0;
+	94   :   0;
+	95   :   0;
+	96   :   0;
+	97   :   0;
+	98   :   0;
+	99   :   0; -- clk2 counter: Odd Division = 0 (1 bit(s))
+	100  :   0; -- clk2 counter: Low Count = 0 (8 bit(s))
+	101  :   0;
+	102  :   0;
+	103  :   0;
+	104  :   0;
+	105  :   0;
+	106  :   0;
+	107  :   0;
+	108  :   1; -- clk3 counter: Bypass = 1 (1 bit(s))
+	109  :   0; -- clk3 counter: High Count = 0 (8 bit(s))
+	110  :   0;
+	111  :   0;
+	112  :   0;
+	113  :   0;
+	114  :   0;
+	115  :   0;
+	116  :   0;
+	117  :   0; -- clk3 counter: Odd Division = 0 (1 bit(s))
+	118  :   0; -- clk3 counter: Low Count = 0 (8 bit(s))
+	119  :   0;
+	120  :   0;
+	121  :   0;
+	122  :   0;
+	123  :   0;
+	124  :   0;
+	125  :   0;
+	126  :   1; -- clk4 counter: Bypass = 1 (1 bit(s))
+	127  :   0; -- clk4 counter: High Count = 0 (8 bit(s))
+	128  :   0;
+	129  :   0;
+	130  :   0;
+	131  :   0;
+	132  :   0;
+	133  :   0;
+	134  :   0;
+	135  :   0; -- clk4 counter: Odd Division = 0 (1 bit(s))
+	136  :   0; -- clk4 counter: Low Count = 0 (8 bit(s))
+	137  :   0;
+	138  :   0;
+	139  :   0;
+	140  :   0;
+	141  :   0;
+	142  :   0;
+	143  :   0;
+END;
diff --git a/FPGA_quartus_GE/altpll4.ppf b/FPGA_quartus_GE/altpll4.ppf
new file mode 100644
index 0000000..541ce91
--- /dev/null
+++ b/FPGA_quartus_GE/altpll4.ppf
@@ -0,0 +1,17 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="altpll4" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="configupdate" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="scanclk" direction="input" scope="external" source="clock"  />
+<pin name="scanclkena" direction="input" scope="external"  />
+<pin name="scandata" direction="input" scope="external"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+<pin name="scandataout" direction="output" scope="external"  />
+<pin name="scandone" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/FPGA_quartus_GE/altpll4.qip b/FPGA_quartus_GE/altpll4.qip
new file mode 100644
index 0000000..f44acdc
--- /dev/null
+++ b/FPGA_quartus_GE/altpll4.qip
@@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.tdf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll4.ppf"]
diff --git a/FPGA_quartus_GE/altpll4.tdf b/FPGA_quartus_GE/altpll4.tdf
new file mode 100644
index 0000000..3ec77d4
--- /dev/null
+++ b/FPGA_quartus_GE/altpll4.tdf
@@ -0,0 +1,298 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: altpll4.tdf
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+INCLUDE "altpll.inc";
+
+
+
+SUBDESIGN altpll4
+(
+	areset	 : INPUT = GND;
+	configupdate	 : INPUT = GND;
+	inclk0	 : INPUT = GND;
+	scanclk	 : INPUT = VCC;
+	scanclkena	 : INPUT = GND;
+	scandata	 : INPUT = GND;
+	c0	 : OUTPUT;
+	locked	 : OUTPUT;
+	scandataout	 : OUTPUT;
+	scandone	 : OUTPUT;
+)
+
+VARIABLE
+
+	altpll_component : altpll WITH (
+			BANDWIDTH_TYPE = "AUTO",
+			CLK0_DIVIDE_BY = 1,
+			CLK0_DUTY_CYCLE = 50,
+			CLK0_MULTIPLY_BY = 2,
+			CLK0_PHASE_SHIFT = "0",
+			COMPENSATE_CLOCK = "CLK0",
+			INCLK0_INPUT_FREQUENCY = 20833,
+			INTENDED_DEVICE_FAMILY = "Cyclone III",
+			LPM_TYPE = "altpll",
+			OPERATION_MODE = "NORMAL",
+			PLL_TYPE = "AUTO",
+			PORT_ACTIVECLOCK = "PORT_UNUSED",
+			PORT_ARESET = "PORT_USED",
+			PORT_CLKBAD0 = "PORT_UNUSED",
+			PORT_CLKBAD1 = "PORT_UNUSED",
+			PORT_CLKLOSS = "PORT_UNUSED",
+			PORT_CLKSWITCH = "PORT_UNUSED",
+			PORT_CONFIGUPDATE = "PORT_USED",
+			PORT_FBIN = "PORT_UNUSED",
+			PORT_INCLK0 = "PORT_USED",
+			PORT_INCLK1 = "PORT_UNUSED",
+			PORT_LOCKED = "PORT_USED",
+			PORT_PFDENA = "PORT_UNUSED",
+			PORT_PHASECOUNTERSELECT = "PORT_UNUSED",
+			PORT_PHASEDONE = "PORT_UNUSED",
+			PORT_PHASESTEP = "PORT_UNUSED",
+			PORT_PHASEUPDOWN = "PORT_UNUSED",
+			PORT_PLLENA = "PORT_UNUSED",
+			PORT_SCANACLR = "PORT_UNUSED",
+			PORT_SCANCLK = "PORT_USED",
+			PORT_SCANCLKENA = "PORT_USED",
+			PORT_SCANDATA = "PORT_USED",
+			PORT_SCANDATAOUT = "PORT_USED",
+			PORT_SCANDONE = "PORT_USED",
+			PORT_SCANREAD = "PORT_UNUSED",
+			PORT_SCANWRITE = "PORT_UNUSED",
+			PORT_clk0 = "PORT_USED",
+			PORT_clk1 = "PORT_UNUSED",
+			PORT_clk2 = "PORT_UNUSED",
+			PORT_clk3 = "PORT_UNUSED",
+			PORT_clk4 = "PORT_UNUSED",
+			PORT_clk5 = "PORT_UNUSED",
+			PORT_clkena0 = "PORT_UNUSED",
+			PORT_clkena1 = "PORT_UNUSED",
+			PORT_clkena2 = "PORT_UNUSED",
+			PORT_clkena3 = "PORT_UNUSED",
+			PORT_clkena4 = "PORT_UNUSED",
+			PORT_clkena5 = "PORT_UNUSED",
+			PORT_extclk0 = "PORT_UNUSED",
+			PORT_extclk1 = "PORT_UNUSED",
+			PORT_extclk2 = "PORT_UNUSED",
+			PORT_extclk3 = "PORT_UNUSED",
+			SELF_RESET_ON_LOSS_LOCK = "OFF",
+			WIDTH_CLOCK = 5,
+			scan_chain_mif_file = "altpll4.mif"
+			);
+
+BEGIN
+
+	c0 = altpll_component.clk[0..0];
+	scandone = altpll_component.scandone;
+	scandataout = altpll_component.scandataout;
+	locked = altpll_component.locked;
+	altpll_component.scanclkena = scanclkena;
+	altpll_component.inclk[0..0] = inclk0;
+	altpll_component.inclk[1..1] = GND;
+	altpll_component.scandata = scandata;
+	altpll_component.areset = areset;
+	altpll_component.scanclk = scanclk;
+	altpll_component.configupdate = configupdate;
+END;
+
+
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "336.000"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "144.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpll4.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: CONSTANT: scan_chain_mif_file STRING "altpll4.mif"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
+-- Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena"
+-- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
+-- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
+-- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
+-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
+-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
+-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.tdf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4_inst.tdf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll4.mif TRUE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/FPGA_quartus_GE/altpll_reconfig0.bsf b/FPGA_quartus_GE/altpll_reconfig0.bsf
new file mode 100644
index 0000000..452f320
--- /dev/null
+++ b/FPGA_quartus_GE/altpll_reconfig0.bsf
@@ -0,0 +1,162 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 216 296)
+	(text "altpll_reconfig0" (rect 54 1 182 20)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 277 31 292)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "reconfig" (rect 0 0 53 16)(font "Arial" (font_size 8)))
+		(text "reconfig" (rect 20 32 65 48)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 16 40)(line_width 1))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "read_param" (rect 0 0 80 16)(font "Arial" (font_size 8)))
+		(text "read_param" (rect 20 48 88 64)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "write_param" (rect 0 0 82 16)(font "Arial" (font_size 8)))
+		(text "write_param" (rect 20 64 90 80)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "data_in[8..0]" (rect 0 0 84 16)(font "Arial" (font_size 8)))
+		(text "data_in[8..0]" (rect 20 88 92 104)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 16 96)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "counter_type[3..0]" (rect 0 0 123 16)(font "Arial" (font_size 8)))
+		(text "counter_type[3..0]" (rect 20 104 125 120)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 16 112)(line_width 3))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "counter_param[2..0]" (rect 0 0 136 16)(font "Arial" (font_size 8)))
+		(text "counter_param[2..0]" (rect 20 120 136 136)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 16 128)(line_width 3))
+	)
+	(port
+		(pt 0 168)
+		(input)
+		(text "pll_scandataout" (rect 0 0 107 16)(font "Arial" (font_size 8)))
+		(text "pll_scandataout" (rect 20 160 111 176)(font "Arial" (font_size 8)))
+		(line (pt 0 168)(pt 16 168)(line_width 1))
+	)
+	(port
+		(pt 0 184)
+		(input)
+		(text "pll_scandone" (rect 0 0 89 16)(font "Arial" (font_size 8)))
+		(text "pll_scandone" (rect 20 176 96 192)(font "Arial" (font_size 8)))
+		(line (pt 0 184)(pt 16 184)(line_width 1))
+	)
+	(port
+		(pt 0 208)
+		(input)
+		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+		(text "clock" (rect 20 200 51 216)(font "Arial" (font_size 8)))
+		(line (pt 0 208)(pt 16 208)(line_width 1))
+	)
+	(port
+		(pt 0 224)
+		(input)
+		(text "reset" (rect 0 0 34 16)(font "Arial" (font_size 8)))
+		(text "reset" (rect 20 216 49 232)(font "Arial" (font_size 8)))
+		(line (pt 0 224)(pt 16 224)(line_width 1))
+	)
+	(port
+		(pt 0 248)
+		(input)
+		(text "pll_areset_in" (rect 0 0 86 16)(font "Arial" (font_size 8)))
+		(text "pll_areset_in" (rect 20 240 93 256)(font "Arial" (font_size 8)))
+		(line (pt 0 248)(pt 16 248)(line_width 1))
+	)
+	(port
+		(pt 216 40)
+		(output)
+		(text "busy" (rect 0 0 33 16)(font "Arial" (font_size 8)))
+		(text "busy" (rect 169 32 197 48)(font "Arial" (font_size 8)))
+		(line (pt 216 40)(pt 200 40)(line_width 1))
+	)
+	(port
+		(pt 216 96)
+		(output)
+		(text "data_out[8..0]" (rect 0 0 94 16)(font "Arial" (font_size 8)))
+		(text "data_out[8..0]" (rect 117 88 197 104)(font "Arial" (font_size 8)))
+		(line (pt 216 96)(pt 200 96)(line_width 3))
+	)
+	(port
+		(pt 216 152)
+		(output)
+		(text "pll_scandata" (rect 0 0 86 16)(font "Arial" (font_size 8)))
+		(text "pll_scandata" (rect 124 144 197 160)(font "Arial" (font_size 8)))
+		(line (pt 216 152)(pt 200 152)(line_width 1))
+	)
+	(port
+		(pt 216 168)
+		(output)
+		(text "pll_scanclk" (rect 0 0 76 16)(font "Arial" (font_size 8)))
+		(text "pll_scanclk" (rect 132 160 197 176)(font "Arial" (font_size 8)))
+		(line (pt 216 168)(pt 200 168)(line_width 1))
+	)
+	(port
+		(pt 216 200)
+		(output)
+		(text "pll_scanclkena" (rect 0 0 101 16)(font "Arial" (font_size 8)))
+		(text "pll_scanclkena" (rect 111 192 197 208)(font "Arial" (font_size 8)))
+		(line (pt 216 200)(pt 200 200)(line_width 1))
+	)
+	(port
+		(pt 216 216)
+		(output)
+		(text "pll_configupdate" (rect 0 0 109 16)(font "Arial" (font_size 8)))
+		(text "pll_configupdate" (rect 104 208 197 224)(font "Arial" (font_size 8)))
+		(line (pt 216 216)(pt 200 216)(line_width 1))
+	)
+	(port
+		(pt 216 248)
+		(output)
+		(text "pll_areset" (rect 0 0 66 16)(font "Arial" (font_size 8)))
+		(text "pll_areset" (rect 141 240 197 256)(font "Arial" (font_size 8)))
+		(line (pt 216 248)(pt 200 248)(line_width 1))
+	)
+	(drawing
+		(line (pt 0 0)(pt 217 0)(line_width 1))
+		(line (pt 217 0)(pt 217 297)(line_width 1))
+		(line (pt 0 297)(pt 217 297)(line_width 1))
+		(line (pt 0 0)(pt 0 297)(line_width 1))
+		(line (pt 16 24)(pt 201 24)(line_width 1))
+		(line (pt 201 24)(pt 201 273)(line_width 1))
+		(line (pt 16 273)(pt 201 273)(line_width 1))
+		(line (pt 16 24)(pt 16 273)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/altpll_reconfig0.qip b/FPGA_quartus_GE/altpll_reconfig0.qip
new file mode 100644
index 0000000..3194459
--- /dev/null
+++ b/FPGA_quartus_GE/altpll_reconfig0.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig0.tdf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig0.cmp"]
diff --git a/FPGA_quartus_GE/altpll_reconfig1.bsf b/FPGA_quartus_GE/altpll_reconfig1.bsf
new file mode 100644
index 0000000..f896607
--- /dev/null
+++ b/FPGA_quartus_GE/altpll_reconfig1.bsf
@@ -0,0 +1,162 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 216 296)
+	(text "altpll_reconfig1" (rect 54 1 182 20)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 277 31 292)(font "Arial" ))
+	(port
+		(pt 0 40)
+		(input)
+		(text "reconfig" (rect 0 0 53 16)(font "Arial" (font_size 8)))
+		(text "reconfig" (rect 20 32 65 48)(font "Arial" (font_size 8)))
+		(line (pt 0 40)(pt 16 40)(line_width 1))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "read_param" (rect 0 0 80 16)(font "Arial" (font_size 8)))
+		(text "read_param" (rect 20 48 88 64)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 16 56)(line_width 1))
+	)
+	(port
+		(pt 0 72)
+		(input)
+		(text "write_param" (rect 0 0 82 16)(font "Arial" (font_size 8)))
+		(text "write_param" (rect 20 64 90 80)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 16 72)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "data_in[8..0]" (rect 0 0 84 16)(font "Arial" (font_size 8)))
+		(text "data_in[8..0]" (rect 20 88 92 104)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 16 96)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "counter_type[3..0]" (rect 0 0 123 16)(font "Arial" (font_size 8)))
+		(text "counter_type[3..0]" (rect 20 104 125 120)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 16 112)(line_width 3))
+	)
+	(port
+		(pt 0 128)
+		(input)
+		(text "counter_param[2..0]" (rect 0 0 136 16)(font "Arial" (font_size 8)))
+		(text "counter_param[2..0]" (rect 20 120 136 136)(font "Arial" (font_size 8)))
+		(line (pt 0 128)(pt 16 128)(line_width 3))
+	)
+	(port
+		(pt 0 168)
+		(input)
+		(text "pll_scandataout" (rect 0 0 107 16)(font "Arial" (font_size 8)))
+		(text "pll_scandataout" (rect 20 160 111 176)(font "Arial" (font_size 8)))
+		(line (pt 0 168)(pt 16 168)(line_width 1))
+	)
+	(port
+		(pt 0 184)
+		(input)
+		(text "pll_scandone" (rect 0 0 89 16)(font "Arial" (font_size 8)))
+		(text "pll_scandone" (rect 20 176 96 192)(font "Arial" (font_size 8)))
+		(line (pt 0 184)(pt 16 184)(line_width 1))
+	)
+	(port
+		(pt 0 208)
+		(input)
+		(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
+		(text "clock" (rect 20 200 51 216)(font "Arial" (font_size 8)))
+		(line (pt 0 208)(pt 16 208)(line_width 1))
+	)
+	(port
+		(pt 0 224)
+		(input)
+		(text "reset" (rect 0 0 34 16)(font "Arial" (font_size 8)))
+		(text "reset" (rect 20 216 49 232)(font "Arial" (font_size 8)))
+		(line (pt 0 224)(pt 16 224)(line_width 1))
+	)
+	(port
+		(pt 0 248)
+		(input)
+		(text "pll_areset_in" (rect 0 0 86 16)(font "Arial" (font_size 8)))
+		(text "pll_areset_in" (rect 20 240 93 256)(font "Arial" (font_size 8)))
+		(line (pt 0 248)(pt 16 248)(line_width 1))
+	)
+	(port
+		(pt 216 40)
+		(output)
+		(text "busy" (rect 0 0 33 16)(font "Arial" (font_size 8)))
+		(text "busy" (rect 169 32 197 48)(font "Arial" (font_size 8)))
+		(line (pt 216 40)(pt 200 40)(line_width 1))
+	)
+	(port
+		(pt 216 96)
+		(output)
+		(text "data_out[8..0]" (rect 0 0 94 16)(font "Arial" (font_size 8)))
+		(text "data_out[8..0]" (rect 117 88 197 104)(font "Arial" (font_size 8)))
+		(line (pt 216 96)(pt 200 96)(line_width 3))
+	)
+	(port
+		(pt 216 152)
+		(output)
+		(text "pll_scandata" (rect 0 0 86 16)(font "Arial" (font_size 8)))
+		(text "pll_scandata" (rect 124 144 197 160)(font "Arial" (font_size 8)))
+		(line (pt 216 152)(pt 200 152)(line_width 1))
+	)
+	(port
+		(pt 216 168)
+		(output)
+		(text "pll_scanclk" (rect 0 0 76 16)(font "Arial" (font_size 8)))
+		(text "pll_scanclk" (rect 132 160 197 176)(font "Arial" (font_size 8)))
+		(line (pt 216 168)(pt 200 168)(line_width 1))
+	)
+	(port
+		(pt 216 200)
+		(output)
+		(text "pll_scanclkena" (rect 0 0 101 16)(font "Arial" (font_size 8)))
+		(text "pll_scanclkena" (rect 111 192 197 208)(font "Arial" (font_size 8)))
+		(line (pt 216 200)(pt 200 200)(line_width 1))
+	)
+	(port
+		(pt 216 216)
+		(output)
+		(text "pll_configupdate" (rect 0 0 109 16)(font "Arial" (font_size 8)))
+		(text "pll_configupdate" (rect 104 208 197 224)(font "Arial" (font_size 8)))
+		(line (pt 216 216)(pt 200 216)(line_width 1))
+	)
+	(port
+		(pt 216 248)
+		(output)
+		(text "pll_areset" (rect 0 0 66 16)(font "Arial" (font_size 8)))
+		(text "pll_areset" (rect 141 240 197 256)(font "Arial" (font_size 8)))
+		(line (pt 216 248)(pt 200 248)(line_width 1))
+	)
+	(drawing
+		(line (pt 0 0)(pt 217 0)(line_width 1))
+		(line (pt 217 0)(pt 217 297)(line_width 1))
+		(line (pt 0 297)(pt 217 297)(line_width 1))
+		(line (pt 0 0)(pt 0 297)(line_width 1))
+		(line (pt 16 24)(pt 201 24)(line_width 1))
+		(line (pt 201 24)(pt 201 273)(line_width 1))
+		(line (pt 16 273)(pt 201 273)(line_width 1))
+		(line (pt 16 24)(pt 16 273)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/altpll_reconfig1.inc b/FPGA_quartus_GE/altpll_reconfig1.inc
new file mode 100644
index 0000000..c1a6e65
--- /dev/null
+++ b/FPGA_quartus_GE/altpll_reconfig1.inc
@@ -0,0 +1,39 @@
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION altpll_reconfig1 
+(
+	clock,
+	counter_param[2..0],
+	counter_type[3..0],
+	data_in[8..0],
+	pll_areset_in,
+	pll_scandataout,
+	pll_scandone,
+	read_param,
+	reconfig,
+	reset,
+	write_param
+)
+
+RETURNS (
+	busy,
+	data_out[8..0],
+	pll_areset,
+	pll_configupdate,
+	pll_scanclk,
+	pll_scanclkena,
+	pll_scandata
+);
diff --git a/FPGA_quartus_GE/altpll_reconfig1.qip b/FPGA_quartus_GE/altpll_reconfig1.qip
new file mode 100644
index 0000000..713a3c3
--- /dev/null
+++ b/FPGA_quartus_GE/altpll_reconfig1.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG"
+set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.tdf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll_reconfig1.cmp"]
diff --git a/FPGA_quartus_GE/altpll_reconfig1.tdf b/FPGA_quartus_GE/altpll_reconfig1.tdf
new file mode 100644
index 0000000..82ad4ff
--- /dev/null
+++ b/FPGA_quartus_GE/altpll_reconfig1.tdf
@@ -0,0 +1,144 @@
+-- megafunction wizard: %ALTPLL_RECONFIG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll_reconfig 
+
+-- ============================================================
+-- File Name: altpll_reconfig1.tdf
+-- Megafunction Name(s):
+-- 			altpll_reconfig
+--
+-- Simulation Library Files(s):
+-- 			altera_mf;cycloneiii;lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+-- Clearbox generated function header
+FUNCTION altpll_reconfig1_pllrcfg_t4q (clock, counter_param[2..0], counter_type[3..0], data_in[8..0], pll_areset_in, pll_scandataout, pll_scandone, read_param, reconfig, reset, write_param)
+RETURNS ( busy, data_out[8..0], pll_areset, pll_configupdate, pll_scanclk, pll_scanclkena, pll_scandata);
+
+
+
+
+SUBDESIGN altpll_reconfig1
+(
+	clock	 : INPUT;
+	counter_param[2..0]	 : INPUT;
+	counter_type[3..0]	 : INPUT;
+	data_in[8..0]	 : INPUT;
+	pll_areset_in	 : INPUT = GND;
+	pll_scandataout	 : INPUT;
+	pll_scandone	 : INPUT;
+	read_param	 : INPUT;
+	reconfig	 : INPUT;
+	reset	 : INPUT;
+	write_param	 : INPUT;
+	busy	 : OUTPUT;
+	data_out[8..0]	 : OUTPUT;
+	pll_areset	 : OUTPUT;
+	pll_configupdate	 : OUTPUT;
+	pll_scanclk	 : OUTPUT;
+	pll_scanclkena	 : OUTPUT;
+	pll_scandata	 : OUTPUT;
+)
+
+VARIABLE
+
+	altpll_reconfig1_pllrcfg_t4q_component : altpll_reconfig1_pllrcfg_t4q;
+
+BEGIN
+
+	pll_areset = altpll_reconfig1_pllrcfg_t4q_component.pll_areset;
+	pll_scanclkena = altpll_reconfig1_pllrcfg_t4q_component.pll_scanclkena;
+	pll_scanclk = altpll_reconfig1_pllrcfg_t4q_component.pll_scanclk;
+	busy = altpll_reconfig1_pllrcfg_t4q_component.busy;
+	data_out[8..0] = altpll_reconfig1_pllrcfg_t4q_component.data_out[8..0];
+	pll_scandata = altpll_reconfig1_pllrcfg_t4q_component.pll_scandata;
+	pll_configupdate = altpll_reconfig1_pllrcfg_t4q_component.pll_configupdate;
+	altpll_reconfig1_pllrcfg_t4q_component.reconfig = reconfig;
+	altpll_reconfig1_pllrcfg_t4q_component.counter_type[3..0] = counter_type[3..0];
+	altpll_reconfig1_pllrcfg_t4q_component.pll_scandone = pll_scandone;
+	altpll_reconfig1_pllrcfg_t4q_component.pll_scandataout = pll_scandataout;
+	altpll_reconfig1_pllrcfg_t4q_component.pll_areset_in = pll_areset_in;
+	altpll_reconfig1_pllrcfg_t4q_component.read_param = read_param;
+	altpll_reconfig1_pllrcfg_t4q_component.reset = reset;
+	altpll_reconfig1_pllrcfg_t4q_component.data_in[8..0] = data_in[8..0];
+	altpll_reconfig1_pllrcfg_t4q_component.clock = clock;
+	altpll_reconfig1_pllrcfg_t4q_component.counter_param[2..0] = counter_param[2..0];
+	altpll_reconfig1_pllrcfg_t4q_component.write_param = write_param;
+END;
+
+
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: CHAIN_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_NAME STRING "./altpll4.mif"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_INIT_FILE STRING "0"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+-- Retrieval info: USED_PORT: counter_param 0 0 3 0 INPUT NODEFVAL "counter_param[2..0]"
+-- Retrieval info: USED_PORT: counter_type 0 0 4 0 INPUT NODEFVAL "counter_type[3..0]"
+-- Retrieval info: USED_PORT: data_in 0 0 9 0 INPUT NODEFVAL "data_in[8..0]"
+-- Retrieval info: USED_PORT: data_out 0 0 9 0 OUTPUT NODEFVAL "data_out[8..0]"
+-- Retrieval info: USED_PORT: pll_areset 0 0 0 0 OUTPUT NODEFVAL "pll_areset"
+-- Retrieval info: USED_PORT: pll_areset_in 0 0 0 0 INPUT GND "pll_areset_in"
+-- Retrieval info: USED_PORT: pll_configupdate 0 0 0 0 OUTPUT NODEFVAL "pll_configupdate"
+-- Retrieval info: USED_PORT: pll_scanclk 0 0 0 0 OUTPUT NODEFVAL "pll_scanclk"
+-- Retrieval info: USED_PORT: pll_scanclkena 0 0 0 0 OUTPUT NODEFVAL "pll_scanclkena"
+-- Retrieval info: USED_PORT: pll_scandata 0 0 0 0 OUTPUT NODEFVAL "pll_scandata"
+-- Retrieval info: USED_PORT: pll_scandataout 0 0 0 0 INPUT NODEFVAL "pll_scandataout"
+-- Retrieval info: USED_PORT: pll_scandone 0 0 0 0 INPUT NODEFVAL "pll_scandone"
+-- Retrieval info: USED_PORT: read_param 0 0 0 0 INPUT NODEFVAL "read_param"
+-- Retrieval info: USED_PORT: reconfig 0 0 0 0 INPUT NODEFVAL "reconfig"
+-- Retrieval info: USED_PORT: reset 0 0 0 0 INPUT NODEFVAL "reset"
+-- Retrieval info: USED_PORT: write_param 0 0 0 0 INPUT NODEFVAL "write_param"
+-- Retrieval info: CONNECT: @data_in 0 0 9 0 data_in 0 0 9 0
+-- Retrieval info: CONNECT: @reset 0 0 0 0 reset 0 0 0 0
+-- Retrieval info: CONNECT: @pll_scandone 0 0 0 0 pll_scandone 0 0 0 0
+-- Retrieval info: CONNECT: @read_param 0 0 0 0 read_param 0 0 0 0
+-- Retrieval info: CONNECT: @counter_type 0 0 4 0 counter_type 0 0 4 0
+-- Retrieval info: CONNECT: @pll_areset_in 0 0 0 0 pll_areset_in 0 0 0 0
+-- Retrieval info: CONNECT: @pll_scandataout 0 0 0 0 pll_scandataout 0 0 0 0
+-- Retrieval info: CONNECT: @write_param 0 0 0 0 write_param 0 0 0 0
+-- Retrieval info: CONNECT: pll_areset 0 0 0 0 @pll_areset 0 0 0 0
+-- Retrieval info: CONNECT: pll_configupdate 0 0 0 0 @pll_configupdate 0 0 0 0
+-- Retrieval info: CONNECT: data_out 0 0 9 0 @data_out 0 0 9 0
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: pll_scanclkena 0 0 0 0 @pll_scanclkena 0 0 0 0
+-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
+-- Retrieval info: CONNECT: @counter_param 0 0 3 0 counter_param 0 0 3 0
+-- Retrieval info: CONNECT: @reconfig 0 0 0 0 reconfig 0 0 0 0
+-- Retrieval info: CONNECT: pll_scandata 0 0 0 0 @pll_scandata 0 0 0 0
+-- Retrieval info: CONNECT: pll_scanclk 0 0 0 0 @pll_scanclk 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.tdf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll_reconfig1_inst.tdf FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: LIB_FILE: cycloneiii
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/altpll_reconfig1_pllrcfg_bju.tdf b/FPGA_quartus_GE/altpll_reconfig1_pllrcfg_bju.tdf
new file mode 100644
index 0000000..81695ae
--- /dev/null
+++ b/FPGA_quartus_GE/altpll_reconfig1_pllrcfg_bju.tdf
@@ -0,0 +1,583 @@
+--altpll_reconfig CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone III" init_from_rom="NO" scan_init_file="./altpll4.mif" busy clock counter_param counter_type data_in data_out pll_areset pll_areset_in pll_configupdate pll_scanclk pll_scanclkena pll_scandata pll_scandataout pll_scandone read_param reconfig reset write_param
+--VERSION_BEGIN 9.1SP2 cbx_altpll_reconfig 2010:03:24:20:43:42:SJ cbx_altsyncram 2010:03:24:20:43:42:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_lpm_add_sub 2010:03:24:20:43:43:SJ cbx_lpm_compare 2010:03:24:20:43:43:SJ cbx_lpm_counter 2010:03:24:20:43:43:SJ cbx_lpm_decode 2010:03:24:20:43:43:SJ cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ cbx_util_mgl 2010:03:24:20:43:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2010 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+include "altsyncram.inc";
+FUNCTION cycloneiii_lcell_comb (cin, dataa, datab, datac, datad)
+WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT)
+RETURNS ( combout, cout);
+FUNCTION lpm_add_sub (aclr, add_sub, cin, clken, clock, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0])
+WITH ( CARRY_CHAIN, CARRY_CHAIN_LENGTH, LPM_DIRECTION, LPM_PIPELINE, LPM_REPRESENTATION, LPM_WIDTH, ONE_INPUT_IS_CONSTANT, REGISTERED_AT_END, USE_WYS)
+RETURNS ( cout, overflow, result[LPM_WIDTH-1..0]);
+FUNCTION lpm_compare (aclr, clken, clock, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0])
+WITH ( LPM_PIPELINE, LPM_REPRESENTATION, LPM_WIDTH, ONE_INPUT_IS_CONSTANT)
+RETURNS ( aeb, agb, ageb, alb, aleb, aneb);
+FUNCTION lpm_counter (aclr, aload, aset, cin, clk_en, clock, cnt_en, data[LPM_WIDTH-1..0], sclr, sload, sset, updown)
+WITH ( lpm_avalue, lpm_direction, lpm_modulus, lpm_port_updown, lpm_pvalue, lpm_svalue, lpm_width)
+RETURNS ( cout, eq[15..0], q[LPM_WIDTH-1..0]);
+FUNCTION lpm_decode (aclr, clken, clock, data[LPM_WIDTH-1..0], enable)
+WITH ( CASCADE_CHAIN, IGNORE_CASCADE_BUFFERS, LPM_DECODES, LPM_PIPELINE, LPM_WIDTH)
+RETURNS ( eq[LPM_DECODES-1..0]);
+
+--synthesis_resources = altsyncram 1 lpm_add_sub 2 lpm_compare 1 lpm_counter 7 lpm_decode 1 lut 3 reg 80 
+OPTIONS ALTERA_INTERNAL_OPTION = "ADV_NETLIST_OPT_ALLOWED=""NEVER_ALLOW"";suppress_da_rule_internal=C106;{-to le_comb10} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=2;{-to le_comb8} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=0;{-to le_comb9} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=1;{-to idle_state} POWER_UP_LEVEL=LOW;{-to read_data_nominal_state} POWER_UP_LEVEL=LOW;{-to read_data_state} POWER_UP_LEVEL=LOW;{-to read_first_nominal_state} POWER_UP_LEVEL=LOW;{-to read_first_state} POWER_UP_LEVEL=LOW;{-to read_init_nominal_state} POWER_UP_LEVEL=LOW;{-to read_init_state} POWER_UP_LEVEL=LOW;{-to read_last_nominal_state} POWER_UP_LEVEL=LOW;{-to read_last_state} POWER_UP_LEVEL=LOW;{-to reconfig_counter_state} POWER_UP_LEVEL=LOW;{-to reconfig_init_state} POWER_UP_LEVEL=LOW;{-to reconfig_post_state} POWER_UP_LEVEL=LOW;{-to reconfig_seq_data_state} POWER_UP_LEVEL=LOW;{-to reconfig_seq_ena_state} POWER_UP_LEVEL=LOW;{-to reconfig_wait_state} POWER_UP_LEVEL=LOW;{-to reset_state} POWER_UP_LEVEL=HIGH;{-to write_data_state} POWER_UP_LEVEL=LOW;{-to write_init_nominal_state} POWER_UP_LEVEL=LOW;{-to write_init_state} POWER_UP_LEVEL=LOW;{-to write_nominal_state} POWER_UP_LEVEL=LOW";
+
+SUBDESIGN altpll_reconfig1_pllrcfg_bju
+( 
+	busy	:	output;
+	clock	:	input;
+	counter_param[2..0]	:	input;
+	counter_type[3..0]	:	input;
+	data_in[8..0]	:	input;
+	data_out[8..0]	:	output;
+	pll_areset	:	output;
+	pll_areset_in	:	input;
+	pll_configupdate	:	output;
+	pll_scanclk	:	output;
+	pll_scanclkena	:	output;
+	pll_scandata	:	output;
+	pll_scandataout	:	input;
+	pll_scandone	:	input;
+	read_param	:	input;
+	reconfig	:	input;
+	reset	:	input;
+	write_param	:	input;
+) 
+VARIABLE 
+	altsyncram4 : altsyncram
+		WITH (
+			INIT_FILE = "./altpll4.mif",
+			NUMWORDS_A = 144,
+			OPERATION_MODE = "SINGLE_PORT",
+			WIDTH_A = 1,
+			WIDTH_BYTEENA_A = 1,
+			WIDTHAD_A = 8
+		);
+	le_comb10 : cycloneiii_lcell_comb
+		WITH (
+			DONT_TOUCH = "on",
+			LUT_MASK = "F0F0",
+			SUM_LUTC_INPUT = "datac"
+		);
+	le_comb8 : cycloneiii_lcell_comb
+		WITH (
+			DONT_TOUCH = "on",
+			LUT_MASK = "AAAA",
+			SUM_LUTC_INPUT = "datac"
+		);
+	le_comb9 : cycloneiii_lcell_comb
+		WITH (
+			DONT_TOUCH = "on",
+			LUT_MASK = "CCCC",
+			SUM_LUTC_INPUT = "datac"
+		);
+	areset_init_state_1 : dffe;
+	areset_state : dffe;
+	C0_data_state : dffe;
+	C0_ena_state : dffe;
+	C1_data_state : dffe;
+	C1_ena_state : dffe;
+	C2_data_state : dffe;
+	C2_ena_state : dffe;
+	C3_data_state : dffe;
+	C3_ena_state : dffe;
+	C4_data_state : dffe;
+	C4_ena_state : dffe;
+	configupdate2_state : dffe;
+	configupdate3_state : dffe;
+	configupdate_state : dffe;
+	counter_param_latch_reg[2..0] : dffe;
+	counter_type_latch_reg[3..0] : dffe;
+	idle_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	nominal_data[17..0] : dffe;
+	read_data_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_data_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_first_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_first_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_init_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_init_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_last_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_last_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_counter_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_init_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_post_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_seq_data_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_seq_ena_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_wait_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reset_state : dffe
+		WITH (
+			power_up = "high"
+		);
+	shift_reg[17..0] : dffeas;
+	tmp_nominal_data_out_state : dffe;
+	tmp_seq_ena_state : dffe;
+	write_data_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	write_init_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	write_init_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	write_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	add_sub5 : lpm_add_sub
+		WITH (
+			LPM_WIDTH = 9
+		);
+	add_sub6 : lpm_add_sub
+		WITH (
+			LPM_WIDTH = 8
+		);
+	cmpr7 : lpm_compare
+		WITH (
+			LPM_WIDTH = 8
+		);
+	cntr1 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_modulus = 144,
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 8
+		);
+	cntr12 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_modulus = 144,
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 8
+		);
+	cntr13 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 6
+		);
+	cntr14 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 5
+		);
+	cntr15 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_modulus = 144,
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 8
+		);
+	cntr2 : lpm_counter
+		WITH (
+			lpm_direction = "UP",
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 8
+		);
+	cntr3 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 5
+		);
+	decode11 : lpm_decode
+		WITH (
+			LPM_DECODES = 5,
+			LPM_WIDTH = 3
+		);
+	addr_counter_enable	: WIRE;
+	addr_counter_out[7..0]	: WIRE;
+	addr_counter_sload	: WIRE;
+	addr_counter_sload_value[7..0]	: WIRE;
+	addr_decoder_out[7..0]	: WIRE;
+	c0_wire[7..0]	: WIRE;
+	c1_wire[7..0]	: WIRE;
+	c2_wire[7..0]	: WIRE;
+	c3_wire[7..0]	: WIRE;
+	c4_wire[7..0]	: WIRE;
+	counter_param_latch[2..0]	: WIRE;
+	counter_type_latch[3..0]	: WIRE;
+	cuda_combout_wire[2..0]	: WIRE;
+	dummy_scandataout	: WIRE;
+	encode_out[2..0]	: WIRE;
+	input_latch_enable	: WIRE;
+	power_up	: WIRE;
+	read_addr_counter_enable	: WIRE;
+	read_addr_counter_out[7..0]	: WIRE;
+	read_addr_counter_sload	: WIRE;
+	read_addr_counter_sload_value[7..0]	: WIRE;
+	read_addr_decoder_out[7..0]	: WIRE;
+	read_nominal_out	: WIRE;
+	reconfig_addr_counter_enable	: WIRE;
+	reconfig_addr_counter_out[7..0]	: WIRE;
+	reconfig_addr_counter_sload	: WIRE;
+	reconfig_addr_counter_sload_value[7..0]	: WIRE;
+	reconfig_done	: WIRE;
+	reconfig_post_done	: WIRE;
+	reconfig_width_counter_done	: WIRE;
+	reconfig_width_counter_enable	: WIRE;
+	reconfig_width_counter_sload	: WIRE;
+	reconfig_width_counter_sload_value[5..0]	: WIRE;
+	rotate_addr_counter_enable	: WIRE;
+	rotate_addr_counter_out[7..0]	: WIRE;
+	rotate_addr_counter_sload	: WIRE;
+	rotate_addr_counter_sload_value[7..0]	: WIRE;
+	rotate_decoder_wires[4..0]	: WIRE;
+	rotate_width_counter_done	: WIRE;
+	rotate_width_counter_enable	: WIRE;
+	rotate_width_counter_sload	: WIRE;
+	rotate_width_counter_sload_value[4..0]	: WIRE;
+	scan_cache_address[7..0]	: WIRE;
+	scan_cache_in	: WIRE;
+	scan_cache_out	: WIRE;
+	scan_cache_write_enable	: WIRE;
+	sel_param_bypass_LF_unused	: WIRE;
+	sel_param_c	: WIRE;
+	sel_param_high_i_postscale	: WIRE;
+	sel_param_low_r	: WIRE;
+	sel_param_nominal_count	: WIRE;
+	sel_param_odd_CP_unused	: WIRE;
+	sel_type_c0	: WIRE;
+	sel_type_c1	: WIRE;
+	sel_type_c2	: WIRE;
+	sel_type_c3	: WIRE;
+	sel_type_c4	: WIRE;
+	sel_type_cplf	: WIRE;
+	sel_type_m	: WIRE;
+	sel_type_n	: WIRE;
+	sel_type_vco	: WIRE;
+	seq_addr_wire[7..0]	: WIRE;
+	seq_sload_value[5..0]	: WIRE;
+	shift_reg_clear	: WIRE;
+	shift_reg_load_enable	: WIRE;
+	shift_reg_load_nominal_enable	: WIRE;
+	shift_reg_serial_in	: WIRE;
+	shift_reg_serial_out	: WIRE;
+	shift_reg_shift_enable	: WIRE;
+	shift_reg_shift_nominal_enable	: WIRE;
+	shift_reg_width_select[7..0]	: WIRE;
+	w1565w	: WIRE;
+	w1592w	: WIRE;
+	w64w	: WIRE;
+	width_counter_done	: WIRE;
+	width_counter_enable	: WIRE;
+	width_counter_sload	: WIRE;
+	width_counter_sload_value[4..0]	: WIRE;
+	width_decoder_out[4..0]	: WIRE;
+	width_decoder_select[7..0]	: WIRE;
+	write_from_rom	: NODE;
+
+BEGIN 
+	altsyncram4.address_a[] = scan_cache_address[];
+	altsyncram4.clock0 = clock;
+	altsyncram4.data_a[] = ( scan_cache_in);
+	altsyncram4.wren_a = scan_cache_write_enable;
+	le_comb10.dataa = encode_out[0..0];
+	le_comb10.datab = encode_out[1..1];
+	le_comb10.datac = encode_out[2..2];
+	le_comb8.dataa = encode_out[0..0];
+	le_comb8.datab = encode_out[1..1];
+	le_comb8.datac = encode_out[2..2];
+	le_comb9.dataa = encode_out[0..0];
+	le_comb9.datab = encode_out[1..1];
+	le_comb9.datac = encode_out[2..2];
+	areset_init_state_1.clk = clock;
+	areset_init_state_1.d = pll_scandone;
+	areset_state.clk = clock;
+	areset_state.d = (areset_init_state_1.q & (! reset));
+	C0_data_state.clk = clock;
+	C0_data_state.d = (C0_ena_state.q # (C0_data_state.q & (! rotate_width_counter_done)));
+	C0_ena_state.clk = clock;
+	C0_ena_state.d = (C1_data_state.q & rotate_width_counter_done);
+	C1_data_state.clk = clock;
+	C1_data_state.d = (C1_ena_state.q # (C1_data_state.q & (! rotate_width_counter_done)));
+	C1_ena_state.clk = clock;
+	C1_ena_state.d = (C2_data_state.q & rotate_width_counter_done);
+	C2_data_state.clk = clock;
+	C2_data_state.d = (C2_ena_state.q # (C2_data_state.q & (! rotate_width_counter_done)));
+	C2_ena_state.clk = clock;
+	C2_ena_state.d = (C3_data_state.q & rotate_width_counter_done);
+	C3_data_state.clk = clock;
+	C3_data_state.d = (C3_ena_state.q # (C3_data_state.q & (! rotate_width_counter_done)));
+	C3_ena_state.clk = clock;
+	C3_ena_state.d = (C4_data_state.q & rotate_width_counter_done);
+	C4_data_state.clk = clock;
+	C4_data_state.d = (C4_ena_state.q # (C4_data_state.q & (! rotate_width_counter_done)));
+	C4_ena_state.clk = clock;
+	C4_ena_state.d = reconfig_init_state.q;
+	configupdate2_state.clk = clock;
+	configupdate2_state.d = configupdate_state.q;
+	configupdate3_state.clk = (! clock);
+	configupdate3_state.d = configupdate2_state.q;
+	configupdate_state.clk = clock;
+	configupdate_state.d = reconfig_post_state.q;
+	counter_param_latch_reg[].clk = clock;
+	counter_param_latch_reg[].clrn = (! reset);
+	counter_param_latch_reg[].d = counter_param[];
+	counter_param_latch_reg[].ena = input_latch_enable;
+	counter_type_latch_reg[].clk = clock;
+	counter_type_latch_reg[].clrn = (! reset);
+	counter_type_latch_reg[].d = counter_type[];
+	counter_type_latch_reg[].ena = input_latch_enable;
+	idle_state.clk = clock;
+	idle_state.clrn = (! reset);
+	idle_state.d = ((((((((((idle_state.q & (! read_param)) & (! write_param)) & (! reconfig)) & (! write_from_rom)) # read_last_state.q) # (write_data_state.q & width_counter_done)) # (write_nominal_state.q & width_counter_done)) # read_last_nominal_state.q) # (reconfig_wait_state.q & reconfig_done)) # reset_state.q);
+	nominal_data[].clk = clock;
+	nominal_data[].clrn = (! reset);
+	nominal_data[].d = ( cmpr7.aeb, data_in[8..0], add_sub6.result[7..0]);
+	read_data_nominal_state.clk = clock;
+	read_data_nominal_state.clrn = (! reset);
+	read_data_nominal_state.d = ((read_first_nominal_state.q & (! width_counter_done)) # (read_data_nominal_state.q & (! width_counter_done)));
+	read_data_state.clk = clock;
+	read_data_state.clrn = (! reset);
+	read_data_state.d = ((read_first_state.q & (! width_counter_done)) # (read_data_state.q & (! width_counter_done)));
+	read_first_nominal_state.clk = clock;
+	read_first_nominal_state.clrn = (! reset);
+	read_first_nominal_state.d = read_init_nominal_state.q;
+	read_first_state.clk = clock;
+	read_first_state.clrn = (! reset);
+	read_first_state.d = read_init_state.q;
+	read_init_nominal_state.clk = clock;
+	read_init_nominal_state.clrn = (! reset);
+	read_init_nominal_state.d = ((idle_state.q & read_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]));
+	read_init_state.clk = clock;
+	read_init_state.clrn = (! reset);
+	read_init_state.d = ((idle_state.q & read_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])));
+	read_last_nominal_state.clk = clock;
+	read_last_nominal_state.clrn = (! reset);
+	read_last_nominal_state.d = ((read_first_nominal_state.q & width_counter_done) # (read_data_nominal_state.q & width_counter_done));
+	read_last_state.clk = clock;
+	read_last_state.clrn = (! reset);
+	read_last_state.d = ((read_first_state.q & width_counter_done) # (read_data_state.q & width_counter_done));
+	reconfig_counter_state.clk = clock;
+	reconfig_counter_state.clrn = (! reset);
+	reconfig_counter_state.d = ((((((((((reconfig_init_state.q # C0_data_state.q) # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q) # C0_ena_state.q) # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q);
+	reconfig_init_state.clk = clock;
+	reconfig_init_state.clrn = (! reset);
+	reconfig_init_state.d = (idle_state.q & reconfig);
+	reconfig_post_state.clk = clock;
+	reconfig_post_state.clrn = (! reset);
+	reconfig_post_state.d = ((reconfig_seq_data_state.q & reconfig_width_counter_done) # (reconfig_post_state.q & (! reconfig_post_done)));
+	reconfig_seq_data_state.clk = clock;
+	reconfig_seq_data_state.clrn = (! reset);
+	reconfig_seq_data_state.d = (reconfig_seq_ena_state.q # (reconfig_seq_data_state.q & (! reconfig_width_counter_done)));
+	reconfig_seq_ena_state.clk = clock;
+	reconfig_seq_ena_state.clrn = (! reset);
+	reconfig_seq_ena_state.d = tmp_seq_ena_state.q;
+	reconfig_wait_state.clk = clock;
+	reconfig_wait_state.clrn = (! reset);
+	reconfig_wait_state.d = ((reconfig_post_state.q & reconfig_post_done) # (reconfig_wait_state.q & (! reconfig_done)));
+	reset_state.clk = clock;
+	reset_state.d = power_up;
+	reset_state.prn = (! reset);
+	shift_reg[].clk = clock;
+	shift_reg[].clrn = (! reset);
+	shift_reg[].d = ( ((((shift_reg_load_nominal_enable & nominal_data[0].q) # (shift_reg_load_enable & data_in[0..0])) # (shift_reg_shift_enable & shift_reg[16].q)) # (shift_reg_shift_nominal_enable & shift_reg[16].q)), ((((shift_reg_load_nominal_enable & nominal_data[1].q) # (shift_reg_load_enable & data_in[1..1])) # (shift_reg_shift_enable & shift_reg[15].q)) # (shift_reg_shift_nominal_enable & shift_reg[15].q)), ((((shift_reg_load_nominal_enable & nominal_data[2].q) # (shift_reg_load_enable & data_in[2..2])) # (shift_reg_shift_enable & shift_reg[14].q)) # (shift_reg_shift_nominal_enable & shift_reg[14].q)), ((((shift_reg_load_nominal_enable & nominal_data[3].q) # (shift_reg_load_enable & data_in[3..3])) # (shift_reg_shift_enable & shift_reg[13].q)) # (shift_reg_shift_nominal_enable & shift_reg[13].q)), ((((shift_reg_load_nominal_enable & nominal_data[4].q) # (shift_reg_load_enable & data_in[4..4])) # (shift_reg_shift_enable & shift_reg[12].q)) # (shift_reg_shift_nominal_enable & shift_reg[12].q)), ((((shift_reg_load_nominal_enable & nominal_data[5].q) # (shift_reg_load_enable & data_in[5..5])) # (shift_reg_shift_enable & shift_reg[11].q)) # (shift_reg_shift_nominal_enable & shift_reg[11].q)), ((((shift_reg_load_nominal_enable & nominal_data[6].q) # (shift_reg_load_enable & data_in[6..6])) # (shift_reg_shift_enable & shift_reg[10].q)) # (shift_reg_shift_nominal_enable & shift_reg[10].q)), ((((shift_reg_load_nominal_enable & nominal_data[7].q) # (shift_reg_load_enable & data_in[7..7])) # (shift_reg_shift_enable & shift_reg[9].q)) # (shift_reg_shift_nominal_enable & shift_reg[9].q)), ((((shift_reg_load_nominal_enable & nominal_data[8].q) # (shift_reg_load_enable & data_in[8..8])) # (shift_reg_shift_enable & shift_reg[8].q)) # (shift_reg_shift_nominal_enable & shift_reg[8].q)), ((((shift_reg_load_nominal_enable & nominal_data[9].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[7].q)) # (shift_reg_shift_nominal_enable & shift_reg[7].q)), ((((shift_reg_load_nominal_enable & nominal_data[10].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[6].q)) # (shift_reg_shift_nominal_enable & shift_reg[6].q)), ((((shift_reg_load_nominal_enable & nominal_data[11].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[5].q)) # (shift_reg_shift_nominal_enable & shift_reg[5].q)), ((((shift_reg_load_nominal_enable & nominal_data[12].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[4].q)) # (shift_reg_shift_nominal_enable & shift_reg[4].q)), ((((shift_reg_load_nominal_enable & nominal_data[13].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[3].q)) # (shift_reg_shift_nominal_enable & shift_reg[3].q)), ((((shift_reg_load_nominal_enable & nominal_data[14].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[2].q)) # (shift_reg_shift_nominal_enable & shift_reg[2].q)), ((((shift_reg_load_nominal_enable & nominal_data[15].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[1].q)) # (shift_reg_shift_nominal_enable & shift_reg[1].q)), ((((shift_reg_load_nominal_enable & nominal_data[16].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[0].q)) # (shift_reg_shift_nominal_enable & shift_reg[0].q)), ((((shift_reg_load_nominal_enable & nominal_data[17].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg_serial_in)) # (shift_reg_shift_nominal_enable & shift_reg_serial_in)));
+	shift_reg[].ena = ((((shift_reg_load_enable # shift_reg_shift_enable) # shift_reg_load_nominal_enable) # shift_reg_shift_nominal_enable) # shift_reg_clear);
+	shift_reg[].sclr = shift_reg_clear;
+	tmp_nominal_data_out_state.clk = clock;
+	tmp_nominal_data_out_state.d = ((read_last_nominal_state.q & (! idle_state.q)) # (tmp_nominal_data_out_state.q & idle_state.q));
+	tmp_seq_ena_state.clk = clock;
+	tmp_seq_ena_state.d = (reconfig_counter_state.q & (C0_data_state.q & rotate_width_counter_done));
+	write_data_state.clk = clock;
+	write_data_state.clrn = (! reset);
+	write_data_state.d = (write_init_state.q # (write_data_state.q & (! width_counter_done)));
+	write_init_nominal_state.clk = clock;
+	write_init_nominal_state.clrn = (! reset);
+	write_init_nominal_state.d = ((idle_state.q & write_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]));
+	write_init_state.clk = clock;
+	write_init_state.clrn = (! reset);
+	write_init_state.d = ((idle_state.q & write_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])));
+	write_nominal_state.clk = clock;
+	write_nominal_state.clrn = (! reset);
+	write_nominal_state.d = (write_init_nominal_state.q # (write_nominal_state.q & (! width_counter_done)));
+	add_sub5.cin = B"0";
+	add_sub5.dataa[] = ( B"0", shift_reg[8..1].q);
+	add_sub5.datab[] = ( B"0", shift_reg[17..10].q);
+	add_sub6.cin = data_in[0..0];
+	add_sub6.dataa[] = ( data_in[8..1]);
+	cmpr7.dataa[] = ( data_in[7..0]);
+	cmpr7.datab[] = B"00000001";
+	cntr1.clock = clock;
+	cntr1.cnt_en = addr_counter_enable;
+	cntr1.data[] = addr_counter_sload_value[];
+	cntr1.sload = addr_counter_sload;
+	cntr12.clock = clock;
+	cntr12.cnt_en = reconfig_addr_counter_enable;
+	cntr12.data[] = reconfig_addr_counter_sload_value[];
+	cntr12.sload = reconfig_addr_counter_sload;
+	cntr13.clock = clock;
+	cntr13.cnt_en = reconfig_width_counter_enable;
+	cntr13.data[] = reconfig_width_counter_sload_value[];
+	cntr13.sload = reconfig_width_counter_sload;
+	cntr14.clock = clock;
+	cntr14.cnt_en = rotate_width_counter_enable;
+	cntr14.data[] = rotate_width_counter_sload_value[];
+	cntr14.sload = rotate_width_counter_sload;
+	cntr15.clock = clock;
+	cntr15.cnt_en = rotate_addr_counter_enable;
+	cntr15.data[] = rotate_addr_counter_sload_value[];
+	cntr15.sload = rotate_addr_counter_sload;
+	cntr2.clock = clock;
+	cntr2.cnt_en = read_addr_counter_enable;
+	cntr2.data[] = read_addr_counter_sload_value[];
+	cntr2.sload = read_addr_counter_sload;
+	cntr3.clock = clock;
+	cntr3.cnt_en = width_counter_enable;
+	cntr3.data[] = width_counter_sload_value[];
+	cntr3.sload = width_counter_sload;
+	decode11.data[] = cuda_combout_wire[];
+	addr_counter_enable = (write_data_state.q # write_nominal_state.q);
+	addr_counter_out[] = cntr1.q[];
+	addr_counter_sload = (write_init_state.q # write_init_nominal_state.q);
+	addr_counter_sload_value[] = (addr_decoder_out[] & (write_init_state.q # write_init_nominal_state.q));
+	addr_decoder_out[] = (((((((((((((((((((((((((((((((((((( B"0", B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_bypass_LF_unused)) # ( B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_c), (sel_type_cplf & sel_param_c))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_low_r), B"0", B"0", B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_vco & sel_param_high_i_postscale), B"0", B"0", (sel_type_vco & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_odd_CP_unused), (sel_type_cplf & sel_param_odd_CP_unused), (sel_type_cplf & sel_param_odd_CP_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale), B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_high_i_postscale), (sel_type_n & sel_param_high_i_postscale), B"0", (sel_type_n & sel_param_high_i_postscale), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused), B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_n & sel_param_low_r), B"0", B"0", B"0", (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r))) # ( B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0", B"0", B"0", (sel_type_n & sel_param_nominal_count), (sel_type_n & sel_param_nominal_count))) # ( B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", (sel_type_m & sel_param_high_i_postscale), (sel_type_m & sel_param_high_i_postscale), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused), (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r))) # ( B"0", B"0", (sel_type_m & sel_param_nominal_count), (sel_type_m & sel_param_nominal_count), B"0", (sel_type_m & sel_param_nominal_count), B"0", (sel_type_m & sel_param_nominal_count))) # ( B"0", B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c0 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c0 & sel_param_low_r), (sel_type_c0 & sel_param_low_r), (sel_type_c0 & sel_param_low_r))) # ( B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c1 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c1 & sel_param_low_r), B"0", (sel_type_c1 & sel_param_low_r), (sel_type_c1 & sel_param_low_r), B"0", B"0", (sel_type_c1 & sel_param_low_r))) # ( B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale), B"0", B"0", B"0", (sel_type_c2 & sel_param_high_i_postscale), B"0")) # ( B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r), B"0", (sel_type_c2 & sel_param_low_r), B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r))) # ( B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0", (sel_type_c3 & sel_param_low_r))) # ( B"0", (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), B"0")) # ( (sel_type_c4 & sel_param_high_i_postscale), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), B"0")) # ( (sel_type_c4 & sel_param_odd_CP_unused), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused))) # ( (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r)));
+	busy = ((! idle_state.q) # areset_state.q);
+	c0_wire[] = B"01000111";
+	c1_wire[] = B"01011001";
+	c2_wire[] = B"01101011";
+	c3_wire[] = B"01111101";
+	c4_wire[] = B"10001111";
+	counter_param_latch[] = counter_param_latch_reg[].q;
+	counter_type_latch[] = counter_type_latch_reg[].q;
+	cuda_combout_wire[] = ( le_comb10.combout, le_comb9.combout, le_comb8.combout);
+	data_out[] = ( ((shift_reg[8].q & (! read_nominal_out)) # (add_sub5.result[8..8] & read_nominal_out)), ((shift_reg[7].q & (! read_nominal_out)) # (add_sub5.result[7..7] & read_nominal_out)), ((shift_reg[6].q & (! read_nominal_out)) # (add_sub5.result[6..6] & read_nominal_out)), ((shift_reg[5].q & (! read_nominal_out)) # (add_sub5.result[5..5] & read_nominal_out)), ((shift_reg[4].q & (! read_nominal_out)) # (add_sub5.result[4..4] & read_nominal_out)), ((shift_reg[3].q & (! read_nominal_out)) # (add_sub5.result[3..3] & read_nominal_out)), ((shift_reg[2].q & (! read_nominal_out)) # (add_sub5.result[2..2] & read_nominal_out)), ((shift_reg[1].q & (! read_nominal_out)) # (add_sub5.result[1..1] & read_nominal_out)), ((shift_reg[0].q & (! read_nominal_out)) # (add_sub5.result[0..0] & read_nominal_out)));
+	dummy_scandataout = pll_scandataout;
+	encode_out[] = ( C4_ena_state.q, (C2_ena_state.q # C3_ena_state.q), (C1_ena_state.q # C3_ena_state.q));
+	input_latch_enable = (idle_state.q & (write_param # read_param));
+	pll_areset = (pll_areset_in # (areset_state.q & reconfig_wait_state.q));
+	pll_configupdate = (configupdate_state.q & (! configupdate3_state.q));
+	pll_scanclk = clock;
+	pll_scanclkena = ((rotate_width_counter_enable & (! rotate_width_counter_done)) # reconfig_seq_data_state.q);
+	pll_scandata = (scan_cache_out & ((rotate_width_counter_enable # reconfig_seq_data_state.q) # reconfig_post_state.q));
+	power_up = ((((((((((((((((((((! reset_state.q) & (! idle_state.q)) & (! read_init_state.q)) & (! read_first_state.q)) & (! read_data_state.q)) & (! read_last_state.q)) & (! read_init_nominal_state.q)) & (! read_first_nominal_state.q)) & (! read_data_nominal_state.q)) & (! read_last_nominal_state.q)) & (! write_init_state.q)) & (! write_data_state.q)) & (! write_init_nominal_state.q)) & (! write_nominal_state.q)) & (! reconfig_init_state.q)) & (! reconfig_counter_state.q)) & (! reconfig_seq_ena_state.q)) & (! reconfig_seq_data_state.q)) & (! reconfig_post_state.q)) & (! reconfig_wait_state.q));
+	read_addr_counter_enable = (((read_first_state.q # read_data_state.q) # read_first_nominal_state.q) # read_data_nominal_state.q);
+	read_addr_counter_out[] = cntr2.q[];
+	read_addr_counter_sload = (read_init_state.q # read_init_nominal_state.q);
+	read_addr_counter_sload_value[] = (read_addr_decoder_out[] & (read_init_state.q # read_init_nominal_state.q));
+	read_addr_decoder_out[] = (((((((((((((((((((((((((((((((((((( B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0") # ( B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_c), B"0")) # ( B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_low_r), B"0", B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_vco & sel_param_high_i_postscale), B"0", B"0", (sel_type_vco & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_odd_CP_unused), B"0", (sel_type_cplf & sel_param_odd_CP_unused), B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_high_i_postscale), B"0", B"0", (sel_type_n & sel_param_high_i_postscale), (sel_type_n & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused), B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r), B"0", B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0")) # ( B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", (sel_type_m & sel_param_high_i_postscale))) # ( B"0", B"0", (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused), (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), B"0")) # ( B"0", B"0", (sel_type_m & sel_param_nominal_count), B"0", B"0", (sel_type_m & sel_param_nominal_count), B"0", B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale))) # ( B"0", B"0", (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c0 & sel_param_low_r), B"0", B"0", B"0", B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", (sel_type_c1 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c1 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c1 & sel_param_low_r), B"0", (sel_type_c1 & sel_param_low_r), B"0", B"0", (sel_type_c1 & sel_param_low_r), B"0")) # ( B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c2 & sel_param_high_i_postscale), B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale), B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r), B"0", B"0", (sel_type_c2 & sel_param_low_r), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0")) # ( B"0", (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale))) # ( (sel_type_c4 & sel_param_odd_CP_unused), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused))) # ( (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0"));
+	read_nominal_out = tmp_nominal_data_out_state.q;
+	reconfig_addr_counter_enable = reconfig_seq_data_state.q;
+	reconfig_addr_counter_out[] = cntr12.q[];
+	reconfig_addr_counter_sload = reconfig_seq_ena_state.q;
+	reconfig_addr_counter_sload_value[] = (reconfig_seq_ena_state.q & seq_addr_wire[]);
+	reconfig_done = ((! pll_scandone) & (dummy_scandataout # (! dummy_scandataout)));
+	reconfig_post_done = pll_scandone;
+	reconfig_width_counter_done = ((((((! cntr13.q[0..0]) & (! cntr13.q[1..1])) & (! cntr13.q[2..2])) & (! cntr13.q[3..3])) & (! cntr13.q[4..4])) & (! cntr13.q[5..5]));
+	reconfig_width_counter_enable = reconfig_seq_data_state.q;
+	reconfig_width_counter_sload = reconfig_seq_ena_state.q;
+	reconfig_width_counter_sload_value[] = (reconfig_seq_ena_state.q & seq_sload_value[]);
+	rotate_addr_counter_enable = ((((C0_data_state.q # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q);
+	rotate_addr_counter_out[] = cntr15.q[];
+	rotate_addr_counter_sload = ((((C0_ena_state.q # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q);
+	rotate_addr_counter_sload_value[] = (((((c0_wire[] & rotate_decoder_wires[0..0]) # (c1_wire[] & rotate_decoder_wires[1..1])) # (c2_wire[] & rotate_decoder_wires[2..2])) # (c3_wire[] & rotate_decoder_wires[3..3])) # (c4_wire[] & rotate_decoder_wires[4..4]));
+	rotate_decoder_wires[] = decode11.eq[];
+	rotate_width_counter_done = (((((! cntr14.q[0..0]) & (! cntr14.q[1..1])) & (! cntr14.q[2..2])) & (! cntr14.q[3..3])) & (! cntr14.q[4..4]));
+	rotate_width_counter_enable = ((((C0_data_state.q # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q);
+	rotate_width_counter_sload = ((((C0_ena_state.q # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q);
+	rotate_width_counter_sload_value[] = B"10010";
+	scan_cache_address[] = ((((addr_counter_out[] & addr_counter_enable) # (read_addr_counter_out[] & read_addr_counter_enable)) # (rotate_addr_counter_out[] & rotate_addr_counter_enable)) # (reconfig_addr_counter_out[] & reconfig_addr_counter_enable));
+	scan_cache_in = shift_reg_serial_out;
+	scan_cache_out = altsyncram4.q_a[0..0];
+	scan_cache_write_enable = (write_data_state.q # write_nominal_state.q);
+	sel_param_bypass_LF_unused = (((! counter_param_latch[0..0]) & (! counter_param_latch[1..1])) & counter_param_latch[2..2]);
+	sel_param_c = (((! counter_param_latch[0..0]) & counter_param_latch[1..1]) & (! counter_param_latch[2..2]));
+	sel_param_high_i_postscale = (((! counter_param_latch[0..0]) & (! counter_param_latch[1..1])) & (! counter_param_latch[2..2]));
+	sel_param_low_r = ((counter_param_latch[0..0] & (! counter_param_latch[1..1])) & (! counter_param_latch[2..2]));
+	sel_param_nominal_count = ((counter_param_latch[0..0] & counter_param_latch[1..1]) & counter_param_latch[2..2]);
+	sel_param_odd_CP_unused = ((counter_param_latch[0..0] & (! counter_param_latch[1..1])) & counter_param_latch[2..2]);
+	sel_type_c0 = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & counter_type_latch[2..2]) & (! counter_type_latch[3..3]));
+	sel_type_c1 = (((counter_type_latch[0..0] & (! counter_type_latch[1..1])) & counter_type_latch[2..2]) & (! counter_type_latch[3..3]));
+	sel_type_c2 = ((((! counter_type_latch[0..0]) & counter_type_latch[1..1]) & counter_type_latch[2..2]) & (! counter_type_latch[3..3]));
+	sel_type_c3 = (((counter_type_latch[0..0] & counter_type_latch[1..1]) & counter_type_latch[2..2]) & (! counter_type_latch[3..3]));
+	sel_type_c4 = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & counter_type_latch[3..3]);
+	sel_type_cplf = ((((! counter_type_latch[0..0]) & counter_type_latch[1..1]) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3]));
+	sel_type_m = (((counter_type_latch[0..0] & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3]));
+	sel_type_n = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3]));
+	sel_type_vco = (((counter_type_latch[0..0] & counter_type_latch[1..1]) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3]));
+	seq_addr_wire[] = B"00110101";
+	seq_sload_value[] = B"110110";
+	shift_reg_clear = (read_init_state.q # read_init_nominal_state.q);
+	shift_reg_load_enable = ((idle_state.q & write_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])));
+	shift_reg_load_nominal_enable = ((idle_state.q & write_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]));
+	shift_reg_serial_in = scan_cache_out;
+	shift_reg_serial_out = ((((((((shift_reg[17].q & shift_reg_width_select[0..0]) # (shift_reg[17].q & shift_reg_width_select[1..1])) # (shift_reg[17].q & shift_reg_width_select[2..2])) # (shift_reg[17].q & shift_reg_width_select[3..3])) # (shift_reg[17].q & shift_reg_width_select[4..4])) # (shift_reg[17].q & shift_reg_width_select[5..5])) # (shift_reg[17].q & shift_reg_width_select[6..6])) # (shift_reg[17].q & shift_reg_width_select[7..7]));
+	shift_reg_shift_enable = ((read_data_state.q # read_last_state.q) # write_data_state.q);
+	shift_reg_shift_nominal_enable = ((read_data_nominal_state.q # read_last_nominal_state.q) # write_nominal_state.q);
+	shift_reg_width_select[] = width_decoder_select[];
+	w1565w = B"0";
+	w1592w = B"0";
+	w64w = B"0";
+	width_counter_done = (((((! cntr3.q[0..0]) & (! cntr3.q[1..1])) & (! cntr3.q[2..2])) & (! cntr3.q[3..3])) & (! cntr3.q[4..4]));
+	width_counter_enable = ((((read_first_state.q # read_data_state.q) # write_data_state.q) # read_data_nominal_state.q) # write_nominal_state.q);
+	width_counter_sload = (((read_init_state.q # write_init_state.q) # read_init_nominal_state.q) # write_init_nominal_state.q);
+	width_counter_sload_value[] = width_decoder_out[];
+	width_decoder_out[] = (((((( B"0", B"0", B"0", B"0", B"0") # ( width_decoder_select[2..2], B"0", B"0", B"0", width_decoder_select[2..2])) # ( B"0", B"0", B"0", B"0", width_decoder_select[3..3])) # ( B"0", B"0", width_decoder_select[5..5], width_decoder_select[5..5], width_decoder_select[5..5])) # ( B"0", B"0", B"0", width_decoder_select[6..6], B"0")) # ( B"0", B"0", width_decoder_select[7..7], B"0", B"0"));
+	width_decoder_select[] = ( ((sel_type_cplf & sel_param_low_r) # (sel_type_cplf & sel_param_odd_CP_unused)), (sel_type_cplf & sel_param_high_i_postscale), ((((((((((((((sel_type_n & sel_param_high_i_postscale) # (sel_type_n & sel_param_low_r)) # (sel_type_m & sel_param_high_i_postscale)) # (sel_type_m & sel_param_low_r)) # (sel_type_c0 & sel_param_high_i_postscale)) # (sel_type_c0 & sel_param_low_r)) # (sel_type_c1 & sel_param_high_i_postscale)) # (sel_type_c1 & sel_param_low_r)) # (sel_type_c2 & sel_param_high_i_postscale)) # (sel_type_c2 & sel_param_low_r)) # (sel_type_c3 & sel_param_high_i_postscale)) # (sel_type_c3 & sel_param_low_r)) # (sel_type_c4 & sel_param_high_i_postscale)) # (sel_type_c4 & sel_param_low_r)), w1592w, ((sel_type_cplf & sel_param_bypass_LF_unused) # (sel_type_cplf & sel_param_c)), ((sel_type_n & sel_param_nominal_count) # (sel_type_m & sel_param_nominal_count)), w1565w, (((((((((((((((sel_type_vco & sel_param_high_i_postscale) # (sel_type_n & sel_param_bypass_LF_unused)) # (sel_type_n & sel_param_odd_CP_unused)) # (sel_type_m & sel_param_bypass_LF_unused)) # (sel_type_m & sel_param_odd_CP_unused)) # (sel_type_c0 & sel_param_bypass_LF_unused)) # (sel_type_c0 & sel_param_odd_CP_unused)) # (sel_type_c1 & sel_param_bypass_LF_unused)) # (sel_type_c1 & sel_param_odd_CP_unused)) # (sel_type_c2 & sel_param_bypass_LF_unused)) # (sel_type_c2 & sel_param_odd_CP_unused)) # (sel_type_c3 & sel_param_bypass_LF_unused)) # (sel_type_c3 & sel_param_odd_CP_unused)) # (sel_type_c4 & sel_param_bypass_LF_unused)) # (sel_type_c4 & sel_param_odd_CP_unused)));
+	write_from_rom = GND;
+END;
+--VALID FILE
diff --git a/FPGA_quartus_GE/altpll_reconfig1_pllrcfg_t4q.tdf b/FPGA_quartus_GE/altpll_reconfig1_pllrcfg_t4q.tdf
new file mode 100644
index 0000000..fae939f
--- /dev/null
+++ b/FPGA_quartus_GE/altpll_reconfig1_pllrcfg_t4q.tdf
@@ -0,0 +1,582 @@
+--altpll_reconfig CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone III" busy clock counter_param counter_type data_in data_out pll_areset pll_areset_in pll_configupdate pll_scanclk pll_scanclkena pll_scandata pll_scandataout pll_scandone read_param reconfig reset write_param
+--VERSION_BEGIN 9.1SP2 cbx_altpll_reconfig 2010:03:24:20:43:42:SJ cbx_altsyncram 2010:03:24:20:43:42:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_lpm_add_sub 2010:03:24:20:43:43:SJ cbx_lpm_compare 2010:03:24:20:43:43:SJ cbx_lpm_counter 2010:03:24:20:43:43:SJ cbx_lpm_decode 2010:03:24:20:43:43:SJ cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ cbx_util_mgl 2010:03:24:20:43:43:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2010 Altera Corporation
+--  Your use of Altera Corporation's design tools, logic functions 
+--  and other software and tools, and its AMPP partner logic 
+--  functions, and any output files from any of the foregoing 
+--  (including device programming or simulation files), and any 
+--  associated documentation or information are expressly subject 
+--  to the terms and conditions of the Altera Program License 
+--  Subscription Agreement, Altera MegaCore Function License 
+--  Agreement, or other applicable license agreement, including, 
+--  without limitation, that your use is for the sole purpose of 
+--  programming logic devices manufactured by Altera and sold by 
+--  Altera or its authorized distributors.  Please refer to the 
+--  applicable agreement for further details.
+
+
+include "altsyncram.inc";
+FUNCTION cycloneiii_lcell_comb (cin, dataa, datab, datac, datad)
+WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT)
+RETURNS ( combout, cout);
+FUNCTION lpm_add_sub (aclr, add_sub, cin, clken, clock, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0])
+WITH ( CARRY_CHAIN, CARRY_CHAIN_LENGTH, LPM_DIRECTION, LPM_PIPELINE, LPM_REPRESENTATION, LPM_WIDTH, ONE_INPUT_IS_CONSTANT, REGISTERED_AT_END, USE_WYS)
+RETURNS ( cout, overflow, result[LPM_WIDTH-1..0]);
+FUNCTION lpm_compare (aclr, clken, clock, dataa[LPM_WIDTH-1..0], datab[LPM_WIDTH-1..0])
+WITH ( LPM_PIPELINE, LPM_REPRESENTATION, LPM_WIDTH, ONE_INPUT_IS_CONSTANT)
+RETURNS ( aeb, agb, ageb, alb, aleb, aneb);
+FUNCTION lpm_counter (aclr, aload, aset, cin, clk_en, clock, cnt_en, data[LPM_WIDTH-1..0], sclr, sload, sset, updown)
+WITH ( lpm_avalue, lpm_direction, lpm_modulus, lpm_port_updown, lpm_pvalue, lpm_svalue, lpm_width)
+RETURNS ( cout, eq[15..0], q[LPM_WIDTH-1..0]);
+FUNCTION lpm_decode (aclr, clken, clock, data[LPM_WIDTH-1..0], enable)
+WITH ( CASCADE_CHAIN, IGNORE_CASCADE_BUFFERS, LPM_DECODES, LPM_PIPELINE, LPM_WIDTH)
+RETURNS ( eq[LPM_DECODES-1..0]);
+
+--synthesis_resources = altsyncram 1 lpm_add_sub 2 lpm_compare 1 lpm_counter 7 lpm_decode 1 lut 3 reg 80 
+OPTIONS ALTERA_INTERNAL_OPTION = "ADV_NETLIST_OPT_ALLOWED=""NEVER_ALLOW"";suppress_da_rule_internal=C106;{-to le_comb10} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=2;{-to le_comb8} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=0;{-to le_comb9} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=1;{-to idle_state} POWER_UP_LEVEL=LOW;{-to read_data_nominal_state} POWER_UP_LEVEL=LOW;{-to read_data_state} POWER_UP_LEVEL=LOW;{-to read_first_nominal_state} POWER_UP_LEVEL=LOW;{-to read_first_state} POWER_UP_LEVEL=LOW;{-to read_init_nominal_state} POWER_UP_LEVEL=LOW;{-to read_init_state} POWER_UP_LEVEL=LOW;{-to read_last_nominal_state} POWER_UP_LEVEL=LOW;{-to read_last_state} POWER_UP_LEVEL=LOW;{-to reconfig_counter_state} POWER_UP_LEVEL=LOW;{-to reconfig_init_state} POWER_UP_LEVEL=LOW;{-to reconfig_post_state} POWER_UP_LEVEL=LOW;{-to reconfig_seq_data_state} POWER_UP_LEVEL=LOW;{-to reconfig_seq_ena_state} POWER_UP_LEVEL=LOW;{-to reconfig_wait_state} POWER_UP_LEVEL=LOW;{-to reset_state} POWER_UP_LEVEL=HIGH;{-to write_data_state} POWER_UP_LEVEL=LOW;{-to write_init_nominal_state} POWER_UP_LEVEL=LOW;{-to write_init_state} POWER_UP_LEVEL=LOW;{-to write_nominal_state} POWER_UP_LEVEL=LOW";
+
+SUBDESIGN altpll_reconfig1_pllrcfg_t4q
+( 
+	busy	:	output;
+	clock	:	input;
+	counter_param[2..0]	:	input;
+	counter_type[3..0]	:	input;
+	data_in[8..0]	:	input;
+	data_out[8..0]	:	output;
+	pll_areset	:	output;
+	pll_areset_in	:	input;
+	pll_configupdate	:	output;
+	pll_scanclk	:	output;
+	pll_scanclkena	:	output;
+	pll_scandata	:	output;
+	pll_scandataout	:	input;
+	pll_scandone	:	input;
+	read_param	:	input;
+	reconfig	:	input;
+	reset	:	input;
+	write_param	:	input;
+) 
+VARIABLE 
+	altsyncram4 : altsyncram
+		WITH (
+			NUMWORDS_A = 144,
+			OPERATION_MODE = "SINGLE_PORT",
+			WIDTH_A = 1,
+			WIDTH_BYTEENA_A = 1,
+			WIDTHAD_A = 8
+		);
+	le_comb10 : cycloneiii_lcell_comb
+		WITH (
+			DONT_TOUCH = "on",
+			LUT_MASK = "F0F0",
+			SUM_LUTC_INPUT = "datac"
+		);
+	le_comb8 : cycloneiii_lcell_comb
+		WITH (
+			DONT_TOUCH = "on",
+			LUT_MASK = "AAAA",
+			SUM_LUTC_INPUT = "datac"
+		);
+	le_comb9 : cycloneiii_lcell_comb
+		WITH (
+			DONT_TOUCH = "on",
+			LUT_MASK = "CCCC",
+			SUM_LUTC_INPUT = "datac"
+		);
+	areset_init_state_1 : dffe;
+	areset_state : dffe;
+	C0_data_state : dffe;
+	C0_ena_state : dffe;
+	C1_data_state : dffe;
+	C1_ena_state : dffe;
+	C2_data_state : dffe;
+	C2_ena_state : dffe;
+	C3_data_state : dffe;
+	C3_ena_state : dffe;
+	C4_data_state : dffe;
+	C4_ena_state : dffe;
+	configupdate2_state : dffe;
+	configupdate3_state : dffe;
+	configupdate_state : dffe;
+	counter_param_latch_reg[2..0] : dffe;
+	counter_type_latch_reg[3..0] : dffe;
+	idle_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	nominal_data[17..0] : dffe;
+	read_data_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_data_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_first_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_first_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_init_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_init_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_last_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	read_last_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_counter_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_init_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_post_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_seq_data_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_seq_ena_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reconfig_wait_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	reset_state : dffe
+		WITH (
+			power_up = "high"
+		);
+	shift_reg[17..0] : dffeas;
+	tmp_nominal_data_out_state : dffe;
+	tmp_seq_ena_state : dffe;
+	write_data_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	write_init_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	write_init_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	write_nominal_state : dffe
+		WITH (
+			power_up = "low"
+		);
+	add_sub5 : lpm_add_sub
+		WITH (
+			LPM_WIDTH = 9
+		);
+	add_sub6 : lpm_add_sub
+		WITH (
+			LPM_WIDTH = 8
+		);
+	cmpr7 : lpm_compare
+		WITH (
+			LPM_WIDTH = 8
+		);
+	cntr1 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_modulus = 144,
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 8
+		);
+	cntr12 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_modulus = 144,
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 8
+		);
+	cntr13 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 6
+		);
+	cntr14 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 5
+		);
+	cntr15 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_modulus = 144,
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 8
+		);
+	cntr2 : lpm_counter
+		WITH (
+			lpm_direction = "UP",
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 8
+		);
+	cntr3 : lpm_counter
+		WITH (
+			lpm_direction = "DOWN",
+			lpm_port_updown = "PORT_UNUSED",
+			lpm_width = 5
+		);
+	decode11 : lpm_decode
+		WITH (
+			LPM_DECODES = 5,
+			LPM_WIDTH = 3
+		);
+	addr_counter_enable	: WIRE;
+	addr_counter_out[7..0]	: WIRE;
+	addr_counter_sload	: WIRE;
+	addr_counter_sload_value[7..0]	: WIRE;
+	addr_decoder_out[7..0]	: WIRE;
+	c0_wire[7..0]	: WIRE;
+	c1_wire[7..0]	: WIRE;
+	c2_wire[7..0]	: WIRE;
+	c3_wire[7..0]	: WIRE;
+	c4_wire[7..0]	: WIRE;
+	counter_param_latch[2..0]	: WIRE;
+	counter_type_latch[3..0]	: WIRE;
+	cuda_combout_wire[2..0]	: WIRE;
+	dummy_scandataout	: WIRE;
+	encode_out[2..0]	: WIRE;
+	input_latch_enable	: WIRE;
+	power_up	: WIRE;
+	read_addr_counter_enable	: WIRE;
+	read_addr_counter_out[7..0]	: WIRE;
+	read_addr_counter_sload	: WIRE;
+	read_addr_counter_sload_value[7..0]	: WIRE;
+	read_addr_decoder_out[7..0]	: WIRE;
+	read_nominal_out	: WIRE;
+	reconfig_addr_counter_enable	: WIRE;
+	reconfig_addr_counter_out[7..0]	: WIRE;
+	reconfig_addr_counter_sload	: WIRE;
+	reconfig_addr_counter_sload_value[7..0]	: WIRE;
+	reconfig_done	: WIRE;
+	reconfig_post_done	: WIRE;
+	reconfig_width_counter_done	: WIRE;
+	reconfig_width_counter_enable	: WIRE;
+	reconfig_width_counter_sload	: WIRE;
+	reconfig_width_counter_sload_value[5..0]	: WIRE;
+	rotate_addr_counter_enable	: WIRE;
+	rotate_addr_counter_out[7..0]	: WIRE;
+	rotate_addr_counter_sload	: WIRE;
+	rotate_addr_counter_sload_value[7..0]	: WIRE;
+	rotate_decoder_wires[4..0]	: WIRE;
+	rotate_width_counter_done	: WIRE;
+	rotate_width_counter_enable	: WIRE;
+	rotate_width_counter_sload	: WIRE;
+	rotate_width_counter_sload_value[4..0]	: WIRE;
+	scan_cache_address[7..0]	: WIRE;
+	scan_cache_in	: WIRE;
+	scan_cache_out	: WIRE;
+	scan_cache_write_enable	: WIRE;
+	sel_param_bypass_LF_unused	: WIRE;
+	sel_param_c	: WIRE;
+	sel_param_high_i_postscale	: WIRE;
+	sel_param_low_r	: WIRE;
+	sel_param_nominal_count	: WIRE;
+	sel_param_odd_CP_unused	: WIRE;
+	sel_type_c0	: WIRE;
+	sel_type_c1	: WIRE;
+	sel_type_c2	: WIRE;
+	sel_type_c3	: WIRE;
+	sel_type_c4	: WIRE;
+	sel_type_cplf	: WIRE;
+	sel_type_m	: WIRE;
+	sel_type_n	: WIRE;
+	sel_type_vco	: WIRE;
+	seq_addr_wire[7..0]	: WIRE;
+	seq_sload_value[5..0]	: WIRE;
+	shift_reg_clear	: WIRE;
+	shift_reg_load_enable	: WIRE;
+	shift_reg_load_nominal_enable	: WIRE;
+	shift_reg_serial_in	: WIRE;
+	shift_reg_serial_out	: WIRE;
+	shift_reg_shift_enable	: WIRE;
+	shift_reg_shift_nominal_enable	: WIRE;
+	shift_reg_width_select[7..0]	: WIRE;
+	w1565w	: WIRE;
+	w1592w	: WIRE;
+	w64w	: WIRE;
+	width_counter_done	: WIRE;
+	width_counter_enable	: WIRE;
+	width_counter_sload	: WIRE;
+	width_counter_sload_value[4..0]	: WIRE;
+	width_decoder_out[4..0]	: WIRE;
+	width_decoder_select[7..0]	: WIRE;
+	write_from_rom	: NODE;
+
+BEGIN 
+	altsyncram4.address_a[] = scan_cache_address[];
+	altsyncram4.clock0 = clock;
+	altsyncram4.data_a[] = ( scan_cache_in);
+	altsyncram4.wren_a = scan_cache_write_enable;
+	le_comb10.dataa = encode_out[0..0];
+	le_comb10.datab = encode_out[1..1];
+	le_comb10.datac = encode_out[2..2];
+	le_comb8.dataa = encode_out[0..0];
+	le_comb8.datab = encode_out[1..1];
+	le_comb8.datac = encode_out[2..2];
+	le_comb9.dataa = encode_out[0..0];
+	le_comb9.datab = encode_out[1..1];
+	le_comb9.datac = encode_out[2..2];
+	areset_init_state_1.clk = clock;
+	areset_init_state_1.d = pll_scandone;
+	areset_state.clk = clock;
+	areset_state.d = (areset_init_state_1.q & (! reset));
+	C0_data_state.clk = clock;
+	C0_data_state.d = (C0_ena_state.q # (C0_data_state.q & (! rotate_width_counter_done)));
+	C0_ena_state.clk = clock;
+	C0_ena_state.d = (C1_data_state.q & rotate_width_counter_done);
+	C1_data_state.clk = clock;
+	C1_data_state.d = (C1_ena_state.q # (C1_data_state.q & (! rotate_width_counter_done)));
+	C1_ena_state.clk = clock;
+	C1_ena_state.d = (C2_data_state.q & rotate_width_counter_done);
+	C2_data_state.clk = clock;
+	C2_data_state.d = (C2_ena_state.q # (C2_data_state.q & (! rotate_width_counter_done)));
+	C2_ena_state.clk = clock;
+	C2_ena_state.d = (C3_data_state.q & rotate_width_counter_done);
+	C3_data_state.clk = clock;
+	C3_data_state.d = (C3_ena_state.q # (C3_data_state.q & (! rotate_width_counter_done)));
+	C3_ena_state.clk = clock;
+	C3_ena_state.d = (C4_data_state.q & rotate_width_counter_done);
+	C4_data_state.clk = clock;
+	C4_data_state.d = (C4_ena_state.q # (C4_data_state.q & (! rotate_width_counter_done)));
+	C4_ena_state.clk = clock;
+	C4_ena_state.d = reconfig_init_state.q;
+	configupdate2_state.clk = clock;
+	configupdate2_state.d = configupdate_state.q;
+	configupdate3_state.clk = (! clock);
+	configupdate3_state.d = configupdate2_state.q;
+	configupdate_state.clk = clock;
+	configupdate_state.d = reconfig_post_state.q;
+	counter_param_latch_reg[].clk = clock;
+	counter_param_latch_reg[].clrn = (! reset);
+	counter_param_latch_reg[].d = counter_param[];
+	counter_param_latch_reg[].ena = input_latch_enable;
+	counter_type_latch_reg[].clk = clock;
+	counter_type_latch_reg[].clrn = (! reset);
+	counter_type_latch_reg[].d = counter_type[];
+	counter_type_latch_reg[].ena = input_latch_enable;
+	idle_state.clk = clock;
+	idle_state.clrn = (! reset);
+	idle_state.d = ((((((((((idle_state.q & (! read_param)) & (! write_param)) & (! reconfig)) & (! write_from_rom)) # read_last_state.q) # (write_data_state.q & width_counter_done)) # (write_nominal_state.q & width_counter_done)) # read_last_nominal_state.q) # (reconfig_wait_state.q & reconfig_done)) # reset_state.q);
+	nominal_data[].clk = clock;
+	nominal_data[].clrn = (! reset);
+	nominal_data[].d = ( cmpr7.aeb, data_in[8..0], add_sub6.result[7..0]);
+	read_data_nominal_state.clk = clock;
+	read_data_nominal_state.clrn = (! reset);
+	read_data_nominal_state.d = ((read_first_nominal_state.q & (! width_counter_done)) # (read_data_nominal_state.q & (! width_counter_done)));
+	read_data_state.clk = clock;
+	read_data_state.clrn = (! reset);
+	read_data_state.d = ((read_first_state.q & (! width_counter_done)) # (read_data_state.q & (! width_counter_done)));
+	read_first_nominal_state.clk = clock;
+	read_first_nominal_state.clrn = (! reset);
+	read_first_nominal_state.d = read_init_nominal_state.q;
+	read_first_state.clk = clock;
+	read_first_state.clrn = (! reset);
+	read_first_state.d = read_init_state.q;
+	read_init_nominal_state.clk = clock;
+	read_init_nominal_state.clrn = (! reset);
+	read_init_nominal_state.d = ((idle_state.q & read_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]));
+	read_init_state.clk = clock;
+	read_init_state.clrn = (! reset);
+	read_init_state.d = ((idle_state.q & read_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])));
+	read_last_nominal_state.clk = clock;
+	read_last_nominal_state.clrn = (! reset);
+	read_last_nominal_state.d = ((read_first_nominal_state.q & width_counter_done) # (read_data_nominal_state.q & width_counter_done));
+	read_last_state.clk = clock;
+	read_last_state.clrn = (! reset);
+	read_last_state.d = ((read_first_state.q & width_counter_done) # (read_data_state.q & width_counter_done));
+	reconfig_counter_state.clk = clock;
+	reconfig_counter_state.clrn = (! reset);
+	reconfig_counter_state.d = ((((((((((reconfig_init_state.q # C0_data_state.q) # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q) # C0_ena_state.q) # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q);
+	reconfig_init_state.clk = clock;
+	reconfig_init_state.clrn = (! reset);
+	reconfig_init_state.d = (idle_state.q & reconfig);
+	reconfig_post_state.clk = clock;
+	reconfig_post_state.clrn = (! reset);
+	reconfig_post_state.d = ((reconfig_seq_data_state.q & reconfig_width_counter_done) # (reconfig_post_state.q & (! reconfig_post_done)));
+	reconfig_seq_data_state.clk = clock;
+	reconfig_seq_data_state.clrn = (! reset);
+	reconfig_seq_data_state.d = (reconfig_seq_ena_state.q # (reconfig_seq_data_state.q & (! reconfig_width_counter_done)));
+	reconfig_seq_ena_state.clk = clock;
+	reconfig_seq_ena_state.clrn = (! reset);
+	reconfig_seq_ena_state.d = tmp_seq_ena_state.q;
+	reconfig_wait_state.clk = clock;
+	reconfig_wait_state.clrn = (! reset);
+	reconfig_wait_state.d = ((reconfig_post_state.q & reconfig_post_done) # (reconfig_wait_state.q & (! reconfig_done)));
+	reset_state.clk = clock;
+	reset_state.d = power_up;
+	reset_state.prn = (! reset);
+	shift_reg[].clk = clock;
+	shift_reg[].clrn = (! reset);
+	shift_reg[].d = ( ((((shift_reg_load_nominal_enable & nominal_data[0].q) # (shift_reg_load_enable & data_in[0..0])) # (shift_reg_shift_enable & shift_reg[16].q)) # (shift_reg_shift_nominal_enable & shift_reg[16].q)), ((((shift_reg_load_nominal_enable & nominal_data[1].q) # (shift_reg_load_enable & data_in[1..1])) # (shift_reg_shift_enable & shift_reg[15].q)) # (shift_reg_shift_nominal_enable & shift_reg[15].q)), ((((shift_reg_load_nominal_enable & nominal_data[2].q) # (shift_reg_load_enable & data_in[2..2])) # (shift_reg_shift_enable & shift_reg[14].q)) # (shift_reg_shift_nominal_enable & shift_reg[14].q)), ((((shift_reg_load_nominal_enable & nominal_data[3].q) # (shift_reg_load_enable & data_in[3..3])) # (shift_reg_shift_enable & shift_reg[13].q)) # (shift_reg_shift_nominal_enable & shift_reg[13].q)), ((((shift_reg_load_nominal_enable & nominal_data[4].q) # (shift_reg_load_enable & data_in[4..4])) # (shift_reg_shift_enable & shift_reg[12].q)) # (shift_reg_shift_nominal_enable & shift_reg[12].q)), ((((shift_reg_load_nominal_enable & nominal_data[5].q) # (shift_reg_load_enable & data_in[5..5])) # (shift_reg_shift_enable & shift_reg[11].q)) # (shift_reg_shift_nominal_enable & shift_reg[11].q)), ((((shift_reg_load_nominal_enable & nominal_data[6].q) # (shift_reg_load_enable & data_in[6..6])) # (shift_reg_shift_enable & shift_reg[10].q)) # (shift_reg_shift_nominal_enable & shift_reg[10].q)), ((((shift_reg_load_nominal_enable & nominal_data[7].q) # (shift_reg_load_enable & data_in[7..7])) # (shift_reg_shift_enable & shift_reg[9].q)) # (shift_reg_shift_nominal_enable & shift_reg[9].q)), ((((shift_reg_load_nominal_enable & nominal_data[8].q) # (shift_reg_load_enable & data_in[8..8])) # (shift_reg_shift_enable & shift_reg[8].q)) # (shift_reg_shift_nominal_enable & shift_reg[8].q)), ((((shift_reg_load_nominal_enable & nominal_data[9].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[7].q)) # (shift_reg_shift_nominal_enable & shift_reg[7].q)), ((((shift_reg_load_nominal_enable & nominal_data[10].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[6].q)) # (shift_reg_shift_nominal_enable & shift_reg[6].q)), ((((shift_reg_load_nominal_enable & nominal_data[11].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[5].q)) # (shift_reg_shift_nominal_enable & shift_reg[5].q)), ((((shift_reg_load_nominal_enable & nominal_data[12].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[4].q)) # (shift_reg_shift_nominal_enable & shift_reg[4].q)), ((((shift_reg_load_nominal_enable & nominal_data[13].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[3].q)) # (shift_reg_shift_nominal_enable & shift_reg[3].q)), ((((shift_reg_load_nominal_enable & nominal_data[14].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[2].q)) # (shift_reg_shift_nominal_enable & shift_reg[2].q)), ((((shift_reg_load_nominal_enable & nominal_data[15].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[1].q)) # (shift_reg_shift_nominal_enable & shift_reg[1].q)), ((((shift_reg_load_nominal_enable & nominal_data[16].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg[0].q)) # (shift_reg_shift_nominal_enable & shift_reg[0].q)), ((((shift_reg_load_nominal_enable & nominal_data[17].q) # (shift_reg_load_enable & w64w)) # (shift_reg_shift_enable & shift_reg_serial_in)) # (shift_reg_shift_nominal_enable & shift_reg_serial_in)));
+	shift_reg[].ena = ((((shift_reg_load_enable # shift_reg_shift_enable) # shift_reg_load_nominal_enable) # shift_reg_shift_nominal_enable) # shift_reg_clear);
+	shift_reg[].sclr = shift_reg_clear;
+	tmp_nominal_data_out_state.clk = clock;
+	tmp_nominal_data_out_state.d = ((read_last_nominal_state.q & (! idle_state.q)) # (tmp_nominal_data_out_state.q & idle_state.q));
+	tmp_seq_ena_state.clk = clock;
+	tmp_seq_ena_state.d = (reconfig_counter_state.q & (C0_data_state.q & rotate_width_counter_done));
+	write_data_state.clk = clock;
+	write_data_state.clrn = (! reset);
+	write_data_state.d = (write_init_state.q # (write_data_state.q & (! width_counter_done)));
+	write_init_nominal_state.clk = clock;
+	write_init_nominal_state.clrn = (! reset);
+	write_init_nominal_state.d = ((idle_state.q & write_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]));
+	write_init_state.clk = clock;
+	write_init_state.clrn = (! reset);
+	write_init_state.d = ((idle_state.q & write_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])));
+	write_nominal_state.clk = clock;
+	write_nominal_state.clrn = (! reset);
+	write_nominal_state.d = (write_init_nominal_state.q # (write_nominal_state.q & (! width_counter_done)));
+	add_sub5.cin = B"0";
+	add_sub5.dataa[] = ( B"0", shift_reg[8..1].q);
+	add_sub5.datab[] = ( B"0", shift_reg[17..10].q);
+	add_sub6.cin = data_in[0..0];
+	add_sub6.dataa[] = ( data_in[8..1]);
+	cmpr7.dataa[] = ( data_in[7..0]);
+	cmpr7.datab[] = B"00000001";
+	cntr1.clock = clock;
+	cntr1.cnt_en = addr_counter_enable;
+	cntr1.data[] = addr_counter_sload_value[];
+	cntr1.sload = addr_counter_sload;
+	cntr12.clock = clock;
+	cntr12.cnt_en = reconfig_addr_counter_enable;
+	cntr12.data[] = reconfig_addr_counter_sload_value[];
+	cntr12.sload = reconfig_addr_counter_sload;
+	cntr13.clock = clock;
+	cntr13.cnt_en = reconfig_width_counter_enable;
+	cntr13.data[] = reconfig_width_counter_sload_value[];
+	cntr13.sload = reconfig_width_counter_sload;
+	cntr14.clock = clock;
+	cntr14.cnt_en = rotate_width_counter_enable;
+	cntr14.data[] = rotate_width_counter_sload_value[];
+	cntr14.sload = rotate_width_counter_sload;
+	cntr15.clock = clock;
+	cntr15.cnt_en = rotate_addr_counter_enable;
+	cntr15.data[] = rotate_addr_counter_sload_value[];
+	cntr15.sload = rotate_addr_counter_sload;
+	cntr2.clock = clock;
+	cntr2.cnt_en = read_addr_counter_enable;
+	cntr2.data[] = read_addr_counter_sload_value[];
+	cntr2.sload = read_addr_counter_sload;
+	cntr3.clock = clock;
+	cntr3.cnt_en = width_counter_enable;
+	cntr3.data[] = width_counter_sload_value[];
+	cntr3.sload = width_counter_sload;
+	decode11.data[] = cuda_combout_wire[];
+	addr_counter_enable = (write_data_state.q # write_nominal_state.q);
+	addr_counter_out[] = cntr1.q[];
+	addr_counter_sload = (write_init_state.q # write_init_nominal_state.q);
+	addr_counter_sload_value[] = (addr_decoder_out[] & (write_init_state.q # write_init_nominal_state.q));
+	addr_decoder_out[] = (((((((((((((((((((((((((((((((((((( B"0", B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_bypass_LF_unused)) # ( B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_c), (sel_type_cplf & sel_param_c))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_low_r), B"0", B"0", B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_vco & sel_param_high_i_postscale), B"0", B"0", (sel_type_vco & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_odd_CP_unused), (sel_type_cplf & sel_param_odd_CP_unused), (sel_type_cplf & sel_param_odd_CP_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale), B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_high_i_postscale), (sel_type_n & sel_param_high_i_postscale), B"0", (sel_type_n & sel_param_high_i_postscale), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused), B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_n & sel_param_low_r), B"0", B"0", B"0", (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r))) # ( B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0", B"0", B"0", (sel_type_n & sel_param_nominal_count), (sel_type_n & sel_param_nominal_count))) # ( B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", (sel_type_m & sel_param_high_i_postscale), (sel_type_m & sel_param_high_i_postscale), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused), (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r))) # ( B"0", B"0", (sel_type_m & sel_param_nominal_count), (sel_type_m & sel_param_nominal_count), B"0", (sel_type_m & sel_param_nominal_count), B"0", (sel_type_m & sel_param_nominal_count))) # ( B"0", B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c0 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c0 & sel_param_low_r), (sel_type_c0 & sel_param_low_r), (sel_type_c0 & sel_param_low_r))) # ( B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c1 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c1 & sel_param_low_r), B"0", (sel_type_c1 & sel_param_low_r), (sel_type_c1 & sel_param_low_r), B"0", B"0", (sel_type_c1 & sel_param_low_r))) # ( B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale), B"0", B"0", B"0", (sel_type_c2 & sel_param_high_i_postscale), B"0")) # ( B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r), B"0", (sel_type_c2 & sel_param_low_r), B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r))) # ( B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0", (sel_type_c3 & sel_param_low_r))) # ( B"0", (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), B"0")) # ( (sel_type_c4 & sel_param_high_i_postscale), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), B"0")) # ( (sel_type_c4 & sel_param_odd_CP_unused), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused))) # ( (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r), (sel_type_c4 & sel_param_low_r)));
+	busy = ((! idle_state.q) # areset_state.q);
+	c0_wire[] = B"01000111";
+	c1_wire[] = B"01011001";
+	c2_wire[] = B"01101011";
+	c3_wire[] = B"01111101";
+	c4_wire[] = B"10001111";
+	counter_param_latch[] = counter_param_latch_reg[].q;
+	counter_type_latch[] = counter_type_latch_reg[].q;
+	cuda_combout_wire[] = ( le_comb10.combout, le_comb9.combout, le_comb8.combout);
+	data_out[] = ( ((shift_reg[8].q & (! read_nominal_out)) # (add_sub5.result[8..8] & read_nominal_out)), ((shift_reg[7].q & (! read_nominal_out)) # (add_sub5.result[7..7] & read_nominal_out)), ((shift_reg[6].q & (! read_nominal_out)) # (add_sub5.result[6..6] & read_nominal_out)), ((shift_reg[5].q & (! read_nominal_out)) # (add_sub5.result[5..5] & read_nominal_out)), ((shift_reg[4].q & (! read_nominal_out)) # (add_sub5.result[4..4] & read_nominal_out)), ((shift_reg[3].q & (! read_nominal_out)) # (add_sub5.result[3..3] & read_nominal_out)), ((shift_reg[2].q & (! read_nominal_out)) # (add_sub5.result[2..2] & read_nominal_out)), ((shift_reg[1].q & (! read_nominal_out)) # (add_sub5.result[1..1] & read_nominal_out)), ((shift_reg[0].q & (! read_nominal_out)) # (add_sub5.result[0..0] & read_nominal_out)));
+	dummy_scandataout = pll_scandataout;
+	encode_out[] = ( C4_ena_state.q, (C2_ena_state.q # C3_ena_state.q), (C1_ena_state.q # C3_ena_state.q));
+	input_latch_enable = (idle_state.q & (write_param # read_param));
+	pll_areset = (pll_areset_in # (areset_state.q & reconfig_wait_state.q));
+	pll_configupdate = (configupdate_state.q & (! configupdate3_state.q));
+	pll_scanclk = clock;
+	pll_scanclkena = ((rotate_width_counter_enable & (! rotate_width_counter_done)) # reconfig_seq_data_state.q);
+	pll_scandata = (scan_cache_out & ((rotate_width_counter_enable # reconfig_seq_data_state.q) # reconfig_post_state.q));
+	power_up = ((((((((((((((((((((! reset_state.q) & (! idle_state.q)) & (! read_init_state.q)) & (! read_first_state.q)) & (! read_data_state.q)) & (! read_last_state.q)) & (! read_init_nominal_state.q)) & (! read_first_nominal_state.q)) & (! read_data_nominal_state.q)) & (! read_last_nominal_state.q)) & (! write_init_state.q)) & (! write_data_state.q)) & (! write_init_nominal_state.q)) & (! write_nominal_state.q)) & (! reconfig_init_state.q)) & (! reconfig_counter_state.q)) & (! reconfig_seq_ena_state.q)) & (! reconfig_seq_data_state.q)) & (! reconfig_post_state.q)) & (! reconfig_wait_state.q));
+	read_addr_counter_enable = (((read_first_state.q # read_data_state.q) # read_first_nominal_state.q) # read_data_nominal_state.q);
+	read_addr_counter_out[] = cntr2.q[];
+	read_addr_counter_sload = (read_init_state.q # read_init_nominal_state.q);
+	read_addr_counter_sload_value[] = (read_addr_decoder_out[] & (read_init_state.q # read_init_nominal_state.q));
+	read_addr_decoder_out[] = (((((((((((((((((((((((((((((((((((( B"0", B"0", B"0", B"0", B"0", B"0", B"0", B"0") # ( B"0", B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_c), B"0")) # ( B"0", B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_low_r), B"0", B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_vco & sel_param_high_i_postscale), B"0", B"0", (sel_type_vco & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_odd_CP_unused), B"0", (sel_type_cplf & sel_param_odd_CP_unused), B"0")) # ( B"0", B"0", B"0", B"0", (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale), (sel_type_cplf & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_n & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_high_i_postscale), B"0", B"0", (sel_type_n & sel_param_high_i_postscale), (sel_type_n & sel_param_high_i_postscale))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused), B"0", (sel_type_n & sel_param_odd_CP_unused), (sel_type_n & sel_param_odd_CP_unused))) # ( B"0", B"0", B"0", (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r), (sel_type_n & sel_param_low_r), B"0", B"0")) # ( B"0", B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0", B"0", (sel_type_n & sel_param_nominal_count), B"0")) # ( B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_m & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", B"0", (sel_type_m & sel_param_high_i_postscale), B"0", (sel_type_m & sel_param_high_i_postscale))) # ( B"0", B"0", (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused), (sel_type_m & sel_param_odd_CP_unused), B"0", (sel_type_m & sel_param_odd_CP_unused))) # ( B"0", B"0", (sel_type_m & sel_param_low_r), B"0", (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), (sel_type_m & sel_param_low_r), B"0")) # ( B"0", B"0", (sel_type_m & sel_param_nominal_count), B"0", B"0", (sel_type_m & sel_param_nominal_count), B"0", B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0", (sel_type_c0 & sel_param_bypass_LF_unused), (sel_type_c0 & sel_param_bypass_LF_unused), B"0")) # ( B"0", B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), B"0", (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale), (sel_type_c0 & sel_param_high_i_postscale))) # ( B"0", B"0", (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused), (sel_type_c0 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c0 & sel_param_low_r), B"0", B"0", B"0", B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", (sel_type_c1 & sel_param_bypass_LF_unused), B"0", B"0", B"0")) # ( B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", (sel_type_c1 & sel_param_high_i_postscale), B"0", B"0", (sel_type_c1 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", (sel_type_c1 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c1 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c1 & sel_param_low_r), B"0", (sel_type_c1 & sel_param_low_r), B"0", B"0", (sel_type_c1 & sel_param_low_r), B"0")) # ( B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), (sel_type_c2 & sel_param_bypass_LF_unused), B"0", (sel_type_c2 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c2 & sel_param_high_i_postscale), B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale), B"0", (sel_type_c2 & sel_param_high_i_postscale), (sel_type_c2 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused), B"0", B"0", B"0", (sel_type_c2 & sel_param_odd_CP_unused), (sel_type_c2 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c2 & sel_param_low_r), (sel_type_c2 & sel_param_low_r), B"0", B"0", (sel_type_c2 & sel_param_low_r), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", (sel_type_c3 & sel_param_bypass_LF_unused), (sel_type_c3 & sel_param_bypass_LF_unused), B"0", B"0")) # ( B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale), (sel_type_c3 & sel_param_high_i_postscale), B"0", (sel_type_c3 & sel_param_high_i_postscale))) # ( B"0", (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused), B"0", (sel_type_c3 & sel_param_odd_CP_unused))) # ( B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0", (sel_type_c3 & sel_param_low_r), (sel_type_c3 & sel_param_low_r), B"0")) # ( B"0", (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), (sel_type_c4 & sel_param_bypass_LF_unused), B"0")) # ( B"0", (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale), (sel_type_c4 & sel_param_high_i_postscale))) # ( (sel_type_c4 & sel_param_odd_CP_unused), B"0", B"0", B"0", B"0", (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused), (sel_type_c4 & sel_param_odd_CP_unused))) # ( (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0", (sel_type_c4 & sel_param_low_r), B"0", B"0", B"0"));
+	read_nominal_out = tmp_nominal_data_out_state.q;
+	reconfig_addr_counter_enable = reconfig_seq_data_state.q;
+	reconfig_addr_counter_out[] = cntr12.q[];
+	reconfig_addr_counter_sload = reconfig_seq_ena_state.q;
+	reconfig_addr_counter_sload_value[] = (reconfig_seq_ena_state.q & seq_addr_wire[]);
+	reconfig_done = ((! pll_scandone) & (dummy_scandataout # (! dummy_scandataout)));
+	reconfig_post_done = pll_scandone;
+	reconfig_width_counter_done = ((((((! cntr13.q[0..0]) & (! cntr13.q[1..1])) & (! cntr13.q[2..2])) & (! cntr13.q[3..3])) & (! cntr13.q[4..4])) & (! cntr13.q[5..5]));
+	reconfig_width_counter_enable = reconfig_seq_data_state.q;
+	reconfig_width_counter_sload = reconfig_seq_ena_state.q;
+	reconfig_width_counter_sload_value[] = (reconfig_seq_ena_state.q & seq_sload_value[]);
+	rotate_addr_counter_enable = ((((C0_data_state.q # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q);
+	rotate_addr_counter_out[] = cntr15.q[];
+	rotate_addr_counter_sload = ((((C0_ena_state.q # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q);
+	rotate_addr_counter_sload_value[] = (((((c0_wire[] & rotate_decoder_wires[0..0]) # (c1_wire[] & rotate_decoder_wires[1..1])) # (c2_wire[] & rotate_decoder_wires[2..2])) # (c3_wire[] & rotate_decoder_wires[3..3])) # (c4_wire[] & rotate_decoder_wires[4..4]));
+	rotate_decoder_wires[] = decode11.eq[];
+	rotate_width_counter_done = (((((! cntr14.q[0..0]) & (! cntr14.q[1..1])) & (! cntr14.q[2..2])) & (! cntr14.q[3..3])) & (! cntr14.q[4..4]));
+	rotate_width_counter_enable = ((((C0_data_state.q # C1_data_state.q) # C2_data_state.q) # C3_data_state.q) # C4_data_state.q);
+	rotate_width_counter_sload = ((((C0_ena_state.q # C1_ena_state.q) # C2_ena_state.q) # C3_ena_state.q) # C4_ena_state.q);
+	rotate_width_counter_sload_value[] = B"10010";
+	scan_cache_address[] = ((((addr_counter_out[] & addr_counter_enable) # (read_addr_counter_out[] & read_addr_counter_enable)) # (rotate_addr_counter_out[] & rotate_addr_counter_enable)) # (reconfig_addr_counter_out[] & reconfig_addr_counter_enable));
+	scan_cache_in = shift_reg_serial_out;
+	scan_cache_out = altsyncram4.q_a[0..0];
+	scan_cache_write_enable = (write_data_state.q # write_nominal_state.q);
+	sel_param_bypass_LF_unused = (((! counter_param_latch[0..0]) & (! counter_param_latch[1..1])) & counter_param_latch[2..2]);
+	sel_param_c = (((! counter_param_latch[0..0]) & counter_param_latch[1..1]) & (! counter_param_latch[2..2]));
+	sel_param_high_i_postscale = (((! counter_param_latch[0..0]) & (! counter_param_latch[1..1])) & (! counter_param_latch[2..2]));
+	sel_param_low_r = ((counter_param_latch[0..0] & (! counter_param_latch[1..1])) & (! counter_param_latch[2..2]));
+	sel_param_nominal_count = ((counter_param_latch[0..0] & counter_param_latch[1..1]) & counter_param_latch[2..2]);
+	sel_param_odd_CP_unused = ((counter_param_latch[0..0] & (! counter_param_latch[1..1])) & counter_param_latch[2..2]);
+	sel_type_c0 = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & counter_type_latch[2..2]) & (! counter_type_latch[3..3]));
+	sel_type_c1 = (((counter_type_latch[0..0] & (! counter_type_latch[1..1])) & counter_type_latch[2..2]) & (! counter_type_latch[3..3]));
+	sel_type_c2 = ((((! counter_type_latch[0..0]) & counter_type_latch[1..1]) & counter_type_latch[2..2]) & (! counter_type_latch[3..3]));
+	sel_type_c3 = (((counter_type_latch[0..0] & counter_type_latch[1..1]) & counter_type_latch[2..2]) & (! counter_type_latch[3..3]));
+	sel_type_c4 = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & counter_type_latch[3..3]);
+	sel_type_cplf = ((((! counter_type_latch[0..0]) & counter_type_latch[1..1]) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3]));
+	sel_type_m = (((counter_type_latch[0..0] & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3]));
+	sel_type_n = ((((! counter_type_latch[0..0]) & (! counter_type_latch[1..1])) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3]));
+	sel_type_vco = (((counter_type_latch[0..0] & counter_type_latch[1..1]) & (! counter_type_latch[2..2])) & (! counter_type_latch[3..3]));
+	seq_addr_wire[] = B"00110101";
+	seq_sload_value[] = B"110110";
+	shift_reg_clear = (read_init_state.q # read_init_nominal_state.q);
+	shift_reg_load_enable = ((idle_state.q & write_param) & (! ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0])));
+	shift_reg_load_nominal_enable = ((idle_state.q & write_param) & ((((((! counter_type[3..3]) & (! counter_type[2..2])) & (! counter_type[1..1])) & counter_param[2..2]) & counter_param[1..1]) & counter_param[0..0]));
+	shift_reg_serial_in = scan_cache_out;
+	shift_reg_serial_out = ((((((((shift_reg[17].q & shift_reg_width_select[0..0]) # (shift_reg[17].q & shift_reg_width_select[1..1])) # (shift_reg[17].q & shift_reg_width_select[2..2])) # (shift_reg[17].q & shift_reg_width_select[3..3])) # (shift_reg[17].q & shift_reg_width_select[4..4])) # (shift_reg[17].q & shift_reg_width_select[5..5])) # (shift_reg[17].q & shift_reg_width_select[6..6])) # (shift_reg[17].q & shift_reg_width_select[7..7]));
+	shift_reg_shift_enable = ((read_data_state.q # read_last_state.q) # write_data_state.q);
+	shift_reg_shift_nominal_enable = ((read_data_nominal_state.q # read_last_nominal_state.q) # write_nominal_state.q);
+	shift_reg_width_select[] = width_decoder_select[];
+	w1565w = B"0";
+	w1592w = B"0";
+	w64w = B"0";
+	width_counter_done = (((((! cntr3.q[0..0]) & (! cntr3.q[1..1])) & (! cntr3.q[2..2])) & (! cntr3.q[3..3])) & (! cntr3.q[4..4]));
+	width_counter_enable = ((((read_first_state.q # read_data_state.q) # write_data_state.q) # read_data_nominal_state.q) # write_nominal_state.q);
+	width_counter_sload = (((read_init_state.q # write_init_state.q) # read_init_nominal_state.q) # write_init_nominal_state.q);
+	width_counter_sload_value[] = width_decoder_out[];
+	width_decoder_out[] = (((((( B"0", B"0", B"0", B"0", B"0") # ( width_decoder_select[2..2], B"0", B"0", B"0", width_decoder_select[2..2])) # ( B"0", B"0", B"0", B"0", width_decoder_select[3..3])) # ( B"0", B"0", width_decoder_select[5..5], width_decoder_select[5..5], width_decoder_select[5..5])) # ( B"0", B"0", B"0", width_decoder_select[6..6], B"0")) # ( B"0", B"0", width_decoder_select[7..7], B"0", B"0"));
+	width_decoder_select[] = ( ((sel_type_cplf & sel_param_low_r) # (sel_type_cplf & sel_param_odd_CP_unused)), (sel_type_cplf & sel_param_high_i_postscale), ((((((((((((((sel_type_n & sel_param_high_i_postscale) # (sel_type_n & sel_param_low_r)) # (sel_type_m & sel_param_high_i_postscale)) # (sel_type_m & sel_param_low_r)) # (sel_type_c0 & sel_param_high_i_postscale)) # (sel_type_c0 & sel_param_low_r)) # (sel_type_c1 & sel_param_high_i_postscale)) # (sel_type_c1 & sel_param_low_r)) # (sel_type_c2 & sel_param_high_i_postscale)) # (sel_type_c2 & sel_param_low_r)) # (sel_type_c3 & sel_param_high_i_postscale)) # (sel_type_c3 & sel_param_low_r)) # (sel_type_c4 & sel_param_high_i_postscale)) # (sel_type_c4 & sel_param_low_r)), w1592w, ((sel_type_cplf & sel_param_bypass_LF_unused) # (sel_type_cplf & sel_param_c)), ((sel_type_n & sel_param_nominal_count) # (sel_type_m & sel_param_nominal_count)), w1565w, (((((((((((((((sel_type_vco & sel_param_high_i_postscale) # (sel_type_n & sel_param_bypass_LF_unused)) # (sel_type_n & sel_param_odd_CP_unused)) # (sel_type_m & sel_param_bypass_LF_unused)) # (sel_type_m & sel_param_odd_CP_unused)) # (sel_type_c0 & sel_param_bypass_LF_unused)) # (sel_type_c0 & sel_param_odd_CP_unused)) # (sel_type_c1 & sel_param_bypass_LF_unused)) # (sel_type_c1 & sel_param_odd_CP_unused)) # (sel_type_c2 & sel_param_bypass_LF_unused)) # (sel_type_c2 & sel_param_odd_CP_unused)) # (sel_type_c3 & sel_param_bypass_LF_unused)) # (sel_type_c3 & sel_param_odd_CP_unused)) # (sel_type_c4 & sel_param_bypass_LF_unused)) # (sel_type_c4 & sel_param_odd_CP_unused)));
+	write_from_rom = GND;
+END;
+--VALID FILE
diff --git a/FPGA_quartus_GE/firebee1.bdf b/FPGA_quartus_GE/firebee1.bdf
new file mode 100644
index 0000000..46507a2
--- /dev/null
+++ b/FPGA_quartus_GE/firebee1.bdf
@@ -0,0 +1,5837 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+//#pragma file_not_in_maxplusii_format
+(header "graphic" (version "1.3"))
+(properties
+	(page_setup "header_footer\nDate: %D\n%f\nProject: %j\n\nPage %p of %P\nRevision: %a\nmargin\n1\n1\n1\n1\norientation\n1\npaper_size\n9\npaper_source\n15\nfit_page_wide\n1\nfit_page_tall\n1\n")
+)
+(pin
+	(input)
+	(rect 208 1392 376 1408)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "FB_ALE" (rect 9 0 60 15)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
+		(line (pt 121 8)(pt 168 8)(line_width 1))
+		(line (pt 92 12)(pt 92 4)(line_width 1))
+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
+	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 136 1408 192 1424))
+)
+(pin
+	(input)
+	(rect 992 936 1160 952)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "nFB_WR" (rect 9 0 66 15)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
+		(line (pt 121 8)(pt 168 8)(line_width 1))
+		(line (pt 92 12)(pt 92 4)(line_width 1))
+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
+	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 944 952 1000 968))
+)
+(pin
+	(input)
+	(rect 168 296 336 312)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "CLK33M" (rect 9 0 64 15)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
+		(line (pt 121 8)(pt 168 8)(line_width 1))
+		(line (pt 92 12)(pt 92 4)(line_width 1))
+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
+	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 104 312 176 328))
+)
+(pin
+	(input)
+	(rect 992 960 1160 976)
+	(text "INPUT" (rect 133 0 169 13)(font "Arial" (font_size 6)))
+	(text "nFB_CS1" (rect 5 0 67 15)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12)(line_width 1))
+		(line (pt 92 4)(pt 117 4)(line_width 1))
+		(line (pt 121 8)(pt 168 8)(line_width 1))
+		(line (pt 92 12)(pt 92 4)(line_width 1))
+		(line (pt 117 4)(pt 121 8)(line_width 1))
+		(line (pt 117 12)(pt 121 8)(line_width 1))
+	)
+	(text "VCC" (rect 136 7 160 20)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect 944 976 1000 992))
+)
+(pin
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+	(block_io "nFB_OE" (input))
+	(block_io "VSYNC" (input))
+	(block_io "HSYNC" (input))
+	(block_io "DSP_INT" (input))
+	(block_io "nBLANK" (input))
+	(block_io "FDC_CLK" (input))
+	(block_io "FB_ALE" (input))
+	(block_io "ACP_CONF[31..24]" (input))
+	(block_io "HD_DD" (input))
+	(block_io "nIDE_CS1" (output))
+	(block_io "nIDE_CS0" (output))
+	(block_io "LP_STR" (output))
+	(block_io "LP_DIR" (output))
+	(block_io "nACSI_ACK" (output))
+	(block_io "nACSI_RESET" (output))
+	(block_io "nACSI_CS" (output))
+	(block_io "ACSI_DIR" (output))
+	(block_io "ACSI_A1" (output))
+	(block_io "nSCSI_ACK" (output))
+	(block_io "nSCSI_ATN" (output))
+	(block_io "SCSI_DIR" (output))
+	(block_io "SD_CLK" (output))
+	(block_io "YM_QA" (output))
+	(block_io "YM_QC" (output))
+	(block_io "YM_QB" (output))
+	(block_io "nSDSEL" (output))
+	(block_io "STEP" (output))
+	(block_io "MOT_ON" (output))
+	(block_io "nRP_LDS" (output))
+	(block_io "nRP_UDS" (output))
+	(block_io "nROM4" (output))
+	(block_io "nROM3" (output))
+	(block_io "nCF_CS1" (output))
+	(block_io "nCF_CS0" (output))
+	(block_io "nIDE_RD" (output))
+	(block_io "nIDE_WR" (output))
+	(block_io "AMKB_TX" (output))
+	(block_io "IDE_RES" (output))
+	(block_io "DTR" (output))
+	(block_io "RTS" (output))
+	(block_io "TxD" (output))
+	(block_io "MIDI_OLR" (output))
+	(block_io "MIDI_TLR" (output))
+	(block_io "nDREQ0" (output))
+	(block_io "DSA_D" (output))
+	(block_io "nMFP_INT" (output))
+	(block_io "FALCON_IO_TA" (output))
+	(block_io "STEP_DIR" (output))
+	(block_io "WR_DATA" (output))
+	(block_io "WR_GATE" (output))
+	(block_io "DMA_DRQ" (output))
+	(block_io "FB_AD[31..0]" (bidir))
+	(block_io "LP_D[7..0]" (bidir))
+	(block_io "ACSI_D[7..0]" (bidir))
+	(block_io "SCSI_D[7..0]" (bidir))
+	(block_io "SCSI_PAR" (bidir))
+	(block_io "nSCSI_SEL" (bidir))
+	(block_io "nSCSI_BUSY" (bidir))
+	(block_io "nSCSI_RST" (bidir))
+	(block_io "SD_CD_DATA3" (bidir))
+	(block_io "SD_CDM_D1" (bidir))
+	(mapper
+		(pt 0 128)
+		(bidir)
+		)
+	(mapper
+		(pt 0 104)
+		(bidir)
+		)
+	(mapper
+		(pt 0 56)
+		(bidir)
+		)
+	(mapper
+		(pt 0 80)
+		(bidir)
+		)
+	(mapper
+		(pt 0 224)
+		(bidir)
+		)
+	(mapper
+		(pt 0 248)
+		(bidir)
+		)
+	(mapper
+		(pt 0 272)
+		(bidir)
+		)
+	(mapper
+		(pt 408 96)
+		(bidir)
+		)
+	(mapper
+		(pt 408 120)
+		(bidir)
+		)
+	(mapper
+		(pt 408 72)
+		(bidir)
+		)
+	(mapper
+		(pt 408 152)
+		(bidir)
+		)
+	(mapper
+		(pt 408 200)
+		(bidir)
+		)
+	(mapper
+		(pt 408 224)
+		(bidir)
+		)
+	(mapper
+		(pt 408 248)
+		(bidir)
+		)
+	(mapper
+		(pt 408 272)
+		(bidir)
+		)
+	(mapper
+		(pt 408 296)
+		(bidir)
+		)
+	(mapper
+		(pt 408 424)
+		(bidir)
+		)
+	(mapper
+		(pt 408 352)
+		(bidir)
+		)
+	(mapper
+		(pt 408 328)
+		(bidir)
+		)
+	(mapper
+		(pt 408 448)
+		(bidir)
+		)
+	(mapper
+		(pt 408 400)
+		(bidir)
+		)
+	(mapper
+		(pt 408 376)
+		(bidir)
+		)
+	(mapper
+		(pt 408 472)
+		(bidir)
+		)
+	(mapper
+		(pt 408 496)
+		(bidir)
+		)
+	(mapper
+		(pt 408 608)
+		(bidir)
+		)
+	(mapper
+		(pt 408 632)
+		(bidir)
+		)
+	(mapper
+		(pt 408 528)
+		(bidir)
+		)
+	(mapper
+		(pt 408 552)
+		(bidir)
+		)
+	(mapper
+		(pt 408 584)
+		(bidir)
+		)
+	(mapper
+		(pt 0 624)
+		(bidir)
+		)
+	(mapper
+		(pt 0 656)
+		(bidir)
+		)
+	(mapper
+		(pt 0 680)
+		(bidir)
+		)
+	(mapper
+		(pt 0 704)
+		(bidir)
+		)
+	(mapper
+		(pt 0 728)
+		(bidir)
+		)
+	(mapper
+		(pt 0 752)
+		(bidir)
+		)
+	(mapper
+		(pt 0 776)
+		(bidir)
+		)
+	(mapper
+		(pt 408 664)
+		(bidir)
+		)
+	(mapper
+		(pt 0 808)
+		(bidir)
+		)
+	(mapper
+		(pt 0 832)
+		(bidir)
+		)
+	(mapper
+		(pt 408 696)
+		(bidir)
+		)
+	(mapper
+		(pt 408 720)
+		(bidir)
+		)
+	(mapper
+		(pt 408 744)
+		(bidir)
+		)
+	(mapper
+		(pt 408 768)
+		(bidir)
+		)
+	(mapper
+		(pt 408 792)
+		(bidir)
+		)
+	(mapper
+		(pt 408 816)
+		(bidir)
+		)
+	(mapper
+		(pt 408 840)
+		(bidir)
+		)
+	(mapper
+		(pt 0 856)
+		(bidir)
+		)
+	(mapper
+		(pt 408 872)
+		(bidir)
+		)
+	(mapper
+		(pt 408 896)
+		(bidir)
+		)
+	(mapper
+		(pt 408 920)
+		(bidir)
+		)
+	(mapper
+		(pt 408 944)
+		(bidir)
+		)
+	(mapper
+		(pt 0 912)
+		(bidir)
+		)
+	(mapper
+		(pt 0 936)
+		(bidir)
+		)
+	(mapper
+		(pt 0 960)
+		(bidir)
+		)
+	(mapper
+		(pt 0 984)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1008)
+		(bidir)
+		)
+	(mapper
+		(pt 408 976)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1000)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1072)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1096)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1176)
+		(bidir)
+		)
+	(mapper
+		(pt 0 296)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1256)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1040)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1064)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1088)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1112)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1136)
+		(bidir)
+		)
+	(mapper
+		(pt 0 432)
+		(bidir)
+		)
+	(mapper
+		(pt 0 464)
+		(bidir)
+		)
+	(mapper
+		(pt 0 488)
+		(bidir)
+		)
+	(mapper
+		(pt 0 520)
+		(bidir)
+		)
+	(mapper
+		(pt 0 544)
+		(bidir)
+		)
+	(mapper
+		(pt 0 568)
+		(bidir)
+		)
+	(mapper
+		(pt 0 592)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1424)
+		(bidir)
+		)
+	(mapper
+		(pt 0 320)
+		(bidir)
+		)
+	(mapper
+		(pt 0 200)
+		(bidir)
+		)
+	(mapper
+		(pt 0 344)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1168)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1192)
+		(bidir)
+		)
+	(mapper
+		(pt 0 368)
+		(bidir)
+		)
+	(mapper
+		(pt 0 392)
+		(bidir)
+		)
+	(mapper
+		(pt 0 176)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1216)
+		(bidir)
+		)
+	(mapper
+		(pt 408 48)
+		(bidir)
+		)
+	(mapper
+		(pt 408 16)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1240)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1304)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1200)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1344)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1280)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1224)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1120)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1048)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1024)
+		(bidir)
+		)
+	(mapper
+		(pt 0 32)
+		(bidir)
+		)
+	(mapper
+		(pt 0 152)
+		(bidir)
+		)
+	(mapper
+		(pt 408 1368)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1264)
+		(bidir)
+		)
+	(mapper
+		(pt 0 1336)
+		(bidir)
+		)
+	(mapper
+		(pt 0 888)
+		(bidir)
+		)
+)
+(block
+	(rect 1264 -48 1672 728)
+	(text "Video" (rect 5 5 43 21)(font "Arial" (font_size 8)))	(text "Fredi_Aschwanden" (rect 5 762 130 777)(font "Arial" ))	(block_io "FB_ADR[31..0]" (input))
+	(block_io "MAIN_CLK" (input))
+	(block_io "nFB_CS1" (input))
+	(block_io "nFB_CS2" (input))
+	(block_io "nFB_CS3" (input))
+	(block_io "nFB_WR" (input))
+	(block_io "FB_SIZE0" (input))
+	(block_io "FB_SIZE1" (input))
+	(block_io "nRSTO" (input))
+	(block_io "nFB_OE" (input))
+	(block_io "FB_ALE" (input))
+	(block_io "DDRCLK[3..0]" (input))
+	(block_io "DDR_SYNC_66M" (input))
+	(block_io "CLK33M" (input))
+	(block_io "CLK25M" (input))
+	(block_io "CLK_VIDEO" (input))
+	(block_io "VR_D[8..0]" (input))
+	(block_io "VR_BUSY" (input))
+	(block_io "VR_RD" (output))
+	(block_io "VG[7..0]" (output))
+	(block_io "VB[7..0]" (output))
+	(block_io "VR[7..0]" (output))
+	(block_io "nBLANK" (output))
+	(block_io "VA[12..0]" (output))
+	(block_io "nVWE" (output))
+	(block_io "nVCAS" (output))
+	(block_io "nVRAS" (output))
+	(block_io "nVCS" (output))
+	(block_io "VDM[3..0]" (output))
+	(block_io "nPD_VGA" (output))
+	(block_io "VCKE" (output))
+	(block_io "VSYNC" (output))
+	(block_io "HSYNC" (output))
+	(block_io "nSYNC" (output))
+	(block_io "VIDEO_TA" (output))
+	(block_io "PIXEL_CLK" (output))
+	(block_io "BA[1..0]" (output))
+	(block_io "VIDEO_RECONFIG" (output))
+	(block_io "VR_WR" (output))
+	(block_io "VDQS[3..0]" (bidir))
+	(block_io "FB_AD[31..0]" (bidir))
+	(block_io "VD[31..0]" (bidir))
+	(mapper
+		(pt 408 448)
+		(bidir)
+		)
+	(mapper
+		(pt 408 496)
+		(bidir)
+		)
+	(mapper
+		(pt 408 592)
+		(bidir)
+		)
+	(mapper
+		(pt 408 352)
+		(bidir)
+		)
+	(mapper
+		(pt 408 760)
+		(bidir)
+		)
+	(mapper
+		(pt 408 72)
+		(bidir)
+		)
+	(mapper
+		(pt 0 392)
+		(bidir)
+		)
+	(mapper
+		(pt 0 248)
+		(bidir)
+		)
+	(mapper
+		(pt 0 272)
+		(bidir)
+		)
+	(mapper
+		(pt 0 320)
+		(bidir)
+		)
+	(mapper
+		(pt 0 344)
+		(bidir)
+		)
+	(mapper
+		(pt 0 152)
+		(bidir)
+		)
+	(mapper
+		(pt 0 104)
+		(bidir)
+		)
+	(mapper
+		(pt 0 296)
+		(bidir)
+		)
+	(mapper
+		(pt 408 128)
+		(bidir)
+		)
+	(mapper
+		(pt 408 152)
+		(bidir)
+		)
+	(mapper
+		(pt 408 176)
+		(bidir)
+		)
+	(mapper
+		(pt 408 200)
+		(bidir)
+		)
+	(mapper
+		(pt 408 224)
+		(bidir)
+		)
+	(mapper
+		(pt 408 248)
+		(bidir)
+		)
+	(mapper
+		(pt 408 272)
+		(bidir)
+		)
+	(mapper
+		(pt 408 296)
+		(bidir)
+		)
+	(mapper
+		(pt 0 416)
+		(bidir)
+		)
+	(mapper
+		(pt 408 320)
+		(bidir)
+		)
+	(mapper
+		(pt 408 472)
+		(bidir)
+		)
+	(mapper
+		(pt 408 424)
+		(bidir)
+		)
+	(mapper
+		(pt 408 400)
+		(bidir)
+		)
+	(mapper
+		(pt 408 376)
+		(bidir)
+		)
+	(mapper
+		(pt 0 224)
+		(bidir)
+		)
+	(mapper
+		(pt 0 368)
+		(bidir)
+		)
+	(mapper
+		(pt 0 200)
+		(bidir)
+		)
+	(mapper
+		(pt 0 176)
+		(bidir)
+		)
+	(mapper
+		(pt 408 568)
+		(bidir)
+		)
+	(mapper
+		(pt 408 520)
+		(bidir)
+		)
+	(mapper
+		(pt 0 648)
+		(bidir)
+		)
+	(mapper
+		(pt 0 672)
+		(bidir)
+		)
+	(mapper
+		(pt 0 616)
+		(bidir)
+		)
+	(mapper
+		(pt 0 528)
+		(bidir)
+		)
+	(mapper
+		(pt 408 656)
+		(bidir)
+		)
+	(mapper
+		(pt 408 640)
+		(bidir)
+		)
+	(mapper
+		(pt 408 624)
+		(bidir)
+		)
+	(mapper
+		(pt 0 512)
+		(bidir)
+		)
+)
+(connector
+	(text "FB_AD[31..0]" (rect 1682 776 1765 791)(font "Arial" ))
+	(pt 1832 792)
+	(pt 1672 792)
+	(bus)
+)
+(connector
+	(text "FB_ADR[31..0]" (rect 1146 1072 1240 1087)(font "Arial" ))
+	(pt 1112 1088)
+	(pt 1264 1088)
+	(bus)
+)
+(connector
+	(text "MAIN_CLK" (rect 1162 784 1231 799)(font "Arial" ))
+	(pt 1152 800)
+	(pt 1264 800)
+)
+(connector
+	(text "CLK33M" (rect 1210 760 1265 775)(font "Arial" ))
+	(pt 1200 776)
+	(pt 1264 776)
+)
+(connector
+	(text "CLK2M" (rect 1202 808 1249 823)(font "Arial" ))
+	(pt 1192 824)
+	(pt 1264 824)
+)
+(connector
+	(text "CLK500k" (rect 1202 832 1262 847)(font "Arial" ))
+	(pt 1192 848)
+	(pt 1264 848)
+)
+(connector
+	(text "LP_DIR" (rect 1682 848 1732 863)(font "Arial" ))
+	(pt 1672 864)
+	(pt 1832 864)
+)
+(connector
+	(text "LP_STR" (rect 1682 824 1736 839)(font "Arial" ))
+	(pt 1672 840)
+	(pt 1832 840)
+)
+(connector
+	(text "nACSI_ACK" (rect 1682 928 1758 943)(font "Arial" ))
+	(pt 1672 944)
+	(pt 1832 944)
+)
+(connector
+	(text "nACSI_RESET" (rect 1682 952 1777 967)(font "Arial" ))
+	(pt 1672 968)
+	(pt 1832 968)
+)
+(connector
+	(text "nACSI_CS" (rect 1682 976 1750 991)(font "Arial" ))
+	(pt 1672 992)
+	(pt 1832 992)
+)
+(connector
+	(text "ACSI_DIR" (rect 1682 1000 1746 1015)(font "Arial" ))
+	(pt 1672 1016)
+	(pt 1832 1016)
+)
+(connector
+	(text "ACSI_A1" (rect 1682 1024 1738 1039)(font "Arial" ))
+	(pt 1672 1040)
+	(pt 1832 1040)
+)
+(connector
+	(text "nSCSI_ATN" (rect 1682 1128 1758 1143)(font "Arial" ))
+	(pt 1672 1144)
+	(pt 1840 1144)
+)
+(connector
+	(text "SCSI_DIR" (rect 1682 1152 1748 1167)(font "Arial" ))
+	(pt 1672 1168)
+	(pt 1840 1168)
+)
+(connector
+	(text "nSCSI_DRQ" (rect 1114 1248 1195 1263)(font "Arial" ))
+	(pt 1264 1264)
+	(pt 1104 1264)
+)
+(connector
+	(text "nSCSI_MSG" (rect 1114 1320 1194 1335)(font "Arial" ))
+	(pt 1104 1336)
+	(pt 1264 1336)
+)
+(connector
+	(text "nSCSI_RST" (rect 1682 1176 1759 1191)(font "Arial" ))
+	(pt 1672 1192)
+	(pt 1840 1192)
+)
+(connector
+	(text "nSCSI_SEL" (rect 1680 1200 1756 1215)(font "Arial" ))
+	(pt 1672 1216)
+	(pt 1840 1216)
+)
+(connector
+	(text "nSCSI_BUSY" (rect 1682 1224 1769 1239)(font "Arial" ))
+	(pt 1672 1240)
+	(pt 1840 1240)
+)
+(connector
+	(text "TxD" (rect 1682 1312 1706 1327)(font "Arial" ))
+	(pt 1672 1328)
+	(pt 1840 1328)
+)
+(connector
+	(text "RTS" (rect 1682 1336 1710 1351)(font "Arial" ))
+	(pt 1672 1352)
+	(pt 1840 1352)
+)
+(connector
+	(text "DTR" (rect 1680 1360 1709 1375)(font "Arial" ))
+	(pt 1672 1376)
+	(pt 1848 1376)
+)
+(connector
+	(text "CTS" (rect 1114 1408 1142 1423)(font "Arial" ))
+	(pt 1104 1424)
+	(pt 1264 1424)
+)
+(connector
+	(text "RI" (rect 1114 1432 1128 1447)(font "Arial" ))
+	(pt 1104 1448)
+	(pt 1264 1448)
+)
+(connector
+	(text "DCD" (rect 1114 1456 1145 1471)(font "Arial" ))
+	(pt 1104 1472)
+	(pt 1264 1472)
+)
+(connector
+	(text "IDE_RDY" (rect 1114 1536 1175 1551)(font "Arial" ))
+	(pt 1264 1552)
+	(pt 1104 1552)
+)
+(connector
+	(text "IDE_INT" (rect 1114 1560 1168 1575)(font "Arial" ))
+	(pt 1104 1576)
+	(pt 1264 1576)
+)
+(connector
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+)
+(connector
+	(text "DDRCLK[0]" (rect 2450 744 2525 759)(font "Arial" ))
+	(pt 2440 760)
+	(pt 2504 760)
+)
+(connector
+	(pt 2504 760)
+	(pt 2536 760)
+)
+(connector
+	(text "MAIN_CLK" (rect 1186 88 1255 103)(font "Arial" ))
+	(pt 1184 104)
+	(pt 1264 104)
+)
+(connector
+	(text "nRSTO" (rect 1194 40 1241 55)(font "Arial" ))
+	(pt 1184 56)
+	(pt 1264 56)
+)
+(connector
+	(text "BA[1..0]" (rect 1682 456 1730 471)(font "Arial" ))
+	(pt 1672 472)
+	(pt 1832 472)
+	(bus)
+)
+(connector
+	(text "PIXEL_CLK" (rect 2394 -64 2469 -49)(font "Arial" ))
+	(pt 2384 -48)
+	(pt 2464 -48)
+)
+(connector
+	(text "PIXEL_CLK" (rect 2394 56 2469 71)(font "Arial" ))
+	(pt 2384 72)
+	(pt 2464 72)
+)
+(connector
+	(text "nBLANK" (rect 2394 24 2448 39)(font "Arial" ))
+	(pt 2464 40)
+	(pt 2384 40)
+)
+(connector
+	(text "nBLANK" (rect 2394 40 2448 55)(font "Arial" ))
+	(pt 2464 56)
+	(pt 2384 56)
+)
+(connector
+	(pt 2696 -80)
+	(pt 2712 -80)
+)
+(connector
+	(pt 2696 40)
+	(pt 2712 40)
+)
+(connector
+	(text "PIXEL_CLK" (rect 1826 -48 1901 -33)(font "Arial" ))
+	(pt 1816 -32)
+	(pt 1896 -32)
+)
+(connector
+	(pt 2128 -64)
+	(pt 2136 -64)
+)
+(connector
+	(text "PIXEL_CLK" (rect 1682 232 1757 247)(font "Arial" ))
+	(pt 1744 248)
+	(pt 1672 248)
+)
+(connector
+	(text "PIXEL_CLK" (rect 2394 184 2469 199)(font "Arial" ))
+	(pt 2384 200)
+	(pt 2464 200)
+)
+(connector
+	(pt 2456 168)
+	(pt 2456 136)
+)
+(connector
+	(pt 2464 168)
+	(pt 2456 168)
+)
+(connector
+	(pt 2456 136)
+	(pt 2400 136)
+)
+(connector
+	(pt 2464 184)
+	(pt 2440 184)
+)
+(connector
+	(pt 2712 168)
+	(pt 2696 168)
+)
+(connector
+	(pt 2440 160)
+	(pt 2424 160)
+)
+(connector
+	(pt 2440 184)
+	(pt 2440 160)
+)
+(connector
+	(text "nFB_CS3" (rect 1170 3128 1232 3143)(font "Arial" ))
+	(pt 1264 3144)
+	(pt 1160 3144)
+)
+(connector
+	(text "nBLANK" (rect 1154 1968 1208 1983)(font "Arial" ))
+	(pt 1264 1984)
+	(pt 1144 1984)
+)
+(connector
+	(text "DSP_INT" (rect 1154 1944 1214 1959)(font "Arial" ))
+	(pt 1264 1960)
+	(pt 1144 1960)
+)
+(connector
+	(text "STEP_DIR" (rect 1682 1752 1751 1767)(font "Arial" ))
+	(pt 1672 1768)
+	(pt 1856 1768)
+)
+(connector
+	(pt 1904 1768)
+	(pt 2136 1768)
+)
+(connector
+	(pt 1904 1816)
+	(pt 2136 1816)
+)
+(connector
+	(text "WR_DATA" (rect 1682 1800 1749 1815)(font "Arial" ))
+	(pt 1672 1816)
+	(pt 1856 1816)
+)
+(connector
+	(text "DMA_DRQ" (rect 1130 2856 1199 2871)(font "Arial" ))
+	(pt 1264 2872)
+	(pt 1120 2872)
+)
+(connector
+	(text "DMA_DRQ" (rect 1682 2096 1751 2111)(font "Arial" ))
+	(pt 1784 2112)
+	(pt 1672 2112)
+)
+(connector
+	(text "FDC_CLK" (rect 1202 880 1268 895)(font "Arial" ))
+	(pt 1192 896)
+	(pt 1264 896)
+)
+(connector
+	(text "MOT_ON" (rect 1626 1728 1685 1743)(font "Arial" ))
+	(pt 1672 1744)
+	(pt 1800 1744)
+)
+(connector
+	(pt 1848 1744)
+	(pt 2136 1744)
+)
+(connector
+	(text "STEP" (rect 1626 1776 1662 1791)(font "Arial" ))
+	(pt 1672 1792)
+	(pt 1800 1792)
+)
+(connector
+	(pt 1848 1792)
+	(pt 2136 1792)
+)
+(connector
+	(text "WR_GATE" (rect 1690 1824 1758 1839)(font "Arial" ))
+	(pt 1672 1840)
+	(pt 1800 1840)
+)
+(connector
+	(pt 1848 1840)
+	(pt 2136 1840)
+)
+(connector
+	(text "FB_ALE" (rect 1186 1992 1237 2007)(font "Arial" ))
+	(pt 1144 2008)
+	(pt 1264 2008)
+)
+(connector
+	(text "AMKB_TX" (rect 1946 1392 2008 1407)(font "Arial" ))
+	(pt 1672 1408)
+	(pt 2112 1408)
+)
+(connector
+	(text "PIC_AMKB_RX" (rect 786 1504 882 1519)(font "Arial" ))
+	(pt 776 1520)
+	(pt 1264 1520)
+)
+(connector
+	(pt 400 -16)
+	(pt 440 -16)
+)
+(connector
+	(pt 440 248)
+	(pt 400 248)
+)
+(connector
+	(pt 400 -16)
+	(pt 400 248)
+)
+(connector
+	(pt 400 248)
+	(pt 400 304)
+)
+(connector
+	(text "CLK2M" (rect 754 -32 801 -17)(font "Arial" ))
+	(pt 744 -16)
+	(pt 816 -16)
+)
+(connector
+	(text "FDC_CLK" (rect 754 -8 820 7)(font "Arial" ))
+	(pt 744 8)
+	(pt 816 8)
+)
+(connector
+	(text "FB_AD[31..0]" (rect 370 1352 453 1367)(font "Arial" ))
+	(pt 352 1368)
+	(pt 464 1368)
+	(bus)
+)
+(connector
+	(text "FB_ADR[31..0]" (rect 642 1376 736 1391)(font "Arial" ))
+	(pt 608 1392)
+	(pt 760 1392)
+	(bus)
+)
+(connector
+	(text "DDR_SYNC_66M" (rect 378 1368 492 1383)(font "Arial" ))
+	(pt 368 1384)
+	(pt 464 1384)
+)
+(connector
+	(text "FB_ALE" (rect 386 1384 437 1399)(font "Arial" ))
+	(pt 376 1400)
+	(pt 464 1400)
+)
+(connector
+	(text "ACP_CONF[31..0]" (rect 1682 2568 1797 2583)(font "Arial" ))
+	(pt 1672 2584)
+	(pt 1832 2584)
+	(bus)
+)
+(connector
+	(text "ACP_CONF[31..24]" (rect 1146 2064 1269 2079)(font "Arial" ))
+	(pt 1136 2080)
+	(pt 1264 2080)
+	(bus)
+)
+(connector
+	(text "TIN0" (rect 1682 2624 1712 2639)(font "Arial" ))
+	(pt 1832 2640)
+	(pt 1672 2640)
+)
+(connector
+	(pt 1896 -48)
+	(pt 1856 -48)
+)
+(connector
+	(pt 1856 -48)
+	(pt 1856 -64)
+)
+(connector
+	(pt 1856 -64)
+	(pt 1896 -64)
+)
+(connector
+	(pt 2464 -64)
+	(pt 2424 -64)
+)
+(connector
+	(pt 2424 -80)
+	(pt 2424 -64)
+)
+(connector
+	(text "HD_DD" (rect 1050 1616 1100 1631)(font "Arial" ))
+	(pt 1040 1632)
+	(pt 1264 1632)
+)
+(connector
+	(text "CLK48M" (rect 754 40 809 55)(font "Arial" ))
+	(pt 744 56)
+	(pt 840 56)
+)
+(connector
+	(text "CLK25M" (rect 754 16 809 31)(font "Arial" ))
+	(pt 744 32)
+	(pt 864 32)
+)
+(connector
+	(text "DDRCLK[0]" (rect 762 -296 837 -281)(font "Arial" ))
+	(pt 752 -280)
+	(pt 848 -280)
+)
+(connector
+	(text "DDRCLK[1]" (rect 762 -272 837 -257)(font "Arial" ))
+	(pt 752 -256)
+	(pt 848 -256)
+)
+(connector
+	(text "DDRCLK[2]" (rect 762 -248 837 -233)(font "Arial" ))
+	(pt 752 -232)
+	(pt 848 -232)
+)
+(connector
+	(text "DDRCLK[3]" (rect 762 -224 837 -209)(font "Arial" ))
+	(pt 752 -208)
+	(pt 848 -208)
+)
+(connector
+	(text "DDR_SYNC_66M" (rect 762 -200 876 -185)(font "Arial" ))
+	(pt 752 -184)
+	(pt 848 -184)
+)
+(connector
+	(pt 408 672)
+	(pt 472 672)
+)
+(connector
+	(text "VIDEO_RECONFIG" (rect 74 496 199 511)(font "Arial" ))
+	(pt 192 512)
+	(pt 64 512)
+)
+(connector
+	(text "MAIN_CLK" (rect 330 -296 399 -281)(font "Arial" ))
+	(pt 264 -280)
+	(pt 448 -280)
+)
+(connector
+	(pt 408 640)
+	(pt 472 640)
+)
+(connector
+	(pt 408 624)
+	(pt 512 624)
+)
+(connector
+	(text "VR_D[8..0]" (rect 418 552 486 567)(font "Arial" ))
+	(pt 496 568)
+	(pt 408 568)
+	(bus)
+)
+(connector
+	(text "MAIN_CLK" (rect 122 664 191 679)(font "Arial" ))
+	(pt 112 680)
+	(pt 192 680)
+)
+(connector
+	(pt 536 720)
+	(pt 408 720)
+)
+(connector
+	(pt 1064 808)
+	(pt 1064 616)
+)
+(connector
+	(pt 1072 816)
+	(pt 1072 592)
+)
+(connector
+	(pt 472 672)
+	(pt 472 664)
+)
+(connector
+	(pt 472 640)
+	(pt 472 616)
+)
+(connector
+	(pt 512 624)
+	(pt 512 640)
+)
+(connector
+	(pt 536 720)
+	(pt 536 592)
+)
+(connector
+	(pt 536 592)
+	(pt 608 592)
+)
+(connector
+	(pt 472 616)
+	(pt 608 616)
+)
+(connector
+	(pt 512 640)
+	(pt 608 640)
+)
+(connector
+	(pt 472 664)
+	(pt 608 664)
+)
+(connector
+	(pt 408 688)
+	(pt 608 688)
+)
+(connector
+	(pt 984 592)
+	(pt 1072 592)
+)
+(connector
+	(pt 984 616)
+	(pt 1064 616)
+)
+(connector
+	(text "FB_ADR[5..2]" (rect 82 568 168 583)(font "Arial" ))
+	(pt 192 584)
+	(pt 72 584)
+	(bus)
+)
+(connector
+	(pt 1064 808)
+	(pt 80 808)
+)
+(connector
+	(pt 192 656)
+	(pt 80 656)
+)
+(connector
+	(pt 80 656)
+	(pt 80 808)
+)
+(connector
+	(pt 1072 816)
+	(pt 72 816)
+)
+(connector
+	(pt 192 640)
+	(pt 72 640)
+)
+(connector
+	(pt 72 640)
+	(pt 72 816)
+)
+(connector
+	(text "FB_ADR[8..6]" (rect 82 584 168 599)(font "Arial" ))
+	(pt 192 600)
+	(pt 72 600)
+	(bus)
+)
+(connector
+	(text "VR_RD" (rect 98 512 146 527)(font "Arial" ))
+	(pt 64 528)
+	(pt 192 528)
+)
+(connector
+	(text "VR_WR" (rect 98 528 148 543)(font "Arial" ))
+	(pt 64 544)
+	(pt 192 544)
+)
+(connector
+	(text "VR_D[8..0]" (rect 1170 464 1238 479)(font "Arial" ))
+	(pt 1144 480)
+	(pt 1264 480)
+	(bus)
+)
+(connector
+	(text "VDQS[3..0]" (rect 1674 504 1743 519)(font "Arial" ))
+	(pt 2040 544)
+	(pt 1960 544)
+	(bus)
+)
+(connector
+	(pt 1672 544)
+	(pt 1888 544)
+	(bus)
+)
+(connector
+	(pt 1888 544)
+	(pt 1888 568)
+	(bus)
+)
+(connector
+	(text "VDM[3..0]" (rect 1682 528 1742 543)(font "Arial" ))
+	(pt 1944 568)
+	(pt 1888 568)
+	(bus)
+)
+(connector
+	(pt 1672 520)
+	(pt 1960 520)
+	(bus)
+)
+(connector
+	(pt 1960 544)
+	(pt 1960 520)
+	(bus)
+)
+(connector
+	(text "VIDEO_RECONFIG" (rect 1674 560 1799 575)(font "Arial" ))
+	(pt 1672 576)
+	(pt 1792 576)
+)
+(connector
+	(text "VR_WR" (rect 1698 592 1748 607)(font "Arial" ))
+	(pt 1672 608)
+	(pt 1792 608)
+)
+(connector
+	(text "VR_BUSY" (rect 418 496 482 511)(font "Arial" ))
+	(pt 408 512)
+	(pt 480 512)
+)
+(connector
+	(text "VR_BUSY" (rect 1170 448 1234 463)(font "Arial" ))
+	(pt 1144 464)
+	(pt 1264 464)
+)
+(connector
+	(text "VR_RD" (rect 1698 576 1746 591)(font "Arial" ))
+	(pt 1792 592)
+	(pt 1672 592)
+)
+(connector
+	(text "nRSTO" (rect -86 680 -39 695)(font "Arial" ))
+	(pt -96 696)
+	(pt -16 696)
+)
+(connector
+	(pt 32 696)
+	(pt 192 696)
+)
+(connector
+	(text "FB_AD[24..16]" (rect 82 552 174 567)(font "Arial" ))
+	(pt 72 568)
+	(pt 192 568)
+	(bus)
+)
+(connector
+	(text "CLK48M" (rect 538 552 593 567)(font "Arial" ))
+	(pt 528 568)
+	(pt 608 568)
+)
+(connector
+	(text "CLK_VIDEO" (rect 1162 552 1241 567)(font "Arial" ))
+	(pt 984 568)
+	(pt 1264 568)
+)
+(connector
+	(text "CLK33M" (rect 1202 584 1257 599)(font "Arial" ))
+	(pt 1264 600)
+	(pt 1192 600)
+)
+(connector
+	(text "CLK500k" (rect 802 232 862 247)(font "Arial" ))
+	(pt 768 248)
+	(pt 864 248)
+)
+(connector
+	(text "CLK2M4576" (rect 802 256 882 271)(font "Arial" ))
+	(pt 768 272)
+	(pt 864 272)
+)
+(connector
+	(text "CLK24M576" (rect 802 280 882 295)(font "Arial" ))
+	(pt 768 296)
+	(pt 864 296)
+)
+(connector
+	(text "nRSTO" (rect 1018 424 1065 439)(font "Arial" ))
+	(pt 1008 440)
+	(pt 1096 440)
+)
+(connector
+	(pt 768 320)
+	(pt 872 320)
+)
+(connector
+	(pt 872 432)
+	(pt 944 432)
+)
+(connector
+	(pt 840 448)
+	(pt 944 448)
+)
+(connector
+	(pt 872 320)
+	(pt 872 432)
+)
+(connector
+	(text "HSYNC" (rect 2314 -96 2363 -81)(font "Arial" ))
+	(pt 2304 -80)
+	(pt 2424 -80)
+)
+(connector
+	(pt 2424 -80)
+	(pt 2464 -80)
+)
+(connector
+	(text "VSYNC" (rect 1746 -80 1793 -65)(font "Arial" ))
+	(pt 1736 -64)
+	(pt 1856 -64)
+)
+(junction (pt 2504 760))
+(junction (pt 400 248))
+(junction (pt 1856 -64))
+(junction (pt 2424 -80))
diff --git a/FPGA_quartus_GE/firebee1.done b/FPGA_quartus_GE/firebee1.done
new file mode 100644
index 0000000..87f69a1
--- /dev/null
+++ b/FPGA_quartus_GE/firebee1.done
@@ -0,0 +1 @@
+Mon Mar 03 21:48:22 2014
diff --git a/FPGA_quartus_GE/firebee1.qpf b/FPGA_quartus_GE/firebee1.qpf
new file mode 100644
index 0000000..49e7c57
--- /dev/null
+++ b/FPGA_quartus_GE/firebee1.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 32-bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 01:26:07  March 01, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "01:26:07  March 01, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "firebee1"
diff --git a/FPGA_quartus_GE/firebee1.qsf b/FPGA_quartus_GE/firebee1.qsf
new file mode 100644
index 0000000..c3904e8
--- /dev/null
+++ b/FPGA_quartus_GE/firebee1.qsf
@@ -0,0 +1,852 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+# Date created = 12:45:00  November 06, 2010
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		firebee1_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29  SEPTEMBER 03, 2009"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_AB12 -to CLK33M
+set_location_assignment PIN_G2 -to MAIN_CLK
+set_location_assignment PIN_Y3 -to FB_AD[0]
+set_location_assignment PIN_Y6 -to FB_AD[1]
+set_location_assignment PIN_AA3 -to FB_AD[2]
+set_location_assignment PIN_AB3 -to FB_AD[3]
+set_location_assignment PIN_W6 -to FB_AD[4]
+set_location_assignment PIN_V7 -to FB_AD[5]
+set_location_assignment PIN_AA4 -to FB_AD[6]
+set_location_assignment PIN_AB4 -to FB_AD[7]
+set_location_assignment PIN_AA5 -to FB_AD[8]
+set_location_assignment PIN_AB5 -to FB_AD[9]
+set_location_assignment PIN_W7 -to FB_AD[10]
+set_location_assignment PIN_Y7 -to FB_AD[11]
+set_location_assignment PIN_U9 -to FB_AD[12]
+set_location_assignment PIN_V8 -to FB_AD[13]
+set_location_assignment PIN_W8 -to FB_AD[14]
+set_location_assignment PIN_AA7 -to FB_AD[15]
+set_location_assignment PIN_AB7 -to FB_AD[16]
+set_location_assignment PIN_Y8 -to FB_AD[17]
+set_location_assignment PIN_V9 -to FB_AD[18]
+set_location_assignment PIN_V10 -to FB_AD[19]
+set_location_assignment PIN_T10 -to FB_AD[20]
+set_location_assignment PIN_U10 -to FB_AD[21]
+set_location_assignment PIN_AA8 -to FB_AD[22]
+set_location_assignment PIN_AB8 -to FB_AD[23]
+set_location_assignment PIN_T11 -to FB_AD[24]
+set_location_assignment PIN_AA9 -to FB_AD[25]
+set_location_assignment PIN_AB9 -to FB_AD[26]
+set_location_assignment PIN_U11 -to FB_AD[27]
+set_location_assignment PIN_V11 -to FB_AD[28]
+set_location_assignment PIN_W10 -to FB_AD[29]
+set_location_assignment PIN_Y10 -to FB_AD[30]
+set_location_assignment PIN_AA10 -to FB_AD[31]
+set_location_assignment PIN_R7 -to FB_ALE
+set_location_assignment PIN_N19 -to LED_FPGA_OK
+set_location_assignment PIN_AB10 -to CLK24M576
+set_location_assignment PIN_J1 -to CLKUSB
+set_location_assignment PIN_T4 -to CLK25M
+set_location_assignment PIN_U8 -to FB_SIZE0
+set_location_assignment PIN_Y4 -to FB_SIZE1
+set_location_assignment PIN_T3 -to nFB_BURST
+set_location_assignment PIN_T8 -to nFB_CS1
+set_location_assignment PIN_T9 -to nFB_CS2
+set_location_assignment PIN_V6 -to nFB_CS3
+set_location_assignment PIN_R6 -to nFB_OE
+set_location_assignment PIN_T5 -to nFB_WR
+set_location_assignment PIN_R5 -to TIN0
+set_location_assignment PIN_T21 -to nMASTER
+set_location_assignment PIN_E11 -to nDREQ1
+set_location_assignment PIN_A12 -to nDACK1
+set_location_assignment PIN_B12 -to nDACK0
+set_location_assignment PIN_T22 -to TOUT0
+set_location_assignment PIN_AB17 -to DDR_CLK
+set_location_assignment PIN_AA17 -to nDDR_CLK
+set_location_assignment PIN_AB18 -to nVCAS
+set_location_assignment PIN_T18 -to nVCS
+set_location_assignment PIN_W17 -to nVRAS
+set_location_assignment PIN_Y17 -to nVWE
+set_location_assignment PIN_W20 -to VA[0]
+set_location_assignment PIN_W22 -to VA[1]
+set_location_assignment PIN_W21 -to VA[2]
+set_location_assignment PIN_Y22 -to VA[3]
+set_location_assignment PIN_AA22 -to VA[4]
+set_location_assignment PIN_Y21 -to VA[5]
+set_location_assignment PIN_AA21 -to VA[6]
+set_location_assignment PIN_AA20 -to VA[7]
+set_location_assignment PIN_AB20 -to VA[8]
+set_location_assignment PIN_AB19 -to VA[9]
+set_location_assignment PIN_V21 -to VA[10]
+set_location_assignment PIN_U19 -to VA[11]
+set_location_assignment PIN_AA18 -to VA[12]
+set_location_assignment PIN_U15 -to VCKE
+set_location_assignment PIN_M22 -to VD[0]
+set_location_assignment PIN_M21 -to VD[1]
+set_location_assignment PIN_P22 -to VD[2]
+set_location_assignment PIN_R20 -to VD[3]
+set_location_assignment PIN_P21 -to VD[4]
+set_location_assignment PIN_R17 -to VD[5]
+set_location_assignment PIN_R19 -to VD[6]
+set_location_assignment PIN_U21 -to VD[7]
+set_location_assignment PIN_V22 -to VD[8]
+set_location_assignment PIN_R18 -to VD[9]
+set_location_assignment PIN_P17 -to VD[10]
+set_location_assignment PIN_R21 -to VD[11]
+set_location_assignment PIN_N17 -to VD[12]
+set_location_assignment PIN_P20 -to VD[13]
+set_location_assignment PIN_R22 -to VD[14]
+set_location_assignment PIN_N20 -to VD[15]
+set_location_assignment PIN_T12 -to VD[16]
+set_location_assignment PIN_Y13 -to VD[17]
+set_location_assignment PIN_AA13 -to VD[18]
+set_location_assignment PIN_V14 -to VD[19]
+set_location_assignment PIN_U13 -to VD[20]
+set_location_assignment PIN_V15 -to VD[21]
+set_location_assignment PIN_W14 -to VD[22]
+set_location_assignment PIN_AB16 -to VD[23]
+set_location_assignment PIN_AB15 -to VD[24]
+set_location_assignment PIN_AA14 -to VD[25]
+set_location_assignment PIN_AB14 -to VD[26]
+set_location_assignment PIN_V13 -to VD[27]
+set_location_assignment PIN_W13 -to VD[28]
+set_location_assignment PIN_AB13 -to VD[29]
+set_location_assignment PIN_V12 -to VD[30]
+set_location_assignment PIN_U12 -to VD[31]
+set_location_assignment PIN_AA16 -to VDM[0]
+set_location_assignment PIN_V16 -to VDM[1]
+set_location_assignment PIN_U20 -to VDM[2]
+set_location_assignment PIN_T17 -to VDM[3]
+set_location_assignment PIN_AA15 -to VDQS[0]
+set_location_assignment PIN_W15 -to VDQS[1]
+set_location_assignment PIN_U22 -to VDQS[2]
+set_location_assignment PIN_T16 -to VDQS[3]
+set_location_assignment PIN_V1 -to nPD_VGA
+set_location_assignment PIN_G18 -to VB[0]
+set_location_assignment PIN_H17 -to VB[1]
+set_location_assignment PIN_C22 -to VB[2]
+set_location_assignment PIN_C21 -to VB[3]
+set_location_assignment PIN_B22 -to VB[4]
+set_location_assignment PIN_B21 -to VB[5]
+set_location_assignment PIN_C20 -to VB[6]
+set_location_assignment PIN_D20 -to VB[7]
+set_location_assignment PIN_H19 -to VG[0]
+set_location_assignment PIN_E22 -to VG[1]
+set_location_assignment PIN_E21 -to VG[2]
+set_location_assignment PIN_H18 -to VG[3]
+set_location_assignment PIN_J17 -to VG[4]
+set_location_assignment PIN_H16 -to VG[5]
+set_location_assignment PIN_D22 -to VG[6]
+set_location_assignment PIN_D21 -to VG[7]
+set_location_assignment PIN_J22 -to VR[0]
+set_location_assignment PIN_J21 -to VR[1]
+set_location_assignment PIN_H22 -to VR[2]
+set_location_assignment PIN_H21 -to VR[3]
+set_location_assignment PIN_K17 -to VR[4]
+set_location_assignment PIN_K18 -to VR[5]
+set_location_assignment PIN_J18 -to VR[6]
+set_location_assignment PIN_F22 -to VR[7]
+set_location_assignment PIN_M6 -to ACSI_A1
+set_location_assignment PIN_B1 -to ACSI_D[0]
+set_location_assignment PIN_G5 -to ACSI_D[1]
+set_location_assignment PIN_E3 -to ACSI_D[2]
+set_location_assignment PIN_C2 -to ACSI_D[3]
+set_location_assignment PIN_C1 -to ACSI_D[4]
+set_location_assignment PIN_D2 -to ACSI_D[5]
+set_location_assignment PIN_H7 -to ACSI_D[6]
+set_location_assignment PIN_H6 -to ACSI_D[7]
+set_location_assignment PIN_L6 -to ACSI_DIR
+set_location_assignment PIN_N1 -to AMKB_TX
+set_location_assignment PIN_F15 -to DSA_D
+set_location_assignment PIN_D15 -to DTR
+set_location_assignment PIN_A11 -to DVI_INT
+set_location_assignment PIN_G21 -to E0_INT
+set_location_assignment PIN_M5 -to IDE_RES
+set_location_assignment PIN_A8 -to IO[0]
+set_location_assignment PIN_A7 -to IO[1]
+set_location_assignment PIN_B7 -to IO[2]
+set_location_assignment PIN_A6 -to IO[3]
+set_location_assignment PIN_B6 -to IO[4]
+set_location_assignment PIN_E9 -to IO[5]
+set_location_assignment PIN_C8 -to IO[6]
+set_location_assignment PIN_C7 -to IO[7]
+set_location_assignment PIN_G10 -to IO[8]
+set_location_assignment PIN_A15 -to IO[9]
+set_location_assignment PIN_B15 -to IO[10]
+set_location_assignment PIN_C13 -to IO[11]
+set_location_assignment PIN_D13 -to IO[12]
+set_location_assignment PIN_E13 -to IO[13]
+set_location_assignment PIN_A14 -to IO[14]
+set_location_assignment PIN_B14 -to IO[15]
+set_location_assignment PIN_A13 -to IO[16]
+set_location_assignment PIN_B13 -to IO[17]
+set_location_assignment PIN_F7 -to LP_D[0]
+set_location_assignment PIN_C4 -to LP_D[1]
+set_location_assignment PIN_C3 -to LP_D[2]
+set_location_assignment PIN_E7 -to LP_D[3]
+set_location_assignment PIN_D6 -to LP_D[4]
+set_location_assignment PIN_B3 -to LP_D[5]
+set_location_assignment PIN_A3 -to LP_D[6]
+set_location_assignment PIN_G8 -to LP_D[7]
+set_location_assignment PIN_E6 -to LP_STR
+set_location_assignment PIN_H5 -to MIDI_OLR
+set_location_assignment PIN_B2 -to MIDI_TLR
+set_location_assignment PIN_M4 -to nACSI_ACK
+set_location_assignment PIN_M2 -to nACSI_CS
+set_location_assignment PIN_M1 -to nACSI_RESET
+set_location_assignment PIN_W2 -to nCF_CS0
+set_location_assignment PIN_W1 -to nCF_CS1
+set_location_assignment PIN_T7 -to nFB_TA
+set_location_assignment PIN_R2 -to nIDE_CS0
+set_location_assignment PIN_R1 -to nIDE_CS1
+set_location_assignment PIN_P1 -to nIDE_RD
+set_location_assignment PIN_P2 -to nIDE_WR
+set_location_assignment PIN_F21 -to nIRQ[2]
+set_location_assignment PIN_H20 -to nIRQ[3]
+set_location_assignment PIN_F20 -to nIRQ[4]
+set_location_assignment PIN_P5 -to nIRQ[5]
+set_location_assignment PIN_P7 -to nIRQ[6]
+set_location_assignment PIN_N7 -to nIRQ[7]
+set_location_assignment PIN_AA1 -to nPCI_INTA
+set_location_assignment PIN_V4 -to nPCI_INTB
+set_location_assignment PIN_V3 -to nPCI_INTC
+set_location_assignment PIN_P6 -to nPCI_INTD
+set_location_assignment PIN_P3 -to nROM3
+set_location_assignment PIN_U2 -to nROM4
+set_location_assignment PIN_N5 -to nRP_LDS
+set_location_assignment PIN_P4 -to nRP_UDS
+set_location_assignment PIN_N2 -to nSCSI_ACK
+set_location_assignment PIN_M3 -to nSCSI_ATN
+set_location_assignment PIN_N8 -to nSCSI_BUSY
+set_location_assignment PIN_N6 -to nSCSI_RST
+set_location_assignment PIN_M8 -to nSCSI_SEL
+set_location_assignment PIN_B20 -to nSDSEL
+set_location_assignment PIN_B4 -to nSRBHE
+set_location_assignment PIN_A4 -to nSRBLE
+set_location_assignment PIN_B8 -to nSRCS
+set_location_assignment PIN_F11 -to nSROE
+set_location_assignment PIN_F8 -to nSRWE
+set_location_assignment PIN_G14 -to nWR
+set_location_assignment PIN_D17 -to nWR_GATE
+set_location_assignment PIN_AA2 -to PIC_INT
+set_location_assignment PIN_B18 -to RTS
+set_location_assignment PIN_J6 -to SCSI_D[0]
+set_location_assignment PIN_E1 -to SCSI_D[1]
+set_location_assignment PIN_F2 -to SCSI_D[2]
+set_location_assignment PIN_F1 -to SCSI_D[3]
+set_location_assignment PIN_G4 -to SCSI_D[4]
+set_location_assignment PIN_G3 -to SCSI_D[5]
+set_location_assignment PIN_L8 -to SCSI_D[6]
+set_location_assignment PIN_K8 -to SCSI_D[7]
+set_location_assignment PIN_J7 -to SCSI_DIR
+set_location_assignment PIN_M7 -to SCSI_PAR
+set_location_assignment PIN_F13 -to SD_CD_DATA3
+set_location_assignment PIN_C15 -to SD_CLK
+set_location_assignment PIN_E14 -to SD_CMD_D1
+set_location_assignment PIN_B5 -to SRD[0]
+set_location_assignment PIN_A5 -to SRD[1]
+set_location_assignment PIN_C6 -to SRD[2]
+set_location_assignment PIN_G11 -to SRD[3]
+set_location_assignment PIN_C10 -to SRD[4]
+set_location_assignment PIN_F9 -to SRD[5]
+set_location_assignment PIN_E10 -to SRD[6]
+set_location_assignment PIN_H11 -to SRD[7]
+set_location_assignment PIN_B9 -to SRD[8]
+set_location_assignment PIN_A10 -to SRD[9]
+set_location_assignment PIN_A9 -to SRD[10]
+set_location_assignment PIN_B10 -to SRD[11]
+set_location_assignment PIN_D10 -to SRD[12]
+set_location_assignment PIN_F10 -to SRD[13]
+set_location_assignment PIN_G9 -to SRD[14]
+set_location_assignment PIN_H10 -to SRD[15]
+set_location_assignment PIN_A18 -to TxD
+set_location_assignment PIN_A17 -to YM_QA
+set_location_assignment PIN_G13 -to YM_QB
+set_location_assignment PIN_E15 -to YM_QC
+set_location_assignment PIN_T1 -to WP_CF_CARD
+set_location_assignment PIN_C19 -to TRACK00
+set_location_assignment PIN_M19 -to SD_WP
+set_location_assignment PIN_B17 -to SD_DATA2
+set_location_assignment PIN_A16 -to SD_DATA1
+set_location_assignment PIN_B16 -to SD_DATA0
+set_location_assignment PIN_M20 -to SD_CARD_DEDECT
+set_location_assignment PIN_H15 -to RxD
+set_location_assignment PIN_B19 -to RI
+set_location_assignment PIN_L7 -to PIC_AMKB_RX
+set_location_assignment PIN_D19 -to nWP
+set_location_assignment PIN_H2 -to nSCSI_MSG
+set_location_assignment PIN_J3 -to nSCSI_I_O
+set_location_assignment PIN_U1 -to nSCSI_DRQ
+set_location_assignment PIN_H1 -to nSCSI_C_D
+set_location_assignment PIN_A20 -to nRD_DATA
+set_location_assignment PIN_C17 -to nDCHG
+set_location_assignment PIN_J4 -to nACSI_INT
+set_location_assignment PIN_K7 -to nACSI_DRQ
+set_location_assignment PIN_E12 -to MIDI_IN
+set_location_assignment PIN_G7 -to LP_BUSY
+set_location_assignment PIN_Y1 -to IDE_RDY
+set_location_assignment PIN_G22 -to IDE_INT
+set_location_assignment PIN_F16 -to HD_DD
+set_location_assignment PIN_A19 -to DCD
+set_location_assignment PIN_H14 -to CTS
+set_location_assignment PIN_Y2 -to AMKB_RX
+set_location_assignment PIN_E16 -to nINDEX
+set_location_assignment PIN_W19 -to BA[0]
+set_location_assignment PIN_AA19 -to BA[1]
+set_location_assignment PIN_K21 -to HSYNC_PAD
+set_location_assignment PIN_K19 -to VSYNC_PAD
+set_location_assignment PIN_G17 -to nBLANK_PAD
+set_location_assignment PIN_F19 -to PIXEL_CLK_PAD
+set_location_assignment PIN_F17 -to nSYNC
+set_location_assignment PIN_G15 -to nSTEP_DIR
+set_location_assignment PIN_F14 -to nSTEP
+set_location_assignment PIN_G16 -to nMOT_ON
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name TPD_REQUIREMENT "1 ns"
+set_global_assignment -name TSU_REQUIREMENT "1 ns"
+set_global_assignment -name TCO_REQUIREMENT "1 ns"
+set_global_assignment -name TH_REQUIREMENT "1 ns"
+set_global_assignment -name FMAX_REQUIREMENT "30 ns"
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY firebee1
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name SAFE_STATE_MACHINE OFF
+set_global_assignment -name STATE_MACHINE_PROCESSING "ONE-HOT"
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C40F484C6
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
+set_instance_assignment -name IO_STANDARD "2.5 V" -to DDR_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VA
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VD
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VDM
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VDQS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVWE
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVRAS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nVCAS
+set_instance_assignment -name IO_STANDARD "2.5 V" -to nDDR_CLK
+set_instance_assignment -name IO_STANDARD "2.5 V" -to VCKE
+set_instance_assignment -name IO_STANDARD "2.5 V" -to LED_FPGA_OK
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "0 ns"
+set_instance_assignment -name IO_STANDARD "2.5 V" -to BA
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to HSYNC_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to PIXEL_CLK_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VB
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VG
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VR
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to VSYNC_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVTTL" -to nBLANK_PAD
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nSYNC
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[2]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[3]
+set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to nIRQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AMKB_TX
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name GENERATE_TTF_FILE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name GENERATE_HEX_FILE OFF
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0XE0700000
+
+# Simulator Assignments
+# =====================
+set_global_assignment -name END_TIME "2 us"
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
+set_global_assignment -name SETUP_HOLD_DETECTION OFF
+set_global_assignment -name GLITCH_DETECTION OFF
+set_global_assignment -name CHECK_OUTPUTS OFF
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE firebee1.vwf
+
+# start EDA_TOOL_SETTINGS(eda_blast_fpga)
+# ---------------------------------------
+
+	# Analysis & Synthesis Assignments
+	# ================================
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+
+# end EDA_TOOL_SETTINGS(eda_blast_fpga)
+# -------------------------------------
+
+# start CLOCK(fast)
+# -----------------
+
+	# Classic Timing Assignments
+	# ==========================
+set_global_assignment -name FMAX_REQUIREMENT "133 MHz" -section_id fast
+
+# end CLOCK(fast)
+# ---------------
+
+# start ASSIGNMENT_GROUP(fast)
+# ----------------------------
+
+	# Assignment Group Assignments
+	# ============================
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[0] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[1] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[2] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER DDRCLK[3] -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:b2v_Fredi_Aschwanden|DDRCLK" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:b2v_Fredi_Aschwanden|DDRCLK[0]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:b2v_Fredi_Aschwanden|DDRCLK[1]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:b2v_Fredi_Aschwanden|DDRCLK[2]" -section_id fast
+set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:b2v_Fredi_Aschwanden|DDRCLK[3]" -section_id fast
+#set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK" -section_id fast
+#set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]" -section_id fast
+#set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]" -section_id fast
+#set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]" -section_id fast
+#set_global_assignment -name ASSIGNMENT_GROUP_MEMBER "video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]" -section_id fast
+
+# end ASSIGNMENT_GROUP(fast)
+# --------------------------
+
+# ----------------------
+# start ENTITY(firebee1)
+
+	# Classic Timing Assignments
+	# ==========================
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[0]
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[1]
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[2]
+set_instance_assignment -name CLOCK_SETTINGS fast -to DDRCLK[3]
+set_instance_assignment -name CLOCK_SETTINGS fast -to "video:b2v_Fredi_Aschwanden|DDRCLK"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "video:b2v_Fredi_Aschwanden|DDRCLK[0]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "video:b2v_Fredi_Aschwanden|DDRCLK[1]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "video:b2v_Fredi_Aschwanden|DDRCLK[2]"
+set_instance_assignment -name CLOCK_SETTINGS fast -to "video:b2v_Fredi_Aschwanden|DDRCLK[3]"
+#set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK"
+#set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[0]"
+#set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[1]"
+#set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[2]"
+#set_instance_assignment -name CLOCK_SETTINGS fast -to "Video:Fredi_Aschwanden|DDR_CTR_BLITTER:DDR_CTR_BLITTER|DDRCLK[3]"
+set_instance_assignment -name INPUT_MAX_DELAY "4 ns" -from * -to FB_ALE
+set_instance_assignment -name MAX_DELAY "5 ns" -from VD -to FB_AD
+set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to VA
+set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to nVRAS
+set_instance_assignment -name MAX_DELAY "5 ns" -from FB_AD -to BA
+
+	# Fitter Assignments
+	# ==================
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED_FPGA_OK
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VCKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nVCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to FB_AD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to BA
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to DDR_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VA
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nVWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nVRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to nVCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to nDDR_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to HSYNC_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to PIXEL_CLK_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VB
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VG
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VR
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to nBLANK_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 16MA -to VSYNC_PAD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nPD_VGA
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSYNC
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SRD
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to IO
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSROE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBLE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to nSRBHE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK24M576
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLKUSB
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to CLK25M
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to AMKB_TX
+
+	# Simulator Assignments
+	# =====================
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to FB_AD
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_DRQ
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to nACSI_INT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CARD_DEDECT
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_WP
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA2
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA1
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_DATA0
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CMD_D1
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CLK
+set_instance_assignment -name PASSIVE_RESISTOR "PULL-UP" -to SD_CD_DATA3
+
+	# start LOGICLOCK_REGION(Root Region)
+	# -----------------------------------
+
+		# LogicLock Region Assignments
+		# ============================
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+
+	# end LOGICLOCK_REGION(Root Region)
+	# ---------------------------------
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(firebee1)
+# --------------------
+set_location_assignment PIN_E5 -to LPDIR
+set_location_assignment PIN_B11 -to nRSTO_MCF
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to DDR_CLK
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VCKE
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to nDDR_CLK
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to nVCAS
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to nVCS
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to nVRAS
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to nVWE
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VA[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[0]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VA[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[1]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VA[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[2]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VA[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[3]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VA[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[4]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VA[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[5]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VA[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[6]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VA[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[7]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VA[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[8]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VA[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[9]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VA[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[10]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VA[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[11]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VA[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VA[12]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to BA[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to BA[0]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to BA[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to BA[1]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VDM[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM[0]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VDM[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM[1]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VDM[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM[2]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VDM[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDM[3]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[0]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[1]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[2]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[3]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[4]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[5]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[6]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[7]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[8]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[9]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[10]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[11]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[12]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[13]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[13]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[14]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[14]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[15]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[15]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[16]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[16]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[17]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[17]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[18]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[18]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[19]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[19]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[20]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[20]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[21]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[21]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[22]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[22]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[23]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[23]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[24]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[24]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[25]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[25]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[26]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[26]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[27]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[27]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[28]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[28]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[29]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[29]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[30]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[30]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VD[31]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VD[31]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VDQS[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS[0]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VDQS[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS[1]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VDQS[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS[2]
+#set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to VDQS[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to VDQS[3]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VDM[0]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VDM[1]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VDM[2]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VDM[3]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[0]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[1]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[2]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[3]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[4]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[5]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[6]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[7]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[8]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[9]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[10]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[11]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[12]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[13]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[14]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[15]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[16]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[17]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[18]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[19]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[20]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[21]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[22]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[23]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[24]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[25]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[26]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[27]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[28]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[29]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[30]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VD[31]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VDQS[0]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VDQS[1]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VDQS[2]
+set_instance_assignment -name OUTPUT_ENABLE_GROUP 1077756020 -to VDQS[3]
+set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to DDR_CLK
+set_instance_assignment -name CKN_CK_PAIR ON -from nDDR_CLK -to DDR_CLK
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_global_assignment -name VERILOG_FILE Video/DDR_CTR.v
+set_global_assignment -name VERILOG_FILE Video/VIDEO_MOD_MUX_CLUTCTR.v
+set_global_assignment -name VERILOG_FILE Interrupt_Handler/interrupt_handler.v
+set_global_assignment -name VERILOG_FILE mux41.v
+set_global_assignment -name VERILOG_FILE Video/video.v
+set_global_assignment -name VERILOG_FILE firebee1.v
+set_global_assignment -name SDC_FILE firebee1.sdc
+set_global_assignment -name VHDL_FILE DSP/DSP.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
+set_global_assignment -name VHDL_FILE Video/BLITTER/BLITTER.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_control.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_registers.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_soc_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF5380/wf5380_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_am_detector.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/dcfifo0.vhd
+set_global_assignment -name VHDL_FILE Video/lpm_bustri0.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_control.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_crc_logic.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_digital_pll.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_registers.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_FDC1772_IP/wf1772ip_transceiver.vhd
+set_global_assignment -name VHDL_FILE Video/lpm_bustri5.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd
+set_global_assignment -name VHDL_FILE Video/lpm_bustri7.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_gpio.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_timers.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_ctrl.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_rx.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_usart_tx.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_pkg.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_top_soc.vhd
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/WF_SND2149_IP/wf2149ip_wave.vhd
+set_global_assignment -name VHDL_FILE lpm_latch0.vhd
+set_global_assignment -name QIP_FILE altpll1.qip
+set_global_assignment -name VHDL_FILE Video/lpm_fifoDZ.vhd
+set_global_assignment -name QIP_FILE altpll2.qip
+set_global_assignment -name QIP_FILE altpll3.qip
+set_global_assignment -name VHDL_FILE Video/altdpram0.vhd
+set_global_assignment -name VHDL_FILE Video/lpm_muxDZ2.vhd
+set_global_assignment -name VHDL_FILE Video/lpm_muxDZ.vhd
+set_global_assignment -name VHDL_FILE Video/lpm_bustri3.vhd
+set_global_assignment -name VHDL_FILE altpll2.vhd
+set_global_assignment -name VHDL_FILE altpll3.vhd
+set_global_assignment -name VHDL_FILE Video/lpm_ff0.vhd
+set_global_assignment -name VHDL_FILE Video/lpm_ff1.vhd
+set_global_assignment -name VHDL_FILE Video/lpm_ff3.vhd
+set_global_assignment -name VHDL_FILE Video/lpm_ff2.vhd
+set_global_assignment -name VHDL_FILE Video/lpm_fifo_dc0.vhd
+set_global_assignment -name VHDL_FILE altpll1.vhd
+set_global_assignment -name QIP_FILE altpll0.qip
+set_global_assignment -name QIP_FILE lpm_counter0.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip
+set_global_assignment -name QIP_FILE Video/altdpram0.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip
+set_global_assignment -name QIP_FILE Video/altdpram1.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri2.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri4.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant0.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant1.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux0.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux1.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux2.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant2.qip
+set_global_assignment -name QIP_FILE Video/altdpram2.qip
+set_global_assignment -name QIP_FILE Video/lpm_bustri6.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux3.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux4.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant3.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg1.qip
+set_global_assignment -name QIP_FILE Video/lpm_latch1.qip
+set_global_assignment -name QIP_FILE Video/lpm_constant4.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip
+set_global_assignment -name QIP_FILE Video/lpm_compare1.qip
+set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
+set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
+set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
+set_global_assignment -name QIP_FILE Video/lpm_ff4.qip
+set_global_assignment -name QIP_FILE Video/lpm_ff5.qip
+set_global_assignment -name QIP_FILE Video/lpm_ff6.qip
+set_global_assignment -name VECTOR_WAVEFORM_FILE firebee1.vwf
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg3.qip
+set_global_assignment -name QIP_FILE Video/altddio_bidir0.qip
+set_global_assignment -name QIP_FILE Video/altddio_out0.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux5.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg5.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg6.qip
+set_global_assignment -name QIP_FILE Video/lpm_shiftreg4.qip
+set_global_assignment -name QIP_FILE Video/altddio_out1.qip
+set_global_assignment -name QIP_FILE Video/altddio_out2.qip
+set_global_assignment -name QIP_FILE altddio_out3.qip
+set_global_assignment -name QIP_FILE Video/lpm_mux6.qip
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF_pgk.vhd
+set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip
+set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip
+set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip
+set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip
+set_global_assignment -name QIP_FILE altpll_reconfig1.qip
+set_global_assignment -name QIP_FILE altpll4.qip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/FPGA_quartus_GE/firebee1.qws b/FPGA_quartus_GE/firebee1.qws
new file mode 100644
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diff --git a/FPGA_quartus_GE/firebee1.rbf b/FPGA_quartus_GE/firebee1.rbf
new file mode 100644
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diff --git a/FPGA_quartus_GE/firebee1.sdc b/FPGA_quartus_GE/firebee1.sdc
new file mode 100644
index 0000000..21df1d3
--- /dev/null
+++ b/FPGA_quartus_GE/firebee1.sdc
@@ -0,0 +1,179 @@
+###########################################################################
+#
+# Generated by : Version 9.1 Build 222 10/21/2009 SJ Full Version
+#
+# Project      : firebee1
+# Revision     : firebee1
+#
+# Date         : Sat Mar 01 15:22:38 CET 2014
+#
+###########################################################################
+ 
+ 
+# WARNING: Ignored QSF Variable: Global TSU_REQUIREMENT = 1 ns
+# WARNING: Ignored QSF Variable: Global TH_REQUIREMENT = 1 ns
+# WARNING: Ignored QSF Variable: Global TPD_REQUIREMENT = 1 ns
+# WARNING: Ignored QSF Variable: Global TCO_REQUIREMENT = 1 ns
+# WARNING: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'
+#          In SDC, create_generated_clock auto-generates clock latency
+#
+# ------------------------------------------
+#
+# Create generated clocks based on PLLs
+derive_pll_clocks -use_tan_name
+#
+# ------------------------------------------
+# WARNING: Global Fmax translated to derive_clocks. Behavior is not identical
+if {![info exist ::qsta_message_posted]} {
+    post_message -type warning "Original Global Fmax translated from QSF using derive_clocks"
+    set ::qsta_message_posted 1
+}
+derive_clocks -period "30.303 ns"
+#
+
+
+# Original Clock Setting Name: CLK33M
+create_clock -period "30.303 ns" \
+             -name {CLK33M} {CLK33M}
+# ---------------------------------------------
+
+# ** Clock Latency
+#    -------------
+
+# ** Clock Uncertainty
+#    -----------------
+
+derive_clock_uncertainty
+
+# ** Multicycles
+#    -----------
+
+# ** Cuts
+#    ----
+
+# ** Input/Output Delays
+#    -------------------
+# QSF: -name INPUT_MAX_DELAY 4 ns -from * -to FB_ALE
+# Command requires a unique clock. Expand clock
+#foreach_in_collection clk [get_clocks * ] {
+#    set_input_delay -add_delay -max 4 -clock [get_object_info -name $clk] [get_ports {FB_ALE}]
+#}
+#set_input_delay -add_delay -max 4 -clock {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]} [get_ports {FB_ALE}]
+
+# ** Tpd requirements
+#    ----------------
+
+# ** Setup/Hold Relationships
+#    ------------------------
+
+# ** Tsu/Th requirements
+#    -------------------
+
+
+# ** Tco/MinTco requirements
+#    -----------------------
+
+#
+# Entity Specific Timing Assignments found in
+# the Timing Analyzer Settings report panel
+#
+set_false_path -from [get_registers {*dcfifo*delayed_wrptr_g[*]}] -to [get_registers {*dcfifo*rs_dgwp*}]
+set_false_path -from [get_registers {*dcfifo*rdptr_g[*]}] -to [get_registers {*dcfifo*ws_dgrp*}]
+
+set_clock_groups -asynchronous -group { \
+altpll4:b2v_inst22|altpll:altpll_component|altpll_r4n2:auto_generated|clk[0] \
+} \
+-group { \
+altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[3] \
+} \
+-group { \
+altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[2] \
+} \
+-group { \
+altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[1] \
+} \
+-group { \
+altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[0] \
+} \
+-group { \
+altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4] \
+altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[3] \
+altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[2] \
+altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[1] \
+altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0] \
+CLK33M \
+} \
+-group { \
+altpll1:b2v_inst|altpll:altpll_component|altpll_8tp2:auto_generated|clk[2] \
+altpll1:b2v_inst|altpll:altpll_component|altpll_8tp2:auto_generated|clk[1] \
+} \
+-group { \
+altpll1:b2v_inst|altpll:altpll_component|altpll_8tp2:auto_generated|clk[0] \
+} \
+
+
+#set_multicycle_path -from [get_clocks {altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[2]}] -to [get_clocks {altpll4:b2v_inst22|altpll:altpll_component|altpll_r4n2:auto_generated|clk[0]}] -setup -end 2
+#set_multicycle_path -from [get_clocks {altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[2]}] -to [get_clocks {altpll4:b2v_inst22|altpll:altpll_component|altpll_r4n2:auto_generated|clk[0]}] -hold -end 1
+
+#set_multicycle_path -from [get_clocks {altpll4:b2v_inst22|altpll:altpll_component|altpll_r4n2:auto_generated|clk[0]}] -to [get_clocks {altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[2]}] -setup -end 2
+#set_multicycle_path -from [get_clocks {altpll4:b2v_inst22|altpll:altpll_component|altpll_r4n2:auto_generated|clk[0]}] -to [get_clocks {altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[2]}] -hold -end 1
+
+
+
+#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[2]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -setup -end 2
+#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[2]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -hold -end 1
+
+#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[3]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -setup -end 2
+#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[3]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -hold -end 1
+
+#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[1]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -setup -end 2
+#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[1]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -hold -end 1
+
+set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -setup -end 2
+set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -hold -end 1
+
+#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[2]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -setup -end 2
+#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[2]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -hold -end 1
+
+#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[3]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -setup -end 2
+#set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[3]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -hold -end 1
+
+
+set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -to [get_clocks {CLK33M}] -setup -end 2
+set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -to [get_clocks {CLK33M}] -hold -end 1
+
+set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -to [get_clocks {CLK33M}] -setup -end 2
+set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -to [get_clocks {CLK33M}] -hold -end 1
+
+set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[3]}] -to [get_clocks {CLK33M}] -setup -end 2
+set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[3]}] -to [get_clocks {CLK33M}] -hold -end 1
+
+set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -setup -end 2
+set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]}] -hold -end 1
+
+set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[1]}] -setup -end 2
+set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[1]}] -hold -end 1
+
+#set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -setup -end 2
+#set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0]}] -hold -end 1
+
+#set_false_path -from [get_clocks {CLK33M}] -to   [get_clocks {altpll4:b2v_inst22|altpll:altpll_component|altpll_r4n2:auto_generated|clk[0]}]
+#set_false_path -to   [get_clocks {CLK33M}] -from [get_clocks {altpll4:b2v_inst22|altpll:altpll_component|altpll_r4n2:auto_generated|clk[0]}]
+
+# ---------------------------------------------
+
+# WARNING: Ignored QSF Variable: -name MAX_DELAY 5 ns -from VD -to FB_AD
+# WARNING: Ignored QSF Variable: -name MAX_DELAY 5 ns -from FB_AD -to VA
+# WARNING: Ignored QSF Variable: -name MAX_DELAY 5 ns -from FB_AD -to nVRAS
+# WARNING: Ignored QSF Variable: -name MAX_DELAY 5 ns -from FB_AD -to BA
+#set_max_delay -from [get_ports {VD[*]}] -to [get_ports {FB_AD[*]}] 5.000
+#set_max_delay -from [get_ports {FB_AD[*]}] -to [get_ports {VA[*]}] 5.000
+#set_max_delay -from [get_ports {FB_AD[*]}] -to [get_ports {nVRAS}] 5.000
+#set_max_delay -from [get_ports {FB_AD[*]}] -to [get_ports {BA[*]}] 5.000
+
+# Constrain the input I/O path
+set_input_delay -clock CLK33M -max 5 [all_inputs]
+#set_input_delay -clock CLK33M -min 4 [all_inputs]
+
+# Constrain the output I/O path
+set_output_delay -clock CLK33M -max 5 [all_outputs]
diff --git a/FPGA_quartus_GE/firebee1.v b/FPGA_quartus_GE/firebee1.v
new file mode 100644
index 0000000..eed07a6
--- /dev/null
+++ b/FPGA_quartus_GE/firebee1.v
@@ -0,0 +1,698 @@
+// Copyright (C) 1991-2009 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// PROGRAM		"Quartus II 64-Bit"
+// VERSION		"Version 9.1 Build 222 10/21/2009 SJ Full Version"
+// CREATED		"Sat Mar 01 09:20:47 2014"
+
+module firebee1(
+	FB_ALE,
+	nFB_WR,
+	CLK33M,
+	nFB_CS1,
+	nFB_CS2,
+	nFB_CS3,
+	FB_SIZE0,
+	FB_SIZE1,
+	nFB_BURST,
+	LP_BUSY,
+	nACSI_DRQ,
+	nACSI_INT,
+	RxD,
+	CTS,
+	RI,
+	DCD,
+	AMKB_RX,
+	PIC_AMKB_RX,
+	IDE_RDY,
+	IDE_INT,
+	WP_CF_CARD,
+	TRACK00,
+	nWP,
+	nDCHG,
+	SD_DATA0,
+	SD_DATA1,
+	SD_DATA2,
+	SD_CARD_DEDECT,
+	MIDI_IN,
+	nSCSI_DRQ,
+	SD_WP,
+	nRD_DATA,
+	nSCSI_C_D,
+	nSCSI_I_O,
+	nSCSI_MSG,
+	nDACK0,
+	PIC_INT,
+	nFB_OE,
+	TOUT0,
+	nMASTER,
+	DVI_INT,
+	nDACK1,
+	nPCI_INTD,
+	nPCI_INTC,
+	nPCI_INTB,
+	nPCI_INTA,
+	E0_INT,
+	nINDEX,
+	HD_DD,
+	MAIN_CLK,
+	nRSTO_MCF,
+	CLK24M576,
+	LP_STR,
+	nACSI_ACK,
+	nACSI_RESET,
+	nACSI_CS,
+	ACSI_DIR,
+	ACSI_A1,
+	nSCSI_ACK,
+	nSCSI_ATN,
+	SCSI_DIR,
+	MIDI_OLR,
+	MIDI_TLR,
+	TxD,
+	RTS,
+	DTR,
+	AMKB_TX,
+	IDE_RES,
+	nIDE_CS0,
+	nIDE_CS1,
+	nIDE_WR,
+	nIDE_RD,
+	nCF_CS0,
+	nCF_CS1,
+	nROM3,
+	nROM4,
+	nRP_UDS,
+	nRP_LDS,
+	nSDSEL,
+	nWR_GATE,
+	nWR,
+	YM_QA,
+	YM_QB,
+	YM_QC,
+	SD_CLK,
+	DSA_D,
+	nVWE,
+	nVCAS,
+	nVRAS,
+	nVCS,
+	nPD_VGA,
+	CLK25M,
+	TIN0,
+	nSRCS,
+	nSRBLE,
+	nSRBHE,
+	nSRWE,
+	nDREQ1,
+	LED_FPGA_OK,
+	nSROE,
+	VCKE,
+	nFB_TA,
+	nDDR_CLK,
+	DDR_CLK,
+	VSYNC_PAD,
+	HSYNC_PAD,
+	nBLANK_PAD,
+	PIXEL_CLK_PAD,
+	nSYNC,
+	nMOT_ON,
+	nSTEP_DIR,
+	nSTEP,
+	CLKUSB,
+	LPDIR,
+	SCSI_PAR,
+	nSCSI_RST,
+	nSCSI_SEL,
+	nSCSI_BUSY,
+	SD_CD_DATA3,
+	SD_CMD_D1,
+	ACSI_D,
+	BA,
+	FB_AD,
+	IO,
+	LP_D,
+	nIRQ,
+	SCSI_D,
+	SRD,
+	VA,
+	VB,
+	VD,
+	VDM,
+	VDQS,
+	VG,
+	VR
+);
+
+
+input	FB_ALE;
+input	nFB_WR;
+input	CLK33M;
+input	nFB_CS1;
+input	nFB_CS2;
+input	nFB_CS3;
+input	FB_SIZE0;
+input	FB_SIZE1;
+input	nFB_BURST;
+input	LP_BUSY;
+input	nACSI_DRQ;
+input	nACSI_INT;
+input	RxD;
+input	CTS;
+input	RI;
+input	DCD;
+input	AMKB_RX;
+input	PIC_AMKB_RX;
+input	IDE_RDY;
+input	IDE_INT;
+input	WP_CF_CARD;
+input	TRACK00;
+input	nWP;
+input	nDCHG;
+input	SD_DATA0;
+input	SD_DATA1;
+input	SD_DATA2;
+input	SD_CARD_DEDECT;
+input	MIDI_IN;
+input	nSCSI_DRQ;
+input	SD_WP;
+input	nRD_DATA;
+input	nSCSI_C_D;
+input	nSCSI_I_O;
+input	nSCSI_MSG;
+input	nDACK0;
+input	PIC_INT;
+input	nFB_OE;
+input	TOUT0;
+input	nMASTER;
+input	DVI_INT;
+input	nDACK1;
+input	nPCI_INTD;
+input	nPCI_INTC;
+input	nPCI_INTB;
+input	nPCI_INTA;
+input	E0_INT;
+input	nINDEX;
+input	HD_DD;
+input	MAIN_CLK;
+input	nRSTO_MCF;
+output	CLK24M576;
+output	LP_STR;
+output	nACSI_ACK;
+output	nACSI_RESET;
+output	nACSI_CS;
+output	ACSI_DIR;
+output	ACSI_A1;
+output	nSCSI_ACK;
+output	nSCSI_ATN;
+output	SCSI_DIR;
+output	MIDI_OLR;
+output	MIDI_TLR;
+output	TxD;
+output	RTS;
+output	DTR;
+output	AMKB_TX;
+output	IDE_RES;
+output	nIDE_CS0;
+output	nIDE_CS1;
+output	nIDE_WR;
+output	nIDE_RD;
+output	nCF_CS0;
+output	nCF_CS1;
+output	nROM3;
+output	nROM4;
+output	nRP_UDS;
+output	nRP_LDS;
+output	nSDSEL;
+output	nWR_GATE;
+output	nWR;
+output	YM_QA;
+output	YM_QB;
+output	YM_QC;
+output	SD_CLK;
+output	DSA_D;
+output	nVWE;
+output	nVCAS;
+output	nVRAS;
+output	nVCS;
+output	nPD_VGA;
+output	CLK25M;
+output	TIN0;
+output	nSRCS;
+output	nSRBLE;
+output	nSRBHE;
+output	nSRWE;
+output	nDREQ1;
+output	LED_FPGA_OK;
+output	nSROE;
+output	VCKE;
+output	nFB_TA;
+output	nDDR_CLK;
+output	DDR_CLK;
+output	VSYNC_PAD;
+output	HSYNC_PAD;
+output	nBLANK_PAD;
+output	PIXEL_CLK_PAD;
+output	nSYNC;
+output	nMOT_ON;
+output	nSTEP_DIR;
+output	nSTEP;
+output	CLKUSB;
+output	LPDIR;
+inout	SCSI_PAR;
+inout	nSCSI_RST;
+inout	nSCSI_SEL;
+inout	nSCSI_BUSY;
+inout	SD_CD_DATA3;
+inout	SD_CMD_D1;
+inout	[7:0] ACSI_D;
+output	[1:0] BA;
+inout	[31:0] FB_AD;
+inout	[17:0] IO;
+inout	[7:0] LP_D;
+output	[7:2] nIRQ;
+inout	[7:0] SCSI_D;
+inout	[15:0] SRD;
+output	[12:0] VA;
+output	[7:0] VB;
+inout	[31:0] VD;
+output	[3:0] VDM;
+inout	[3:0] VDQS;
+output	[7:0] VG;
+output	[7:0] VR;
+
+wire	[31:0] ACP_CONF;
+wire	CLK25M_ALTERA_SYNTHESIZED;
+wire	CLK2M;
+wire	CLK2M4576;
+wire	CLK48M;
+wire	CLK500k;
+wire	CLK_VIDEO;
+wire	DDR_SYNC_66M;
+wire	[3:0] DDRCLK;
+wire	DMA_DRQ;
+wire	DSP_INT;
+wire	DSP_TA;
+wire	FALCON_IO_TA;
+wire	[31:0] FB_ADR;
+wire	FDC_CLK;
+wire	HSYNC;
+wire	INT_HANDLER_TA;
+wire	LP_DIR;
+wire	MOT_ON;
+wire	nBLANK;
+wire	nDREQ0;
+wire	nMFP_INT;
+wire	nRSTO;
+wire	PIXEL_CLK;
+wire	SD_CDM_D1;
+wire	STEP;
+wire	STEP_DIR;
+wire	[17:0] TIMEBASE;
+wire	VIDEO_RECONFIG;
+wire	Video_TA;
+wire	VR_BUSY;
+wire	[8:0] VR_D;
+wire	VR_RD;
+wire	VR_WR;
+wire	VSYNC;
+wire	WR_DATA;
+wire	WR_GATE;
+wire	SYNTHESIZED_WIRE_0;
+wire	SYNTHESIZED_WIRE_1;
+wire	SYNTHESIZED_WIRE_2;
+wire	SYNTHESIZED_WIRE_3;
+wire	SYNTHESIZED_WIRE_4;
+wire	SYNTHESIZED_WIRE_5;
+wire	SYNTHESIZED_WIRE_6;
+wire	SYNTHESIZED_WIRE_7;
+wire	SYNTHESIZED_WIRE_8;
+wire	SYNTHESIZED_WIRE_9;
+wire	SYNTHESIZED_WIRE_10;
+
+assign	nDREQ1 = nDACK1;
+assign	SYNTHESIZED_WIRE_9 = 0;
+assign	SYNTHESIZED_WIRE_10 = 1;
+
+wire w_MAIN_CLK;
+assign w_MAIN_CLK = CLK33M;
+
+video	b2v_Fredi_Aschwanden(
+	.MAIN_CLK(w_MAIN_CLK),
+	.nFB_CS1(nFB_CS1),
+	.nFB_CS2(nFB_CS2),
+	.nFB_CS3(nFB_CS3),
+	.nFB_WR(nFB_WR),
+	.FB_SIZE0(FB_SIZE0),
+	.FB_SIZE1(FB_SIZE1),
+	.nRSTO(nRSTO),
+	.nFB_OE(nFB_OE),
+	.FB_ALE(FB_ALE),
+	.DDR_SYNC_66M(DDR_SYNC_66M),
+	.CLK33M(CLK33M),
+	.CLK25M(CLK25M_ALTERA_SYNTHESIZED),
+	.CLK_VIDEO(CLK_VIDEO),
+	.VR_BUSY(VR_BUSY),
+	.DDRCLK(DDRCLK),
+	.FB_AD(FB_AD),
+	.FB_ADR(FB_ADR),
+	.VD(VD),
+	.VDQS(VDQS),
+	.VR_D(VR_D),
+	.VR_RD(VR_RD),
+	.nBLANK(nBLANK),
+	.nVWE(nVWE),
+	.nVCAS(nVCAS),
+	.nVRAS(nVRAS),
+	.nVCS(nVCS),
+	.nPD_VGA(nPD_VGA),
+	.VCKE(VCKE),
+	.VSYNC(VSYNC),
+	.HSYNC(HSYNC),
+	.nSYNC(nSYNC),
+	.VIDEO_TA(Video_TA),
+	.PIXEL_CLK(PIXEL_CLK),
+	.VIDEO_RECONFIG(VIDEO_RECONFIG),
+	.VR_WR(VR_WR),
+	.BA(BA),
+	
+	.VA(VA),
+	.VB(VB),
+	
+	.VDM(VDM),
+	
+	.VG(VG),
+	.VR(VR));
+
+
+altpll1	b2v_inst(
+	.inclk0(CLK33M),
+	.c0(CLK500k),
+	.c1(CLK2M4576),
+	.c2(CLK24M576),
+	.locked(SYNTHESIZED_WIRE_5));
+
+
+lpm_ff0	b2v_inst1(
+	.clock(DDR_SYNC_66M),
+	.enable(FB_ALE),
+	.data(FB_AD),
+	.q(FB_ADR));
+
+
+
+
+altpll2	b2v_inst12(
+	.inclk0(w_MAIN_CLK),
+	.c0(DDRCLK[0]),
+	.c1(DDRCLK[1]),
+	.c2(DDRCLK[2]),
+	.c3(DDRCLK[3]),
+	.c4(DDR_SYNC_66M));
+
+
+altpll3	b2v_inst13(
+	.inclk0(CLK33M),
+	.c0(CLK2M),
+	.c1(FDC_CLK),
+	.c2(CLK25M_ALTERA_SYNTHESIZED),
+	.c3(CLK48M));
+
+assign	nMOT_ON =  ~MOT_ON;
+
+assign	nSTEP_DIR =  ~STEP_DIR;
+
+assign	nSTEP =  ~STEP;
+
+assign	nWR =  ~WR_DATA;
+
+
+lpm_counter0	b2v_inst18(
+	.clock(CLK500k),
+	.q(TIMEBASE));
+
+assign	nWR_GATE =  ~WR_GATE;
+
+assign	nFB_TA = ~(Video_TA | INT_HANDLER_TA | DSP_TA | FALCON_IO_TA);
+
+
+altpll4	b2v_inst22(
+	.inclk0(CLK48M),
+	.areset(SYNTHESIZED_WIRE_0),
+	.scanclk(SYNTHESIZED_WIRE_1),
+	.scandata(SYNTHESIZED_WIRE_2),
+	.scanclkena(SYNTHESIZED_WIRE_3),
+	.configupdate(SYNTHESIZED_WIRE_4),
+	.c0(CLK_VIDEO),
+	.scandataout(SYNTHESIZED_WIRE_6),
+	.scandone(SYNTHESIZED_WIRE_7)
+	);
+
+assign	SYNTHESIZED_WIRE_8 =  ~nRSTO;
+
+assign	nRSTO = SYNTHESIZED_WIRE_5 & nRSTO_MCF;
+
+assign	LED_FPGA_OK = TIMEBASE[17];
+
+
+assign	nDDR_CLK =  ~DDRCLK[0];
+
+
+altddio_out3	b2v_inst5(
+	.datain_h(VSYNC),
+	.datain_l(VSYNC),
+	.outclock(PIXEL_CLK),
+	.dataout(VSYNC_PAD));
+
+
+altddio_out3	b2v_inst6(
+	.datain_h(HSYNC),
+	.datain_l(HSYNC),
+	.outclock(PIXEL_CLK),
+	.dataout(HSYNC_PAD));
+
+
+altpll_reconfig1	b2v_inst7(
+	.reconfig(VIDEO_RECONFIG),
+	.read_param(VR_RD),
+	.write_param(VR_WR),
+	.pll_scandataout(SYNTHESIZED_WIRE_6),
+	.pll_scandone(SYNTHESIZED_WIRE_7),
+	.clock(w_MAIN_CLK),
+	.reset(SYNTHESIZED_WIRE_8),
+	
+	.counter_param(FB_ADR[8:6]),
+	.counter_type(FB_ADR[5:2]),
+	.data_in(FB_AD[24:16]),
+	.busy(VR_BUSY),
+	.pll_scandata(SYNTHESIZED_WIRE_2),
+	.pll_scanclk(SYNTHESIZED_WIRE_1),
+	.pll_scanclkena(SYNTHESIZED_WIRE_3),
+	.pll_configupdate(SYNTHESIZED_WIRE_4),
+	.pll_areset(SYNTHESIZED_WIRE_0),
+	.data_out(VR_D));
+
+
+altddio_out3	b2v_inst8(
+	.datain_h(nBLANK),
+	.datain_l(nBLANK),
+	.outclock(PIXEL_CLK),
+	.dataout(nBLANK_PAD));
+
+
+altddio_out3	b2v_inst9(
+	.datain_h(SYNTHESIZED_WIRE_9),
+	.datain_l(SYNTHESIZED_WIRE_10),
+	.outclock(PIXEL_CLK),
+	.dataout(PIXEL_CLK_PAD));
+
+
+DSP	b2v_Mathias_Alles(
+	.CLK33M(CLK33M),
+	.MAIN_CLK(w_MAIN_CLK),
+	.nFB_OE(nFB_OE),
+	.nFB_WR(nFB_WR),
+	.nFB_CS1(nFB_CS1),
+	.nFB_CS2(nFB_CS2),
+	.FB_SIZE0(FB_SIZE0),
+	.FB_SIZE1(FB_SIZE1),
+	.nFB_BURST(nFB_BURST),
+	.nRSTO(nRSTO),
+	.nFB_CS3(nFB_CS3),
+	.FB_AD(FB_AD),
+	.FB_ADR(FB_ADR),
+	.IO(IO),
+	.SRD(SRD),
+	.nSRCS(nSRCS),
+	.nSRBLE(nSRBLE),
+	.nSRBHE(nSRBHE),
+	.nSRWE(nSRWE),
+	.nSROE(nSROE),
+	.DSP_INT(DSP_INT),
+	.DSP_TA(DSP_TA)
+	
+	
+	);
+
+
+interrupt_handler	b2v_nobody(
+	.MAIN_CLK(w_MAIN_CLK),
+	.nFB_WR(nFB_WR),
+	.nFB_CS1(nFB_CS1),
+	.nFB_CS2(nFB_CS2),
+	.FB_SIZE0(FB_SIZE0),
+	.FB_SIZE1(FB_SIZE1),
+	.PIC_INT(PIC_INT),
+	.E0_INT(E0_INT),
+	.DVI_INT(DVI_INT),
+	.nPCI_INTA(nPCI_INTA),
+	.nPCI_INTB(nPCI_INTB),
+	.nPCI_INTC(nPCI_INTC),
+	.nPCI_INTD(nPCI_INTD),
+	.nMFP_INT(nMFP_INT),
+	.nFB_OE(nFB_OE),
+	.DSP_INT(DSP_INT),
+	.VSYNC(VSYNC),
+	.HSYNC(HSYNC),
+	.DMA_DRQ(DMA_DRQ),
+	.FB_AD(FB_AD),
+	.FB_ADR(FB_ADR),
+	.INT_HANDLER_TA(INT_HANDLER_TA),
+	.TIN0(TIN0),
+	.ACP_CONF(ACP_CONF),
+	.nRST(nRSTO), //GE
+	.nIRQ(nIRQ));
+
+
+FalconIO_SDCard_IDE_CF	b2v_Wolfgang_Foerster_and_Fredi_Aschwanden(
+	.CLK33M(CLK33M),
+	.MAIN_CLK(w_MAIN_CLK),
+	.CLK2M(CLK2M),
+	.CLK500k(CLK500k),
+	.nFB_CS1(nFB_CS1),
+	.FB_SIZE0(FB_SIZE0),
+	.FB_SIZE1(FB_SIZE1),
+	.nFB_BURST(nFB_BURST),
+	.LP_BUSY(LP_BUSY),
+	.nACSI_DRQ(nACSI_DRQ),
+	.nACSI_INT(nACSI_INT),
+	.nSCSI_DRQ(nSCSI_DRQ),
+	.nSCSI_MSG(nSCSI_MSG),
+	.MIDI_IN(MIDI_IN),
+	.RxD(RxD),
+	.CTS(CTS),
+	.RI(RI),
+	.DCD(DCD),
+	.AMKB_RX(AMKB_RX),
+	.PIC_AMKB_RX(PIC_AMKB_RX),
+	.IDE_RDY(IDE_RDY),
+	.IDE_INT(IDE_INT),
+	
+	.nINDEX(nINDEX),
+	.TRACK00(TRACK00),
+	.nRD_DATA(nRD_DATA),
+	.nDCHG(nDCHG),
+	.SD_DATA0(SD_DATA0),
+	.SD_DATA1(SD_DATA1),
+	.SD_DATA2(SD_DATA2),
+	.SD_CARD_DEDECT(SD_CARD_DEDECT),
+	.SD_WP(SD_WP),
+	.nDACK0(nDACK0),
+	.nFB_WR(nFB_WR),
+	.WP_CF_CARD(WP_CF_CARD),
+	.nWP(nWP),
+	.nFB_CS2(nFB_CS2),
+	.nRSTO(nRSTO),
+	.nSCSI_C_D(nSCSI_C_D),
+	.nSCSI_I_O(nSCSI_I_O),
+	.CLK2M4576(CLK2M4576),
+	.nFB_OE(nFB_OE),
+	.VSYNC(VSYNC),
+	.HSYNC(HSYNC),
+	.DSP_INT(DSP_INT),
+	.nBLANK(nBLANK),
+	.FDC_CLK(FDC_CLK),
+	.FB_ALE(FB_ALE),
+	.HD_DD(HD_DD),
+	.SCSI_PAR(SCSI_PAR),
+	.nSCSI_SEL(nSCSI_SEL),
+	.nSCSI_BUSY(nSCSI_BUSY),
+	.nSCSI_RST(nSCSI_RST),
+	.SD_CD_DATA3(SD_CD_DATA3),
+	.SD_CDM_D1(SD_CDM_D1),
+	.ACP_CONF(ACP_CONF[31:24]),
+	.ACSI_D(ACSI_D),
+	.FB_AD(FB_AD),
+	.FB_ADR(FB_ADR),
+	.LP_D(LP_D),
+	.SCSI_D(SCSI_D),
+	.nIDE_CS1(nIDE_CS1),
+	.nIDE_CS0(nIDE_CS0),
+	.LP_STR(LP_STR),
+	.LP_DIR(LP_DIR),
+	.nACSI_ACK(nACSI_ACK),
+	.nACSI_RESET(nACSI_RESET),
+	.nACSI_CS(nACSI_CS),
+	.ACSI_DIR(ACSI_DIR),
+	.ACSI_A1(ACSI_A1),
+	.nSCSI_ACK(nSCSI_ACK),
+	.nSCSI_ATN(nSCSI_ATN),
+	.SCSI_DIR(SCSI_DIR),
+	.SD_CLK(SD_CLK),
+	.YM_QA(YM_QA),
+	.YM_QC(YM_QC),
+	.YM_QB(YM_QB),
+	.nSDSEL(nSDSEL),
+	.STEP(STEP),
+	.MOT_ON(MOT_ON),
+	.nRP_LDS(nRP_LDS),
+	.nRP_UDS(nRP_UDS),
+	.nROM4(nROM4),
+	.nROM3(nROM3),
+	.nCF_CS1(nCF_CS1),
+	.nCF_CS0(nCF_CS0),
+	.nIDE_RD(nIDE_RD),
+	.nIDE_WR(nIDE_WR),
+	.AMKB_TX(AMKB_TX),
+	.IDE_RES(IDE_RES),
+	.DTR(DTR),
+	.RTS(RTS),
+	.TxD(TxD),
+	.MIDI_OLR(MIDI_OLR),
+	.MIDI_TLR(MIDI_TLR),
+	
+	.DSA_D(DSA_D),
+	.nMFP_INT(nMFP_INT),
+	.FALCON_IO_TA(FALCON_IO_TA),
+	.STEP_DIR(STEP_DIR),
+	.WR_DATA(WR_DATA),
+	.WR_GATE(WR_GATE),
+	.DMA_DRQ(DMA_DRQ)
+	
+	
+	
+	
+	
+	
+	
+	
+	
+	);
+
+assign	SD_CMD_D1 = SD_CDM_D1;
+assign	CLK25M = CLK25M_ALTERA_SYNTHESIZED;
+assign	DDR_CLK = DDRCLK[0];
+assign	CLKUSB = CLK48M;
+assign	LPDIR = LP_DIR;
+
+endmodule
diff --git a/FPGA_quartus_GE/firebee1.vhd b/FPGA_quartus_GE/firebee1.vhd
new file mode 100644
index 0000000..25431e1
--- /dev/null
+++ b/FPGA_quartus_GE/firebee1.vhd
@@ -0,0 +1,861 @@
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 9.1 Build 222 10/21/2009 SJ Full Version"
+-- CREATED		"Sat Mar 01 09:20:24 2014"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY work;
+
+ENTITY firebee1 IS 
+	PORT
+	(
+		FB_ALE :  IN  STD_LOGIC;
+		nFB_WR :  IN  STD_LOGIC;
+		CLK33M :  IN  STD_LOGIC;
+		nFB_CS1 :  IN  STD_LOGIC;
+		nFB_CS2 :  IN  STD_LOGIC;
+		nFB_CS3 :  IN  STD_LOGIC;
+		FB_SIZE0 :  IN  STD_LOGIC;
+		FB_SIZE1 :  IN  STD_LOGIC;
+		nFB_BURST :  IN  STD_LOGIC;
+		LP_BUSY :  IN  STD_LOGIC;
+		nACSI_DRQ :  IN  STD_LOGIC;
+		nACSI_INT :  IN  STD_LOGIC;
+		RxD :  IN  STD_LOGIC;
+		CTS :  IN  STD_LOGIC;
+		RI :  IN  STD_LOGIC;
+		DCD :  IN  STD_LOGIC;
+		AMKB_RX :  IN  STD_LOGIC;
+		PIC_AMKB_RX :  IN  STD_LOGIC;
+		IDE_RDY :  IN  STD_LOGIC;
+		IDE_INT :  IN  STD_LOGIC;
+		WP_CF_CARD :  IN  STD_LOGIC;
+		TRACK00 :  IN  STD_LOGIC;
+		nWP :  IN  STD_LOGIC;
+		nDCHG :  IN  STD_LOGIC;
+		SD_DATA0 :  IN  STD_LOGIC;
+		SD_DATA1 :  IN  STD_LOGIC;
+		SD_DATA2 :  IN  STD_LOGIC;
+		SD_CARD_DEDECT :  IN  STD_LOGIC;
+		MIDI_IN :  IN  STD_LOGIC;
+		nSCSI_DRQ :  IN  STD_LOGIC;
+		SD_WP :  IN  STD_LOGIC;
+		nRD_DATA :  IN  STD_LOGIC;
+		nSCSI_C_D :  IN  STD_LOGIC;
+		nSCSI_I_O :  IN  STD_LOGIC;
+		nSCSI_MSG :  IN  STD_LOGIC;
+		nDACK0 :  IN  STD_LOGIC;
+		PIC_INT :  IN  STD_LOGIC;
+		nFB_OE :  IN  STD_LOGIC;
+		TOUT0 :  IN  STD_LOGIC;
+		nMASTER :  IN  STD_LOGIC;
+		DVI_INT :  IN  STD_LOGIC;
+		nDACK1 :  IN  STD_LOGIC;
+		nPCI_INTD :  IN  STD_LOGIC;
+		nPCI_INTC :  IN  STD_LOGIC;
+		nPCI_INTB :  IN  STD_LOGIC;
+		nPCI_INTA :  IN  STD_LOGIC;
+		E0_INT :  IN  STD_LOGIC;
+		nINDEX :  IN  STD_LOGIC;
+		HD_DD :  IN  STD_LOGIC;
+		MAIN_CLK :  IN  STD_LOGIC;
+		nRSTO_MCF :  IN  STD_LOGIC;
+		SCSI_PAR :  INOUT  STD_LOGIC;
+		nSCSI_RST :  INOUT  STD_LOGIC;
+		nSCSI_SEL :  INOUT  STD_LOGIC;
+		nSCSI_BUSY :  INOUT  STD_LOGIC;
+		SD_CD_DATA3 :  INOUT  STD_LOGIC;
+		SD_CMD_D1 :  INOUT  STD_LOGIC;
+		ACSI_D :  INOUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		FB_AD :  INOUT  STD_LOGIC_VECTOR(31 DOWNTO 0);
+		IO :  INOUT  STD_LOGIC_VECTOR(17 DOWNTO 0);
+		LP_D :  INOUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		SCSI_D :  INOUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		SRD :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		VD :  INOUT  STD_LOGIC_VECTOR(31 DOWNTO 0);
+		VDQS :  INOUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		CLK24M576 :  OUT  STD_LOGIC;
+		LP_STR :  OUT  STD_LOGIC;
+		nACSI_ACK :  OUT  STD_LOGIC;
+		nACSI_RESET :  OUT  STD_LOGIC;
+		nACSI_CS :  OUT  STD_LOGIC;
+		ACSI_DIR :  OUT  STD_LOGIC;
+		ACSI_A1 :  OUT  STD_LOGIC;
+		nSCSI_ACK :  OUT  STD_LOGIC;
+		nSCSI_ATN :  OUT  STD_LOGIC;
+		SCSI_DIR :  OUT  STD_LOGIC;
+		MIDI_OLR :  OUT  STD_LOGIC;
+		MIDI_TLR :  OUT  STD_LOGIC;
+		TxD :  OUT  STD_LOGIC;
+		RTS :  OUT  STD_LOGIC;
+		DTR :  OUT  STD_LOGIC;
+		AMKB_TX :  OUT  STD_LOGIC;
+		IDE_RES :  OUT  STD_LOGIC;
+		nIDE_CS0 :  OUT  STD_LOGIC;
+		nIDE_CS1 :  OUT  STD_LOGIC;
+		nIDE_WR :  OUT  STD_LOGIC;
+		nIDE_RD :  OUT  STD_LOGIC;
+		nCF_CS0 :  OUT  STD_LOGIC;
+		nCF_CS1 :  OUT  STD_LOGIC;
+		nROM3 :  OUT  STD_LOGIC;
+		nROM4 :  OUT  STD_LOGIC;
+		nRP_UDS :  OUT  STD_LOGIC;
+		nRP_LDS :  OUT  STD_LOGIC;
+		nSDSEL :  OUT  STD_LOGIC;
+		nWR_GATE :  OUT  STD_LOGIC;
+		nWR :  OUT  STD_LOGIC;
+		YM_QA :  OUT  STD_LOGIC;
+		YM_QB :  OUT  STD_LOGIC;
+		YM_QC :  OUT  STD_LOGIC;
+		SD_CLK :  OUT  STD_LOGIC;
+		DSA_D :  OUT  STD_LOGIC;
+		nVWE :  OUT  STD_LOGIC;
+		nVCAS :  OUT  STD_LOGIC;
+		nVRAS :  OUT  STD_LOGIC;
+		nVCS :  OUT  STD_LOGIC;
+		nPD_VGA :  OUT  STD_LOGIC;
+		CLK25M :  OUT  STD_LOGIC;
+		TIN0 :  OUT  STD_LOGIC;
+		nSRCS :  OUT  STD_LOGIC;
+		nSRBLE :  OUT  STD_LOGIC;
+		nSRBHE :  OUT  STD_LOGIC;
+		nSRWE :  OUT  STD_LOGIC;
+		nDREQ1 :  OUT  STD_LOGIC;
+		LED_FPGA_OK :  OUT  STD_LOGIC;
+		nSROE :  OUT  STD_LOGIC;
+		VCKE :  OUT  STD_LOGIC;
+		nFB_TA :  OUT  STD_LOGIC;
+		nDDR_CLK :  OUT  STD_LOGIC;
+		DDR_CLK :  OUT  STD_LOGIC;
+		VSYNC_PAD :  OUT  STD_LOGIC;
+		HSYNC_PAD :  OUT  STD_LOGIC;
+		nBLANK_PAD :  OUT  STD_LOGIC;
+		PIXEL_CLK_PAD :  OUT  STD_LOGIC;
+		nSYNC :  OUT  STD_LOGIC;
+		nMOT_ON :  OUT  STD_LOGIC;
+		nSTEP_DIR :  OUT  STD_LOGIC;
+		nSTEP :  OUT  STD_LOGIC;
+		CLKUSB :  OUT  STD_LOGIC;
+		LPDIR :  OUT  STD_LOGIC;
+		BA :  OUT  STD_LOGIC_VECTOR(1 DOWNTO 0);
+		nIRQ :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 2);
+		VA :  OUT  STD_LOGIC_VECTOR(12 DOWNTO 0);
+		VB :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		VDM :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VG :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		VR :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END firebee1;
+
+ARCHITECTURE bdf_type OF firebee1 IS 
+
+COMPONENT video
+	PORT(MAIN_CLK : IN STD_LOGIC;
+		 nFB_CS1 : IN STD_LOGIC;
+		 nFB_CS2 : IN STD_LOGIC;
+		 nFB_CS3 : IN STD_LOGIC;
+		 nFB_WR : IN STD_LOGIC;
+		 FB_SIZE0 : IN STD_LOGIC;
+		 FB_SIZE1 : IN STD_LOGIC;
+		 nRSTO : IN STD_LOGIC;
+		 nFB_OE : IN STD_LOGIC;
+		 FB_ALE : IN STD_LOGIC;
+		 DDR_SYNC_66M : IN STD_LOGIC;
+		 CLK33M : IN STD_LOGIC;
+		 CLK25M : IN STD_LOGIC;
+		 CLK_VIDEO : IN STD_LOGIC;
+		 VR_BUSY : IN STD_LOGIC;
+		 DDRCLK : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 VD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 VDQS : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 VR_D : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+		 VR_RD : OUT STD_LOGIC;
+		 nBLANK : OUT STD_LOGIC;
+		 nVWE : OUT STD_LOGIC;
+		 nVCAS : OUT STD_LOGIC;
+		 nVRAS : OUT STD_LOGIC;
+		 nVCS : OUT STD_LOGIC;
+		 nPD_VGA : OUT STD_LOGIC;
+		 VCKE : OUT STD_LOGIC;
+		 VSYNC : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 nSYNC : OUT STD_LOGIC;
+		 VIDEO_TA : OUT STD_LOGIC;
+		 PIXEL_CLK : OUT STD_LOGIC;
+		 VIDEO_RECONFIG : OUT STD_LOGIC;
+		 VR_WR : OUT STD_LOGIC;
+		 BA : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 VA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
+		 VB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VDM : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 VG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VR : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT altpll1
+	PORT(inclk0 : IN STD_LOGIC;
+		 c0 : OUT STD_LOGIC;
+		 c1 : OUT STD_LOGIC;
+		 c2 : OUT STD_LOGIC;
+		 locked : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT lpm_ff0
+	PORT(clock : IN STD_LOGIC;
+		 enable : IN STD_LOGIC;
+		 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT altpll2
+	PORT(inclk0 : IN STD_LOGIC;
+		 c0 : OUT STD_LOGIC;
+		 c1 : OUT STD_LOGIC;
+		 c2 : OUT STD_LOGIC;
+		 c3 : OUT STD_LOGIC;
+		 c4 : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT altpll3
+	PORT(inclk0 : IN STD_LOGIC;
+		 c0 : OUT STD_LOGIC;
+		 c1 : OUT STD_LOGIC;
+		 c2 : OUT STD_LOGIC;
+		 c3 : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT lpm_counter0
+	PORT(clock : IN STD_LOGIC;
+		 q : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT altpll4
+	PORT(inclk0 : IN STD_LOGIC;
+		 areset : IN STD_LOGIC;
+		 scanclk : IN STD_LOGIC;
+		 scandata : IN STD_LOGIC;
+		 scanclkena : IN STD_LOGIC;
+		 configupdate : IN STD_LOGIC;
+		 c0 : OUT STD_LOGIC;
+		 scandataout : OUT STD_LOGIC;
+		 scandone : OUT STD_LOGIC;
+		 locked : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT altddio_out3
+	PORT(datain_h : IN STD_LOGIC;
+		 datain_l : IN STD_LOGIC;
+		 outclock : IN STD_LOGIC;
+		 dataout : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT altpll_reconfig1
+	PORT(reconfig : IN STD_LOGIC;
+		 read_param : IN STD_LOGIC;
+		 write_param : IN STD_LOGIC;
+		 pll_scandataout : IN STD_LOGIC;
+		 pll_scandone : IN STD_LOGIC;
+		 clock : IN STD_LOGIC;
+		 reset : IN STD_LOGIC;
+		 pll_areset_in : IN STD_LOGIC;
+		 counter_param : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 counter_type : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 data_in : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+		 busy : OUT STD_LOGIC;
+		 pll_scandata : OUT STD_LOGIC;
+		 pll_scanclk : OUT STD_LOGIC;
+		 pll_scanclkena : OUT STD_LOGIC;
+		 pll_configupdate : OUT STD_LOGIC;
+		 pll_areset : OUT STD_LOGIC;
+		 data_out : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT dsp
+	PORT(CLK33M : IN STD_LOGIC;
+		 MAIN_CLK : IN STD_LOGIC;
+		 nFB_OE : IN STD_LOGIC;
+		 nFB_WR : IN STD_LOGIC;
+		 nFB_CS1 : IN STD_LOGIC;
+		 nFB_CS2 : IN STD_LOGIC;
+		 FB_SIZE0 : IN STD_LOGIC;
+		 FB_SIZE1 : IN STD_LOGIC;
+		 nFB_BURST : IN STD_LOGIC;
+		 nRSTO : IN STD_LOGIC;
+		 nFB_CS3 : IN STD_LOGIC;
+		 FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 IO : INOUT STD_LOGIC_VECTOR(17 DOWNTO 0);
+		 SRD : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 nSRCS : OUT STD_LOGIC;
+		 nSRBLE : OUT STD_LOGIC;
+		 nSRBHE : OUT STD_LOGIC;
+		 nSRWE : OUT STD_LOGIC;
+		 nSROE : OUT STD_LOGIC;
+		 DSP_INT : OUT STD_LOGIC;
+		 DSP_TA : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT interrupt_handler
+	PORT(MAIN_CLK : IN STD_LOGIC;
+		 nFB_WR : IN STD_LOGIC;
+		 nFB_CS1 : IN STD_LOGIC;
+		 nFB_CS2 : IN STD_LOGIC;
+		 FB_SIZE0 : IN STD_LOGIC;
+		 FB_SIZE1 : IN STD_LOGIC;
+		 PIC_INT : IN STD_LOGIC;
+		 E0_INT : IN STD_LOGIC;
+		 DVI_INT : IN STD_LOGIC;
+		 nPCI_INTA : IN STD_LOGIC;
+		 nPCI_INTB : IN STD_LOGIC;
+		 nPCI_INTC : IN STD_LOGIC;
+		 nPCI_INTD : IN STD_LOGIC;
+		 nMFP_INT : IN STD_LOGIC;
+		 nFB_OE : IN STD_LOGIC;
+		 DSP_INT : IN STD_LOGIC;
+		 VSYNC : IN STD_LOGIC;
+		 HSYNC : IN STD_LOGIC;
+		 DMA_DRQ : IN STD_LOGIC;
+		 FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 INT_HANDLER_TA : OUT STD_LOGIC;
+		 TIN0 : OUT STD_LOGIC;
+		 ACP_CONF : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 nIRQ : OUT STD_LOGIC_VECTOR(7 DOWNTO 2)
+	);
+END COMPONENT;
+
+COMPONENT falconio_sdcard_ide_cf
+	PORT(CLK33M : IN STD_LOGIC;
+		 MAIN_CLK : IN STD_LOGIC;
+		 CLK2M : IN STD_LOGIC;
+		 CLK500k : IN STD_LOGIC;
+		 nFB_CS1 : IN STD_LOGIC;
+		 FB_SIZE0 : IN STD_LOGIC;
+		 FB_SIZE1 : IN STD_LOGIC;
+		 nFB_BURST : IN STD_LOGIC;
+		 LP_BUSY : IN STD_LOGIC;
+		 nACSI_DRQ : IN STD_LOGIC;
+		 nACSI_INT : IN STD_LOGIC;
+		 nSCSI_DRQ : IN STD_LOGIC;
+		 nSCSI_MSG : IN STD_LOGIC;
+		 MIDI_IN : IN STD_LOGIC;
+		 RxD : IN STD_LOGIC;
+		 CTS : IN STD_LOGIC;
+		 RI : IN STD_LOGIC;
+		 DCD : IN STD_LOGIC;
+		 AMKB_RX : IN STD_LOGIC;
+		 PIC_AMKB_RX : IN STD_LOGIC;
+		 IDE_RDY : IN STD_LOGIC;
+		 IDE_INT : IN STD_LOGIC;
+		 WP_CS_CARD : IN STD_LOGIC;
+		 nINDEX : IN STD_LOGIC;
+		 TRACK00 : IN STD_LOGIC;
+		 nRD_DATA : IN STD_LOGIC;
+		 nDCHG : IN STD_LOGIC;
+		 SD_DATA0 : IN STD_LOGIC;
+		 SD_DATA1 : IN STD_LOGIC;
+		 SD_DATA2 : IN STD_LOGIC;
+		 SD_CARD_DEDECT : IN STD_LOGIC;
+		 SD_WP : IN STD_LOGIC;
+		 nDACK0 : IN STD_LOGIC;
+		 nFB_WR : IN STD_LOGIC;
+		 WP_CF_CARD : IN STD_LOGIC;
+		 nWP : IN STD_LOGIC;
+		 nFB_CS2 : IN STD_LOGIC;
+		 nRSTO : IN STD_LOGIC;
+		 nSCSI_C_D : IN STD_LOGIC;
+		 nSCSI_I_O : IN STD_LOGIC;
+		 CLK2M4576 : IN STD_LOGIC;
+		 nFB_OE : IN STD_LOGIC;
+		 VSYNC : IN STD_LOGIC;
+		 HSYNC : IN STD_LOGIC;
+		 DSP_INT : IN STD_LOGIC;
+		 nBLANK : IN STD_LOGIC;
+		 FDC_CLK : IN STD_LOGIC;
+		 FB_ALE : IN STD_LOGIC;
+		 HD_DD : IN STD_LOGIC;
+		 SCSI_PAR : INOUT STD_LOGIC;
+		 nSCSI_SEL : INOUT STD_LOGIC;
+		 nSCSI_BUSY : INOUT STD_LOGIC;
+		 nSCSI_RST : INOUT STD_LOGIC;
+		 SD_CD_DATA3 : INOUT STD_LOGIC;
+		 SD_CDM_D1 : INOUT STD_LOGIC;
+		 ACP_CONF : IN STD_LOGIC_VECTOR(31 DOWNTO 24);
+		 ACSI_D : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 FB_AD : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 FB_ADR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 LP_D : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 SCSI_D : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 nIDE_CS1 : OUT STD_LOGIC;
+		 nIDE_CS0 : OUT STD_LOGIC;
+		 LP_STR : OUT STD_LOGIC;
+		 LP_DIR : OUT STD_LOGIC;
+		 nACSI_ACK : OUT STD_LOGIC;
+		 nACSI_RESET : OUT STD_LOGIC;
+		 nACSI_CS : OUT STD_LOGIC;
+		 ACSI_DIR : OUT STD_LOGIC;
+		 ACSI_A1 : OUT STD_LOGIC;
+		 nSCSI_ACK : OUT STD_LOGIC;
+		 nSCSI_ATN : OUT STD_LOGIC;
+		 SCSI_DIR : OUT STD_LOGIC;
+		 SD_CLK : OUT STD_LOGIC;
+		 YM_QA : OUT STD_LOGIC;
+		 YM_QC : OUT STD_LOGIC;
+		 YM_QB : OUT STD_LOGIC;
+		 nSDSEL : OUT STD_LOGIC;
+		 STEP : OUT STD_LOGIC;
+		 MOT_ON : OUT STD_LOGIC;
+		 nRP_LDS : OUT STD_LOGIC;
+		 nRP_UDS : OUT STD_LOGIC;
+		 nROM4 : OUT STD_LOGIC;
+		 nROM3 : OUT STD_LOGIC;
+		 nCF_CS1 : OUT STD_LOGIC;
+		 nCF_CS0 : OUT STD_LOGIC;
+		 nIDE_RD : OUT STD_LOGIC;
+		 nIDE_WR : OUT STD_LOGIC;
+		 AMKB_TX : OUT STD_LOGIC;
+		 IDE_RES : OUT STD_LOGIC;
+		 DTR : OUT STD_LOGIC;
+		 RTS : OUT STD_LOGIC;
+		 TxD : OUT STD_LOGIC;
+		 MIDI_OLR : OUT STD_LOGIC;
+		 MIDI_TLR : OUT STD_LOGIC;
+		 nDREQ0 : OUT STD_LOGIC;
+		 DSA_D : OUT STD_LOGIC;
+		 nMFP_INT : OUT STD_LOGIC;
+		 FALCON_IO_TA : OUT STD_LOGIC;
+		 STEP_DIR : OUT STD_LOGIC;
+		 WR_DATA : OUT STD_LOGIC;
+		 WR_GATE : OUT STD_LOGIC;
+		 DMA_DRQ : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+SIGNAL	ACP_CONF :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	CLK25M_ALTERA_SYNTHESIZED :  STD_LOGIC;
+SIGNAL	CLK2M :  STD_LOGIC;
+SIGNAL	CLK2M4576 :  STD_LOGIC;
+SIGNAL	CLK48M :  STD_LOGIC;
+SIGNAL	CLK500k :  STD_LOGIC;
+SIGNAL	CLK_VIDEO :  STD_LOGIC;
+SIGNAL	DDR_SYNC_66M :  STD_LOGIC;
+SIGNAL	DDRCLK :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	DMA_DRQ :  STD_LOGIC;
+SIGNAL	DSP_INT :  STD_LOGIC;
+SIGNAL	DSP_TA :  STD_LOGIC;
+SIGNAL	FALCON_IO_TA :  STD_LOGIC;
+SIGNAL	FB_ADR :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	FDC_CLK :  STD_LOGIC;
+SIGNAL	HSYNC :  STD_LOGIC;
+SIGNAL	INT_HANDLER_TA :  STD_LOGIC;
+SIGNAL	LP_DIR :  STD_LOGIC;
+SIGNAL	MOT_ON :  STD_LOGIC;
+SIGNAL	nBLANK :  STD_LOGIC;
+SIGNAL	nDREQ0 :  STD_LOGIC;
+SIGNAL	nMFP_INT :  STD_LOGIC;
+SIGNAL	nRSTO :  STD_LOGIC;
+SIGNAL	PIXEL_CLK :  STD_LOGIC;
+SIGNAL	SD_CDM_D1 :  STD_LOGIC;
+SIGNAL	STEP :  STD_LOGIC;
+SIGNAL	STEP_DIR :  STD_LOGIC;
+SIGNAL	TIMEBASE :  STD_LOGIC_VECTOR(17 DOWNTO 0);
+SIGNAL	VIDEO_RECONFIG :  STD_LOGIC;
+SIGNAL	Video_TA :  STD_LOGIC;
+SIGNAL	VR_BUSY :  STD_LOGIC;
+SIGNAL	VR_D :  STD_LOGIC_VECTOR(8 DOWNTO 0);
+SIGNAL	VR_RD :  STD_LOGIC;
+SIGNAL	VR_WR :  STD_LOGIC;
+SIGNAL	VSYNC :  STD_LOGIC;
+SIGNAL	WR_DATA :  STD_LOGIC;
+SIGNAL	WR_GATE :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_6 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
+
+
+BEGIN 
+nDREQ1 <= nDACK1;
+SYNTHESIZED_WIRE_9 <= '0';
+SYNTHESIZED_WIRE_10 <= '1';
+
+
+
+b2v_Fredi_Aschwanden : video
+PORT MAP(MAIN_CLK => MAIN_CLK,
+		 nFB_CS1 => nFB_CS1,
+		 nFB_CS2 => nFB_CS2,
+		 nFB_CS3 => nFB_CS3,
+		 nFB_WR => nFB_WR,
+		 FB_SIZE0 => FB_SIZE0,
+		 FB_SIZE1 => FB_SIZE1,
+		 nRSTO => nRSTO,
+		 nFB_OE => nFB_OE,
+		 FB_ALE => FB_ALE,
+		 DDR_SYNC_66M => DDR_SYNC_66M,
+		 CLK33M => CLK33M,
+		 CLK25M => CLK25M_ALTERA_SYNTHESIZED,
+		 CLK_VIDEO => CLK_VIDEO,
+		 VR_BUSY => VR_BUSY,
+		 DDRCLK => DDRCLK,
+		 FB_AD => FB_AD,
+		 FB_ADR => FB_ADR,
+		 VD => VD,
+		 VDQS => VDQS,
+		 VR_D => VR_D,
+		 VR_RD => VR_RD,
+		 nBLANK => nBLANK,
+		 nVWE => nVWE,
+		 nVCAS => nVCAS,
+		 nVRAS => nVRAS,
+		 nVCS => nVCS,
+		 nPD_VGA => nPD_VGA,
+		 VCKE => VCKE,
+		 VSYNC => VSYNC,
+		 HSYNC => HSYNC,
+		 nSYNC => nSYNC,
+		 VIDEO_TA => Video_TA,
+		 PIXEL_CLK => PIXEL_CLK,
+		 VIDEO_RECONFIG => VIDEO_RECONFIG,
+		 VR_WR => VR_WR,
+		 BA => BA,
+		 VA => VA,
+		 VB => VB,
+		 VDM => VDM,
+		 VG => VG,
+		 VR => VR);
+
+
+b2v_inst : altpll1
+PORT MAP(inclk0 => CLK33M,
+		 c0 => CLK500k,
+		 c1 => CLK2M4576,
+		 c2 => CLK24M576,
+		 locked => SYNTHESIZED_WIRE_5);
+
+
+b2v_inst1 : lpm_ff0
+PORT MAP(clock => DDR_SYNC_66M,
+		 enable => FB_ALE,
+		 data => FB_AD,
+		 q => FB_ADR);
+
+
+
+
+b2v_inst12 : altpll2
+PORT MAP(inclk0 => MAIN_CLK,
+		 c0 => DDRCLK(0),
+		 c1 => DDRCLK(1),
+		 c2 => DDRCLK(2),
+		 c3 => DDRCLK(3),
+		 c4 => DDR_SYNC_66M);
+
+
+b2v_inst13 : altpll3
+PORT MAP(inclk0 => CLK33M,
+		 c0 => CLK2M,
+		 c1 => FDC_CLK,
+		 c2 => CLK25M_ALTERA_SYNTHESIZED,
+		 c3 => CLK48M);
+
+
+nMOT_ON <= NOT(MOT_ON);
+
+
+
+nSTEP_DIR <= NOT(STEP_DIR);
+
+
+
+nSTEP <= NOT(STEP);
+
+
+
+nWR <= NOT(WR_DATA);
+
+
+
+b2v_inst18 : lpm_counter0
+PORT MAP(clock => CLK500k,
+		 q => TIMEBASE);
+
+
+nWR_GATE <= NOT(WR_GATE);
+
+
+
+nFB_TA <= NOT(Video_TA OR INT_HANDLER_TA OR DSP_TA OR FALCON_IO_TA);
+
+
+b2v_inst22 : altpll4
+PORT MAP(inclk0 => CLK48M,
+		 areset => SYNTHESIZED_WIRE_0,
+		 scanclk => SYNTHESIZED_WIRE_1,
+		 scandata => SYNTHESIZED_WIRE_2,
+		 scanclkena => SYNTHESIZED_WIRE_3,
+		 configupdate => SYNTHESIZED_WIRE_4,
+		 c0 => CLK_VIDEO,
+		 scandataout => SYNTHESIZED_WIRE_6,
+		 scandone => SYNTHESIZED_WIRE_7);
+
+
+SYNTHESIZED_WIRE_8 <= NOT(nRSTO);
+
+
+
+nRSTO <= SYNTHESIZED_WIRE_5 AND nRSTO_MCF;
+
+LED_FPGA_OK <= TIMEBASE(17);
+
+
+
+nDDR_CLK <= NOT(DDRCLK(0));
+
+
+
+b2v_inst5 : altddio_out3
+PORT MAP(datain_h => VSYNC,
+		 datain_l => VSYNC,
+		 outclock => PIXEL_CLK,
+		 dataout => VSYNC_PAD);
+
+
+b2v_inst6 : altddio_out3
+PORT MAP(datain_h => HSYNC,
+		 datain_l => HSYNC,
+		 outclock => PIXEL_CLK,
+		 dataout => HSYNC_PAD);
+
+
+b2v_inst7 : altpll_reconfig1
+PORT MAP(reconfig => VIDEO_RECONFIG,
+		 read_param => VR_RD,
+		 write_param => VR_WR,
+		 pll_scandataout => SYNTHESIZED_WIRE_6,
+		 pll_scandone => SYNTHESIZED_WIRE_7,
+		 clock => MAIN_CLK,
+		 reset => SYNTHESIZED_WIRE_8,
+		 counter_param => FB_ADR(8 DOWNTO 6),
+		 counter_type => FB_ADR(5 DOWNTO 2),
+		 data_in => FB_AD(24 DOWNTO 16),
+		 busy => VR_BUSY,
+		 pll_scandata => SYNTHESIZED_WIRE_2,
+		 pll_scanclk => SYNTHESIZED_WIRE_1,
+		 pll_scanclkena => SYNTHESIZED_WIRE_3,
+		 pll_configupdate => SYNTHESIZED_WIRE_4,
+		 pll_areset => SYNTHESIZED_WIRE_0,
+		 data_out => VR_D);
+
+
+b2v_inst8 : altddio_out3
+PORT MAP(datain_h => nBLANK,
+		 datain_l => nBLANK,
+		 outclock => PIXEL_CLK,
+		 dataout => nBLANK_PAD);
+
+
+b2v_inst9 : altddio_out3
+PORT MAP(datain_h => SYNTHESIZED_WIRE_9,
+		 datain_l => SYNTHESIZED_WIRE_10,
+		 outclock => PIXEL_CLK,
+		 dataout => PIXEL_CLK_PAD);
+
+
+b2v_Mathias_Alles : dsp
+PORT MAP(CLK33M => CLK33M,
+		 MAIN_CLK => MAIN_CLK,
+		 nFB_OE => nFB_OE,
+		 nFB_WR => nFB_WR,
+		 nFB_CS1 => nFB_CS1,
+		 nFB_CS2 => nFB_CS2,
+		 FB_SIZE0 => FB_SIZE0,
+		 FB_SIZE1 => FB_SIZE1,
+		 nFB_BURST => nFB_BURST,
+		 nRSTO => nRSTO,
+		 nFB_CS3 => nFB_CS3,
+		 FB_AD => FB_AD,
+		 FB_ADR => FB_ADR,
+		 IO => IO,
+		 SRD => SRD,
+		 nSRCS => nSRCS,
+		 nSRBLE => nSRBLE,
+		 nSRBHE => nSRBHE,
+		 nSRWE => nSRWE,
+		 nSROE => nSROE,
+		 DSP_INT => DSP_INT,
+		 DSP_TA => DSP_TA);
+
+
+b2v_nobody : interrupt_handler
+PORT MAP(MAIN_CLK => MAIN_CLK,
+		 nFB_WR => nFB_WR,
+		 nFB_CS1 => nFB_CS1,
+		 nFB_CS2 => nFB_CS2,
+		 FB_SIZE0 => FB_SIZE0,
+		 FB_SIZE1 => FB_SIZE1,
+		 PIC_INT => PIC_INT,
+		 E0_INT => E0_INT,
+		 DVI_INT => DVI_INT,
+		 nPCI_INTA => nPCI_INTA,
+		 nPCI_INTB => nPCI_INTB,
+		 nPCI_INTC => nPCI_INTC,
+		 nPCI_INTD => nPCI_INTD,
+		 nMFP_INT => nMFP_INT,
+		 nFB_OE => nFB_OE,
+		 DSP_INT => DSP_INT,
+		 VSYNC => VSYNC,
+		 HSYNC => HSYNC,
+		 DMA_DRQ => DMA_DRQ,
+		 FB_AD => FB_AD,
+		 FB_ADR => FB_ADR,
+		 INT_HANDLER_TA => INT_HANDLER_TA,
+		 TIN0 => TIN0,
+		 ACP_CONF => ACP_CONF,
+		 nIRQ => nIRQ);
+
+
+b2v_Wolfgang_Foerster_and_Fredi_Aschwanden : falconio_sdcard_ide_cf
+PORT MAP(CLK33M => CLK33M,
+		 MAIN_CLK => MAIN_CLK,
+		 CLK2M => CLK2M,
+		 CLK500k => CLK500k,
+		 nFB_CS1 => nFB_CS1,
+		 FB_SIZE0 => FB_SIZE0,
+		 FB_SIZE1 => FB_SIZE1,
+		 nFB_BURST => nFB_BURST,
+		 LP_BUSY => LP_BUSY,
+		 nACSI_DRQ => nACSI_DRQ,
+		 nACSI_INT => nACSI_INT,
+		 nSCSI_DRQ => nSCSI_DRQ,
+		 nSCSI_MSG => nSCSI_MSG,
+		 MIDI_IN => MIDI_IN,
+		 RxD => RxD,
+		 CTS => CTS,
+		 RI => RI,
+		 DCD => DCD,
+		 AMKB_RX => AMKB_RX,
+		 PIC_AMKB_RX => PIC_AMKB_RX,
+		 IDE_RDY => IDE_RDY,
+		 IDE_INT => IDE_INT,
+		 nINDEX => nINDEX,
+		 TRACK00 => TRACK00,
+		 nRD_DATA => nRD_DATA,
+		 nDCHG => nDCHG,
+		 SD_DATA0 => SD_DATA0,
+		 SD_DATA1 => SD_DATA1,
+		 SD_DATA2 => SD_DATA2,
+		 SD_CARD_DEDECT => SD_CARD_DEDECT,
+		 SD_WP => SD_WP,
+		 nDACK0 => nDACK0,
+		 nFB_WR => nFB_WR,
+		 WP_CF_CARD => WP_CF_CARD,
+		 nWP => nWP,
+		 nFB_CS2 => nFB_CS2,
+		 nRSTO => nRSTO,
+		 nSCSI_C_D => nSCSI_C_D,
+		 nSCSI_I_O => nSCSI_I_O,
+		 CLK2M4576 => CLK2M4576,
+		 nFB_OE => nFB_OE,
+		 VSYNC => VSYNC,
+		 HSYNC => HSYNC,
+		 DSP_INT => DSP_INT,
+		 nBLANK => nBLANK,
+		 FDC_CLK => FDC_CLK,
+		 FB_ALE => FB_ALE,
+		 HD_DD => HD_DD,
+		 SCSI_PAR => SCSI_PAR,
+		 nSCSI_SEL => nSCSI_SEL,
+		 nSCSI_BUSY => nSCSI_BUSY,
+		 nSCSI_RST => nSCSI_RST,
+		 SD_CD_DATA3 => SD_CD_DATA3,
+		 SD_CDM_D1 => SD_CDM_D1,
+		 ACP_CONF => ACP_CONF(31 DOWNTO 24),
+		 ACSI_D => ACSI_D,
+		 FB_AD => FB_AD,
+		 FB_ADR => FB_ADR,
+		 LP_D => LP_D,
+		 SCSI_D => SCSI_D,
+		 nIDE_CS1 => nIDE_CS1,
+		 nIDE_CS0 => nIDE_CS0,
+		 LP_STR => LP_STR,
+		 LP_DIR => LP_DIR,
+		 nACSI_ACK => nACSI_ACK,
+		 nACSI_RESET => nACSI_RESET,
+		 nACSI_CS => nACSI_CS,
+		 ACSI_DIR => ACSI_DIR,
+		 ACSI_A1 => ACSI_A1,
+		 nSCSI_ACK => nSCSI_ACK,
+		 nSCSI_ATN => nSCSI_ATN,
+		 SCSI_DIR => SCSI_DIR,
+		 SD_CLK => SD_CLK,
+		 YM_QA => YM_QA,
+		 YM_QC => YM_QC,
+		 YM_QB => YM_QB,
+		 nSDSEL => nSDSEL,
+		 STEP => STEP,
+		 MOT_ON => MOT_ON,
+		 nRP_LDS => nRP_LDS,
+		 nRP_UDS => nRP_UDS,
+		 nROM4 => nROM4,
+		 nROM3 => nROM3,
+		 nCF_CS1 => nCF_CS1,
+		 nCF_CS0 => nCF_CS0,
+		 nIDE_RD => nIDE_RD,
+		 nIDE_WR => nIDE_WR,
+		 AMKB_TX => AMKB_TX,
+		 IDE_RES => IDE_RES,
+		 DTR => DTR,
+		 RTS => RTS,
+		 TxD => TxD,
+		 MIDI_OLR => MIDI_OLR,
+		 MIDI_TLR => MIDI_TLR,
+		 DSA_D => DSA_D,
+		 nMFP_INT => nMFP_INT,
+		 FALCON_IO_TA => FALCON_IO_TA,
+		 STEP_DIR => STEP_DIR,
+		 WR_DATA => WR_DATA,
+		 WR_GATE => WR_GATE,
+		 DMA_DRQ => DMA_DRQ);
+
+SD_CMD_D1 <= SD_CDM_D1;
+CLK25M <= CLK25M_ALTERA_SYNTHESIZED;
+DDR_CLK <= DDRCLK(0);
+CLKUSB <= CLK48M;
+LPDIR <= LP_DIR;
+
+END bdf_type;
\ No newline at end of file
diff --git a/FPGA_quartus_GE/firebee1_assignment_defaults.qdf b/FPGA_quartus_GE/firebee1_assignment_defaults.qdf
new file mode 100644
index 0000000..2119467
--- /dev/null
+++ b/FPGA_quartus_GE/firebee1_assignment_defaults.qdf
@@ -0,0 +1,687 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
+# Date created = 08:49:57  June 14, 2010
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus II software and is used
+#    to preserve global assignments across Quartus II versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name SMART_RECOMPILE Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name IGNORE_CLOCK_SETTINGS Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off
+set_global_assignment -name ENABLE_CLOCK_LATENCY Off
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000B
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone IV E"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix IV"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "HardCopy Stratix"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000AE
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Cyclone
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "MAX II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria II GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX7000S
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Cyclone II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone IV GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "HardCopy IV"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Cyclone III LS"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Stratix III"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER On -family "Arria GX"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family MAX3000A
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family "Stratix II"
+set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER Off -family Stratix
+set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200
+set_global_assignment -name DO_MIN_ANALYSIS Off
+set_global_assignment -name DO_MIN_TIMING Off
+set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off
+set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "HardCopy Stratix"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000B
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy Stratix"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000AE
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family Cyclone
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000S
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX3000A
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family Stratix
+set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy Stratix"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Stratix II"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On
+set_global_assignment -name PARALLEL_SYNTHESIS -value ON
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Cyclone III LS"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Cyclone III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Stratix III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "HardCopy III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "Arria II GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value ON -family "HardCopy IV"
+set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy Stratix"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy Stratix"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS Off
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name STOP_AFTER_CONGESTION_MAP Off
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy Stratix"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT Off
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name INCREMENTAL_COMPILATION FULL_INCREMENTAL_COMPILATION
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE POST_FIT
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ?
+set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
diff --git a/FPGA_quartus_GE/firebee1_description.txt b/FPGA_quartus_GE/firebee1_description.txt
new file mode 100644
index 0000000..e69de29
diff --git a/FPGA_quartus_GE/lpm_bustri_BYT.bsf b/FPGA_quartus_GE/lpm_bustri_BYT.bsf
new file mode 100644
index 0000000..dcc4b63
--- /dev/null
+++ b/FPGA_quartus_GE/lpm_bustri_BYT.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 96 40)
+	(text "lpm_bustri_BYT" (rect 2 1 110 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[7..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 96 24)
+		(bidir)
+		(text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
+		(text "tridata[7..0]" (rect 100 -30 113 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 96 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "8" (rect 71 25 76 37)(font "Arial" ))
+		(text "8" (rect 15 25 20 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 66 28)(pt 74 20)(line_width 1))
+		(line (pt 10 28)(pt 18 20)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/lpm_bustri_BYT.inc b/FPGA_quartus_GE/lpm_bustri_BYT.inc
new file mode 100644
index 0000000..8cb4941
--- /dev/null
+++ b/FPGA_quartus_GE/lpm_bustri_BYT.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_bustri_BYT 
+(
+	data[7..0],
+	enabledt
+)
+
+RETURNS (
+	tridata[7..0]
+);
diff --git a/FPGA_quartus_GE/lpm_bustri_BYT.qip b/FPGA_quartus_GE/lpm_bustri_BYT.qip
new file mode 100644
index 0000000..89e40bd
--- /dev/null
+++ b/FPGA_quartus_GE/lpm_bustri_BYT.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_BYT.cmp"]
diff --git a/FPGA_quartus_GE/lpm_bustri_BYT.vhd b/FPGA_quartus_GE/lpm_bustri_BYT.vhd
new file mode 100644
index 0000000..d24e3cb
--- /dev/null
+++ b/FPGA_quartus_GE/lpm_bustri_BYT.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri_BYT.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri_BYT IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END lpm_bustri_BYT;
+
+
+ARCHITECTURE SYN OF lpm_bustri_byt IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 8
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "8"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 8 0 BIDIR NODEFVAL tridata[7..0]
+-- Retrieval info: CONNECT: tridata 0 0 8 0 @tridata 0 0 8 0
+-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_BYT_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/lpm_bustri_LONG.bsf b/FPGA_quartus_GE/lpm_bustri_LONG.bsf
new file mode 100644
index 0000000..6535d3e
--- /dev/null
+++ b/FPGA_quartus_GE/lpm_bustri_LONG.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 112 40)
+	(text "lpm_bustri_LONG" (rect 5 1 126 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 112 24)
+		(bidir)
+		(text "tridata[31..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "tridata[31..0]" (rect 116 -36 129 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 112 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "32" (rect 77 25 87 37)(font "Arial" ))
+		(text "32" (rect 13 25 23 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 72 28)(pt 80 20)(line_width 1))
+		(line (pt 8 28)(pt 16 20)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/lpm_bustri_LONG.inc b/FPGA_quartus_GE/lpm_bustri_LONG.inc
new file mode 100644
index 0000000..f180c48
--- /dev/null
+++ b/FPGA_quartus_GE/lpm_bustri_LONG.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_bustri_LONG 
+(
+	data[31..0],
+	enabledt
+)
+
+RETURNS (
+	tridata[31..0]
+);
diff --git a/FPGA_quartus_GE/lpm_bustri_LONG.qip b/FPGA_quartus_GE/lpm_bustri_LONG.qip
new file mode 100644
index 0000000..67b7232
--- /dev/null
+++ b/FPGA_quartus_GE/lpm_bustri_LONG.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_LONG.cmp"]
diff --git a/FPGA_quartus_GE/lpm_bustri_LONG.vhd b/FPGA_quartus_GE/lpm_bustri_LONG.vhd
new file mode 100644
index 0000000..3de83c0
--- /dev/null
+++ b/FPGA_quartus_GE/lpm_bustri_LONG.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri_LONG.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri_LONG IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END lpm_bustri_LONG;
+
+
+ARCHITECTURE SYN OF lpm_bustri_long IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 32
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 32 0 BIDIR NODEFVAL tridata[31..0]
+-- Retrieval info: CONNECT: tridata 0 0 32 0 @tridata 0 0 32 0
+-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_LONG_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/lpm_bustri_WORD.bsf b/FPGA_quartus_GE/lpm_bustri_WORD.bsf
new file mode 100644
index 0000000..4e882d1
--- /dev/null
+++ b/FPGA_quartus_GE/lpm_bustri_WORD.bsf
@@ -0,0 +1,56 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 112 40)
+	(text "lpm_bustri_WORD" (rect 2 1 129 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 24 25 36)(font "Arial" ))
+	(port
+		(pt 40 40)
+		(input)
+		(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
+		(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
+		(line (pt 40 40)(pt 40 28)(line_width 1))
+	)
+	(port
+		(pt 0 24)
+		(input)
+		(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[15..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 0 24)(pt 32 24)(line_width 3))
+	)
+	(port
+		(pt 112 24)
+		(bidir)
+		(text "tridata[15..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
+		(text "tridata[15..0]" (rect 116 -36 129 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 112 24)(pt 48 24)(line_width 3))
+	)
+	(drawing
+		(text "16" (rect 77 25 87 37)(font "Arial" ))
+		(text "16" (rect 13 25 23 37)(font "Arial" ))
+		(line (pt 32 16)(pt 48 24)(line_width 1))
+		(line (pt 48 24)(pt 32 32)(line_width 1))
+		(line (pt 32 32)(pt 32 16)(line_width 1))
+		(line (pt 72 28)(pt 80 20)(line_width 1))
+		(line (pt 8 28)(pt 16 20)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/lpm_bustri_WORD.inc b/FPGA_quartus_GE/lpm_bustri_WORD.inc
new file mode 100644
index 0000000..09f6251
--- /dev/null
+++ b/FPGA_quartus_GE/lpm_bustri_WORD.inc
@@ -0,0 +1,24 @@
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+FUNCTION lpm_bustri_WORD 
+(
+	data[15..0],
+	enabledt
+)
+
+RETURNS (
+	tridata[15..0]
+);
diff --git a/FPGA_quartus_GE/lpm_bustri_WORD.qip b/FPGA_quartus_GE/lpm_bustri_WORD.qip
new file mode 100644
index 0000000..57bbe2e
--- /dev/null
+++ b/FPGA_quartus_GE/lpm_bustri_WORD.qip
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_BUSTRI"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.inc"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_bustri_WORD.cmp"]
diff --git a/FPGA_quartus_GE/lpm_bustri_WORD.vhd b/FPGA_quartus_GE/lpm_bustri_WORD.vhd
new file mode 100644
index 0000000..85cbdd1
--- /dev/null
+++ b/FPGA_quartus_GE/lpm_bustri_WORD.vhd
@@ -0,0 +1,107 @@
+-- megafunction wizard: %LPM_BUSTRI%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_bustri 
+
+-- ============================================================
+-- File Name: lpm_bustri_WORD.vhd
+-- Megafunction Name(s):
+-- 			lpm_bustri
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_bustri_WORD IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		enabledt		: IN STD_LOGIC ;
+		tridata		: INOUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+END lpm_bustri_WORD;
+
+
+ARCHITECTURE SYN OF lpm_bustri_word IS
+
+
+
+
+	COMPONENT lpm_bustri
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			enabledt	: IN STD_LOGIC ;
+			data	: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+			tridata	: INOUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+
+	lpm_bustri_component : lpm_bustri
+	GENERIC MAP (
+		lpm_type => "LPM_BUSTRI",
+		lpm_width => 16
+	)
+	PORT MAP (
+		enabledt => enabledt,
+		data => data,
+		tridata => tridata
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: BiDir NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "16"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_BUSTRI"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+-- Retrieval info: USED_PORT: enabledt 0 0 0 0 INPUT NODEFVAL enabledt
+-- Retrieval info: USED_PORT: tridata 0 0 16 0 BIDIR NODEFVAL tridata[15..0]
+-- Retrieval info: CONNECT: tridata 0 0 16 0 @tridata 0 0 16 0
+-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+-- Retrieval info: CONNECT: @enabledt 0 0 0 0 enabledt 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_bustri_WORD_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/lpm_counter0.bsf b/FPGA_quartus_GE/lpm_counter0.bsf
new file mode 100644
index 0000000..7fc7aaa
--- /dev/null
+++ b/FPGA_quartus_GE/lpm_counter0.bsf
@@ -0,0 +1,49 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 144 64)
+	(text "lpm_counter0" (rect 33 1 125 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 48 25 60)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 144 40)
+		(output)
+		(text "q[17..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[17..0]" (rect 89 34 125 47)(font "Arial" (font_size 8)))
+		(line (pt 144 40)(pt 128 40)(line_width 3))
+	)
+	(drawing
+		(text "up counter" (rect 84 17 128 29)(font "Arial" ))
+		(line (pt 16 16)(pt 128 16)(line_width 1))
+		(line (pt 128 16)(pt 128 48)(line_width 1))
+		(line (pt 128 48)(pt 16 48)(line_width 1))
+		(line (pt 16 48)(pt 16 16)(line_width 1))
+		(line (pt 16 26)(pt 22 32)(line_width 1))
+		(line (pt 22 32)(pt 16 38)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/lpm_counter0.qip b/FPGA_quartus_GE/lpm_counter0.qip
new file mode 100644
index 0000000..a72845b
--- /dev/null
+++ b/FPGA_quartus_GE/lpm_counter0.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_COUNTER"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_counter0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_counter0.cmp"]
diff --git a/FPGA_quartus_GE/lpm_counter0.vhd b/FPGA_quartus_GE/lpm_counter0.vhd
new file mode 100644
index 0000000..9135dbc
--- /dev/null
+++ b/FPGA_quartus_GE/lpm_counter0.vhd
@@ -0,0 +1,126 @@
+-- megafunction wizard: %LPM_COUNTER%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_counter 
+
+-- ============================================================
+-- File Name: lpm_counter0.vhd
+-- Megafunction Name(s):
+-- 			lpm_counter
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_counter0 IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
+	);
+END lpm_counter0;
+
+
+ARCHITECTURE SYN OF lpm_counter0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (17 DOWNTO 0);
+
+
+
+	COMPONENT lpm_counter
+	GENERIC (
+		lpm_direction		: STRING;
+		lpm_port_updown		: STRING;
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			clock	: IN STD_LOGIC ;
+			q	: OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(17 DOWNTO 0);
+
+	lpm_counter_component : lpm_counter
+	GENERIC MAP (
+		lpm_direction => "UP",
+		lpm_port_updown => "PORT_UNUSED",
+		lpm_type => "LPM_COUNTER",
+		lpm_width => 18
+	)
+	PORT MAP (
+		clock => clock,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
+-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET NUMERIC "0"
+-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
+-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
+-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
+-- Retrieval info: PRIVATE: Direction NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
+-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
+-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
+-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET NUMERIC "0"
+-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "18"
+-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
+-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "18"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+-- Retrieval info: USED_PORT: q 0 0 18 0 OUTPUT NODEFVAL q[17..0]
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 18 0 @q 0 0 18 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_waveforms.html TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter0_wave*.jpg FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/lpm_latch0.bsf b/FPGA_quartus_GE/lpm_latch0.bsf
new file mode 100644
index 0000000..ddb325c
--- /dev/null
+++ b/FPGA_quartus_GE/lpm_latch0.bsf
@@ -0,0 +1,53 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2008 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 80)
+	(text "lpm_latch0" (rect 49 1 123 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 64 25 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
+		(text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "gate" (rect 0 0 24 14)(font "Arial" (font_size 8)))
+		(text "gate" (rect 20 42 41 55)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 160 32)
+		(output)
+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+		(text "q[31..0]" (rect 105 26 141 39)(font "Arial" (font_size 8)))
+		(line (pt 160 32)(pt 144 32)(line_width 3))
+	)
+	(drawing
+		(line (pt 16 16)(pt 144 16)(line_width 1))
+		(line (pt 144 16)(pt 144 64)(line_width 1))
+		(line (pt 144 64)(pt 16 64)(line_width 1))
+		(line (pt 16 64)(pt 16 16)(line_width 1))
+	)
+)
diff --git a/FPGA_quartus_GE/lpm_latch0.qip b/FPGA_quartus_GE/lpm_latch0.qip
new file mode 100644
index 0000000..1bda27a
--- /dev/null
+++ b/FPGA_quartus_GE/lpm_latch0.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "LPM_LATCH"
+set_global_assignment -name IP_TOOL_VERSION "8.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_latch0.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch0.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_latch0.cmp"]
diff --git a/FPGA_quartus_GE/lpm_latch0.vhd b/FPGA_quartus_GE/lpm_latch0.vhd
new file mode 100644
index 0000000..1eda161
--- /dev/null
+++ b/FPGA_quartus_GE/lpm_latch0.vhd
@@ -0,0 +1,110 @@
+-- megafunction wizard: %LPM_LATCH%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: lpm_latch 
+
+-- ============================================================
+-- File Name: lpm_latch0.vhd
+-- Megafunction Name(s):
+-- 			lpm_latch
+--
+-- Simulation Library Files(s):
+-- 			lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 8.1 Build 163 10/28/2008 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2008 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY lpm;
+USE lpm.all;
+
+ENTITY lpm_latch0 IS
+	PORT
+	(
+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		gate		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END lpm_latch0;
+
+
+ARCHITECTURE SYN OF lpm_latch0 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT lpm_latch
+	GENERIC (
+		lpm_type		: STRING;
+		lpm_width		: NATURAL
+	);
+	PORT (
+			q	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+			data	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			gate	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(31 DOWNTO 0);
+
+	lpm_latch_component : lpm_latch
+	GENERIC MAP (
+		lpm_type => "LPM_LATCH",
+		lpm_width => 32
+	)
+	PORT MAP (
+		data => data,
+		gate => gate,
+		q => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: aclr NUMERIC "0"
+-- Retrieval info: PRIVATE: aset NUMERIC "0"
+-- Retrieval info: PRIVATE: nBit NUMERIC "32"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_LATCH"
+-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+-- Retrieval info: USED_PORT: gate 0 0 0 0 INPUT NODEFVAL gate
+-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+-- Retrieval info: CONNECT: @gate 0 0 0 0 gate 0 0 0 0
+-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_latch0_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: lpm
diff --git a/FPGA_quartus_GE/mux41.v b/FPGA_quartus_GE/mux41.v
new file mode 100644
index 0000000..ddb02fb
--- /dev/null
+++ b/FPGA_quartus_GE/mux41.v
@@ -0,0 +1,74 @@
+// Copyright (C) 1991-2009 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+// PROGRAM		"Quartus II 64-Bit"
+// VERSION		"Version 9.1 Build 222 10/21/2009 SJ Full Version"
+// CREATED		"Sat Mar 01 09:17:14 2014"
+
+module mux41(
+	S0,
+	D2,
+	INH,
+	D0,
+	D1,
+	D3,
+	S1,
+	Q
+);
+
+
+input	S0;
+input	D2;
+input	INH;
+input	D0;
+input	D1;
+input	D3;
+input	S1;
+output	Q;
+
+wire	SYNTHESIZED_WIRE_18;
+wire	SYNTHESIZED_WIRE_19;
+wire	SYNTHESIZED_WIRE_20;
+wire	SYNTHESIZED_WIRE_21;
+wire	SYNTHESIZED_WIRE_22;
+wire	SYNTHESIZED_WIRE_13;
+wire	SYNTHESIZED_WIRE_14;
+wire	SYNTHESIZED_WIRE_15;
+wire	SYNTHESIZED_WIRE_16;
+
+
+
+
+assign	SYNTHESIZED_WIRE_18 =  ~S0;
+
+assign	SYNTHESIZED_WIRE_21 =  ~SYNTHESIZED_WIRE_18;
+
+assign	SYNTHESIZED_WIRE_13 = SYNTHESIZED_WIRE_19 & SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_18 & D0;
+
+assign	SYNTHESIZED_WIRE_14 = SYNTHESIZED_WIRE_19 & SYNTHESIZED_WIRE_20 & SYNTHESIZED_WIRE_21 & D1;
+
+assign	SYNTHESIZED_WIRE_15 = SYNTHESIZED_WIRE_19 & SYNTHESIZED_WIRE_22 & SYNTHESIZED_WIRE_18 & D2;
+
+assign	SYNTHESIZED_WIRE_16 = SYNTHESIZED_WIRE_19 & SYNTHESIZED_WIRE_22 & SYNTHESIZED_WIRE_21 & D3;
+
+assign	Q = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14 | SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
+
+assign	SYNTHESIZED_WIRE_19 =  ~INH;
+
+assign	SYNTHESIZED_WIRE_20 =  ~S1;
+
+assign	SYNTHESIZED_WIRE_22 =  ~SYNTHESIZED_WIRE_20;
+
+
+endmodule
diff --git a/FPGA_quartus_GE/mux41.vhd b/FPGA_quartus_GE/mux41.vhd
new file mode 100644
index 0000000..b0b24ad
--- /dev/null
+++ b/FPGA_quartus_GE/mux41.vhd
@@ -0,0 +1,90 @@
+-- Copyright (C) 1991-2009 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 9.1 Build 222 10/21/2009 SJ Full Version"
+-- CREATED		"Sat Mar 01 09:16:22 2014"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY work;
+
+ENTITY mux41 IS 
+	PORT
+	(
+		S0 :  IN  STD_LOGIC;
+		D2 :  IN  STD_LOGIC;
+		INH :  IN  STD_LOGIC;
+		D0 :  IN  STD_LOGIC;
+		D1 :  IN  STD_LOGIC;
+		D3 :  IN  STD_LOGIC;
+		S1 :  IN  STD_LOGIC;
+		Q :  OUT  STD_LOGIC
+	);
+END mux41;
+
+ARCHITECTURE bdf_type OF mux41 IS 
+
+SIGNAL	SYNTHESIZED_WIRE_18 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_19 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_20 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_21 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_22 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_13 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_14 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_15 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_16 :  STD_LOGIC;
+
+
+BEGIN 
+
+
+
+SYNTHESIZED_WIRE_18 <= NOT(S0);
+
+
+
+SYNTHESIZED_WIRE_21 <= NOT(SYNTHESIZED_WIRE_18);
+
+
+
+SYNTHESIZED_WIRE_13 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_20 AND SYNTHESIZED_WIRE_18 AND D0;
+
+
+SYNTHESIZED_WIRE_14 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_20 AND SYNTHESIZED_WIRE_21 AND D1;
+
+
+SYNTHESIZED_WIRE_15 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_22 AND SYNTHESIZED_WIRE_18 AND D2;
+
+
+SYNTHESIZED_WIRE_16 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_22 AND SYNTHESIZED_WIRE_21 AND D3;
+
+
+Q <= SYNTHESIZED_WIRE_13 OR SYNTHESIZED_WIRE_14 OR SYNTHESIZED_WIRE_15 OR SYNTHESIZED_WIRE_16;
+
+
+SYNTHESIZED_WIRE_19 <= NOT(INH);
+
+
+
+SYNTHESIZED_WIRE_20 <= NOT(S1);
+
+
+
+SYNTHESIZED_WIRE_22 <= NOT(SYNTHESIZED_WIRE_20);
+
+
+
+END bdf_type;
\ No newline at end of file