First full HDL version

FPGA_quartus_GE/ahdl2v/lpm_bustri_WORD.v

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+// Xilinx XPort Language Converter, Version 4.1 (110)
+// 
+// AHDL    Design Source: lpm_bustri_WORD.tdf
+// Verilog Design Output: lpm_bustri_WORD.v
+// Created 02-Mar-2014 04:36 PM
+//
+// Copyright (c) 2014, Xilinx, Inc.  All Rights Reserved.
+// Xilinx Inc makes no warranty, expressed or implied, with respect to
+// the operation and/or functionality of the converted output files.
+// 
+
+
+// ------------------------------------------------------------------
+//   LPM_BUSTRI Parameterized Megafunction
+//   Copyright (C) 1991-2013 Altera Corporation
+//   Your use of Altera Corporation's design tools, logic functions
+//   and other software and tools, and its AMPP partner logic
+//   functions, and any output files from any of the foregoing
+//   (including device programming or simulation files), and any
+//   associated documentation or information are expressly subject
+//   to the terms and conditions of the Altera Program License
+//   Subscription Agreement, Altera MegaCore Function License
+//   Agreement, or other applicable license agreement, including,
+//   without limitation, that your use is for the sole purpose of
+//   programming logic devices manufactured by Altera and sold by
+//   Altera or its authorized distributors.  Please refer to the
+//   applicable agreement for further details.
+//   Quartus II 13.1.0 Build 162 10/23/2013
+//   Version 2.0
+// ------------------------------------------------------------------
+module lpm_bustri_WORD(tridata, data, enabletr, enabledt, result);
+   input [15:0] data;
+   input enabletr, enabledt;
+   output [15:0] result;
+   inout [15:0] tridata;
+
+//  Are the enable inputs used? 
+   wire [15:0] dout;
+   wire [15:0] dout_in;
+   wire gnd, result0_1, result0_2, result1_1, result1_2, result2_1, result2_2,
+	 result3_1, result3_2, result4_1, result4_2, result5_1, result5_2,
+	 result6_1, result6_2, result7_1, result7_2, result8_1, result8_2,
+	 result9_1, result9_2, result10_1, result10_2, result11_1, result11_2,
+	 result12_1, result12_2, result13_1, result13_2, result14_1,
+	 result14_2, result15_1, result15_2, dout0_oe_ctrl;
+
+   assign dout[0] = (dout0_oe_ctrl) ? dout_in[0] : 1'bz;
+   assign dout[1] = (dout0_oe_ctrl) ? dout_in[1] : 1'bz;
+   assign dout[2] = (dout0_oe_ctrl) ? dout_in[2] : 1'bz;
+   assign dout[3] = (dout0_oe_ctrl) ? dout_in[3] : 1'bz;
+   assign dout[4] = (dout0_oe_ctrl) ? dout_in[4] : 1'bz;
+   assign dout[5] = (dout0_oe_ctrl) ? dout_in[5] : 1'bz;
+   assign dout[6] = (dout0_oe_ctrl) ? dout_in[6] : 1'bz;
+   assign dout[7] = (dout0_oe_ctrl) ? dout_in[7] : 1'bz;
+   assign dout[8] = (dout0_oe_ctrl) ? dout_in[8] : 1'bz;
+   assign dout[9] = (dout0_oe_ctrl) ? dout_in[9] : 1'bz;
+   assign dout[10] = (dout0_oe_ctrl) ? dout_in[10] : 1'bz;
+   assign dout[11] = (dout0_oe_ctrl) ? dout_in[11] : 1'bz;
+   assign dout[12] = (dout0_oe_ctrl) ? dout_in[12] : 1'bz;
+   assign dout[13] = (dout0_oe_ctrl) ? dout_in[13] : 1'bz;
+   assign dout[14] = (dout0_oe_ctrl) ? dout_in[14] : 1'bz;
+   assign dout[15] = (dout0_oe_ctrl) ? dout_in[15] : 1'bz;
+
+// Start of original equations
+
+//  Connect buffers if they are used 
+   assign dout0_oe_ctrl = enabledt;
+   assign dout_in = data;
+   assign tridata = dout;
+   assign {result15_1, result14_1, result13_1, result12_1, result11_1,
+	 result10_1, result9_1, result8_1, result7_1, result6_1, result5_1,
+	 result4_1, result3_1, result2_1, result1_1, result0_1} = tridata;
+   assign {result15_2, result14_2, result13_2, result12_2, result11_2,
+	 result10_2, result9_2, result8_2, result7_2, result6_2, result5_2,
+	 result4_2, result3_2, result2_2, result1_2, result0_2} = {16{gnd}};
+
+
+// Assignments added to explicitly combine the
+// effects of multiple drivers in the source
+   assign result[0] = result0_1 | result0_2;
+   assign result[1] = result1_1 | result1_2;
+   assign result[2] = result2_1 | result2_2;
+   assign result[3] = result3_1 | result3_2;
+   assign result[4] = result4_1 | result4_2;
+   assign result[5] = result5_1 | result5_2;
+   assign result[6] = result6_1 | result6_2;
+   assign result[7] = result7_1 | result7_2;
+   assign result[8] = result8_1 | result8_2;
+   assign result[9] = result9_1 | result9_2;
+   assign result[10] = result10_1 | result10_2;
+   assign result[11] = result11_1 | result11_2;
+   assign result[12] = result12_1 | result12_2;
+   assign result[13] = result13_1 | result13_2;
+   assign result[14] = result14_1 | result14_2;
+   assign result[15] = result15_1 | result15_2;
+
+// Define power signal(s)
+   assign gnd = 1'b0;
+endmodule