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First full HDL version

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This commit is contained in:
torlus
2014-03-03 21:04:21 +00:00
parent f378ec7051
commit efc98f83bc
367 changed files with 85885 additions and 0 deletions
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20
FPGA_quartus_GE/PLLJ_PLLSPE_INFO.txt Normal file
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PLL_Name altpll1:b2v_inst|altpll:altpll_component|altpll_8tp2:auto_generated|pll1
PLLJITTER 33
PLLSPEmax 84
PLLSPEmin -53
PLL_Name altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|pll1
PLLJITTER 43
PLLSPEmax 84
PLLSPEmin -53
PLL_Name altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|pll1
PLLJITTER NA
PLLSPEmax 84
PLLSPEmin -53
PLL_Name altpll4:b2v_inst22|altpll:altpll_component|altpll_r4n2:auto_generated|pll1
PLLJITTER 31
PLLSPEmax 84
PLLSPEmin -53