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inserted a wait cycle to ensure FPGA reset finished before configuration

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This commit is contained in:
Markus Fröschle
2013-07-31 10:10:01 +00:00
parent 2d18a2310e
commit ded976b05d
1 changed files with 8 additions and 3 deletions
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11
BaS_gcc/sources/init_fpga.c
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@@ -22,9 +22,10 @@
* *
*/ */
#include <MCF5475.h> #include "MCF5475.h"
#include "sysinit.h" #include "sysinit.h"
#include <bas_printf.h> #include "bas_printf.h"
#include "wait.h"
#define FPGA_STATUS (1 << 0) #define FPGA_STATUS (1 << 0)
#define FPGA_CLOCK (1 << 1) #define FPGA_CLOCK (1 << 1)
@@ -45,10 +46,14 @@ void init_fpga(void)
MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK; /* FPGA clock => low */ MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK; /* FPGA clock => low */
/* pulling FPGA_CONFIG to low resets the FPGA */
MCF_GPIO_PODR_FEC1L &= ~FPGA_CONFIG; /* FPGA config => low */ MCF_GPIO_PODR_FEC1L &= ~FPGA_CONFIG; /* FPGA config => low */
wait(10); /* give it some time to do its reset stuff */
while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS) && (MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS) && (MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));
MCF_GPIO_PODR_FEC1L |= FPGA_CONFIG; /* pull FPGA_CONFIG high */
MCF_GPIO_PODR_FEC1L |= FPGA_CONFIG; /* pull FPGA_CONFIG high to start config cycle */
while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS)); /* wait until status becomes high */ while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS)); /* wait until status becomes high */
/* /*