From ded976b05d6105217e86c0e21474ef51f8f69b23 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Wed, 31 Jul 2013 10:10:01 +0000 Subject: [PATCH] inserted a wait cycle to ensure FPGA reset finished before configuration --- BaS_gcc/sources/init_fpga.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/BaS_gcc/sources/init_fpga.c b/BaS_gcc/sources/init_fpga.c index 0800f78..11048f6 100644 --- a/BaS_gcc/sources/init_fpga.c +++ b/BaS_gcc/sources/init_fpga.c @@ -22,9 +22,10 @@ * */ -#include +#include "MCF5475.h" #include "sysinit.h" -#include +#include "bas_printf.h" +#include "wait.h" #define FPGA_STATUS (1 << 0) #define FPGA_CLOCK (1 << 1) @@ -45,10 +46,14 @@ void init_fpga(void) MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK; /* FPGA clock => low */ + + /* pulling FPGA_CONFIG to low resets the FPGA */ MCF_GPIO_PODR_FEC1L &= ~FPGA_CONFIG; /* FPGA config => low */ + wait(10); /* give it some time to do its reset stuff */ while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS) && (MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); - MCF_GPIO_PODR_FEC1L |= FPGA_CONFIG; /* pull FPGA_CONFIG high */ + + MCF_GPIO_PODR_FEC1L |= FPGA_CONFIG; /* pull FPGA_CONFIG high to start config cycle */ while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS)); /* wait until status becomes high */ /*