started simulator for DDR RAM

vhdl/testbenches/ddr_ctlr_tb.vhd

@@ -7,9 +7,11 @@ use ieee.numeric_std.all;
 
 use std.textio.all;
 
+
 entity ddr_ctlr_tb is
 end ddr_ctlr_tb;
 
+
 architecture beh of ddr_ctlr_tb is
 	signal clock			: std_logic := '0';	-- main clock
 	signal ddr_clk 		: std_logic := '0';	-- ddr clock
@@ -99,6 +101,24 @@ architecture beh of ddr_ctlr_tb is
 			DATA_EN_L       : out std_logic
 		);
 	end component;
+	
+	component ddr_ram_model
+	port (
+		signal CK		: in std_logic;
+		signal CKE		: in std_logic;
+		signal CSn		: in std_logic;
+		signal RASn		: in std_logic;
+		signal CASn		: in std_logic;
+		signal WEn		: in std_logic;
+		signal LDM		: in std_logic;
+		signal UDM		: in std_logic;
+		signal BA		: in std_logic_vector(1 downto 0);
+		signal A			: in std_logic_vector(12 downto 0);
+		signal DQ		: inout std_logic_vector(7 downto 0);
+		signal LDQS		: inout std_logic;
+		signal UDQS		: inout std_logic
+	);
+	end component;
 begin
 	t : DDR_CTRL_V1
 	port map
@@ -144,6 +164,24 @@ begin
 		DATA_EN_L => DATA_EN_L
 	);
 	
+	d : ddr_ram_model
+	port map
+	(
+		CK		=> DDRCLK0,
+		CKE	=> VCKE,
+		CSn	=> VCSn,
+		RASn	=> VRASn,
+		CASn	=> VCASn,
+		WEn	=> VWEn,
+		LDM	=> DATA_EN_L,
+		UDM	=> DATA_EN_H,
+		BA		=> BA,
+		A		=> VA,
+		DQ		=> SR_VDMP,
+		LDQS	=> DATA_EN_L,
+		UDQS	=> DATA_EN_H
+	);
+	
 	stimulate_main_clock : process
 	begin
 		wait for 4.31 ns;
@@ -194,3 +232,4 @@ begin
 		end case;
 	end process;
 end beh;
+

vhdl/testbenches/ddr_ram_model.vhd

@@ -0,0 +1,47 @@
+library work;
+use work.firebee_pkg.all;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use std.textio.all;
+
+-- DDR ram simulation for Firebee video RAM
+
+entity ddr_ram_model is
+	port (
+		signal CK		: in std_logic;
+		signal CKE		: in std_logic;
+		signal CSn		: in std_logic;
+		signal RASn		: in std_logic;
+		signal CASn		: in std_logic;
+		signal WEn		: in std_logic;
+		signal LDM		: in std_logic;
+		signal UDM		: in std_logic;
+		signal BA		: in std_logic_vector(1 downto 0);
+		signal A			: in std_logic_vector(12 downto 0);
+		signal DQ		: inout std_logic_vector(7 downto 0);
+		signal LDQS		: inout std_logic;
+		signal UDQS		: inout std_logic
+	);
+end entity ddr_ram_model;
+
+architecture behav of ddr_ram_model is
+	signal opcode 		: std_logic_vector(14 downto 0);
+	signal command 	: std_logic_vector(5 downto 0);
+	signal OLD_CKE		: std_logic := 'X';
+begin
+	opcode <= BA & A(10) & A(12 downto 11) & A(9 downto 0);
+	command <= OLD_CKE & CKE & CSn & RASn & CASn & WEn;
+	clock_hi : process
+	begin
+		wait until rising_edge(CK) and CK = '1';
+		
+	end process;
+	
+	clock_lo : process
+	begin
+		wait until falling_edge(CK) and CK = '0';
+	end process;
+end behav;