From dd3a3e9da4c724be35506c11aeea98b1d2f90d05 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Mon, 16 Jun 2014 14:35:54 +0000 Subject: [PATCH] started simulator for DDR RAM --- vhdl/backend/Altera/Firebee/firebee.qsf | 4 ++- vhdl/testbenches/ddr_ctlr_tb.vhd | 39 ++++++++++++++++++++ vhdl/testbenches/ddr_ram_model.vhd | 47 +++++++++++++++++++++++++ 3 files changed, 89 insertions(+), 1 deletion(-) create mode 100644 vhdl/testbenches/ddr_ram_model.vhd diff --git a/vhdl/backend/Altera/Firebee/firebee.qsf b/vhdl/backend/Altera/Firebee/firebee.qsf index ac512f1..17c9a48 100755 --- a/vhdl/backend/Altera/Firebee/firebee.qsf +++ b/vhdl/backend/Altera/Firebee/firebee.qsf @@ -41,7 +41,7 @@ set_global_assignment -name DEVICE EP3C40F484C6 set_global_assignment -name TOP_LEVEL_ENTITY firebee set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:04:08 MAY 31, 2014" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 @@ -670,5 +670,7 @@ set_global_assignment -name SOURCE_FILE ../../../rtl/vhdl/Firebee_V1/altpll1.cmp set_global_assignment -name VHDL_FILE ../../../rtl/vhdl/Firebee_V1/Firebee_V1_pkg.vhd set_global_assignment -name QIP_FILE ../../../rtl/vhdl/Firebee_V1/altpll_reconfig1.qip set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ns" +set_global_assignment -name VHDL_FILE ../../../testbenches/ddr_ram_model.vhd set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ctlr_tb.vhd -section_id ddr_ctlr_tb +set_global_assignment -name EDA_TEST_BENCH_FILE ../../../testbenches/ddr_ram_model.vhd -section_id ddr_ctlr_tb set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/vhdl/testbenches/ddr_ctlr_tb.vhd b/vhdl/testbenches/ddr_ctlr_tb.vhd index 1591d94..42b73f9 100644 --- a/vhdl/testbenches/ddr_ctlr_tb.vhd +++ b/vhdl/testbenches/ddr_ctlr_tb.vhd @@ -7,9 +7,11 @@ use ieee.numeric_std.all; use std.textio.all; + entity ddr_ctlr_tb is end ddr_ctlr_tb; + architecture beh of ddr_ctlr_tb is signal clock : std_logic := '0'; -- main clock signal ddr_clk : std_logic := '0'; -- ddr clock @@ -99,6 +101,24 @@ architecture beh of ddr_ctlr_tb is DATA_EN_L : out std_logic ); end component; + + component ddr_ram_model + port ( + signal CK : in std_logic; + signal CKE : in std_logic; + signal CSn : in std_logic; + signal RASn : in std_logic; + signal CASn : in std_logic; + signal WEn : in std_logic; + signal LDM : in std_logic; + signal UDM : in std_logic; + signal BA : in std_logic_vector(1 downto 0); + signal A : in std_logic_vector(12 downto 0); + signal DQ : inout std_logic_vector(7 downto 0); + signal LDQS : inout std_logic; + signal UDQS : inout std_logic + ); + end component; begin t : DDR_CTRL_V1 port map @@ -144,6 +164,24 @@ begin DATA_EN_L => DATA_EN_L ); + d : ddr_ram_model + port map + ( + CK => DDRCLK0, + CKE => VCKE, + CSn => VCSn, + RASn => VRASn, + CASn => VCASn, + WEn => VWEn, + LDM => DATA_EN_L, + UDM => DATA_EN_H, + BA => BA, + A => VA, + DQ => SR_VDMP, + LDQS => DATA_EN_L, + UDQS => DATA_EN_H + ); + stimulate_main_clock : process begin wait for 4.31 ns; @@ -194,3 +232,4 @@ begin end case; end process; end beh; + diff --git a/vhdl/testbenches/ddr_ram_model.vhd b/vhdl/testbenches/ddr_ram_model.vhd new file mode 100644 index 0000000..884689d --- /dev/null +++ b/vhdl/testbenches/ddr_ram_model.vhd @@ -0,0 +1,47 @@ +library work; +use work.firebee_pkg.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use std.textio.all; + +-- DDR ram simulation for Firebee video RAM + +entity ddr_ram_model is + port ( + signal CK : in std_logic; + signal CKE : in std_logic; + signal CSn : in std_logic; + signal RASn : in std_logic; + signal CASn : in std_logic; + signal WEn : in std_logic; + signal LDM : in std_logic; + signal UDM : in std_logic; + signal BA : in std_logic_vector(1 downto 0); + signal A : in std_logic_vector(12 downto 0); + signal DQ : inout std_logic_vector(7 downto 0); + signal LDQS : inout std_logic; + signal UDQS : inout std_logic + ); +end entity ddr_ram_model; + +architecture behav of ddr_ram_model is + signal opcode : std_logic_vector(14 downto 0); + signal command : std_logic_vector(5 downto 0); + signal OLD_CKE : std_logic := 'X'; +begin + opcode <= BA & A(10) & A(12 downto 11) & A(9 downto 0); + command <= OLD_CKE & CKE & CSn & RASn & CASn & WEn; + clock_hi : process + begin + wait until rising_edge(CK) and CK = '1'; + + end process; + + clock_lo : process + begin + wait until falling_edge(CK) and CK = '0'; + end process; +end behav;