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fixed comments

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This commit is contained in:
Markus Fröschle
2013-11-15 07:55:23 +00:00
parent b7d60e168c
commit ccf7724956
2 changed files with 9 additions and 4 deletions
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4
BaS_gcc/sources/mmu.S
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@@ -212,8 +212,8 @@ _mmu_init:
move.l #0x80000000|nocache_precise_mmudr|MCF_MMU_MMUDR_LK,d1
move.l d0,MCF_MMU_MMUTR
move.l d1,MCF_MMU_MMUDR
move.l d2,MCF_MMU_MMUOR // mapped to ffffxxx, precise,
move.l d3,MCF_MMU_MMUOR // mapped to ffffxxx, precise,
move.l d2,MCF_MMU_MMUOR
move.l d3,MCF_MMU_MMUOR
// maps (locked) the last MB (this is where BaS .data and .bss resides) of physical SDRAM to the same physical address
move.l #(SDRAM_START + SDRAM_SIZE - 0x100000) | std_mmutr, d0

7
BaS_gcc/sources/pci.c
View File

@@ -749,6 +749,7 @@ void init_pci(void)
| MCF_PCIARB_PACR_INTMINTEN /* enable "internal master broken" interrupt */
| MCF_PCIARB_PACR_EXTMINTEN(0x1F); /* enable "external master broken" interrupt */
#ifdef _NOT_USED_ /* since this is already done in sysinit.c */
#if MACHINE_FIREBEE
//MCF_PAD_PAR_PCIBG = 0x3f; // FIXME: MiNT initialization hangs if this is enabled ???
//MCF_PAD_PAR_PCIBR = 0x3f;
@@ -756,6 +757,7 @@ void init_pci(void)
MCF_PAD_PAR_PCIBG = 0x3ff; /* enable all PCI bus grant and bus requests on the LITE board */
MCF_PAD_PAR_PCIBR = 0x3ff;
#endif /* MACHINE_FIREBEE */
#endif /* _NOT_USED_ */
MCF_PCI_PCISCR = MCF_PCI_PCISCR_M | /* memory access control enabled */
MCF_PCI_PCISCR_B | /* bus master enabled */
@@ -796,7 +798,10 @@ void init_pci(void)
MCF_PCI_PCIIWCR_WINCTRL0_E |
MCF_PCI_PCIIWCR_WINCTRL1_E;
/* initialize target control register */
/*
* Initialize target control register.
* Used when an external bus master accesses the Coldfire PCI as target
*/
MCF_PCI_PCIBAR0 = 0x40000000; /* 256 kB window */
MCF_PCI_PCITBATR0 = (uint32_t) &_MBAR[0] | MCF_PCI_PCITBATR0_EN; /* target base address translation register 0 */
MCF_PCI_PCIBAR1 = 0; /* 1GB window */